Opened 8 years ago

Closed 7 years ago

#1014 closed task (wontfix)

Set our current Architectures

Reported by: William Harrington Owned by: clfs-commits@…
Priority: trivial Milestone:
Component: BOOK Version: CLFS Standard GIT
Keywords: Cc: berzerkula@…, jonathan@…, chris@…

Description

We need to decided which architectures to support.

Right now we have:

x86, x86_64 (AMD64), SPARC, SPARC64, MIPS, MIPSN32, MIPS64, PPC, PPC64.

SPARC, MIPS, and PPC are all fine with RISC, but ARM has become a point of attention and SPARC, MIPS, and PPC has become uncommon and hard to get as of now.

I suggest we drop some architectures and concentrate on x86/x86_64 (AMD64), and AND, possibly mips.

Change History (3)

comment:1 Changed 8 years ago by Oleksii

Hello there! Let me suggest that we need keep mips for sure. Me personally use 2 device with such arch:

system type		: Sigma Designs TangoX
processor		: 0
cpu model		: MIPS 4KEc V6.9
BogoMIPS		: 299.82
wait instruction	: yes
microsecond timers	: yes
tlb_entries		: 32
extra interrupt vector	: yes
hardware watchpoint	: yes, count: 4, address/irw mask: [0x0fff, 0x0fff, 0x0fff, 0x0fff]
isa			: mips1 mips2 mips32r1 mips32r2
ASEs implemented	: mips16
shadow register sets	: 1
kscratch registers	: 0
core			: 0
VCED exceptions		: not available
VCEI exceptions		: not available
SMP8XXX Chip ID		: 8634
SMP8XXX Rev ID		: 86
System bus frequency	: 200250000 Hz
CPU frequency		: 300375000 Hz
DSP frequency		: 300375000 Hz

And second:

system type		: BCM7425B2 STB platform
machine			: Unknown
processor		: 0
cpu model		: Broadcom BMIPS5000 V1.1  FPU V0.1
BogoMIPS		: 864.25
cpu MHz			: 1305.080
wait instruction	: yes
microsecond timers	: yes
tlb_entries		: 64
extra interrupt vector	: yes
hardware watchpoint	: no
isa			: mips1 mips2 mips32r1
ASEs implemented	:
shadow register sets	: 1
kscratch registers	: 0
core			: 0
VCED exceptions		: not available
VCEI exceptions		: not available

processor		: 1
cpu model		: Broadcom BMIPS5000 V1.1  FPU V0.1
BogoMIPS		: 655.36
cpu MHz			: 1305.080
wait instruction	: yes
microsecond timers	: yes
tlb_entries		: 64
extra interrupt vector	: yes
hardware watchpoint	: no
isa			: mips1 mips2 mips32r1
ASEs implemented	:
shadow register sets	: 1
kscratch registers	: 0
core			: 0
VCED exceptions		: not available
VCEI exceptions		: not available

So, it is power devices with HD-video support and few team for software development. If possible, please keep books for MIPS just in "Embedded Development". Thank You!

comment:2 Changed 7 years ago by William Harrington

Milestone: CLFS Standard 3.1.0

comment:3 Changed 7 years ago by William Harrington

Resolution: wontfix
Status: newclosed

Going to keep current archs and add ARM someday.

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