Changeset a60e4c5 for patches/gcc-4.2.2-branch_update-2.patch
- Timestamp:
- Dec 19, 2007, 9:35:11 PM (17 years ago)
- Branches:
- clfs-1.2, clfs-2.1, clfs-3.0.0-systemd, clfs-3.0.0-sysvinit, master, systemd, sysvinit
- Children:
- a4357b0
- Parents:
- a2498b26
- File:
-
- 1 moved
-
patches/gcc-4.2.2-branch_update-2.patch (moved) (moved from patches/gcc-4.2.2-branch_update-1.patch ) (73 diffs)
Legend:
- Unmodified
- Added
- Removed
-
patches/gcc-4.2.2-branch_update-2.patch
ra2498b26 ra60e4c5 1 1 Submitted By: Jim Gifford (jim at linuxfromscratch dot org) 2 Date: 1 0-25-20072 Date: 12-21-2007 3 3 Initial Package Version: 4.2.2 4 4 Origin: Upstream … … 8 8 9 9 diff -Naur gcc-4.2.2.orig/boehm-gc/include/private/gc_priv.h gcc-4.2.2/boehm-gc/include/private/gc_priv.h 10 --- gcc-4.2.2.orig/boehm-gc/include/private/gc_priv.h 2007-05-19 0 5:18:32.000000000 -070011 +++ gcc-4.2.2/boehm-gc/include/private/gc_priv.h 2007-10-09 1 2:42:40.000000000 -070010 --- gcc-4.2.2.orig/boehm-gc/include/private/gc_priv.h 2007-05-19 08:18:32.000000000 -0400 11 +++ gcc-4.2.2/boehm-gc/include/private/gc_priv.h 2007-10-09 15:42:40.000000000 -0400 12 12 @@ -286,53 +286,6 @@ 13 13 #endif … … 65 65 /* OS interface routines */ 66 66 diff -Naur gcc-4.2.2.orig/boehm-gc/pthread_support.c gcc-4.2.2/boehm-gc/pthread_support.c 67 --- gcc-4.2.2.orig/boehm-gc/pthread_support.c 2007-07-02 07:59:47.000000000 -070068 +++ gcc-4.2.2/boehm-gc/pthread_support.c 2007-10-13 08:01:29.000000000 -070067 --- gcc-4.2.2.orig/boehm-gc/pthread_support.c 2007-07-02 10:59:47.000000000 -0400 68 +++ gcc-4.2.2/boehm-gc/pthread_support.c 2007-10-13 11:01:29.000000000 -0400 69 69 @@ -1153,7 +1153,7 @@ 70 70 # ifdef STACK_GROWS_DOWN … … 76 76 77 77 # else 78 diff -Naur gcc-4.2.2.orig/gcc/c-common.c gcc-4.2.2/gcc/c-common.c79 --- gcc-4.2.2.orig/gcc/c-common.c 2007-09-01 08:28:30.000000000 -070080 +++ gcc-4.2.2/gcc/c-common.c 2007-10-10 13:46:11.000000000 -070081 @@ -6229,6 +6229,16 @@82 else83 type = c_build_qualified_type (main_type, quals);84 85 + if (COMPLETE_TYPE_P (type)86 + && TREE_CODE (TYPE_SIZE_UNIT (type)) == INTEGER_CST87 + && TREE_OVERFLOW (TYPE_SIZE_UNIT (type)))88 + {89 + error ("size of array is too large");90 + /* If we proceed with the array type as it is, we'll eventually91 + crash in tree_low_cst(). */92 + type = error_mark_node;93 + }94 +95 *ptype = type;96 return failure;97 }98 78 diff -Naur gcc-4.2.2.orig/gcc/ChangeLog gcc-4.2.2/gcc/ChangeLog 99 --- gcc-4.2.2.orig/gcc/ChangeLog 2007-10-07 14:20:02.000000000 -0700 100 +++ gcc-4.2.2/gcc/ChangeLog 2007-10-24 10:54:40.000000000 -0700 101 @@ -1,3 +1,162 @@ 79 --- gcc-4.2.2.orig/gcc/ChangeLog 2007-10-07 17:20:02.000000000 -0400 80 +++ gcc-4.2.2/gcc/ChangeLog 2007-12-19 05:04:28.000000000 -0500 81 @@ -1,3 +1,315 @@ 82 +2007-12-19 Kaz Kylheku <kaz@zeugmasystems.com> 83 + 84 + PR rtl-optimization/34456 85 + * resource.c (mark_set_resources): Use regs_invalidated_by_call 86 + rather than call_used_regs and global_regs. 87 + 88 +2007-12-17 Jakub Jelinek <jakub@redhat.com> 89 + 90 + PR bootstrap/34003 91 + * c-decl.c (merge_decls): Copy RTL from olddecl to newdecl. 92 + * config/pa/pa.c (pa_encode_section_info): If !first, preserve 93 + SYMBOL_FLAG_REFERENCED flag. 94 + 95 +2007-12-13 Torbjorn Granlund <tege@swox.com> 96 + 97 + * config/i386/i386.c (ix86_rtx_costs) [MULT]: Check op0 for 98 + ZERO_EXTEND when computing costs for widening multiplication. 99 + 100 +2007-12-09 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 101 + 102 + PR middle-end/32889 103 + PR target/34091 104 + * pa.md: Consolidate HImode and QImode move patterns into one pattern 105 + each, eliminating floating-point alternatives. 106 + * pa-protos.h (pa_cannot_change_mode_class, pa_modes_tieable_p): 107 + Declare functions. 108 + * pa-64.h (SECONDARY_MEMORY_NEEDED): Define here. 109 + * pa.c (pa_secondary_reload): Use an intermediate general register 110 + for copies to/from floating-point register classes. Simplify code 111 + SHIFT_REGS class. Provide additional comments. 112 + (pa_cannot_change_mode_class, pa_modes_tieable_p): New functions. 113 + * pa.h (MODES_TIEABLE_P): Use pa_modes_tieable_p. 114 + (SECONDARY_MEMORY_NEEDED): Delete define. 115 + (INT14_OK_STRICT): Define. 116 + (MODE_OK_FOR_SCALED_INDEXING_P): Allow SFmode and DFmode when using 117 + soft float. 118 + (MODE_OK_FOR_UNSCALED_INDEXING_P): Likewise. 119 + (GO_IF_LEGITIMATE_ADDRESS): Use INT14_OK_STRICT in REG+D case for 120 + SFmode and DFmode. 121 + (LEGITIMIZE_RELOAD_ADDRESS): Use INT14_OK_STRICT in mask selection. 122 + Align DImode offsets when generating 64-bit code. 123 + * pa32-regs.h (VALID_FP_MODE_P): Remove QImode and HImode. 124 + (CANNOT_CHANGE_MODE_CLASS): Define. 125 + * pa64-regs.h (VALID_FP_MODE_P): Remove QImode and HImode. 126 + (CANNOT_CHANGE_MODE_CLASS): Define using pa_cannot_change_mode_class. 127 + 128 +2007-11-28 Rask Ingemann Lambertsen <rask@sygehus.dk> 129 + 130 + Backport from mainline: 131 + 2007-11-26 Rask Ingemann Lambertsen <rask@sygehus.dk> 132 + 133 + PR target/34174 134 + * config/fr30/fr30.c (fr30_move_double): Sanitize mem->reg case. Copy 135 + the address before it is clobbered. 136 + 137 +2007-11-26 Uros Bizjak <ubizjak@gmail.com> 138 + 139 + PR target/34215 140 + * config/i386/i386.md (truncdfsf2): Select SLOT_TEMP stack slot if 141 + virtual registers are instantiated. 142 + (truncxfsf2): Ditto. 143 + (truncxfdf2): Ditto. 144 + 145 +2007-11-22 Matthias Klose <doko@ubuntu.com> 146 + 147 + Backport from mainline: 148 + 2007-11-17 Richard Guenther <rguenther@suse.de> 149 + 150 + PR middle-end/34130 151 + * fold-const.c (extract_muldiv_1): Do not move negative 152 + constants inside ABS_EXPR. 153 + 154 +2007-11-22 Richard Sandiford <rsandifo@nildram.co.uk> 155 + 156 + PR rtl-optimization/33848 157 + * reload.c (subst_reloads): When replacing a LABEL_REF with a 158 + register, only add a REG_LABEL note if the label is the target 159 + of the jump. 160 + 161 +2007-11-16 Richard Guenther <rguenther@suse.de> 162 + 163 + PR middle-end/34030 164 + * fold-const.c (fold_binary): Use correct types for folding 165 + 1 << X & Y to Y >> X & 1. 166 + 167 +2007-11-08 Uros Bizjak <ubizjak@gmail.com> 168 + 169 + PR target/32787 170 + Backport from mainline: 171 + 172 + 2007-11-06 Rask Ingemann Lambertsen <rask@sygehus.dk> 173 + 174 + * config/i386/driver-i386.c: Test for __GNUC__ instead of 175 + GCC_VERSION which is always defined. 176 + 177 +2007-11-07 Eric Botcazou <ebotcazou@libertysurf.fr> 178 + 179 + PR rtl-optimization/33822 180 + * rtl.h (REG_OFFSET): Fix comment. 181 + * var-tracking.c (INT_MEM_OFFSET): New macro. 182 + (var_mem_set): Use it. 183 + (var_mem_delete_and_set): Likewise. 184 + (var_mem_delete): Likewise. 185 + (same_variable_part_p): Likewise. 186 + (vt_get_decl_and_offset): Likewise. 187 + (offset_valid_for_tracked_p): New predicate. 188 + (count_uses): Do not track locations with invalid offsets. 189 + (add_uses): Likewise. 190 + (add_stores): Likewise. 191 + 192 +2007-11-02 Bob Wilson <bob.wilson@acm.org> 193 + 194 + * config/xtensa/xtensa.c (xtensa_expand_prologue): Put a 195 + REG_FRAME_RELATED_EXPR note on the last insn that sets up the stack 196 + pointer or frame pointer. 197 + * config/xtensa/xtensa.h (DWARF_UNWIND_INFO): Delete. 198 + (MUST_USE_SJLJ_EXCEPTIONS): Define. 199 + (DWARF2_UNWIND_INFO): Define. 200 + (INCOMING_RETURN_ADDR_RTX): Define. 201 + (DWARF_FRAME_RETURN_COLUMN): Define. 202 + 203 +2007-10-31 Richard Guenther <rguenther@suse.de> 204 + 205 + * Makefile.in (targhooks.o): Add $(OPTABS_H) dependency. 206 + 207 +2007-10-29 Ian Lance Taylor <iant@google.com> 208 + 209 + * ifcvt.c (noce_can_store_speculate_p): New static function. 210 + (noce_process_if_block): Call it. 211 + (find_if_header): Only call find_if_case_1 and find_if_case_2 if 212 + life_data_ok is set. 213 + (if_convert): Always compute postdominators. 214 + 215 +2007-10-29 Janis Johnson <janis187@us.ibm.com> 216 + 217 + * doc/invoke.texi (Option Summary, optimizations): Remove 218 + -fbounds-check. Show that the value for options -falign-jumps, 219 + -falign-labels, -falign-loops, -falign-functions, 220 + -fsched-stalled-insns, and -fsched-stalled-insns-dep is optional. 221 + Break up a long line. Add -ftree-vrp and -funit-at-a-time. 222 + (Option Summary, code gen options) Add -fno-stack-limit. Add 223 + missing @gol to the end of a line. 224 + * doc/invoke.texi (Option Summary, optimizations): 225 + (Optimization Options): Remove -fbounds-check, which is also 226 + documented under Code Generation Options. In the descriptions for 227 + -fsched-stalled-insns and -fsched-stalled-insns-dep, show the 228 + options with and without values. Change -fno-cprop-registers 229 + to -fcprop-registers to match other options, and say when it is 230 + enabled rather than disabled. Remove extra index entry for 231 + -fno-cx-limited-range. Add opindex for several optimization 232 + options, and fix typos in the opindex commands for several others. 233 + (Code Gen Options): Add index entry for -ftls-model. 234 + 102 235 +2007-10-24 Richard Sandiford <rsandifo@nildram.co.uk> 103 236 + … … 262 395 263 396 * GCC 4.2.2 released. 397 diff -Naur gcc-4.2.2.orig/gcc/Makefile.in gcc-4.2.2/gcc/Makefile.in 398 --- gcc-4.2.2.orig/gcc/Makefile.in 2007-09-01 11:28:30.000000000 -0400 399 +++ gcc-4.2.2/gcc/Makefile.in 2007-10-31 12:32:06.000000000 -0400 400 @@ -2141,7 +2141,8 @@ 401 coretypes.h intl.h 402 targhooks.o : targhooks.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TREE_H) \ 403 $(EXPR_H) $(TM_H) $(RTL_H) $(TM_P_H) $(FUNCTION_H) output.h toplev.h \ 404 - $(MACHMODE_H) $(TARGET_DEF_H) $(TARGET_H) $(GGC_H) gt-targhooks.h 405 + $(MACHMODE_H) $(TARGET_DEF_H) $(TARGET_H) $(GGC_H) gt-targhooks.h \ 406 + $(OPTABS_H) 407 408 toplev.o : toplev.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(TREE_H) \ 409 version.h $(RTL_H) $(FUNCTION_H) $(FLAGS_H) xcoffout.h input.h \ 410 diff -Naur gcc-4.2.2.orig/gcc/ada/ChangeLog gcc-4.2.2/gcc/ada/ChangeLog 411 --- gcc-4.2.2.orig/gcc/ada/ChangeLog 2007-10-07 17:19:54.000000000 -0400 412 +++ gcc-4.2.2/gcc/ada/ChangeLog 2007-12-01 07:03:42.000000000 -0500 413 @@ -1,3 +1,9 @@ 414 +2007-12-01 Kostik Belousov <kostikbel@ukr.net> 415 + 416 + PR ada/33722 417 + * env.c (__gnat_setenv): FreeBSD 7 has a POSIX conformant putenv() 418 + and its argument must not be free()ed. 419 + 420 2007-10-07 Release Manager 421 422 * GCC 4.2.2 released. 423 diff -Naur gcc-4.2.2.orig/gcc/ada/env.c gcc-4.2.2/gcc/ada/env.c 424 --- gcc-4.2.2.orig/gcc/ada/env.c 2007-08-22 13:54:43.000000000 -0400 425 +++ gcc-4.2.2/gcc/ada/env.c 2007-12-01 07:03:42.000000000 -0500 426 @@ -177,9 +177,9 @@ 427 428 sprintf (expression, "%s=%s", name, value); 429 putenv (expression); 430 -#if defined (__FreeBSD__) || defined (__APPLE__) || defined (__MINGW32__) \ 431 - ||(defined (__vxworks) && ! defined (__RTP__)) 432 - /* On some systems like FreeBSD, MacOS X and Windows, putenv is making 433 +#if (defined (__FreeBSD__) && (__FreeBSD__ < 7)) || defined (__APPLE__) \ 434 + || defined (__MINGW32__) ||(defined (__vxworks) && ! defined (__RTP__)) 435 + /* On some systems like pre-7 FreeBSD, MacOS X and Windows, putenv is making 436 a copy of the expression string so we can free it after the call to 437 putenv */ 438 free (expression); 439 diff -Naur gcc-4.2.2.orig/gcc/c-common.c gcc-4.2.2/gcc/c-common.c 440 --- gcc-4.2.2.orig/gcc/c-common.c 2007-09-01 11:28:30.000000000 -0400 441 +++ gcc-4.2.2/gcc/c-common.c 2007-10-10 16:46:11.000000000 -0400 442 @@ -6229,6 +6229,16 @@ 443 else 444 type = c_build_qualified_type (main_type, quals); 445 446 + if (COMPLETE_TYPE_P (type) 447 + && TREE_CODE (TYPE_SIZE_UNIT (type)) == INTEGER_CST 448 + && TREE_OVERFLOW (TYPE_SIZE_UNIT (type))) 449 + { 450 + error ("size of array is too large"); 451 + /* If we proceed with the array type as it is, we'll eventually 452 + crash in tree_low_cst(). */ 453 + type = error_mark_node; 454 + } 455 + 456 *ptype = type; 457 return failure; 458 } 459 diff -Naur gcc-4.2.2.orig/gcc/c-decl.c gcc-4.2.2/gcc/c-decl.c 460 --- gcc-4.2.2.orig/gcc/c-decl.c 2007-09-01 11:28:30.000000000 -0400 461 +++ gcc-4.2.2/gcc/c-decl.c 2007-12-18 00:05:43.000000000 -0500 462 @@ -1660,6 +1660,9 @@ 463 } 464 } 465 466 + /* Keep the old rtl since we can safely use it. */ 467 + if (HAS_RTL_P (olddecl)) 468 + COPY_DECL_RTL (olddecl, newdecl); 469 470 /* Merge the type qualifiers. */ 471 if (TREE_READONLY (newdecl)) 472 diff -Naur gcc-4.2.2.orig/gcc/c-typeck.c gcc-4.2.2/gcc/c-typeck.c 473 --- gcc-4.2.2.orig/gcc/c-typeck.c 2007-09-01 11:28:30.000000000 -0400 474 +++ gcc-4.2.2/gcc/c-typeck.c 2007-10-10 14:24:29.000000000 -0400 475 @@ -1682,14 +1682,19 @@ 476 if (TREE_NO_WARNING (orig_exp)) 477 TREE_NO_WARNING (exp) = 1; 478 479 - if (INTEGRAL_TYPE_P (type)) 480 - return perform_integral_promotions (exp); 481 - 482 if (code == VOID_TYPE) 483 { 484 error ("void value not ignored as it ought to be"); 485 return error_mark_node; 486 } 487 + 488 + exp = require_complete_type (exp); 489 + if (exp == error_mark_node) 490 + return error_mark_node; 491 + 492 + if (INTEGRAL_TYPE_P (type)) 493 + return perform_integral_promotions (exp); 494 + 495 return exp; 496 } 497 498 499 @@ -2801,11 +2806,15 @@ 500 /* No default_conversion here. It causes trouble for ADDR_EXPR. */ 501 tree arg = xarg; 502 tree argtype = 0; 503 - enum tree_code typecode = TREE_CODE (TREE_TYPE (arg)); 504 + enum tree_code typecode; 505 tree val; 506 int noconvert = flag; 507 const char *invalid_op_diag; 508 509 + if (code != ADDR_EXPR) 510 + arg = require_complete_type (arg); 511 + 512 + typecode = TREE_CODE (TREE_TYPE (arg)); 513 if (typecode == ERROR_MARK) 514 return error_mark_node; 515 if (typecode == ENUMERAL_TYPE || typecode == BOOLEAN_TYPE) 516 @@ -3490,6 +3499,13 @@ 517 return error_mark_node; 518 } 519 520 + if (!VOID_TYPE_P (type)) 521 + { 522 + value = require_complete_type (value); 523 + if (value == error_mark_node) 524 + return error_mark_node; 525 + } 526 + 527 if (type == TYPE_MAIN_VARIANT (TREE_TYPE (value))) 528 { 529 if (pedantic) 530 @@ -3900,6 +3916,9 @@ 531 error ("void value not ignored as it ought to be"); 532 return error_mark_node; 533 } 534 + rhs = require_complete_type (rhs); 535 + if (rhs == error_mark_node) 536 + return error_mark_node; 537 /* A type converts to a reference to it. 538 This code doesn't fully support references, it's just for the 539 special case of va_start and va_copy. */ 540 diff -Naur gcc-4.2.2.orig/gcc/config/fr30/fr30.c gcc-4.2.2/gcc/config/fr30/fr30.c 541 --- gcc-4.2.2.orig/gcc/config/fr30/fr30.c 2007-09-01 11:28:30.000000000 -0400 542 +++ gcc-4.2.2/gcc/config/fr30/fr30.c 2007-11-27 20:44:10.000000000 -0500 543 @@ -827,47 +827,23 @@ 544 { 545 rtx addr = XEXP (src, 0); 546 int dregno = REGNO (dest); 547 - rtx dest0; 548 - rtx dest1; 549 + rtx dest0 = operand_subword (dest, 0, TRUE, mode);; 550 + rtx dest1 = operand_subword (dest, 1, TRUE, mode);; 551 rtx new_mem; 552 553 - /* If the high-address word is used in the address, we 554 - must load it last. Otherwise, load it first. */ 555 - int reverse = (refers_to_regno_p (dregno, dregno + 1, addr, 0) != 0); 556 - 557 gcc_assert (GET_CODE (addr) == REG); 558 559 - dest0 = operand_subword (dest, reverse, TRUE, mode); 560 - dest1 = operand_subword (dest, !reverse, TRUE, mode); 561 - 562 - if (reverse) 563 - { 564 - emit_insn (gen_rtx_SET (VOIDmode, dest1, 565 - adjust_address (src, SImode, 0))); 566 - emit_insn (gen_rtx_SET (SImode, dest0, 567 - gen_rtx_REG (SImode, REGNO (addr)))); 568 - emit_insn (gen_rtx_SET (SImode, dest0, 569 - plus_constant (dest0, UNITS_PER_WORD))); 570 - 571 - new_mem = gen_rtx_MEM (SImode, dest0); 572 - MEM_COPY_ATTRIBUTES (new_mem, src); 573 - 574 - emit_insn (gen_rtx_SET (VOIDmode, dest0, new_mem)); 575 - } 576 - else 577 - { 578 - emit_insn (gen_rtx_SET (VOIDmode, dest0, 579 - adjust_address (src, SImode, 0))); 580 - emit_insn (gen_rtx_SET (SImode, dest1, 581 - gen_rtx_REG (SImode, REGNO (addr)))); 582 - emit_insn (gen_rtx_SET (SImode, dest1, 583 - plus_constant (dest1, UNITS_PER_WORD))); 584 + /* Copy the address before clobbering it. See PR 34174. */ 585 + emit_insn (gen_rtx_SET (SImode, dest1, addr)); 586 + emit_insn (gen_rtx_SET (VOIDmode, dest0, 587 + adjust_address (src, SImode, 0))); 588 + emit_insn (gen_rtx_SET (SImode, dest1, 589 + plus_constant (dest1, UNITS_PER_WORD))); 590 591 - new_mem = gen_rtx_MEM (SImode, dest1); 592 - MEM_COPY_ATTRIBUTES (new_mem, src); 593 + new_mem = gen_rtx_MEM (SImode, dest1); 594 + MEM_COPY_ATTRIBUTES (new_mem, src); 595 596 - emit_insn (gen_rtx_SET (VOIDmode, dest1, new_mem)); 597 - } 598 + emit_insn (gen_rtx_SET (VOIDmode, dest1, new_mem)); 599 } 600 else if (src_code == CONST_INT || src_code == CONST_DOUBLE) 601 { 602 diff -Naur gcc-4.2.2.orig/gcc/config/i386/driver-i386.c gcc-4.2.2/gcc/config/i386/driver-i386.c 603 --- gcc-4.2.2.orig/gcc/config/i386/driver-i386.c 2007-09-01 11:28:30.000000000 -0400 604 +++ gcc-4.2.2/gcc/config/i386/driver-i386.c 2007-11-08 05:07:06.000000000 -0500 605 @@ -25,7 +25,7 @@ 606 607 const char *host_detect_local_cpu (int argc, const char **argv); 608 609 -#ifdef GCC_VERSION 610 +#ifdef __GNUC__ 611 #define cpuid(num,a,b,c,d) \ 612 asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1" \ 613 : "=a" (a), "=r" (b), "=c" (c), "=d" (d) \ 614 @@ -296,4 +296,4 @@ 615 616 return concat ("-m", argv[0], "=", cpu, NULL); 617 } 618 -#endif /* GCC_VERSION */ 619 +#endif /* __GNUC__ */ 264 620 diff -Naur gcc-4.2.2.orig/gcc/config/i386/emmintrin.h gcc-4.2.2/gcc/config/i386/emmintrin.h 265 --- gcc-4.2.2.orig/gcc/config/i386/emmintrin.h 2007-04-04 1 5:13:13.000000000 -0700266 +++ gcc-4.2.2/gcc/config/i386/emmintrin.h 2007-10-18 0 2:12:30.000000000 -0700621 --- gcc-4.2.2.orig/gcc/config/i386/emmintrin.h 2007-04-04 18:13:13.000000000 -0400 622 +++ gcc-4.2.2/gcc/config/i386/emmintrin.h 2007-10-18 05:12:30.000000000 -0400 267 623 @@ -1100,7 +1100,6 @@ 268 624 return (__m128i)__builtin_ia32_pmuludq128 ((__v4si)__A, (__v4si)__B); … … 327 683 _mm_sll_epi16 (__m128i __A, __m128i __B) 328 684 diff -Naur gcc-4.2.2.orig/gcc/config/i386/i386.c gcc-4.2.2/gcc/config/i386/i386.c 329 --- gcc-4.2.2.orig/gcc/config/i386/i386.c 2007-09-01 08:28:30.000000000 -0700330 +++ gcc-4.2.2/gcc/config/i386/i386.c 2007-1 0-18 02:12:30.000000000 -0700685 --- gcc-4.2.2.orig/gcc/config/i386/i386.c 2007-09-01 11:28:30.000000000 -0400 686 +++ gcc-4.2.2/gcc/config/i386/i386.c 2007-12-13 04:25:46.000000000 -0500 331 687 @@ -16209,80 +16209,38 @@ 332 688 emit_insn (pat); … … 432 788 433 789 target = gen_reg_rtx (tmode); 790 @@ -17232,7 +17192,7 @@ 791 nbits = 7; 792 793 /* Compute costs correctly for widening multiplication. */ 794 - if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op1) == ZERO_EXTEND) 795 + if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND) 796 && GET_MODE_SIZE (GET_MODE (XEXP (op0, 0))) * 2 797 == GET_MODE_SIZE (mode)) 798 { 434 799 diff -Naur gcc-4.2.2.orig/gcc/config/i386/i386.md gcc-4.2.2/gcc/config/i386/i386.md 435 --- gcc-4.2.2.orig/gcc/config/i386/i386.md 2007-09-01 08:28:30.000000000 -0700 436 +++ gcc-4.2.2/gcc/config/i386/i386.md 2007-10-10 03:01:53.000000000 -0700 437 @@ -15660,11 +15660,20 @@ 800 --- gcc-4.2.2.orig/gcc/config/i386/i386.md 2007-09-01 11:28:30.000000000 -0400 801 +++ gcc-4.2.2/gcc/config/i386/i386.md 2007-11-26 09:22:59.000000000 -0500 802 @@ -3715,7 +3715,8 @@ 803 ; 804 else 805 { 806 - rtx temp = assign_386_stack_local (SFmode, SLOT_VIRTUAL); 807 + int slot = virtuals_instantiated ? SLOT_TEMP : SLOT_VIRTUAL; 808 + rtx temp = assign_386_stack_local (SFmode, slot); 809 emit_insn (gen_truncdfsf2_with_temp (operands[0], operands[1], temp)); 810 DONE; 811 } 812 @@ -3867,7 +3868,10 @@ 813 DONE; 814 } 815 else 816 - operands[2] = assign_386_stack_local (SFmode, SLOT_VIRTUAL); 817 + { 818 + int slot = virtuals_instantiated ? SLOT_TEMP : SLOT_VIRTUAL; 819 + operands[2] = assign_386_stack_local (SFmode, slot); 820 + } 821 }) 822 823 (define_insn "*truncxfsf2_mixed" 824 @@ -3965,7 +3969,10 @@ 825 DONE; 826 } 827 else 828 - operands[2] = assign_386_stack_local (DFmode, SLOT_VIRTUAL); 829 + { 830 + int slot = virtuals_instantiated ? SLOT_TEMP : SLOT_VIRTUAL; 831 + operands[2] = assign_386_stack_local (DFmode, slot); 832 + } 833 }) 834 835 (define_insn "*truncxfdf2_mixed" 836 @@ -15660,11 +15667,20 @@ 438 837 { 439 838 rtx label = gen_label_rtx (); … … 459 858 emit_move_insn (operands[0], operands[1]); 460 859 DONE; 461 @@ -15745,11 +157 54,20 @@860 @@ -15745,11 +15761,20 @@ 462 861 { 463 862 rtx label = gen_label_rtx (); … … 465 864 - emit_label (label); 466 865 + rtx op2; 467 + 866 867 - emit_insn (gen_fprem1xf4 (operands[1], operands[2], 868 - operands[1], operands[2])); 468 869 + if (rtx_equal_p (operands[1], operands[2])) 469 870 + { … … 473 874 + else 474 875 + op2 = operands[2]; 475 476 - emit_insn (gen_fprem1xf4 (operands[1], operands[2], 477 - operands[1], operands[2])); 876 + 478 877 + emit_label (label); 479 878 + emit_insn (gen_fprem1xf4 (operands[1], op2, operands[1], op2)); … … 484 883 DONE; 485 884 diff -Naur gcc-4.2.2.orig/gcc/config/i386/sse.md gcc-4.2.2/gcc/config/i386/sse.md 486 --- gcc-4.2.2.orig/gcc/config/i386/sse.md 2007-09-01 08:28:30.000000000 -0700487 +++ gcc-4.2.2/gcc/config/i386/sse.md 2007-10-10 0 3:01:53.000000000 -0700885 --- gcc-4.2.2.orig/gcc/config/i386/sse.md 2007-09-01 11:28:30.000000000 -0400 886 +++ gcc-4.2.2/gcc/config/i386/sse.md 2007-10-10 06:01:53.000000000 -0400 488 887 @@ -2724,7 +2724,7 @@ 489 888 [(set (match_operand:SSEMODE24 0 "register_operand" "=x") … … 540 939 }) 541 940 diff -Naur gcc-4.2.2.orig/gcc/config/mips/mips.c gcc-4.2.2/gcc/config/mips/mips.c 542 --- gcc-4.2.2.orig/gcc/config/mips/mips.c 2007-09-06 1 1:04:51.000000000 -0700543 +++ gcc-4.2.2/gcc/config/mips/mips.c 2007-10-24 1 0:54:40.000000000 -0700941 --- gcc-4.2.2.orig/gcc/config/mips/mips.c 2007-09-06 14:04:51.000000000 -0400 942 +++ gcc-4.2.2/gcc/config/mips/mips.c 2007-10-24 13:54:40.000000000 -0400 544 943 @@ -289,7 +289,7 @@ 545 944 static bool mips_rtx_costs (rtx, int, int, int *); … … 966 1365 /* This function does three things: 967 1366 diff -Naur gcc-4.2.2.orig/gcc/config/mips/mips.md gcc-4.2.2/gcc/config/mips/mips.md 968 --- gcc-4.2.2.orig/gcc/config/mips/mips.md 2007-09-01 08:28:30.000000000 -0700969 +++ gcc-4.2.2/gcc/config/mips/mips.md 2007-10-22 1 3:09:07.000000000 -07001367 --- gcc-4.2.2.orig/gcc/config/mips/mips.md 2007-09-01 11:28:30.000000000 -0400 1368 +++ gcc-4.2.2/gcc/config/mips/mips.md 2007-10-22 16:09:07.000000000 -0400 970 1369 @@ -370,6 +370,17 @@ 971 1370 (const_string "hilo")] … … 1014 1413 1015 1414 ;; Sibling calls. All these patterns use jump instructions. 1415 diff -Naur gcc-4.2.2.orig/gcc/config/pa/pa-64.h gcc-4.2.2/gcc/config/pa/pa-64.h 1416 --- gcc-4.2.2.orig/gcc/config/pa/pa-64.h 2007-09-01 11:28:30.000000000 -0400 1417 +++ gcc-4.2.2/gcc/config/pa/pa-64.h 2007-12-09 22:17:24.000000000 -0500 1418 @@ -84,3 +84,17 @@ 1419 want aggregates padded down. */ 1420 1421 #define PAD_VARARGS_DOWN (!AGGREGATE_TYPE_P (type)) 1422 + 1423 +/* In the PA architecture, it is not possible to directly move data 1424 + between GENERAL_REGS and FP_REGS. On the 32-bit port, we use the 1425 + location at SP-16 because PA 1.X only supports 5-bit immediates for 1426 + floating-point loads and stores. We don't expose this location in 1427 + the RTL to avoid scheduling related problems. For example, the 1428 + store and load could be separated by a call to a pure or const 1429 + function which has no frame and this function might also use SP-16. 1430 + We have 14-bit immediates on the 64-bit port, so we use secondary 1431 + memory for the copies. */ 1432 +#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ 1433 + (MAYBE_FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2) \ 1434 + || MAYBE_FP_REG_CLASS_P (CLASS2) != FP_REG_CLASS_P (CLASS1)) 1435 + 1436 diff -Naur gcc-4.2.2.orig/gcc/config/pa/pa-protos.h gcc-4.2.2/gcc/config/pa/pa-protos.h 1437 --- gcc-4.2.2.orig/gcc/config/pa/pa-protos.h 2007-09-01 11:28:30.000000000 -0400 1438 +++ gcc-4.2.2/gcc/config/pa/pa-protos.h 2007-12-09 22:17:24.000000000 -0500 1439 @@ -174,6 +174,9 @@ 1440 unsigned HOST_WIDE_INT, 1441 unsigned int); 1442 extern void pa_hpux_asm_output_external (FILE *, tree, const char *); 1443 +extern bool pa_cannot_change_mode_class (enum machine_mode, enum machine_mode, 1444 + enum reg_class); 1445 +extern bool pa_modes_tieable_p (enum machine_mode, enum machine_mode); 1446 1447 extern const int magic_milli[]; 1448 extern int shadd_constant_p (int); 1449 diff -Naur gcc-4.2.2.orig/gcc/config/pa/pa.c gcc-4.2.2/gcc/config/pa/pa.c 1450 --- gcc-4.2.2.orig/gcc/config/pa/pa.c 2007-09-01 11:28:30.000000000 -0400 1451 +++ gcc-4.2.2/gcc/config/pa/pa.c 2007-12-18 00:05:43.000000000 -0500 1452 @@ -5652,12 +5652,49 @@ 1453 if (regno >= FIRST_PSEUDO_REGISTER || GET_CODE (x) == SUBREG) 1454 regno = true_regnum (x); 1455 1456 - /* Handle out of range displacement for integer mode loads/stores of 1457 - FP registers. */ 1458 - if (((regno >= FIRST_PSEUDO_REGISTER || regno == -1) 1459 - && GET_MODE_CLASS (mode) == MODE_INT 1460 - && FP_REG_CLASS_P (class)) 1461 - || (class == SHIFT_REGS && (regno <= 0 || regno >= 32))) 1462 + /* In order to allow 14-bit displacements in integer loads and stores, 1463 + we need to prevent reload from generating out of range integer mode 1464 + loads and stores to the floating point registers. Previously, we 1465 + used to call for a secondary reload and have emit_move_sequence() 1466 + fix the instruction sequence. However, reload occasionally wouldn't 1467 + generate the reload and we would end up with an invalid REG+D memory 1468 + address. So, now we use an intermediate general register for most 1469 + memory loads and stores. */ 1470 + if ((regno >= FIRST_PSEUDO_REGISTER || regno == -1) 1471 + && GET_MODE_CLASS (mode) == MODE_INT 1472 + && FP_REG_CLASS_P (class)) 1473 + { 1474 + /* Reload passes (mem:SI (reg/f:DI 30 %r30) when it wants to check 1475 + the secondary reload needed for a pseudo. It never passes a 1476 + REG+D address. */ 1477 + if (GET_CODE (x) == MEM) 1478 + { 1479 + x = XEXP (x, 0); 1480 + 1481 + /* We don't need an intermediate for indexed and LO_SUM DLT 1482 + memory addresses. When INT14_OK_STRICT is true, it might 1483 + appear that we could directly allow register indirect 1484 + memory addresses. However, this doesn't work because we 1485 + don't support SUBREGs in floating-point register copies 1486 + and reload doesn't tell us when it's going to use a SUBREG. */ 1487 + if (IS_INDEX_ADDR_P (x) 1488 + || IS_LO_SUM_DLT_ADDR_P (x)) 1489 + return NO_REGS; 1490 + 1491 + /* Otherwise, we need an intermediate general register. */ 1492 + return GENERAL_REGS; 1493 + } 1494 + 1495 + /* Request a secondary reload with a general scratch register 1496 + for everthing else. ??? Could symbolic operands be handled 1497 + directly when generating non-pic PA 2.0 code? */ 1498 + sri->icode = in_p ? reload_in_optab[mode] : reload_out_optab[mode]; 1499 + return NO_REGS; 1500 + } 1501 + 1502 + /* We need a secondary register (GPR) for copies between the SAR 1503 + and anything other than a general register. */ 1504 + if (class == SHIFT_REGS && (regno <= 0 || regno >= 32)) 1505 { 1506 sri->icode = in_p ? reload_in_optab[mode] : reload_out_optab[mode]; 1507 return NO_REGS; 1508 @@ -5666,16 +5703,15 @@ 1509 /* A SAR<->FP register copy requires a secondary register (GPR) as 1510 well as secondary memory. */ 1511 if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER 1512 - && ((REGNO_REG_CLASS (regno) == SHIFT_REGS && FP_REG_CLASS_P (class)) 1513 - || (class == SHIFT_REGS 1514 - && FP_REG_CLASS_P (REGNO_REG_CLASS (regno))))) 1515 + && (REGNO_REG_CLASS (regno) == SHIFT_REGS 1516 + && FP_REG_CLASS_P (class))) 1517 { 1518 sri->icode = in_p ? reload_in_optab[mode] : reload_out_optab[mode]; 1519 return NO_REGS; 1520 } 1521 1522 /* Secondary reloads of symbolic operands require %r1 as a scratch 1523 - register when we're generating PIC code and the operand isn't 1524 + register when we're generating PIC code and when the operand isn't 1525 readonly. */ 1526 if (GET_CODE (x) == HIGH) 1527 x = XEXP (x, 0); 1528 @@ -7743,6 +7779,12 @@ 1529 static void 1530 pa_encode_section_info (tree decl, rtx rtl, int first) 1531 { 1532 + int old_referenced = 0; 1533 + 1534 + if (!first && MEM_P (rtl) && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF) 1535 + old_referenced 1536 + = SYMBOL_REF_FLAGS (XEXP (rtl, 0)) & SYMBOL_FLAG_REFERENCED; 1537 + 1538 default_encode_section_info (decl, rtl, first); 1539 1540 if (first && TEXT_SPACE_P (decl)) 1541 @@ -7751,6 +7793,8 @@ 1542 if (TREE_CODE (decl) == FUNCTION_DECL) 1543 hppa_encode_label (XEXP (rtl, 0)); 1544 } 1545 + else if (old_referenced) 1546 + SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= old_referenced; 1547 } 1548 1549 /* This is sort of inverse to pa_encode_section_info. */ 1550 @@ -9519,4 +9563,62 @@ 1551 } 1552 #endif 1553 1554 +/* Return true if a change from mode FROM to mode TO for a register 1555 + in register class CLASS is invalid. */ 1556 + 1557 +bool 1558 +pa_cannot_change_mode_class (enum machine_mode from, enum machine_mode to, 1559 + enum reg_class class) 1560 +{ 1561 + if (from == to) 1562 + return false; 1563 + 1564 + /* Reject changes to/from complex and vector modes. */ 1565 + if (COMPLEX_MODE_P (from) || VECTOR_MODE_P (from) 1566 + || COMPLEX_MODE_P (to) || VECTOR_MODE_P (to)) 1567 + return true; 1568 + 1569 + if (GET_MODE_SIZE (from) == GET_MODE_SIZE (to)) 1570 + return false; 1571 + 1572 + /* There is no way to load QImode or HImode values directly from 1573 + memory. SImode loads to the FP registers are not zero extended. 1574 + On the 64-bit target, this conflicts with the definition of 1575 + LOAD_EXTEND_OP. Thus, we can't allow changing between modes 1576 + with different sizes in the floating-point registers. */ 1577 + if (MAYBE_FP_REG_CLASS_P (class)) 1578 + return true; 1579 + 1580 + /* HARD_REGNO_MODE_OK places modes with sizes larger than a word 1581 + in specific sets of registers. Thus, we cannot allow changing 1582 + to a larger mode when it's larger than a word. */ 1583 + if (GET_MODE_SIZE (to) > UNITS_PER_WORD 1584 + && GET_MODE_SIZE (to) > GET_MODE_SIZE (from)) 1585 + return true; 1586 + 1587 + return false; 1588 +} 1589 + 1590 +/* Returns TRUE if it is a good idea to tie two pseudo registers 1591 + when one has mode MODE1 and one has mode MODE2. 1592 + If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 1593 + for any hard reg, then this must be FALSE for correct output. 1594 + 1595 + We should return FALSE for QImode and HImode because these modes 1596 + are not ok in the floating-point registers. However, this prevents 1597 + tieing these modes to SImode and DImode in the general registers. 1598 + So, this isn't a good idea. We rely on HARD_REGNO_MODE_OK and 1599 + CANNOT_CHANGE_MODE_CLASS to prevent these modes from being used 1600 + in the floating-point registers. */ 1601 + 1602 +bool 1603 +pa_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2) 1604 +{ 1605 + /* Don't tie modes in different classes. */ 1606 + if (GET_MODE_CLASS (mode1) != GET_MODE_CLASS (mode2)) 1607 + return false; 1608 + 1609 + return true; 1610 +} 1611 + 1612 #include "gt-pa.h" 1613 diff -Naur gcc-4.2.2.orig/gcc/config/pa/pa.h gcc-4.2.2/gcc/config/pa/pa.h 1614 --- gcc-4.2.2.orig/gcc/config/pa/pa.h 2007-09-01 11:28:30.000000000 -0400 1615 +++ gcc-4.2.2/gcc/config/pa/pa.h 2007-12-09 22:17:24.000000000 -0500 1616 @@ -344,7 +344,7 @@ 1617 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 1618 for any hard reg, then this must be 0 for correct output. */ 1619 #define MODES_TIEABLE_P(MODE1, MODE2) \ 1620 - (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)) 1621 + pa_modes_tieable_p (MODE1, MODE2) 1622 1623 /* Specify the registers used for certain standard purposes. 1624 The values of these macros are register numbers. */ 1625 @@ -534,17 +534,6 @@ 1626 #define MAYBE_FP_REG_CLASS_P(CLASS) \ 1627 reg_classes_intersect_p ((CLASS), FP_REGS) 1628 1629 -/* On the PA it is not possible to directly move data between 1630 - GENERAL_REGS and FP_REGS. On the 32-bit port, we use the 1631 - location at SP-16. We don't expose this location in the RTL to 1632 - avoid scheduling related problems. For example, the store and 1633 - load could be separated by a call to a pure or const function 1634 - which has no frame and uses SP-16. */ 1635 -#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ 1636 - (TARGET_64BIT \ 1637 - && (MAYBE_FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2) \ 1638 - || MAYBE_FP_REG_CLASS_P (CLASS2) != FP_REG_CLASS_P (CLASS1))) 1639 - 1640 1641 1642 /* Stack layout; function entry, exit and calling. */ 1643 1644 @@ -1229,6 +1218,24 @@ 1645 (GET_CODE (OP) == CONST_INT && INTVAL (OP) == 63) : 0))))))) 1646 1647 1648 +/* Nonzero if 14-bit offsets can be used for all loads and stores. 1649 + This is not possible when generating PA 1.x code as floating point 1650 + loads and stores only support 5-bit offsets. Note that we do not 1651 + forbid the use of 14-bit offsets in GO_IF_LEGITIMATE_ADDRESS. 1652 + Instead, we use pa_secondary_reload() to reload integer mode 1653 + REG+D memory addresses used in floating point loads and stores. 1654 + 1655 + FIXME: the ELF32 linker clobbers the LSB of the FP register number 1656 + in PA 2.0 floating-point insns with long displacements. This is 1657 + because R_PARISC_DPREL14WR and other relocations like it are not 1658 + yet supported by GNU ld. For now, we reject long displacements 1659 + on this target. */ 1660 + 1661 +#define INT14_OK_STRICT \ 1662 + (TARGET_SOFT_FLOAT \ 1663 + || TARGET_DISABLE_FPREGS \ 1664 + || (TARGET_PA_20 && !TARGET_ELF32)) 1665 + 1666 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1667 and check its validity for a certain class. 1668 We have two alternate definitions for each of them. 1669 @@ -1247,16 +1254,18 @@ 1670 /* Nonzero if X is a hard reg that can be used as an index 1671 or if it is a pseudo reg. */ 1672 #define REG_OK_FOR_INDEX_P(X) \ 1673 -(REGNO (X) && (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER)) 1674 + (REGNO (X) && (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER)) 1675 + 1676 /* Nonzero if X is a hard reg that can be used as a base reg 1677 or if it is a pseudo reg. */ 1678 #define REG_OK_FOR_BASE_P(X) \ 1679 -(REGNO (X) && (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER)) 1680 + (REGNO (X) && (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER)) 1681 1682 #else 1683 1684 /* Nonzero if X is a hard reg that can be used as an index. */ 1685 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 1686 + 1687 /* Nonzero if X is a hard reg that can be used as a base reg. */ 1688 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 1689 1690 @@ -1308,11 +1317,7 @@ 1691 1692 We treat a SYMBOL_REF as legitimate if it is part of the current 1693 function's constant-pool, because such addresses can actually be 1694 - output as REG+SMALLINT. 1695 - 1696 - Note we only allow 5 bit immediates for access to a constant address; 1697 - doing so avoids losing for loading/storing a FP register at an address 1698 - which will not fit in 5 bits. */ 1699 + output as REG+SMALLINT. */ 1700 1701 #define VAL_5_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) + 0x10 < 0x20) 1702 #define INT_5_BITS(X) VAL_5_BITS_P (INTVAL (X)) 1703 @@ -1340,7 +1345,8 @@ 1704 ((TARGET_64BIT && (MODE) == DImode) \ 1705 || (MODE) == SImode \ 1706 || (MODE) == HImode \ 1707 - || (!TARGET_SOFT_FLOAT && ((MODE) == DFmode || (MODE) == SFmode))) 1708 + || (MODE) == SFmode \ 1709 + || (MODE) == DFmode) 1710 1711 /* These are the modes that we allow for unscaled indexing. */ 1712 #define MODE_OK_FOR_UNSCALED_INDEXING_P(MODE) \ 1713 @@ -1348,7 +1354,8 @@ 1714 || (MODE) == SImode \ 1715 || (MODE) == HImode \ 1716 || (MODE) == QImode \ 1717 - || (!TARGET_SOFT_FLOAT && ((MODE) == DFmode || (MODE) == SFmode))) 1718 + || (MODE) == SFmode \ 1719 + || (MODE) == DFmode) 1720 1721 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 1722 { \ 1723 @@ -1382,20 +1389,10 @@ 1724 || (INTVAL (index) % 8) == 0)) \ 1725 /* Similarly, the base register for SFmode/DFmode \ 1726 loads and stores with long displacements must \ 1727 - be aligned. \ 1728 - \ 1729 - FIXME: the ELF32 linker clobbers the LSB of \ 1730 - the FP register number in PA 2.0 floating-point \ 1731 - insns with long displacements. This is because \ 1732 - R_PARISC_DPREL14WR and other relocations like \ 1733 - it are not supported. For now, we reject long \ 1734 - displacements on this target. */ \ 1735 + be aligned. */ \ 1736 || (((MODE) == SFmode || (MODE) == DFmode) \ 1737 - && (TARGET_SOFT_FLOAT \ 1738 - || (TARGET_PA_20 \ 1739 - && !TARGET_ELF32 \ 1740 - && (INTVAL (index) \ 1741 - % GET_MODE_SIZE (MODE)) == 0))))) \ 1742 + && INT14_OK_STRICT \ 1743 + && (INTVAL (index) % GET_MODE_SIZE (MODE)) == 0))) \ 1744 || INT_5_BITS (index))) \ 1745 goto ADDR; \ 1746 if (!TARGET_DISABLE_INDEXING \ 1747 @@ -1495,7 +1492,7 @@ 1748 rtx new, temp = NULL_RTX; \ 1749 \ 1750 mask = (GET_MODE_CLASS (MODE) == MODE_FLOAT \ 1751 - ? (TARGET_PA_20 && !TARGET_ELF32 ? 0x3fff : 0x1f) : 0x3fff); \ 1752 + ? (INT14_OK_STRICT ? 0x3fff : 0x1f) : 0x3fff); \ 1753 \ 1754 if (optimize && GET_CODE (AD) == PLUS) \ 1755 temp = simplify_binary_operation (PLUS, Pmode, \ 1756 @@ -1517,9 +1514,10 @@ 1757 newoffset = offset & ~mask; \ 1758 \ 1759 /* Ensure that long displacements are aligned. */ \ 1760 - if (!VAL_5_BITS_P (newoffset) \ 1761 - && GET_MODE_CLASS (MODE) == MODE_FLOAT) \ 1762 - newoffset &= ~(GET_MODE_SIZE (MODE) -1); \ 1763 + if (mask == 0x3fff \ 1764 + && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ 1765 + || (TARGET_64BIT && (MODE) == DImode))) \ 1766 + newoffset &= ~(GET_MODE_SIZE (MODE) - 1); \ 1767 \ 1768 if (newoffset != 0 && VAL_14_BITS_P (newoffset)) \ 1769 { \ 1770 diff -Naur gcc-4.2.2.orig/gcc/config/pa/pa.md gcc-4.2.2/gcc/config/pa/pa.md 1771 --- gcc-4.2.2.orig/gcc/config/pa/pa.md 2007-09-01 11:28:30.000000000 -0400 1772 +++ gcc-4.2.2/gcc/config/pa/pa.md 2007-12-09 22:17:24.000000000 -0500 1773 @@ -3125,60 +3125,11 @@ 1774 1775 (define_insn "" 1776 [(set (match_operand:HI 0 "move_dest_operand" 1777 - "=r,r,r,r,r,Q,!*q,!r,!*f,?r,?*f") 1778 - (match_operand:HI 1 "move_src_operand" 1779 - "r,J,N,K,RQ,rM,!rM,!*q,!*fM,*f,r"))] 1780 - "(register_operand (operands[0], HImode) 1781 - || reg_or_0_operand (operands[1], HImode)) 1782 - && !TARGET_SOFT_FLOAT 1783 - && !TARGET_64BIT" 1784 - "@ 1785 - copy %1,%0 1786 - ldi %1,%0 1787 - ldil L'%1,%0 1788 - {zdepi|depwi,z} %Z1,%0 1789 - ldh%M1 %1,%0 1790 - sth%M0 %r1,%0 1791 - mtsar %r1 1792 - {mfctl|mfctl,w} %sar,%0 1793 - fcpy,sgl %f1,%0 1794 - {fstws|fstw} %1,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0 1795 - {stws|stw} %1,-16(%%sp)\n\t{fldws|fldw} -16(%%sp),%0" 1796 - [(set_attr "type" "move,move,move,shift,load,store,move,move,move,move,move") 1797 - (set_attr "pa_combine_type" "addmove") 1798 - (set_attr "length" "4,4,4,4,4,4,4,4,4,8,8")]) 1799 - 1800 -(define_insn "" 1801 - [(set (match_operand:HI 0 "move_dest_operand" 1802 - "=r,r,r,r,r,Q,!*q,!r,!*f") 1803 - (match_operand:HI 1 "move_src_operand" 1804 - "r,J,N,K,RQ,rM,!rM,!*q,!*fM"))] 1805 - "(register_operand (operands[0], HImode) 1806 - || reg_or_0_operand (operands[1], HImode)) 1807 - && !TARGET_SOFT_FLOAT 1808 - && TARGET_64BIT" 1809 - "@ 1810 - copy %1,%0 1811 - ldi %1,%0 1812 - ldil L'%1,%0 1813 - {zdepi|depwi,z} %Z1,%0 1814 - ldh%M1 %1,%0 1815 - sth%M0 %r1,%0 1816 - mtsar %r1 1817 - {mfctl|mfctl,w} %sar,%0 1818 - fcpy,sgl %f1,%0" 1819 - [(set_attr "type" "move,move,move,shift,load,store,move,move,move") 1820 - (set_attr "pa_combine_type" "addmove") 1821 - (set_attr "length" "4,4,4,4,4,4,4,4,4")]) 1822 - 1823 -(define_insn "" 1824 - [(set (match_operand:HI 0 "move_dest_operand" 1825 "=r,r,r,r,r,Q,!*q,!r") 1826 (match_operand:HI 1 "move_src_operand" 1827 "r,J,N,K,RQ,rM,!rM,!*q"))] 1828 "(register_operand (operands[0], HImode) 1829 - || reg_or_0_operand (operands[1], HImode)) 1830 - && TARGET_SOFT_FLOAT" 1831 + || reg_or_0_operand (operands[1], HImode))" 1832 "@ 1833 copy %1,%0 1834 ldi %1,%0 1835 @@ -3298,60 +3249,11 @@ 1836 1837 (define_insn "" 1838 [(set (match_operand:QI 0 "move_dest_operand" 1839 - "=r,r,r,r,r,Q,!*q,!r,!*f,?r,?*f") 1840 - (match_operand:QI 1 "move_src_operand" 1841 - "r,J,N,K,RQ,rM,!rM,!*q,!*fM,*f,r"))] 1842 - "(register_operand (operands[0], QImode) 1843 - || reg_or_0_operand (operands[1], QImode)) 1844 - && !TARGET_SOFT_FLOAT 1845 - && !TARGET_64BIT" 1846 - "@ 1847 - copy %1,%0 1848 - ldi %1,%0 1849 - ldil L'%1,%0 1850 - {zdepi|depwi,z} %Z1,%0 1851 - ldb%M1 %1,%0 1852 - stb%M0 %r1,%0 1853 - mtsar %r1 1854 - {mfctl|mfctl,w} %%sar,%0 1855 - fcpy,sgl %f1,%0 1856 - {fstws|fstw} %1,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0 1857 - {stws|stw} %1,-16(%%sp)\n\t{fldws|fldw} -16(%%sp),%0" 1858 - [(set_attr "type" "move,move,move,shift,load,store,move,move,move,move,move") 1859 - (set_attr "pa_combine_type" "addmove") 1860 - (set_attr "length" "4,4,4,4,4,4,4,4,4,8,8")]) 1861 - 1862 -(define_insn "" 1863 - [(set (match_operand:QI 0 "move_dest_operand" 1864 - "=r,r,r,r,r,Q,!*q,!r,!*f") 1865 - (match_operand:QI 1 "move_src_operand" 1866 - "r,J,N,K,RQ,rM,!rM,!*q,!*fM"))] 1867 - "(register_operand (operands[0], QImode) 1868 - || reg_or_0_operand (operands[1], QImode)) 1869 - && !TARGET_SOFT_FLOAT 1870 - && TARGET_64BIT" 1871 - "@ 1872 - copy %1,%0 1873 - ldi %1,%0 1874 - ldil L'%1,%0 1875 - {zdepi|depwi,z} %Z1,%0 1876 - ldb%M1 %1,%0 1877 - stb%M0 %r1,%0 1878 - mtsar %r1 1879 - {mfctl|mfctl,w} %%sar,%0 1880 - fcpy,sgl %f1,%0" 1881 - [(set_attr "type" "move,move,move,shift,load,store,move,move,move") 1882 - (set_attr "pa_combine_type" "addmove") 1883 - (set_attr "length" "4,4,4,4,4,4,4,4,4")]) 1884 - 1885 -(define_insn "" 1886 - [(set (match_operand:QI 0 "move_dest_operand" 1887 "=r,r,r,r,r,Q,!*q,!r") 1888 (match_operand:QI 1 "move_src_operand" 1889 "r,J,N,K,RQ,rM,!rM,!*q"))] 1890 "(register_operand (operands[0], QImode) 1891 - || reg_or_0_operand (operands[1], QImode)) 1892 - && TARGET_SOFT_FLOAT" 1893 + || reg_or_0_operand (operands[1], QImode))" 1894 "@ 1895 copy %1,%0 1896 ldi %1,%0 1897 diff -Naur gcc-4.2.2.orig/gcc/config/pa/pa32-regs.h gcc-4.2.2/gcc/config/pa/pa32-regs.h 1898 --- gcc-4.2.2.orig/gcc/config/pa/pa32-regs.h 2006-02-17 17:19:05.000000000 -0500 1899 +++ gcc-4.2.2/gcc/config/pa/pa32-regs.h 2007-12-09 22:17:24.000000000 -0500 1900 @@ -172,8 +172,7 @@ 1901 #define VALID_FP_MODE_P(MODE) \ 1902 ((MODE) == SFmode || (MODE) == DFmode \ 1903 || (MODE) == SCmode || (MODE) == DCmode \ 1904 - || (MODE) == QImode || (MODE) == HImode || (MODE) == SImode \ 1905 - || (TARGET_PA_11 && (MODE) == DImode)) 1906 + || (MODE) == SImode || (TARGET_PA_11 && (MODE) == DImode)) 1907 1908 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. 1909 1910 @@ -288,6 +287,11 @@ 1911 {0x00000000, 0x00000000, 0x01000000}, /* SHIFT_REGS */ \ 1912 {0xfffffffe, 0xffffffff, 0x01ffffff}} /* ALL_REGS */ 1913 1914 +/* Defines invalid mode changes. */ 1915 + 1916 +#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1917 + pa_cannot_change_mode_class (FROM, TO, CLASS) 1918 + 1919 /* Return the class number of the smallest class containing 1920 reg number REGNO. This could be a conditional expression 1921 or could index an array. */ 1922 diff -Naur gcc-4.2.2.orig/gcc/config/pa/pa64-regs.h gcc-4.2.2/gcc/config/pa/pa64-regs.h 1923 --- gcc-4.2.2.orig/gcc/config/pa/pa64-regs.h 2007-09-01 11:28:30.000000000 -0400 1924 +++ gcc-4.2.2/gcc/config/pa/pa64-regs.h 2007-12-09 22:17:24.000000000 -0500 1925 @@ -156,8 +156,7 @@ 1926 #define VALID_FP_MODE_P(MODE) \ 1927 ((MODE) == SFmode || (MODE) == DFmode \ 1928 || (MODE) == SCmode || (MODE) == DCmode \ 1929 - || (MODE) == QImode || (MODE) == HImode || (MODE) == SImode \ 1930 - || (MODE) == DImode) 1931 + || (MODE) == SImode || (MODE) == DImode) 1932 1933 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. 1934 On the HP-PA, the cpu registers can hold any mode. We 1935 @@ -242,17 +241,10 @@ 1936 {0x00000000, 0x10000000}, /* SHIFT_REGS */ \ 1937 {0xfffffffe, 0x1fffffff}} /* ALL_REGS */ 1938 1939 -/* Defines invalid mode changes. 1940 +/* Defines invalid mode changes. */ 1941 1942 - SImode loads to floating-point registers are not zero-extended. 1943 - The definition for LOAD_EXTEND_OP specifies that integer loads 1944 - narrower than BITS_PER_WORD will be zero-extended. As a result, 1945 - we inhibit changes from SImode unless they are to a mode that is 1946 - identical in size. */ 1947 - 1948 -#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1949 - ((FROM) == SImode && GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ 1950 - ? reg_classes_intersect_p (CLASS, FP_REGS) : 0) 1951 +#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1952 + pa_cannot_change_mode_class (FROM, TO, CLASS) 1953 1954 /* Return the class number of the smallest class containing 1955 reg number REGNO. This could be a conditional expression 1016 1956 diff -Naur gcc-4.2.2.orig/gcc/config/rs6000/linux-unwind.h gcc-4.2.2/gcc/config/rs6000/linux-unwind.h 1017 --- gcc-4.2.2.orig/gcc/config/rs6000/linux-unwind.h 2007-01-03 1 5:47:14.000000000 -08001018 +++ gcc-4.2.2/gcc/config/rs6000/linux-unwind.h 2007-10-20 17:51:31.000000000 -07001957 --- gcc-4.2.2.orig/gcc/config/rs6000/linux-unwind.h 2007-01-03 18:47:14.000000000 -0500 1958 +++ gcc-4.2.2/gcc/config/rs6000/linux-unwind.h 2007-10-20 20:51:31.000000000 -0400 1019 1959 @@ -244,7 +244,10 @@ 1020 1960 } … … 1030 1970 fs->regs.reg[LINK_REGISTER_REGNUM].loc.offset = (long) ®s->link - new_cfa; 1031 1971 diff -Naur gcc-4.2.2.orig/gcc/config/score/crti.asm gcc-4.2.2/gcc/config/score/crti.asm 1032 --- gcc-4.2.2.orig/gcc/config/score/crti.asm 2007-04-03 18:24:10.000000000 -07001033 +++ gcc-4.2.2/gcc/config/score/crti.asm 2007-10-1 7 23:24:34.000000000 -07001972 --- gcc-4.2.2.orig/gcc/config/score/crti.asm 2007-04-03 21:24:10.000000000 -0400 1973 +++ gcc-4.2.2/gcc/config/score/crti.asm 2007-10-18 02:24:34.000000000 -0400 1034 1974 @@ -34,6 +34,7 @@ 1035 1975 … … 1101 2041 - 1102 2042 diff -Naur gcc-4.2.2.orig/gcc/config/score/elf.h gcc-4.2.2/gcc/config/score/elf.h 1103 --- gcc-4.2.2.orig/gcc/config/score/elf.h 2007-09-01 08:28:30.000000000 -07001104 +++ gcc-4.2.2/gcc/config/score/elf.h 2007-10-1 7 23:24:34.000000000 -07002043 --- gcc-4.2.2.orig/gcc/config/score/elf.h 2007-09-01 11:28:30.000000000 -0400 2044 +++ gcc-4.2.2/gcc/config/score/elf.h 2007-10-18 02:24:34.000000000 -0400 1105 2045 @@ -32,16 +32,16 @@ 1106 2046 #define TYPE_OPERAND_FMT "@%s" … … 1124 2064 #ifndef ASM_OUTPUT_ALIGNED_BSS 1125 2065 diff -Naur gcc-4.2.2.orig/gcc/config/score/mac.md gcc-4.2.2/gcc/config/score/mac.md 1126 --- gcc-4.2.2.orig/gcc/config/score/mac.md 2007-09-01 08:28:30.000000000 -07001127 +++ gcc-4.2.2/gcc/config/score/mac.md 1969-12-31 1 6:00:00.000000000 -08002066 --- gcc-4.2.2.orig/gcc/config/score/mac.md 2007-09-01 11:28:30.000000000 -0400 2067 +++ gcc-4.2.2/gcc/config/score/mac.md 1969-12-31 19:00:00.000000000 -0500 1128 2068 @@ -1,180 +0,0 @@ 1129 2069 -;; Machine description for Sunplus S+CORE … … 1308 2248 - [(set_attr "mode" "DI")]) 1309 2249 diff -Naur gcc-4.2.2.orig/gcc/config/score/misc.md gcc-4.2.2/gcc/config/score/misc.md 1310 --- gcc-4.2.2.orig/gcc/config/score/misc.md 2007-09-01 08:28:30.000000000 -07001311 +++ gcc-4.2.2/gcc/config/score/misc.md 1969-12-31 1 6:00:00.000000000 -08002250 --- gcc-4.2.2.orig/gcc/config/score/misc.md 2007-09-01 11:28:30.000000000 -0400 2251 +++ gcc-4.2.2/gcc/config/score/misc.md 1969-12-31 19:00:00.000000000 -0500 1312 2252 @@ -1,381 +0,0 @@ 1313 2253 -;; Machine description for Sunplus S+CORE … … 1693 2633 - 1694 2634 diff -Naur gcc-4.2.2.orig/gcc/config/score/mul-div.S gcc-4.2.2/gcc/config/score/mul-div.S 1695 --- gcc-4.2.2.orig/gcc/config/score/mul-div.S 2007-09-01 08:28:30.000000000 -07001696 +++ gcc-4.2.2/gcc/config/score/mul-div.S 2007-10-1 7 23:24:34.000000000 -07002635 --- gcc-4.2.2.orig/gcc/config/score/mul-div.S 2007-09-01 11:28:30.000000000 -0400 2636 +++ gcc-4.2.2/gcc/config/score/mul-div.S 2007-10-18 02:24:34.000000000 -0400 1697 2637 @@ -14,8 +14,8 @@ 1698 2638 License for more details. … … 1769 2709 mv r4, a1 1770 2710 diff -Naur gcc-4.2.2.orig/gcc/config/score/predicates.md gcc-4.2.2/gcc/config/score/predicates.md 1771 --- gcc-4.2.2.orig/gcc/config/score/predicates.md 2007-09-01 08:28:30.000000000 -07001772 +++ gcc-4.2.2/gcc/config/score/predicates.md 2007-10-1 7 23:24:34.000000000 -07002711 --- gcc-4.2.2.orig/gcc/config/score/predicates.md 2007-09-01 11:28:30.000000000 -0400 2712 +++ gcc-4.2.2/gcc/config/score/predicates.md 2007-10-18 02:24:34.000000000 -0400 1773 2713 @@ -17,16 +17,44 @@ 1774 2714 ;; along with GCC; see the file COPYING3. If not see … … 1910 2850 }) 1911 2851 2852 diff -Naur gcc-4.2.2.orig/gcc/config/score/score-conv.h gcc-4.2.2/gcc/config/score/score-conv.h 2853 --- gcc-4.2.2.orig/gcc/config/score/score-conv.h 2007-09-01 11:28:30.000000000 -0400 2854 +++ gcc-4.2.2/gcc/config/score/score-conv.h 2007-10-18 02:24:34.000000000 -0400 2855 @@ -17,11 +17,16 @@ 2856 along with GCC; see the file COPYING3. If not see 2857 <http://www.gnu.org/licenses/>. */ 2858 2859 -#ifndef SCORE_CONV_0601 2860 -#define SCORE_CONV_0601 2861 +#ifndef GCC_SCORE_CONV_H 2862 +#define GCC_SCORE_CONV_H 2863 2864 extern int target_flags; 2865 2866 +/* Define the information needed to generate branch insns. This is 2867 + stored from the compare operation. */ 2868 +extern GTY(()) rtx cmp_op0; 2869 +extern GTY(()) rtx cmp_op1; 2870 + 2871 #define GP_REG_FIRST 0U 2872 #define GP_REG_LAST 31U 2873 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1U) 2874 @@ -40,47 +45,38 @@ 2875 2876 #define GP_REG_P(REGNO) REG_CONTAIN (REGNO, GP_REG_FIRST, GP_REG_NUM) 2877 2878 +#define G8_REG_P(REGNO) REG_CONTAIN (REGNO, GP_REG_FIRST, 8) 2879 + 2880 #define G16_REG_P(REGNO) REG_CONTAIN (REGNO, GP_REG_FIRST, 16) 2881 2882 #define CE_REG_P(REGNO) REG_CONTAIN (REGNO, CE_REG_FIRST, CE_REG_NUM) 2883 2884 -#define UIMM_IN_RANGE(V, W) ((V) >= 0 && (V) < ((HOST_WIDE_INT) 1 << (W))) 2885 +#define GR_REG_CLASS_P(C) ((C) == G16_REGS || (C) == G32_REGS) 2886 +#define SP_REG_CLASS_P(C) \ 2887 + ((C) == CN_REG || (C) == LC_REG || (C) == SC_REG || (C) == SP_REGS) 2888 +#define CP_REG_CLASS_P(C) \ 2889 + ((C) == CP1_REGS || (C) == CP2_REGS || (C) == CP3_REGS || (C) == CPA_REGS) 2890 +#define CE_REG_CLASS_P(C) \ 2891 + ((C) == HI_REG || (C) == LO_REG || (C) == CE_REGS) 2892 + 2893 +#define UIMM_IN_RANGE(V, W) ((V) >= 0 && (V) < ((HOST_WIDE_INT) 1 << (W))) 2894 2895 #define SIMM_IN_RANGE(V, W) \ 2896 ((V) >= (-1 * ((HOST_WIDE_INT) 1 << ((W) - 1))) \ 2897 && (V) < (1 * ((HOST_WIDE_INT) 1 << ((W) - 1)))) 2898 2899 -#define IMM_IN_RANGE(V, W, S) \ 2900 +#define IMM_IN_RANGE(V, W, S) \ 2901 ((S) ? SIMM_IN_RANGE (V, W) : UIMM_IN_RANGE (V, W)) 2902 2903 -#define IMM_IS_POW_OF_2(V, E1, E2) \ 2904 +#define IMM_IS_POW_OF_2(V, E1, E2) \ 2905 ((V) >= ((unsigned HOST_WIDE_INT) 1 << (E1)) \ 2906 && (V) <= ((unsigned HOST_WIDE_INT) 1 << (E2)) \ 2907 && ((V) & ((V) - 1)) == 0) 2908 2909 -#define SCORE_STACK_ALIGN(LOC) (((LOC) + 3) & ~3) 2910 - 2911 -#define SCORE_MAX_FIRST_STACK_STEP (0x3ff0) 2912 - 2913 -#define SCORE_SDATA_MAX score_sdata_max () 2914 - 2915 -#define DEFAULT_SDATA_MAX 8 2916 - 2917 -#define CONST_HIGH_PART(VALUE) \ 2918 - (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff) 2919 - 2920 -#define CONST_LOW_PART(VALUE) ((VALUE) - CONST_HIGH_PART (VALUE)) 2921 - 2922 -#define PROLOGUE_TEMP_REGNUM (GP_REG_FIRST + 8) 2923 - 2924 -#define EPILOGUE_TEMP_REGNUM (GP_REG_FIRST + 8) 2925 - 2926 enum score_symbol_type 2927 { 2928 SYMBOL_GENERAL, 2929 - SYMBOL_SMALL_DATA /* The symbol refers to something in a small data section. */ 2930 + SYMBOL_SMALL_DATA /* The symbol refers to something in a small data section */ 2931 }; 2932 2933 -int score_sdata_max (void); 2934 - 2935 #endif 2936 diff -Naur gcc-4.2.2.orig/gcc/config/score/score-generic.md gcc-4.2.2/gcc/config/score/score-generic.md 2937 --- gcc-4.2.2.orig/gcc/config/score/score-generic.md 1969-12-31 19:00:00.000000000 -0500 2938 +++ gcc-4.2.2/gcc/config/score/score-generic.md 2007-10-18 02:24:34.000000000 -0400 2939 @@ -0,0 +1,45 @@ 2940 +;; Machine description for Sunplus S+CORE 2941 +;; Sunplus S+CORE Pipeline Description 2942 +;; Copyright (C) 2005, 2007 2943 +;; Free Software Foundation, Inc. 2944 +;; Contributed by Sunnorth. 2945 + 2946 +;; This file is part of GCC. 2947 + 2948 +;; GCC is free software; you can redistribute it and/or modify 2949 +;; it under the terms of the GNU General Public License as published by 2950 +;; the Free Software Foundation; either version 3, or (at your option) 2951 +;; any later version. 2952 + 2953 +;; GCC is distributed in the hope that it will be useful, 2954 +;; but WITHOUT ANY WARRANTY; without even the implied warranty of 2955 +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 2956 +;; GNU General Public License for more details. 2957 + 2958 +;; You should have received a copy of the GNU General Public License 2959 +;; along with GCC; see the file COPYING3. If not see 2960 +;; <http://www.gnu.org/licenses/>. 2961 + 2962 +(define_automaton "score") 2963 + 2964 +(define_cpu_unit "core" "score") 2965 + 2966 +(define_insn_reservation "memory" 3 2967 + (eq_attr "type" "load") 2968 + "core") 2969 + 2970 +(define_insn_reservation "mul" 3 2971 + (eq_attr "type" "mul,div") 2972 + "core") 2973 + 2974 +(define_insn_reservation "fce" 1 2975 + (eq_attr "type" "fce") 2976 + "core") 2977 + 2978 +(define_insn_reservation "tsr" 1 2979 + (eq_attr "type" "tsr,fsr") 2980 + "core") 2981 + 2982 +(define_insn_reservation "up_c" 1 2983 + (eq_attr "up_c" "yes") 2984 + "core") 2985 diff -Naur gcc-4.2.2.orig/gcc/config/score/score-mdaux.c gcc-4.2.2/gcc/config/score/score-mdaux.c 2986 --- gcc-4.2.2.orig/gcc/config/score/score-mdaux.c 2007-09-01 11:28:30.000000000 -0400 2987 +++ gcc-4.2.2/gcc/config/score/score-mdaux.c 1969-12-31 19:00:00.000000000 -0500 2988 @@ -1,1058 +0,0 @@ 2989 -/* score-mdaux.c for Sunplus S+CORE processor 2990 - Copyright (C) 2005, 2007 Free Software Foundation, Inc. 2991 - Contributed by Sunnorth 2992 - 2993 - This file is part of GCC. 2994 - 2995 - GCC is free software; you can redistribute it and/or modify it 2996 - under the terms of the GNU General Public License as published 2997 - by the Free Software Foundation; either version 3, or (at your 2998 - option) any later version. 2999 - 3000 - GCC is distributed in the hope that it will be useful, but WITHOUT 3001 - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 3002 - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 3003 - License for more details. 3004 - 3005 - You should have received a copy of the GNU General Public License 3006 - along with GCC; see the file COPYING3. If not see 3007 - <http://www.gnu.org/licenses/>. */ 3008 - 3009 -#include "config.h" 3010 -#include "system.h" 3011 -#include "coretypes.h" 3012 -#include "tm.h" 3013 -#include <signal.h> 3014 -#include "rtl.h" 3015 -#include "regs.h" 3016 -#include "hard-reg-set.h" 3017 -#include "real.h" 3018 -#include "insn-config.h" 3019 -#include "conditions.h" 3020 -#include "insn-attr.h" 3021 -#include "recog.h" 3022 -#include "toplev.h" 3023 -#include "output.h" 3024 -#include "tree.h" 3025 -#include "function.h" 3026 -#include "expr.h" 3027 -#include "optabs.h" 3028 -#include "flags.h" 3029 -#include "reload.h" 3030 -#include "tm_p.h" 3031 -#include "ggc.h" 3032 -#include "gstab.h" 3033 -#include "hashtab.h" 3034 -#include "debug.h" 3035 -#include "target.h" 3036 -#include "target-def.h" 3037 -#include "integrate.h" 3038 -#include "langhooks.h" 3039 -#include "cfglayout.h" 3040 -#include "score-mdaux.h" 3041 - 3042 -#define BITSET_P(VALUE, BIT) (((VALUE) & (1L << (BIT))) != 0) 3043 -#define INS_BUF_SZ 100 3044 - 3045 -/* Define the information needed to generate branch insns. This is 3046 - stored from the compare operation. */ 3047 -rtx cmp_op0, cmp_op1; 3048 - 3049 -static char ins[INS_BUF_SZ + 8]; 3050 - 3051 -/* Return true if SYMBOL is a SYMBOL_REF and OFFSET + SYMBOL points 3052 - to the same object as SYMBOL. */ 3053 -static int 3054 -score_offset_within_object_p (rtx symbol, HOST_WIDE_INT offset) 3055 -{ 3056 - if (GET_CODE (symbol) != SYMBOL_REF) 3057 - return 0; 3058 - 3059 - if (CONSTANT_POOL_ADDRESS_P (symbol) 3060 - && offset >= 0 3061 - && offset < (int)GET_MODE_SIZE (get_pool_mode (symbol))) 3062 - return 1; 3063 - 3064 - if (SYMBOL_REF_DECL (symbol) != 0 3065 - && offset >= 0 3066 - && offset < int_size_in_bytes (TREE_TYPE (SYMBOL_REF_DECL (symbol)))) 3067 - return 1; 3068 - 3069 - return 0; 3070 -} 3071 - 3072 -/* Split X into a base and a constant offset, storing them in *BASE 3073 - and *OFFSET respectively. */ 3074 -static void 3075 -score_split_const (rtx x, rtx *base, HOST_WIDE_INT *offset) 3076 -{ 3077 - *offset = 0; 3078 - 3079 - if (GET_CODE (x) == CONST) 3080 - x = XEXP (x, 0); 3081 - 3082 - if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT) 3083 - { 3084 - *offset += INTVAL (XEXP (x, 1)); 3085 - x = XEXP (x, 0); 3086 - } 3087 - 3088 - *base = x; 3089 -} 3090 - 3091 -/* Classify symbol X, which must be a SYMBOL_REF or a LABEL_REF. */ 3092 -static enum 3093 -score_symbol_type score_classify_symbol (rtx x) 3094 -{ 3095 - if (GET_CODE (x) == LABEL_REF) 3096 - return SYMBOL_GENERAL; 3097 - 3098 - gcc_assert (GET_CODE (x) == SYMBOL_REF); 3099 - 3100 - if (CONSTANT_POOL_ADDRESS_P (x)) 3101 - { 3102 - if (GET_MODE_SIZE (get_pool_mode (x)) <= SCORE_SDATA_MAX) 3103 - return SYMBOL_SMALL_DATA; 3104 - return SYMBOL_GENERAL; 3105 - } 3106 - if (SYMBOL_REF_SMALL_P (x)) 3107 - return SYMBOL_SMALL_DATA; 3108 - return SYMBOL_GENERAL; 3109 -} 3110 - 3111 -/* Return true if the current function must save REGNO. */ 3112 -static int 3113 -score_save_reg_p (unsigned int regno) 3114 -{ 3115 - /* Check call-saved registers. */ 3116 - if (regs_ever_live[regno] && !call_used_regs[regno]) 3117 - return 1; 3118 - 3119 - /* We need to save the old frame pointer before setting up a new one. */ 3120 - if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) 3121 - return 1; 3122 - 3123 - /* We need to save the incoming return address if it is ever clobbered 3124 - within the function. */ 3125 - if (regno == RA_REGNUM && regs_ever_live[regno]) 3126 - return 1; 3127 - 3128 - return 0; 3129 -} 3130 - 3131 -/* Return one word of double-word value OP, taking into account the fixed 3132 - endianness of certain registers. HIGH_P is true to select the high part, 3133 - false to select the low part. */ 3134 -static rtx 3135 -subw (rtx op, int high_p) 3136 -{ 3137 - unsigned int byte; 3138 - enum machine_mode mode = GET_MODE (op); 3139 - 3140 - if (mode == VOIDmode) 3141 - mode = DImode; 3142 - 3143 - byte = (TARGET_LITTLE_ENDIAN ? high_p : !high_p) ? UNITS_PER_WORD : 0; 3144 - 3145 - if (GET_CODE (op) == REG && REGNO (op) == HI_REGNUM) 3146 - return gen_rtx_REG (SImode, high_p ? HI_REGNUM : LO_REGNUM); 3147 - 3148 - if (GET_CODE (op) == MEM) 3149 - return adjust_address (op, SImode, byte); 3150 - 3151 - return simplify_gen_subreg (SImode, op, mode, byte); 3152 -} 3153 - 3154 -struct score_frame_info * 3155 -mda_cached_frame (void) 3156 -{ 3157 - static struct score_frame_info _frame_info; 3158 - return &_frame_info; 3159 -} 3160 - 3161 -/* Return the bytes needed to compute the frame pointer from the current 3162 - stack pointer. SIZE is the size (in bytes) of the local variables. */ 3163 -struct score_frame_info * 3164 -mda_compute_frame_size (HOST_WIDE_INT size) 3165 -{ 3166 - unsigned int regno; 3167 - struct score_frame_info *f = mda_cached_frame (); 3168 - 3169 - memset (f, 0, sizeof (struct score_frame_info)); 3170 - f->gp_reg_size = 0; 3171 - f->mask = 0; 3172 - f->var_size = SCORE_STACK_ALIGN (size); 3173 - f->args_size = current_function_outgoing_args_size; 3174 - f->cprestore_size = flag_pic ? UNITS_PER_WORD : 0; 3175 - if (f->var_size == 0 && current_function_is_leaf) 3176 - f->args_size = f->cprestore_size = 0; 3177 - 3178 - if (f->args_size == 0 && current_function_calls_alloca) 3179 - f->args_size = UNITS_PER_WORD; 3180 - 3181 - f->total_size = f->var_size + f->args_size + f->cprestore_size; 3182 - for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) 3183 - { 3184 - if (score_save_reg_p (regno)) 3185 - { 3186 - f->gp_reg_size += GET_MODE_SIZE (SImode); 3187 - f->mask |= 1 << (regno - GP_REG_FIRST); 3188 - } 3189 - } 3190 - 3191 - if (current_function_calls_eh_return) 3192 - { 3193 - unsigned int i; 3194 - for (i = 0;; ++i) 3195 - { 3196 - regno = EH_RETURN_DATA_REGNO (i); 3197 - if (regno == INVALID_REGNUM) 3198 - break; 3199 - f->gp_reg_size += GET_MODE_SIZE (SImode); 3200 - f->mask |= 1 << (regno - GP_REG_FIRST); 3201 - } 3202 - } 3203 - 3204 - f->total_size += f->gp_reg_size; 3205 - f->num_gp = f->gp_reg_size / UNITS_PER_WORD; 3206 - 3207 - if (f->mask) 3208 - { 3209 - HOST_WIDE_INT offset; 3210 - offset = (f->args_size + f->cprestore_size + f->var_size 3211 - + f->gp_reg_size - GET_MODE_SIZE (SImode)); 3212 - f->gp_sp_offset = offset; 3213 - } 3214 - else 3215 - f->gp_sp_offset = 0; 3216 - 3217 - return f; 3218 -} 3219 - 3220 -/* Generate the prologue instructions for entry into a S+core function. */ 3221 -void 3222 -mdx_prologue (void) 3223 -{ 3224 -#define EMIT_PL(_rtx) RTX_FRAME_RELATED_P (_rtx) = 1 3225 - 3226 - struct score_frame_info *f = mda_compute_frame_size (get_frame_size ()); 3227 - HOST_WIDE_INT size; 3228 - int regno; 3229 - 3230 - size = f->total_size - f->gp_reg_size; 3231 - 3232 - if (flag_pic) 3233 - emit_insn (gen_cpload ()); 3234 - 3235 - for (regno = (int) GP_REG_LAST; regno >= (int) GP_REG_FIRST; regno--) 3236 - { 3237 - if (BITSET_P (f->mask, regno - GP_REG_FIRST)) 3238 - { 3239 - rtx mem = gen_rtx_MEM (SImode, 3240 - gen_rtx_PRE_DEC (SImode, stack_pointer_rtx)); 3241 - rtx reg = gen_rtx_REG (SImode, regno); 3242 - if (!current_function_calls_eh_return) 3243 - MEM_READONLY_P (mem) = 1; 3244 - EMIT_PL (emit_insn (gen_pushsi (mem, reg))); 3245 - } 3246 - } 3247 - 3248 - if (size > 0) 3249 - { 3250 - rtx insn; 3251 - 3252 - if (CONST_OK_FOR_LETTER_P (-size, 'L')) 3253 - EMIT_PL (emit_insn (gen_add3_insn (stack_pointer_rtx, 3254 - stack_pointer_rtx, 3255 - GEN_INT (-size)))); 3256 - else 3257 - { 3258 - EMIT_PL (emit_move_insn (gen_rtx_REG (Pmode, PROLOGUE_TEMP_REGNUM), 3259 - GEN_INT (size))); 3260 - EMIT_PL (emit_insn 3261 - (gen_sub3_insn (stack_pointer_rtx, 3262 - stack_pointer_rtx, 3263 - gen_rtx_REG (Pmode, 3264 - PROLOGUE_TEMP_REGNUM)))); 3265 - } 3266 - insn = get_last_insn (); 3267 - REG_NOTES (insn) = 3268 - alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR, 3269 - gen_rtx_SET (VOIDmode, stack_pointer_rtx, 3270 - plus_constant (stack_pointer_rtx, 3271 - -size)), 3272 - REG_NOTES (insn)); 3273 - } 3274 - 3275 - if (frame_pointer_needed) 3276 - EMIT_PL (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx)); 3277 - 3278 - if (flag_pic && f->cprestore_size) 3279 - { 3280 - if (frame_pointer_needed) 3281 - emit_insn (gen_cprestore_use_fp (GEN_INT (size - f->cprestore_size))); 3282 - else 3283 - emit_insn (gen_cprestore_use_sp (GEN_INT (size - f->cprestore_size))); 3284 - } 3285 - 3286 -#undef EMIT_PL 3287 -} 3288 - 3289 -/* Generate the epilogue instructions in a S+core function. */ 3290 -void 3291 -mdx_epilogue (int sibcall_p) 3292 -{ 3293 - struct score_frame_info *f = mda_compute_frame_size (get_frame_size ()); 3294 - HOST_WIDE_INT size; 3295 - int regno; 3296 - rtx base; 3297 - 3298 - size = f->total_size - f->gp_reg_size; 3299 - 3300 - if (!frame_pointer_needed) 3301 - base = stack_pointer_rtx; 3302 - else 3303 - base = hard_frame_pointer_rtx; 3304 - 3305 - if (size) 3306 - { 3307 - if (CONST_OK_FOR_LETTER_P (size, 'L')) 3308 - emit_insn (gen_add3_insn (base, base, GEN_INT (size))); 3309 - else 3310 - { 3311 - emit_move_insn (gen_rtx_REG (Pmode, EPILOGUE_TEMP_REGNUM), 3312 - GEN_INT (size)); 3313 - emit_insn (gen_add3_insn (base, base, 3314 - gen_rtx_REG (Pmode, 3315 - EPILOGUE_TEMP_REGNUM))); 3316 - } 3317 - } 3318 - 3319 - if (base != stack_pointer_rtx) 3320 - emit_move_insn (stack_pointer_rtx, base); 3321 - 3322 - if (current_function_calls_eh_return) 3323 - emit_insn (gen_add3_insn (stack_pointer_rtx, 3324 - stack_pointer_rtx, 3325 - EH_RETURN_STACKADJ_RTX)); 3326 - 3327 - for (regno = (int) GP_REG_FIRST; regno <= (int) GP_REG_LAST; regno++) 3328 - { 3329 - if (BITSET_P (f->mask, regno - GP_REG_FIRST)) 3330 - { 3331 - rtx mem = gen_rtx_MEM (SImode, 3332 - gen_rtx_POST_INC (SImode, stack_pointer_rtx)); 3333 - rtx reg = gen_rtx_REG (SImode, regno); 3334 - 3335 - if (!current_function_calls_eh_return) 3336 - MEM_READONLY_P (mem) = 1; 3337 - 3338 - emit_insn (gen_popsi (reg, mem)); 3339 - } 3340 - } 3341 - 3342 - if (!sibcall_p) 3343 - emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, RA_REGNUM))); 3344 -} 3345 - 3346 -/* Return true if X is a valid base register for the given mode. 3347 - Allow only hard registers if STRICT. */ 3348 -int 3349 -mda_valid_base_register_p (rtx x, int strict) 3350 -{ 3351 - if (!strict && GET_CODE (x) == SUBREG) 3352 - x = SUBREG_REG (x); 3353 - 3354 - return (GET_CODE (x) == REG 3355 - && score_regno_mode_ok_for_base_p (REGNO (x), strict)); 3356 -} 3357 - 3358 -/* Return true if X is a valid address for machine mode MODE. If it is, 3359 - fill in INFO appropriately. STRICT is true if we should only accept 3360 - hard base registers. */ 3361 -int 3362 -mda_classify_address (struct score_address_info *info, 3363 - enum machine_mode mode, rtx x, int strict) 3364 -{ 3365 - info->code = GET_CODE (x); 3366 - 3367 - switch (info->code) 3368 - { 3369 - case REG: 3370 - case SUBREG: 3371 - info->type = ADD_REG; 3372 - info->reg = x; 3373 - info->offset = const0_rtx; 3374 - return mda_valid_base_register_p (info->reg, strict); 3375 - case PLUS: 3376 - info->type = ADD_REG; 3377 - info->reg = XEXP (x, 0); 3378 - info->offset = XEXP (x, 1); 3379 - return (mda_valid_base_register_p (info->reg, strict) 3380 - && GET_CODE (info->offset) == CONST_INT 3381 - && IMM_IN_RANGE (INTVAL (info->offset), 15, 1)); 3382 - case PRE_DEC: 3383 - case POST_DEC: 3384 - case PRE_INC: 3385 - case POST_INC: 3386 - if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (SImode)) 3387 - return false; 3388 - info->type = ADD_REG; 3389 - info->reg = XEXP (x, 0); 3390 - info->offset = GEN_INT (GET_MODE_SIZE (mode)); 3391 - return mda_valid_base_register_p (info->reg, strict); 3392 - case CONST_INT: 3393 - info->type = ADD_CONST_INT; 3394 - return IMM_IN_RANGE (INTVAL (x), 15, 1); 3395 - case CONST: 3396 - case LABEL_REF: 3397 - case SYMBOL_REF: 3398 - info->type = ADD_SYMBOLIC; 3399 - return (mda_symbolic_constant_p (x, &info->symbol_type) 3400 - && (info->symbol_type == SYMBOL_GENERAL 3401 - || info->symbol_type == SYMBOL_SMALL_DATA)); 3402 - default: 3403 - return 0; 3404 - } 3405 -} 3406 - 3407 -void 3408 -mda_gen_cmp (enum machine_mode mode) 3409 -{ 3410 - emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, CC_REGNUM), 3411 - gen_rtx_COMPARE (mode, cmp_op0, cmp_op1))); 3412 -} 3413 - 3414 -/* Return true if X is a symbolic constant that can be calculated in 3415 - the same way as a bare symbol. If it is, store the type of the 3416 - symbol in *SYMBOL_TYPE. */ 3417 -int 3418 -mda_symbolic_constant_p (rtx x, enum score_symbol_type *symbol_type) 3419 -{ 3420 - HOST_WIDE_INT offset; 3421 - 3422 - score_split_const (x, &x, &offset); 3423 - if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF) 3424 - *symbol_type = score_classify_symbol (x); 3425 - else 3426 - return 0; 3427 - 3428 - if (offset == 0) 3429 - return 1; 3430 - 3431 - /* if offset > 15bit, must reload */ 3432 - if (!IMM_IN_RANGE (offset, 15, 1)) 3433 - return 0; 3434 - 3435 - switch (*symbol_type) 3436 - { 3437 - case SYMBOL_GENERAL: 3438 - return 1; 3439 - case SYMBOL_SMALL_DATA: 3440 - return score_offset_within_object_p (x, offset); 3441 - } 3442 - gcc_unreachable (); 3443 -} 3444 - 3445 -void 3446 -mdx_movsicc (rtx *ops) 3447 -{ 3448 - enum machine_mode mode; 3449 - 3450 - mode = score_select_cc_mode (GET_CODE (ops[1]), ops[2], ops[3]); 3451 - emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, CC_REGNUM), 3452 - gen_rtx_COMPARE (mode, cmp_op0, cmp_op1))); 3453 -} 3454 - 3455 -/* Call and sibcall pattern all need call this function. */ 3456 -void 3457 -mdx_call (rtx *ops, bool sib) 3458 -{ 3459 - rtx addr = XEXP (ops[0], 0); 3460 - if (!call_insn_operand (addr, VOIDmode)) 3461 - { 3462 - rtx oaddr = addr; 3463 - addr = gen_reg_rtx (Pmode); 3464 - gen_move_insn (addr, oaddr); 3465 - } 3466 - 3467 - if (sib) 3468 - emit_call_insn (gen_sibcall_internal (addr, ops[1])); 3469 - else 3470 - emit_call_insn (gen_call_internal (addr, ops[1])); 3471 -} 3472 - 3473 -/* Call value and sibcall value pattern all need call this function. */ 3474 -void 3475 -mdx_call_value (rtx *ops, bool sib) 3476 -{ 3477 - rtx result = ops[0]; 3478 - rtx addr = XEXP (ops[1], 0); 3479 - rtx arg = ops[2]; 3480 - 3481 - if (!call_insn_operand (addr, VOIDmode)) 3482 - { 3483 - rtx oaddr = addr; 3484 - addr = gen_reg_rtx (Pmode); 3485 - gen_move_insn (addr, oaddr); 3486 - } 3487 - 3488 - if (sib) 3489 - emit_call_insn (gen_sibcall_value_internal (result, addr, arg)); 3490 - else 3491 - emit_call_insn (gen_call_value_internal (result, addr, arg)); 3492 -} 3493 - 3494 -/* Machine Split */ 3495 -void 3496 -mds_movdi (rtx *ops) 3497 -{ 3498 - rtx dst = ops[0]; 3499 - rtx src = ops[1]; 3500 - rtx dst0 = subw (dst, 0); 3501 - rtx dst1 = subw (dst, 1); 3502 - rtx src0 = subw (src, 0); 3503 - rtx src1 = subw (src, 1); 3504 - 3505 - if (GET_CODE (dst0) == REG && reg_overlap_mentioned_p (dst0, src)) 3506 - { 3507 - emit_move_insn (dst1, src1); 3508 - emit_move_insn (dst0, src0); 3509 - } 3510 - else 3511 - { 3512 - emit_move_insn (dst0, src0); 3513 - emit_move_insn (dst1, src1); 3514 - } 3515 -} 3516 - 3517 -void 3518 -mds_zero_extract_andi (rtx *ops) 3519 -{ 3520 - if (INTVAL (ops[1]) == 1 && const_uimm5 (ops[2], SImode)) 3521 - emit_insn (gen_zero_extract_bittst (ops[0], ops[2])); 3522 - else 3523 - { 3524 - unsigned HOST_WIDE_INT mask; 3525 - mask = (0xffffffffU & ((1U << INTVAL (ops[1])) - 1U)); 3526 - mask = mask << INTVAL (ops[2]); 3527 - emit_insn (gen_andsi3_cmp (ops[3], ops[0], 3528 - gen_int_mode (mask, SImode))); 3529 - } 3530 -} 3531 - 3532 -/* Check addr could be present as PRE/POST mode. */ 3533 -static bool 3534 -mda_pindex_mem (rtx addr) 3535 -{ 3536 - if (GET_CODE (addr) == MEM) 3537 - { 3538 - switch (GET_CODE (XEXP (addr, 0))) 3539 - { 3540 - case PRE_DEC: 3541 - case POST_DEC: 3542 - case PRE_INC: 3543 - case POST_INC: 3544 - return true; 3545 - default: 3546 - break; 3547 - } 3548 - } 3549 - return false; 3550 -} 3551 - 3552 -/* Output asm code for ld/sw insn. */ 3553 -static int 3554 -pr_addr_post (rtx *ops, int idata, int iaddr, char *ip, enum mda_mem_unit unit) 3555 -{ 3556 - struct score_address_info ai; 3557 - 3558 - gcc_assert (GET_CODE (ops[idata]) == REG); 3559 - gcc_assert (mda_classify_address (&ai, SImode, XEXP (ops[iaddr], 0), true)); 3560 - 3561 - if (!mda_pindex_mem (ops[iaddr]) 3562 - && ai.type == ADD_REG 3563 - && GET_CODE (ai.offset) == CONST_INT 3564 - && G16_REG_P (REGNO (ops[idata])) 3565 - && G16_REG_P (REGNO (ai.reg))) 3566 - { 3567 - if (INTVAL (ai.offset) == 0) 3568 - { 3569 - ops[iaddr] = ai.reg; 3570 - return snprintf (ip, INS_BUF_SZ, 3571 - "! %%%d, [%%%d]", idata, iaddr); 3572 - } 3573 - if (REGNO (ai.reg) == HARD_FRAME_POINTER_REGNUM) 3574 - { 3575 - HOST_WIDE_INT offset = INTVAL (ai.offset); 3576 - if (MDA_ALIGN_UNIT (offset, unit) 3577 - && CONST_OK_FOR_LETTER_P (offset >> unit, 'J')) 3578 - { 3579 - ops[iaddr] = ai.offset; 3580 - return snprintf (ip, INS_BUF_SZ, 3581 - "p! %%%d, %%c%d", idata, iaddr); 3582 - } 3583 - } 3584 - } 3585 - return snprintf (ip, INS_BUF_SZ, " %%%d, %%a%d", idata, iaddr); 3586 -} 3587 - 3588 -/* Output asm insn for load. */ 3589 -const char * 3590 -mdp_linsn (rtx *ops, enum mda_mem_unit unit, bool sign) 3591 -{ 3592 - const char *pre_ins[] = 3593 - {"lbu", "lhu", "lw", "??", "lb", "lh", "lw", "??"}; 3594 - char *ip; 3595 - 3596 - strcpy (ins, pre_ins[(sign ? 4 : 0) + unit]); 3597 - ip = ins + strlen (ins); 3598 - 3599 - if ((!sign && unit != MDA_HWORD) 3600 - || (sign && unit != MDA_BYTE)) 3601 - pr_addr_post (ops, 0, 1, ip, unit); 3602 - else 3603 - snprintf (ip, INS_BUF_SZ, " %%0, %%a1"); 3604 - 3605 - return ins; 3606 -} 3607 - 3608 -/* Output asm insn for store. */ 3609 -const char * 3610 -mdp_sinsn (rtx *ops, enum mda_mem_unit unit) 3611 -{ 3612 - const char *pre_ins[] = {"sb", "sh", "sw"}; 3613 - char *ip; 3614 - 3615 - strcpy (ins, pre_ins[unit]); 3616 - ip = ins + strlen (ins); 3617 - pr_addr_post (ops, 1, 0, ip, unit); 3618 - return ins; 3619 -} 3620 - 3621 -/* Output asm insn for load immediate. */ 3622 -const char * 3623 -mdp_limm (rtx *ops) 3624 -{ 3625 - HOST_WIDE_INT v; 3626 - 3627 - gcc_assert (GET_CODE (ops[0]) == REG); 3628 - gcc_assert (GET_CODE (ops[1]) == CONST_INT); 3629 - 3630 - v = INTVAL (ops[1]); 3631 - if (G16_REG_P (REGNO (ops[0])) && IMM_IN_RANGE (v, 8, 0)) 3632 - return "ldiu! %0, %c1"; 3633 - else if (IMM_IN_RANGE (v, 16, 1)) 3634 - return "ldi %0, %c1"; 3635 - else if ((v & 0xffff) == 0) 3636 - return "ldis %0, %U1"; 3637 - else 3638 - return "li %0, %c1"; 3639 -} 3640 - 3641 -/* Output asm insn for move. */ 3642 -const char * 3643 -mdp_move (rtx *ops) 3644 -{ 3645 - gcc_assert (GET_CODE (ops[0]) == REG); 3646 - gcc_assert (GET_CODE (ops[1]) == REG); 3647 - 3648 - if (G16_REG_P (REGNO (ops[0]))) 3649 - { 3650 - if (G16_REG_P (REGNO (ops[1]))) 3651 - return "mv! %0, %1"; 3652 - else 3653 - return "mlfh! %0, %1"; 3654 - } 3655 - else if (G16_REG_P (REGNO (ops[1]))) 3656 - return "mhfl! %0, %1"; 3657 - else 3658 - return "mv %0, %1"; 3659 -} 3660 - 3661 -/* Emit lcb/lce insns. */ 3662 -bool 3663 -mdx_unaligned_load (rtx *ops) 3664 -{ 3665 - rtx dst = ops[0]; 3666 - rtx src = ops[1]; 3667 - rtx len = ops[2]; 3668 - rtx off = ops[3]; 3669 - rtx addr_reg; 3670 - 3671 - if (INTVAL (len) != BITS_PER_WORD 3672 - || (INTVAL (off) % BITS_PER_UNIT) != 0) 3673 - return false; 3674 - 3675 - gcc_assert (GET_MODE_SIZE (GET_MODE (dst)) == GET_MODE_SIZE (SImode)); 3676 - 3677 - addr_reg = copy_addr_to_reg (XEXP (src, 0)); 3678 - emit_insn (gen_move_lcb (addr_reg, addr_reg)); 3679 - emit_insn (gen_move_lce (addr_reg, addr_reg, dst)); 3680 - 3681 - return true; 3682 -} 3683 - 3684 -/* Emit scb/sce insns. */ 3685 -bool 3686 -mdx_unaligned_store (rtx *ops) 3687 -{ 3688 - rtx dst = ops[0]; 3689 - rtx len = ops[1]; 3690 - rtx off = ops[2]; 3691 - rtx src = ops[3]; 3692 - rtx addr_reg; 3693 - 3694 - if (INTVAL(len) != BITS_PER_WORD 3695 - || (INTVAL(off) % BITS_PER_UNIT) != 0) 3696 - return false; 3697 - 3698 - gcc_assert (GET_MODE_SIZE (GET_MODE (src)) == GET_MODE_SIZE (SImode)); 3699 - 3700 - addr_reg = copy_addr_to_reg (XEXP (dst, 0)); 3701 - emit_insn (gen_move_scb (addr_reg, addr_reg, src)); 3702 - emit_insn (gen_move_sce (addr_reg, addr_reg)); 3703 - 3704 - return true; 3705 -} 3706 - 3707 -/* If length is short, generate move insns straight. */ 3708 -static void 3709 -mdx_block_move_straight (rtx dst, rtx src, HOST_WIDE_INT length) 3710 -{ 3711 - HOST_WIDE_INT leftover; 3712 - int i, reg_count; 3713 - rtx *regs; 3714 - 3715 - leftover = length % UNITS_PER_WORD; 3716 - length -= leftover; 3717 - reg_count = length / UNITS_PER_WORD; 3718 - 3719 - regs = alloca (sizeof (rtx) * reg_count); 3720 - for (i = 0; i < reg_count; i++) 3721 - regs[i] = gen_reg_rtx (SImode); 3722 - 3723 - /* Load from src to regs. */ 3724 - if (MEM_ALIGN (src) >= BITS_PER_WORD) 3725 - { 3726 - HOST_WIDE_INT offset = 0; 3727 - for (i = 0; i < reg_count; offset += UNITS_PER_WORD, i++) 3728 - emit_move_insn (regs[i], adjust_address (src, SImode, offset)); 3729 - } 3730 - else if (reg_count >= 1) 3731 - { 3732 - rtx src_reg = copy_addr_to_reg (XEXP (src, 0)); 3733 - 3734 - emit_insn (gen_move_lcb (src_reg, src_reg)); 3735 - for (i = 0; i < (reg_count - 1); i++) 3736 - emit_insn (gen_move_lcw (src_reg, src_reg, regs[i])); 3737 - emit_insn (gen_move_lce (src_reg, src_reg, regs[i])); 3738 - } 3739 - 3740 - /* Store regs to dest. */ 3741 - if (MEM_ALIGN (dst) >= BITS_PER_WORD) 3742 - { 3743 - HOST_WIDE_INT offset = 0; 3744 - for (i = 0; i < reg_count; offset += UNITS_PER_WORD, i++) 3745 - emit_move_insn (adjust_address (dst, SImode, offset), regs[i]); 3746 - } 3747 - else if (reg_count >= 1) 3748 - { 3749 - rtx dst_reg = copy_addr_to_reg (XEXP (dst, 0)); 3750 - 3751 - emit_insn (gen_move_scb (dst_reg, dst_reg, regs[0])); 3752 - for (i = 1; i < reg_count; i++) 3753 - emit_insn (gen_move_scw (dst_reg, dst_reg, regs[i])); 3754 - emit_insn (gen_move_sce (dst_reg, dst_reg)); 3755 - } 3756 - 3757 - /* Mop up any left-over bytes. */ 3758 - if (leftover > 0) 3759 - { 3760 - src = adjust_address (src, BLKmode, length); 3761 - dst = adjust_address (dst, BLKmode, length); 3762 - move_by_pieces (dst, src, leftover, 3763 - MIN (MEM_ALIGN (src), MEM_ALIGN (dst)), 0); 3764 - } 3765 -} 3766 - 3767 -/* Generate loop head when dst or src is unaligned. */ 3768 -static void 3769 -mdx_block_move_loop_head (rtx dst_reg, HOST_WIDE_INT dst_align, 3770 - rtx src_reg, HOST_WIDE_INT src_align, 3771 - HOST_WIDE_INT length) 3772 -{ 3773 - bool src_unaligned = (src_align < BITS_PER_WORD); 3774 - bool dst_unaligned = (dst_align < BITS_PER_WORD); 3775 - 3776 - rtx temp = gen_reg_rtx (SImode); 3777 - 3778 - gcc_assert (length == UNITS_PER_WORD); 3779 - 3780 - if (src_unaligned) 3781 - { 3782 - emit_insn (gen_move_lcb (src_reg, src_reg)); 3783 - emit_insn (gen_move_lcw (src_reg, src_reg, temp)); 3784 - } 3785 - else 3786 - emit_insn (gen_move_lw_a (src_reg, 3787 - src_reg, gen_int_mode (4, SImode), temp)); 3788 - 3789 - if (dst_unaligned) 3790 - emit_insn (gen_move_scb (dst_reg, dst_reg, temp)); 3791 - else 3792 - emit_insn (gen_move_sw_a (dst_reg, 3793 - dst_reg, gen_int_mode (4, SImode), temp)); 3794 -} 3795 - 3796 -/* Generate loop body, copy length bytes per iteration. */ 3797 -static void 3798 -mdx_block_move_loop_body (rtx dst_reg, HOST_WIDE_INT dst_align, 3799 - rtx src_reg, HOST_WIDE_INT src_align, 3800 - HOST_WIDE_INT length) 3801 -{ 3802 - int reg_count = length / UNITS_PER_WORD; 3803 - rtx *regs = alloca (sizeof (rtx) * reg_count); 3804 - int i; 3805 - bool src_unaligned = (src_align < BITS_PER_WORD); 3806 - bool dst_unaligned = (dst_align < BITS_PER_WORD); 3807 - 3808 - for (i = 0; i < reg_count; i++) 3809 - regs[i] = gen_reg_rtx (SImode); 3810 - 3811 - if (src_unaligned) 3812 - { 3813 - for (i = 0; i < reg_count; i++) 3814 - emit_insn (gen_move_lcw (src_reg, src_reg, regs[i])); 3815 - } 3816 - else 3817 - { 3818 - for (i = 0; i < reg_count; i++) 3819 - emit_insn (gen_move_lw_a (src_reg, 3820 - src_reg, gen_int_mode (4, SImode), regs[i])); 3821 - } 3822 - 3823 - if (dst_unaligned) 3824 - { 3825 - for (i = 0; i < reg_count; i++) 3826 - emit_insn (gen_move_scw (dst_reg, dst_reg, regs[i])); 3827 - } 3828 - else 3829 - { 3830 - for (i = 0; i < reg_count; i++) 3831 - emit_insn (gen_move_sw_a (dst_reg, 3832 - dst_reg, gen_int_mode (4, SImode), regs[i])); 3833 - } 3834 -} 3835 - 3836 -/* Generate loop foot, copy the leftover bytes. */ 3837 -static void 3838 -mdx_block_move_loop_foot (rtx dst_reg, HOST_WIDE_INT dst_align, 3839 - rtx src_reg, HOST_WIDE_INT src_align, 3840 - HOST_WIDE_INT length) 3841 -{ 3842 - bool src_unaligned = (src_align < BITS_PER_WORD); 3843 - bool dst_unaligned = (dst_align < BITS_PER_WORD); 3844 - 3845 - HOST_WIDE_INT leftover; 3846 - 3847 - leftover = length % UNITS_PER_WORD; 3848 - length -= leftover; 3849 - 3850 - if (length > 0) 3851 - mdx_block_move_loop_body (dst_reg, dst_align, 3852 - src_reg, src_align, length); 3853 - 3854 - if (dst_unaligned) 3855 - emit_insn (gen_move_sce (dst_reg, dst_reg)); 3856 - 3857 - if (leftover > 0) 3858 - { 3859 - HOST_WIDE_INT src_adj = src_unaligned ? -4 : 0; 3860 - HOST_WIDE_INT dst_adj = dst_unaligned ? -4 : 0; 3861 - rtx temp; 3862 - 3863 - gcc_assert (leftover < UNITS_PER_WORD); 3864 - 3865 - if (leftover >= UNITS_PER_WORD / 2 3866 - && src_align >= BITS_PER_WORD / 2 3867 - && dst_align >= BITS_PER_WORD / 2) 3868 - { 3869 - temp = gen_reg_rtx (HImode); 3870 - emit_insn (gen_move_lhu_b (src_reg, src_reg, 3871 - gen_int_mode (src_adj, SImode), temp)); 3872 - emit_insn (gen_move_sh_b (dst_reg, dst_reg, 3873 - gen_int_mode (dst_adj, SImode), temp)); 3874 - leftover -= UNITS_PER_WORD / 2; 3875 - src_adj = UNITS_PER_WORD / 2; 3876 - dst_adj = UNITS_PER_WORD / 2; 3877 - } 3878 - 3879 - while (leftover > 0) 3880 - { 3881 - temp = gen_reg_rtx (QImode); 3882 - emit_insn (gen_move_lbu_b (src_reg, src_reg, 3883 - gen_int_mode (src_adj, SImode), temp)); 3884 - emit_insn (gen_move_sb_b (dst_reg, dst_reg, 3885 - gen_int_mode (dst_adj, SImode), temp)); 3886 - leftover--; 3887 - src_adj = 1; 3888 - dst_adj = 1; 3889 - } 3890 - } 3891 -} 3892 - 3893 -#define MIN_MOVE_REGS 3 3894 -#define MIN_MOVE_BYTES (MIN_MOVE_REGS * UNITS_PER_WORD) 3895 -#define MAX_MOVE_REGS 4 3896 -#define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD) 3897 - 3898 -/* The length is large, generate a loop if necessary. 3899 - The loop is consisted by loop head/body/foot. */ 3900 -static void 3901 -mdx_block_move_loop (rtx dst, rtx src, HOST_WIDE_INT length) 3902 -{ 3903 - HOST_WIDE_INT src_align = MEM_ALIGN (src); 3904 - HOST_WIDE_INT dst_align = MEM_ALIGN (dst); 3905 - HOST_WIDE_INT loop_mov_bytes; 3906 - HOST_WIDE_INT iteration = 0; 3907 - HOST_WIDE_INT head_length = 0, leftover; 3908 - rtx label, src_reg, dst_reg, final_dst; 3909 - 3910 - bool gen_loop_head = (src_align < BITS_PER_WORD 3911 - || dst_align < BITS_PER_WORD); 3912 - 3913 - if (gen_loop_head) 3914 - head_length += UNITS_PER_WORD; 3915 - 3916 - for (loop_mov_bytes = MAX_MOVE_BYTES; 3917 - loop_mov_bytes >= MIN_MOVE_BYTES; 3918 - loop_mov_bytes -= UNITS_PER_WORD) 3919 - { 3920 - iteration = (length - head_length) / loop_mov_bytes; 3921 - if (iteration > 1) 3922 - break; 3923 - } 3924 - if (iteration <= 1) 3925 - { 3926 - mdx_block_move_straight (dst, src, length); 3927 - return; 3928 - } 3929 - 3930 - leftover = (length - head_length) % loop_mov_bytes; 3931 - length -= leftover; 3932 - 3933 - src_reg = copy_addr_to_reg (XEXP (src, 0)); 3934 - dst_reg = copy_addr_to_reg (XEXP (dst, 0)); 3935 - final_dst = expand_simple_binop (Pmode, PLUS, dst_reg, GEN_INT (length), 3936 - 0, 0, OPTAB_WIDEN); 3937 - 3938 - if (gen_loop_head) 3939 - mdx_block_move_loop_head (dst_reg, dst_align, 3940 - src_reg, src_align, head_length); 3941 - 3942 - label = gen_label_rtx (); 3943 - emit_label (label); 3944 - 3945 - mdx_block_move_loop_body (dst_reg, dst_align, 3946 - src_reg, src_align, loop_mov_bytes); 3947 - 3948 - emit_insn (gen_cmpsi (dst_reg, final_dst)); 3949 - emit_jump_insn (gen_bne (label)); 3950 - 3951 - mdx_block_move_loop_foot (dst_reg, dst_align, 3952 - src_reg, src_align, leftover); 3953 -} 3954 - 3955 -/* Generate block move, for misc.md: "movmemsi". */ 3956 -bool 3957 -mdx_block_move (rtx *ops) 3958 -{ 3959 - rtx dst = ops[0]; 3960 - rtx src = ops[1]; 3961 - rtx length = ops[2]; 3962 - 3963 - if (TARGET_LITTLE_ENDIAN 3964 - && (MEM_ALIGN (src) < BITS_PER_WORD || MEM_ALIGN (dst) < BITS_PER_WORD) 3965 - && INTVAL (length) >= UNITS_PER_WORD) 3966 - return false; 3967 - 3968 - if (GET_CODE (length) == CONST_INT) 3969 - { 3970 - if (INTVAL (length) <= 2 * MAX_MOVE_BYTES) 3971 - { 3972 - mdx_block_move_straight (dst, src, INTVAL (length)); 3973 - return true; 3974 - } 3975 - else if (optimize && 3976 - !(flag_unroll_loops || flag_unroll_all_loops)) 3977 - { 3978 - mdx_block_move_loop (dst, src, INTVAL (length)); 3979 - return true; 3980 - } 3981 - } 3982 - return false; 3983 -} 3984 - 3985 -/* Generate add insn. */ 3986 -const char * 3987 -mdp_select_add_imm (rtx *ops, bool set_cc) 3988 -{ 3989 - HOST_WIDE_INT v = INTVAL (ops[2]); 3990 - 3991 - gcc_assert (GET_CODE (ops[2]) == CONST_INT); 3992 - gcc_assert (REGNO (ops[0]) == REGNO (ops[1])); 3993 - 3994 - if (set_cc && G16_REG_P (REGNO (ops[0]))) 3995 - { 3996 - if (v > 0 && IMM_IS_POW_OF_2 ((unsigned HOST_WIDE_INT) v, 0, 15)) 3997 - { 3998 - ops[2] = GEN_INT (ffs (v) - 1); 3999 - return "addei! %0, %c2"; 4000 - } 4001 - 4002 - if (v < 0 && IMM_IS_POW_OF_2 ((unsigned HOST_WIDE_INT) (-v), 0, 15)) 4003 - { 4004 - ops[2] = GEN_INT (ffs (-v) - 1); 4005 - return "subei! %0, %c2"; 4006 - } 4007 - } 4008 - 4009 - if (set_cc) 4010 - return "addi.c %0, %c2"; 4011 - else 4012 - return "addi %0, %c2"; 4013 -} 4014 - 4015 -/* Output arith insn. */ 4016 -const char * 4017 -mdp_select (rtx *ops, const char *inst_pre, 4018 - bool commu, const char *letter, bool set_cc) 4019 -{ 4020 - gcc_assert (GET_CODE (ops[0]) == REG); 4021 - gcc_assert (GET_CODE (ops[1]) == REG); 4022 - 4023 - if (set_cc && G16_REG_P (REGNO (ops[0])) 4024 - && (GET_CODE (ops[2]) == REG ? G16_REG_P (REGNO (ops[2])) : 1) 4025 - && REGNO (ops[0]) == REGNO (ops[1])) 4026 - { 4027 - snprintf (ins, INS_BUF_SZ, "%s! %%0, %%%s2", inst_pre, letter); 4028 - return ins; 4029 - } 4030 - 4031 - if (commu && set_cc && G16_REG_P (REGNO (ops[0])) 4032 - && G16_REG_P (REGNO (ops[1])) 4033 - && REGNO (ops[0]) == REGNO (ops[2])) 4034 - { 4035 - gcc_assert (GET_CODE (ops[2]) == REG); 4036 - snprintf (ins, INS_BUF_SZ, "%s! %%0, %%%s1", inst_pre, letter); 4037 - return ins; 4038 - } 4039 - 4040 - if (set_cc) 4041 - snprintf (ins, INS_BUF_SZ, "%s.c %%0, %%1, %%%s2", inst_pre, letter); 4042 - else 4043 - snprintf (ins, INS_BUF_SZ, "%s %%0, %%1, %%%s2", inst_pre, letter); 4044 - return ins; 4045 -} 4046 - 4047 diff -Naur gcc-4.2.2.orig/gcc/config/score/score-mdaux.h gcc-4.2.2/gcc/config/score/score-mdaux.h 4048 --- gcc-4.2.2.orig/gcc/config/score/score-mdaux.h 2007-09-01 11:28:30.000000000 -0400 4049 +++ gcc-4.2.2/gcc/config/score/score-mdaux.h 1969-12-31 19:00:00.000000000 -0500 4050 @@ -1,115 +0,0 @@ 4051 -/* score-mdaux.h for Sunplus S+CORE processor 4052 - Copyright (C) 2005, 2007 Free Software Foundation, Inc. 4053 - Contributed by Sunnorth 4054 - 4055 - This file is part of GCC. 4056 - 4057 - GCC is free software; you can redistribute it and/or modify it 4058 - under the terms of the GNU General Public License as published 4059 - by the Free Software Foundation; either version 3, or (at your 4060 - option) any later version. 4061 - 4062 - GCC is distributed in the hope that it will be useful, but WITHOUT 4063 - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 4064 - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 4065 - License for more details. 4066 - 4067 - You should have received a copy of the GNU General Public License 4068 - along with GCC; see the file COPYING3. If not see 4069 - <http://www.gnu.org/licenses/>. */ 4070 - 4071 -#ifndef SCORE_MDAUX_0621 4072 -#define SCORE_MDAUX_0621 4073 - 4074 -/* Machine Auxiliary Functions. */ 4075 -enum score_address_type 4076 -{ 4077 - ADD_REG, 4078 - ADD_CONST_INT, 4079 - ADD_SYMBOLIC 4080 -}; 4081 -#ifdef RTX_CODE 4082 -struct score_address_info 4083 -{ 4084 - enum score_address_type type; 4085 - rtx reg; 4086 - rtx offset; 4087 - enum rtx_code code; 4088 - enum score_symbol_type symbol_type; 4089 -}; 4090 -#endif 4091 - 4092 -struct score_frame_info 4093 -{ 4094 - HOST_WIDE_INT total_size; /* bytes that the entire frame takes up */ 4095 - HOST_WIDE_INT var_size; /* bytes that variables take up */ 4096 - HOST_WIDE_INT args_size; /* bytes that outgoing arguments take up */ 4097 - HOST_WIDE_INT gp_reg_size; /* bytes needed to store gp regs */ 4098 - HOST_WIDE_INT gp_sp_offset; /* offset from new sp to store gp registers */ 4099 - HOST_WIDE_INT cprestore_size; /* # bytes that the .cprestore slot takes up */ 4100 - unsigned int mask; /* mask of saved gp registers */ 4101 - int num_gp; /* number of gp registers saved */ 4102 -}; 4103 - 4104 -typedef void (*score_save_restore_fn) (rtx, rtx); 4105 - 4106 -int mda_valid_base_register_p (rtx x, int strict); 4107 - 4108 -#ifdef RTX_CODE 4109 -int mda_classify_address (struct score_address_info *info, 4110 - enum machine_mode mode, rtx x, int strict); 4111 - 4112 -struct score_frame_info *mda_compute_frame_size (HOST_WIDE_INT size); 4113 - 4114 -struct score_frame_info *mda_cached_frame (void); 4115 - 4116 -void mda_gen_cmp (enum machine_mode mode); 4117 -#endif 4118 - 4119 -int mda_symbolic_constant_p (rtx x, enum score_symbol_type *symbol_type); 4120 - 4121 -int mda_bp (void); 4122 - 4123 -/* Machine Expand. */ 4124 -void mdx_prologue (void); 4125 - 4126 -void mdx_epilogue (int sibcall_p); 4127 - 4128 -void mdx_movsicc (rtx *ops); 4129 - 4130 -void mdx_call (rtx *ops, bool sibcall); 4131 - 4132 -void mdx_call_value (rtx *ops, bool sibcall); 4133 - 4134 -/* Machine Split. */ 4135 -void mds_movdi (rtx *ops); 4136 - 4137 -void mds_zero_extract_andi (rtx *ops); 4138 - 4139 -/* Machine Print. */ 4140 -enum mda_mem_unit {MDA_BYTE = 0, MDA_HWORD = 1, MDA_WORD = 2}; 4141 - 4142 -#define MDA_ALIGN_UNIT(V, UNIT) !(V & ((1 << UNIT) - 1)) 4143 - 4144 -const char * mdp_linsn (rtx *ops, enum mda_mem_unit unit, bool sign); 4145 - 4146 -const char * mdp_sinsn (rtx *ops, enum mda_mem_unit unit); 4147 - 4148 -const char * mdp_select_add_imm (rtx *ops, bool set_cc); 4149 - 4150 -const char * mdp_select (rtx *ops, const char *inst_pre, 4151 - bool commu, const char *letter, bool set_cc); 4152 - 4153 -const char * mdp_limm (rtx *ops); 4154 - 4155 -const char * mdp_move (rtx *ops); 4156 - 4157 -/* Machine unaligned memory load/store. */ 4158 -bool mdx_unaligned_load (rtx* ops); 4159 - 4160 -bool mdx_unaligned_store (rtx* ops); 4161 - 4162 -bool mdx_block_move (rtx* ops); 4163 - 4164 -#endif 4165 - 4166 diff -Naur gcc-4.2.2.orig/gcc/config/score/score-protos.h gcc-4.2.2/gcc/config/score/score-protos.h 4167 --- gcc-4.2.2.orig/gcc/config/score/score-protos.h 2007-09-01 11:28:30.000000000 -0400 4168 +++ gcc-4.2.2/gcc/config/score/score-protos.h 2007-10-18 02:24:34.000000000 -0400 4169 @@ -17,75 +17,80 @@ 4170 along with GCC; see the file COPYING3. If not see 4171 <http://www.gnu.org/licenses/>. */ 4172 4173 -#ifndef __SCORE_PROTOS_H__ 4174 -#define __SCORE_PROTOS_H__ 4175 +#ifndef GCC_SCORE_PROTOS_H 4176 +#define GCC_SCORE_PROTOS_H 4177 4178 -extern enum reg_class score_char_to_class[]; 4179 +/* Machine Print. */ 4180 +enum score_mem_unit {SCORE_BYTE = 0, SCORE_HWORD = 1, SCORE_WORD = 2}; 4181 4182 -void score_override_options (void); 4183 +#define SCORE_ALIGN_UNIT(V, UNIT) !(V & ((1 << UNIT) - 1)) 4184 4185 -void score_init_expanders (void); 4186 - 4187 -int score_hard_regno_mode_ok (unsigned int, enum machine_mode); 4188 - 4189 -int score_reg_class (int regno); 4190 - 4191 -enum reg_class score_preferred_reload_class (rtx x, enum reg_class class); 4192 - 4193 -enum reg_class score_secondary_reload_class (enum reg_class class, 4194 - enum machine_mode mode, rtx x); 4195 - 4196 -int score_const_ok_for_letter_p (HOST_WIDE_INT value, char c); 4197 - 4198 -int score_extra_constraint (rtx op, char c); 4199 - 4200 -rtx score_return_addr (int count, rtx frame); 4201 - 4202 -HOST_WIDE_INT score_initial_elimination_offset (int from, int to); 4203 - 4204 -rtx score_function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode, 4205 - tree type, int named); 4206 - 4207 -int score_arg_partial_nregs (const CUMULATIVE_ARGS *cum, 4208 - enum machine_mode mode, tree type, int named); 4209 - 4210 -void score_init_cumulative_args (CUMULATIVE_ARGS *cum, 4211 - tree fntype, rtx libname); 4212 - 4213 -void score_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode, 4214 - tree type, int named); 4215 - 4216 -rtx score_function_value (tree valtype, tree func, enum machine_mode mode); 4217 - 4218 -rtx score_va_arg (tree va_list, tree type); 4219 - 4220 -void score_initialize_trampoline (rtx ADDR, rtx FUNC, rtx CHAIN); 4221 - 4222 -int score_address_p (enum machine_mode mode, rtx x, int strict); 4223 - 4224 -int score_legitimize_address (rtx *xloc); 4225 - 4226 -int score_regno_mode_ok_for_base_p (int regno, int strict); 4227 - 4228 -int score_register_move_cost (enum machine_mode mode, enum reg_class to, 4229 - enum reg_class from); 4230 - 4231 -void score_declare_object (FILE *stream, const char *name, 4232 - const char *directive, const char *fmt, ...); 4233 - 4234 -void score_declare_object_name (FILE *stream, const char *name, tree decl); 4235 - 4236 -int score_output_external (FILE *file, tree decl, const char *name); 4237 - 4238 -void score_print_operand (FILE *file, rtx op, int letter); 4239 - 4240 -void score_print_operand_address (FILE *file, rtx addr); 4241 +extern void score_gen_cmp (enum machine_mode mode); 4242 +extern void score_prologue (void); 4243 +extern void score_epilogue (int sibcall_p); 4244 +extern void score_call (rtx *ops, bool sib); 4245 +extern void score_call_value (rtx *ops, bool sib); 4246 +extern void score_movdi (rtx *ops); 4247 +extern void score_zero_extract_andi (rtx *ops); 4248 +extern const char * score_linsn (rtx *ops, enum score_mem_unit unit, bool sign); 4249 +extern const char * score_sinsn (rtx *ops, enum score_mem_unit unit); 4250 +extern const char * score_limm (rtx *ops); 4251 +extern const char * score_move (rtx *ops); 4252 +extern bool score_unaligned_load (rtx* ops); 4253 +extern bool score_unaligned_store (rtx* ops); 4254 +extern bool score_block_move (rtx* ops); 4255 +extern int score_address_cost (rtx addr); 4256 +extern rtx score_function_arg (const CUMULATIVE_ARGS *cum, 4257 + enum machine_mode mode, 4258 + tree type, int named); 4259 +extern int score_address_p (enum machine_mode mode, rtx x, int strict); 4260 +extern int score_reg_class (int regno); 4261 +extern int score_register_move_cost (enum machine_mode mode, enum reg_class to, 4262 + enum reg_class from); 4263 +extern int score_hard_regno_mode_ok (unsigned int, enum machine_mode); 4264 +extern int score_const_ok_for_letter_p (HOST_WIDE_INT value, char c); 4265 +extern int score_extra_constraint (rtx op, char c); 4266 +extern rtx score_return_addr (int count, rtx frame); 4267 +extern void score_initialize_trampoline (rtx ADDR, rtx FUNC, rtx CHAIN); 4268 +extern int score_regno_mode_ok_for_base_p (int regno, int strict); 4269 +extern void score_function_arg_advance (CUMULATIVE_ARGS *cum, 4270 + enum machine_mode mode, 4271 + tree type, int named); 4272 +extern void score_init_cumulative_args (CUMULATIVE_ARGS *cum, 4273 + tree fntype, rtx libname); 4274 +extern void score_declare_object (FILE *stream, const char *name, 4275 + const char *directive, const char *fmt, ...); 4276 +extern int score_output_external (FILE *file, tree decl, const char *name); 4277 +extern void score_override_options (void); 4278 +extern enum reg_class score_secondary_reload_class (enum reg_class class, 4279 + enum machine_mode mode, 4280 + rtx x); 4281 +extern rtx score_function_value (tree valtype, tree func, 4282 + enum machine_mode mode); 4283 +extern enum reg_class score_preferred_reload_class (rtx x, 4284 + enum reg_class class); 4285 +extern HOST_WIDE_INT score_initial_elimination_offset (int from, int to); 4286 +extern void score_print_operand (FILE *file, rtx op, int letter); 4287 +extern void score_print_operand_address (FILE *file, rtx addr); 4288 +extern int score_legitimize_address (rtx *xloc); 4289 +extern int score_arg_partial_bytes (CUMULATIVE_ARGS *cum, 4290 + enum machine_mode mode, 4291 + tree type, bool named); 4292 +extern int score_symbolic_constant_p (rtx x, 4293 + enum score_symbol_type *symbol_type); 4294 +extern void score_movsicc (rtx *ops); 4295 +extern const char * score_select_add_imm (rtx *ops, bool set_cc); 4296 +extern const char * score_select (rtx *ops, const char *inst_pre, bool commu, 4297 + const char *letter, bool set_cc); 4298 +extern const char * score_output_casesi (rtx *operands); 4299 +extern const char * score_rpush (rtx *ops); 4300 +extern const char * score_rpop (rtx *ops); 4301 +extern bool score_rtx_costs (rtx x, int code, int outer_code, int *total); 4302 4303 #ifdef RTX_CODE 4304 -enum machine_mode score_select_cc_mode (enum rtx_code op, rtx x, rtx y); 4305 +extern enum machine_mode score_select_cc_mode (enum rtx_code op, rtx x, rtx y); 4306 #endif 4307 4308 -#include "score-mdaux.h" 4309 - 4310 -#endif /* __SCORE_PROTOS_H__ */ 4311 +extern struct extern_list *extern_head; 4312 4313 +#endif /* GCC_SCORE_PROTOS_H */ 4314 diff -Naur gcc-4.2.2.orig/gcc/config/score/score-version.h gcc-4.2.2/gcc/config/score/score-version.h 4315 --- gcc-4.2.2.orig/gcc/config/score/score-version.h 2007-09-01 11:28:30.000000000 -0400 4316 +++ gcc-4.2.2/gcc/config/score/score-version.h 1969-12-31 19:00:00.000000000 -0500 4317 @@ -1,20 +0,0 @@ 4318 -/* score-version.h for Sunplus S+CORE processor 4319 - Copyright (C) 2005, 2007 Free Software Foundation, Inc. 4320 - 4321 - This file is part of GCC. 4322 - 4323 - GCC is free software; you can redistribute it and/or modify it 4324 - under the terms of the GNU General Public License as published 4325 - by the Free Software Foundation; either version 3, or (at your 4326 - option) any later version. 4327 - 4328 - GCC is distributed in the hope that it will be useful, but WITHOUT 4329 - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 4330 - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 4331 - License for more details. 4332 - 4333 - You should have received a copy of the GNU General Public License 4334 - along with GCC; see the file COPYING3. If not see 4335 - <http://www.gnu.org/licenses/>. */ 4336 - 4337 -#define SCORE_GCC_VERSION "1.2" 4338 diff -Naur gcc-4.2.2.orig/gcc/config/score/score.c gcc-4.2.2/gcc/config/score/score.c 4339 --- gcc-4.2.2.orig/gcc/config/score/score.c 2007-09-01 11:28:30.000000000 -0400 4340 +++ gcc-4.2.2/gcc/config/score/score.c 2007-10-18 02:24:34.000000000 -0400 4341 @@ -22,7 +22,6 @@ 4342 #include "system.h" 4343 #include "coretypes.h" 4344 #include "tm.h" 4345 -#include <signal.h> 4346 #include "rtl.h" 4347 #include "regs.h" 4348 #include "hard-reg-set.h" 4349 @@ -48,57 +47,43 @@ 4350 #include "target-def.h" 4351 #include "integrate.h" 4352 #include "langhooks.h" 4353 -#include "cfglayout.h" 4354 -#include "score-mdaux.h" 4355 - 4356 -#define GR_REG_CLASS_P(C) ((C) == G16_REGS || (C) == G32_REGS) 4357 -#define SP_REG_CLASS_P(C) \ 4358 - ((C) == CN_REG || (C) == LC_REG || (C) == SC_REG || (C) == SP_REGS) 4359 -#define CP_REG_CLASS_P(C) \ 4360 - ((C) == CP1_REGS || (C) == CP2_REGS || (C) == CP3_REGS || (C) == CPA_REGS) 4361 -#define CE_REG_CLASS_P(C) \ 4362 - ((C) == HI_REG || (C) == LO_REG || (C) == CE_REGS) 4363 - 4364 -static int score_arg_partial_bytes (const CUMULATIVE_ARGS *, 4365 - enum machine_mode, tree, int); 4366 - 4367 -static int score_symbol_insns (enum score_symbol_type); 4368 - 4369 -static int score_address_insns (rtx, enum machine_mode); 4370 - 4371 -static bool score_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *); 4372 - 4373 -static int score_address_cost (rtx); 4374 +#include "score7.h" 4375 +#include "score3.h" 4376 4377 #undef TARGET_ASM_FILE_START 4378 -#define TARGET_ASM_FILE_START th_asm_file_start 4379 +#define TARGET_ASM_FILE_START score_asm_file_start 4380 4381 #undef TARGET_ASM_FILE_END 4382 -#define TARGET_ASM_FILE_END th_asm_file_end 4383 +#define TARGET_ASM_FILE_END score_asm_file_end 4384 4385 #undef TARGET_ASM_FUNCTION_PROLOGUE 4386 -#define TARGET_ASM_FUNCTION_PROLOGUE th_function_prologue 4387 +#define TARGET_ASM_FUNCTION_PROLOGUE score_function_prologue 4388 4389 #undef TARGET_ASM_FUNCTION_EPILOGUE 4390 -#define TARGET_ASM_FUNCTION_EPILOGUE th_function_epilogue 4391 +#define TARGET_ASM_FUNCTION_EPILOGUE score_function_epilogue 4392 + 4393 +#undef TARGET_DEFAULT_TARGET_FLAGS 4394 +#define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT 4395 +#undef TARGET_HANDLE_OPTION 4396 +#define TARGET_HANDLE_OPTION score_handle_option 4397 4398 #undef TARGET_SCHED_ISSUE_RATE 4399 -#define TARGET_SCHED_ISSUE_RATE th_issue_rate 4400 +#define TARGET_SCHED_ISSUE_RATE score_issue_rate 4401 4402 #undef TARGET_ASM_SELECT_RTX_SECTION 4403 -#define TARGET_ASM_SELECT_RTX_SECTION th_select_rtx_section 4404 +#define TARGET_ASM_SELECT_RTX_SECTION score_select_rtx_section 4405 4406 #undef TARGET_IN_SMALL_DATA_P 4407 -#define TARGET_IN_SMALL_DATA_P th_in_small_data_p 4408 +#define TARGET_IN_SMALL_DATA_P score_in_small_data_p 4409 4410 #undef TARGET_FUNCTION_OK_FOR_SIBCALL 4411 -#define TARGET_FUNCTION_OK_FOR_SIBCALL th_function_ok_for_sibcall 4412 +#define TARGET_FUNCTION_OK_FOR_SIBCALL score_function_ok_for_sibcall 4413 4414 #undef TARGET_STRICT_ARGUMENT_NAMING 4415 -#define TARGET_STRICT_ARGUMENT_NAMING th_strict_argument_naming 4416 +#define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true 4417 4418 #undef TARGET_ASM_OUTPUT_MI_THUNK 4419 -#define TARGET_ASM_OUTPUT_MI_THUNK th_output_mi_thunk 4420 +#define TARGET_ASM_OUTPUT_MI_THUNK score_output_mi_thunk 4421 4422 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK 4423 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true 4424 @@ -130,8 +115,11 @@ 4425 #undef TARGET_ADDRESS_COST 4426 #define TARGET_ADDRESS_COST score_address_cost 4427 4428 -#undef TARGET_DEFAULT_TARGET_FLAGS 4429 -#define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT 4430 +struct extern_list *extern_head = 0; 4431 +rtx cmp_op0, cmp_op1; 4432 + 4433 +/* default 0 = NO_REGS */ 4434 +enum reg_class score_char_to_class[256]; 4435 4436 /* Implement TARGET_RETURN_IN_MEMORY. In S+core, 4437 small structures are returned in a register. 4438 @@ -139,9 +127,12 @@ 4439 static bool 4440 score_return_in_memory (tree type, tree fndecl ATTRIBUTE_UNUSED) 4441 { 4442 - return ((TYPE_MODE (type) == BLKmode) 4443 - || (int_size_in_bytes (type) > 2 * UNITS_PER_WORD) 4444 - || (int_size_in_bytes (type) == -1)); 4445 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 4446 + return score7_return_in_memory (type, fndecl); 4447 + else if (TARGET_SCORE3) 4448 + return score3_return_in_memory (type, fndecl); 4449 + 4450 + gcc_unreachable (); 4451 } 4452 4453 /* Return nonzero when an argument must be passed by reference. */ 4454 @@ -154,308 +145,116 @@ 4455 return targetm.calls.must_pass_in_stack (mode, type); 4456 } 4457 4458 -/* Return a legitimate address for REG + OFFSET. */ 4459 -static rtx 4460 -score_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset) 4461 -{ 4462 - if (!IMM_IN_RANGE (offset, 15, 1)) 4463 - { 4464 - reg = expand_simple_binop (GET_MODE (reg), PLUS, 4465 - gen_int_mode (offset & 0xffffc000, 4466 - GET_MODE (reg)), 4467 - reg, NULL, 0, OPTAB_WIDEN); 4468 - offset &= 0x3fff; 4469 - } 4470 - 4471 - return plus_constant (reg, offset); 4472 -} 4473 - 4474 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text 4475 in order to avoid duplicating too much logic from elsewhere. */ 4476 static void 4477 -th_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, 4478 - HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, 4479 - tree function) 4480 -{ 4481 - rtx this, temp1, temp2, insn, fnaddr; 4482 - 4483 - /* Pretend to be a post-reload pass while generating rtl. */ 4484 - no_new_pseudos = 1; 4485 - reload_completed = 1; 4486 - reset_block_changes (); 4487 - 4488 - /* We need two temporary registers in some cases. */ 4489 - temp1 = gen_rtx_REG (Pmode, 8); 4490 - temp2 = gen_rtx_REG (Pmode, 9); 4491 - 4492 - /* Find out which register contains the "this" pointer. */ 4493 - if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) 4494 - this = gen_rtx_REG (Pmode, ARG_REG_FIRST + 1); 4495 - else 4496 - this = gen_rtx_REG (Pmode, ARG_REG_FIRST); 4497 - 4498 - /* Add DELTA to THIS. */ 4499 - if (delta != 0) 4500 - { 4501 - rtx offset = GEN_INT (delta); 4502 - if (!CONST_OK_FOR_LETTER_P (delta, 'L')) 4503 - { 4504 - emit_move_insn (temp1, offset); 4505 - offset = temp1; 4506 - } 4507 - emit_insn (gen_add3_insn (this, this, offset)); 4508 - } 4509 - 4510 - /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */ 4511 - if (vcall_offset != 0) 4512 - { 4513 - rtx addr; 4514 - 4515 - /* Set TEMP1 to *THIS. */ 4516 - emit_move_insn (temp1, gen_rtx_MEM (Pmode, this)); 4517 - 4518 - /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */ 4519 - addr = score_add_offset (temp2, temp1, vcall_offset); 4520 - 4521 - /* Load the offset and add it to THIS. */ 4522 - emit_move_insn (temp1, gen_rtx_MEM (Pmode, addr)); 4523 - emit_insn (gen_add3_insn (this, this, temp1)); 4524 - } 4525 - 4526 - /* Jump to the target function. */ 4527 - fnaddr = XEXP (DECL_RTL (function), 0); 4528 - insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx)); 4529 - SIBLING_CALL_P (insn) = 1; 4530 - 4531 - /* Run just enough of rest_of_compilation. This sequence was 4532 - "borrowed" from alpha.c. */ 4533 - insn = get_insns (); 4534 - insn_locators_initialize (); 4535 - split_all_insns_noflow (); 4536 - shorten_branches (insn); 4537 - final_start_function (insn, file, 1); 4538 - final (insn, file, 1); 4539 - final_end_function (); 4540 - 4541 - /* Clean up the vars set above. Note that final_end_function resets 4542 - the global pointer for us. */ 4543 - reload_completed = 0; 4544 - no_new_pseudos = 0; 4545 -} 4546 - 4547 -/* Implement TARGET_STRICT_ARGUMENT_NAMING. */ 4548 -static bool 4549 -th_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED) 4550 -{ 4551 - return true; 4552 +score_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, 4553 + HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, 4554 + tree function) 4555 +{ 4556 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 4557 + return score7_output_mi_thunk (file, thunk_fndecl, delta, 4558 + vcall_offset, function); 4559 + else if (TARGET_SCORE3) 4560 + return score3_output_mi_thunk (file, thunk_fndecl, delta, 4561 + vcall_offset, function); 4562 + gcc_unreachable (); 4563 } 4564 4565 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */ 4566 static bool 4567 -th_function_ok_for_sibcall (ATTRIBUTE_UNUSED tree decl, 4568 - ATTRIBUTE_UNUSED tree exp) 4569 +score_function_ok_for_sibcall (ATTRIBUTE_UNUSED tree decl, 4570 + ATTRIBUTE_UNUSED tree exp) 4571 { 4572 return true; 4573 } 4574 4575 -struct score_arg_info 4576 -{ 4577 - /* The argument's size, in bytes. */ 4578 - unsigned int num_bytes; 4579 - 4580 - /* The number of words passed in registers, rounded up. */ 4581 - unsigned int reg_words; 4582 - 4583 - /* The offset of the first register from GP_ARG_FIRST or FP_ARG_FIRST, 4584 - or ARG_REG_NUM if the argument is passed entirely on the stack. */ 4585 - unsigned int reg_offset; 4586 - 4587 - /* The number of words that must be passed on the stack, rounded up. */ 4588 - unsigned int stack_words; 4589 - 4590 - /* The offset from the start of the stack overflow area of the argument's 4591 - first stack word. Only meaningful when STACK_WORDS is nonzero. */ 4592 - unsigned int stack_offset; 4593 -}; 4594 - 4595 -/* Fill INFO with information about a single argument. CUM is the 4596 - cumulative state for earlier arguments. MODE is the mode of this 4597 - argument and TYPE is its type (if known). NAMED is true if this 4598 - is a named (fixed) argument rather than a variable one. */ 4599 -static void 4600 -classify_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode, 4601 - tree type, int named, struct score_arg_info *info) 4602 -{ 4603 - int even_reg_p; 4604 - unsigned int num_words, max_regs; 4605 - 4606 - even_reg_p = 0; 4607 - if (GET_MODE_CLASS (mode) == MODE_INT 4608 - || GET_MODE_CLASS (mode) == MODE_FLOAT) 4609 - even_reg_p = (GET_MODE_SIZE (mode) > UNITS_PER_WORD); 4610 - else 4611 - if (type != NULL_TREE && TYPE_ALIGN (type) > BITS_PER_WORD && named) 4612 - even_reg_p = 1; 4613 - 4614 - if (TARGET_MUST_PASS_IN_STACK (mode, type)) 4615 - info->reg_offset = ARG_REG_NUM; 4616 - else 4617 - { 4618 - info->reg_offset = cum->num_gprs; 4619 - if (even_reg_p) 4620 - info->reg_offset += info->reg_offset & 1; 4621 - } 4622 - 4623 - if (mode == BLKmode) 4624 - info->num_bytes = int_size_in_bytes (type); 4625 - else 4626 - info->num_bytes = GET_MODE_SIZE (mode); 4627 - 4628 - num_words = (info->num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD; 4629 - max_regs = ARG_REG_NUM - info->reg_offset; 4630 - 4631 - /* Partition the argument between registers and stack. */ 4632 - info->reg_words = MIN (num_words, max_regs); 4633 - info->stack_words = num_words - info->reg_words; 4634 - 4635 - /* The alignment applied to registers is also applied to stack arguments. */ 4636 - if (info->stack_words) 4637 - { 4638 - info->stack_offset = cum->stack_words; 4639 - if (even_reg_p) 4640 - info->stack_offset += info->stack_offset & 1; 4641 - } 4642 -} 4643 - 4644 /* Set up the stack and frame (if desired) for the function. */ 4645 static void 4646 -th_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) 4647 +score_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) 4648 { 4649 - const char *fnname; 4650 - struct score_frame_info *f = mda_cached_frame (); 4651 - HOST_WIDE_INT tsize = f->total_size; 4652 - 4653 - fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); 4654 - if (!flag_inhibit_size_directive) 4655 - { 4656 - fputs ("\t.ent\t", file); 4657 - assemble_name (file, fnname); 4658 - fputs ("\n", file); 4659 - } 4660 - assemble_name (file, fnname); 4661 - fputs (":\n", file); 4662 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 4663 + return score7_function_prologue (file, size); 4664 + else if (TARGET_SCORE3) 4665 + return score3_function_prologue (file, size); 4666 4667 - if (!flag_inhibit_size_directive) 4668 - { 4669 - fprintf (file, 4670 - "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s, %d\t\t" 4671 - "# vars= " HOST_WIDE_INT_PRINT_DEC ", regs= %d" 4672 - ", args= " HOST_WIDE_INT_PRINT_DEC 4673 - ", gp= " HOST_WIDE_INT_PRINT_DEC "\n", 4674 - (reg_names[(frame_pointer_needed) 4675 - ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]), 4676 - tsize, 4677 - reg_names[RA_REGNUM], 4678 - current_function_is_leaf ? 1 : 0, 4679 - f->var_size, 4680 - f->num_gp, 4681 - f->args_size, 4682 - f->cprestore_size); 4683 - 4684 - fprintf(file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n", 4685 - f->mask, 4686 - (f->gp_sp_offset - f->total_size)); 4687 - } 4688 + gcc_unreachable (); 4689 } 4690 4691 /* Do any necessary cleanup after a function to restore stack, frame, 4692 and regs. */ 4693 static void 4694 -th_function_epilogue (FILE *file, 4695 - HOST_WIDE_INT size ATTRIBUTE_UNUSED) 4696 +score_function_epilogue (FILE *file, 4697 + HOST_WIDE_INT size ATTRIBUTE_UNUSED) 4698 { 4699 - if (!flag_inhibit_size_directive) 4700 - { 4701 - const char *fnname; 4702 - fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); 4703 - fputs ("\t.end\t", file); 4704 - assemble_name (file, fnname); 4705 - fputs ("\n", file); 4706 - } 4707 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 4708 + return score7_function_epilogue (file, size); 4709 + else if (TARGET_SCORE3) 4710 + return score3_function_epilogue (file, size); 4711 + 4712 + gcc_unreachable (); 4713 } 4714 4715 /* Implement TARGET_SCHED_ISSUE_RATE. */ 4716 static int 4717 -th_issue_rate (void) 4718 +score_issue_rate (void) 4719 { 4720 return 1; 4721 } 4722 4723 -/* Returns true if X contains a SYMBOL_REF. */ 4724 -static bool 4725 -symbolic_expression_p (rtx x) 4726 -{ 4727 - if (GET_CODE (x) == SYMBOL_REF) 4728 - return true; 4729 - 4730 - if (GET_CODE (x) == CONST) 4731 - return symbolic_expression_p (XEXP (x, 0)); 4732 - 4733 - if (UNARY_P (x)) 4734 - return symbolic_expression_p (XEXP (x, 0)); 4735 - 4736 - if (ARITHMETIC_P (x)) 4737 - return (symbolic_expression_p (XEXP (x, 0)) 4738 - || symbolic_expression_p (XEXP (x, 1))); 4739 - 4740 - return false; 4741 -} 4742 - 4743 /* Choose the section to use for the constant rtx expression X that has 4744 mode MODE. */ 4745 static section * 4746 -th_select_rtx_section (enum machine_mode mode, rtx x, 4747 - unsigned HOST_WIDE_INT align) 4748 +score_select_rtx_section (enum machine_mode mode, rtx x, 4749 + unsigned HOST_WIDE_INT align) 4750 { 4751 - if (GET_MODE_SIZE (mode) <= SCORE_SDATA_MAX) 4752 - return get_named_section (0, ".sdata", 0); 4753 - else if (flag_pic && symbolic_expression_p (x)) 4754 - return get_named_section (0, ".data.rel.ro", 3); 4755 - else 4756 - return mergeable_constant_section (mode, align, 0); 4757 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 4758 + return score7_select_rtx_section (mode, x, align); 4759 + else if (TARGET_SCORE3) 4760 + return score3_select_rtx_section (mode, x, align); 4761 + 4762 + gcc_unreachable (); 4763 } 4764 4765 /* Implement TARGET_IN_SMALL_DATA_P. */ 4766 static bool 4767 -th_in_small_data_p (tree decl) 4768 +score_in_small_data_p (tree decl) 4769 { 4770 - HOST_WIDE_INT size; 4771 - 4772 - if (TREE_CODE (decl) == STRING_CST 4773 - || TREE_CODE (decl) == FUNCTION_DECL) 4774 - return false; 4775 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 4776 + return score7_in_small_data_p (decl); 4777 + else if (TARGET_SCORE3) 4778 + return score3_in_small_data_p (decl); 4779 4780 - if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0) 4781 - { 4782 - const char *name; 4783 - name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl)); 4784 - if (strcmp (name, ".sdata") != 0 4785 - && strcmp (name, ".sbss") != 0) 4786 - return true; 4787 - if (!DECL_EXTERNAL (decl)) 4788 - return false; 4789 - } 4790 - size = int_size_in_bytes (TREE_TYPE (decl)); 4791 - return (size > 0 && size <= SCORE_SDATA_MAX); 4792 + gcc_unreachable (); 4793 } 4794 4795 /* Implement TARGET_ASM_FILE_START. */ 4796 static void 4797 -th_asm_file_start (void) 4798 +score_asm_file_start (void) 4799 { 4800 + if (TARGET_SCORE5) 4801 + fprintf (asm_out_file, "# Sunplus S+core5 %s rev=%s\n", 4802 + TARGET_LITTLE_ENDIAN ? "el" : "eb", SCORE_GCC_VERSION); 4803 + else if (TARGET_SCORE5U) 4804 + fprintf (asm_out_file, "# Sunplus S+core5u %s rev=%s\n", 4805 + TARGET_LITTLE_ENDIAN ? "el" : "eb", SCORE_GCC_VERSION); 4806 + else if (TARGET_SCORE7D) 4807 + fprintf (asm_out_file, "# Sunplus S+core7d %s rev=%s\n", 4808 + TARGET_LITTLE_ENDIAN ? "el" : "eb", SCORE_GCC_VERSION); 4809 + else if (TARGET_SCORE7) 4810 + fprintf (asm_out_file, "# Sunplus S+core7 %s rev=%s\n", 4811 + TARGET_LITTLE_ENDIAN ? "el" : "eb", SCORE_GCC_VERSION); 4812 + else if (TARGET_SCORE3D) 4813 + fprintf (asm_out_file, "# Sunplus S+core3d %s rev=%s\n", 4814 + TARGET_LITTLE_ENDIAN ? "el" : "eb", SCORE_GCC_VERSION); 4815 + else if (TARGET_SCORE3) 4816 + fprintf (asm_out_file, "# Sunplus S+core3 %s rev=%s\n", 4817 + TARGET_LITTLE_ENDIAN ? "el" : "eb", SCORE_GCC_VERSION); 4818 + else 4819 + fprintf (asm_out_file, "# Sunplus S+core unknown %s rev=%s\n", 4820 + TARGET_LITTLE_ENDIAN ? "el" : "eb", SCORE_GCC_VERSION); 4821 + 4822 default_file_start (); 4823 - fprintf (asm_out_file, ASM_COMMENT_START 4824 - "GCC for S+core %s \n", SCORE_GCC_VERSION); 4825 4826 if (flag_pic) 4827 fprintf (asm_out_file, "\t.set pic\n"); 4828 @@ -463,104 +262,116 @@ 4829 4830 /* Implement TARGET_ASM_FILE_END. When using assembler macros, emit 4831 .externs for any small-data variables that turned out to be external. */ 4832 -struct extern_list *extern_head = 0; 4833 - 4834 static void 4835 -th_asm_file_end (void) 4836 +score_asm_file_end (void) 4837 { 4838 - tree name_tree; 4839 - struct extern_list *p; 4840 - if (extern_head) 4841 - { 4842 - fputs ("\n", asm_out_file); 4843 - for (p = extern_head; p != 0; p = p->next) 4844 - { 4845 - name_tree = get_identifier (p->name); 4846 - if (!TREE_ASM_WRITTEN (name_tree) 4847 - && TREE_SYMBOL_REFERENCED (name_tree)) 4848 - { 4849 - TREE_ASM_WRITTEN (name_tree) = 1; 4850 - fputs ("\t.extern\t", asm_out_file); 4851 - assemble_name (asm_out_file, p->name); 4852 - fprintf (asm_out_file, ", %d\n", p->size); 4853 - } 4854 - } 4855 - } 4856 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 4857 + return score7_asm_file_end (); 4858 + else if (TARGET_SCORE3) 4859 + return score3_asm_file_end (); 4860 + 4861 + gcc_unreachable (); 4862 } 4863 4864 -static unsigned int sdata_max; 4865 +#define MASK_ALL_CPU_BITS \ 4866 + (MASK_SCORE5 | MASK_SCORE5U | MASK_SCORE7 | MASK_SCORE7D \ 4867 + | MASK_SCORE3 | MASK_SCORE3D) 4868 4869 -int 4870 -score_sdata_max (void) 4871 +/* Implement TARGET_HANDLE_OPTION. */ 4872 +static bool 4873 +score_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED) 4874 { 4875 - return sdata_max; 4876 -} 4877 + switch (code) 4878 + { 4879 + case OPT_mscore7d: 4880 + target_flags &= ~(MASK_ALL_CPU_BITS); 4881 + target_flags |= MASK_SCORE7 | MASK_SCORE7D; 4882 + return true; 4883 4884 -/* default 0 = NO_REGS */ 4885 -enum reg_class score_char_to_class[256]; 4886 + case OPT_mscore3d: 4887 + target_flags &= ~(MASK_ALL_CPU_BITS); 4888 + target_flags |= MASK_SCORE3 | MASK_SCORE3D; 4889 + return true; 4890 + 4891 + case OPT_march_: 4892 + if (strcmp (arg, "score5") == 0) 4893 + { 4894 + target_flags &= ~(MASK_ALL_CPU_BITS); 4895 + target_flags |= MASK_SCORE5; 4896 + return true; 4897 + } 4898 + else if (strcmp (arg, "score5u") == 0) 4899 + { 4900 + target_flags &= ~(MASK_ALL_CPU_BITS); 4901 + target_flags |= MASK_SCORE5U; 4902 + return true; 4903 + } 4904 + else if (strcmp (arg, "score7") == 0) 4905 + { 4906 + target_flags &= ~(MASK_ALL_CPU_BITS); 4907 + target_flags |= MASK_SCORE7; 4908 + return true; 4909 + } 4910 + else if (strcmp (arg, "score7d") == 0) 4911 + { 4912 + target_flags &= ~(MASK_ALL_CPU_BITS); 4913 + target_flags |= MASK_SCORE7 | MASK_SCORE7D; 4914 + return true; 4915 + } 4916 + else if (strcmp (arg, "score3") == 0) 4917 + { 4918 + target_flags &= ~(MASK_ALL_CPU_BITS); 4919 + target_flags |= MASK_SCORE3; 4920 + return true; 4921 + } 4922 + else if (strcmp (arg, "score3d") == 0) 4923 + { 4924 + target_flags &= ~(MASK_ALL_CPU_BITS); 4925 + target_flags |= MASK_SCORE3 | MASK_SCORE3D; 4926 + return true; 4927 + } 4928 + else 4929 + return false; 4930 + 4931 + default: 4932 + return true; 4933 + } 4934 +} 4935 4936 /* Implement OVERRIDE_OPTIONS macro. */ 4937 void 4938 score_override_options (void) 4939 { 4940 - flag_pic = false; 4941 - if (!flag_pic) 4942 - sdata_max = g_switch_set ? g_switch_value : DEFAULT_SDATA_MAX; 4943 - else 4944 - { 4945 - sdata_max = 0; 4946 - if (g_switch_set && (g_switch_value != 0)) 4947 - warning (0, "-fPIC and -G are incompatible"); 4948 - } 4949 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 4950 + return score7_override_options (); 4951 + else if (TARGET_SCORE3) 4952 + return score3_override_options (); 4953 4954 - score_char_to_class['d'] = G32_REGS; 4955 - score_char_to_class['e'] = G16_REGS; 4956 - score_char_to_class['t'] = T32_REGS; 4957 - 4958 - score_char_to_class['h'] = HI_REG; 4959 - score_char_to_class['l'] = LO_REG; 4960 - score_char_to_class['x'] = CE_REGS; 4961 - 4962 - score_char_to_class['q'] = CN_REG; 4963 - score_char_to_class['y'] = LC_REG; 4964 - score_char_to_class['z'] = SC_REG; 4965 - score_char_to_class['a'] = SP_REGS; 4966 - 4967 - score_char_to_class['c'] = CR_REGS; 4968 - 4969 - score_char_to_class['b'] = CP1_REGS; 4970 - score_char_to_class['f'] = CP2_REGS; 4971 - score_char_to_class['i'] = CP3_REGS; 4972 - score_char_to_class['j'] = CPA_REGS; 4973 + return score7_override_options (); 4974 } 4975 4976 /* Implement REGNO_REG_CLASS macro. */ 4977 int 4978 score_reg_class (int regno) 4979 { 4980 - int c; 4981 - gcc_assert (regno >= 0 && regno < FIRST_PSEUDO_REGISTER); 4982 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 4983 + return score7_reg_class (regno); 4984 + else if (TARGET_SCORE3) 4985 + return score3_reg_class (regno); 4986 4987 - if (regno == FRAME_POINTER_REGNUM 4988 - || regno == ARG_POINTER_REGNUM) 4989 - return ALL_REGS; 4990 - 4991 - for (c = 0; c < N_REG_CLASSES; c++) 4992 - if (TEST_HARD_REG_BIT (reg_class_contents[c], regno)) 4993 - return c; 4994 - 4995 - return NO_REGS; 4996 + gcc_unreachable (); 4997 } 4998 4999 /* Implement PREFERRED_RELOAD_CLASS macro. */ 5000 enum reg_class 5001 score_preferred_reload_class (rtx x ATTRIBUTE_UNUSED, enum reg_class class) 5002 { 5003 - if (reg_class_subset_p (G16_REGS, class)) 5004 - return G16_REGS; 5005 - if (reg_class_subset_p (G32_REGS, class)) 5006 - return G32_REGS; 5007 - return class; 5008 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 5009 + return score7_preferred_reload_class (x, class); 5010 + else if (TARGET_SCORE3) 5011 + return score3_preferred_reload_class (x, class); 5012 + 5013 + gcc_unreachable (); 5014 } 5015 5016 /* Implement SECONDARY_INPUT_RELOAD_CLASS 5017 @@ -570,50 +381,36 @@ 5018 enum machine_mode mode ATTRIBUTE_UNUSED, 5019 rtx x) 5020 { 5021 - int regno = -1; 5022 - if (GET_CODE (x) == REG || GET_CODE(x) == SUBREG) 5023 - regno = true_regnum (x); 5024 - 5025 - if (!GR_REG_CLASS_P (class)) 5026 - return GP_REG_P (regno) ? NO_REGS : G32_REGS; 5027 - return NO_REGS; 5028 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 5029 + return score7_secondary_reload_class (class, mode, x); 5030 + else if (TARGET_SCORE3) 5031 + return score3_secondary_reload_class (class, mode, x); 5032 + 5033 + gcc_unreachable (); 5034 } 5035 5036 /* Implement CONST_OK_FOR_LETTER_P macro. */ 5037 -/* imm constraints 5038 - I imm16 << 16 5039 - J uimm5 5040 - K uimm16 5041 - L simm16 5042 - M uimm14 5043 - N simm14 */ 5044 int 5045 score_const_ok_for_letter_p (HOST_WIDE_INT value, char c) 5046 { 5047 - switch (c) 5048 - { 5049 - case 'I': return ((value & 0xffff) == 0); 5050 - case 'J': return IMM_IN_RANGE (value, 5, 0); 5051 - case 'K': return IMM_IN_RANGE (value, 16, 0); 5052 - case 'L': return IMM_IN_RANGE (value, 16, 1); 5053 - case 'M': return IMM_IN_RANGE (value, 14, 0); 5054 - case 'N': return IMM_IN_RANGE (value, 14, 1); 5055 - default : return 0; 5056 - } 5057 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 5058 + return score7_const_ok_for_letter_p (value, c); 5059 + else if (TARGET_SCORE3) 5060 + return score3_const_ok_for_letter_p (value, c); 5061 + 5062 + gcc_unreachable (); 5063 } 5064 5065 /* Implement EXTRA_CONSTRAINT macro. */ 5066 -/* Z symbol_ref */ 5067 int 5068 score_extra_constraint (rtx op, char c) 5069 { 5070 - switch (c) 5071 - { 5072 - case 'Z': 5073 - return GET_CODE (op) == SYMBOL_REF; 5074 - default: 5075 - gcc_unreachable (); 5076 - } 5077 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 5078 + return score7_extra_constraint (op, c); 5079 + else if (TARGET_SCORE3) 5080 + return score3_extra_constraint (op, c); 5081 + 5082 + gcc_unreachable (); 5083 } 5084 5085 /* Return truth value on whether or not a given hard register 5086 @@ -621,23 +418,12 @@ 5087 int 5088 score_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode) 5089 { 5090 - int size = GET_MODE_SIZE (mode); 5091 - enum mode_class class = GET_MODE_CLASS (mode); 5092 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 5093 + return score7_hard_regno_mode_ok (regno, mode); 5094 + else if (TARGET_SCORE3) 5095 + return score3_hard_regno_mode_ok (regno, mode); 5096 5097 - if (class == MODE_CC) 5098 - return regno == CC_REGNUM; 5099 - else if (regno == FRAME_POINTER_REGNUM 5100 - || regno == ARG_POINTER_REGNUM) 5101 - return class == MODE_INT; 5102 - else if (GP_REG_P (regno)) 5103 - /* ((regno <= (GP_REG_LAST- HARD_REGNO_NREGS (dummy, mode)) + 1) */ 5104 - return !(regno & 1) || (size <= UNITS_PER_WORD); 5105 - else if (CE_REG_P (regno)) 5106 - return (class == MODE_INT 5107 - && ((size <= UNITS_PER_WORD) 5108 - || (regno == CE_REG_FIRST && size == 2 * UNITS_PER_WORD))); 5109 - else 5110 - return (class == MODE_INT) && (size <= UNITS_PER_WORD); 5111 + gcc_unreachable (); 5112 } 5113 5114 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame 5115 @@ -647,16 +433,12 @@ 5116 score_initial_elimination_offset (int from, 5117 int to ATTRIBUTE_UNUSED) 5118 { 5119 - struct score_frame_info *f = mda_compute_frame_size (get_frame_size ()); 5120 - switch (from) 5121 - { 5122 - case ARG_POINTER_REGNUM: 5123 - return f->total_size; 5124 - case FRAME_POINTER_REGNUM: 5125 - return 0; 5126 - default: 5127 - gcc_unreachable (); 5128 - } 5129 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 5130 + return score7_initial_elimination_offset (from, to); 5131 + else if (TARGET_SCORE3) 5132 + return score3_initial_elimination_offset (from, to); 5133 + 5134 + gcc_unreachable (); 5135 } 5136 5137 /* Argument support functions. */ 5138 @@ -675,22 +457,25 @@ 5139 score_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode, 5140 tree type, int named) 5141 { 5142 - struct score_arg_info info; 5143 - classify_arg (cum, mode, type, named, &info); 5144 - cum->num_gprs = info.reg_offset + info.reg_words; 5145 - if (info.stack_words > 0) 5146 - cum->stack_words = info.stack_offset + info.stack_words; 5147 - cum->arg_number++; 5148 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 5149 + return score7_function_arg_advance (cum, mode, type, named); 5150 + else if (TARGET_SCORE3) 5151 + return score3_function_arg_advance (cum, mode, type, named); 5152 + 5153 + gcc_unreachable (); 5154 } 5155 5156 /* Implement TARGET_ARG_PARTIAL_BYTES macro. */ 5157 -static int 5158 -score_arg_partial_bytes (const CUMULATIVE_ARGS *cum, 5159 - enum machine_mode mode, tree type, int named) 5160 +int 5161 +score_arg_partial_bytes (CUMULATIVE_ARGS *cum, 5162 + enum machine_mode mode, tree type, bool named) 5163 { 5164 - struct score_arg_info info; 5165 - classify_arg (cum, mode, type, named, &info); 5166 - return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0; 5167 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 5168 + return score7_arg_partial_bytes (cum, mode, type, named); 5169 + else if (TARGET_SCORE3) 5170 + return score3_arg_partial_bytes (cum, mode, type, named); 5171 + 5172 + gcc_unreachable (); 5173 } 5174 5175 /* Implement FUNCTION_ARG macro. */ 5176 @@ -698,32 +483,12 @@ 5177 score_function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode, 5178 tree type, int named) 5179 { 5180 - struct score_arg_info info; 5181 - 5182 - if (mode == VOIDmode || !named) 5183 - return 0; 5184 - 5185 - classify_arg (cum, mode, type, named, &info); 5186 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 5187 + return score7_function_arg (cum, mode, type, named); 5188 + else if (TARGET_SCORE3) 5189 + return score3_function_arg (cum, mode, type, named); 5190 5191 - if (info.reg_offset == ARG_REG_NUM) 5192 - return 0; 5193 - 5194 - if (!info.stack_words) 5195 - return gen_rtx_REG (mode, ARG_REG_FIRST + info.reg_offset); 5196 - else 5197 - { 5198 - rtx ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words)); 5199 - unsigned int i, part_offset = 0; 5200 - for (i = 0; i < info.reg_words; i++) 5201 - { 5202 - rtx reg; 5203 - reg = gen_rtx_REG (SImode, ARG_REG_FIRST + info.reg_offset + i); 5204 - XVECEXP (ret, 0, i) = gen_rtx_EXPR_LIST (SImode, reg, 5205 - GEN_INT (part_offset)); 5206 - part_offset += UNITS_PER_WORD; 5207 - } 5208 - return ret; 5209 - } 5210 + gcc_unreachable (); 5211 } 5212 5213 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls, 5214 @@ -733,85 +498,48 @@ 5215 score_function_value (tree valtype, tree func ATTRIBUTE_UNUSED, 5216 enum machine_mode mode) 5217 { 5218 - if (valtype) 5219 - { 5220 - int unsignedp; 5221 - mode = TYPE_MODE (valtype); 5222 - unsignedp = TYPE_UNSIGNED (valtype); 5223 - mode = promote_mode (valtype, mode, &unsignedp, 1); 5224 - } 5225 - return gen_rtx_REG (mode, RT_REGNUM); 5226 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 5227 + return score7_function_value (valtype, func, mode); 5228 + else if (TARGET_SCORE3) 5229 + return score3_function_value (valtype, func, mode); 5230 + 5231 + gcc_unreachable (); 5232 } 5233 5234 /* Implement INITIALIZE_TRAMPOLINE macro. */ 5235 void 5236 score_initialize_trampoline (rtx ADDR, rtx FUNC, rtx CHAIN) 5237 { 5238 -#define FFCACHE "_flush_cache" 5239 -#define CODE_SIZE (TRAMPOLINE_INSNS * UNITS_PER_WORD) 5240 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 5241 + return score7_initialize_trampoline (ADDR, FUNC, CHAIN); 5242 + else if (TARGET_SCORE3) 5243 + return score3_initialize_trampoline (ADDR, FUNC, CHAIN); 5244 5245 - rtx pfunc, pchain; 5246 - 5247 - pfunc = plus_constant (ADDR, CODE_SIZE); 5248 - pchain = plus_constant (ADDR, CODE_SIZE + GET_MODE_SIZE (SImode)); 5249 - 5250 - emit_move_insn (gen_rtx_MEM (SImode, pfunc), FUNC); 5251 - emit_move_insn (gen_rtx_MEM (SImode, pchain), CHAIN); 5252 - emit_library_call (gen_rtx_SYMBOL_REF (Pmode, FFCACHE), 5253 - 0, VOIDmode, 2, 5254 - ADDR, Pmode, 5255 - GEN_INT (TRAMPOLINE_SIZE), SImode); 5256 -#undef FFCACHE 5257 -#undef CODE_SIZE 5258 + gcc_unreachable (); 5259 } 5260 5261 /* This function is used to implement REG_MODE_OK_FOR_BASE_P macro. */ 5262 int 5263 score_regno_mode_ok_for_base_p (int regno, int strict) 5264 { 5265 - if (regno >= FIRST_PSEUDO_REGISTER) 5266 - { 5267 - if (!strict) 5268 - return 1; 5269 - regno = reg_renumber[regno]; 5270 - } 5271 - if (regno == ARG_POINTER_REGNUM 5272 - || regno == FRAME_POINTER_REGNUM) 5273 - return 1; 5274 - return GP_REG_P (regno); 5275 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 5276 + return score7_regno_mode_ok_for_base_p (regno, strict); 5277 + else if (TARGET_SCORE3) 5278 + return score3_regno_mode_ok_for_base_p (regno, strict); 5279 + 5280 + gcc_unreachable (); 5281 } 5282 5283 /* Implement GO_IF_LEGITIMATE_ADDRESS macro. */ 5284 int 5285 score_address_p (enum machine_mode mode, rtx x, int strict) 5286 { 5287 - struct score_address_info addr; 5288 - 5289 - return mda_classify_address (&addr, mode, x, strict); 5290 -} 5291 - 5292 -/* Copy VALUE to a register and return that register. If new psuedos 5293 - are allowed, copy it into a new register, otherwise use DEST. */ 5294 -static rtx 5295 -score_force_temporary (rtx dest, rtx value) 5296 -{ 5297 - if (!no_new_pseudos) 5298 - return force_reg (Pmode, value); 5299 - else 5300 - { 5301 - emit_move_insn (copy_rtx (dest), value); 5302 - return dest; 5303 - } 5304 -} 5305 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 5306 + return score7_address_p (mode, x, strict); 5307 + else if (TARGET_SCORE3) 5308 + return score3_address_p (mode, x, strict); 5309 5310 -/* Return a LO_SUM expression for ADDR. TEMP is as for score_force_temporary 5311 - and is used to load the high part into a register. */ 5312 -static rtx 5313 -score_split_symbol (rtx temp, rtx addr) 5314 -{ 5315 - rtx high = score_force_temporary (temp, 5316 - gen_rtx_HIGH (Pmode, copy_rtx (addr))); 5317 - return gen_rtx_LO_SUM (Pmode, high, addr); 5318 + gcc_unreachable (); 5319 } 5320 5321 /* This function is used to implement LEGITIMIZE_ADDRESS. If *XLOC can 5322 @@ -820,25 +548,12 @@ 5323 int 5324 score_legitimize_address (rtx *xloc) 5325 { 5326 - enum score_symbol_type symbol_type; 5327 - 5328 - if (mda_symbolic_constant_p (*xloc, &symbol_type) 5329 - && symbol_type == SYMBOL_GENERAL) 5330 - { 5331 - *xloc = score_split_symbol (0, *xloc); 5332 - return 1; 5333 - } 5334 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 5335 + return score7_legitimize_address (xloc); 5336 + else if (TARGET_SCORE3) 5337 + return score3_legitimize_address (xloc); 5338 5339 - if (GET_CODE (*xloc) == PLUS 5340 - && GET_CODE (XEXP (*xloc, 1)) == CONST_INT) 5341 - { 5342 - rtx reg = XEXP (*xloc, 0); 5343 - if (!mda_valid_base_register_p (reg, 0)) 5344 - reg = copy_to_mode_reg (Pmode, reg); 5345 - *xloc = score_add_offset (NULL, reg, INTVAL (XEXP (*xloc, 1))); 5346 - return 1; 5347 - } 5348 - return 0; 5349 + gcc_unreachable (); 5350 } 5351 5352 /* Return a number assessing the cost of moving a register in class 5353 @@ -847,503 +562,633 @@ 5354 score_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED, 5355 enum reg_class from, enum reg_class to) 5356 { 5357 - if (GR_REG_CLASS_P (from)) 5358 - { 5359 - if (GR_REG_CLASS_P (to)) 5360 - return 2; 5361 - else if (SP_REG_CLASS_P (to)) 5362 - return 4; 5363 - else if (CP_REG_CLASS_P (to)) 5364 - return 5; 5365 - else if (CE_REG_CLASS_P (to)) 5366 - return 6; 5367 - } 5368 - if (GR_REG_CLASS_P (to)) 5369 - { 5370 - if (GR_REG_CLASS_P (from)) 5371 - return 2; 5372 - else if (SP_REG_CLASS_P (from)) 5373 - return 4; 5374 - else if (CP_REG_CLASS_P (from)) 5375 - return 5; 5376 - else if (CE_REG_CLASS_P (from)) 5377 - return 6; 5378 - } 5379 - return 12; 5380 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 5381 + return score7_register_move_cost (mode, from, to); 5382 + else if (TARGET_SCORE3) 5383 + return score3_register_move_cost (mode, from, to); 5384 + 5385 + gcc_unreachable (); 5386 } 5387 5388 -/* Return the number of instructions needed to load a symbol of the 5389 - given type into a register. */ 5390 -static int 5391 -score_symbol_insns (enum score_symbol_type type) 5392 +/* Implement TARGET_RTX_COSTS macro. */ 5393 +bool 5394 +score_rtx_costs (rtx x, int code, int outer_code, int *total) 5395 { 5396 - switch (type) 5397 - { 5398 - case SYMBOL_GENERAL: 5399 - return 2; 5400 - 5401 - case SYMBOL_SMALL_DATA: 5402 - return 1; 5403 - } 5404 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 5405 + return score7_rtx_costs (x, code, outer_code, total); 5406 + else if (TARGET_SCORE3) 5407 + return score3_rtx_costs (x, code, outer_code, total); 5408 5409 gcc_unreachable (); 5410 } 5411 5412 -/* Return the number of instructions needed to load or store a value 5413 - of mode MODE at X. Return 0 if X isn't valid for MODE. */ 5414 -static int 5415 -score_address_insns (rtx x, enum machine_mode mode) 5416 +/* Implement TARGET_ADDRESS_COST macro. */ 5417 +int 5418 +score_address_cost (rtx addr) 5419 { 5420 - struct score_address_info addr; 5421 - int factor; 5422 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 5423 + return score7_address_cost (addr); 5424 + else if (TARGET_SCORE3) 5425 + return score3_address_cost (addr); 5426 5427 - if (mode == BLKmode) 5428 - factor = 1; 5429 - else 5430 - factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; 5431 + gcc_unreachable (); 5432 +} 5433 5434 - if (mda_classify_address (&addr, mode, x, false)) 5435 - switch (addr.type) 5436 - { 5437 - case ADD_REG: 5438 - case ADD_CONST_INT: 5439 - return factor; 5440 - 5441 - case ADD_SYMBOLIC: 5442 - return factor * score_symbol_insns (addr.symbol_type); 5443 - } 5444 - return 0; 5445 +/* Implement ASM_OUTPUT_EXTERNAL macro. */ 5446 +int 5447 +score_output_external (FILE *file ATTRIBUTE_UNUSED, 5448 + tree decl, const char *name) 5449 +{ 5450 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 5451 + return score7_output_external (file, decl, name); 5452 + else if (TARGET_SCORE3) 5453 + return score3_output_external (file, decl, name); 5454 + 5455 + gcc_unreachable (); 5456 } 5457 5458 -/* Implement TARGET_RTX_COSTS macro. */ 5459 -static bool 5460 -score_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, 5461 - int *total) 5462 +/* Implement RETURN_ADDR_RTX. Note, we do not support moving 5463 + back to a previous frame. */ 5464 +rtx 5465 +score_return_addr (int count, rtx frame ATTRIBUTE_UNUSED) 5466 { 5467 - enum machine_mode mode = GET_MODE (x); 5468 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 5469 + return score7_return_addr (count, frame); 5470 + else if (TARGET_SCORE3) 5471 + return score3_return_addr (count, frame); 5472 5473 - switch (code) 5474 - { 5475 - case CONST_INT: 5476 - if (outer_code == SET) 5477 - { 5478 - if (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I') 5479 - || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')) 5480 - *total = COSTS_N_INSNS (1); 5481 - else 5482 - *total = COSTS_N_INSNS (2); 5483 - } 5484 - else if (outer_code == PLUS || outer_code == MINUS) 5485 - { 5486 - if (CONST_OK_FOR_LETTER_P (INTVAL (x), 'N')) 5487 - *total = 0; 5488 - else if (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I') 5489 - || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')) 5490 - *total = 1; 5491 - else 5492 - *total = COSTS_N_INSNS (2); 5493 - } 5494 - else if (outer_code == AND || outer_code == IOR) 5495 - { 5496 - if (CONST_OK_FOR_LETTER_P (INTVAL (x), 'M')) 5497 - *total = 0; 5498 - else if (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I') 5499 - || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')) 5500 - *total = 1; 5501 - else 5502 - *total = COSTS_N_INSNS (2); 5503 - } 5504 - else 5505 - { 5506 - *total = 0; 5507 - } 5508 - return true; 5509 + gcc_unreachable (); 5510 +} 5511 5512 - case CONST: 5513 - case SYMBOL_REF: 5514 - case LABEL_REF: 5515 - case CONST_DOUBLE: 5516 - *total = COSTS_N_INSNS (2); 5517 - return true; 5518 +/* Implement PRINT_OPERAND macro. */ 5519 +void 5520 +score_print_operand (FILE *file, rtx op, int c) 5521 +{ 5522 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 5523 + return score7_print_operand (file, op, c); 5524 + else if (TARGET_SCORE3) 5525 + return score3_print_operand (file, op, c); 5526 5527 - case MEM: 5528 - { 5529 - /* If the address is legitimate, return the number of 5530 - instructions it needs, otherwise use the default handling. */ 5531 - int n = score_address_insns (XEXP (x, 0), GET_MODE (x)); 5532 - if (n > 0) 5533 - { 5534 - *total = COSTS_N_INSNS (n + 1); 5535 - return true; 5536 - } 5537 - return false; 5538 - } 5539 + gcc_unreachable (); 5540 +} 5541 5542 - case FFS: 5543 - *total = COSTS_N_INSNS (6); 5544 - return true; 5545 +/* Implement PRINT_OPERAND_ADDRESS macro. */ 5546 +void 5547 +score_print_operand_address (FILE *file, rtx x) 5548 +{ 5549 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 5550 + return score7_print_operand_address (file, x); 5551 + else if (TARGET_SCORE3) 5552 + return score3_print_operand_address (file, x); 5553 5554 - case NOT: 5555 - *total = COSTS_N_INSNS (1); 5556 - return true; 5557 + gcc_unreachable (); 5558 +} 5559 5560 - case AND: 5561 - case IOR: 5562 - case XOR: 5563 - if (mode == DImode) 5564 - { 5565 - *total = COSTS_N_INSNS (2); 5566 - return true; 5567 - } 5568 - return false; 5569 +/* Implement SELECT_CC_MODE macro. */ 5570 +enum machine_mode 5571 +score_select_cc_mode (enum rtx_code op, rtx x, rtx y) 5572 +{ 5573 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 5574 + return score7_select_cc_mode (op, x, y); 5575 + else if (TARGET_SCORE3) 5576 + return score3_select_cc_mode (op, x, y); 5577 5578 - case ASHIFT: 5579 - case ASHIFTRT: 5580 - case LSHIFTRT: 5581 - if (mode == DImode) 5582 - { 5583 - *total = COSTS_N_INSNS ((GET_CODE (XEXP (x, 1)) == CONST_INT) 5584 - ? 4 : 12); 5585 - return true; 5586 - } 5587 - return false; 5588 + gcc_unreachable (); 5589 +} 5590 5591 - case ABS: 5592 - *total = COSTS_N_INSNS (4); 5593 - return true; 5594 +/* Return true if X is a symbolic constant that can be calculated in 5595 + the same way as a bare symbol. If it is, store the type of the 5596 + symbol in *SYMBOL_TYPE. */ 5597 +int 5598 +score_symbolic_constant_p (rtx x, enum score_symbol_type *symbol_type) 5599 +{ 5600 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 5601 + return score7_symbolic_constant_p (x, symbol_type); 5602 + else if (TARGET_SCORE3) 5603 + return score3_symbolic_constant_p (x, symbol_type); 5604 5605 - case PLUS: 5606 - case MINUS: 5607 - if (mode == DImode) 5608 - { 5609 - *total = COSTS_N_INSNS (4); 5610 - return true; 5611 - } 5612 - *total = COSTS_N_INSNS (1); 5613 - return true; 5614 + gcc_unreachable (); 5615 +} 5616 5617 - case NEG: 5618 - if (mode == DImode) 5619 - { 5620 - *total = COSTS_N_INSNS (4); 5621 - return true; 5622 - } 5623 - return false; 5624 +/* Generate the prologue instructions for entry into a S+core function. */ 5625 +void 5626 +score_prologue (void) 5627 +{ 5628 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 5629 + return score7_prologue (); 5630 + else if (TARGET_SCORE3) 5631 + return score3_prologue (); 5632 5633 - case MULT: 5634 - *total = optimize_size ? COSTS_N_INSNS (2) : COSTS_N_INSNS (12); 5635 - return true; 5636 + gcc_unreachable (); 5637 +} 5638 5639 - case DIV: 5640 - case MOD: 5641 - case UDIV: 5642 - case UMOD: 5643 - *total = optimize_size ? COSTS_N_INSNS (2) : COSTS_N_INSNS (33); 5644 - return true; 5645 +/* Generate the epilogue instructions in a S+core function. */ 5646 +void 5647 +score_epilogue (int sibcall_p) 5648 +{ 5649 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 5650 + return score7_epilogue (sibcall_p); 5651 + else if (TARGET_SCORE3) 5652 + return score3_epilogue (sibcall_p); 5653 5654 - case SIGN_EXTEND: 5655 - case ZERO_EXTEND: 5656 - switch (GET_MODE (XEXP (x, 0))) 5657 - { 5658 - case QImode: 5659 - case HImode: 5660 - if (GET_CODE (XEXP (x, 0)) == MEM) 5661 - { 5662 - *total = COSTS_N_INSNS (2); 5663 - 5664 - if (!TARGET_LITTLE_ENDIAN && 5665 - side_effects_p (XEXP (XEXP (x, 0), 0))) 5666 - *total = 100; 5667 - } 5668 - else 5669 - *total = COSTS_N_INSNS (1); 5670 - break; 5671 - 5672 - default: 5673 - *total = COSTS_N_INSNS (1); 5674 - break; 5675 - } 5676 - return true; 5677 + gcc_unreachable (); 5678 +} 5679 5680 - default: 5681 - return false; 5682 - } 5683 +void 5684 +score_gen_cmp (enum machine_mode mode) 5685 +{ 5686 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 5687 + return score7_gen_cmp (mode); 5688 + else if (TARGET_SCORE3) 5689 + return score3_gen_cmp (mode); 5690 + 5691 + gcc_unreachable (); 5692 } 5693 5694 -/* Implement TARGET_ADDRESS_COST macro. */ 5695 -int 5696 -score_address_cost (rtx addr) 5697 +/* Call and sibcall pattern all need call this function. */ 5698 +void 5699 +score_call (rtx *ops, bool sib) 5700 { 5701 - return score_address_insns (addr, SImode); 5702 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 5703 + return score7_call (ops, sib); 5704 + else if (TARGET_SCORE3) 5705 + return score3_call (ops, sib); 5706 + 5707 + gcc_unreachable (); 5708 } 5709 5710 -/* Implement ASM_OUTPUT_EXTERNAL macro. */ 5711 -int 5712 -score_output_external (FILE *file ATTRIBUTE_UNUSED, 5713 - tree decl, const char *name) 5714 +/* Call value and sibcall value pattern all need call this function. */ 5715 +void 5716 +score_call_value (rtx *ops, bool sib) 5717 { 5718 - register struct extern_list *p; 5719 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 5720 + return score7_call_value (ops, sib); 5721 + else if (TARGET_SCORE3) 5722 + return score3_call_value (ops, sib); 5723 5724 - if (th_in_small_data_p (decl)) 5725 - { 5726 - p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list)); 5727 - p->next = extern_head; 5728 - p->name = name; 5729 - p->size = int_size_in_bytes (TREE_TYPE (decl)); 5730 - extern_head = p; 5731 - } 5732 - return 0; 5733 + gcc_unreachable (); 5734 } 5735 5736 -/* Output format asm string. */ 5737 void 5738 -score_declare_object (FILE *stream, const char *name, 5739 - const char *directive, const char *fmt, ...) 5740 +score_movsicc (rtx *ops) 5741 { 5742 - va_list ap; 5743 - fputs (directive, stream); 5744 - assemble_name (stream, name); 5745 - va_start (ap, fmt); 5746 - vfprintf (stream, fmt, ap); 5747 - va_end (ap); 5748 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 5749 + return score7_movsicc (ops); 5750 + else if (TARGET_SCORE3) 5751 + return score3_movsicc (ops); 5752 + 5753 + gcc_unreachable (); 5754 } 5755 5756 -/* Implement RETURN_ADDR_RTX. Note, we do not support moving 5757 - back to a previous frame. */ 5758 -rtx 5759 -score_return_addr (int count, rtx frame ATTRIBUTE_UNUSED) 5760 +/* Machine Split */ 5761 +void 5762 +score_movdi (rtx *ops) 5763 { 5764 - if (count != 0) 5765 - return const0_rtx; 5766 - return get_hard_reg_initial_val (Pmode, RA_REGNUM); 5767 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 5768 + return score7_movdi (ops); 5769 + else if (TARGET_SCORE3) 5770 + return score3_movdi (ops); 5771 + 5772 + gcc_unreachable (); 5773 } 5774 5775 -/* Implement PRINT_OPERAND macro. */ 5776 -/* Score-specific operand codes: 5777 - '[' print .set nor1 directive 5778 - ']' print .set r1 directive 5779 - 'U' print hi part of a CONST_INT rtx 5780 - 'E' print log2(v) 5781 - 'F' print log2(~v) 5782 - 'D' print SFmode const double 5783 - 'S' selectively print "!" if operand is 15bit instruction accessible 5784 - 'V' print "v!" if operand is 15bit instruction accessible, or "lfh!" 5785 - 'L' low part of DImode reg operand 5786 - 'H' high part of DImode reg operand 5787 - 'C' print part of opcode for a branch condition. */ 5788 void 5789 -score_print_operand (FILE *file, rtx op, int c) 5790 +score_zero_extract_andi (rtx *ops) 5791 { 5792 - enum rtx_code code = -1; 5793 - if (!PRINT_OPERAND_PUNCT_VALID_P (c)) 5794 - code = GET_CODE (op); 5795 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 5796 + return score7_zero_extract_andi (ops); 5797 + else if (TARGET_SCORE3) 5798 + return score3_zero_extract_andi (ops); 5799 + 5800 + gcc_unreachable (); 5801 +} 5802 + 5803 +/* Output asm insn for move. */ 5804 +const char * 5805 +score_move (rtx *ops) 5806 +{ 5807 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 5808 + return score7_move (ops); 5809 + else if (TARGET_SCORE3) 5810 + return score3_move (ops); 5811 5812 - if (c == '[') 5813 + gcc_unreachable (); 5814 +} 5815 + 5816 +/* Output asm insn for load. */ 5817 +const char * 5818 +score_linsn (rtx *ops, enum score_mem_unit unit, bool sign) 5819 +{ 5820 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 5821 + return score7_linsn (ops, unit, sign); 5822 + else if (TARGET_SCORE3) 5823 + return score3_linsn (ops, unit, sign); 5824 + 5825 + gcc_unreachable (); 5826 +} 5827 + 5828 +/* Output asm insn for store. */ 5829 +const char * 5830 +score_sinsn (rtx *ops, enum score_mem_unit unit) 5831 +{ 5832 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 5833 + return score7_sinsn (ops, unit); 5834 + else if (TARGET_SCORE3) 5835 + return score3_sinsn (ops, unit); 5836 + 5837 + gcc_unreachable (); 5838 +} 5839 + 5840 +/* Output asm insn for load immediate. */ 5841 +const char * 5842 +score_limm (rtx *ops) 5843 +{ 5844 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 5845 + return score7_limm (ops); 5846 + else if (TARGET_SCORE3) 5847 + return score3_limm (ops); 5848 + 5849 + gcc_unreachable (); 5850 +} 5851 + 5852 + 5853 +/* Generate add insn. */ 5854 +const char * 5855 +score_select_add_imm (rtx *ops, bool set_cc) 5856 +{ 5857 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 5858 + return score7_select_add_imm (ops, set_cc); 5859 + else if (TARGET_SCORE3) 5860 + return score3_select_add_imm (ops, set_cc); 5861 + 5862 + gcc_unreachable (); 5863 +} 5864 + 5865 +/* Output arith insn. */ 5866 +const char * 5867 +score_select (rtx *ops, const char *inst_pre, 5868 + bool commu, const char *letter, bool set_cc) 5869 +{ 5870 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 5871 + return score7_select (ops, inst_pre, commu, letter, set_cc); 5872 + else if (TARGET_SCORE3) 5873 + return score3_select (ops, inst_pre, commu, letter, set_cc); 5874 + 5875 + gcc_unreachable (); 5876 +} 5877 + 5878 +/* Output switch case insn, only supported in score3. */ 5879 +const char * 5880 +score_output_casesi (rtx *operands) 5881 +{ 5882 + if (TARGET_SCORE3) 5883 + return score3_output_casesi (operands); 5884 + 5885 + gcc_unreachable (); 5886 +} 5887 + 5888 +/* Output rpush insn, only supported in score3. */ 5889 +const char * 5890 +score_rpush (rtx *operands) 5891 +{ 5892 + if (TARGET_SCORE3) 5893 + return score3_rpush (operands); 5894 + 5895 + gcc_unreachable (); 5896 +} 5897 + 5898 +/* Output rpop insn, only supported in score3. */ 5899 +const char * 5900 +score_rpop (rtx *operands) 5901 +{ 5902 + if (TARGET_SCORE3) 5903 + return score3_rpop (operands); 5904 + 5905 + gcc_unreachable (); 5906 +} 5907 + 5908 +/* Emit lcb/lce insns. */ 5909 +bool 5910 +score_unaligned_load (rtx *ops) 5911 +{ 5912 + rtx dst = ops[0]; 5913 + rtx src = ops[1]; 5914 + rtx len = ops[2]; 5915 + rtx off = ops[3]; 5916 + rtx addr_reg; 5917 + 5918 + if (INTVAL (len) != BITS_PER_WORD 5919 + || (INTVAL (off) % BITS_PER_UNIT) != 0) 5920 + return false; 5921 + 5922 + gcc_assert (GET_MODE_SIZE (GET_MODE (dst)) == GET_MODE_SIZE (SImode)); 5923 + 5924 + addr_reg = copy_addr_to_reg (XEXP (src, 0)); 5925 + emit_insn (gen_move_lcb (addr_reg, addr_reg)); 5926 + emit_insn (gen_move_lce (addr_reg, addr_reg, dst)); 5927 + 5928 + return true; 5929 +} 5930 + 5931 +/* Emit scb/sce insns. */ 5932 +bool 5933 +score_unaligned_store (rtx *ops) 5934 +{ 5935 + rtx dst = ops[0]; 5936 + rtx len = ops[1]; 5937 + rtx off = ops[2]; 5938 + rtx src = ops[3]; 5939 + rtx addr_reg; 5940 + 5941 + if (INTVAL(len) != BITS_PER_WORD 5942 + || (INTVAL(off) % BITS_PER_UNIT) != 0) 5943 + return false; 5944 + 5945 + gcc_assert (GET_MODE_SIZE (GET_MODE (src)) == GET_MODE_SIZE (SImode)); 5946 + 5947 + addr_reg = copy_addr_to_reg (XEXP (dst, 0)); 5948 + emit_insn (gen_move_scb (addr_reg, addr_reg, src)); 5949 + emit_insn (gen_move_sce (addr_reg, addr_reg)); 5950 + 5951 + return true; 5952 +} 5953 + 5954 +/* If length is short, generate move insns straight. */ 5955 +static void 5956 +score_block_move_straight (rtx dst, rtx src, HOST_WIDE_INT length) 5957 +{ 5958 + HOST_WIDE_INT leftover; 5959 + int i, reg_count; 5960 + rtx *regs; 5961 + 5962 + leftover = length % UNITS_PER_WORD; 5963 + length -= leftover; 5964 + reg_count = length / UNITS_PER_WORD; 5965 + 5966 + regs = alloca (sizeof (rtx) * reg_count); 5967 + for (i = 0; i < reg_count; i++) 5968 + regs[i] = gen_reg_rtx (SImode); 5969 + 5970 + /* Load from src to regs. */ 5971 + if (MEM_ALIGN (src) >= BITS_PER_WORD) 5972 { 5973 - fprintf (file, ".set r1\n"); 5974 + HOST_WIDE_INT offset = 0; 5975 + for (i = 0; i < reg_count; offset += UNITS_PER_WORD, i++) 5976 + emit_move_insn (regs[i], adjust_address (src, SImode, offset)); 5977 } 5978 - else if (c == ']') 5979 + else if (reg_count >= 1) 5980 { 5981 - fprintf (file, "\n\t.set nor1"); 5982 + rtx src_reg = copy_addr_to_reg (XEXP (src, 0)); 5983 + 5984 + emit_insn (gen_move_lcb (src_reg, src_reg)); 5985 + for (i = 0; i < (reg_count - 1); i++) 5986 + emit_insn (gen_move_lcw (src_reg, src_reg, regs[i])); 5987 + emit_insn (gen_move_lce (src_reg, src_reg, regs[i])); 5988 } 5989 - else if (c == 'U') 5990 + 5991 + /* Store regs to dest. */ 5992 + if (MEM_ALIGN (dst) >= BITS_PER_WORD) 5993 { 5994 - gcc_assert (code == CONST_INT); 5995 - fprintf (file, HOST_WIDE_INT_PRINT_HEX, 5996 - (INTVAL (op) >> 16) & 0xffff); 5997 + HOST_WIDE_INT offset = 0; 5998 + for (i = 0; i < reg_count; offset += UNITS_PER_WORD, i++) 5999 + emit_move_insn (adjust_address (dst, SImode, offset), regs[i]); 6000 } 6001 - else if (c == 'D') 6002 + else if (reg_count >= 1) 6003 { 6004 - if (GET_CODE (op) == CONST_DOUBLE) 6005 - { 6006 - rtx temp = gen_lowpart (SImode, op); 6007 - gcc_assert (GET_MODE (op) == SFmode); 6008 - fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (temp) & 0xffffffff); 6009 - } 6010 - else 6011 - output_addr_const (file, op); 6012 + rtx dst_reg = copy_addr_to_reg (XEXP (dst, 0)); 6013 + 6014 + emit_insn (gen_move_scb (dst_reg, dst_reg, regs[0])); 6015 + for (i = 1; i < reg_count; i++) 6016 + emit_insn (gen_move_scw (dst_reg, dst_reg, regs[i])); 6017 + emit_insn (gen_move_sce (dst_reg, dst_reg)); 6018 } 6019 - else if (c == 'S') 6020 + 6021 + /* Mop up any left-over bytes. */ 6022 + if (leftover > 0) 6023 { 6024 - gcc_assert (code == REG); 6025 - if (G16_REG_P (REGNO (op))) 6026 - fprintf (file, "!"); 6027 + src = adjust_address (src, BLKmode, length); 6028 + dst = adjust_address (dst, BLKmode, length); 6029 + move_by_pieces (dst, src, leftover, 6030 + MIN (MEM_ALIGN (src), MEM_ALIGN (dst)), 0); 6031 } 6032 - else if (c == 'V') 6033 +} 6034 + 6035 +/* Generate loop head when dst or src is unaligned. */ 6036 +static void 6037 +score_block_move_loop_head (rtx dst_reg, HOST_WIDE_INT dst_align, 6038 + rtx src_reg, HOST_WIDE_INT src_align, 6039 + HOST_WIDE_INT length) 6040 +{ 6041 + bool src_unaligned = (src_align < BITS_PER_WORD); 6042 + bool dst_unaligned = (dst_align < BITS_PER_WORD); 6043 + 6044 + rtx temp = gen_reg_rtx (SImode); 6045 + 6046 + gcc_assert (length == UNITS_PER_WORD); 6047 + 6048 + if (src_unaligned) 6049 { 6050 - gcc_assert (code == REG); 6051 - fprintf (file, G16_REG_P (REGNO (op)) ? "v!" : "lfh!"); 6052 + emit_insn (gen_move_lcb (src_reg, src_reg)); 6053 + emit_insn (gen_move_lcw (src_reg, src_reg, temp)); 6054 } 6055 - else if (c == 'C') 6056 - { 6057 - enum machine_mode mode = GET_MODE (XEXP (op, 0)); 6058 + else 6059 + emit_insn (gen_move_lw_a (src_reg, 6060 + src_reg, gen_int_mode (4, SImode), temp)); 6061 6062 - switch (code) 6063 - { 6064 - case EQ: fputs ("eq", file); break; 6065 - case NE: fputs ("ne", file); break; 6066 - case GT: fputs ("gt", file); break; 6067 - case GE: fputs (mode != CCmode ? "pl" : "ge", file); break; 6068 - case LT: fputs (mode != CCmode ? "mi" : "lt", file); break; 6069 - case LE: fputs ("le", file); break; 6070 - case GTU: fputs ("gtu", file); break; 6071 - case GEU: fputs ("cs", file); break; 6072 - case LTU: fputs ("cc", file); break; 6073 - case LEU: fputs ("leu", file); break; 6074 - default: 6075 - output_operand_lossage ("invalid operand for code: '%c'", code); 6076 - } 6077 - } 6078 - else if (c == 'E') 6079 - { 6080 - unsigned HOST_WIDE_INT i; 6081 - unsigned HOST_WIDE_INT pow2mask = 1; 6082 - unsigned HOST_WIDE_INT val; 6083 + if (dst_unaligned) 6084 + emit_insn (gen_move_scb (dst_reg, dst_reg, temp)); 6085 + else 6086 + emit_insn (gen_move_sw_a (dst_reg, 6087 + dst_reg, gen_int_mode (4, SImode), temp)); 6088 +} 6089 6090 - val = INTVAL (op); 6091 - for (i = 0; i < 32; i++) 6092 - { 6093 - if (val == pow2mask) 6094 - break; 6095 - pow2mask <<= 1; 6096 - } 6097 - gcc_assert (i < 32); 6098 - fprintf (file, HOST_WIDE_INT_PRINT_HEX, i); 6099 +/* Generate loop body, copy length bytes per iteration. */ 6100 +static void 6101 +score_block_move_loop_body (rtx dst_reg, HOST_WIDE_INT dst_align, 6102 + rtx src_reg, HOST_WIDE_INT src_align, 6103 + HOST_WIDE_INT length) 6104 +{ 6105 + int reg_count = length / UNITS_PER_WORD; 6106 + rtx *regs = alloca (sizeof (rtx) * reg_count); 6107 + int i; 6108 + bool src_unaligned = (src_align < BITS_PER_WORD); 6109 + bool dst_unaligned = (dst_align < BITS_PER_WORD); 6110 + 6111 + for (i = 0; i < reg_count; i++) 6112 + regs[i] = gen_reg_rtx (SImode); 6113 + 6114 + if (src_unaligned) 6115 + { 6116 + for (i = 0; i < reg_count; i++) 6117 + emit_insn (gen_move_lcw (src_reg, src_reg, regs[i])); 6118 } 6119 - else if (c == 'F') 6120 + else 6121 { 6122 - unsigned HOST_WIDE_INT i; 6123 - unsigned HOST_WIDE_INT pow2mask = 1; 6124 - unsigned HOST_WIDE_INT val; 6125 - 6126 - val = ~INTVAL (op); 6127 - for (i = 0; i < 32; i++) 6128 - { 6129 - if (val == pow2mask) 6130 - break; 6131 - pow2mask <<= 1; 6132 - } 6133 - gcc_assert (i < 32); 6134 - fprintf (file, HOST_WIDE_INT_PRINT_HEX, i); 6135 + for (i = 0; i < reg_count; i++) 6136 + emit_insn (gen_move_lw_a (src_reg, 6137 + src_reg, gen_int_mode (4, SImode), regs[i])); 6138 } 6139 - else if (code == REG) 6140 + 6141 + if (dst_unaligned) 6142 { 6143 - int regnum = REGNO (op); 6144 - if ((c == 'H' && !WORDS_BIG_ENDIAN) 6145 - || (c == 'L' && WORDS_BIG_ENDIAN)) 6146 - regnum ++; 6147 - fprintf (file, "%s", reg_names[regnum]); 6148 + for (i = 0; i < reg_count; i++) 6149 + emit_insn (gen_move_scw (dst_reg, dst_reg, regs[i])); 6150 } 6151 else 6152 { 6153 - switch (code) 6154 - { 6155 - case MEM: 6156 - score_print_operand_address (file, op); 6157 - break; 6158 - default: 6159 - output_addr_const (file, op); 6160 - } 6161 + for (i = 0; i < reg_count; i++) 6162 + emit_insn (gen_move_sw_a (dst_reg, 6163 + dst_reg, gen_int_mode (4, SImode), regs[i])); 6164 } 6165 } 6166 6167 -/* Implement PRINT_OPERAND_ADDRESS macro. */ 6168 -void 6169 -score_print_operand_address (FILE *file, rtx x) 6170 +/* Generate loop foot, copy the leftover bytes. */ 6171 +static void 6172 +score_block_move_loop_foot (rtx dst_reg, HOST_WIDE_INT dst_align, 6173 + rtx src_reg, HOST_WIDE_INT src_align, 6174 + HOST_WIDE_INT length) 6175 { 6176 - struct score_address_info addr; 6177 - enum rtx_code code = GET_CODE (x); 6178 - enum machine_mode mode = GET_MODE (x); 6179 + bool src_unaligned = (src_align < BITS_PER_WORD); 6180 + bool dst_unaligned = (dst_align < BITS_PER_WORD); 6181 + 6182 + HOST_WIDE_INT leftover; 6183 + 6184 + leftover = length % UNITS_PER_WORD; 6185 + length -= leftover; 6186 6187 - if (code == MEM) 6188 - x = XEXP (x, 0); 6189 + if (length > 0) 6190 + score_block_move_loop_body (dst_reg, dst_align, 6191 + src_reg, src_align, length); 6192 6193 - if (mda_classify_address (&addr, mode, x, true)) 6194 + if (dst_unaligned) 6195 + emit_insn (gen_move_sce (dst_reg, dst_reg)); 6196 + 6197 + if (leftover > 0) 6198 { 6199 - switch (addr.type) 6200 + HOST_WIDE_INT src_adj = src_unaligned ? -4 : 0; 6201 + HOST_WIDE_INT dst_adj = dst_unaligned ? -4 : 0; 6202 + rtx temp; 6203 + 6204 + gcc_assert (leftover < UNITS_PER_WORD); 6205 + 6206 + if (leftover >= UNITS_PER_WORD / 2 6207 + && src_align >= BITS_PER_WORD / 2 6208 + && dst_align >= BITS_PER_WORD / 2) 6209 { 6210 - case ADD_REG: 6211 - { 6212 - switch (addr.code) 6213 - { 6214 - case PRE_DEC: 6215 - fprintf (file, "[%s,-%ld]+", reg_names[REGNO (addr.reg)], 6216 - INTVAL (addr.offset)); 6217 - break; 6218 - case POST_DEC: 6219 - fprintf (file, "[%s]+,-%ld", reg_names[REGNO (addr.reg)], 6220 - INTVAL (addr.offset)); 6221 - break; 6222 - case PRE_INC: 6223 - fprintf (file, "[%s, %ld]+", reg_names[REGNO (addr.reg)], 6224 - INTVAL (addr.offset)); 6225 - break; 6226 - case POST_INC: 6227 - fprintf (file, "[%s]+, %ld", reg_names[REGNO (addr.reg)], 6228 - INTVAL (addr.offset)); 6229 - break; 6230 - default: 6231 - if (INTVAL(addr.offset) == 0) 6232 - fprintf(file, "[%s]", reg_names[REGNO (addr.reg)]); 6233 - else 6234 - fprintf(file, "[%s, %ld]", reg_names[REGNO (addr.reg)], 6235 - INTVAL(addr.offset)); 6236 - break; 6237 - } 6238 - } 6239 - return; 6240 - case ADD_CONST_INT: 6241 - case ADD_SYMBOLIC: 6242 - output_addr_const (file, x); 6243 - return; 6244 + temp = gen_reg_rtx (HImode); 6245 + emit_insn (gen_move_lhu_b (src_reg, src_reg, 6246 + gen_int_mode (src_adj, SImode), temp)); 6247 + emit_insn (gen_move_sh_b (dst_reg, dst_reg, 6248 + gen_int_mode (dst_adj, SImode), temp)); 6249 + leftover -= UNITS_PER_WORD / 2; 6250 + src_adj = UNITS_PER_WORD / 2; 6251 + dst_adj = UNITS_PER_WORD / 2; 6252 + } 6253 + 6254 + while (leftover > 0) 6255 + { 6256 + temp = gen_reg_rtx (QImode); 6257 + emit_insn (gen_move_lbu_b (src_reg, src_reg, 6258 + gen_int_mode (src_adj, SImode), temp)); 6259 + emit_insn (gen_move_sb_b (dst_reg, dst_reg, 6260 + gen_int_mode (dst_adj, SImode), temp)); 6261 + leftover--; 6262 + src_adj = 1; 6263 + dst_adj = 1; 6264 } 6265 } 6266 - print_rtl (stderr, x); 6267 - gcc_unreachable (); 6268 } 6269 6270 -/* Implement SELECT_CC_MODE macro. */ 6271 -enum machine_mode 6272 -score_select_cc_mode (enum rtx_code op, rtx x, rtx y) 6273 +#define MIN_MOVE_REGS 3 6274 +#define MIN_MOVE_BYTES (MIN_MOVE_REGS * UNITS_PER_WORD) 6275 +#define MAX_MOVE_REGS 4 6276 +#define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD) 6277 + 6278 +/* The length is large, generate a loop if necessary. 6279 + The loop is consisted by loop head/body/foot. */ 6280 +static void 6281 +score_block_move_loop (rtx dst, rtx src, HOST_WIDE_INT length) 6282 { 6283 - if ((op == EQ || op == NE || op == LT || op == GE) 6284 - && y == const0_rtx 6285 - && GET_MODE (x) == SImode) 6286 - { 6287 - switch (GET_CODE (x)) 6288 - { 6289 - case PLUS: 6290 - case MINUS: 6291 - case NEG: 6292 - case AND: 6293 - case IOR: 6294 - case XOR: 6295 - case NOT: 6296 - case ASHIFT: 6297 - case LSHIFTRT: 6298 - case ASHIFTRT: 6299 - return CC_NZmode; 6300 - 6301 - case SIGN_EXTEND: 6302 - case ZERO_EXTEND: 6303 - case ROTATE: 6304 - case ROTATERT: 6305 - return (op == LT || op == GE) ? CC_Nmode : CCmode; 6306 + HOST_WIDE_INT src_align = MEM_ALIGN (src); 6307 + HOST_WIDE_INT dst_align = MEM_ALIGN (dst); 6308 + HOST_WIDE_INT loop_mov_bytes; 6309 + HOST_WIDE_INT iteration = 0; 6310 + HOST_WIDE_INT head_length = 0, leftover; 6311 + rtx label, src_reg, dst_reg, final_dst; 6312 6313 - default: 6314 - return CCmode; 6315 - } 6316 - } 6317 + bool gen_loop_head = (src_align < BITS_PER_WORD 6318 + || dst_align < BITS_PER_WORD); 6319 + 6320 + if (gen_loop_head) 6321 + head_length += UNITS_PER_WORD; 6322 6323 - if ((op == EQ || op == NE) 6324 - && (GET_CODE (y) == NEG) 6325 - && register_operand (XEXP (y, 0), SImode) 6326 - && register_operand (x, SImode)) 6327 + for (loop_mov_bytes = MAX_MOVE_BYTES; 6328 + loop_mov_bytes >= MIN_MOVE_BYTES; 6329 + loop_mov_bytes -= UNITS_PER_WORD) 6330 + { 6331 + iteration = (length - head_length) / loop_mov_bytes; 6332 + if (iteration > 1) 6333 + break; 6334 + } 6335 + if (iteration <= 1) 6336 { 6337 - return CC_NZmode; 6338 + score_block_move_straight (dst, src, length); 6339 + return; 6340 } 6341 6342 - return CCmode; 6343 + leftover = (length - head_length) % loop_mov_bytes; 6344 + length -= leftover; 6345 + 6346 + src_reg = copy_addr_to_reg (XEXP (src, 0)); 6347 + dst_reg = copy_addr_to_reg (XEXP (dst, 0)); 6348 + final_dst = expand_simple_binop (Pmode, PLUS, dst_reg, GEN_INT (length), 6349 + 0, 0, OPTAB_WIDEN); 6350 + 6351 + if (gen_loop_head) 6352 + score_block_move_loop_head (dst_reg, dst_align, 6353 + src_reg, src_align, head_length); 6354 + 6355 + label = gen_label_rtx (); 6356 + emit_label (label); 6357 + 6358 + score_block_move_loop_body (dst_reg, dst_align, 6359 + src_reg, src_align, loop_mov_bytes); 6360 + 6361 + emit_insn (gen_cmpsi (dst_reg, final_dst)); 6362 + emit_jump_insn (gen_bne (label)); 6363 + 6364 + score_block_move_loop_foot (dst_reg, dst_align, 6365 + src_reg, src_align, leftover); 6366 +} 6367 + 6368 +/* Generate block move, for misc.md: "movmemsi". */ 6369 +bool 6370 +score_block_move (rtx *ops) 6371 +{ 6372 + rtx dst = ops[0]; 6373 + rtx src = ops[1]; 6374 + rtx length = ops[2]; 6375 + 6376 + if (TARGET_LITTLE_ENDIAN 6377 + && (MEM_ALIGN (src) < BITS_PER_WORD || MEM_ALIGN (dst) < BITS_PER_WORD) 6378 + && INTVAL (length) >= UNITS_PER_WORD) 6379 + return false; 6380 + 6381 + if (GET_CODE (length) == CONST_INT) 6382 + { 6383 + if (INTVAL (length) <= 2 * MAX_MOVE_BYTES) 6384 + { 6385 + score_block_move_straight (dst, src, INTVAL (length)); 6386 + return true; 6387 + } 6388 + else if (optimize && 6389 + !(flag_unroll_loops || flag_unroll_all_loops)) 6390 + { 6391 + score_block_move_loop (dst, src, INTVAL (length)); 6392 + return true; 6393 + } 6394 + } 6395 + return false; 6396 } 6397 6398 struct gcc_target targetm = TARGET_INITIALIZER; 6399 diff -Naur gcc-4.2.2.orig/gcc/config/score/score.h gcc-4.2.2/gcc/config/score/score.h 6400 --- gcc-4.2.2.orig/gcc/config/score/score.h 2007-09-01 11:28:30.000000000 -0400 6401 +++ gcc-4.2.2/gcc/config/score/score.h 2007-10-18 02:24:34.000000000 -0400 6402 @@ -19,30 +19,53 @@ 6403 <http://www.gnu.org/licenses/>. */ 6404 6405 #include "score-conv.h" 6406 -#include "score-version.h" 6407 - 6408 -/* Define the information needed to generate branch insns. This is 6409 - stored from the compare operation. */ 6410 -extern GTY(()) rtx cmp_op0; 6411 -extern GTY(()) rtx cmp_op1; 6412 6413 /* Controlling the Compilation Driver. */ 6414 #undef SWITCH_TAKES_ARG 6415 #define SWITCH_TAKES_ARG(CHAR) \ 6416 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G') 6417 6418 -/* CC1_SPEC is the set of arguments to pass to the compiler proper. */ 6419 +#undef CPP_SPEC 6420 +#define CPP_SPEC "%{mscore3:-D__score3__} %{G*}" 6421 + 6422 #undef CC1_SPEC 6423 -#define CC1_SPEC "%{G*} %{!mel:-meb}" 6424 +#define CC1_SPEC "%{!mel:-meb} %{mel:-mel } \ 6425 +%{!mscore*:-mscore7} \ 6426 +%{mscore3:-mscore3} \ 6427 +%{mscore3d:-mscore3d} \ 6428 +%{mscore7:-mscore7} \ 6429 +%{mscore7d:-mscore7d} \ 6430 +%{G*}" 6431 6432 #undef ASM_SPEC 6433 -#define ASM_SPEC \ 6434 - "%{!mel:-EB} %{mel:-EL} %{mscore5:-SCORE5} %{mscore5u:-SCORE5U} \ 6435 - %{mscore7:%{!mmac:-SCORE7}} %{mscore7:%{mmac:-SCORE7D}} \ 6436 - %{mscore7d:-SCORE7D} %{G*}" 6437 +#define ASM_SPEC "%{!mel:-EB} %{mel:-EL} \ 6438 +%{!mscore*:-march=score7} \ 6439 +%{mscore7:-march=score7} \ 6440 +%{mscore7d:-march=score7} \ 6441 +%{mscore3:-march=score3} \ 6442 +%{mscore3d:-march=score3} \ 6443 +%{march=score5:-march=score7} \ 6444 +%{march=score5u:-march=score7} \ 6445 +%{march=score7:-march=score7} \ 6446 +%{march=score7d:-march=score7} \ 6447 +%{march=score3:-march=score3} \ 6448 +%{march=score3d:-march=score3} \ 6449 +%{G*}" 6450 6451 #undef LINK_SPEC 6452 -#define LINK_SPEC "%{!mel:-EB} %{mel:-EL} %{G*}" 6453 +#define LINK_SPEC "%{!mel:-EB} %{mel:-EL} \ 6454 +%{!mscore*:-mscore7_elf} \ 6455 +%{mscore7:-mscore7_elf} \ 6456 +%{mscore7d:-mscore7_elf} \ 6457 +%{mscore3:-mscore3_elf} \ 6458 +%{mscore3d:-mscore3_elf} \ 6459 +%{march=score5:-mscore7_elf} \ 6460 +%{march=score5u:-mscore7_elf} \ 6461 +%{march=score7:-mscore7_elf} \ 6462 +%{march=score7d:-mscore7_elf} \ 6463 +%{march=score3:-mscore3_elf} \ 6464 +%{march=score3d:-mscore3_elf} \ 6465 +%{G*}" 6466 6467 /* Run-time Target Specification. */ 6468 #define TARGET_CPU_CPP_BUILTINS() \ 6469 @@ -54,16 +77,26 @@ 6470 builtin_define ("__scorele__"); \ 6471 else \ 6472 builtin_define ("__scorebe__"); \ 6473 + if (TARGET_SCORE5) \ 6474 + builtin_define ("__score5__"); \ 6475 if (TARGET_SCORE5U) \ 6476 builtin_define ("__score5u__"); \ 6477 - else \ 6478 + if (TARGET_SCORE7) \ 6479 builtin_define ("__score7__"); \ 6480 + if (TARGET_SCORE7D) \ 6481 + builtin_define ("__score7d__"); \ 6482 + if (TARGET_SCORE3) \ 6483 + builtin_define ("__score3__"); \ 6484 + if (TARGET_SCORE3D) \ 6485 + builtin_define ("__score3d__"); \ 6486 } while (0) 6487 6488 -#define TARGET_DEFAULT MASK_SCORE7 6489 +#define TARGET_DEFAULT 0 6490 + 6491 +#define SCORE_GCC_VERSION "1.6" 6492 6493 #define TARGET_VERSION \ 6494 - fprintf (stderr, "Sunplus S+CORE %s", SCORE_GCC_VERSION); 6495 + fprintf (stderr, "Sunplus S+core rev=%s", SCORE_GCC_VERSION); 6496 6497 #define OVERRIDE_OPTIONS score_override_options () 6498 6499 @@ -415,6 +448,7 @@ 6500 /* The class value for index registers. */ 6501 #define INDEX_REG_CLASS NO_REGS 6502 6503 +extern enum reg_class score_char_to_class[256]; 6504 #define REG_CLASS_FROM_LETTER(C) score_char_to_class[(unsigned char) (C)] 6505 6506 /* Addressing modes, and classification of registers for them. */ 6507 @@ -545,7 +579,7 @@ 6508 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect 6509 of this macro is to determine whether the space is included in 6510 `current_function_outgoing_args_size'. */ 6511 -#define OUTGOING_REG_PARM_STACK_SPACE 1 6512 +#define OUTGOING_REG_PARM_STACK_SPACE 6513 6514 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACK_SIZE) 0 6515 6516 @@ -619,28 +653,58 @@ 6517 /* Generating Code for Profiling */ 6518 /* Output assembler code to FILE to increment profiler label # LABELNO 6519 for profiling a function entry. */ 6520 -#define FUNCTION_PROFILER(FILE, LABELNO) \ 6521 -{ \ 6522 - fprintf (FILE, " .set r1 \n"); \ 6523 - fprintf (FILE, " mv r%d,r%d \n", AT_REGNUM, RA_REGNUM); \ 6524 - fprintf (FILE, " subi r%d, %d \n", STACK_POINTER_REGNUM, 8); \ 6525 - fprintf (FILE, " jl _mcount \n"); \ 6526 - fprintf (FILE, " .set nor1 \n"); \ 6527 -} 6528 +#define FUNCTION_PROFILER(FILE, LABELNO) \ 6529 + do { \ 6530 + if (TARGET_SCORE7) \ 6531 + { \ 6532 + fprintf (FILE, " .set r1 \n"); \ 6533 + fprintf (FILE, " mv r%d,r%d \n", AT_REGNUM, RA_REGNUM); \ 6534 + fprintf (FILE, " subi r%d, %d \n", STACK_POINTER_REGNUM, 8); \ 6535 + fprintf (FILE, " jl _mcount \n"); \ 6536 + fprintf (FILE, " .set nor1 \n"); \ 6537 + } \ 6538 + else if (TARGET_SCORE3) \ 6539 + { \ 6540 + fprintf (FILE, " .set r1 \n"); \ 6541 + fprintf (FILE, " mv! r%d,r%d \n", AT_REGNUM, RA_REGNUM); \ 6542 + fprintf (FILE, " addi! r%d, %d \n", STACK_POINTER_REGNUM, -8);\ 6543 + fprintf (FILE, " jl _mcount \n"); \ 6544 + fprintf (FILE, " .set nor1 \n"); \ 6545 + } \ 6546 + } while (0) 6547 6548 -#define TRAMPOLINE_TEMPLATE(STREAM) \ 6549 -{ \ 6550 - fprintf (STREAM, "\t.set r1\n"); \ 6551 - fprintf (STREAM, "\tmv r31, r3\n"); \ 6552 - fprintf (STREAM, "\tbl nextinsn\n"); \ 6553 - fprintf (STREAM, "nextinsn:\n"); \ 6554 - fprintf (STREAM, "\tlw r1, [r3, 6*4-8]\n"); \ 6555 - fprintf (STREAM, "\tlw r23, [r3, 6*4-4]\n"); \ 6556 - fprintf (STREAM, "\tmv r3, r31\n"); \ 6557 - fprintf (STREAM, "\tbr! r1\n"); \ 6558 - fprintf (STREAM, "\tnop!\n"); \ 6559 - fprintf (STREAM, "\t.set nor1\n"); \ 6560 -} 6561 +#define TRAMPOLINE_TEMPLATE(STREAM) \ 6562 + do { \ 6563 + if (TARGET_SCORE7) \ 6564 + { \ 6565 + fprintf (STREAM, "\t.set r1\n"); \ 6566 + fprintf (STREAM, "\tmv r31, r3\n"); \ 6567 + fprintf (STREAM, "\tbl nextinsn\n"); \ 6568 + fprintf (STREAM, "nextinsn:\n"); \ 6569 + fprintf (STREAM, "\tlw r1, [r3, 6*4-8]\n"); \ 6570 + fprintf (STREAM, "\tlw r23, [r3, 6*4-4]\n"); \ 6571 + fprintf (STREAM, "\tmv r3, r31\n"); \ 6572 + fprintf (STREAM, "\tbr! r1\n"); \ 6573 + fprintf (STREAM, "\tnop!\n"); \ 6574 + fprintf (STREAM, "\t.set nor1\n"); \ 6575 + } \ 6576 + else if (TARGET_SCORE3) \ 6577 + { \ 6578 + fprintf (STREAM, "\t.set r1\n"); \ 6579 + fprintf (STREAM, "\tmv! r31, r3\n"); \ 6580 + fprintf (STREAM, "\tnop!\n"); \ 6581 + fprintf (STREAM, "\tbl nextinsn\n"); \ 6582 + fprintf (STREAM, "nextinsn:\n"); \ 6583 + fprintf (STREAM, "\tlw! r1, [r3, 6*4-8]\n"); \ 6584 + fprintf (STREAM, "\tnop!\n"); \ 6585 + fprintf (STREAM, "\tlw r23, [r3, 6*4-4]\n"); \ 6586 + fprintf (STREAM, "\tmv! r3, r31\n"); \ 6587 + fprintf (STREAM, "\tnop!\n"); \ 6588 + fprintf (STREAM, "\tbr! r1\n"); \ 6589 + fprintf (STREAM, "\tnop!\n"); \ 6590 + fprintf (STREAM, "\t.set nor1\n"); \ 6591 + } \ 6592 + } while (0) 6593 6594 /* Trampolines for Nested Functions. */ 6595 #define TRAMPOLINE_INSNS 6 6596 @@ -765,17 +829,23 @@ 6597 /* Output of Uninitialized Variables. */ 6598 /* This says how to define a global common symbol. */ 6599 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGN) \ 6600 - score_declare_object (STREAM, NAME, "\n\t.comm\t", \ 6601 - ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n", \ 6602 - SIZE, ALIGN / BITS_PER_UNIT); 6603 + do { \ 6604 + fputs ("\n\t.comm\t", STREAM); \ 6605 + assemble_name (STREAM, NAME); \ 6606 + fprintf (STREAM, " , " HOST_WIDE_INT_PRINT_UNSIGNED ", %u\n", \ 6607 + SIZE, ALIGN / BITS_PER_UNIT); \ 6608 + } while (0) 6609 6610 /* This says how to define a local common symbol (i.e., not visible to 6611 linker). */ 6612 #undef ASM_OUTPUT_ALIGNED_LOCAL 6613 -#define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \ 6614 - score_declare_object (STREAM, NAME, "\n\t.lcomm\t", \ 6615 - ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n", \ 6616 - SIZE, ALIGN / BITS_PER_UNIT); 6617 +#define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \ 6618 + do { \ 6619 + fputs ("\n\t.lcomm\t", STREAM); \ 6620 + assemble_name (STREAM, NAME); \ 6621 + fprintf (STREAM, " , " HOST_WIDE_INT_PRINT_UNSIGNED ", %u\n", \ 6622 + SIZE, ALIGN / BITS_PER_UNIT); \ 6623 + } while (0) 6624 6625 /* Globalizing directive for a label. */ 6626 #define GLOBAL_ASM_OP "\t.globl\t" 6627 @@ -790,8 +860,11 @@ 6628 #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) 6629 6630 #undef ASM_DECLARE_OBJECT_NAME 6631 -#define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \ 6632 - score_declare_object (STREAM, NAME, "", ":\n", 0) 6633 +#define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \ 6634 + do { \ 6635 + assemble_name (STREAM, NAME); \ 6636 + fprintf (STREAM, ":\n"); \ 6637 + } while (0) 6638 6639 /* This says how to output an external. It would be possible not to 6640 output anything and let undefined symbol become external. However 6641 @@ -808,7 +881,7 @@ 6642 6643 /* Local compiler-generated symbols must have a prefix that the assembler 6644 understands. */ 6645 -#define LOCAL_LABEL_PREFIX "." 6646 +#define LOCAL_LABEL_PREFIX (TARGET_SCORE7 ? "." : "$") 6647 6648 #undef ASM_GENERATE_INTERNAL_LABEL 6649 #define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \ 6650 @@ -859,32 +932,88 @@ 6651 #define USER_LABEL_PREFIX "" 6652 6653 /* This is how to output an insn to push a register on the stack. */ 6654 -#define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \ 6655 - do { \ 6656 - fprintf (STREAM, "\tpush! %s,[%s]\n", \ 6657 - reg_names[REGNO], \ 6658 - reg_names[STACK_POINTER_REGNUM]); \ 6659 +#define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \ 6660 + do { \ 6661 + if (TARGET_SCORE7) \ 6662 + fprintf (STREAM, "\tpush! %s,[%s]\n", \ 6663 + reg_names[REGNO], \ 6664 + reg_names[STACK_POINTER_REGNUM]); \ 6665 + else if (TARGET_SCORE3) \ 6666 + fprintf (STREAM, "\tpush!\t%s\n", \ 6667 + reg_names[REGNO]); \ 6668 } while (0) 6669 6670 /* This is how to output an insn to pop a register from the stack. */ 6671 -#define ASM_OUTPUT_REG_POP(STREAM, REGNO) \ 6672 - do { \ 6673 - fprintf (STREAM, "\tpop! %s,[%s]\n", \ 6674 - reg_names[REGNO], \ 6675 - reg_names[STACK_POINTER_REGNUM]); \ 6676 +#define ASM_OUTPUT_REG_POP(STREAM, REGNO) \ 6677 + do { \ 6678 + if (TARGET_SCORE7) \ 6679 + fprintf (STREAM, "\tpop! %s,[%s]\n", \ 6680 + reg_names[REGNO], \ 6681 + reg_names[STACK_POINTER_REGNUM]); \ 6682 + else if (TARGET_SCORE3) \ 6683 + fprintf (STREAM, "\tpop!\t%s\n", \ 6684 + reg_names[REGNO]); \ 6685 } while (0) 6686 6687 /* Output of Dispatch Tables. */ 6688 /* This is how to output an element of a case-vector. We can make the 6689 entries PC-relative in GP-relative when .gp(d)word is supported. */ 6690 -#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \ 6691 +#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \ 6692 + do { \ 6693 + if (TARGET_SCORE7) \ 6694 + if (flag_pic) \ 6695 + fprintf (STREAM, "\t.gpword %sL%d\n", LOCAL_LABEL_PREFIX, VALUE); \ 6696 + else \ 6697 + fprintf (STREAM, "\t.word %sL%d\n", LOCAL_LABEL_PREFIX, VALUE); \ 6698 + else if (TARGET_SCORE3) \ 6699 + { \ 6700 + switch (GET_MODE(BODY)) \ 6701 + { \ 6702 + case QImode: /* TBB */ \ 6703 + asm_fprintf (STREAM, "\t.byte\t(%LL%d-%LL%d_tbb)/2\n", \ 6704 + VALUE, REL); \ 6705 + break; \ 6706 + case HImode: /* TBH */ \ 6707 + asm_fprintf (STREAM, "\t.2byte\t(%LL%d-%LL%d_tbb)/2\n", \ 6708 + VALUE, REL); \ 6709 + break; \ 6710 + case SImode: \ 6711 + if (flag_pic) \ 6712 + fprintf (STREAM, "\t.gpword %sL%d\n", LOCAL_LABEL_PREFIX, VALUE); \ 6713 + else \ 6714 + fprintf (STREAM, "\t.word %sL%d\n", LOCAL_LABEL_PREFIX, VALUE); \ 6715 + break; \ 6716 + default: \ 6717 + gcc_unreachable(); \ 6718 + } \ 6719 + } \ 6720 + } while (0) 6721 + 6722 +/* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */ 6723 +#define ADDR_VEC_ALIGN(JUMPTABLE) (GET_MODE (PATTERN (JUMPTABLE)) == SImode ? 2 \ 6724 + : GET_MODE (PATTERN (JUMPTABLE)) == HImode ? 1 : 0) 6725 + 6726 +/* This is how to output a label which precedes a jumptable. Since 6727 + Score3 instructions are 2 bytes, we may need explicit alignment here. */ 6728 +#undef ASM_OUTPUT_CASE_LABEL 6729 +#define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \ 6730 do { \ 6731 - if (flag_pic) \ 6732 - fprintf (STREAM, "\t.gpword %sL%d\n", LOCAL_LABEL_PREFIX, VALUE); \ 6733 - else \ 6734 - fprintf (STREAM, "\t.word %sL%d\n", LOCAL_LABEL_PREFIX, VALUE); \ 6735 + if ((TARGET_SCORE7) && GET_MODE (PATTERN (JUMPTABLE)) == SImode) \ 6736 + ASM_OUTPUT_ALIGN (FILE, 2); \ 6737 + (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \ 6738 } while (0) 6739 6740 +/* Specify the machine mode that this machine uses 6741 + for the index in the tablejump instruction. */ 6742 +#define CASE_VECTOR_MODE SImode 6743 + 6744 +#define CASE_VECTOR_PC_RELATIVE (TARGET_SCORE3) 6745 + 6746 +#define CASE_VECTOR_SHORTEN_MODE(min, max, body) \ 6747 + ((min < 0 || max >= 0x2000 || TARGET_SCORE7) ? SImode \ 6748 + : (max >= 0x200) ? HImode \ 6749 + : QImode) 6750 + 6751 /* This is how to output an element of a case-vector that is absolute. */ 6752 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \ 6753 fprintf (STREAM, "\t.word %sL%d\n", LOCAL_LABEL_PREFIX, VALUE) 6754 @@ -927,10 +1056,6 @@ 6755 /* The DWARF 2 CFA column which tracks the return address. */ 6756 #define DWARF_FRAME_RETURN_COLUMN 3 6757 6758 -/* Specify the machine mode that this machine uses 6759 - for the index in the tablejump instruction. */ 6760 -#define CASE_VECTOR_MODE SImode 6761 - 6762 /* Define if operations between registers always perform the operation 6763 on the full register even if a narrower mode is specified. */ 6764 #define WORD_REGISTER_OPERATIONS 6765 diff -Naur gcc-4.2.2.orig/gcc/config/score/score.md gcc-4.2.2/gcc/config/score/score.md 6766 --- gcc-4.2.2.orig/gcc/config/score/score.md 2007-09-01 11:28:30.000000000 -0400 6767 +++ gcc-4.2.2/gcc/config/score/score.md 2007-10-18 02:24:34.000000000 -0400 6768 @@ -38,7 +38,6 @@ 6769 ; tce transfer to hi/lo registers 6770 ; fsr transfer from special registers 6771 ; tsr transfer to special registers 6772 -; pseudo pseudo instruction 6773 6774 (define_constants 6775 [(CC_REGNUM 33) 6776 @@ -73,19 +72,19 @@ 6777 (SFFS 10)]) 6778 6779 (define_attr "type" 6780 - "unknown,branch,jump,call,load,store,cmp,arith,move,const,nop,mul,div,cndmv,fce,tce,fsr,tsr,fcr,tcr,pseudo" 6781 + "unknown,branch,jump,call,load,store,cmp,arith,move,const,nop,mul,div,cndmv,fce,tce,fsr,tsr,fcr,tcr" 6782 (const_string "unknown")) 6783 6784 -(define_attr "mode" "unknown,none,QI,HI,SI,DI" 6785 +(define_attr "mode" "unknown,QI,HI,SI,DI" 6786 (const_string "unknown")) 6787 6788 +(define_attr "length" "" (const_int 4)) 6789 + 6790 (define_attr "up_c" "yes,no" 6791 (const_string "no")) 6792 6793 -(include "score7.md") 6794 +(include "score-generic.md") 6795 (include "predicates.md") 6796 -(include "misc.md") 6797 -(include "mac.md") 6798 6799 (define_expand "movqi" 6800 [(set (match_operand:QI 0 "nonimmediate_operand") 6801 @@ -99,25 +98,49 @@ 6802 } 6803 }) 6804 6805 -(define_insn "*movqi_insns" 6806 +(define_insn "*movqi_insns_score7" 6807 + [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,d,*x,d,*a") 6808 + (match_operand:QI 1 "general_operand" "i,d,m,d,*x,d,*a,d"))] 6809 + "(!MEM_P (operands[0]) || register_operand (operands[1], QImode)) 6810 + && (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 6811 +{ 6812 + switch (which_alternative) 6813 + { 6814 + case 0: return score_limm (operands); 6815 + case 1: return score_move (operands); 6816 + case 2: return score_linsn (operands, SCORE_BYTE, false); 6817 + case 3: return score_sinsn (operands, SCORE_BYTE); 6818 + case 4: return TARGET_SCORE7D ? \"mf%1%S0 %0\" : \"mf%1 %0\"; 6819 + case 5: return TARGET_SCORE7D ? \"mt%0%S1 %1\" : \"mt%0 %1\"; 6820 + case 6: return \"mfsr\t%0, %1\"; 6821 + case 7: return \"mtsr\t%1, %0\"; 6822 + default: gcc_unreachable (); 6823 + } 6824 +} 6825 + [(set_attr "type" "arith,move,load,store,fce,tce,fsr,tsr") 6826 + (set_attr "mode" "QI")]) 6827 + 6828 +(define_insn "*movqi_insns_score3" 6829 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,d,*x,d,*a") 6830 (match_operand:QI 1 "general_operand" "i,d,m,d,*x,d,*a,d"))] 6831 - "!MEM_P (operands[0]) || register_operand (operands[1], QImode)" 6832 + "(!MEM_P (operands[0]) || register_operand (operands[1], QImode)) 6833 + && (TARGET_SCORE3)" 6834 { 6835 switch (which_alternative) 6836 { 6837 - case 0: return mdp_limm (operands); 6838 - case 1: return mdp_move (operands); 6839 - case 2: return mdp_linsn (operands, MDA_BYTE, false); 6840 - case 3: return mdp_sinsn (operands, MDA_BYTE); 6841 - case 4: return TARGET_MAC ? \"mf%1%S0 %0\" : \"mf%1 %0\"; 6842 - case 5: return TARGET_MAC ? \"mt%0%S1 %1\" : \"mt%0 %1\"; 6843 - case 6: return \"mfsr %0, %1\"; 6844 - case 7: return \"mtsr %1, %0\"; 6845 + case 0: return score_limm (operands); 6846 + case 1: return \"mv!\t%0, %1\"; 6847 + case 2: return score_linsn (operands, SCORE_BYTE, false); 6848 + case 3: return score_sinsn (operands, SCORE_BYTE); 6849 + case 4: return TARGET_SCORE3D ? \"mf%1%S0\t%0\" : \"mf%1\t%0\"; 6850 + case 5: return TARGET_SCORE3D ? \"mt%0%S1\t%1\" : \"mt%0\t%1\"; 6851 + case 6: return \"mfsr\t%0, %1\"; 6852 + case 7: return \"mtsr\t%1, %0\"; 6853 default: gcc_unreachable (); 6854 } 6855 } 6856 [(set_attr "type" "arith,move,load,store,fce,tce,fsr,tsr") 6857 + (set_attr "length" "6,2,6,6,4,4,4,4") 6858 (set_attr "mode" "QI")]) 6859 6860 (define_expand "movhi" 6861 @@ -132,25 +155,49 @@ 6862 } 6863 }) 6864 6865 -(define_insn "*movhi_insns" 6866 +(define_insn "*movhi_insns_score7" 6867 + [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,d,*x,d,*a") 6868 + (match_operand:HI 1 "general_operand" "i,d,m,d,*x,d,*a,d"))] 6869 + "(!MEM_P (operands[0]) || register_operand (operands[1], HImode)) 6870 + && (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 6871 +{ 6872 + switch (which_alternative) 6873 + { 6874 + case 0: return score_limm (operands); 6875 + case 1: return score_move (operands); 6876 + case 2: return score_linsn (operands, SCORE_HWORD, false); 6877 + case 3: return score_sinsn (operands, SCORE_HWORD); 6878 + case 4: return TARGET_SCORE7D ? \"mf%1%S0 %0\" : \"mf%1 %0\"; 6879 + case 5: return TARGET_SCORE7D ? \"mt%0%S1 %1\" : \"mt%0 %1\"; 6880 + case 6: return \"mfsr\t%0, %1\"; 6881 + case 7: return \"mtsr\t%1, %0\"; 6882 + default: gcc_unreachable (); 6883 + } 6884 +} 6885 + [(set_attr "type" "arith,move,load,store,fce,tce,fsr,tsr") 6886 + (set_attr "mode" "HI")]) 6887 + 6888 +(define_insn "*movhi_insns_score3" 6889 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,d,*x,d,*a") 6890 (match_operand:HI 1 "general_operand" "i,d,m,d,*x,d,*a,d"))] 6891 - "!MEM_P (operands[0]) || register_operand (operands[1], HImode)" 6892 + "(!MEM_P (operands[0]) || register_operand (operands[1], HImode)) 6893 + && (TARGET_SCORE3)" 6894 { 6895 switch (which_alternative) 6896 { 6897 - case 0: return mdp_limm (operands); 6898 - case 1: return mdp_move (operands); 6899 - case 2: return mdp_linsn (operands, MDA_HWORD, false); 6900 - case 3: return mdp_sinsn (operands, MDA_HWORD); 6901 - case 4: return TARGET_MAC ? \"mf%1%S0 %0\" : \"mf%1 %0\"; 6902 - case 5: return TARGET_MAC ? \"mt%0%S1 %1\" : \"mt%0 %1\"; 6903 - case 6: return \"mfsr %0, %1\"; 6904 - case 7: return \"mtsr %1, %0\"; 6905 + case 0: return score_limm (operands); 6906 + case 1: return \"mv!\t%0, %1\"; 6907 + case 2: return score_linsn (operands, SCORE_HWORD, false); 6908 + case 3: return score_sinsn (operands, SCORE_HWORD); 6909 + case 4: return TARGET_SCORE3D ? \"mf%1%S0\t%0\" : \"mf%1\t%0\"; 6910 + case 5: return TARGET_SCORE3D ? \"mt%0%S1\t%1\" : \"mt%0\t%1\"; 6911 + case 6: return \"mfsr\t%0, %1\"; 6912 + case 7: return \"mtsr\t%1, %0\"; 6913 default: gcc_unreachable (); 6914 } 6915 } 6916 [(set_attr "type" "arith,move,load,store,fce,tce,fsr,tsr") 6917 + (set_attr "length" "6,2,6,6,4,4,4,4") 6918 (set_attr "mode" "HI")]) 6919 6920 (define_expand "movsi" 6921 @@ -165,33 +212,62 @@ 6922 } 6923 }) 6924 6925 -(define_insn "*movsi_insns" 6926 +(define_insn "*movsi_insns_score7" 6927 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,m,d,*x,d,*a,d,*c") 6928 (match_operand:SI 1 "general_operand" "i,d,m,d,*x,d,*a,d,*c,d"))] 6929 - "!MEM_P (operands[0]) || register_operand (operands[1], SImode)" 6930 + "(!MEM_P (operands[0]) || register_operand (operands[1], SImode)) 6931 + && (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 6932 { 6933 switch (which_alternative) 6934 { 6935 case 0: 6936 if (GET_CODE (operands[1]) != CONST_INT) 6937 - return \"la %0, %1\"; 6938 + return \"la\t%0, %1\"; 6939 else 6940 - return mdp_limm (operands); 6941 - case 1: return mdp_move (operands); 6942 - case 2: return mdp_linsn (operands, MDA_WORD, false); 6943 - case 3: return mdp_sinsn (operands, MDA_WORD); 6944 - case 4: return TARGET_MAC ? \"mf%1%S0 %0\" : \"mf%1 %0\"; 6945 - case 5: return TARGET_MAC ? \"mt%0%S1 %1\" : \"mt%0 %1\"; 6946 - case 6: return \"mfsr %0, %1\"; 6947 - case 7: return \"mtsr %1, %0\"; 6948 - case 8: return \"mfcr %0, %1\"; 6949 - case 9: return \"mtcr %1, %0\"; 6950 + return score_limm (operands); 6951 + case 1: return score_move (operands); 6952 + case 2: return score_linsn (operands, SCORE_WORD, false); 6953 + case 3: return score_sinsn (operands, SCORE_WORD); 6954 + case 4: return TARGET_SCORE7D ? \"mf%1%S0 %0\" : \"mf%1 %0\"; 6955 + case 5: return TARGET_SCORE7D ? \"mt%0%S1 %1\" : \"mt%0 %1\"; 6956 + case 6: return \"mfsr\t%0, %1\"; 6957 + case 7: return \"mtsr\t%1, %0\"; 6958 + case 8: return \"mfcr\t%0, %1\"; 6959 + case 9: return \"mtcr\t%1, %0\"; 6960 default: gcc_unreachable (); 6961 } 6962 } 6963 [(set_attr "type" "arith,move,load,store,fce,tce,fsr,tsr,fcr,tcr") 6964 (set_attr "mode" "SI")]) 6965 6966 +(define_insn "*movsi_insns_score3" 6967 + [(set (match_operand:SI 0 "nonimmediate_operand" "=ed,e,d,d,m,d,*x,d,*a") 6968 + (match_operand:SI 1 "general_operand" "i,e,d,m,d,*x,d,*a,d"))] 6969 + "(!MEM_P (operands[0]) || register_operand (operands[1], SImode)) 6970 + && (TARGET_SCORE3)" 6971 +{ 6972 + switch (which_alternative) 6973 + { 6974 + case 0: 6975 + if (GET_CODE (operands[1]) != CONST_INT) 6976 + return \"ldi48\t%0, %1\"; 6977 + else 6978 + return score_limm (operands); 6979 + case 1: return \"mv!\t%0, %1\"; 6980 + case 2: return \"mv!\t%0, %1\"; 6981 + case 3: return score_linsn (operands, SCORE_WORD, false); 6982 + case 4: return score_sinsn (operands, SCORE_WORD); 6983 + case 5: return TARGET_SCORE3D ? \"mf%1%S0\t%0\" : \"mf%1\t%0\"; 6984 + case 6: return TARGET_SCORE3D ? \"mt%0%S1\t%1\" : \"mt%0\t%1\"; 6985 + case 7: return \"mfsr\t%0, %1\"; 6986 + case 8: return \"mtsr\t%1, %0\"; 6987 + default: gcc_unreachable (); 6988 + } 6989 +} 6990 + [(set_attr "type" "arith,move,move,load,store,fce,tce,fsr,tsr") 6991 + (set_attr "length" "6,2,2,6,6,4,4,4,4") 6992 + (set_attr "mode" "SI")]) 6993 + 6994 (define_insn_and_split "movdi" 6995 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,d,*x") 6996 (match_operand:DI 1 "general_operand" "i,d,m,d,*x,d"))] 6997 @@ -200,7 +276,7 @@ 6998 "reload_completed" 6999 [(const_int 0)] 7000 { 7001 - mds_movdi (operands); 7002 + score_movdi (operands); 7003 DONE; 7004 }) 7005 7006 @@ -216,21 +292,41 @@ 7007 } 7008 }) 7009 7010 -(define_insn "*movsf_insns" 7011 +(define_insn "*movsf_insns_score7" 7012 + [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,d,m") 7013 + (match_operand:SF 1 "general_operand" "i,d,m,d"))] 7014 + "(!MEM_P (operands[0]) || register_operand (operands[1], SFmode)) 7015 + && (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 7016 +{ 7017 + switch (which_alternative) 7018 + { 7019 + case 0: return \"li\t%0, %D1\";; 7020 + case 1: return score_move (operands); 7021 + case 2: return score_linsn (operands, SCORE_WORD, false); 7022 + case 3: return score_sinsn (operands, SCORE_WORD); 7023 + default: gcc_unreachable (); 7024 + } 7025 +} 7026 + [(set_attr "type" "arith,move,load,store") 7027 + (set_attr "mode" "SI")]) 7028 + 7029 +(define_insn "*movsf_insns_score3" 7030 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,d,m") 7031 (match_operand:SF 1 "general_operand" "i,d,m,d"))] 7032 - "!MEM_P (operands[0]) || register_operand (operands[1], SFmode)" 7033 + "(!MEM_P (operands[0]) || register_operand (operands[1], SFmode)) 7034 + && (TARGET_SCORE3)" 7035 { 7036 switch (which_alternative) 7037 { 7038 - case 0: return \"li %0, %D1\";; 7039 - case 1: return mdp_move (operands); 7040 - case 2: return mdp_linsn (operands, MDA_WORD, false); 7041 - case 3: return mdp_sinsn (operands, MDA_WORD); 7042 + case 0: return \"li\t%0, %D1\"; 7043 + case 1: return \"mv!\t%0, %1\"; 7044 + case 2: return score_linsn (operands, SCORE_WORD, false); 7045 + case 3: return score_sinsn (operands, SCORE_WORD); 7046 default: gcc_unreachable (); 7047 } 7048 } 7049 [(set_attr "type" "arith,move,load,store") 7050 + (set_attr "length" "4,2,6,6") 7051 (set_attr "mode" "SI")]) 7052 7053 (define_insn_and_split "movdf" 7054 @@ -241,51 +337,101 @@ 7055 "reload_completed" 7056 [(const_int 0)] 7057 { 7058 - mds_movdi (operands); 7059 + score_movdi (operands); 7060 DONE; 7061 }) 7062 7063 -(define_insn "addsi3" 7064 +(define_expand "addsi3" 7065 + [(set (match_operand:SI 0 "score_register_operand" ) 7066 + (plus:SI (match_operand:SI 1 "score_register_operand") 7067 + (match_operand:SI 2 "arith_operand")))] 7068 + "" 7069 + "" 7070 +) 7071 + 7072 +(define_insn "*addsi3_score7" 7073 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") 7074 (plus:SI (match_operand:SI 1 "register_operand" "0,0,d,d") 7075 (match_operand:SI 2 "arith_operand" "I,L,N,d")))] 7076 - "" 7077 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 7078 +{ 7079 + switch (which_alternative) 7080 + { 7081 + case 0: return \"addis\t%0, %U2\"; 7082 + case 1: return score_select_add_imm (operands, false); 7083 + case 2: return \"addri\t%0, %1, %c2\"; 7084 + case 3: return score_select (operands, "add", true, "", false); 7085 + default: gcc_unreachable (); 7086 + } 7087 +} 7088 + [(set_attr "type" "arith") 7089 + (set_attr "mode" "SI")]) 7090 + 7091 +(define_insn "*addsi3_score3" 7092 + [(set (match_operand:SI 0 "score_register_operand" "=d,d,d,d") 7093 + (plus:SI (match_operand:SI 1 "score_register_operand" "%0,0,d,d") 7094 + (match_operand:SI 2 "arith_operand" "I,L,N,d")))] 7095 + "(TARGET_SCORE3)" 7096 { 7097 switch (which_alternative) 7098 { 7099 - case 0: return \"addis %0, %U2\"; 7100 - case 1: return mdp_select_add_imm (operands, false); 7101 - case 2: return \"addri %0, %1, %c2\"; 7102 - case 3: return mdp_select (operands, "add", true, "", false); 7103 + case 0: return \"addis\t%0, %U2\"; 7104 + case 1: return score_select_add_imm (operands, false); 7105 + case 2: return \"addri\t%0, %1, %c2\"; 7106 + case 3: return score_select (operands, "add", true, "", false); 7107 default: gcc_unreachable (); 7108 } 7109 } 7110 [(set_attr "type" "arith") 7111 + (set_attr "length" "4,4,4,4") 7112 (set_attr "mode" "SI")]) 7113 7114 -(define_insn "*addsi3_cmp" 7115 +(define_insn "*addsi3_cmp_score7" 7116 [(set (reg:CC_NZ CC_REGNUM) 7117 (compare:CC_NZ (plus:SI 7118 (match_operand:SI 1 "register_operand" "0,0,d,d") 7119 (match_operand:SI 2 "arith_operand" "I,L,N,d")) 7120 (const_int 0))) 7121 (clobber (match_scratch:SI 0 "=d,d,d,d"))] 7122 - "" 7123 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 7124 +{ 7125 + switch (which_alternative) 7126 + { 7127 + case 0: return \"addis.c\t%0, %U2\"; 7128 + case 1: return score_select_add_imm (operands, true); 7129 + case 2: return \"addri.c\t%0, %1, %c2\"; 7130 + case 3: return score_select (operands, "add", true, "", true); 7131 + default: gcc_unreachable (); 7132 + } 7133 +} 7134 + [(set_attr "type" "arith") 7135 + (set_attr "up_c" "yes") 7136 + (set_attr "mode" "SI")]) 7137 + 7138 +(define_insn "*addsi3_cmp_score3" 7139 + [(set (reg:CC_NZ CC_REGNUM) 7140 + (compare:CC_NZ (plus:SI 7141 + (match_operand:SI 1 "score_register_operand" "0,0,d,d") 7142 + (match_operand:SI 2 "arith_operand" "I,L,N,d")) 7143 + (const_int 0))) 7144 + (clobber (match_scratch:SI 0 "=d,d,d,d"))] 7145 + "(TARGET_SCORE3)" 7146 { 7147 switch (which_alternative) 7148 { 7149 - case 0: return \"addis.c %0, %U2\"; 7150 - case 1: return mdp_select_add_imm (operands, true); 7151 - case 2: return \"addri.c %0, %1, %c2\"; 7152 - case 3: return mdp_select (operands, "add", true, "", true); 7153 + case 0: return \"addis.c\t%0, %U2\"; 7154 + case 1: return score_select_add_imm (operands, true); 7155 + case 2: return \"addri.c\t%0, %1, %c2\"; 7156 + case 3: return score_select (operands, "add", true, "", true); 7157 default: gcc_unreachable (); 7158 } 7159 } 7160 [(set_attr "type" "arith") 7161 + (set_attr "length" "4,4,4,4") 7162 (set_attr "up_c" "yes") 7163 (set_attr "mode" "SI")]) 7164 7165 -(define_insn "*addsi3_ucc" 7166 +(define_insn "*addsi3_ucc_score7" 7167 [(set (reg:CC_NZ CC_REGNUM) 7168 (compare:CC_NZ (plus:SI 7169 (match_operand:SI 1 "register_operand" "0,0,d,d") 7170 @@ -293,55 +439,140 @@ 7171 (const_int 0))) 7172 (set (match_operand:SI 0 "register_operand" "=d,d,d,d") 7173 (plus:SI (match_dup 1) (match_dup 2)))] 7174 - "" 7175 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 7176 +{ 7177 + switch (which_alternative) 7178 + { 7179 + case 0: return \"addis.c\t%0, %U2\"; 7180 + case 1: return score_select_add_imm (operands, true); 7181 + case 2: return \"addri.c\t%0, %1, %c2\"; 7182 + case 3: return score_select (operands, "add", true, "", true); 7183 + default: gcc_unreachable (); 7184 + } 7185 +} 7186 + [(set_attr "type" "arith") 7187 + (set_attr "up_c" "yes") 7188 + (set_attr "mode" "SI")]) 7189 + 7190 +(define_insn "*addsi3_ucc_score3" 7191 + [(set (reg:CC_NZ CC_REGNUM) 7192 + (compare:CC_NZ (plus:SI 7193 + (match_operand:SI 1 "score_register_operand" "0,0,d,d") 7194 + (match_operand:SI 2 "arith_operand" "I,L,N,d")) 7195 + (const_int 0))) 7196 + (set (match_operand:SI 0 "score_register_operand" "=d,d,d,d") 7197 + (plus:SI (match_dup 1) (match_dup 2)))] 7198 + "(TARGET_SCORE3)" 7199 { 7200 switch (which_alternative) 7201 { 7202 - case 0: return \"addis.c %0, %U2\"; 7203 - case 1: return mdp_select_add_imm (operands, true); 7204 - case 2: return \"addri.c %0, %1, %c2\"; 7205 - case 3: return mdp_select (operands, "add", true, "", true); 7206 + case 0: return \"addis.c\t%0, %U2\"; 7207 + case 1: return score_select_add_imm (operands, true); 7208 + case 2: return \"addri.c\t%0, %1, %c2\"; 7209 + case 3: return score_select (operands, "add", true, "", true); 7210 default: gcc_unreachable (); 7211 } 7212 } 7213 [(set_attr "type" "arith") 7214 + (set_attr "length" "4,4,4,4") 7215 (set_attr "up_c" "yes") 7216 (set_attr "mode" "SI")]) 7217 7218 -(define_insn "adddi3" 7219 +(define_expand "adddi3" 7220 + [(parallel 7221 + [(set (match_operand:DI 0 "score_register_operand") 7222 + (plus:DI (match_operand:DI 1 "score_register_operand") 7223 + (match_operand:DI 2 "score_register_operand"))) 7224 + (clobber (reg:CC CC_REGNUM))])] 7225 + "" 7226 + "" 7227 +) 7228 + 7229 +(define_insn "*adddi3_score7" 7230 [(set (match_operand:DI 0 "register_operand" "=e,d") 7231 (plus:DI (match_operand:DI 1 "register_operand" "0,d") 7232 (match_operand:DI 2 "register_operand" "e,d"))) 7233 (clobber (reg:CC CC_REGNUM))] 7234 - "" 7235 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 7236 "@ 7237 add! %L0, %L2\;addc! %H0, %H2 7238 add.c %L0, %L1, %L2\;addc %H0, %H1, %H2" 7239 [(set_attr "type" "arith") 7240 (set_attr "mode" "DI")]) 7241 7242 -(define_insn "subsi3" 7243 +(define_insn "*adddi3_score3" 7244 + [(set (match_operand:DI 0 "score_register_operand" "=d") 7245 + (plus:DI (match_operand:DI 1 "score_register_operand" "d") 7246 + (match_operand:DI 2 "score_register_operand" "d"))) 7247 + (clobber (reg:CC CC_REGNUM))] 7248 + "(TARGET_SCORE3)" 7249 + "add.c\t%L0, %L1, %L2\;addc\t%H0, %H1, %H2" 7250 + [(set_attr "type" "arith") 7251 + (set_attr "length" "8") 7252 + (set_attr "mode" "DI")]) 7253 + 7254 +(define_expand "subsi3" 7255 + [(set (match_operand:SI 0 "score_register_operand") 7256 + (minus:SI (match_operand:SI 1 "score_register_operand") 7257 + (match_operand:SI 2 "score_register_operand")))] 7258 + "" 7259 + "" 7260 +) 7261 + 7262 +(define_insn "*subsi3_score7" 7263 [(set (match_operand:SI 0 "register_operand" "=d") 7264 (minus:SI (match_operand:SI 1 "register_operand" "d") 7265 (match_operand:SI 2 "register_operand" "d")))] 7266 - "" 7267 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 7268 +{ 7269 + return score_select (operands, "sub", false, "", false); 7270 +} 7271 + [(set_attr "type" "arith") 7272 + (set_attr "mode" "SI")]) 7273 + 7274 +(define_insn "*subsi3_score3" 7275 + [(set (match_operand:SI 0 "score_register_operand" "=e,d") 7276 + (minus:SI (match_operand:SI 1 "score_register_operand" "0,d") 7277 + (match_operand:SI 2 "score_register_operand" "e,d")))] 7278 + "(TARGET_SCORE3)" 7279 { 7280 - return mdp_select (operands, "sub", false, "", false); 7281 + switch (which_alternative) 7282 + { 7283 + case 0: return \"sub!\t%0, %2\"; 7284 + case 1: return score_select (operands, "sub", false, "", false); 7285 + default: gcc_unreachable (); 7286 + } 7287 } 7288 [(set_attr "type" "arith") 7289 + (set_attr "length" "2,4") 7290 (set_attr "mode" "SI")]) 7291 7292 -(define_insn "*subsi3_cmp" 7293 +(define_insn "*subsi3_cmp_score7" 7294 [(set (reg:CC_NZ CC_REGNUM) 7295 (compare:CC_NZ (minus:SI (match_operand:SI 1 "register_operand" "d") 7296 (match_operand:SI 2 "register_operand" "d")) 7297 (const_int 0))) 7298 (clobber (match_scratch:SI 0 "=d"))] 7299 - "" 7300 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 7301 +{ 7302 + return score_select (operands, "sub", false, "", true); 7303 +} 7304 + [(set_attr "type" "arith") 7305 + (set_attr "up_c" "yes") 7306 + (set_attr "mode" "SI")]) 7307 + 7308 +(define_insn "*subsi3_cmp_score3" 7309 + [(set (reg:CC_NZ CC_REGNUM) 7310 + (compare:CC_NZ (minus:SI (match_operand:SI 1 "score_register_operand" "d") 7311 + (match_operand:SI 2 "score_register_operand" "d")) 7312 + (const_int 0))) 7313 + (clobber (match_scratch:SI 0 "=d"))] 7314 + "(TARGET_SCORE3)" 7315 { 7316 - return mdp_select (operands, "sub", false, "", true); 7317 + return score_select (operands, "sub", false, "", true); 7318 } 7319 [(set_attr "type" "arith") 7320 + (set_attr "length" "4") 7321 (set_attr "up_c" "yes") 7322 (set_attr "mode" "SI")]) 7323 7324 @@ -359,86 +590,159 @@ 7325 7326 (define_insn "subsi3_ucc_pcmp" 7327 [(parallel 7328 - [(set (reg:CC CC_REGNUM) 7329 - (compare:CC (match_operand:SI 1 "register_operand" "d") 7330 - (match_operand:SI 2 "register_operand" "d"))) 7331 - (set (match_operand:SI 0 "register_operand" "=d") 7332 - (minus:SI (match_dup 1) (match_dup 2)))])] 7333 + [(set (reg:CC CC_REGNUM) 7334 + (compare:CC (match_operand:SI 1 "score_register_operand" "d") 7335 + (match_operand:SI 2 "score_register_operand" "d"))) 7336 + (set (match_operand:SI 0 "score_register_operand" "=d") 7337 + (minus:SI (match_dup 1) (match_dup 2)))])] 7338 "" 7339 { 7340 - return mdp_select (operands, "sub", false, "", true); 7341 + return score_select (operands, "sub", false, "", true); 7342 } 7343 [(set_attr "type" "arith") 7344 + (set_attr "length" "4") 7345 (set_attr "up_c" "yes") 7346 (set_attr "mode" "SI")]) 7347 7348 (define_insn "subsi3_ucc" 7349 [(set (reg:CC_NZ CC_REGNUM) 7350 - (compare:CC_NZ (minus:SI (match_operand:SI 1 "register_operand" "d") 7351 - (match_operand:SI 2 "register_operand" "d")) 7352 + (compare:CC_NZ (minus:SI (match_operand:SI 1 "score_register_operand" "d") 7353 + (match_operand:SI 2 "score_register_operand" "d")) 7354 (const_int 0))) 7355 - (set (match_operand:SI 0 "register_operand" "=d") 7356 + (set (match_operand:SI 0 "score_register_operand" "=d") 7357 (minus:SI (match_dup 1) (match_dup 2)))] 7358 "" 7359 { 7360 - return mdp_select (operands, "sub", false, "", true); 7361 + return score_select (operands, "sub", false, "", true); 7362 } 7363 [(set_attr "type" "arith") 7364 + (set_attr "length" "4") 7365 (set_attr "up_c" "yes") 7366 (set_attr "mode" "SI")]) 7367 7368 -(define_insn "subdi3" 7369 +(define_expand "subdi3" 7370 + [(parallel 7371 + [(set (match_operand:DI 0 "score_register_operand") 7372 + (minus:DI (match_operand:DI 1 "score_register_operand") 7373 + (match_operand:DI 2 "score_register_operand"))) 7374 + (clobber (reg:CC CC_REGNUM))])] 7375 + "" 7376 + "" 7377 +) 7378 + 7379 +(define_insn "*subdi3_score7" 7380 [(set (match_operand:DI 0 "register_operand" "=e,d") 7381 (minus:DI (match_operand:DI 1 "register_operand" "0,d") 7382 (match_operand:DI 2 "register_operand" "e,d"))) 7383 (clobber (reg:CC CC_REGNUM))] 7384 - "" 7385 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 7386 "@ 7387 sub! %L0, %L2\;subc %H0, %H1, %H2 7388 sub.c %L0, %L1, %L2\;subc %H0, %H1, %H2" 7389 [(set_attr "type" "arith") 7390 (set_attr "mode" "DI")]) 7391 7392 -(define_insn "andsi3" 7393 +(define_insn "*subdi3_score3" 7394 + [(set (match_operand:DI 0 "score_register_operand" "=d") 7395 + (minus:DI (match_operand:DI 1 "score_register_operand" "d") 7396 + (match_operand:DI 2 "score_register_operand" "d"))) 7397 + (clobber (reg:CC CC_REGNUM))] 7398 + "(TARGET_SCORE3)" 7399 + "sub.c\t%L0, %L1, %L2\;subc\t%H0, %H1, %H2" 7400 + [(set_attr "type" "arith") 7401 + (set_attr "length" "8") 7402 + (set_attr "mode" "DI")]) 7403 + 7404 +(define_expand "andsi3" 7405 + [(set (match_operand:SI 0 "score_register_operand") 7406 + (and:SI (match_operand:SI 1 "score_register_operand") 7407 + (match_operand:SI 2 "arith_operand")))] 7408 + "" 7409 + "" 7410 +) 7411 + 7412 +(define_insn "*andsi3_score7" 7413 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") 7414 (and:SI (match_operand:SI 1 "register_operand" "0,0,d,d") 7415 (match_operand:SI 2 "arith_operand" "I,K,M,d")))] 7416 - "" 7417 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 7418 { 7419 switch (which_alternative) 7420 { 7421 - case 0: return \"andis %0, %U2\"; 7422 - case 1: return \"andi %0, %c2"; 7423 - case 2: return \"andri %0, %1, %c2\"; 7424 - case 3: return mdp_select (operands, "and", true, "", false); 7425 + case 0: return \"andis\t%0, %U2\"; 7426 + case 1: return \"andi\t%0, %c2"; 7427 + case 2: return \"andri\t%0, %1, %c2\"; 7428 + case 3: return score_select (operands, "and", true, "", false); 7429 default: gcc_unreachable (); 7430 } 7431 } 7432 [(set_attr "type" "arith") 7433 (set_attr "mode" "SI")]) 7434 7435 -(define_insn "andsi3_cmp" 7436 +(define_insn "*andsi3_score3" 7437 + [(set (match_operand:SI 0 "score_register_operand" "=e,d,d,d,d") 7438 + (and:SI (match_operand:SI 1 "score_register_operand" "%0,0,0,d,d") 7439 + (match_operand:SI 2 "arith_operand" "e,I,K,M,d")))] 7440 + "(TARGET_SCORE3)" 7441 +{ 7442 + switch (which_alternative) 7443 + { 7444 + case 0: return \"and!\t%0, %2\"; 7445 + case 1: return \"andis\t%0, %U2\"; 7446 + case 2: return \"andi\t%0, %c2"; 7447 + case 3: return \"andri\t%0, %1, %c2\"; 7448 + case 4: return score_select (operands, "and", true, "", false); 7449 + default: gcc_unreachable (); 7450 + } 7451 +} 7452 + [(set_attr "type" "arith") 7453 + (set_attr "length" "2,4,4,4,4") 7454 + (set_attr "mode" "SI")]) 7455 + 7456 +(define_insn "andsi3_cmp_score7" 7457 [(set (reg:CC_NZ CC_REGNUM) 7458 (compare:CC_NZ (and:SI (match_operand:SI 1 "register_operand" "0,0,0,d") 7459 (match_operand:SI 2 "arith_operand" "I,K,M,d")) 7460 (const_int 0))) 7461 (clobber (match_scratch:SI 0 "=d,d,d,d"))] 7462 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 7463 +{ 7464 + switch (which_alternative) 7465 + { 7466 + case 0: return \"andis.c\t%0, %U2\"; 7467 + case 1: return \"andi.c\t%0, %c2"; 7468 + case 2: return \"andri.c\t%0, %1, %c2\"; 7469 + case 3: return score_select (operands, "and", true, "", true); 7470 + default: gcc_unreachable (); 7471 + } 7472 +} 7473 + [(set_attr "type" "arith") 7474 + (set_attr "up_c" "yes") 7475 + (set_attr "mode" "SI")]) 7476 + 7477 +(define_insn "andsi3_cmp_score3" 7478 + [(set (reg:CC_NZ CC_REGNUM) 7479 + (compare:CC_NZ (and:SI (match_operand:SI 1 "score_register_operand" "0,0,0,d") 7480 + (match_operand:SI 2 "arith_operand" "I,K,M,d")) 7481 + (const_int 0))) 7482 + (clobber (match_scratch:SI 0 "=d,d,d,d"))] 7483 "" 7484 { 7485 switch (which_alternative) 7486 { 7487 - case 0: return \"andis.c %0, %U2\"; 7488 - case 1: return \"andi.c %0, %c2"; 7489 - case 2: return \"andri.c %0, %1, %c2\"; 7490 - case 3: return mdp_select (operands, "and", true, "", true); 7491 + case 0: return \"andis.c\t%0, %U2\"; 7492 + case 1: return \"andi.c\t%0, %c2"; 7493 + case 2: return \"andri.c\t%0, %1, %c2\"; 7494 + case 3: return score_select (operands, "and", true, "", true); 7495 default: gcc_unreachable (); 7496 } 7497 } 7498 [(set_attr "type" "arith") 7499 + (set_attr "length" "4,4,4,4") 7500 (set_attr "up_c" "yes") 7501 (set_attr "mode" "SI")]) 7502 7503 -(define_insn "*andsi3_ucc" 7504 +(define_insn "*andsi3_ucc_score7" 7505 [(set (reg:CC_NZ CC_REGNUM) 7506 (compare:CC_NZ (and:SI 7507 (match_operand:SI 1 "register_operand" "0,0,d,d") 7508 @@ -446,25 +750,50 @@ 7509 (const_int 0))) 7510 (set (match_operand:SI 0 "register_operand" "=d,d,d,d") 7511 (and:SI (match_dup 1) (match_dup 2)))] 7512 - "" 7513 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 7514 +{ 7515 + switch (which_alternative) 7516 + { 7517 + case 0: return \"andis.c\t%0, %U2\"; 7518 + case 1: return \"andi.c\t%0, %c2"; 7519 + case 2: return \"andri.c\t%0, %1, %c2\"; 7520 + case 3: return score_select (operands, "and", true, "", true); 7521 + default: gcc_unreachable (); 7522 + } 7523 +} 7524 + [(set_attr "type" "arith") 7525 + (set_attr "up_c" "yes") 7526 + (set_attr "mode" "SI")]) 7527 + 7528 +(define_insn "*andsi3_ucc_score3" 7529 + [(set (reg:CC_NZ CC_REGNUM) 7530 + (compare:CC_NZ (and:SI 7531 + (match_operand:SI 1 "score_register_operand" "0,0,d,d") 7532 + (match_operand:SI 2 "arith_operand" "I,K,M,d")) 7533 + (const_int 0))) 7534 + (set (match_operand:SI 0 "score_register_operand" "=d,d,d,d") 7535 + (and:SI (match_dup 1) (match_dup 2)))] 7536 + "(TARGET_SCORE3)" 7537 { 7538 switch (which_alternative) 7539 { 7540 - case 0: return \"andis.c %0, %U2\"; 7541 - case 1: return \"andi.c %0, %c2"; 7542 - case 2: return \"andri.c %0, %1, %c2\"; 7543 - case 3: return mdp_select (operands, "and", true, "", true); 7544 + case 0: return \"andis.c\t%0, %U2\"; 7545 + case 1: return \"andi.c\t%0, %c2"; 7546 + case 2: return \"andri.c\t%0, %1, %c2\"; 7547 + case 3: return score_select (operands, "and", true, "", true); 7548 default: gcc_unreachable (); 7549 } 7550 } 7551 [(set_attr "type" "arith") 7552 + (set_attr "length" "4,4,4,4") 7553 (set_attr "up_c" "yes") 7554 (set_attr "mode" "SI")]) 7555 7556 + 7557 (define_insn_and_split "*zero_extract_andi" 7558 [(set (reg:CC CC_REGNUM) 7559 (compare:CC (zero_extract:SI 7560 - (match_operand:SI 0 "register_operand" "d") 7561 + (match_operand:SI 0 "score_register_operand" "d") 7562 (match_operand:SI 1 "const_uimm5" "") 7563 (match_operand:SI 2 "const_uimm5" "")) 7564 (const_int 0)))] 7565 @@ -473,29 +802,57 @@ 7566 "" 7567 [(const_int 1)] 7568 { 7569 - mds_zero_extract_andi (operands); 7570 + score_zero_extract_andi (operands); 7571 DONE; 7572 }) 7573 7574 -(define_insn "iorsi3" 7575 +(define_expand "iorsi3" 7576 + [(set (match_operand:SI 0 "score_register_operand") 7577 + (ior:SI (match_operand:SI 1 "score_register_operand") 7578 + (match_operand:SI 2 "arith_operand")))] 7579 + "" 7580 + "" 7581 +) 7582 + 7583 +(define_insn "*iorsi3_score7" 7584 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") 7585 (ior:SI (match_operand:SI 1 "register_operand" "0,0,d,d") 7586 (match_operand:SI 2 "arith_operand" "I,K,M,d")))] 7587 - "" 7588 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 7589 +{ 7590 + switch (which_alternative) 7591 + { 7592 + case 0: return \"oris\t%0, %U2\"; 7593 + case 1: return \"ori\t%0, %c2\"; 7594 + case 2: return \"orri\t%0, %1, %c2\"; 7595 + case 3: return score_select (operands, "or", true, "", false); 7596 + default: gcc_unreachable (); 7597 + } 7598 +} 7599 + [(set_attr "type" "arith") 7600 + (set_attr "mode" "SI")]) 7601 + 7602 +(define_insn "*iorsi3_score3" 7603 + [(set (match_operand:SI 0 "score_register_operand" "=e,d,d,d,d") 7604 + (ior:SI (match_operand:SI 1 "score_register_operand" "%0,0,0,d,d") 7605 + (match_operand:SI 2 "arith_operand" "e,I,K,M,d")))] 7606 + "(TARGET_SCORE3)" 7607 { 7608 switch (which_alternative) 7609 { 7610 - case 0: return \"oris %0, %U2\"; 7611 - case 1: return \"ori %0, %c2\"; 7612 - case 2: return \"orri %0, %1, %c2\"; 7613 - case 3: return mdp_select (operands, "or", true, "", false); 7614 + case 0: return \"or!\t%0, %2\"; 7615 + case 1: return \"oris\t%0, %U2\"; 7616 + case 2: return \"ori\t%0, %c2\"; 7617 + case 3: return \"orri\t%0, %1, %c2\"; 7618 + case 4: return score_select (operands, "or", true, "", false); 7619 default: gcc_unreachable (); 7620 } 7621 } 7622 [(set_attr "type" "arith") 7623 + (set_attr "length" "2,4,4,4,4") 7624 (set_attr "mode" "SI")]) 7625 7626 -(define_insn "iorsi3_ucc" 7627 +(define_insn "*iorsi3_ucc_score7" 7628 [(set (reg:CC_NZ CC_REGNUM) 7629 (compare:CC_NZ (ior:SI 7630 (match_operand:SI 1 "register_operand" "0,0,d,d") 7631 @@ -503,70 +860,155 @@ 7632 (const_int 0))) 7633 (set (match_operand:SI 0 "register_operand" "=d,d,d,d") 7634 (ior:SI (match_dup 1) (match_dup 2)))] 7635 - "" 7636 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 7637 +{ 7638 + switch (which_alternative) 7639 + { 7640 + case 0: return \"oris.c\t%0, %U2\"; 7641 + case 1: return \"ori.c\t%0, %c2\"; 7642 + case 2: return \"orri.c\t%0, %1, %c2\"; 7643 + case 3: return score_select (operands, "or", true, "", true); 7644 + default: gcc_unreachable (); 7645 + } 7646 +} 7647 + [(set_attr "type" "arith") 7648 + (set_attr "up_c" "yes") 7649 + (set_attr "mode" "SI")]) 7650 + 7651 +(define_insn "*iorsi3_ucc_score3" 7652 + [(set (reg:CC_NZ CC_REGNUM) 7653 + (compare:CC_NZ (ior:SI 7654 + (match_operand:SI 1 "score_register_operand" "0,0,d,d") 7655 + (match_operand:SI 2 "arith_operand" "I,K,M,d")) 7656 + (const_int 0))) 7657 + (set (match_operand:SI 0 "score_register_operand" "=d,d,d,d") 7658 + (ior:SI (match_dup 1) (match_dup 2)))] 7659 + "(TARGET_SCORE3)" 7660 { 7661 switch (which_alternative) 7662 { 7663 - case 0: return \"oris.c %0, %U2\"; 7664 - case 1: return \"ori.c %0, %c2\"; 7665 - case 2: return \"orri.c %0, %1, %c2\"; 7666 - case 3: return mdp_select (operands, "or", true, "", true); 7667 + case 0: return \"oris.c\t%0, %U2\"; 7668 + case 1: return \"ori.c\t%0, %c2\"; 7669 + case 2: return \"orri.c\t%0, %1, %c2\"; 7670 + case 3: return score_select (operands, "or", true, "", true); 7671 default: gcc_unreachable (); 7672 } 7673 } 7674 [(set_attr "type" "arith") 7675 + (set_attr "length" "4,4,4,4") 7676 (set_attr "up_c" "yes") 7677 (set_attr "mode" "SI")]) 7678 7679 -(define_insn "iorsi3_cmp" 7680 +(define_insn "*iorsi3_cmp_score7" 7681 [(set (reg:CC_NZ CC_REGNUM) 7682 (compare:CC_NZ (ior:SI 7683 (match_operand:SI 1 "register_operand" "0,0,d,d") 7684 (match_operand:SI 2 "arith_operand" "I,K,M,d")) 7685 (const_int 0))) 7686 (clobber (match_scratch:SI 0 "=d,d,d,d"))] 7687 - "" 7688 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 7689 +{ 7690 + switch (which_alternative) 7691 + { 7692 + case 0: return \"oris.c\t%0, %U2\"; 7693 + case 1: return \"ori.c\t%0, %c2\"; 7694 + case 2: return \"orri.c\t%0, %1, %c2\"; 7695 + case 3: return score_select (operands, "or", true, "", true); 7696 + default: gcc_unreachable (); 7697 + } 7698 +} 7699 + [(set_attr "type" "arith") 7700 + (set_attr "up_c" "yes") 7701 + (set_attr "mode" "SI")]) 7702 + 7703 +(define_insn "*iorsi3_cmp_score3" 7704 + [(set (reg:CC_NZ CC_REGNUM) 7705 + (compare:CC_NZ (ior:SI 7706 + (match_operand:SI 1 "score_register_operand" "0,0,d,d") 7707 + (match_operand:SI 2 "arith_operand" "I,K,M,d")) 7708 + (const_int 0))) 7709 + (clobber (match_scratch:SI 0 "=d,d,d,d"))] 7710 + "(TARGET_SCORE3)" 7711 { 7712 switch (which_alternative) 7713 { 7714 - case 0: return \"oris.c %0, %U2\"; 7715 - case 1: return \"ori.c %0, %c2\"; 7716 - case 2: return \"orri.c %0, %1, %c2\"; 7717 - case 3: return mdp_select (operands, "or", true, "", true); 7718 + case 0: return \"oris.c\t%0, %U2\"; 7719 + case 1: return \"ori.c\t%0, %c2\"; 7720 + case 2: return \"orri.c\t%0, %1, %c2\"; 7721 + case 3: return score_select (operands, "or", true, "", true); 7722 default: gcc_unreachable (); 7723 } 7724 } 7725 [(set_attr "type" "arith") 7726 + (set_attr "length" "4,4,4,4") 7727 (set_attr "up_c" "yes") 7728 (set_attr "mode" "SI")]) 7729 7730 -(define_insn "xorsi3" 7731 +(define_expand "xorsi3" 7732 + [(set (match_operand:SI 0 "score_register_operand") 7733 + (xor:SI (match_operand:SI 1 "score_register_operand") 7734 + (match_operand:SI 2 "score_register_operand")))] 7735 + "" 7736 + "" 7737 +) 7738 + 7739 +(define_insn "*xorsi3_score7" 7740 [(set (match_operand:SI 0 "register_operand" "=d") 7741 (xor:SI (match_operand:SI 1 "register_operand" "d") 7742 (match_operand:SI 2 "register_operand" "d")))] 7743 - "" 7744 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 7745 +{ 7746 + return score_select (operands, "xor", true, "", false); 7747 +} 7748 + [(set_attr "type" "arith") 7749 + (set_attr "mode" "SI")]) 7750 + 7751 +(define_insn "*xorsi3_score3" 7752 + [(set (match_operand:SI 0 "score_register_operand" "=d") 7753 + (xor:SI (match_operand:SI 1 "score_register_operand" "d") 7754 + (match_operand:SI 2 "score_register_operand" "d")))] 7755 + "(TARGET_SCORE3)" 7756 { 7757 - return mdp_select (operands, "xor", true, "", false); 7758 + return score_select (operands, "xor", true, "", false); 7759 } 7760 [(set_attr "type" "arith") 7761 + (set_attr "length" "4") 7762 (set_attr "mode" "SI")]) 7763 7764 -(define_insn "xorsi3_ucc" 7765 + 7766 +(define_insn "*xorsi3_ucc_score7" 7767 [(set (reg:CC_NZ CC_REGNUM) 7768 (compare:CC_NZ (xor:SI (match_operand:SI 1 "register_operand" "d") 7769 (match_operand:SI 2 "register_operand" "d")) 7770 (const_int 0))) 7771 (set (match_operand:SI 0 "register_operand" "=d") 7772 (xor:SI (match_dup 1) (match_dup 2)))] 7773 - "" 7774 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 7775 +{ 7776 + return score_select (operands, "xor", true, "", true); 7777 +} 7778 + [(set_attr "type" "arith") 7779 + (set_attr "up_c" "yes") 7780 + (set_attr "mode" "SI")]) 7781 + 7782 +(define_insn "*xorsi3_ucc_score3" 7783 + [(set (reg:CC_NZ CC_REGNUM) 7784 + (compare:CC_NZ (xor:SI (match_operand:SI 1 "score_register_operand" "d") 7785 + (match_operand:SI 2 "score_register_operand" "d")) 7786 + (const_int 0))) 7787 + (set (match_operand:SI 0 "score_register_operand" "=d") 7788 + (xor:SI (match_dup 1) (match_dup 2)))] 7789 + "(TARGET_SCORE3)" 7790 { 7791 - return mdp_select (operands, "xor", true, "", true); 7792 + return score_select (operands, "xor", true, "", true); 7793 } 7794 [(set_attr "type" "arith") 7795 + (set_attr "length" "4") 7796 (set_attr "up_c" "yes") 7797 (set_attr "mode" "SI")]) 7798 7799 -(define_insn "xorsi3_cmp" 7800 + 7801 +(define_insn "*xorsi3_cmp_score7" 7802 [(set (reg:CC_NZ CC_REGNUM) 7803 (compare:CC_NZ (xor:SI (match_operand:SI 1 "register_operand" "d") 7804 (match_operand:SI 2 "register_operand" "d")) 7805 @@ -574,28 +1016,66 @@ 7806 (clobber (match_scratch:SI 0 "=d"))] 7807 "" 7808 { 7809 - return mdp_select (operands, "xor", true, "", true); 7810 + return score_select (operands, "xor", true, "", true); 7811 } 7812 [(set_attr "type" "arith") 7813 (set_attr "up_c" "yes") 7814 (set_attr "mode" "SI")]) 7815 7816 -(define_insn "extendqisi2" 7817 - [(set (match_operand:SI 0 "register_operand" "=d,d") 7818 - (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))] 7819 - "" 7820 -{ 7821 +(define_insn "*xorsi3_cmp_score3" 7822 + [(set (reg:CC_NZ CC_REGNUM) 7823 + (compare:CC_NZ (xor:SI (match_operand:SI 1 "score_register_operand" "d") 7824 + (match_operand:SI 2 "score_register_operand" "d")) 7825 + (const_int 0))) 7826 + (clobber (match_scratch:SI 0 "=d"))] 7827 + "" 7828 +{ 7829 + return score_select (operands, "xor", true, "", true); 7830 +} 7831 + [(set_attr "type" "arith") 7832 + (set_attr "length" "4") 7833 + (set_attr "up_c" "yes") 7834 + (set_attr "mode" "SI")]) 7835 + 7836 +(define_expand "extendqisi2" 7837 + [(set (match_operand:SI 0 "score_register_operand") 7838 + (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand")))] 7839 + "" 7840 + "" 7841 +) 7842 + 7843 +(define_insn "*extendqisi2_score7" 7844 + [(set (match_operand:SI 0 "register_operand" "=d,d") 7845 + (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))] 7846 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 7847 +{ 7848 + switch (which_alternative) 7849 + { 7850 + case 0: return \"extsb\t%0, %1\"; 7851 + case 1: return score_linsn (operands, SCORE_BYTE, true); 7852 + default: gcc_unreachable (); 7853 + } 7854 +} 7855 + [(set_attr "type" "arith,load") 7856 + (set_attr "mode" "SI")]) 7857 + 7858 +(define_insn "*extendqisi2_score3" 7859 + [(set (match_operand:SI 0 "score_register_operand" "=d,d") 7860 + (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))] 7861 + "(TARGET_SCORE3)" 7862 +{ 7863 switch (which_alternative) 7864 { 7865 - case 0: return \"extsb %0, %1\"; 7866 - case 1: return mdp_linsn (operands, MDA_BYTE, true); 7867 + case 0: return \"extsb\t%0, %1\"; 7868 + case 1: return score_linsn (operands, SCORE_BYTE, true); 7869 default: gcc_unreachable (); 7870 } 7871 } 7872 [(set_attr "type" "arith,load") 7873 + (set_attr "length" "4,4") 7874 (set_attr "mode" "SI")]) 7875 7876 -(define_insn "*extendqisi2_ucc" 7877 +(define_insn "*extendqisi2_ucc_score7" 7878 [(set (reg:CC_N CC_REGNUM) 7879 (compare:CC_N (ashiftrt:SI 7880 (ashift:SI (match_operand:SI 1 "register_operand" "d") 7881 @@ -604,13 +1084,29 @@ 7882 (const_int 0))) 7883 (set (match_operand:SI 0 "register_operand" "=d") 7884 (sign_extend:SI (match_operand:QI 2 "register_operand" "0")))] 7885 - "" 7886 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 7887 "extsb.c %0, %1" 7888 [(set_attr "type" "arith") 7889 (set_attr "up_c" "yes") 7890 (set_attr "mode" "SI")]) 7891 7892 -(define_insn "*extendqisi2_cmp" 7893 +(define_insn "*extendqisi2_ucc_score3" 7894 + [(set (reg:CC_N CC_REGNUM) 7895 + (compare:CC_N (ashiftrt:SI 7896 + (ashift:SI (match_operand:SI 1 "score_register_operand" "d") 7897 + (const_int 24)) 7898 + (const_int 24)) 7899 + (const_int 0))) 7900 + (set (match_operand:SI 0 "score_register_operand" "=d") 7901 + (sign_extend:SI (match_operand:QI 2 "score_register_operand" "0")))] 7902 + "(TARGET_SCORE3)" 7903 + "extsb.c\t%0, %1" 7904 + [(set_attr "type" "arith") 7905 + (set_attr "length" "4") 7906 + (set_attr "up_c" "yes") 7907 + (set_attr "mode" "SI")]) 7908 + 7909 +(define_insn "*extendqisi2_cmp_score7" 7910 [(set (reg:CC_N CC_REGNUM) 7911 (compare:CC_N (ashiftrt:SI 7912 (ashift:SI (match_operand:SI 1 "register_operand" "d") 7913 @@ -618,28 +1114,66 @@ 7914 (const_int 24)) 7915 (const_int 0))) 7916 (clobber (match_scratch:SI 0 "=d"))] 7917 - "" 7918 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 7919 "extsb.c %0, %1" 7920 [(set_attr "type" "arith") 7921 (set_attr "up_c" "yes") 7922 (set_attr "mode" "SI")]) 7923 7924 -(define_insn "extendhisi2" 7925 +(define_insn "*extendqisi2_cmp_score3" 7926 + [(set (reg:CC_N CC_REGNUM) 7927 + (compare:CC_N (ashiftrt:SI 7928 + (ashift:SI (match_operand:SI 1 "score_register_operand" "d") 7929 + (const_int 24)) 7930 + (const_int 24)) 7931 + (const_int 0))) 7932 + (clobber (match_scratch:SI 0 "=d"))] 7933 + "(TARGET_SCORE3)" 7934 + "extsb.c\t%0, %1" 7935 + [(set_attr "type" "arith") 7936 + (set_attr "length" "4") 7937 + (set_attr "up_c" "yes") 7938 + (set_attr "mode" "SI")]) 7939 + 7940 +(define_expand "extendhisi2" 7941 + [(set (match_operand:SI 0 "score_register_operand") 7942 + (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand")))] 7943 + "" 7944 + "" 7945 +) 7946 + 7947 +(define_insn "*extendhisi2_score7" 7948 [(set (match_operand:SI 0 "register_operand" "=d,d") 7949 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,m")))] 7950 - "" 7951 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 7952 +{ 7953 + switch (which_alternative) 7954 + { 7955 + case 0: return \"extsh\t%0, %1\"; 7956 + case 1: return score_linsn (operands, SCORE_HWORD, true); 7957 + default: gcc_unreachable (); 7958 + } 7959 +} 7960 + [(set_attr "type" "arith, load") 7961 + (set_attr "mode" "SI")]) 7962 + 7963 +(define_insn "*extendhisi2_score3" 7964 + [(set (match_operand:SI 0 "score_register_operand" "=d,d") 7965 + (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,m")))] 7966 + "(TARGET_SCORE3)" 7967 { 7968 switch (which_alternative) 7969 { 7970 - case 0: return \"extsh %0, %1\"; 7971 - case 1: return mdp_linsn (operands, MDA_HWORD, true); 7972 + case 0: return \"extsh\t%0, %1\"; 7973 + case 1: return score_linsn (operands, SCORE_HWORD, true); 7974 default: gcc_unreachable (); 7975 } 7976 } 7977 [(set_attr "type" "arith, load") 7978 + (set_attr "length" "4,4") 7979 (set_attr "mode" "SI")]) 7980 7981 -(define_insn "*extendhisi2_ucc" 7982 +(define_insn "*extendhisi2_ucc_score7" 7983 [(set (reg:CC_N CC_REGNUM) 7984 (compare:CC_N (ashiftrt:SI 7985 (ashift:SI (match_operand:SI 1 "register_operand" "d") 7986 @@ -648,13 +1182,29 @@ 7987 (const_int 0))) 7988 (set (match_operand:SI 0 "register_operand" "=d") 7989 (sign_extend:SI (match_operand:HI 2 "register_operand" "0")))] 7990 - "" 7991 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 7992 "extsh.c %0, %1" 7993 [(set_attr "type" "arith") 7994 (set_attr "up_c" "yes") 7995 (set_attr "mode" "SI")]) 7996 7997 -(define_insn "*extendhisi2_cmp" 7998 +(define_insn "*extendhisi2_ucc_score3" 7999 + [(set (reg:CC_N CC_REGNUM) 8000 + (compare:CC_N (ashiftrt:SI 8001 + (ashift:SI (match_operand:SI 1 "score_register_operand" "d") 8002 + (const_int 16)) 8003 + (const_int 16)) 8004 + (const_int 0))) 8005 + (set (match_operand:SI 0 "score_register_operand" "=d") 8006 + (sign_extend:SI (match_operand:HI 2 "score_register_operand" "0")))] 8007 + "(TARGET_SCORE3)" 8008 + "extsh.c\t%0, %1" 8009 + [(set_attr "type" "arith") 8010 + (set_attr "length" "4") 8011 + (set_attr "up_c" "yes") 8012 + (set_attr "mode" "SI")]) 8013 + 8014 +(define_insn "*extendhisi2_cmp_score7" 8015 [(set (reg:CC_N CC_REGNUM) 8016 (compare:CC_N (ashiftrt:SI 8017 (ashift:SI (match_operand:SI 1 "register_operand" "d") 8018 @@ -662,28 +1212,66 @@ 8019 (const_int 16)) 8020 (const_int 0))) 8021 (clobber (match_scratch:SI 0 "=d"))] 8022 - "" 8023 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 8024 "extsh.c %0, %1" 8025 [(set_attr "type" "arith") 8026 (set_attr "up_c" "yes") 8027 (set_attr "mode" "SI")]) 8028 8029 -(define_insn "zero_extendqisi2" 8030 +(define_insn "*extendhisi2_cmp_score3" 8031 + [(set (reg:CC_N CC_REGNUM) 8032 + (compare:CC_N (ashiftrt:SI 8033 + (ashift:SI (match_operand:SI 1 "score_register_operand" "d") 8034 + (const_int 16)) 8035 + (const_int 16)) 8036 + (const_int 0))) 8037 + (clobber (match_scratch:SI 0 "=d"))] 8038 + "(TARGET_SCORE3)" 8039 + "extsh.c\t%0, %1" 8040 + [(set_attr "type" "arith") 8041 + (set_attr "length" "4") 8042 + (set_attr "up_c" "yes") 8043 + (set_attr "mode" "SI")]) 8044 + 8045 +(define_expand "zero_extendqisi2" 8046 + [(set (match_operand:SI 0 "score_register_operand") 8047 + (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand")))] 8048 + "" 8049 + "" 8050 +) 8051 + 8052 +(define_insn "*zero_extendqisi2_score7" 8053 [(set (match_operand:SI 0 "register_operand" "=d,d") 8054 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))] 8055 - "" 8056 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 8057 +{ 8058 + switch (which_alternative) 8059 + { 8060 + case 0: return \"extzb\t%0, %1\"; 8061 + case 1: return score_linsn (operands, SCORE_BYTE, false); 8062 + default: gcc_unreachable (); 8063 + } 8064 +} 8065 + [(set_attr "type" "arith, load") 8066 + (set_attr "mode" "SI")]) 8067 + 8068 +(define_insn "*zero_extendqisi2_score3" 8069 + [(set (match_operand:SI 0 "score_register_operand" "=d,d") 8070 + (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))] 8071 + "(TARGET_SCORE3)" 8072 { 8073 switch (which_alternative) 8074 { 8075 - case 0: return \"extzb %0, %1\"; 8076 - case 1: return mdp_linsn (operands, MDA_BYTE, false); 8077 + case 0: return \"extzb\t%0, %1\"; 8078 + case 1: return score_linsn (operands, SCORE_BYTE, false); 8079 default: gcc_unreachable (); 8080 } 8081 - } 8082 +} 8083 [(set_attr "type" "arith, load") 8084 + (set_attr "length" "4,4") 8085 (set_attr "mode" "SI")]) 8086 8087 -(define_insn "*zero_extendqisi2_ucc" 8088 +(define_insn "*zero_extendqisi2_ucc_score7" 8089 [(set (reg:CC_N CC_REGNUM) 8090 (compare:CC_N (lshiftrt:SI 8091 (ashift:SI (match_operand:SI 1 "register_operand" "d") 8092 @@ -692,13 +1280,29 @@ 8093 (const_int 0))) 8094 (set (match_operand:SI 0 "register_operand" "=d") 8095 (zero_extend:SI (match_operand:QI 2 "register_operand" "0")))] 8096 - "" 8097 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 8098 "extzb.c %0, %1" 8099 [(set_attr "type" "arith") 8100 (set_attr "up_c" "yes") 8101 (set_attr "mode" "SI")]) 8102 8103 -(define_insn "*zero_extendqisi2_cmp" 8104 +(define_insn "*zero_extendqisi2_ucc_score3" 8105 + [(set (reg:CC_N CC_REGNUM) 8106 + (compare:CC_N (lshiftrt:SI 8107 + (ashift:SI (match_operand:SI 1 "score_register_operand" "d") 8108 + (const_int 24)) 8109 + (const_int 24)) 8110 + (const_int 0))) 8111 + (set (match_operand:SI 0 "score_register_operand" "=d") 8112 + (zero_extend:SI (match_operand:QI 2 "score_register_operand" "0")))] 8113 + "(TARGET_SCORE3)" 8114 + "extzb.c\t%0, %1" 8115 + [(set_attr "type" "arith") 8116 + (set_attr "length" "4") 8117 + (set_attr "up_c" "yes") 8118 + (set_attr "mode" "SI")]) 8119 + 8120 +(define_insn "*zero_extendqisi2_cmp_score7" 8121 [(set (reg:CC_N CC_REGNUM) 8122 (compare:CC_N (lshiftrt:SI 8123 (ashift:SI (match_operand:SI 1 "register_operand" "d") 8124 @@ -706,28 +1310,66 @@ 8125 (const_int 24)) 8126 (const_int 0))) 8127 (clobber (match_scratch:SI 0 "=d"))] 8128 - "" 8129 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 8130 "extzb.c %0, %1" 8131 [(set_attr "type" "arith") 8132 (set_attr "up_c" "yes") 8133 (set_attr "mode" "SI")]) 8134 8135 -(define_insn "zero_extendhisi2" 8136 +(define_insn "*zero_extendqisi2_cmp_score3" 8137 + [(set (reg:CC_N CC_REGNUM) 8138 + (compare:CC_N (lshiftrt:SI 8139 + (ashift:SI (match_operand:SI 1 "score_register_operand" "d") 8140 + (const_int 24)) 8141 + (const_int 24)) 8142 + (const_int 0))) 8143 + (clobber (match_scratch:SI 0 "=d"))] 8144 + "(TARGET_SCORE3)" 8145 + "extzb.c\t%0, %1" 8146 + [(set_attr "type" "arith") 8147 + (set_attr "length" "4") 8148 + (set_attr "up_c" "yes") 8149 + (set_attr "mode" "SI")]) 8150 + 8151 +(define_expand "zero_extendhisi2" 8152 + [(set (match_operand:SI 0 "score_register_operand") 8153 + (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand")))] 8154 + "" 8155 + "" 8156 +) 8157 + 8158 +(define_insn "*zero_extendhisi2_score7" 8159 [(set (match_operand:SI 0 "register_operand" "=d,d") 8160 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,m")))] 8161 - "" 8162 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 8163 +{ 8164 + switch (which_alternative) 8165 + { 8166 + case 0: return \"extzh\t%0, %1\"; 8167 + case 1: return score_linsn (operands, SCORE_HWORD, false); 8168 + default: gcc_unreachable (); 8169 + } 8170 +} 8171 + [(set_attr "type" "arith, load") 8172 + (set_attr "mode" "SI")]) 8173 + 8174 +(define_insn "*zero_extendhisi2_score3" 8175 + [(set (match_operand:SI 0 "score_register_operand" "=d,d") 8176 + (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,m")))] 8177 + "(TARGET_SCORE3)" 8178 { 8179 switch (which_alternative) 8180 { 8181 - case 0: return \"extzh %0, %1\"; 8182 - case 1: return mdp_linsn (operands, MDA_HWORD, false); 8183 + case 0: return \"extzh\t%0, %1\"; 8184 + case 1: return score_linsn (operands, SCORE_HWORD, false); 8185 default: gcc_unreachable (); 8186 } 8187 - } 8188 +} 8189 [(set_attr "type" "arith, load") 8190 + (set_attr "length" "4,4") 8191 (set_attr "mode" "SI")]) 8192 8193 -(define_insn "*zero_extendhisi2_ucc" 8194 +(define_insn "*zero_extendhisi2_ucc_score7" 8195 [(set (reg:CC_N CC_REGNUM) 8196 (compare:CC_N (lshiftrt:SI 8197 (ashift:SI (match_operand:SI 1 "register_operand" "d") 8198 @@ -736,13 +1378,29 @@ 8199 (const_int 0))) 8200 (set (match_operand:SI 0 "register_operand" "=d") 8201 (zero_extend:SI (match_operand:HI 2 "register_operand" "0")))] 8202 - "" 8203 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 8204 "extzh.c %0, %1" 8205 [(set_attr "type" "arith") 8206 (set_attr "up_c" "yes") 8207 (set_attr "mode" "SI")]) 8208 8209 -(define_insn "*zero_extendhisi2_cmp" 8210 +(define_insn "*zero_extendhisi2_ucc_score3" 8211 + [(set (reg:CC_N CC_REGNUM) 8212 + (compare:CC_N (lshiftrt:SI 8213 + (ashift:SI (match_operand:SI 1 "score_register_operand" "d") 8214 + (const_int 16)) 8215 + (const_int 16)) 8216 + (const_int 0))) 8217 + (set (match_operand:SI 0 "score_register_operand" "=d") 8218 + (zero_extend:SI (match_operand:HI 2 "score_register_operand" "0")))] 8219 + "(TARGET_SCORE3)" 8220 + "extzh.c\t%0, %1" 8221 + [(set_attr "type" "arith") 8222 + (set_attr "length" "4") 8223 + (set_attr "up_c" "yes") 8224 + (set_attr "mode" "SI")]) 8225 + 8226 +(define_insn "*zero_extendhisi2_cmp_score7" 8227 [(set (reg:CC_N CC_REGNUM) 8228 (compare:CC_N (lshiftrt:SI 8229 (ashift:SI (match_operand:SI 1 "register_operand" "d") 8230 @@ -750,78 +1408,235 @@ 8231 (const_int 16)) 8232 (const_int 0))) 8233 (clobber (match_scratch:SI 0 "=d"))] 8234 - "" 8235 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 8236 "extzh.c %0, %1" 8237 [(set_attr "type" "arith") 8238 (set_attr "up_c" "yes") 8239 (set_attr "mode" "SI")]) 8240 8241 -(define_insn "mulsi3" 8242 +(define_insn "*zero_extendhisi2_cmp_score3" 8243 + [(set (reg:CC_N CC_REGNUM) 8244 + (compare:CC_N (lshiftrt:SI 8245 + (ashift:SI (match_operand:SI 1 "score_register_operand" "d") 8246 + (const_int 16)) 8247 + (const_int 16)) 8248 + (const_int 0))) 8249 + (clobber (match_scratch:SI 0 "=d"))] 8250 + "(TARGET_SCORE3)" 8251 + "extzh.c\t%0, %1" 8252 + [(set_attr "type" "arith") 8253 + (set_attr "length" "4") 8254 + (set_attr "up_c" "yes") 8255 + (set_attr "mode" "SI")]) 8256 + 8257 +(define_expand "mulsi3" 8258 + [(set (match_operand:SI 0 "score_register_operand") 8259 + (mult:SI (match_operand:SI 1 "score_register_operand") 8260 + (match_operand:SI 2 "score_register_operand")))] 8261 + "" 8262 +{ 8263 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 8264 + emit_insn (gen_mulsi3_score7 (operands[0], operands[1], operands[2])); 8265 + else if (TARGET_SCORE3) 8266 + emit_insn (gen_mulsi3_score3 (operands[0], operands[1], operands[2])); 8267 + DONE; 8268 +}) 8269 + 8270 +(define_insn "mulsi3_score7" 8271 [(set (match_operand:SI 0 "register_operand" "=l") 8272 (mult:SI (match_operand:SI 1 "register_operand" "d") 8273 (match_operand:SI 2 "register_operand" "d"))) 8274 - (clobber (reg:SI HI_REGNUM))] 8275 - "!TARGET_SCORE5U" 8276 + (clobber (reg:SI HI_REGNUM))] 8277 + "(TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)" 8278 "mul %1, %2" 8279 [(set_attr "type" "mul") 8280 (set_attr "mode" "SI")]) 8281 8282 -(define_insn "mulsidi3" 8283 +(define_insn "mulsi3_score3" 8284 + [(set (match_operand:SI 0 "score_register_operand" "=d") 8285 + (mult:SI (match_operand:SI 1 "score_register_operand" "d") 8286 + (match_operand:SI 2 "score_register_operand" "d")))] 8287 + "(TARGET_SCORE3)" 8288 + "mulr.l\t%0, %1, %2" 8289 + [(set_attr "type" "mul") 8290 + (set_attr "length" "4") 8291 + (set_attr "mode" "SI")]) 8292 + 8293 +(define_expand "mulsidi3" 8294 + [(set (match_operand:DI 0 "score_register_operand") 8295 + (mult:DI (sign_extend:DI 8296 + (match_operand:SI 1 "score_register_operand")) 8297 + (sign_extend:DI 8298 + (match_operand:SI 2 "score_register_operand"))))] 8299 + "" 8300 +{ 8301 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 8302 + emit_insn (gen_mulsidi3_score7 (operands[0], operands[1], operands[2])); 8303 + else if (TARGET_SCORE3) 8304 + emit_insn (gen_mulsidi3_score3 (operands[0], operands[1], operands[2])); 8305 + DONE; 8306 +}) 8307 + 8308 +(define_insn "mulsidi3_score7" 8309 [(set (match_operand:DI 0 "register_operand" "=x") 8310 (mult:DI (sign_extend:DI 8311 (match_operand:SI 1 "register_operand" "d")) 8312 (sign_extend:DI 8313 (match_operand:SI 2 "register_operand" "d"))))] 8314 - "!TARGET_SCORE5U" 8315 + "(TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)" 8316 "mul %1, %2" 8317 [(set_attr "type" "mul") 8318 (set_attr "mode" "DI")]) 8319 8320 -(define_insn "umulsidi3" 8321 +(define_insn "mulsidi3_score3" 8322 + [(set (match_operand:DI 0 "score_register_operand" "=d") 8323 + (mult:DI (sign_extend:DI 8324 + (match_operand:SI 1 "score_register_operand" "d")) 8325 + (sign_extend:DI 8326 + (match_operand:SI 2 "score_register_operand" "d"))))] 8327 + "(TARGET_SCORE3)" 8328 + "mulr\t%0, %1, %2" 8329 + [(set_attr "type" "mul") 8330 + (set_attr "length" "4") 8331 + (set_attr "mode" "DI")]) 8332 + 8333 +(define_expand "umulsidi3" 8334 + [(set (match_operand:DI 0 "score_register_operand") 8335 + (mult:DI (zero_extend:DI 8336 + (match_operand:SI 1 "score_register_operand")) 8337 + (zero_extend:DI 8338 + (match_operand:SI 2 "score_register_operand"))))] 8339 + "" 8340 +{ 8341 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 8342 + emit_insn (gen_umulsidi3_score7 (operands[0], operands[1], operands[2])); 8343 + else if (TARGET_SCORE3) 8344 + emit_insn (gen_umulsidi3_score3 (operands[0], operands[1], operands[2])); 8345 + DONE; 8346 +}) 8347 + 8348 +(define_insn "umulsidi3_score7" 8349 [(set (match_operand:DI 0 "register_operand" "=x") 8350 (mult:DI (zero_extend:DI 8351 (match_operand:SI 1 "register_operand" "d")) 8352 (zero_extend:DI 8353 (match_operand:SI 2 "register_operand" "d"))))] 8354 - "!TARGET_SCORE5U" 8355 + "(TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)" 8356 "mulu %1, %2" 8357 [(set_attr "type" "mul") 8358 (set_attr "mode" "DI")]) 8359 8360 -(define_insn "divmodsi4" 8361 +(define_insn "umulsidi3_score3" 8362 + [(set (match_operand:DI 0 "score_register_operand" "=d") 8363 + (mult:DI (zero_extend:DI 8364 + (match_operand:SI 1 "score_register_operand" "d")) 8365 + (zero_extend:DI 8366 + (match_operand:SI 2 "score_register_operand" "d"))))] 8367 + "(TARGET_SCORE3)" 8368 + "mulur\t%0, %1, %2" 8369 + [(set_attr "type" "mul") 8370 + (set_attr "length" "4") 8371 + (set_attr "mode" "DI")]) 8372 + 8373 +(define_expand "divmodsi4" 8374 + [(parallel 8375 + [(set (match_operand:SI 0 "score_register_operand") 8376 + (div:SI (match_operand:SI 1 "score_register_operand") 8377 + (match_operand:SI 2 "score_register_operand"))) 8378 + (set (match_operand:SI 3 "score_register_operand") 8379 + (mod:SI (match_dup 1) (match_dup 2)))])] 8380 + "" 8381 + "" 8382 +) 8383 + 8384 +(define_insn "*divmodsi4_score7" 8385 [(set (match_operand:SI 0 "register_operand" "=l") 8386 (div:SI (match_operand:SI 1 "register_operand" "d") 8387 (match_operand:SI 2 "register_operand" "d"))) 8388 (set (match_operand:SI 3 "register_operand" "=h") 8389 (mod:SI (match_dup 1) (match_dup 2)))] 8390 - "!TARGET_SCORE5U" 8391 + "(TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)" 8392 "div %1, %2" 8393 [(set_attr "type" "div") 8394 (set_attr "mode" "SI")]) 8395 8396 -(define_insn "udivmodsi4" 8397 +(define_insn "*divmodsi4_score3" 8398 + [(set (match_operand:SI 0 "score_register_operand" "=l") 8399 + (div:SI (match_operand:SI 1 "score_register_operand" "d") 8400 + (match_operand:SI 2 "score_register_operand" "d"))) 8401 + (set (match_operand:SI 3 "score_register_operand" "=h") 8402 + (mod:SI (match_dup 1) (match_dup 2)))] 8403 + "(TARGET_SCORE3)" 8404 + "div\t%1, %2" 8405 + [(set_attr "type" "div") 8406 + (set_attr "mode" "SI")]) 8407 + 8408 +(define_expand "udivmodsi4" 8409 + [(parallel 8410 + [(set (match_operand:SI 0 "score_register_operand") 8411 + (udiv:SI (match_operand:SI 1 "score_register_operand") 8412 + (match_operand:SI 2 "score_register_operand"))) 8413 + (set (match_operand:SI 3 "score_register_operand") 8414 + (umod:SI (match_dup 1) (match_dup 2)))])] 8415 + "" 8416 + "" 8417 +) 8418 + 8419 +(define_insn "*udivmodsi4_score7" 8420 [(set (match_operand:SI 0 "register_operand" "=l") 8421 (udiv:SI (match_operand:SI 1 "register_operand" "d") 8422 (match_operand:SI 2 "register_operand" "d"))) 8423 (set (match_operand:SI 3 "register_operand" "=h") 8424 (umod:SI (match_dup 1) (match_dup 2)))] 8425 - "!TARGET_SCORE5U" 8426 + "(TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)" 8427 "divu %1, %2" 8428 [(set_attr "type" "div") 8429 (set_attr "mode" "SI")]) 8430 8431 -(define_insn "ashlsi3" 8432 +(define_insn "*udivmodsi4_score3" 8433 + [(set (match_operand:SI 0 "score_register_operand" "=l") 8434 + (udiv:SI (match_operand:SI 1 "score_register_operand" "d") 8435 + (match_operand:SI 2 "score_register_operand" "d"))) 8436 + (set (match_operand:SI 3 "score_register_operand" "=h") 8437 + (umod:SI (match_dup 1) (match_dup 2)))] 8438 + "(TARGET_SCORE3)" 8439 + "divu\t%1, %2" 8440 + [(set_attr "type" "div") 8441 + (set_attr "mode" "SI")]) 8442 + 8443 +(define_expand "ashlsi3" 8444 + [(set (match_operand:SI 0 "score_register_operand") 8445 + (ashift:SI (match_operand:SI 1 "score_register_operand") 8446 + (match_operand:SI 2 "arith_operand")))] 8447 + "" 8448 + "" 8449 +) 8450 + 8451 +(define_insn "*ashlsi3_score7" 8452 [(set (match_operand:SI 0 "register_operand" "=d,d") 8453 (ashift:SI (match_operand:SI 1 "register_operand" "d,d") 8454 (match_operand:SI 2 "arith_operand" "J,d")))] 8455 - "" 8456 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 8457 "@ 8458 slli %0, %1, %c2 8459 sll %0, %1, %2" 8460 [(set_attr "type" "arith") 8461 (set_attr "mode" "SI")]) 8462 8463 -(define_insn "ashlsi3_ucc" 8464 +(define_insn "*ashlsi3_score3" 8465 + [(set (match_operand:SI 0 "score_register_operand" "=e,d,d") 8466 + (ashift:SI (match_operand:SI 1 "score_register_operand" "0,d,d") 8467 + (match_operand:SI 2 "arith_operand" "J,J,d")))] 8468 + "(TARGET_SCORE3)" 8469 + "@ 8470 + slli!\t%0, %c2 8471 + slli\t%0, %1, %c2 8472 + sll\t%0, %1, %2" 8473 + [(set_attr "type" "arith") 8474 + (set_attr "length" "2,4,4") 8475 + (set_attr "mode" "SI")]) 8476 + 8477 +(define_insn "*ashlsi3_ucc_score7" 8478 [(set (reg:CC_NZ CC_REGNUM) 8479 (compare:CC_NZ (ashift:SI 8480 (match_operand:SI 1 "register_operand" "d,d") 8481 @@ -829,12 +1644,12 @@ 8482 (const_int 0))) 8483 (set (match_operand:SI 0 "register_operand" "=d,d") 8484 (ashift:SI (match_dup 1) (match_dup 2)))] 8485 - "" 8486 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 8487 { 8488 switch (which_alternative) 8489 { 8490 - case 0: return mdp_select (operands, "slli", false, "c", true); 8491 - case 1: return mdp_select (operands, "sll", false, "", true); 8492 + case 0: return score_select (operands, "slli", false, "c", true); 8493 + case 1: return score_select (operands, "sll", false, "", true); 8494 default: gcc_unreachable (); 8495 } 8496 } 8497 @@ -842,51 +1657,41 @@ 8498 (set_attr "up_c" "yes") 8499 (set_attr "mode" "SI")]) 8500 8501 -(define_insn "ashlsi3_cmp" 8502 +(define_insn "*ashlsi3_ucc_score3" 8503 [(set (reg:CC_NZ CC_REGNUM) 8504 (compare:CC_NZ (ashift:SI 8505 - (match_operand:SI 1 "register_operand" "d,d") 8506 + (match_operand:SI 1 "score_register_operand" "d,d") 8507 (match_operand:SI 2 "arith_operand" "J,d")) 8508 (const_int 0))) 8509 - (clobber (match_scratch:SI 0 "=d,d"))] 8510 - "" 8511 + (set (match_operand:SI 0 "score_register_operand" "=d,d") 8512 + (ashift:SI (match_dup 1) (match_dup 2)))] 8513 + "(TARGET_SCORE3)" 8514 { 8515 switch (which_alternative) 8516 { 8517 - case 0: return mdp_select (operands, "slli", false, "c", true); 8518 - case 1: return mdp_select (operands, "sll", false, "", true); 8519 + case 0: return score_select (operands, "slli", false, "c", true); 8520 + case 1: return score_select (operands, "sll", false, "", true); 8521 default: gcc_unreachable (); 8522 } 8523 } 8524 [(set_attr "type" "arith") 8525 + (set_attr "length" "4,4") 8526 (set_attr "up_c" "yes") 8527 (set_attr "mode" "SI")]) 8528 8529 -(define_insn "ashrsi3" 8530 - [(set (match_operand:SI 0 "register_operand" "=d,d") 8531 - (ashiftrt:SI (match_operand:SI 1 "register_operand" "d,d") 8532 - (match_operand:SI 2 "arith_operand" "J,d")))] 8533 - "" 8534 - "@ 8535 - srai %0, %1, %c2 8536 - sra %0, %1, %2" 8537 - [(set_attr "type" "arith") 8538 - (set_attr "mode" "SI")]) 8539 - 8540 -(define_insn "ashrsi3_ucc" 8541 +(define_insn "*ashlsi3_cmp_score7" 8542 [(set (reg:CC_NZ CC_REGNUM) 8543 - (compare:CC_NZ (ashiftrt:SI 8544 + (compare:CC_NZ (ashift:SI 8545 (match_operand:SI 1 "register_operand" "d,d") 8546 (match_operand:SI 2 "arith_operand" "J,d")) 8547 (const_int 0))) 8548 - (set (match_operand:SI 0 "register_operand" "=d,d") 8549 - (ashiftrt:SI (match_dup 1) (match_dup 2)))] 8550 - "" 8551 + (clobber (match_scratch:SI 0 "=d,d"))] 8552 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 8553 { 8554 switch (which_alternative) 8555 { 8556 - case 0: return \"srai.c %0, %1, %c2\"; 8557 - case 1: return mdp_select (operands, "sra", false, "", true); 8558 + case 0: return score_select (operands, "slli", false, "c", true); 8559 + case 1: return score_select (operands, "sll", false, "", true); 8560 default: gcc_unreachable (); 8561 } 8562 } 8563 @@ -894,92 +1699,289 @@ 8564 (set_attr "up_c" "yes") 8565 (set_attr "mode" "SI")]) 8566 8567 -(define_insn "ashrsi3_cmp" 8568 +(define_insn "*ashlsi3_cmp_score3" 8569 [(set (reg:CC_NZ CC_REGNUM) 8570 - (compare:CC_NZ (ashiftrt:SI 8571 - (match_operand:SI 1 "register_operand" "d,d") 8572 + (compare:CC_NZ (ashift:SI 8573 + (match_operand:SI 1 "score_register_operand" "d,d") 8574 (match_operand:SI 2 "arith_operand" "J,d")) 8575 (const_int 0))) 8576 (clobber (match_scratch:SI 0 "=d,d"))] 8577 - "" 8578 + "(TARGET_SCORE3)" 8579 { 8580 switch (which_alternative) 8581 { 8582 - case 0: return \"srai.c %0, %1, %c2\"; 8583 - case 1: return mdp_select (operands, "sra", false, "", true); 8584 + case 0: return score_select (operands, "slli", false, "c", true); 8585 + case 1: return score_select (operands, "sll", false, "", true); 8586 default: gcc_unreachable (); 8587 } 8588 } 8589 [(set_attr "type" "arith") 8590 + (set_attr "length" "4,4") 8591 (set_attr "up_c" "yes") 8592 (set_attr "mode" "SI")]) 8593 8594 -(define_insn "lshrsi3" 8595 + 8596 +(define_expand "ashrsi3" 8597 + [(set (match_operand:SI 0 "score_register_operand") 8598 + (ashiftrt:SI (match_operand:SI 1 "score_register_operand") 8599 + (match_operand:SI 2 "arith_operand")))] 8600 + "" 8601 + "" 8602 +) 8603 + 8604 +(define_insn "*ashrsi3_score7" 8605 [(set (match_operand:SI 0 "register_operand" "=d,d") 8606 - (lshiftrt:SI (match_operand:SI 1 "register_operand" "d,d") 8607 + (ashiftrt:SI (match_operand:SI 1 "register_operand" "d,d") 8608 (match_operand:SI 2 "arith_operand" "J,d")))] 8609 - "" 8610 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 8611 "@ 8612 - srli %0, %1, %c2 8613 - srl %0, %1, %2" 8614 + srai %0, %1, %c2 8615 + sra %0, %1, %2" 8616 [(set_attr "type" "arith") 8617 (set_attr "mode" "SI")]) 8618 8619 -(define_insn "lshrsi3_ucc" 8620 - [(set (reg:CC_NZ CC_REGNUM) 8621 - (compare:CC_NZ (lshiftrt:SI 8622 - (match_operand:SI 1 "register_operand" "d,d") 8623 - (match_operand:SI 2 "arith_operand" "J,d")) 8624 +(define_insn "*ashrsi3_score3" 8625 + [(set (match_operand:SI 0 "score_register_operand" "=d,d") 8626 + (ashiftrt:SI (match_operand:SI 1 "score_register_operand" "d,d") 8627 + (match_operand:SI 2 "arith_operand" "J,d")))] 8628 + "(TARGET_SCORE3)" 8629 + "@ 8630 + srai\t%0, %1, %c2 8631 + sra\t%0, %1, %2" 8632 + [(set_attr "type" "arith") 8633 + (set_attr "length" "4,4") 8634 + (set_attr "mode" "SI")]) 8635 + 8636 +(define_insn "*ashrsi3_ucc_score7" 8637 + [(set (reg:CC_NZ CC_REGNUM) 8638 + (compare:CC_NZ (ashiftrt:SI 8639 + (match_operand:SI 1 "register_operand" "d,d") 8640 + (match_operand:SI 2 "arith_operand" "J,d")) 8641 (const_int 0))) 8642 (set (match_operand:SI 0 "register_operand" "=d,d") 8643 - (lshiftrt:SI (match_dup 1) (match_dup 2)))] 8644 + (ashiftrt:SI (match_dup 1) (match_dup 2)))] 8645 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 8646 +{ 8647 + switch (which_alternative) 8648 + { 8649 + case 0: return \"srai.c\t%0, %1, %c2\"; 8650 + case 1: return score_select (operands, "sra", false, "", true); 8651 + default: gcc_unreachable (); 8652 + } 8653 +} 8654 + [(set_attr "type" "arith") 8655 + (set_attr "up_c" "yes") 8656 + (set_attr "mode" "SI")]) 8657 + 8658 +(define_insn "*ashrsi3_ucc_score3" 8659 + [(set (reg:CC_NZ CC_REGNUM) 8660 + (compare:CC_NZ (ashiftrt:SI 8661 + (match_operand:SI 1 "score_register_operand" "d,d") 8662 + (match_operand:SI 2 "arith_operand" "J,d")) 8663 + (const_int 0))) 8664 + (set (match_operand:SI 0 "score_register_operand" "=d,d") 8665 + (ashiftrt:SI (match_dup 1) (match_dup 2)))] 8666 + "(TARGET_SCORE3)" 8667 +{ 8668 + switch (which_alternative) 8669 + { 8670 + case 0: return \"srai.c\t%0, %1, %c2\"; 8671 + case 1: return score_select (operands, "sra", false, "", true); 8672 + default: gcc_unreachable (); 8673 + } 8674 +} 8675 + [(set_attr "type" "arith") 8676 + (set_attr "length" "4,4") 8677 + (set_attr "up_c" "yes") 8678 + (set_attr "mode" "SI")]) 8679 + 8680 +(define_insn "*ashrsi3_cmp_score7" 8681 + [(set (reg:CC_NZ CC_REGNUM) 8682 + (compare:CC_NZ (ashiftrt:SI 8683 + (match_operand:SI 1 "register_operand" "d,d") 8684 + (match_operand:SI 2 "arith_operand" "J,d")) 8685 + (const_int 0))) 8686 + (clobber (match_scratch:SI 0 "=d,d"))] 8687 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 8688 +{ 8689 + switch (which_alternative) 8690 + { 8691 + case 0: return \"srai.c\t%0, %1, %c2\"; 8692 + case 1: return score_select (operands, "sra", false, "", true); 8693 + default: gcc_unreachable (); 8694 + } 8695 +} 8696 + [(set_attr "type" "arith") 8697 + (set_attr "up_c" "yes") 8698 + (set_attr "mode" "SI")]) 8699 + 8700 +(define_insn "ashrsi3_cmp_score3" 8701 + [(set (reg:CC_NZ CC_REGNUM) 8702 + (compare:CC_NZ (ashiftrt:SI 8703 + (match_operand:SI 1 "score_register_operand" "d,d") 8704 + (match_operand:SI 2 "arith_operand" "J,d")) 8705 + (const_int 0))) 8706 + (clobber (match_scratch:SI 0 "=d,d"))] 8707 + "(TARGET_SCORE3)" 8708 +{ 8709 + switch (which_alternative) 8710 + { 8711 + case 0: return \"srai.c\t%0, %1, %c2\"; 8712 + case 1: return score_select (operands, "sra", false, "", true); 8713 + default: gcc_unreachable (); 8714 + } 8715 +} 8716 + [(set_attr "type" "arith") 8717 + (set_attr "length" "4,4") 8718 + (set_attr "up_c" "yes") 8719 + (set_attr "mode" "SI")]) 8720 + 8721 +(define_expand "lshrsi3" 8722 + [(set (match_operand:SI 0 "score_register_operand") 8723 + (lshiftrt:SI (match_operand:SI 1 "score_register_operand") 8724 + (match_operand:SI 2 "arith_operand")))] 8725 + "" 8726 "" 8727 +) 8728 + 8729 +(define_insn "*lshrsi3_score7" 8730 + [(set (match_operand:SI 0 "register_operand" "=d,d") 8731 + (lshiftrt:SI (match_operand:SI 1 "register_operand" "d,d") 8732 + (match_operand:SI 2 "arith_operand" "J,d")))] 8733 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 8734 + "@ 8735 + srli %0, %1, %c2 8736 + srl %0, %1, %2" 8737 + [(set_attr "type" "arith") 8738 + (set_attr "mode" "SI")]) 8739 + 8740 +(define_insn "*lshrsi3_score3" 8741 + [(set (match_operand:SI 0 "score_register_operand" "=e,d,d") 8742 + (lshiftrt:SI (match_operand:SI 1 "score_register_operand" "0,d,d") 8743 + (match_operand:SI 2 "arith_operand" "J,J,d")))] 8744 + "(TARGET_SCORE3)" 8745 + "@ 8746 + srli!\t%0, %c2 8747 + srli\t%0, %1, %c2 8748 + srl\t%0, %1, %2" 8749 + [(set_attr "type" "arith") 8750 + (set_attr "length" "2,4,4") 8751 + (set_attr "mode" "SI")]) 8752 + 8753 +(define_insn "*lshrsi3_ucc_score7" 8754 + [(set (reg:CC_NZ CC_REGNUM) 8755 + (compare:CC_NZ (lshiftrt:SI 8756 + (match_operand:SI 1 "register_operand" "d,d") 8757 + (match_operand:SI 2 "arith_operand" "J,d")) 8758 + (const_int 0))) 8759 + (set (match_operand:SI 0 "register_operand" "=d,d") 8760 + (lshiftrt:SI (match_dup 1) (match_dup 2)))] 8761 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 8762 +{ 8763 + switch (which_alternative) 8764 + { 8765 + case 0: return score_select (operands, "srli", false, "c", true); 8766 + case 1: return score_select (operands, "srl", false, "", true); 8767 + default: gcc_unreachable (); 8768 + } 8769 +} 8770 + [(set_attr "type" "arith") 8771 + (set_attr "up_c" "yes") 8772 + (set_attr "mode" "SI")]) 8773 + 8774 +(define_insn "*lshrsi3_ucc_score3" 8775 + [(set (reg:CC_NZ CC_REGNUM) 8776 + (compare:CC_NZ (lshiftrt:SI 8777 + (match_operand:SI 1 "score_register_operand" "d,d") 8778 + (match_operand:SI 2 "arith_operand" "J,d")) 8779 + (const_int 0))) 8780 + (set (match_operand:SI 0 "score_register_operand" "=d,d") 8781 + (lshiftrt:SI (match_dup 1) (match_dup 2)))] 8782 + "(TARGET_SCORE3)" 8783 { 8784 switch (which_alternative) 8785 { 8786 - case 0: return mdp_select (operands, "srli", false, "c", true); 8787 - case 1: return mdp_select (operands, "srl", false, "", true); 8788 + case 0: return score_select (operands, "srli", false, "c", true); 8789 + case 1: return score_select (operands, "srl", false, "", true); 8790 default: gcc_unreachable (); 8791 } 8792 } 8793 [(set_attr "type" "arith") 8794 + (set_attr "length" "4,4") 8795 (set_attr "up_c" "yes") 8796 (set_attr "mode" "SI")]) 8797 8798 -(define_insn "lshrsi3_cmp" 8799 +(define_insn "*lshrsi3_cmp_score7" 8800 [(set (reg:CC_NZ CC_REGNUM) 8801 (compare:CC_NZ (lshiftrt:SI 8802 (match_operand:SI 1 "register_operand" "d,d") 8803 (match_operand:SI 2 "arith_operand" "J,d")) 8804 (const_int 0))) 8805 (clobber (match_scratch:SI 0 "=d,d"))] 8806 - "" 8807 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 8808 +{ 8809 + switch (which_alternative) 8810 + { 8811 + case 0: return score_select (operands, "srli", false, "c", true); 8812 + case 1: return score_select (operands, "srl", false, "", true); 8813 + default: gcc_unreachable (); 8814 + } 8815 +} 8816 + [(set_attr "type" "arith") 8817 + (set_attr "up_c" "yes") 8818 + (set_attr "mode" "SI")]) 8819 + 8820 +(define_insn "*lshrsi3_cmp_score3" 8821 + [(set (reg:CC_NZ CC_REGNUM) 8822 + (compare:CC_NZ (lshiftrt:SI 8823 + (match_operand:SI 1 "score_register_operand" "d,d") 8824 + (match_operand:SI 2 "arith_operand" "J,d")) 8825 + (const_int 0))) 8826 + (clobber (match_scratch:SI 0 "=d,d"))] 8827 + "(TARGET_SCORE3)" 8828 { 8829 switch (which_alternative) 8830 { 8831 - case 0: return mdp_select (operands, "srli", false, "c", true); 8832 - case 1: return mdp_select (operands, "srl", false, "", true); 8833 + case 0: return score_select (operands, "srli", false, "c", true); 8834 + case 1: return score_select (operands, "srl", false, "", true); 8835 default: gcc_unreachable (); 8836 } 8837 } 8838 [(set_attr "type" "arith") 8839 + (set_attr "length" "4,4") 8840 (set_attr "up_c" "yes") 8841 (set_attr "mode" "SI")]) 8842 8843 -(define_insn "negsi2" 8844 +(define_expand "negsi2" 8845 + [(set (match_operand:SI 0 "score_register_operand") 8846 + (neg:SI (match_operand:SI 1 "score_register_operand")))] 8847 + "" 8848 + "" 8849 +) 8850 + 8851 +(define_insn "*negsi2_score7" 8852 [(set (match_operand:SI 0 "register_operand" "=d") 8853 (neg:SI (match_operand:SI 1 "register_operand" "d")))] 8854 - "" 8855 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 8856 "neg %0, %1" 8857 [(set_attr "type" "arith") 8858 (set_attr "mode" "SI")]) 8859 8860 -(define_insn "*negsi2_cmp" 8861 +(define_insn "*negsi2_score3" 8862 + [(set (match_operand:SI 0 "score_register_operand" "=d") 8863 + (neg:SI (match_operand:SI 1 "score_register_operand" "d")))] 8864 + "(TARGET_SCORE3)" 8865 + "neg\t%0, %1" 8866 + [(set_attr "type" "arith") 8867 + (set_attr "length" "4") 8868 + (set_attr "mode" "SI")]) 8869 + 8870 +(define_insn "*negsi2_cmp_score7" 8871 [(set (reg:CC_NZ CC_REGNUM) 8872 (compare:CC_NZ (neg:SI (match_operand:SI 1 "register_operand" "e,d")) 8873 (const_int 0))) 8874 (clobber (match_scratch:SI 0 "=e,d"))] 8875 - "" 8876 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 8877 "@ 8878 neg! %0, %1 8879 neg.c %0, %1" 8880 @@ -987,13 +1989,25 @@ 8881 (set_attr "up_c" "yes") 8882 (set_attr "mode" "SI")]) 8883 8884 -(define_insn "negsi2_ucc" 8885 +(define_insn "*negsi2_cmp_score3" 8886 + [(set (reg:CC_NZ CC_REGNUM) 8887 + (compare:CC_NZ (neg:SI (match_operand:SI 1 "score_register_operand" "d")) 8888 + (const_int 0))) 8889 + (clobber (match_scratch:SI 0 "=d"))] 8890 + "(TARGET_SCORE3)" 8891 + "neg.c\t%0, %1" 8892 + [(set_attr "type" "arith") 8893 + (set_attr "length" "4") 8894 + (set_attr "up_c" "yes") 8895 + (set_attr "mode" "SI")]) 8896 + 8897 +(define_insn "*negsi2_ucc_score7" 8898 [(set (reg:CC_NZ CC_REGNUM) 8899 (compare:CC_NZ (neg:SI (match_operand:SI 1 "register_operand" "e,d")) 8900 (const_int 0))) 8901 (set (match_operand:SI 0 "register_operand" "=e,d") 8902 (neg:SI (match_dup 1)))] 8903 - "" 8904 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 8905 "@ 8906 neg! %0, %1 8907 neg.c %0, %1" 8908 @@ -1001,21 +2015,51 @@ 8909 (set_attr "up_c" "yes") 8910 (set_attr "mode" "SI")]) 8911 8912 -(define_insn "one_cmplsi2" 8913 +(define_insn "*negsi2_ucc_score3" 8914 + [(set (reg:CC_NZ CC_REGNUM) 8915 + (compare:CC_NZ (neg:SI (match_operand:SI 1 "score_register_operand" "d")) 8916 + (const_int 0))) 8917 + (set (match_operand:SI 0 "score_register_operand" "=d") 8918 + (neg:SI (match_dup 1)))] 8919 + "(TARGET_SCORE3)" 8920 + "neg.c\t%0, %1" 8921 + [(set_attr "type" "arith") 8922 + (set_attr "length" "4") 8923 + (set_attr "up_c" "yes") 8924 + (set_attr "mode" "SI")]) 8925 + 8926 + 8927 +(define_expand "one_cmplsi2" 8928 + [(set (match_operand:SI 0 "score_register_operand") 8929 + (not:SI (match_operand:SI 1 "score_register_operand")))] 8930 + "" 8931 + "" 8932 +) 8933 + 8934 +(define_insn "*one_cmplsi2_score7" 8935 [(set (match_operand:SI 0 "register_operand" "=d") 8936 (not:SI (match_operand:SI 1 "register_operand" "d")))] 8937 - "" 8938 - "not %0, %1" 8939 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 8940 + "not\t%0, %1" 8941 + [(set_attr "type" "arith") 8942 + (set_attr "mode" "SI")]) 8943 + 8944 +(define_insn "*one_cmplsi2_score3" 8945 + [(set (match_operand:SI 0 "score_register_operand" "=d") 8946 + (not:SI (match_operand:SI 1 "score_register_operand" "d")))] 8947 + "(TARGET_SCORE3)" 8948 + "not\t%0, %1" 8949 [(set_attr "type" "arith") 8950 + (set_attr "length" "4") 8951 (set_attr "mode" "SI")]) 8952 8953 -(define_insn "one_cmplsi2_ucc" 8954 +(define_insn "*one_cmplsi2_ucc_score7" 8955 [(set (reg:CC_NZ CC_REGNUM) 8956 (compare:CC_NZ (not:SI (match_operand:SI 1 "register_operand" "e,d")) 8957 (const_int 0))) 8958 (set (match_operand:SI 0 "register_operand" "=e,d") 8959 (not:SI (match_dup 1)))] 8960 - "" 8961 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 8962 "@ 8963 not! %0, %1 8964 not.c %0, %1" 8965 @@ -1023,12 +2067,25 @@ 8966 (set_attr "up_c" "yes") 8967 (set_attr "mode" "SI")]) 8968 8969 -(define_insn "one_cmplsi2_cmp" 8970 +(define_insn "*one_cmplsi2_ucc_score3" 8971 + [(set (reg:CC_NZ CC_REGNUM) 8972 + (compare:CC_NZ (not:SI (match_operand:SI 1 "score_register_operand" "d")) 8973 + (const_int 0))) 8974 + (set (match_operand:SI 0 "score_register_operand" "=d") 8975 + (not:SI (match_dup 1)))] 8976 + "(TARGET_SCORE3)" 8977 + "not.c\t%0, %1" 8978 + [(set_attr "type" "arith") 8979 + (set_attr "length" "4") 8980 + (set_attr "up_c" "yes") 8981 + (set_attr "mode" "SI")]) 8982 + 8983 +(define_insn "*one_cmplsi2_cmp_score7" 8984 [(set (reg:CC_NZ CC_REGNUM) 8985 (compare:CC_NZ (not:SI (match_operand:SI 1 "register_operand" "e,d")) 8986 (const_int 0))) 8987 (clobber (match_scratch:SI 0 "=e,d"))] 8988 - "" 8989 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 8990 "@ 8991 not! %0, %1 8992 not.c %0, %1" 8993 @@ -1036,33 +2093,175 @@ 8994 (set_attr "up_c" "yes") 8995 (set_attr "mode" "SI")]) 8996 8997 -(define_insn "rotlsi3" 8998 +(define_insn "*one_cmplsi2_cmp_score3" 8999 + [(set (reg:CC_NZ CC_REGNUM) 9000 + (compare:CC_NZ (not:SI (match_operand:SI 1 "score_register_operand" "d")) 9001 + (const_int 0))) 9002 + (clobber (match_scratch:SI 0 "=d"))] 9003 + "(TARGET_SCORE3)" 9004 + "not.c\t%0, %1" 9005 + [(set_attr "type" "arith") 9006 + (set_attr "length" "4") 9007 + (set_attr "up_c" "yes") 9008 + (set_attr "mode" "SI")]) 9009 + 9010 +(define_expand "rotlsi3" 9011 + [(parallel 9012 + [(set (match_operand:SI 0 "score_register_operand") 9013 + (rotate:SI (match_operand:SI 1 "score_register_operand") 9014 + (match_operand:SI 2 "arith_operand"))) 9015 + (clobber (reg:CC CC_REGNUM))])] 9016 + "" 9017 + "" 9018 +) 9019 + 9020 +(define_insn "*rotlsi3_score7" 9021 [(set (match_operand:SI 0 "register_operand" "=d,d") 9022 (rotate:SI (match_operand:SI 1 "register_operand" "d,d") 9023 (match_operand:SI 2 "arith_operand" "J,d"))) 9024 (clobber (reg:CC CC_REGNUM))] 9025 - "" 9026 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 9027 "@ 9028 roli.c %0, %1, %c2 9029 rol.c %0, %1, %2" 9030 [(set_attr "type" "arith") 9031 (set_attr "mode" "SI")]) 9032 9033 -(define_insn "rotrsi3" 9034 +(define_insn "*rotlsi3_score3" 9035 + [(set (match_operand:SI 0 "score_register_operand" "=d,d") 9036 + (rotate:SI (match_operand:SI 1 "score_register_operand" "d,d") 9037 + (match_operand:SI 2 "arith_operand" "J,d"))) 9038 + (clobber (reg:CC CC_REGNUM))] 9039 + "(TARGET_SCORE3)" 9040 + "@ 9041 + roli.c\t%0, %1, %c2 9042 + rol.c\t%0, %1, %2" 9043 + [(set_attr "type" "arith") 9044 + (set_attr "length" "4,4") 9045 + (set_attr "mode" "SI")]) 9046 + 9047 +(define_expand "rotrsi3" 9048 + [(parallel 9049 + [(set (match_operand:SI 0 "score_register_operand") 9050 + (rotatert:SI (match_operand:SI 1 "score_register_operand") 9051 + (match_operand:SI 2 "arith_operand"))) 9052 + (clobber (reg:CC CC_REGNUM))])] 9053 + "" 9054 + "" 9055 +) 9056 + 9057 +(define_insn "*rotrsi3_score7" 9058 [(set (match_operand:SI 0 "register_operand" "=d,d") 9059 (rotatert:SI (match_operand:SI 1 "register_operand" "d,d") 9060 (match_operand:SI 2 "arith_operand" "J,d"))) 9061 (clobber (reg:CC CC_REGNUM))] 9062 - "" 9063 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 9064 "@ 9065 rori.c %0, %1, %c2 9066 ror.c %0, %1, %2" 9067 [(set_attr "type" "arith") 9068 (set_attr "mode" "SI")]) 9069 9070 +(define_insn "*rotrsi3_score3" 9071 + [(set (match_operand:SI 0 "score_register_operand" "=d,d") 9072 + (rotatert:SI (match_operand:SI 1 "score_register_operand" "d,d") 9073 + (match_operand:SI 2 "arith_operand" "J,d"))) 9074 + (clobber (reg:CC CC_REGNUM))] 9075 + "(TARGET_SCORE3)" 9076 + "@ 9077 + rori.c\t%0, %1, %c2 9078 + ror.c\t%0, %1, %2" 9079 + [(set_attr "type" "arith") 9080 + (set_attr "length" "4,4") 9081 + (set_attr "mode" "SI")]) 9082 + 9083 +(define_insn "cbrancheqz" 9084 + [(set (pc) (if_then_else 9085 + (eq (match_operand:SI 0 "score_register_operand" "d") 9086 + (const_int 0)) 9087 + (label_ref (match_operand 1 "" "")) 9088 + (pc))) 9089 + (clobber (reg:CC CC_REGNUM))] 9090 + "(TARGET_SCORE3)" 9091 +{ 9092 + if (get_attr_length (insn) == 4) 9093 + return \"bcmpeqz\t%0, %1\"; 9094 + else 9095 + return \"cmpi!\t%0, 0\;beq!\t%1\"; 9096 +} 9097 + [(set (attr "length") 9098 + (if_then_else 9099 + (and (ge (minus (match_dup 1) (pc)) (const_int -504)) 9100 + (le (minus (match_dup 1) (pc)) (const_int 502))) 9101 + (const_int 4) 9102 + (const_int 6)))]) 9103 + 9104 +(define_insn "cbrancheq" 9105 + [(set (pc) (if_then_else 9106 + (eq (match_operand:SI 0 "score_register_operand" "d") 9107 + (match_operand:SI 1 "score_register_operand" "d")) 9108 + (label_ref (match_operand 2 "" "")) 9109 + (pc))) 9110 + (clobber (reg:CC CC_REGNUM))] 9111 + "(TARGET_SCORE3)" 9112 +{ 9113 + if (get_attr_length (insn) == 4) 9114 + return \"bcmpeq\t%0, %1, %2\"; 9115 + else 9116 + return \"cmp!\t%0, %1\;beq!\t%2\"; 9117 +} 9118 + [(set (attr "length") 9119 + (if_then_else 9120 + (and (ge (minus (match_dup 2) (pc)) (const_int -504)) 9121 + (le (minus (match_dup 2) (pc)) (const_int 502))) 9122 + (const_int 4) 9123 + (const_int 6)))]) 9124 + 9125 +(define_insn "cbranchnez" 9126 + [(set (pc) (if_then_else 9127 + (ne (match_operand:SI 0 "score_register_operand" "d") 9128 + (const_int 0)) 9129 + (label_ref (match_operand 1 "" "")) 9130 + (pc))) 9131 + (clobber (reg:CC CC_REGNUM))] 9132 + "(TARGET_SCORE3)" 9133 +{ 9134 + if (get_attr_length (insn) == 4) 9135 + return \"bcmpnez\t%0, %1\"; 9136 + else 9137 + return \"cmpi!\t%0, 0\;bne\t%1\"; 9138 +} 9139 + [(set (attr "length") 9140 + (if_then_else 9141 + (and (ge (minus (match_dup 1) (pc)) (const_int -504)) 9142 + (le (minus (match_dup 1) (pc)) (const_int 502))) 9143 + (const_int 4) 9144 + (const_int 6)))]) 9145 + 9146 +(define_insn "cbranchne" 9147 + [(set (pc) (if_then_else 9148 + (ne (match_operand:SI 0 "score_register_operand" "d") 9149 + (match_operand:SI 1 "score_register_operand" "d")) 9150 + (label_ref (match_operand 2 "" "")) 9151 + (pc))) 9152 + (clobber (reg:CC CC_REGNUM))] 9153 + "(TARGET_SCORE3)" 9154 +{ 9155 + if (get_attr_length (insn) == 4) 9156 + return \"bcmpne\t%0, %1, %2\"; 9157 + else 9158 + return \"cmp!\t%0, %1\;bne\t%2\"; 9159 +} 9160 + [(set (attr "length") 9161 + (if_then_else 9162 + (and (ge (minus (match_dup 2) (pc)) (const_int -504)) 9163 + (le (minus (match_dup 2) (pc)) (const_int 502))) 9164 + (const_int 4) 9165 + (const_int 6)))]) 9166 + 9167 (define_expand "cmpsi" 9168 - [(match_operand:SI 0 "register_operand" "") 9169 - (match_operand:SI 1 "arith_operand" "")] 9170 + [(match_operand:SI 0 "score_register_operand") 9171 + (match_operand:SI 1 "arith_operand")] 9172 "" 9173 { 9174 cmp_op0 = operands[0]; 9175 @@ -1070,11 +2269,11 @@ 9176 DONE; 9177 }) 9178 9179 -(define_insn "cmpsi_nz" 9180 +(define_insn "cmpsi_nz_score7" 9181 [(set (reg:CC_NZ CC_REGNUM) 9182 (compare:CC_NZ (match_operand:SI 0 "register_operand" "d,e,d") 9183 (match_operand:SI 1 "arith_operand" "L,e,d")))] 9184 - "" 9185 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 9186 "@ 9187 cmpi.c %0, %c1 9188 cmp! %0, %1 9189 @@ -1083,11 +2282,25 @@ 9190 (set_attr "up_c" "yes") 9191 (set_attr "mode" "SI")]) 9192 9193 -(define_insn "cmpsi_n" 9194 +(define_insn "cmpsi_nz_score3" 9195 + [(set (reg:CC_NZ CC_REGNUM) 9196 + (compare:CC_NZ (match_operand:SI 0 "score_register_operand" "d,d,d") 9197 + (match_operand:SI 1 "arith_operand" "O,L,d")))] 9198 + "(TARGET_SCORE3)" 9199 + "@ 9200 + cmpi!\t%0, %c1 9201 + cmpi.c\t%0, %c1 9202 + cmp!\t %0, %1" 9203 + [(set_attr "type" "cmp") 9204 + (set_attr "length" "2,4,2") 9205 + (set_attr "up_c" "yes") 9206 + (set_attr "mode" "SI")]) 9207 + 9208 +(define_insn "cmpsi_n_score7" 9209 [(set (reg:CC_N CC_REGNUM) 9210 (compare:CC_N (match_operand:SI 0 "register_operand" "d,e,d") 9211 (match_operand:SI 1 "arith_operand" "L,e,d")))] 9212 - "" 9213 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 9214 "@ 9215 cmpi.c %0, %c1 9216 cmp! %0, %1 9217 @@ -1096,12 +2309,26 @@ 9218 (set_attr "up_c" "yes") 9219 (set_attr "mode" "SI")]) 9220 9221 -(define_insn "*cmpsi_to_addsi" 9222 +(define_insn "cmpsi_n_score3" 9223 + [(set (reg:CC_N CC_REGNUM) 9224 + (compare:CC_N (match_operand:SI 0 "score_register_operand" "d,d,d") 9225 + (match_operand:SI 1 "arith_operand" "O,L,d")))] 9226 + "(TARGET_SCORE3)" 9227 + "@ 9228 + cmpi!\t%0, %c1 9229 + cmpi.c\t%0, %c1 9230 + cmp!\t%0, %1" 9231 + [(set_attr "type" "cmp") 9232 + (set_attr "length" "2,4,2") 9233 + (set_attr "up_c" "yes") 9234 + (set_attr "mode" "SI")]) 9235 + 9236 +(define_insn "*cmpsi_to_addsi_score7" 9237 [(set (reg:CC_NZ CC_REGNUM) 9238 (compare:CC_NZ (match_operand:SI 1 "register_operand" "0,d") 9239 (neg:SI (match_operand:SI 2 "register_operand" "e,d")))) 9240 (clobber (match_scratch:SI 0 "=e,d"))] 9241 - "" 9242 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 9243 "@ 9244 add! %0, %2 9245 add.c %0, %1, %2" 9246 @@ -1109,11 +2336,23 @@ 9247 (set_attr "up_c" "yes") 9248 (set_attr "mode" "SI")]) 9249 9250 -(define_insn "cmpsi_cc" 9251 +(define_insn "*cmpsi_to_addsi_score3" 9252 + [(set (reg:CC_NZ CC_REGNUM) 9253 + (compare:CC_NZ (match_operand:SI 1 "score_register_operand" "d") 9254 + (neg:SI (match_operand:SI 2 "score_register_operand" "d")))) 9255 + (clobber (match_scratch:SI 0 "=d"))] 9256 + "(TARGET_SCORE3)" 9257 + "add.c\t%0, %1, %2" 9258 + [(set_attr "type" "cmp") 9259 + (set_attr "length" "4") 9260 + (set_attr "up_c" "yes") 9261 + (set_attr "mode" "SI")]) 9262 + 9263 +(define_insn "cmpsi_cc_score7" 9264 [(set (reg:CC CC_REGNUM) 9265 (compare:CC (match_operand:SI 0 "register_operand" "d,e,d") 9266 (match_operand:SI 1 "arith_operand" "L,e,d")))] 9267 - "" 9268 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 9269 "@ 9270 cmpi.c %0, %c1 9271 cmp! %0, %1 9272 @@ -1122,6 +2361,20 @@ 9273 (set_attr "up_c" "yes") 9274 (set_attr "mode" "SI")]) 9275 9276 +(define_insn "cmpsi_cc_score3" 9277 + [(set (reg:CC CC_REGNUM) 9278 + (compare:CC (match_operand:SI 0 "score_register_operand" "d,d,d") 9279 + (match_operand:SI 1 "arith_operand" "O,L,d")))] 9280 + "(TARGET_SCORE3)" 9281 + "@ 9282 + cmpi!\t%0, %c1 9283 + cmpi.c\t%0, %c1 9284 + cmp!\t%0, %1" 9285 + [(set_attr "type" "cmp") 9286 + (set_attr "length" "2,4,2") 9287 + (set_attr "up_c" "yes") 9288 + (set_attr "mode" "SI")]) 9289 + 9290 (define_expand "beq" 9291 [(set (pc) 9292 (if_then_else (eq (reg:CC CC_REGNUM) (const_int 0)) 9293 @@ -1129,7 +2382,7 @@ 9294 (pc)))] 9295 "" 9296 { 9297 - mda_gen_cmp (CCmode); 9298 + score_gen_cmp (CCmode); 9299 }) 9300 9301 (define_expand "bne" 9302 @@ -1139,7 +2392,7 @@ 9303 (pc)))] 9304 "" 9305 { 9306 - mda_gen_cmp (CCmode); 9307 + score_gen_cmp (CCmode); 9308 }) 9309 9310 (define_expand "bgt" 9311 @@ -1149,7 +2402,7 @@ 9312 (pc)))] 9313 "" 9314 { 9315 - mda_gen_cmp (CCmode); 9316 + score_gen_cmp (CCmode); 9317 }) 9318 9319 (define_expand "ble" 9320 @@ -1159,7 +2412,7 @@ 9321 (pc)))] 9322 "" 9323 { 9324 - mda_gen_cmp (CCmode); 9325 + score_gen_cmp (CCmode); 9326 }) 9327 9328 (define_expand "bge" 9329 @@ -1169,7 +2422,7 @@ 9330 (pc)))] 9331 "" 9332 { 9333 - mda_gen_cmp (CCmode); 9334 + score_gen_cmp (CCmode); 9335 }) 9336 9337 (define_expand "blt" 9338 @@ -1179,7 +2432,7 @@ 9339 (pc)))] 9340 "" 9341 { 9342 - mda_gen_cmp (CCmode); 9343 + score_gen_cmp (CCmode); 9344 }) 9345 9346 (define_expand "bgtu" 9347 @@ -1189,7 +2442,7 @@ 9348 (pc)))] 9349 "" 9350 { 9351 - mda_gen_cmp (CCmode); 9352 + score_gen_cmp (CCmode); 9353 }) 9354 9355 (define_expand "bleu" 9356 @@ -1199,7 +2452,7 @@ 9357 (pc)))] 9358 "" 9359 { 9360 - mda_gen_cmp (CCmode); 9361 + score_gen_cmp (CCmode); 9362 }) 9363 9364 (define_expand "bgeu" 9365 @@ -1209,7 +2462,7 @@ 9366 (pc)))] 9367 "" 9368 { 9369 - mda_gen_cmp (CCmode); 9370 + score_gen_cmp (CCmode); 9371 }) 9372 9373 (define_expand "bltu" 9374 @@ -1219,10 +2472,10 @@ 9375 (pc)))] 9376 "" 9377 { 9378 - mda_gen_cmp (CCmode); 9379 + score_gen_cmp (CCmode); 9380 }) 9381 9382 -(define_insn "branch_n" 9383 +(define_insn "*branch_n_score7" 9384 [(set (pc) 9385 (if_then_else 9386 (match_operator 0 "branch_n_operator" 9387 @@ -1230,11 +2483,24 @@ 9388 (const_int 0)]) 9389 (label_ref (match_operand 1 "" "")) 9390 (pc)))] 9391 - "" 9392 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 9393 "b%C0 %1" 9394 [(set_attr "type" "branch")]) 9395 9396 -(define_insn "branch_nz" 9397 +(define_insn "*branch_n_score3" 9398 + [(set (pc) 9399 + (if_then_else 9400 + (match_operator 0 "branch_n_operator" 9401 + [(reg:CC_N CC_REGNUM) 9402 + (const_int 0)]) 9403 + (label_ref (match_operand 1 "" "")) 9404 + (pc)))] 9405 + "(TARGET_SCORE3)" 9406 + "b%C0\t%1" 9407 + [(set_attr "type" "branch") 9408 + (set_attr "length" "4")]) 9409 + 9410 +(define_insn "*branch_nz_score7" 9411 [(set (pc) 9412 (if_then_else 9413 (match_operator 0 "branch_nz_operator" 9414 @@ -1242,21 +2508,48 @@ 9415 (const_int 0)]) 9416 (label_ref (match_operand 1 "" "")) 9417 (pc)))] 9418 - "" 9419 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 9420 "b%C0 %1" 9421 [(set_attr "type" "branch")]) 9422 9423 -(define_insn "branch_cc" 9424 +(define_insn "*branch_nz_score3" 9425 [(set (pc) 9426 (if_then_else 9427 - (match_operator 0 "comparison_operator" 9428 - [(reg:CC CC_REGNUM) 9429 + (match_operator 0 "branch_nz_operator" 9430 + [(reg:CC_NZ CC_REGNUM) 9431 (const_int 0)]) 9432 (label_ref (match_operand 1 "" "")) 9433 (pc)))] 9434 - "" 9435 - "b%C0 %1" 9436 - [(set_attr "type" "branch")]) 9437 + "(TARGET_SCORE3)" 9438 + "b%C0\t%1" 9439 + [(set_attr "type" "branch") 9440 + (set_attr "length" "4")]) 9441 + 9442 + 9443 +(define_insn "*branch_cc_score7" 9444 + [(set (pc) 9445 + (if_then_else 9446 + (match_operator 0 "comparison_operator" 9447 + [(reg:CC CC_REGNUM) 9448 + (const_int 0)]) 9449 + (label_ref (match_operand 1 "" "")) 9450 + (pc)))] 9451 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 9452 + "b%C0 %1" 9453 + [(set_attr "type" "branch")]) 9454 + 9455 +(define_insn "*branch_cc_score3" 9456 + [(set (pc) 9457 + (if_then_else 9458 + (match_operator 0 "comparison_operator" 9459 + [(reg:CC CC_REGNUM) 9460 + (const_int 0)]) 9461 + (label_ref (match_operand 1 "" "")) 9462 + (pc)))] 9463 + "(TARGET_SCORE3)" 9464 + "b%C0\t%1" 9465 + [(set_attr "type" "branch") 9466 + (set_attr "length" "4")]) 9467 9468 (define_insn "jump" 9469 [(set (pc) 9470 @@ -1264,11 +2557,12 @@ 9471 "" 9472 { 9473 if (!flag_pic) 9474 - return \"j %0\"; 9475 + return \"j\t%0\"; 9476 else 9477 - return \"b %0\"; 9478 + return \"b\t%0\"; 9479 } 9480 - [(set_attr "type" "jump")]) 9481 + [(set_attr "type" "jump") 9482 + (set_attr "length" "4")]) 9483 9484 (define_expand "sibcall" 9485 [(parallel [(call (match_operand 0 "" "") 9486 @@ -1276,135 +2570,235 @@ 9487 (use (match_operand 2 "" ""))])] 9488 "" 9489 { 9490 - mdx_call (operands, true); 9491 + score_call (operands, true); 9492 DONE; 9493 }) 9494 9495 -(define_insn "sibcall_internal" 9496 +(define_insn "sibcall_internal_score7" 9497 [(call (mem:SI (match_operand:SI 0 "call_insn_operand" "t,Z")) 9498 (match_operand 1 "" "")) 9499 (clobber (reg:SI RT_REGNUM))] 9500 - "SIBLING_CALL_P (insn)" 9501 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 9502 + && SIBLING_CALL_P (insn)" 9503 { 9504 if (!flag_pic) 9505 switch (which_alternative) 9506 { 9507 - case 0: return \"br%S0 %0\"; 9508 - case 1: return \"j %0\"; 9509 + case 0: return \"br%S0\t%0\"; 9510 + case 1: return \"j\t%0\"; 9511 default: gcc_unreachable (); 9512 } 9513 else 9514 switch (which_alternative) 9515 { 9516 - case 0: return \"mv r29, %0\;br r29\"; 9517 - case 1: return \"la r29, %0\;br r29\"; 9518 + case 0: return \"mv\tr29, %0\;br\tr29\"; 9519 + case 1: return \"la\tr29, %0\;br\tr29\"; 9520 default: gcc_unreachable (); 9521 } 9522 } 9523 [(set_attr "type" "call")]) 9524 9525 +(define_insn "sibcall_internal_score3" 9526 + [(call (mem:SI (match_operand:SI 0 "call_insn_operand" "t,Z")) 9527 + (match_operand 1 "" "")) 9528 + (clobber (reg:SI RT_REGNUM))] 9529 + "(TARGET_SCORE3) && (SIBLING_CALL_P (insn))" 9530 +{ 9531 + if (!flag_pic) 9532 + switch (which_alternative) 9533 + { 9534 + case 0: return \"br%S0\t%0\"; 9535 + case 1: return \"j\t%0\"; 9536 + default: gcc_unreachable (); 9537 + } 9538 + else 9539 + switch (which_alternative) 9540 + { 9541 + case 0: return \"mv!\tr29, %0\;br!\tr29\"; 9542 + case 1: return \"ldi48\tr29, %0\;br!\tr29\"; 9543 + default: gcc_unreachable (); 9544 + } 9545 +} 9546 + [(set_attr "type" "call") 9547 + (set_attr "length" "4,8")]) 9548 + 9549 (define_expand "sibcall_value" 9550 [(parallel [(set (match_operand 0 "" "") 9551 (call (match_operand 1 "" "") (match_operand 2 "" ""))) 9552 (use (match_operand 3 "" ""))])] 9553 "" 9554 { 9555 - mdx_call_value (operands, true); 9556 + score_call_value (operands, true); 9557 DONE; 9558 }) 9559 9560 -(define_insn "sibcall_value_internal" 9561 +(define_insn "sibcall_value_internal_score7" 9562 [(set (match_operand 0 "register_operand" "=d,d") 9563 (call (mem:SI (match_operand:SI 1 "call_insn_operand" "t,Z")) 9564 (match_operand 2 "" ""))) 9565 (clobber (reg:SI RT_REGNUM))] 9566 - "SIBLING_CALL_P (insn)" 9567 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 9568 + && SIBLING_CALL_P (insn)" 9569 { 9570 if (!flag_pic) 9571 switch (which_alternative) 9572 { 9573 - case 0: return \"br%S1 %1\"; 9574 - case 1: return \"j %1\"; 9575 + case 0: return \"br%S1\t%1\"; 9576 + case 1: return \"j\t%1\"; 9577 default: gcc_unreachable (); 9578 } 9579 else 9580 switch (which_alternative) 9581 { 9582 - case 0: return \"mv r29, %1\;br r29\"; 9583 - case 1: return \"la r29, %1\;br r29\"; 9584 + case 0: return \"mv\tr29, %1\;br\tr29\"; 9585 + case 1: return \"la\tr29, %1\;br\tr29\"; 9586 default: gcc_unreachable (); 9587 } 9588 } 9589 [(set_attr "type" "call")]) 9590 9591 +(define_insn "sibcall_value_internal_score3" 9592 + [(set (match_operand 0 "score_register_operand" "=d,d") 9593 + (call (mem:SI (match_operand:SI 1 "call_insn_operand" "t,Z")) 9594 + (match_operand 2 "" ""))) 9595 + (clobber (reg:SI RT_REGNUM))] 9596 + "(TARGET_SCORE3) && (SIBLING_CALL_P (insn))" 9597 +{ 9598 + if (!flag_pic) 9599 + switch (which_alternative) 9600 + { 9601 + case 0: return \"br%S1\t%1\"; 9602 + case 1: return \"j\t%1\"; 9603 + default: gcc_unreachable (); 9604 + } 9605 + else 9606 + switch (which_alternative) 9607 + { 9608 + case 0: return \"mv!\tr29, %1\;br!\tr29\"; 9609 + case 1: return \"ldi48\tr29, %1\;br!\tr29\"; 9610 + default: gcc_unreachable (); 9611 + } 9612 +} 9613 + [(set_attr "length" "4,8") 9614 + (set_attr "type" "call")]) 9615 + 9616 (define_expand "call" 9617 [(parallel [(call (match_operand 0 "" "") (match_operand 1 "" "")) 9618 (use (match_operand 2 "" ""))])] 9619 "" 9620 { 9621 - mdx_call (operands, false); 9622 + score_call (operands, false); 9623 DONE; 9624 }) 9625 9626 -(define_insn "call_internal" 9627 +(define_insn "call_internal_score7" 9628 [(call (mem:SI (match_operand:SI 0 "call_insn_operand" "d,Z")) 9629 (match_operand 1 "" "")) 9630 (clobber (reg:SI RA_REGNUM))] 9631 - "" 9632 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 9633 { 9634 if (!flag_pic) 9635 switch (which_alternative) 9636 { 9637 - case 0: return \"brl%S0 %0\"; 9638 - case 1: return \"jl %0\"; 9639 + case 0: return \"brl%S0\t%0\"; 9640 + case 1: return \"jl\t%0\"; 9641 default: gcc_unreachable (); 9642 } 9643 else 9644 switch (which_alternative) 9645 { 9646 - case 0: return \"mv r29, %0\;brl r29\"; 9647 - case 1: return \"la r29, %0\;brl r29\"; 9648 + case 0: return \"mv\tr29, %0\;brl\tr29\"; 9649 + case 1: return \"la\tr29, %0\;brl\tr29\"; 9650 default: gcc_unreachable (); 9651 } 9652 } 9653 [(set_attr "type" "call")]) 9654 9655 +(define_insn "call_internal_score3" 9656 + [(call (mem:SI (match_operand:SI 0 "call_insn_operand" "d,Z")) 9657 + (match_operand 1 "" "")) 9658 + (clobber (reg:SI RA_REGNUM))] 9659 + "(TARGET_SCORE3)" 9660 +{ 9661 + if (!flag_pic) 9662 + switch (which_alternative) 9663 + { 9664 + case 0: return \"brl!\t%0\"; 9665 + case 1: return \"jl\t%0\"; 9666 + default: gcc_unreachable (); 9667 + } 9668 + else 9669 + switch (which_alternative) 9670 + { 9671 + case 0: return \"mv!\tr29, %0\;brl!\tr29\"; 9672 + case 1: return \"ldi48\tr29, %0\;brl!\tr29\"; 9673 + default: gcc_unreachable (); 9674 + } 9675 +} 9676 + [(set_attr "length" "4,8") 9677 + (set_attr "type" "call")]) 9678 + 9679 (define_expand "call_value" 9680 [(parallel [(set (match_operand 0 "" "") 9681 (call (match_operand 1 "" "") (match_operand 2 "" ""))) 9682 (use (match_operand 3 "" ""))])] 9683 "" 9684 { 9685 - mdx_call_value (operands, false); 9686 + score_call_value (operands, false); 9687 DONE; 9688 }) 9689 9690 -(define_insn "call_value_internal" 9691 +(define_insn "call_value_internal_score7" 9692 [(set (match_operand 0 "register_operand" "=d,d") 9693 (call (mem:SI (match_operand:SI 1 "call_insn_operand" "d,Z")) 9694 (match_operand 2 "" ""))) 9695 (clobber (reg:SI RA_REGNUM))] 9696 - "" 9697 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 9698 { 9699 if (!flag_pic) 9700 switch (which_alternative) 9701 { 9702 - case 0: return \"brl%S1 %1\"; 9703 - case 1: return \"jl %1\"; 9704 + case 0: return \"brl%S1\t%1\"; 9705 + case 1: return \"jl\t%1\"; 9706 default: gcc_unreachable (); 9707 } 9708 else 9709 switch (which_alternative) 9710 { 9711 - case 0: return \"mv r29, %1\;brl r29\"; 9712 - case 1: return \"la r29, %1\;brl r29\"; 9713 + case 0: return \"mv\tr29, %1\;brl\tr29\"; 9714 + case 1: return \"la\tr29, %1\;brl\tr29\"; 9715 default: gcc_unreachable (); 9716 } 9717 } 9718 [(set_attr "type" "call")]) 9719 9720 +(define_insn "call_value_internal_score3" 9721 + [(set (match_operand 0 "score_register_operand" "=d,d") 9722 + (call (mem:SI (match_operand:SI 1 "call_insn_operand" "d,Z")) 9723 + (match_operand 2 "" ""))) 9724 + (clobber (reg:SI RA_REGNUM))] 9725 + "(TARGET_SCORE3)" 9726 +{ 9727 + if (!flag_pic) 9728 + switch (which_alternative) 9729 + { 9730 + case 0: return \"brl!\t%1\"; 9731 + case 1: return \"jl\t%1\"; 9732 + default: gcc_unreachable (); 9733 + } 9734 + else 9735 + switch (which_alternative) 9736 + { 9737 + case 0: return \"mv!\tr29, %1\;brl!\tr29\"; 9738 + case 1: return \"ldi48\tr29, %1\;brl!\tr29\"; 9739 + default: gcc_unreachable (); 9740 + } 9741 +} 9742 + [(set_attr "length" "4,8") 9743 + (set_attr "type" "call")]) 9744 + 9745 (define_expand "indirect_jump" 9746 - [(set (pc) (match_operand 0 "register_operand" "d"))] 9747 + [(set (pc) (match_operand 0 "score_register_operand" "d"))] 9748 "" 9749 { 9750 rtx dest; 9751 @@ -1413,44 +2807,105 @@ 9752 || GET_MODE (dest) != Pmode) 9753 operands[0] = copy_to_mode_reg (Pmode, dest); 9754 9755 - emit_jump_insn (gen_indirect_jump_internal1 (operands[0])); 9756 + emit_jump_insn (gen_indirect_jump_internal_score (operands[0])); 9757 DONE; 9758 }) 9759 9760 -(define_insn "indirect_jump_internal1" 9761 - [(set (pc) (match_operand:SI 0 "register_operand" "d"))] 9762 +(define_insn "indirect_jump_internal_score" 9763 + [(set (pc) (match_operand:SI 0 "score_register_operand" "d"))] 9764 "" 9765 "br%S0 %0" 9766 [(set_attr "type" "jump")]) 9767 9768 +(define_expand "casesi" 9769 + [(match_operand:SI 0 "score_register_operand" "") ; index to jump on 9770 + (match_operand:SI 1 "const_int_operand" "") ; lower bound 9771 + (match_operand:SI 2 "const_int_operand" "") ; total range 9772 + (match_operand:SI 3 "" "") ; table label 9773 + (match_operand:SI 4 "" "")] ; Out of range label 9774 + "TARGET_SCORE3" 9775 +{ 9776 + rtx reg; 9777 + if (operands[1] != const0_rtx) 9778 + { 9779 + reg = gen_reg_rtx (SImode); 9780 + emit_insn (gen_addsi3 (reg, operands[0], 9781 + GEN_INT (-INTVAL (operands[1])))); 9782 + operands[0] = reg; 9783 + } 9784 + 9785 + if (!CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'L')) 9786 + operands[2] = force_reg (SImode, operands[2]); 9787 + 9788 + reg = gen_reg_rtx (SImode); 9789 + emit_jump_insn (gen_score3_casesi_internal (operands[0], operands[2], 9790 + operands[3], operands[4], reg)); 9791 + DONE; 9792 +}) 9793 + 9794 +(define_insn "score3_casesi_internal" 9795 + [(parallel [(set (pc) 9796 + (if_then_else 9797 + (leu (match_operand:SI 0 "score_register_operand" "e") 9798 + (match_operand:SI 1 "arith_operand" "dL")) 9799 + (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4)) 9800 + (label_ref (match_operand 2 "" "")))) 9801 + (label_ref (match_operand 3 "" "")))) 9802 + (clobber (reg:CC CC_REGNUM)) 9803 + (clobber (match_operand:SI 4 "score_register_operand" "=e")) 9804 + (use (label_ref (match_dup 2)))])] 9805 + "TARGET_SCORE3 && !flag_pic" 9806 + "* 9807 + return score_output_casesi(operands); 9808 + " 9809 + [(set_attr "length" "20")]) 9810 + 9811 (define_expand "tablejump" 9812 [(set (pc) 9813 - (match_operand 0 "register_operand" "d")) 9814 + (match_operand 0 "score_register_operand" "d")) 9815 (use (label_ref (match_operand 1 "" "")))] 9816 "" 9817 { 9818 - emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1])); 9819 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 9820 + emit_jump_insn (gen_tablejump_internal_score7 (operands[0], operands[1])); 9821 + else if (TARGET_SCORE3) 9822 + emit_jump_insn (gen_tablejump_internal_score3 (operands[0], operands[1])); 9823 + 9824 DONE; 9825 }) 9826 9827 -(define_insn "tablejump_internal1" 9828 +(define_insn "tablejump_internal_score7" 9829 [(set (pc) 9830 (match_operand:SI 0 "register_operand" "d")) 9831 (use (label_ref (match_operand 1 "" "")))] 9832 - "" 9833 - "* 9834 - if (flag_pic) 9835 - return \"mv r29, %0\;.cpadd r29\;br r29\"; 9836 - else 9837 - return \"br%S0 %0\"; 9838 - " 9839 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 9840 +{ 9841 + if (flag_pic) 9842 + return \"mv\tr29, %0\;.cpadd\tr29\;br\tr29\"; 9843 + else 9844 + return \"br%S0\t%0\"; 9845 +} 9846 [(set_attr "type" "jump")]) 9847 9848 +(define_insn "tablejump_internal_score3" 9849 + [(set (pc) 9850 + (match_operand:SI 0 "score_register_operand" "d")) 9851 + (use (label_ref (match_operand 1 "" "")))] 9852 + "(TARGET_SCORE3)" 9853 +{ 9854 + if (flag_pic) 9855 + return \"mv!\tr29, %0\;.cpadd\tr29\;br!\tr29\"; 9856 + else 9857 + return \"br%S0\t%0\"; 9858 +} 9859 + [(set_attr "type" "jump") 9860 + (set_attr "length" "8")]) 9861 + 9862 (define_expand "prologue" 9863 [(const_int 1)] 9864 "" 9865 { 9866 - mdx_prologue (); 9867 + score_prologue (); 9868 DONE; 9869 }) 9870 9871 @@ -1458,7 +2913,7 @@ 9872 [(const_int 2)] 9873 "" 9874 { 9875 - mdx_epilogue (false); 9876 + score_epilogue (false); 9877 DONE; 9878 }) 9879 9880 @@ -1466,15 +2921,22 @@ 9881 [(const_int 2)] 9882 "" 9883 { 9884 - mdx_epilogue (true); 9885 + score_epilogue (true); 9886 DONE; 9887 }) 9888 9889 -(define_insn "return_internal" 9890 +(define_insn "return_internal_score7" 9891 [(return) 9892 (use (match_operand 0 "pmode_register_operand" "d"))] 9893 - "" 9894 - "br%S0 %0") 9895 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 9896 + "br%S0\t%0") 9897 + 9898 +(define_insn "return_internal_score3" 9899 + [(return) 9900 + (use (match_operand 0 "pmode_register_operand" "d"))] 9901 + "(TARGET_SCORE3)" 9902 + "br%S0\t%0" 9903 + [(set_attr "length" "4")]) 9904 9905 (define_insn "nop" 9906 [(const_int 0)] 9907 @@ -1482,26 +2944,49 @@ 9908 "#nop!" 9909 ) 9910 9911 -(define_insn "cpload" 9912 +(define_insn "cpload_score7" 9913 [(unspec_volatile:SI [(const_int 1)] CPLOAD)] 9914 - "flag_pic" 9915 - ".cpload r29" 9916 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 9917 + && flag_pic" 9918 + ".cpload\tr29" 9919 ) 9920 9921 -(define_insn "cprestore_use_fp" 9922 +(define_insn "cpload_score3" 9923 + [(unspec_volatile:SI [(const_int 1)] CPLOAD)] 9924 + "(TARGET_SCORE3) && flag_pic" 9925 + ".cpload\tr29" 9926 + [(set_attr "length" "4")]) 9927 + 9928 +(define_insn "cprestore_use_fp_score7" 9929 [(unspec_volatile:SI [(match_operand:SI 0 "" "")] CPRESTORE) 9930 (use (reg:SI FP_REGNUM))] 9931 - "flag_pic" 9932 - ".cprestore r2, %0" 9933 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 9934 + && flag_pic" 9935 + ".cprestore\tr2, %0" 9936 ) 9937 9938 -(define_insn "cprestore_use_sp" 9939 +(define_insn "cprestore_use_fp_score3" 9940 + [(unspec_volatile:SI [(match_operand:SI 0 "" "")] CPRESTORE) 9941 + (use (reg:SI FP_REGNUM))] 9942 + "(TARGET_SCORE3) && flag_pic" 9943 + ".cprestore\tr2, %0" 9944 + [(set_attr "length" "4")]) 9945 + 9946 +(define_insn "cprestore_use_sp_score7" 9947 [(unspec_volatile:SI [(match_operand:SI 0 "" "")] CPRESTORE) 9948 (use (reg:SI SP_REGNUM))] 9949 - "flag_pic" 9950 - ".cprestore r0, %0" 9951 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D) 9952 + && flag_pic" 9953 + ".cprestore\tr0, %0" 9954 ) 9955 9956 +(define_insn "cprestore_use_sp_score3" 9957 + [(unspec_volatile:SI [(match_operand:SI 0 "" "")] CPRESTORE) 9958 + (use (reg:SI SP_REGNUM))] 9959 + "(TARGET_SCORE3) && flag_pic" 9960 + ".cprestore\tr0, %0" 9961 + [(set_attr "length" "4")]) 9962 + 9963 (define_expand "doloop_end" 9964 [(use (match_operand 0 "" "")) ; loop pseudo 9965 (use (match_operand 1 "" "")) ; iterations; zero if unknown 9966 @@ -1509,20 +2994,20 @@ 9967 (use (match_operand 3 "" "")) ; loop level 9968 (use (match_operand 4 "" ""))] ; label 9969 "!TARGET_NHWLOOP" 9970 - { 9971 - if (INTVAL (operands[3]) > 1) 9972 - FAIL; 9973 +{ 9974 + if (INTVAL (operands[3]) > 1) 9975 + FAIL; 9976 9977 - if (GET_MODE (operands[0]) == SImode) 9978 - { 9979 - rtx sr0 = gen_rtx_REG (SImode, CN_REGNUM); 9980 - emit_jump_insn (gen_doloop_end_si (sr0, operands[4])); 9981 - } 9982 - else 9983 - FAIL; 9984 + if (GET_MODE (operands[0]) == SImode) 9985 + { 9986 + rtx sr0 = gen_rtx_REG (SImode, CN_REGNUM); 9987 + emit_jump_insn (gen_doloop_end_si (sr0, operands[4])); 9988 + } 9989 + else 9990 + FAIL; 9991 9992 - DONE; 9993 - }) 9994 + DONE; 9995 +}) 9996 9997 (define_insn "doloop_end_si" 9998 [(set (pc) 9999 @@ -1534,8 +3019,692 @@ 10000 (set (match_dup 0) 10001 (plus:SI (match_dup 0) 10002 (const_int -1))) 10003 - (clobber (reg:CC CC_REGNUM)) 10004 -] 10005 + (clobber (reg:CC CC_REGNUM))] 10006 "!TARGET_NHWLOOP" 10007 "bcnz %1" 10008 - [(set_attr "type" "branch")]) 10009 + [(set_attr "type" "branch") 10010 + (set_attr "length" "4")]) 10011 + 10012 +(define_insn "pushsi_score7" 10013 + [(set (match_operand:SI 0 "push_operand" "=<") 10014 + (match_operand:SI 1 "register_operand" "d"))] 10015 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 10016 + "push!\t%1, [r0]" 10017 + [(set_attr "type" "store") 10018 + (set_attr "mode" "SI")]) 10019 + 10020 +(define_insn "pushsi_score3" 10021 + [(set (match_operand:SI 0 "push_operand" "=<") 10022 + (match_operand:SI 1 "register_operand" "d"))] 10023 + "(TARGET_SCORE3)" 10024 + "push!\t%1" 10025 + [(set_attr "type" "store") 10026 + (set_attr "length" "2") 10027 + (set_attr "mode" "SI")]) 10028 + 10029 +(define_insn "popsi_score7" 10030 + [(set (match_operand:SI 0 "register_operand" "=d") 10031 + (match_operand:SI 1 "pop_operand" ">"))] 10032 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 10033 + "pop!\t%0, [r0]" 10034 + [(set_attr "type" "store") 10035 + (set_attr "mode" "SI")]) 10036 + 10037 +(define_insn "popsi_score3" 10038 + [(set (match_operand:SI 0 "register_operand" "=d") 10039 + (match_operand:SI 1 "pop_operand" ">"))] 10040 + "(TARGET_SCORE3)" 10041 + "pop!\t%0" 10042 + [(set_attr "type" "store") 10043 + (set_attr "length" "2") 10044 + (set_attr "mode" "SI")]) 10045 + 10046 +(define_expand "load_multiple" 10047 + [(match_par_dup 3 [(set (match_operand:SI 0 "" "") 10048 + (match_operand:SI 1 "" "")) 10049 + (use (match_operand:SI 2 "" "")) 10050 + (clobber (reg:SI 0))])] 10051 + "(TARGET_SCORE3)" 10052 +{ 10053 + int regno, count, i; 10054 + 10055 + if (GET_CODE (operands[2]) != CONST_INT 10056 + || INTVAL (operands[2]) < 2 10057 + || GET_CODE (operands[1]) != MEM 10058 + || XEXP (operands[1], 0) != stack_pointer_rtx 10059 + || GET_CODE (operands[0]) != REG) 10060 + FAIL; 10061 + 10062 + count = INTVAL (operands[2]); 10063 + regno = REGNO (operands[0]); 10064 + 10065 + operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); 10066 + 10067 + for (i = 0; i < count; i++) 10068 + XVECEXP (operands[3], 0, i) 10069 + = gen_rtx_SET (VOIDmode, 10070 + gen_rtx_REG (SImode, regno + i), 10071 + gen_rtx_MEM (SImode, gen_rtx_POST_INC (SImode, stack_pointer_rtx))); 10072 +}) 10073 + 10074 +(define_insn "" 10075 + [(match_parallel 0 "score_load_multiple_operation" 10076 + [(set (match_operand:SI 1 "register_operand" "=d") 10077 + (mem:SI (post_inc:SI (reg:SI SP_REGNUM))))])] 10078 + "(TARGET_SCORE3)" 10079 +{ 10080 + return score_rpop (operands); 10081 +} 10082 + [(set_attr "length" "2")]) 10083 + 10084 +(define_expand "store_multiple" 10085 + [(match_par_dup 3 [(set (match_operand:SI 0 "" "") 10086 + (match_operand:SI 1 "" "")) 10087 + (use (match_operand:SI 2 "" "")) 10088 + (clobber (reg:SI 0))])] 10089 + "(TARGET_SCORE3)" 10090 +{ 10091 + int regno, count, i; 10092 + 10093 + if (GET_CODE (operands[2]) != CONST_INT 10094 + || INTVAL (operands[2]) < 2 10095 + || GET_CODE (operands[0]) != MEM 10096 + || XEXP (operands[0], 0) != stack_pointer_rtx 10097 + || GET_CODE (operands[1]) != REG) 10098 + FAIL; 10099 + 10100 + count = INTVAL (operands[2]); 10101 + regno = REGNO (operands[1]); 10102 + 10103 + operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); 10104 + 10105 + for (i = 0; i < count; i++) 10106 + XVECEXP (operands[3], 0, i) 10107 + = gen_rtx_SET (VOIDmode, 10108 + gen_rtx_MEM (SImode, gen_rtx_PRE_DEC (SImode, stack_pointer_rtx)), 10109 + gen_rtx_REG (SImode, regno + i)); 10110 +}) 10111 + 10112 +(define_insn "" 10113 + [(match_parallel 0 "score_store_multiple_operation" 10114 + [(set (mem:SI (pre_dec:SI (reg:SI SP_REGNUM))) 10115 + (match_operand:SI 1 "register_operand" "d"))])] 10116 + "(TARGET_SCORE3)" 10117 +{ 10118 + return score_rpush (operands); 10119 +} 10120 + [(set_attr "length" "2")]) 10121 + 10122 +(define_peephole2 10123 + [(set (match_operand:SI 0 "g32reg_operand" "") 10124 + (match_operand:SI 1 "loreg_operand" "")) 10125 + (set (match_operand:SI 2 "g32reg_operand" "") 10126 + (match_operand:SI 3 "hireg_operand" ""))] 10127 + "" 10128 + [(parallel 10129 + [(set (match_dup 0) (match_dup 1)) 10130 + (set (match_dup 2) (match_dup 3))])]) 10131 + 10132 +(define_peephole2 10133 + [(set (match_operand:SI 0 "g32reg_operand" "") 10134 + (match_operand:SI 1 "hireg_operand" "")) 10135 + (set (match_operand:SI 2 "g32reg_operand" "") 10136 + (match_operand:SI 3 "loreg_operand" ""))] 10137 + "" 10138 + [(parallel 10139 + [(set (match_dup 2) (match_dup 3)) 10140 + (set (match_dup 0) (match_dup 1))])]) 10141 + 10142 +(define_insn "movhilo" 10143 + [(parallel 10144 + [(set (match_operand:SI 0 "register_operand" "=d") 10145 + (match_operand:SI 1 "loreg_operand" "")) 10146 + (set (match_operand:SI 2 "register_operand" "=d") 10147 + (match_operand:SI 3 "hireg_operand" ""))])] 10148 + "" 10149 + "mfcehl\t%2, %0" 10150 + [(set_attr "type" "fce") 10151 + (set_attr "mode" "SI")]) 10152 + 10153 +(define_expand "movsicc" 10154 + [(set (match_operand:SI 0 "register_operand" "") 10155 + (if_then_else:SI (match_operator 1 "comparison_operator" 10156 + [(reg:CC CC_REGNUM) (const_int 0)]) 10157 + (match_operand:SI 2 "register_operand" "") 10158 + (match_operand:SI 3 "register_operand" "")))] 10159 + "" 10160 +{ 10161 + score_movsicc (operands); 10162 +}) 10163 + 10164 +(define_insn "movsicc_internal_score7" 10165 + [(set (match_operand:SI 0 "register_operand" "=d") 10166 + (if_then_else:SI (match_operator 1 "comparison_operator" 10167 + [(reg:CC CC_REGNUM) (const_int 0)]) 10168 + (match_operand:SI 2 "arith_operand" "d") 10169 + (match_operand:SI 3 "arith_operand" "0")))] 10170 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 10171 + "mv%C1\t%0, %2" 10172 + [(set_attr "type" "cndmv") 10173 + (set_attr "mode" "SI")]) 10174 + 10175 +(define_insn "movsicc_internal_score3" 10176 + [(set (match_operand:SI 0 "register_operand" "=d") 10177 + (if_then_else:SI (match_operator 1 "comparison_operator" 10178 + [(reg:CC CC_REGNUM) (const_int 0)]) 10179 + (match_operand:SI 2 "arith_operand" "d") 10180 + (match_operand:SI 3 "arith_operand" "0")))] 10181 + "(TARGET_SCORE3)" 10182 + "mv%G1\t%0, %2" 10183 + [(set_attr "type" "cndmv") 10184 + (set_attr "length" "4") 10185 + (set_attr "mode" "SI")]) 10186 + 10187 +(define_insn "zero_extract_bittst_score7" 10188 + [(set (reg:CC_NZ CC_REGNUM) 10189 + (compare:CC_NZ (unspec:SI 10190 + [(match_operand:SI 0 "register_operand" "*e,d") 10191 + (match_operand:SI 1 "const_uimm5" "")] 10192 + BITTST) 10193 + (const_int 0)))] 10194 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)" 10195 + "@ 10196 + bittst!\t%0, %c1 10197 + bittst.c\t%0, %c1" 10198 + [(set_attr "type" "arith") 10199 + (set_attr "up_c" "yes") 10200 + (set_attr "mode" "SI")]) 10201 + 10202 +(define_insn "zero_extract_bittst_score3" 10203 + [(set (reg:CC_NZ CC_REGNUM) 10204 + (compare:CC_NZ (unspec:SI 10205 + [(match_operand:SI 0 "register_operand" "e,d") 10206 + (match_operand:SI 1 "const_uimm5" "")] 10207 + BITTST) 10208 + (const_int 0)))] 10209 + "(TARGET_SCORE3)" 10210 + "@ 10211 + bittst!\t%0, %c1 10212 + bittst.c\t%0, %c1" 10213 + [(set_attr "type" "arith") 10214 + (set_attr "length" "2,4") 10215 + (set_attr "up_c" "yes") 10216 + (set_attr "mode" "SI")]) 10217 + 10218 +(define_expand "extzv" 10219 + [(set (match_operand:SI 0 "register_operand" "") 10220 + (zero_extract (match_operand:SI 1 "memory_operand" "") 10221 + (match_operand:SI 2 "immediate_operand" "") 10222 + (match_operand:SI 3 "immediate_operand" "")))] 10223 + "((TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D) 10224 + && (!TARGET_LITTLE_ENDIAN) && (TARGET_ULS)) 10225 + || (TARGET_SCORE3 && TARGET_ULS)" 10226 +{ 10227 + if (score_unaligned_load (operands)) 10228 + DONE; 10229 + else 10230 + FAIL; 10231 +}) 10232 + 10233 +(define_expand "insv" 10234 + [(set (zero_extract (match_operand:SI 0 "memory_operand" "") 10235 + (match_operand:SI 1 "immediate_operand" "") 10236 + (match_operand:SI 2 "immediate_operand" "")) 10237 + (match_operand:SI 3 "register_operand" ""))] 10238 + "((TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D) 10239 + && (!TARGET_LITTLE_ENDIAN) && (TARGET_ULS)) 10240 + || (TARGET_SCORE3 && TARGET_ULS)" 10241 +{ 10242 + if (score_unaligned_store (operands)) 10243 + DONE; 10244 + else 10245 + FAIL; 10246 +}) 10247 + 10248 +(define_expand "extv" 10249 + [(set (match_operand:SI 0 "register_operand" "") 10250 + (sign_extract (match_operand:SI 1 "memory_operand" "") 10251 + (match_operand:SI 2 "immediate_operand" "") 10252 + (match_operand:SI 3 "immediate_operand" "")))] 10253 + "((TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D) 10254 + && (!TARGET_LITTLE_ENDIAN) && (TARGET_ULS)) 10255 + || (TARGET_SCORE3 && TARGET_ULS)" 10256 +{ 10257 + if (score_unaligned_load (operands)) 10258 + DONE; 10259 + else 10260 + FAIL; 10261 +}) 10262 + 10263 +(define_expand "movmemsi" 10264 + [(parallel [(set (match_operand:BLK 0 "general_operand") 10265 + (match_operand:BLK 1 "general_operand")) 10266 + (use (match_operand:SI 2 "")) 10267 + (use (match_operand:SI 3 "const_int_operand"))])] 10268 + "((TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D) 10269 + && (TARGET_ULS)) 10270 + || (TARGET_SCORE3 && TARGET_ULS)" 10271 +{ 10272 + if (score_block_move (operands)) 10273 + DONE; 10274 + else 10275 + FAIL; 10276 +}) 10277 + 10278 +(define_insn "move_lbu_a" 10279 + [(set (match_operand:SI 0 "register_operand" "=d") 10280 + (plus:SI (match_operand:SI 1 "register_operand" "0") 10281 + (match_operand:SI 2 "const_simm12" ""))) 10282 + (set (match_operand:QI 3 "register_operand" "=d") 10283 + (mem:QI (match_dup 1)))] 10284 + "" 10285 + "lbu\t%3, [%1]+, %2" 10286 + [(set_attr "type" "load") 10287 + (set_attr "length" "4") 10288 + (set_attr "mode" "QI")]) 10289 + 10290 +(define_insn "move_lhu_a" 10291 + [(set (match_operand:SI 0 "register_operand" "=d") 10292 + (plus:SI (match_operand:SI 1 "register_operand" "0") 10293 + (match_operand:SI 2 "const_simm12" ""))) 10294 + (set (match_operand:HI 3 "register_operand" "=d") 10295 + (mem:HI (match_dup 1)))] 10296 + "" 10297 + "lhu\t%3, [%1]+, %2" 10298 + [(set_attr "type" "load") 10299 + (set_attr "length" "4") 10300 + (set_attr "mode" "HI")]) 10301 + 10302 +(define_insn "move_lw_a" 10303 + [(set (match_operand:SI 0 "register_operand" "=d") 10304 + (plus:SI (match_operand:SI 1 "register_operand" "0") 10305 + (match_operand:SI 2 "const_simm12" ""))) 10306 + (set (match_operand:SI 3 "register_operand" "=d") 10307 + (mem:SI (match_dup 1)))] 10308 + "" 10309 + "lw\t%3, [%1]+, %2" 10310 + [(set_attr "type" "load") 10311 + (set_attr "length" "4") 10312 + (set_attr "mode" "SI")]) 10313 + 10314 +(define_insn "move_sb_a" 10315 + [(set (match_operand:SI 0 "register_operand" "=d") 10316 + (plus:SI (match_operand:SI 1 "register_operand" "0") 10317 + (match_operand:SI 2 "const_simm12" ""))) 10318 + (set (mem:QI (match_dup 1)) 10319 + (match_operand:QI 3 "register_operand" "d"))] 10320 + "" 10321 + "sb\t%3, [%1]+, %2" 10322 + [(set_attr "type" "store") 10323 + (set_attr "length" "4") 10324 + (set_attr "mode" "QI")]) 10325 + 10326 +(define_insn "move_sh_a" 10327 + [(set (match_operand:SI 0 "register_operand" "=d") 10328 + (plus:SI (match_operand:SI 1 "register_operand" "0") 10329 + (match_operand:SI 2 "const_simm12" ""))) 10330 + (set (mem:HI (match_dup 1)) 10331 + (match_operand:HI 3 "register_operand" "d"))] 10332 + "" 10333 + "sh\t%3, [%1]+, %2" 10334 + [(set_attr "type" "store") 10335 + (set_attr "length" "4") 10336 + (set_attr "mode" "HI")]) 10337 + 10338 +(define_insn "move_sw_a" 10339 + [(set (match_operand:SI 0 "register_operand" "=d") 10340 + (plus:SI (match_operand:SI 1 "register_operand" "0") 10341 + (match_operand:SI 2 "const_simm12" ""))) 10342 + (set (mem:SI (match_dup 1)) 10343 + (match_operand:SI 3 "register_operand" "d"))] 10344 + "" 10345 + "sw\t%3, [%1]+, %2" 10346 + [(set_attr "type" "store") 10347 + (set_attr "length" "4") 10348 + (set_attr "mode" "SI")]) 10349 + 10350 +(define_insn "move_lbu_b" 10351 + [(set (match_operand:SI 0 "register_operand" "=d") 10352 + (plus:SI (match_operand:SI 1 "register_operand" "0") 10353 + (match_operand:SI 2 "const_simm12" ""))) 10354 + (set (match_operand:QI 3 "register_operand" "=d") 10355 + (mem:QI (plus:SI (match_dup 1) 10356 + (match_dup 2))))] 10357 + "" 10358 + "lbu\t%3, [%1, %2]+" 10359 + [(set_attr "type" "load") 10360 + (set_attr "length" "4") 10361 + (set_attr "mode" "QI")]) 10362 + 10363 +(define_insn "move_lhu_b" 10364 + [(set (match_operand:SI 0 "register_operand" "=d") 10365 + (plus:SI (match_operand:SI 1 "register_operand" "0") 10366 + (match_operand:SI 2 "const_simm12" ""))) 10367 + (set (match_operand:HI 3 "register_operand" "=d") 10368 + (mem:HI (plus:SI (match_dup 1) 10369 + (match_dup 2))))] 10370 + "" 10371 + "lhu\t%3, [%1, %2]+" 10372 + [(set_attr "type" "load") 10373 + (set_attr "length" "4") 10374 + (set_attr "mode" "HI")]) 10375 + 10376 +(define_insn "move_lw_b" 10377 + [(set (match_operand:SI 0 "register_operand" "=d") 10378 + (plus:SI (match_operand:SI 1 "register_operand" "0") 10379 + (match_operand:SI 2 "const_simm12" ""))) 10380 + (set (match_operand:SI 3 "register_operand" "=d") 10381 + (mem:SI (plus:SI (match_dup 1) 10382 + (match_dup 2))))] 10383 + "" 10384 + "lw\t%3, [%1, %2]+" 10385 + [(set_attr "type" "load") 10386 + (set_attr "length" "4") 10387 + (set_attr "mode" "SI")]) 10388 + 10389 +(define_insn "move_sb_b" 10390 + [(set (match_operand:SI 0 "register_operand" "=d") 10391 + (plus:SI (match_operand:SI 1 "register_operand" "0") 10392 + (match_operand:SI 2 "const_simm12" ""))) 10393 + (set (mem:QI (plus:SI (match_dup 1) 10394 + (match_dup 2))) 10395 + (match_operand:QI 3 "register_operand" "d"))] 10396 + "" 10397 + "sb\t%3, [%1, %2]+" 10398 + [(set_attr "type" "store") 10399 + (set_attr "length" "4") 10400 + (set_attr "mode" "QI")]) 10401 + 10402 +(define_insn "move_sh_b" 10403 + [(set (match_operand:SI 0 "register_operand" "=d") 10404 + (plus:SI (match_operand:SI 1 "register_operand" "0") 10405 + (match_operand:SI 2 "const_simm12" ""))) 10406 + (set (mem:HI (plus:SI (match_dup 1) 10407 + (match_dup 2))) 10408 + (match_operand:HI 3 "register_operand" "d"))] 10409 + "" 10410 + "sh\t%3, [%1, %2]+" 10411 + [(set_attr "type" "store") 10412 + (set_attr "length" "4") 10413 + (set_attr "mode" "HI")]) 10414 + 10415 +(define_insn "move_sw_b" 10416 + [(set (match_operand:SI 0 "register_operand" "=d") 10417 + (plus:SI (match_operand:SI 1 "register_operand" "0") 10418 + (match_operand:SI 2 "const_simm12" ""))) 10419 + (set (mem:SI (plus:SI (match_dup 1) 10420 + (match_dup 2))) 10421 + (match_operand:SI 3 "register_operand" "d"))] 10422 + "" 10423 + "sw\t%3, [%1, %2]+" 10424 + [(set_attr "type" "store") 10425 + (set_attr "length" "4") 10426 + (set_attr "mode" "SI")]) 10427 + 10428 +(define_insn "move_lcb" 10429 + [(set (match_operand:SI 0 "register_operand" "=d") 10430 + (plus:SI (match_operand:SI 1 "register_operand" "0") 10431 + (const_int 4))) 10432 + (set (reg:SI LC_REGNUM) 10433 + (unspec:SI [(mem:BLK (match_dup 1))] LCB))] 10434 + "((TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D) 10435 + && (!TARGET_LITTLE_ENDIAN) && (TARGET_ULS)) 10436 + || (TARGET_SCORE3 && TARGET_ULS)" 10437 + "lcb\t[%1]+" 10438 + [(set_attr "type" "load") 10439 + (set_attr "length" "4") 10440 + (set_attr "mode" "SI")]) 10441 + 10442 +(define_insn "move_lcw" 10443 + [(set (match_operand:SI 0 "register_operand" "=d") 10444 + (plus:SI (match_operand:SI 1 "register_operand" "0") 10445 + (const_int 4))) 10446 + (set (match_operand:SI 2 "register_operand" "=d") 10447 + (unspec:SI [(mem:BLK (match_dup 1)) 10448 + (reg:SI LC_REGNUM)] LCW)) 10449 + (set (reg:SI LC_REGNUM) 10450 + (unspec:SI [(mem:BLK (match_dup 1))] LCB))] 10451 + "((TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D) 10452 + && (!TARGET_LITTLE_ENDIAN) && (TARGET_ULS)) 10453 + || (TARGET_SCORE3 && TARGET_ULS)" 10454 + "lcw\t%2, [%1]+" 10455 + [(set_attr "type" "load") 10456 + (set_attr "length" "4") 10457 + (set_attr "mode" "SI")]) 10458 + 10459 +(define_insn "move_lce" 10460 + [(set (match_operand:SI 0 "register_operand" "=d") 10461 + (plus:SI (match_operand:SI 1 "register_operand" "0") 10462 + (const_int 4))) 10463 + (set (match_operand:SI 2 "register_operand" "=d") 10464 + (unspec:SI [(mem:BLK (match_dup 1)) 10465 + (reg:SI LC_REGNUM)] LCE))] 10466 + "((TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D) 10467 + && (!TARGET_LITTLE_ENDIAN) && (TARGET_ULS)) 10468 + || (TARGET_SCORE3 && TARGET_ULS)" 10469 + "lce\t%2, [%1]+" 10470 + [(set_attr "type" "load") 10471 + (set_attr "length" "4") 10472 + (set_attr "mode" "SI")]) 10473 + 10474 +(define_insn "move_scb" 10475 + [(set (match_operand:SI 0 "register_operand" "=d") 10476 + (plus:SI (match_operand:SI 1 "register_operand" "0") 10477 + (const_int 4))) 10478 + (set (mem:BLK (match_dup 1)) 10479 + (unspec:BLK [(match_operand:SI 2 "register_operand" "d")] SCB)) 10480 + (set (reg:SI SC_REGNUM) 10481 + (unspec:SI [(match_dup 2)] SCLC))] 10482 + "((TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D) 10483 + && (!TARGET_LITTLE_ENDIAN) && (TARGET_ULS)) 10484 + || (TARGET_SCORE3 && TARGET_ULS)" 10485 + "scb\t%2, [%1]+" 10486 + [(set_attr "type" "store") 10487 + (set_attr "length" "4") 10488 + (set_attr "mode" "SI")]) 10489 + 10490 +(define_insn "move_scw" 10491 + [(set (match_operand:SI 0 "register_operand" "=d") 10492 + (plus:SI (match_operand:SI 1 "register_operand" "0") 10493 + (const_int 4))) 10494 + (set (mem:BLK (match_dup 1)) 10495 + (unspec:BLK [(match_operand:SI 2 "register_operand" "d") 10496 + (reg:SI SC_REGNUM)] SCW)) 10497 + (set (reg:SI SC_REGNUM) 10498 + (unspec:SI [(match_dup 2)] SCLC))] 10499 + "((TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D) 10500 + && (!TARGET_LITTLE_ENDIAN) && (TARGET_ULS)) 10501 + || (TARGET_SCORE3 && TARGET_ULS)" 10502 + "scw\t%2, [%1]+" 10503 + [(set_attr "type" "store") 10504 + (set_attr "length" "4") 10505 + (set_attr "mode" "SI")]) 10506 + 10507 +(define_insn "move_sce" 10508 + [(set (match_operand:SI 0 "register_operand" "=d") 10509 + (plus:SI (match_operand:SI 1 "register_operand" "0") 10510 + (const_int 4))) 10511 + (set (mem:BLK (match_dup 1)) 10512 + (unspec:BLK [(reg:SI SC_REGNUM)] SCE))] 10513 + "((TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D) 10514 + && (!TARGET_LITTLE_ENDIAN) && (TARGET_ULS)) 10515 + || (TARGET_SCORE3 && TARGET_ULS)" 10516 + "sce [%1]+" 10517 + [(set_attr "type" "store") 10518 + (set_attr "length" "4") 10519 + (set_attr "mode" "SI")]) 10520 + 10521 +(define_insn "andsi3_extzh" 10522 + [(set (match_operand:SI 0 "register_operand" "=d") 10523 + (and:SI (match_operand:SI 1 "register_operand" "d") 10524 + (const_int 65535)))] 10525 + "" 10526 + "extzh\t%0, %1" 10527 + [(set_attr "type" "arith") 10528 + (set_attr "length" "4") 10529 + (set_attr "mode" "SI")]) 10530 + 10531 +(define_insn "clzsi2" 10532 + [(set (match_operand:SI 0 "register_operand" "=d") 10533 + (clz:SI (match_operand:SI 1 "register_operand" "d")))] 10534 + "(TARGET_SCORE7D || TARGET_SCORE3)" 10535 + "clz\t%0, %1" 10536 + [(set_attr "type" "arith") 10537 + (set_attr "mode" "SI")]) 10538 + 10539 +(define_insn "smaxsi3" 10540 + [(set (match_operand:SI 0 "register_operand" "=d") 10541 + (smax:SI (match_operand:SI 1 "register_operand" "d") 10542 + (match_operand:SI 2 "register_operand" "d")))] 10543 + "(TARGET_SCORE7D || TARGET_SCORE3D)" 10544 + "max\t%0, %1, %2" 10545 + [(set_attr "type" "arith") 10546 + (set_attr "mode" "SI")]) 10547 + 10548 +(define_insn "sminsi3" 10549 + [(set (match_operand:SI 0 "register_operand" "=d") 10550 + (smin:SI (match_operand:SI 1 "register_operand" "d") 10551 + (match_operand:SI 2 "register_operand" "d")))] 10552 + "(TARGET_SCORE7D || TARGET_SCORE3D)" 10553 + "min\t%0, %1, %2" 10554 + [(set_attr "type" "arith") 10555 + (set_attr "mode" "SI")]) 10556 + 10557 +(define_insn "abssi2" 10558 + [(set (match_operand:SI 0 "register_operand" "=d") 10559 + (abs:SI (match_operand:SI 1 "register_operand" "d")))] 10560 + "(TARGET_SCORE7D || TARGET_SCORE3D)" 10561 + "abs\t%0, %1" 10562 + [(set_attr "type" "arith") 10563 + (set_attr "mode" "SI")]) 10564 + 10565 +(define_insn "sffs" 10566 + [(set (match_operand:SI 0 "register_operand" "=d") 10567 + (unspec:SI [(match_operand:SI 1 "register_operand" "d")] SFFS))] 10568 + "(TARGET_SCORE7D || TARGET_SCORE3D)" 10569 + "bitrev\t%0, %1, r0\;clz\t%0, %0\;addi\t%0, 0x1" 10570 + [(set_attr "type" "arith") 10571 + (set_attr "mode" "SI")]) 10572 + 10573 +(define_expand "ffssi2" 10574 + [(set (match_operand:SI 0 "register_operand") 10575 + (ffs:SI (match_operand:SI 1 "register_operand")))] 10576 + "(TARGET_SCORE7D || TARGET_SCORE3D)" 10577 +{ 10578 + emit_insn (gen_sffs (operands[0], operands[1])); 10579 + emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_REG (CC_NZmode, CC_REGNUM), 10580 + gen_rtx_COMPARE (CC_NZmode, operands[0], 10581 + GEN_INT (33)))); 10582 + if (TARGET_SCORE7D) 10583 + emit_insn (gen_movsicc_internal_score7 (operands[0], 10584 + gen_rtx_fmt_ee (EQ, VOIDmode, operands[0], GEN_INT (33)), 10585 + GEN_INT (0), 10586 + operands[0])); 10587 + else 10588 + emit_insn (gen_movsicc_internal_score3 (operands[0], 10589 + gen_rtx_fmt_ee (EQ, VOIDmode, operands[0], GEN_INT (33)), 10590 + GEN_INT (0), 10591 + operands[0])); 10592 + DONE; 10593 +}) 10594 + 10595 +(define_peephole2 10596 + [(set (match_operand:SI 0 "loreg_operand" "") 10597 + (match_operand:SI 1 "register_operand" "")) 10598 + (set (match_operand:SI 2 "hireg_operand" "") 10599 + (match_operand:SI 3 "register_operand" ""))] 10600 + "(TARGET_SCORE7D || TARGET_SCORE3D)" 10601 + [(parallel 10602 + [(set (match_dup 0) (match_dup 1)) 10603 + (set (match_dup 2) (match_dup 3))])]) 10604 + 10605 +(define_peephole2 10606 + [(set (match_operand:SI 0 "hireg_operand" "") 10607 + (match_operand:SI 1 "register_operand" "")) 10608 + (set (match_operand:SI 2 "loreg_operand" "") 10609 + (match_operand:SI 3 "register_operand" ""))] 10610 + "(TARGET_SCORE7D || TARGET_SCORE3D)" 10611 + [(parallel 10612 + [(set (match_dup 2) (match_dup 3)) 10613 + (set (match_dup 0) (match_dup 1))])]) 10614 + 10615 +(define_insn "movtohilo" 10616 + [(parallel 10617 + [(set (match_operand:SI 0 "loreg_operand" "=l") 10618 + (match_operand:SI 1 "register_operand" "d")) 10619 + (set (match_operand:SI 2 "hireg_operand" "=h") 10620 + (match_operand:SI 3 "register_operand" "d"))])] 10621 + "(TARGET_SCORE7D || TARGET_SCORE3D)" 10622 + "mtcehl\t%3, %1" 10623 + [(set_attr "type" "fce") 10624 + (set_attr "mode" "SI")]) 10625 + 10626 +(define_insn "mulsi3addsi" 10627 + [(set (match_operand:SI 0 "register_operand" "=l,l,d") 10628 + (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "d,d,d") 10629 + (match_operand:SI 3 "register_operand" "d,d,d")) 10630 + (match_operand:SI 1 "register_operand" "0,d,l"))) 10631 + (clobber (reg:SI HI_REGNUM))] 10632 + "(TARGET_SCORE7D || TARGET_SCORE3D)" 10633 + "@ 10634 + mad\t%2, %3 10635 + mtcel%S1\t%1\;mad\t%2, %3 10636 + mad\t%2, %3\;mfcel%S0\t%0" 10637 + [(set_attr "mode" "SI")]) 10638 + 10639 +(define_insn "mulsi3subsi" 10640 + [(set (match_operand:SI 0 "register_operand" "=l,l,d") 10641 + (minus:SI (match_operand:SI 1 "register_operand" "0,d,l") 10642 + (mult:SI (match_operand:SI 2 "register_operand" "d,d,d") 10643 + (match_operand:SI 3 "register_operand" "d,d,d")))) 10644 + (clobber (reg:SI HI_REGNUM))] 10645 + "(TARGET_SCORE7D || TARGET_SCORE3D)" 10646 + "@ 10647 + msb\t%2, %3 10648 + mtcel%S1\t%1\;msb\t%2, %3 10649 + msb\t%2, %3\;mfcel%S0\t%0" 10650 + [(set_attr "mode" "SI")]) 10651 + 10652 +(define_insn "mulsidi3adddi" 10653 + [(set (match_operand:DI 0 "register_operand" "=x") 10654 + (plus:DI (mult:DI 10655 + (sign_extend:DI (match_operand:SI 2 "register_operand" "%d")) 10656 + (sign_extend:DI (match_operand:SI 3 "register_operand" "d"))) 10657 + (match_operand:DI 1 "register_operand" "0")))] 10658 + "(TARGET_SCORE7D || TARGET_SCORE3D)" 10659 + "mad\t%2, %3" 10660 + [(set_attr "mode" "DI")]) 10661 + 10662 +(define_insn "umulsidi3adddi" 10663 + [(set (match_operand:DI 0 "register_operand" "=x") 10664 + (plus:DI (mult:DI 10665 + (zero_extend:DI (match_operand:SI 2 "register_operand" "%d")) 10666 + (zero_extend:DI (match_operand:SI 3 "register_operand" "d"))) 10667 + (match_operand:DI 1 "register_operand" "0")))] 10668 + "(TARGET_SCORE7D || TARGET_SCORE3D)" 10669 + "madu\t%2, %3" 10670 + [(set_attr "mode" "DI")]) 10671 + 10672 +(define_insn "mulsidi3subdi" 10673 + [(set (match_operand:DI 0 "register_operand" "=x") 10674 + (minus:DI 10675 + (match_operand:DI 1 "register_operand" "0") 10676 + (mult:DI 10677 + (sign_extend:DI (match_operand:SI 2 "register_operand" "%d")) 10678 + (sign_extend:DI (match_operand:SI 3 "register_operand" "d")))))] 10679 + "(TARGET_SCORE7D || TARGET_SCORE3D)" 10680 + "msb\t%2, %3" 10681 + [(set_attr "mode" "DI")]) 10682 + 10683 +(define_insn "umulsidi3subdi" 10684 + [(set (match_operand:DI 0 "register_operand" "=x") 10685 + (minus:DI 10686 + (match_operand:DI 1 "register_operand" "0") 10687 + (mult:DI (zero_extend:DI 10688 + (match_operand:SI 2 "register_operand" "%d")) 10689 + (zero_extend:DI 10690 + (match_operand:SI 3 "register_operand" "d")))))] 10691 + "(TARGET_SCORE7D || TARGET_SCORE3D)" 10692 + "msbu\t%2, %3" 10693 + [(set_attr "mode" "DI")]) 10694 + 10695 diff -Naur gcc-4.2.2.orig/gcc/config/score/score.opt gcc-4.2.2/gcc/config/score/score.opt 10696 --- gcc-4.2.2.orig/gcc/config/score/score.opt 2007-09-01 11:28:30.000000000 -0400 10697 +++ gcc-4.2.2/gcc/config/score/score.opt 2007-10-18 02:24:34.000000000 -0400 10698 @@ -34,10 +34,6 @@ 10699 Target RejectNegative Report Mask(ULS) 10700 Enable unaligned load/store instruction 10701 10702 -mmac 10703 -Target RejectNegative Report Mask(MAC) 10704 -Enable mac instruction 10705 - 10706 mscore5 10707 Target RejectNegative Report Mask(SCORE5) 10708 Support SCORE 5 ISA 10709 @@ -53,3 +49,15 @@ 10710 mscore7d 10711 Target RejectNegative Report Mask(SCORE7D) 10712 Support SCORE 7D ISA 10713 + 10714 +mscore3 10715 +Target RejectNegative Report Mask(SCORE3) 10716 +Support SCORE 3 ISA 10717 + 10718 +mscore3d 10719 +Target RejectNegative Report Mask(SCORE3D) 10720 +Support SCORE 3d ISA 10721 + 10722 +march= 10723 +Target RejectNegative Joined 10724 +Specify the name of the target architecture 1912 10725 diff -Naur gcc-4.2.2.orig/gcc/config/score/score3.c gcc-4.2.2/gcc/config/score/score3.c 1913 --- gcc-4.2.2.orig/gcc/config/score/score3.c 1969-12-31 1 6:00:00.000000000 -08001914 +++ gcc-4.2.2/gcc/config/score/score3.c 2007-10-1 7 23:24:34.000000000 -070010726 --- gcc-4.2.2.orig/gcc/config/score/score3.c 1969-12-31 19:00:00.000000000 -0500 10727 +++ gcc-4.2.2/gcc/config/score/score3.c 2007-10-18 02:24:34.000000000 -0400 1915 10728 @@ -0,0 +1,1945 @@ 1916 10729 +/* score3.c for Sunplus S+CORE processor … … 3860 12673 +} 3861 12674 diff -Naur gcc-4.2.2.orig/gcc/config/score/score3.h gcc-4.2.2/gcc/config/score/score3.h 3862 --- gcc-4.2.2.orig/gcc/config/score/score3.h 1969-12-31 1 6:00:00.000000000 -08003863 +++ gcc-4.2.2/gcc/config/score/score3.h 2007-10-1 7 23:24:34.000000000 -070012675 --- gcc-4.2.2.orig/gcc/config/score/score3.h 1969-12-31 19:00:00.000000000 -0500 12676 +++ gcc-4.2.2/gcc/config/score/score3.h 2007-10-18 02:24:34.000000000 -0400 3864 12677 @@ -0,0 +1,159 @@ 3865 12678 +/* score3.h for Sunplus S+CORE processor … … 4023 12836 +#endif 4024 12837 diff -Naur gcc-4.2.2.orig/gcc/config/score/score7.c gcc-4.2.2/gcc/config/score/score7.c 4025 --- gcc-4.2.2.orig/gcc/config/score/score7.c 1969-12-31 1 6:00:00.000000000 -08004026 +++ gcc-4.2.2/gcc/config/score/score7.c 2007-10-1 7 23:24:34.000000000 -070012838 --- gcc-4.2.2.orig/gcc/config/score/score7.c 1969-12-31 19:00:00.000000000 -0500 12839 +++ gcc-4.2.2/gcc/config/score/score7.c 2007-10-18 02:24:34.000000000 -0400 4027 12840 @@ -0,0 +1,1849 @@ 4028 12841 +/* score7.c for Sunplus S+CORE processor … … 5876 14689 + 5877 14690 diff -Naur gcc-4.2.2.orig/gcc/config/score/score7.h gcc-4.2.2/gcc/config/score/score7.h 5878 --- gcc-4.2.2.orig/gcc/config/score/score7.h 1969-12-31 1 6:00:00.000000000 -08005879 +++ gcc-4.2.2/gcc/config/score/score7.h 2007-10-1 7 23:24:34.000000000 -070014691 --- gcc-4.2.2.orig/gcc/config/score/score7.h 1969-12-31 19:00:00.000000000 -0500 14692 +++ gcc-4.2.2/gcc/config/score/score7.h 2007-10-18 02:24:34.000000000 -0400 5880 14693 @@ -0,0 +1,157 @@ 5881 14694 +/* score7.h for Sunplus S+CORE processor … … 6037 14850 +#endif 6038 14851 diff -Naur gcc-4.2.2.orig/gcc/config/score/score7.md gcc-4.2.2/gcc/config/score/score7.md 6039 --- gcc-4.2.2.orig/gcc/config/score/score7.md 2007-09-01 08:28:30.000000000 -07006040 +++ gcc-4.2.2/gcc/config/score/score7.md 1969-12-31 1 6:00:00.000000000 -080014852 --- gcc-4.2.2.orig/gcc/config/score/score7.md 2007-09-01 11:28:30.000000000 -0400 14853 +++ gcc-4.2.2/gcc/config/score/score7.md 1969-12-31 19:00:00.000000000 -0500 6041 14854 @@ -1,45 +0,0 @@ 6042 14855 -;; Machine description for Sunplus S+CORE … … 6085 14898 - (eq_attr "up_c" "yes") 6086 14899 - "core") 6087 diff -Naur gcc-4.2.2.orig/gcc/config/score/score.c gcc-4.2.2/gcc/config/score/score.c6088 --- gcc-4.2.2.orig/gcc/config/score/score.c 2007-09-01 08:28:30.000000000 -07006089 +++ gcc-4.2.2/gcc/config/score/score.c 2007-10-17 23:24:34.000000000 -07006090 @@ -22,7 +22,6 @@6091 #include "system.h"6092 #include "coretypes.h"6093 #include "tm.h"6094 -#include <signal.h>6095 #include "rtl.h"6096 #include "regs.h"6097 #include "hard-reg-set.h"6098 @@ -48,57 +47,43 @@6099 #include "target-def.h"6100 #include "integrate.h"6101 #include "langhooks.h"6102 -#include "cfglayout.h"6103 -#include "score-mdaux.h"6104 -6105 -#define GR_REG_CLASS_P(C) ((C) == G16_REGS || (C) == G32_REGS)6106 -#define SP_REG_CLASS_P(C) \6107 - ((C) == CN_REG || (C) == LC_REG || (C) == SC_REG || (C) == SP_REGS)6108 -#define CP_REG_CLASS_P(C) \6109 - ((C) == CP1_REGS || (C) == CP2_REGS || (C) == CP3_REGS || (C) == CPA_REGS)6110 -#define CE_REG_CLASS_P(C) \6111 - ((C) == HI_REG || (C) == LO_REG || (C) == CE_REGS)6112 -6113 -static int score_arg_partial_bytes (const CUMULATIVE_ARGS *,6114 - enum machine_mode, tree, int);6115 -6116 -static int score_symbol_insns (enum score_symbol_type);6117 -6118 -static int score_address_insns (rtx, enum machine_mode);6119 -6120 -static bool score_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *);6121 -6122 -static int score_address_cost (rtx);6123 +#include "score7.h"6124 +#include "score3.h"6125 6126 #undef TARGET_ASM_FILE_START6127 -#define TARGET_ASM_FILE_START th_asm_file_start6128 +#define TARGET_ASM_FILE_START score_asm_file_start6129 6130 #undef TARGET_ASM_FILE_END6131 -#define TARGET_ASM_FILE_END th_asm_file_end6132 +#define TARGET_ASM_FILE_END score_asm_file_end6133 6134 #undef TARGET_ASM_FUNCTION_PROLOGUE6135 -#define TARGET_ASM_FUNCTION_PROLOGUE th_function_prologue6136 +#define TARGET_ASM_FUNCTION_PROLOGUE score_function_prologue6137 6138 #undef TARGET_ASM_FUNCTION_EPILOGUE6139 -#define TARGET_ASM_FUNCTION_EPILOGUE th_function_epilogue6140 +#define TARGET_ASM_FUNCTION_EPILOGUE score_function_epilogue6141 +6142 +#undef TARGET_DEFAULT_TARGET_FLAGS6143 +#define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT6144 +#undef TARGET_HANDLE_OPTION6145 +#define TARGET_HANDLE_OPTION score_handle_option6146 6147 #undef TARGET_SCHED_ISSUE_RATE6148 -#define TARGET_SCHED_ISSUE_RATE th_issue_rate6149 +#define TARGET_SCHED_ISSUE_RATE score_issue_rate6150 6151 #undef TARGET_ASM_SELECT_RTX_SECTION6152 -#define TARGET_ASM_SELECT_RTX_SECTION th_select_rtx_section6153 +#define TARGET_ASM_SELECT_RTX_SECTION score_select_rtx_section6154 6155 #undef TARGET_IN_SMALL_DATA_P6156 -#define TARGET_IN_SMALL_DATA_P th_in_small_data_p6157 +#define TARGET_IN_SMALL_DATA_P score_in_small_data_p6158 6159 #undef TARGET_FUNCTION_OK_FOR_SIBCALL6160 -#define TARGET_FUNCTION_OK_FOR_SIBCALL th_function_ok_for_sibcall6161 +#define TARGET_FUNCTION_OK_FOR_SIBCALL score_function_ok_for_sibcall6162 6163 #undef TARGET_STRICT_ARGUMENT_NAMING6164 -#define TARGET_STRICT_ARGUMENT_NAMING th_strict_argument_naming6165 +#define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true6166 6167 #undef TARGET_ASM_OUTPUT_MI_THUNK6168 -#define TARGET_ASM_OUTPUT_MI_THUNK th_output_mi_thunk6169 +#define TARGET_ASM_OUTPUT_MI_THUNK score_output_mi_thunk6170 6171 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK6172 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true6173 @@ -130,8 +115,11 @@6174 #undef TARGET_ADDRESS_COST6175 #define TARGET_ADDRESS_COST score_address_cost6176 6177 -#undef TARGET_DEFAULT_TARGET_FLAGS6178 -#define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT6179 +struct extern_list *extern_head = 0;6180 +rtx cmp_op0, cmp_op1;6181 +6182 +/* default 0 = NO_REGS */6183 +enum reg_class score_char_to_class[256];6184 6185 /* Implement TARGET_RETURN_IN_MEMORY. In S+core,6186 small structures are returned in a register.6187 @@ -139,9 +127,12 @@6188 static bool6189 score_return_in_memory (tree type, tree fndecl ATTRIBUTE_UNUSED)6190 {6191 - return ((TYPE_MODE (type) == BLKmode)6192 - || (int_size_in_bytes (type) > 2 * UNITS_PER_WORD)6193 - || (int_size_in_bytes (type) == -1));6194 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)6195 + return score7_return_in_memory (type, fndecl);6196 + else if (TARGET_SCORE3)6197 + return score3_return_in_memory (type, fndecl);6198 +6199 + gcc_unreachable ();6200 }6201 6202 /* Return nonzero when an argument must be passed by reference. */6203 @@ -154,308 +145,116 @@6204 return targetm.calls.must_pass_in_stack (mode, type);6205 }6206 6207 -/* Return a legitimate address for REG + OFFSET. */6208 -static rtx6209 -score_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)6210 -{6211 - if (!IMM_IN_RANGE (offset, 15, 1))6212 - {6213 - reg = expand_simple_binop (GET_MODE (reg), PLUS,6214 - gen_int_mode (offset & 0xffffc000,6215 - GET_MODE (reg)),6216 - reg, NULL, 0, OPTAB_WIDEN);6217 - offset &= 0x3fff;6218 - }6219 -6220 - return plus_constant (reg, offset);6221 -}6222 -6223 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text6224 in order to avoid duplicating too much logic from elsewhere. */6225 static void6226 -th_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,6227 - HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,6228 - tree function)6229 -{6230 - rtx this, temp1, temp2, insn, fnaddr;6231 -6232 - /* Pretend to be a post-reload pass while generating rtl. */6233 - no_new_pseudos = 1;6234 - reload_completed = 1;6235 - reset_block_changes ();6236 -6237 - /* We need two temporary registers in some cases. */6238 - temp1 = gen_rtx_REG (Pmode, 8);6239 - temp2 = gen_rtx_REG (Pmode, 9);6240 -6241 - /* Find out which register contains the "this" pointer. */6242 - if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))6243 - this = gen_rtx_REG (Pmode, ARG_REG_FIRST + 1);6244 - else6245 - this = gen_rtx_REG (Pmode, ARG_REG_FIRST);6246 -6247 - /* Add DELTA to THIS. */6248 - if (delta != 0)6249 - {6250 - rtx offset = GEN_INT (delta);6251 - if (!CONST_OK_FOR_LETTER_P (delta, 'L'))6252 - {6253 - emit_move_insn (temp1, offset);6254 - offset = temp1;6255 - }6256 - emit_insn (gen_add3_insn (this, this, offset));6257 - }6258 -6259 - /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */6260 - if (vcall_offset != 0)6261 - {6262 - rtx addr;6263 -6264 - /* Set TEMP1 to *THIS. */6265 - emit_move_insn (temp1, gen_rtx_MEM (Pmode, this));6266 -6267 - /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */6268 - addr = score_add_offset (temp2, temp1, vcall_offset);6269 -6270 - /* Load the offset and add it to THIS. */6271 - emit_move_insn (temp1, gen_rtx_MEM (Pmode, addr));6272 - emit_insn (gen_add3_insn (this, this, temp1));6273 - }6274 -6275 - /* Jump to the target function. */6276 - fnaddr = XEXP (DECL_RTL (function), 0);6277 - insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));6278 - SIBLING_CALL_P (insn) = 1;6279 -6280 - /* Run just enough of rest_of_compilation. This sequence was6281 - "borrowed" from alpha.c. */6282 - insn = get_insns ();6283 - insn_locators_initialize ();6284 - split_all_insns_noflow ();6285 - shorten_branches (insn);6286 - final_start_function (insn, file, 1);6287 - final (insn, file, 1);6288 - final_end_function ();6289 -6290 - /* Clean up the vars set above. Note that final_end_function resets6291 - the global pointer for us. */6292 - reload_completed = 0;6293 - no_new_pseudos = 0;6294 -}6295 -6296 -/* Implement TARGET_STRICT_ARGUMENT_NAMING. */6297 -static bool6298 -th_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)6299 -{6300 - return true;6301 +score_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,6302 + HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,6303 + tree function)6304 +{6305 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)6306 + return score7_output_mi_thunk (file, thunk_fndecl, delta,6307 + vcall_offset, function);6308 + else if (TARGET_SCORE3)6309 + return score3_output_mi_thunk (file, thunk_fndecl, delta,6310 + vcall_offset, function);6311 + gcc_unreachable ();6312 }6313 6314 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */6315 static bool6316 -th_function_ok_for_sibcall (ATTRIBUTE_UNUSED tree decl,6317 - ATTRIBUTE_UNUSED tree exp)6318 +score_function_ok_for_sibcall (ATTRIBUTE_UNUSED tree decl,6319 + ATTRIBUTE_UNUSED tree exp)6320 {6321 return true;6322 }6323 6324 -struct score_arg_info6325 -{6326 - /* The argument's size, in bytes. */6327 - unsigned int num_bytes;6328 -6329 - /* The number of words passed in registers, rounded up. */6330 - unsigned int reg_words;6331 -6332 - /* The offset of the first register from GP_ARG_FIRST or FP_ARG_FIRST,6333 - or ARG_REG_NUM if the argument is passed entirely on the stack. */6334 - unsigned int reg_offset;6335 -6336 - /* The number of words that must be passed on the stack, rounded up. */6337 - unsigned int stack_words;6338 -6339 - /* The offset from the start of the stack overflow area of the argument's6340 - first stack word. Only meaningful when STACK_WORDS is nonzero. */6341 - unsigned int stack_offset;6342 -};6343 -6344 -/* Fill INFO with information about a single argument. CUM is the6345 - cumulative state for earlier arguments. MODE is the mode of this6346 - argument and TYPE is its type (if known). NAMED is true if this6347 - is a named (fixed) argument rather than a variable one. */6348 -static void6349 -classify_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,6350 - tree type, int named, struct score_arg_info *info)6351 -{6352 - int even_reg_p;6353 - unsigned int num_words, max_regs;6354 -6355 - even_reg_p = 0;6356 - if (GET_MODE_CLASS (mode) == MODE_INT6357 - || GET_MODE_CLASS (mode) == MODE_FLOAT)6358 - even_reg_p = (GET_MODE_SIZE (mode) > UNITS_PER_WORD);6359 - else6360 - if (type != NULL_TREE && TYPE_ALIGN (type) > BITS_PER_WORD && named)6361 - even_reg_p = 1;6362 -6363 - if (TARGET_MUST_PASS_IN_STACK (mode, type))6364 - info->reg_offset = ARG_REG_NUM;6365 - else6366 - {6367 - info->reg_offset = cum->num_gprs;6368 - if (even_reg_p)6369 - info->reg_offset += info->reg_offset & 1;6370 - }6371 -6372 - if (mode == BLKmode)6373 - info->num_bytes = int_size_in_bytes (type);6374 - else6375 - info->num_bytes = GET_MODE_SIZE (mode);6376 -6377 - num_words = (info->num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;6378 - max_regs = ARG_REG_NUM - info->reg_offset;6379 -6380 - /* Partition the argument between registers and stack. */6381 - info->reg_words = MIN (num_words, max_regs);6382 - info->stack_words = num_words - info->reg_words;6383 -6384 - /* The alignment applied to registers is also applied to stack arguments. */6385 - if (info->stack_words)6386 - {6387 - info->stack_offset = cum->stack_words;6388 - if (even_reg_p)6389 - info->stack_offset += info->stack_offset & 1;6390 - }6391 -}6392 -6393 /* Set up the stack and frame (if desired) for the function. */6394 static void6395 -th_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)6396 +score_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)6397 {6398 - const char *fnname;6399 - struct score_frame_info *f = mda_cached_frame ();6400 - HOST_WIDE_INT tsize = f->total_size;6401 -6402 - fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);6403 - if (!flag_inhibit_size_directive)6404 - {6405 - fputs ("\t.ent\t", file);6406 - assemble_name (file, fnname);6407 - fputs ("\n", file);6408 - }6409 - assemble_name (file, fnname);6410 - fputs (":\n", file);6411 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)6412 + return score7_function_prologue (file, size);6413 + else if (TARGET_SCORE3)6414 + return score3_function_prologue (file, size);6415 6416 - if (!flag_inhibit_size_directive)6417 - {6418 - fprintf (file,6419 - "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s, %d\t\t"6420 - "# vars= " HOST_WIDE_INT_PRINT_DEC ", regs= %d"6421 - ", args= " HOST_WIDE_INT_PRINT_DEC6422 - ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",6423 - (reg_names[(frame_pointer_needed)6424 - ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]),6425 - tsize,6426 - reg_names[RA_REGNUM],6427 - current_function_is_leaf ? 1 : 0,6428 - f->var_size,6429 - f->num_gp,6430 - f->args_size,6431 - f->cprestore_size);6432 -6433 - fprintf(file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",6434 - f->mask,6435 - (f->gp_sp_offset - f->total_size));6436 - }6437 + gcc_unreachable ();6438 }6439 6440 /* Do any necessary cleanup after a function to restore stack, frame,6441 and regs. */6442 static void6443 -th_function_epilogue (FILE *file,6444 - HOST_WIDE_INT size ATTRIBUTE_UNUSED)6445 +score_function_epilogue (FILE *file,6446 + HOST_WIDE_INT size ATTRIBUTE_UNUSED)6447 {6448 - if (!flag_inhibit_size_directive)6449 - {6450 - const char *fnname;6451 - fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);6452 - fputs ("\t.end\t", file);6453 - assemble_name (file, fnname);6454 - fputs ("\n", file);6455 - }6456 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)6457 + return score7_function_epilogue (file, size);6458 + else if (TARGET_SCORE3)6459 + return score3_function_epilogue (file, size);6460 +6461 + gcc_unreachable ();6462 }6463 6464 /* Implement TARGET_SCHED_ISSUE_RATE. */6465 static int6466 -th_issue_rate (void)6467 +score_issue_rate (void)6468 {6469 return 1;6470 }6471 6472 -/* Returns true if X contains a SYMBOL_REF. */6473 -static bool6474 -symbolic_expression_p (rtx x)6475 -{6476 - if (GET_CODE (x) == SYMBOL_REF)6477 - return true;6478 -6479 - if (GET_CODE (x) == CONST)6480 - return symbolic_expression_p (XEXP (x, 0));6481 -6482 - if (UNARY_P (x))6483 - return symbolic_expression_p (XEXP (x, 0));6484 -6485 - if (ARITHMETIC_P (x))6486 - return (symbolic_expression_p (XEXP (x, 0))6487 - || symbolic_expression_p (XEXP (x, 1)));6488 -6489 - return false;6490 -}6491 -6492 /* Choose the section to use for the constant rtx expression X that has6493 mode MODE. */6494 static section *6495 -th_select_rtx_section (enum machine_mode mode, rtx x,6496 - unsigned HOST_WIDE_INT align)6497 +score_select_rtx_section (enum machine_mode mode, rtx x,6498 + unsigned HOST_WIDE_INT align)6499 {6500 - if (GET_MODE_SIZE (mode) <= SCORE_SDATA_MAX)6501 - return get_named_section (0, ".sdata", 0);6502 - else if (flag_pic && symbolic_expression_p (x))6503 - return get_named_section (0, ".data.rel.ro", 3);6504 - else6505 - return mergeable_constant_section (mode, align, 0);6506 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)6507 + return score7_select_rtx_section (mode, x, align);6508 + else if (TARGET_SCORE3)6509 + return score3_select_rtx_section (mode, x, align);6510 +6511 + gcc_unreachable ();6512 }6513 6514 /* Implement TARGET_IN_SMALL_DATA_P. */6515 static bool6516 -th_in_small_data_p (tree decl)6517 +score_in_small_data_p (tree decl)6518 {6519 - HOST_WIDE_INT size;6520 -6521 - if (TREE_CODE (decl) == STRING_CST6522 - || TREE_CODE (decl) == FUNCTION_DECL)6523 - return false;6524 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)6525 + return score7_in_small_data_p (decl);6526 + else if (TARGET_SCORE3)6527 + return score3_in_small_data_p (decl);6528 6529 - if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)6530 - {6531 - const char *name;6532 - name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));6533 - if (strcmp (name, ".sdata") != 06534 - && strcmp (name, ".sbss") != 0)6535 - return true;6536 - if (!DECL_EXTERNAL (decl))6537 - return false;6538 - }6539 - size = int_size_in_bytes (TREE_TYPE (decl));6540 - return (size > 0 && size <= SCORE_SDATA_MAX);6541 + gcc_unreachable ();6542 }6543 6544 /* Implement TARGET_ASM_FILE_START. */6545 static void6546 -th_asm_file_start (void)6547 +score_asm_file_start (void)6548 {6549 + if (TARGET_SCORE5)6550 + fprintf (asm_out_file, "# Sunplus S+core5 %s rev=%s\n",6551 + TARGET_LITTLE_ENDIAN ? "el" : "eb", SCORE_GCC_VERSION);6552 + else if (TARGET_SCORE5U)6553 + fprintf (asm_out_file, "# Sunplus S+core5u %s rev=%s\n",6554 + TARGET_LITTLE_ENDIAN ? "el" : "eb", SCORE_GCC_VERSION);6555 + else if (TARGET_SCORE7D)6556 + fprintf (asm_out_file, "# Sunplus S+core7d %s rev=%s\n",6557 + TARGET_LITTLE_ENDIAN ? "el" : "eb", SCORE_GCC_VERSION);6558 + else if (TARGET_SCORE7)6559 + fprintf (asm_out_file, "# Sunplus S+core7 %s rev=%s\n",6560 + TARGET_LITTLE_ENDIAN ? "el" : "eb", SCORE_GCC_VERSION);6561 + else if (TARGET_SCORE3D)6562 + fprintf (asm_out_file, "# Sunplus S+core3d %s rev=%s\n",6563 + TARGET_LITTLE_ENDIAN ? "el" : "eb", SCORE_GCC_VERSION);6564 + else if (TARGET_SCORE3)6565 + fprintf (asm_out_file, "# Sunplus S+core3 %s rev=%s\n",6566 + TARGET_LITTLE_ENDIAN ? "el" : "eb", SCORE_GCC_VERSION);6567 + else6568 + fprintf (asm_out_file, "# Sunplus S+core unknown %s rev=%s\n",6569 + TARGET_LITTLE_ENDIAN ? "el" : "eb", SCORE_GCC_VERSION);6570 +6571 default_file_start ();6572 - fprintf (asm_out_file, ASM_COMMENT_START6573 - "GCC for S+core %s \n", SCORE_GCC_VERSION);6574 6575 if (flag_pic)6576 fprintf (asm_out_file, "\t.set pic\n");6577 @@ -463,104 +262,116 @@6578 6579 /* Implement TARGET_ASM_FILE_END. When using assembler macros, emit6580 .externs for any small-data variables that turned out to be external. */6581 -struct extern_list *extern_head = 0;6582 -6583 static void6584 -th_asm_file_end (void)6585 +score_asm_file_end (void)6586 {6587 - tree name_tree;6588 - struct extern_list *p;6589 - if (extern_head)6590 - {6591 - fputs ("\n", asm_out_file);6592 - for (p = extern_head; p != 0; p = p->next)6593 - {6594 - name_tree = get_identifier (p->name);6595 - if (!TREE_ASM_WRITTEN (name_tree)6596 - && TREE_SYMBOL_REFERENCED (name_tree))6597 - {6598 - TREE_ASM_WRITTEN (name_tree) = 1;6599 - fputs ("\t.extern\t", asm_out_file);6600 - assemble_name (asm_out_file, p->name);6601 - fprintf (asm_out_file, ", %d\n", p->size);6602 - }6603 - }6604 - }6605 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)6606 + return score7_asm_file_end ();6607 + else if (TARGET_SCORE3)6608 + return score3_asm_file_end ();6609 +6610 + gcc_unreachable ();6611 }6612 6613 -static unsigned int sdata_max;6614 +#define MASK_ALL_CPU_BITS \6615 + (MASK_SCORE5 | MASK_SCORE5U | MASK_SCORE7 | MASK_SCORE7D \6616 + | MASK_SCORE3 | MASK_SCORE3D)6617 6618 -int6619 -score_sdata_max (void)6620 +/* Implement TARGET_HANDLE_OPTION. */6621 +static bool6622 +score_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)6623 {6624 - return sdata_max;6625 -}6626 + switch (code)6627 + {6628 + case OPT_mscore7d:6629 + target_flags &= ~(MASK_ALL_CPU_BITS);6630 + target_flags |= MASK_SCORE7 | MASK_SCORE7D;6631 + return true;6632 6633 -/* default 0 = NO_REGS */6634 -enum reg_class score_char_to_class[256];6635 + case OPT_mscore3d:6636 + target_flags &= ~(MASK_ALL_CPU_BITS);6637 + target_flags |= MASK_SCORE3 | MASK_SCORE3D;6638 + return true;6639 +6640 + case OPT_march_:6641 + if (strcmp (arg, "score5") == 0)6642 + {6643 + target_flags &= ~(MASK_ALL_CPU_BITS);6644 + target_flags |= MASK_SCORE5;6645 + return true;6646 + }6647 + else if (strcmp (arg, "score5u") == 0)6648 + {6649 + target_flags &= ~(MASK_ALL_CPU_BITS);6650 + target_flags |= MASK_SCORE5U;6651 + return true;6652 + }6653 + else if (strcmp (arg, "score7") == 0)6654 + {6655 + target_flags &= ~(MASK_ALL_CPU_BITS);6656 + target_flags |= MASK_SCORE7;6657 + return true;6658 + }6659 + else if (strcmp (arg, "score7d") == 0)6660 + {6661 + target_flags &= ~(MASK_ALL_CPU_BITS);6662 + target_flags |= MASK_SCORE7 | MASK_SCORE7D;6663 + return true;6664 + }6665 + else if (strcmp (arg, "score3") == 0)6666 + {6667 + target_flags &= ~(MASK_ALL_CPU_BITS);6668 + target_flags |= MASK_SCORE3;6669 + return true;6670 + }6671 + else if (strcmp (arg, "score3d") == 0)6672 + {6673 + target_flags &= ~(MASK_ALL_CPU_BITS);6674 + target_flags |= MASK_SCORE3 | MASK_SCORE3D;6675 + return true;6676 + }6677 + else6678 + return false;6679 +6680 + default:6681 + return true;6682 + }6683 +}6684 6685 /* Implement OVERRIDE_OPTIONS macro. */6686 void6687 score_override_options (void)6688 {6689 - flag_pic = false;6690 - if (!flag_pic)6691 - sdata_max = g_switch_set ? g_switch_value : DEFAULT_SDATA_MAX;6692 - else6693 - {6694 - sdata_max = 0;6695 - if (g_switch_set && (g_switch_value != 0))6696 - warning (0, "-fPIC and -G are incompatible");6697 - }6698 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)6699 + return score7_override_options ();6700 + else if (TARGET_SCORE3)6701 + return score3_override_options ();6702 6703 - score_char_to_class['d'] = G32_REGS;6704 - score_char_to_class['e'] = G16_REGS;6705 - score_char_to_class['t'] = T32_REGS;6706 -6707 - score_char_to_class['h'] = HI_REG;6708 - score_char_to_class['l'] = LO_REG;6709 - score_char_to_class['x'] = CE_REGS;6710 -6711 - score_char_to_class['q'] = CN_REG;6712 - score_char_to_class['y'] = LC_REG;6713 - score_char_to_class['z'] = SC_REG;6714 - score_char_to_class['a'] = SP_REGS;6715 -6716 - score_char_to_class['c'] = CR_REGS;6717 -6718 - score_char_to_class['b'] = CP1_REGS;6719 - score_char_to_class['f'] = CP2_REGS;6720 - score_char_to_class['i'] = CP3_REGS;6721 - score_char_to_class['j'] = CPA_REGS;6722 + return score7_override_options ();6723 }6724 6725 /* Implement REGNO_REG_CLASS macro. */6726 int6727 score_reg_class (int regno)6728 {6729 - int c;6730 - gcc_assert (regno >= 0 && regno < FIRST_PSEUDO_REGISTER);6731 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)6732 + return score7_reg_class (regno);6733 + else if (TARGET_SCORE3)6734 + return score3_reg_class (regno);6735 6736 - if (regno == FRAME_POINTER_REGNUM6737 - || regno == ARG_POINTER_REGNUM)6738 - return ALL_REGS;6739 -6740 - for (c = 0; c < N_REG_CLASSES; c++)6741 - if (TEST_HARD_REG_BIT (reg_class_contents[c], regno))6742 - return c;6743 -6744 - return NO_REGS;6745 + gcc_unreachable ();6746 }6747 6748 /* Implement PREFERRED_RELOAD_CLASS macro. */6749 enum reg_class6750 score_preferred_reload_class (rtx x ATTRIBUTE_UNUSED, enum reg_class class)6751 {6752 - if (reg_class_subset_p (G16_REGS, class))6753 - return G16_REGS;6754 - if (reg_class_subset_p (G32_REGS, class))6755 - return G32_REGS;6756 - return class;6757 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)6758 + return score7_preferred_reload_class (x, class);6759 + else if (TARGET_SCORE3)6760 + return score3_preferred_reload_class (x, class);6761 +6762 + gcc_unreachable ();6763 }6764 6765 /* Implement SECONDARY_INPUT_RELOAD_CLASS6766 @@ -570,50 +381,36 @@6767 enum machine_mode mode ATTRIBUTE_UNUSED,6768 rtx x)6769 {6770 - int regno = -1;6771 - if (GET_CODE (x) == REG || GET_CODE(x) == SUBREG)6772 - regno = true_regnum (x);6773 -6774 - if (!GR_REG_CLASS_P (class))6775 - return GP_REG_P (regno) ? NO_REGS : G32_REGS;6776 - return NO_REGS;6777 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)6778 + return score7_secondary_reload_class (class, mode, x);6779 + else if (TARGET_SCORE3)6780 + return score3_secondary_reload_class (class, mode, x);6781 +6782 + gcc_unreachable ();6783 }6784 6785 /* Implement CONST_OK_FOR_LETTER_P macro. */6786 -/* imm constraints6787 - I imm16 << 166788 - J uimm56789 - K uimm166790 - L simm166791 - M uimm146792 - N simm14 */6793 int6794 score_const_ok_for_letter_p (HOST_WIDE_INT value, char c)6795 {6796 - switch (c)6797 - {6798 - case 'I': return ((value & 0xffff) == 0);6799 - case 'J': return IMM_IN_RANGE (value, 5, 0);6800 - case 'K': return IMM_IN_RANGE (value, 16, 0);6801 - case 'L': return IMM_IN_RANGE (value, 16, 1);6802 - case 'M': return IMM_IN_RANGE (value, 14, 0);6803 - case 'N': return IMM_IN_RANGE (value, 14, 1);6804 - default : return 0;6805 - }6806 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)6807 + return score7_const_ok_for_letter_p (value, c);6808 + else if (TARGET_SCORE3)6809 + return score3_const_ok_for_letter_p (value, c);6810 +6811 + gcc_unreachable ();6812 }6813 6814 /* Implement EXTRA_CONSTRAINT macro. */6815 -/* Z symbol_ref */6816 int6817 score_extra_constraint (rtx op, char c)6818 {6819 - switch (c)6820 - {6821 - case 'Z':6822 - return GET_CODE (op) == SYMBOL_REF;6823 - default:6824 - gcc_unreachable ();6825 - }6826 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)6827 + return score7_extra_constraint (op, c);6828 + else if (TARGET_SCORE3)6829 + return score3_extra_constraint (op, c);6830 +6831 + gcc_unreachable ();6832 }6833 6834 /* Return truth value on whether or not a given hard register6835 @@ -621,23 +418,12 @@6836 int6837 score_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)6838 {6839 - int size = GET_MODE_SIZE (mode);6840 - enum mode_class class = GET_MODE_CLASS (mode);6841 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)6842 + return score7_hard_regno_mode_ok (regno, mode);6843 + else if (TARGET_SCORE3)6844 + return score3_hard_regno_mode_ok (regno, mode);6845 6846 - if (class == MODE_CC)6847 - return regno == CC_REGNUM;6848 - else if (regno == FRAME_POINTER_REGNUM6849 - || regno == ARG_POINTER_REGNUM)6850 - return class == MODE_INT;6851 - else if (GP_REG_P (regno))6852 - /* ((regno <= (GP_REG_LAST- HARD_REGNO_NREGS (dummy, mode)) + 1) */6853 - return !(regno & 1) || (size <= UNITS_PER_WORD);6854 - else if (CE_REG_P (regno))6855 - return (class == MODE_INT6856 - && ((size <= UNITS_PER_WORD)6857 - || (regno == CE_REG_FIRST && size == 2 * UNITS_PER_WORD)));6858 - else6859 - return (class == MODE_INT) && (size <= UNITS_PER_WORD);6860 + gcc_unreachable ();6861 }6862 6863 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame6864 @@ -647,16 +433,12 @@6865 score_initial_elimination_offset (int from,6866 int to ATTRIBUTE_UNUSED)6867 {6868 - struct score_frame_info *f = mda_compute_frame_size (get_frame_size ());6869 - switch (from)6870 - {6871 - case ARG_POINTER_REGNUM:6872 - return f->total_size;6873 - case FRAME_POINTER_REGNUM:6874 - return 0;6875 - default:6876 - gcc_unreachable ();6877 - }6878 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)6879 + return score7_initial_elimination_offset (from, to);6880 + else if (TARGET_SCORE3)6881 + return score3_initial_elimination_offset (from, to);6882 +6883 + gcc_unreachable ();6884 }6885 6886 /* Argument support functions. */6887 @@ -675,22 +457,25 @@6888 score_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,6889 tree type, int named)6890 {6891 - struct score_arg_info info;6892 - classify_arg (cum, mode, type, named, &info);6893 - cum->num_gprs = info.reg_offset + info.reg_words;6894 - if (info.stack_words > 0)6895 - cum->stack_words = info.stack_offset + info.stack_words;6896 - cum->arg_number++;6897 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)6898 + return score7_function_arg_advance (cum, mode, type, named);6899 + else if (TARGET_SCORE3)6900 + return score3_function_arg_advance (cum, mode, type, named);6901 +6902 + gcc_unreachable ();6903 }6904 6905 /* Implement TARGET_ARG_PARTIAL_BYTES macro. */6906 -static int6907 -score_arg_partial_bytes (const CUMULATIVE_ARGS *cum,6908 - enum machine_mode mode, tree type, int named)6909 +int6910 +score_arg_partial_bytes (CUMULATIVE_ARGS *cum,6911 + enum machine_mode mode, tree type, bool named)6912 {6913 - struct score_arg_info info;6914 - classify_arg (cum, mode, type, named, &info);6915 - return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;6916 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)6917 + return score7_arg_partial_bytes (cum, mode, type, named);6918 + else if (TARGET_SCORE3)6919 + return score3_arg_partial_bytes (cum, mode, type, named);6920 +6921 + gcc_unreachable ();6922 }6923 6924 /* Implement FUNCTION_ARG macro. */6925 @@ -698,32 +483,12 @@6926 score_function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,6927 tree type, int named)6928 {6929 - struct score_arg_info info;6930 -6931 - if (mode == VOIDmode || !named)6932 - return 0;6933 -6934 - classify_arg (cum, mode, type, named, &info);6935 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)6936 + return score7_function_arg (cum, mode, type, named);6937 + else if (TARGET_SCORE3)6938 + return score3_function_arg (cum, mode, type, named);6939 6940 - if (info.reg_offset == ARG_REG_NUM)6941 - return 0;6942 -6943 - if (!info.stack_words)6944 - return gen_rtx_REG (mode, ARG_REG_FIRST + info.reg_offset);6945 - else6946 - {6947 - rtx ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));6948 - unsigned int i, part_offset = 0;6949 - for (i = 0; i < info.reg_words; i++)6950 - {6951 - rtx reg;6952 - reg = gen_rtx_REG (SImode, ARG_REG_FIRST + info.reg_offset + i);6953 - XVECEXP (ret, 0, i) = gen_rtx_EXPR_LIST (SImode, reg,6954 - GEN_INT (part_offset));6955 - part_offset += UNITS_PER_WORD;6956 - }6957 - return ret;6958 - }6959 + gcc_unreachable ();6960 }6961 6962 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,6963 @@ -733,85 +498,48 @@6964 score_function_value (tree valtype, tree func ATTRIBUTE_UNUSED,6965 enum machine_mode mode)6966 {6967 - if (valtype)6968 - {6969 - int unsignedp;6970 - mode = TYPE_MODE (valtype);6971 - unsignedp = TYPE_UNSIGNED (valtype);6972 - mode = promote_mode (valtype, mode, &unsignedp, 1);6973 - }6974 - return gen_rtx_REG (mode, RT_REGNUM);6975 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)6976 + return score7_function_value (valtype, func, mode);6977 + else if (TARGET_SCORE3)6978 + return score3_function_value (valtype, func, mode);6979 +6980 + gcc_unreachable ();6981 }6982 6983 /* Implement INITIALIZE_TRAMPOLINE macro. */6984 void6985 score_initialize_trampoline (rtx ADDR, rtx FUNC, rtx CHAIN)6986 {6987 -#define FFCACHE "_flush_cache"6988 -#define CODE_SIZE (TRAMPOLINE_INSNS * UNITS_PER_WORD)6989 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)6990 + return score7_initialize_trampoline (ADDR, FUNC, CHAIN);6991 + else if (TARGET_SCORE3)6992 + return score3_initialize_trampoline (ADDR, FUNC, CHAIN);6993 6994 - rtx pfunc, pchain;6995 -6996 - pfunc = plus_constant (ADDR, CODE_SIZE);6997 - pchain = plus_constant (ADDR, CODE_SIZE + GET_MODE_SIZE (SImode));6998 -6999 - emit_move_insn (gen_rtx_MEM (SImode, pfunc), FUNC);7000 - emit_move_insn (gen_rtx_MEM (SImode, pchain), CHAIN);7001 - emit_library_call (gen_rtx_SYMBOL_REF (Pmode, FFCACHE),7002 - 0, VOIDmode, 2,7003 - ADDR, Pmode,7004 - GEN_INT (TRAMPOLINE_SIZE), SImode);7005 -#undef FFCACHE7006 -#undef CODE_SIZE7007 + gcc_unreachable ();7008 }7009 7010 /* This function is used to implement REG_MODE_OK_FOR_BASE_P macro. */7011 int7012 score_regno_mode_ok_for_base_p (int regno, int strict)7013 {7014 - if (regno >= FIRST_PSEUDO_REGISTER)7015 - {7016 - if (!strict)7017 - return 1;7018 - regno = reg_renumber[regno];7019 - }7020 - if (regno == ARG_POINTER_REGNUM7021 - || regno == FRAME_POINTER_REGNUM)7022 - return 1;7023 - return GP_REG_P (regno);7024 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)7025 + return score7_regno_mode_ok_for_base_p (regno, strict);7026 + else if (TARGET_SCORE3)7027 + return score3_regno_mode_ok_for_base_p (regno, strict);7028 +7029 + gcc_unreachable ();7030 }7031 7032 /* Implement GO_IF_LEGITIMATE_ADDRESS macro. */7033 int7034 score_address_p (enum machine_mode mode, rtx x, int strict)7035 {7036 - struct score_address_info addr;7037 -7038 - return mda_classify_address (&addr, mode, x, strict);7039 -}7040 -7041 -/* Copy VALUE to a register and return that register. If new psuedos7042 - are allowed, copy it into a new register, otherwise use DEST. */7043 -static rtx7044 -score_force_temporary (rtx dest, rtx value)7045 -{7046 - if (!no_new_pseudos)7047 - return force_reg (Pmode, value);7048 - else7049 - {7050 - emit_move_insn (copy_rtx (dest), value);7051 - return dest;7052 - }7053 -}7054 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)7055 + return score7_address_p (mode, x, strict);7056 + else if (TARGET_SCORE3)7057 + return score3_address_p (mode, x, strict);7058 7059 -/* Return a LO_SUM expression for ADDR. TEMP is as for score_force_temporary7060 - and is used to load the high part into a register. */7061 -static rtx7062 -score_split_symbol (rtx temp, rtx addr)7063 -{7064 - rtx high = score_force_temporary (temp,7065 - gen_rtx_HIGH (Pmode, copy_rtx (addr)));7066 - return gen_rtx_LO_SUM (Pmode, high, addr);7067 + gcc_unreachable ();7068 }7069 7070 /* This function is used to implement LEGITIMIZE_ADDRESS. If *XLOC can7071 @@ -820,25 +548,12 @@7072 int7073 score_legitimize_address (rtx *xloc)7074 {7075 - enum score_symbol_type symbol_type;7076 -7077 - if (mda_symbolic_constant_p (*xloc, &symbol_type)7078 - && symbol_type == SYMBOL_GENERAL)7079 - {7080 - *xloc = score_split_symbol (0, *xloc);7081 - return 1;7082 - }7083 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)7084 + return score7_legitimize_address (xloc);7085 + else if (TARGET_SCORE3)7086 + return score3_legitimize_address (xloc);7087 7088 - if (GET_CODE (*xloc) == PLUS7089 - && GET_CODE (XEXP (*xloc, 1)) == CONST_INT)7090 - {7091 - rtx reg = XEXP (*xloc, 0);7092 - if (!mda_valid_base_register_p (reg, 0))7093 - reg = copy_to_mode_reg (Pmode, reg);7094 - *xloc = score_add_offset (NULL, reg, INTVAL (XEXP (*xloc, 1)));7095 - return 1;7096 - }7097 - return 0;7098 + gcc_unreachable ();7099 }7100 7101 /* Return a number assessing the cost of moving a register in class7102 @@ -847,503 +562,633 @@7103 score_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,7104 enum reg_class from, enum reg_class to)7105 {7106 - if (GR_REG_CLASS_P (from))7107 - {7108 - if (GR_REG_CLASS_P (to))7109 - return 2;7110 - else if (SP_REG_CLASS_P (to))7111 - return 4;7112 - else if (CP_REG_CLASS_P (to))7113 - return 5;7114 - else if (CE_REG_CLASS_P (to))7115 - return 6;7116 - }7117 - if (GR_REG_CLASS_P (to))7118 - {7119 - if (GR_REG_CLASS_P (from))7120 - return 2;7121 - else if (SP_REG_CLASS_P (from))7122 - return 4;7123 - else if (CP_REG_CLASS_P (from))7124 - return 5;7125 - else if (CE_REG_CLASS_P (from))7126 - return 6;7127 - }7128 - return 12;7129 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)7130 + return score7_register_move_cost (mode, from, to);7131 + else if (TARGET_SCORE3)7132 + return score3_register_move_cost (mode, from, to);7133 +7134 + gcc_unreachable ();7135 }7136 7137 -/* Return the number of instructions needed to load a symbol of the7138 - given type into a register. */7139 -static int7140 -score_symbol_insns (enum score_symbol_type type)7141 +/* Implement TARGET_RTX_COSTS macro. */7142 +bool7143 +score_rtx_costs (rtx x, int code, int outer_code, int *total)7144 {7145 - switch (type)7146 - {7147 - case SYMBOL_GENERAL:7148 - return 2;7149 -7150 - case SYMBOL_SMALL_DATA:7151 - return 1;7152 - }7153 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)7154 + return score7_rtx_costs (x, code, outer_code, total);7155 + else if (TARGET_SCORE3)7156 + return score3_rtx_costs (x, code, outer_code, total);7157 7158 gcc_unreachable ();7159 }7160 7161 -/* Return the number of instructions needed to load or store a value7162 - of mode MODE at X. Return 0 if X isn't valid for MODE. */7163 -static int7164 -score_address_insns (rtx x, enum machine_mode mode)7165 +/* Implement TARGET_ADDRESS_COST macro. */7166 +int7167 +score_address_cost (rtx addr)7168 {7169 - struct score_address_info addr;7170 - int factor;7171 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)7172 + return score7_address_cost (addr);7173 + else if (TARGET_SCORE3)7174 + return score3_address_cost (addr);7175 7176 - if (mode == BLKmode)7177 - factor = 1;7178 - else7179 - factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;7180 + gcc_unreachable ();7181 +}7182 7183 - if (mda_classify_address (&addr, mode, x, false))7184 - switch (addr.type)7185 - {7186 - case ADD_REG:7187 - case ADD_CONST_INT:7188 - return factor;7189 -7190 - case ADD_SYMBOLIC:7191 - return factor * score_symbol_insns (addr.symbol_type);7192 - }7193 - return 0;7194 +/* Implement ASM_OUTPUT_EXTERNAL macro. */7195 +int7196 +score_output_external (FILE *file ATTRIBUTE_UNUSED,7197 + tree decl, const char *name)7198 +{7199 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)7200 + return score7_output_external (file, decl, name);7201 + else if (TARGET_SCORE3)7202 + return score3_output_external (file, decl, name);7203 +7204 + gcc_unreachable ();7205 }7206 7207 -/* Implement TARGET_RTX_COSTS macro. */7208 -static bool7209 -score_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,7210 - int *total)7211 +/* Implement RETURN_ADDR_RTX. Note, we do not support moving7212 + back to a previous frame. */7213 +rtx7214 +score_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)7215 {7216 - enum machine_mode mode = GET_MODE (x);7217 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)7218 + return score7_return_addr (count, frame);7219 + else if (TARGET_SCORE3)7220 + return score3_return_addr (count, frame);7221 7222 - switch (code)7223 - {7224 - case CONST_INT:7225 - if (outer_code == SET)7226 - {7227 - if (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')7228 - || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L'))7229 - *total = COSTS_N_INSNS (1);7230 - else7231 - *total = COSTS_N_INSNS (2);7232 - }7233 - else if (outer_code == PLUS || outer_code == MINUS)7234 - {7235 - if (CONST_OK_FOR_LETTER_P (INTVAL (x), 'N'))7236 - *total = 0;7237 - else if (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')7238 - || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L'))7239 - *total = 1;7240 - else7241 - *total = COSTS_N_INSNS (2);7242 - }7243 - else if (outer_code == AND || outer_code == IOR)7244 - {7245 - if (CONST_OK_FOR_LETTER_P (INTVAL (x), 'M'))7246 - *total = 0;7247 - else if (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')7248 - || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K'))7249 - *total = 1;7250 - else7251 - *total = COSTS_N_INSNS (2);7252 - }7253 - else7254 - {7255 - *total = 0;7256 - }7257 - return true;7258 + gcc_unreachable ();7259 +}7260 7261 - case CONST:7262 - case SYMBOL_REF:7263 - case LABEL_REF:7264 - case CONST_DOUBLE:7265 - *total = COSTS_N_INSNS (2);7266 - return true;7267 +/* Implement PRINT_OPERAND macro. */7268 +void7269 +score_print_operand (FILE *file, rtx op, int c)7270 +{7271 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)7272 + return score7_print_operand (file, op, c);7273 + else if (TARGET_SCORE3)7274 + return score3_print_operand (file, op, c);7275 7276 - case MEM:7277 - {7278 - /* If the address is legitimate, return the number of7279 - instructions it needs, otherwise use the default handling. */7280 - int n = score_address_insns (XEXP (x, 0), GET_MODE (x));7281 - if (n > 0)7282 - {7283 - *total = COSTS_N_INSNS (n + 1);7284 - return true;7285 - }7286 - return false;7287 - }7288 + gcc_unreachable ();7289 +}7290 7291 - case FFS:7292 - *total = COSTS_N_INSNS (6);7293 - return true;7294 +/* Implement PRINT_OPERAND_ADDRESS macro. */7295 +void7296 +score_print_operand_address (FILE *file, rtx x)7297 +{7298 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)7299 + return score7_print_operand_address (file, x);7300 + else if (TARGET_SCORE3)7301 + return score3_print_operand_address (file, x);7302 7303 - case NOT:7304 - *total = COSTS_N_INSNS (1);7305 - return true;7306 + gcc_unreachable ();7307 +}7308 7309 - case AND:7310 - case IOR:7311 - case XOR:7312 - if (mode == DImode)7313 - {7314 - *total = COSTS_N_INSNS (2);7315 - return true;7316 - }7317 - return false;7318 +/* Implement SELECT_CC_MODE macro. */7319 +enum machine_mode7320 +score_select_cc_mode (enum rtx_code op, rtx x, rtx y)7321 +{7322 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)7323 + return score7_select_cc_mode (op, x, y);7324 + else if (TARGET_SCORE3)7325 + return score3_select_cc_mode (op, x, y);7326 7327 - case ASHIFT:7328 - case ASHIFTRT:7329 - case LSHIFTRT:7330 - if (mode == DImode)7331 - {7332 - *total = COSTS_N_INSNS ((GET_CODE (XEXP (x, 1)) == CONST_INT)7333 - ? 4 : 12);7334 - return true;7335 - }7336 - return false;7337 + gcc_unreachable ();7338 +}7339 7340 - case ABS:7341 - *total = COSTS_N_INSNS (4);7342 - return true;7343 +/* Return true if X is a symbolic constant that can be calculated in7344 + the same way as a bare symbol. If it is, store the type of the7345 + symbol in *SYMBOL_TYPE. */7346 +int7347 +score_symbolic_constant_p (rtx x, enum score_symbol_type *symbol_type)7348 +{7349 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)7350 + return score7_symbolic_constant_p (x, symbol_type);7351 + else if (TARGET_SCORE3)7352 + return score3_symbolic_constant_p (x, symbol_type);7353 7354 - case PLUS:7355 - case MINUS:7356 - if (mode == DImode)7357 - {7358 - *total = COSTS_N_INSNS (4);7359 - return true;7360 - }7361 - *total = COSTS_N_INSNS (1);7362 - return true;7363 + gcc_unreachable ();7364 +}7365 7366 - case NEG:7367 - if (mode == DImode)7368 - {7369 - *total = COSTS_N_INSNS (4);7370 - return true;7371 - }7372 - return false;7373 +/* Generate the prologue instructions for entry into a S+core function. */7374 +void7375 +score_prologue (void)7376 +{7377 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)7378 + return score7_prologue ();7379 + else if (TARGET_SCORE3)7380 + return score3_prologue ();7381 7382 - case MULT:7383 - *total = optimize_size ? COSTS_N_INSNS (2) : COSTS_N_INSNS (12);7384 - return true;7385 + gcc_unreachable ();7386 +}7387 7388 - case DIV:7389 - case MOD:7390 - case UDIV:7391 - case UMOD:7392 - *total = optimize_size ? COSTS_N_INSNS (2) : COSTS_N_INSNS (33);7393 - return true;7394 +/* Generate the epilogue instructions in a S+core function. */7395 +void7396 +score_epilogue (int sibcall_p)7397 +{7398 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)7399 + return score7_epilogue (sibcall_p);7400 + else if (TARGET_SCORE3)7401 + return score3_epilogue (sibcall_p);7402 7403 - case SIGN_EXTEND:7404 - case ZERO_EXTEND:7405 - switch (GET_MODE (XEXP (x, 0)))7406 - {7407 - case QImode:7408 - case HImode:7409 - if (GET_CODE (XEXP (x, 0)) == MEM)7410 - {7411 - *total = COSTS_N_INSNS (2);7412 -7413 - if (!TARGET_LITTLE_ENDIAN &&7414 - side_effects_p (XEXP (XEXP (x, 0), 0)))7415 - *total = 100;7416 - }7417 - else7418 - *total = COSTS_N_INSNS (1);7419 - break;7420 -7421 - default:7422 - *total = COSTS_N_INSNS (1);7423 - break;7424 - }7425 - return true;7426 + gcc_unreachable ();7427 +}7428 7429 - default:7430 - return false;7431 - }7432 +void7433 +score_gen_cmp (enum machine_mode mode)7434 +{7435 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)7436 + return score7_gen_cmp (mode);7437 + else if (TARGET_SCORE3)7438 + return score3_gen_cmp (mode);7439 +7440 + gcc_unreachable ();7441 }7442 7443 -/* Implement TARGET_ADDRESS_COST macro. */7444 -int7445 -score_address_cost (rtx addr)7446 +/* Call and sibcall pattern all need call this function. */7447 +void7448 +score_call (rtx *ops, bool sib)7449 {7450 - return score_address_insns (addr, SImode);7451 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)7452 + return score7_call (ops, sib);7453 + else if (TARGET_SCORE3)7454 + return score3_call (ops, sib);7455 +7456 + gcc_unreachable ();7457 }7458 7459 -/* Implement ASM_OUTPUT_EXTERNAL macro. */7460 -int7461 -score_output_external (FILE *file ATTRIBUTE_UNUSED,7462 - tree decl, const char *name)7463 +/* Call value and sibcall value pattern all need call this function. */7464 +void7465 +score_call_value (rtx *ops, bool sib)7466 {7467 - register struct extern_list *p;7468 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)7469 + return score7_call_value (ops, sib);7470 + else if (TARGET_SCORE3)7471 + return score3_call_value (ops, sib);7472 7473 - if (th_in_small_data_p (decl))7474 - {7475 - p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));7476 - p->next = extern_head;7477 - p->name = name;7478 - p->size = int_size_in_bytes (TREE_TYPE (decl));7479 - extern_head = p;7480 - }7481 - return 0;7482 + gcc_unreachable ();7483 }7484 7485 -/* Output format asm string. */7486 void7487 -score_declare_object (FILE *stream, const char *name,7488 - const char *directive, const char *fmt, ...)7489 +score_movsicc (rtx *ops)7490 {7491 - va_list ap;7492 - fputs (directive, stream);7493 - assemble_name (stream, name);7494 - va_start (ap, fmt);7495 - vfprintf (stream, fmt, ap);7496 - va_end (ap);7497 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)7498 + return score7_movsicc (ops);7499 + else if (TARGET_SCORE3)7500 + return score3_movsicc (ops);7501 +7502 + gcc_unreachable ();7503 }7504 7505 -/* Implement RETURN_ADDR_RTX. Note, we do not support moving7506 - back to a previous frame. */7507 -rtx7508 -score_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)7509 +/* Machine Split */7510 +void7511 +score_movdi (rtx *ops)7512 {7513 - if (count != 0)7514 - return const0_rtx;7515 - return get_hard_reg_initial_val (Pmode, RA_REGNUM);7516 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)7517 + return score7_movdi (ops);7518 + else if (TARGET_SCORE3)7519 + return score3_movdi (ops);7520 +7521 + gcc_unreachable ();7522 }7523 7524 -/* Implement PRINT_OPERAND macro. */7525 -/* Score-specific operand codes:7526 - '[' print .set nor1 directive7527 - ']' print .set r1 directive7528 - 'U' print hi part of a CONST_INT rtx7529 - 'E' print log2(v)7530 - 'F' print log2(~v)7531 - 'D' print SFmode const double7532 - 'S' selectively print "!" if operand is 15bit instruction accessible7533 - 'V' print "v!" if operand is 15bit instruction accessible, or "lfh!"7534 - 'L' low part of DImode reg operand7535 - 'H' high part of DImode reg operand7536 - 'C' print part of opcode for a branch condition. */7537 void7538 -score_print_operand (FILE *file, rtx op, int c)7539 +score_zero_extract_andi (rtx *ops)7540 {7541 - enum rtx_code code = -1;7542 - if (!PRINT_OPERAND_PUNCT_VALID_P (c))7543 - code = GET_CODE (op);7544 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)7545 + return score7_zero_extract_andi (ops);7546 + else if (TARGET_SCORE3)7547 + return score3_zero_extract_andi (ops);7548 +7549 + gcc_unreachable ();7550 +}7551 +7552 +/* Output asm insn for move. */7553 +const char *7554 +score_move (rtx *ops)7555 +{7556 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)7557 + return score7_move (ops);7558 + else if (TARGET_SCORE3)7559 + return score3_move (ops);7560 7561 - if (c == '[')7562 + gcc_unreachable ();7563 +}7564 +7565 +/* Output asm insn for load. */7566 +const char *7567 +score_linsn (rtx *ops, enum score_mem_unit unit, bool sign)7568 +{7569 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)7570 + return score7_linsn (ops, unit, sign);7571 + else if (TARGET_SCORE3)7572 + return score3_linsn (ops, unit, sign);7573 +7574 + gcc_unreachable ();7575 +}7576 +7577 +/* Output asm insn for store. */7578 +const char *7579 +score_sinsn (rtx *ops, enum score_mem_unit unit)7580 +{7581 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)7582 + return score7_sinsn (ops, unit);7583 + else if (TARGET_SCORE3)7584 + return score3_sinsn (ops, unit);7585 +7586 + gcc_unreachable ();7587 +}7588 +7589 +/* Output asm insn for load immediate. */7590 +const char *7591 +score_limm (rtx *ops)7592 +{7593 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)7594 + return score7_limm (ops);7595 + else if (TARGET_SCORE3)7596 + return score3_limm (ops);7597 +7598 + gcc_unreachable ();7599 +}7600 +7601 +7602 +/* Generate add insn. */7603 +const char *7604 +score_select_add_imm (rtx *ops, bool set_cc)7605 +{7606 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)7607 + return score7_select_add_imm (ops, set_cc);7608 + else if (TARGET_SCORE3)7609 + return score3_select_add_imm (ops, set_cc);7610 +7611 + gcc_unreachable ();7612 +}7613 +7614 +/* Output arith insn. */7615 +const char *7616 +score_select (rtx *ops, const char *inst_pre,7617 + bool commu, const char *letter, bool set_cc)7618 +{7619 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)7620 + return score7_select (ops, inst_pre, commu, letter, set_cc);7621 + else if (TARGET_SCORE3)7622 + return score3_select (ops, inst_pre, commu, letter, set_cc);7623 +7624 + gcc_unreachable ();7625 +}7626 +7627 +/* Output switch case insn, only supported in score3. */7628 +const char *7629 +score_output_casesi (rtx *operands)7630 +{7631 + if (TARGET_SCORE3)7632 + return score3_output_casesi (operands);7633 +7634 + gcc_unreachable ();7635 +}7636 +7637 +/* Output rpush insn, only supported in score3. */7638 +const char *7639 +score_rpush (rtx *operands)7640 +{7641 + if (TARGET_SCORE3)7642 + return score3_rpush (operands);7643 +7644 + gcc_unreachable ();7645 +}7646 +7647 +/* Output rpop insn, only supported in score3. */7648 +const char *7649 +score_rpop (rtx *operands)7650 +{7651 + if (TARGET_SCORE3)7652 + return score3_rpop (operands);7653 +7654 + gcc_unreachable ();7655 +}7656 +7657 +/* Emit lcb/lce insns. */7658 +bool7659 +score_unaligned_load (rtx *ops)7660 +{7661 + rtx dst = ops[0];7662 + rtx src = ops[1];7663 + rtx len = ops[2];7664 + rtx off = ops[3];7665 + rtx addr_reg;7666 +7667 + if (INTVAL (len) != BITS_PER_WORD7668 + || (INTVAL (off) % BITS_PER_UNIT) != 0)7669 + return false;7670 +7671 + gcc_assert (GET_MODE_SIZE (GET_MODE (dst)) == GET_MODE_SIZE (SImode));7672 +7673 + addr_reg = copy_addr_to_reg (XEXP (src, 0));7674 + emit_insn (gen_move_lcb (addr_reg, addr_reg));7675 + emit_insn (gen_move_lce (addr_reg, addr_reg, dst));7676 +7677 + return true;7678 +}7679 +7680 +/* Emit scb/sce insns. */7681 +bool7682 +score_unaligned_store (rtx *ops)7683 +{7684 + rtx dst = ops[0];7685 + rtx len = ops[1];7686 + rtx off = ops[2];7687 + rtx src = ops[3];7688 + rtx addr_reg;7689 +7690 + if (INTVAL(len) != BITS_PER_WORD7691 + || (INTVAL(off) % BITS_PER_UNIT) != 0)7692 + return false;7693 +7694 + gcc_assert (GET_MODE_SIZE (GET_MODE (src)) == GET_MODE_SIZE (SImode));7695 +7696 + addr_reg = copy_addr_to_reg (XEXP (dst, 0));7697 + emit_insn (gen_move_scb (addr_reg, addr_reg, src));7698 + emit_insn (gen_move_sce (addr_reg, addr_reg));7699 +7700 + return true;7701 +}7702 +7703 +/* If length is short, generate move insns straight. */7704 +static void7705 +score_block_move_straight (rtx dst, rtx src, HOST_WIDE_INT length)7706 +{7707 + HOST_WIDE_INT leftover;7708 + int i, reg_count;7709 + rtx *regs;7710 +7711 + leftover = length % UNITS_PER_WORD;7712 + length -= leftover;7713 + reg_count = length / UNITS_PER_WORD;7714 +7715 + regs = alloca (sizeof (rtx) * reg_count);7716 + for (i = 0; i < reg_count; i++)7717 + regs[i] = gen_reg_rtx (SImode);7718 +7719 + /* Load from src to regs. */7720 + if (MEM_ALIGN (src) >= BITS_PER_WORD)7721 {7722 - fprintf (file, ".set r1\n");7723 + HOST_WIDE_INT offset = 0;7724 + for (i = 0; i < reg_count; offset += UNITS_PER_WORD, i++)7725 + emit_move_insn (regs[i], adjust_address (src, SImode, offset));7726 }7727 - else if (c == ']')7728 + else if (reg_count >= 1)7729 {7730 - fprintf (file, "\n\t.set nor1");7731 + rtx src_reg = copy_addr_to_reg (XEXP (src, 0));7732 +7733 + emit_insn (gen_move_lcb (src_reg, src_reg));7734 + for (i = 0; i < (reg_count - 1); i++)7735 + emit_insn (gen_move_lcw (src_reg, src_reg, regs[i]));7736 + emit_insn (gen_move_lce (src_reg, src_reg, regs[i]));7737 }7738 - else if (c == 'U')7739 +7740 + /* Store regs to dest. */7741 + if (MEM_ALIGN (dst) >= BITS_PER_WORD)7742 {7743 - gcc_assert (code == CONST_INT);7744 - fprintf (file, HOST_WIDE_INT_PRINT_HEX,7745 - (INTVAL (op) >> 16) & 0xffff);7746 + HOST_WIDE_INT offset = 0;7747 + for (i = 0; i < reg_count; offset += UNITS_PER_WORD, i++)7748 + emit_move_insn (adjust_address (dst, SImode, offset), regs[i]);7749 }7750 - else if (c == 'D')7751 + else if (reg_count >= 1)7752 {7753 - if (GET_CODE (op) == CONST_DOUBLE)7754 - {7755 - rtx temp = gen_lowpart (SImode, op);7756 - gcc_assert (GET_MODE (op) == SFmode);7757 - fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (temp) & 0xffffffff);7758 - }7759 - else7760 - output_addr_const (file, op);7761 + rtx dst_reg = copy_addr_to_reg (XEXP (dst, 0));7762 +7763 + emit_insn (gen_move_scb (dst_reg, dst_reg, regs[0]));7764 + for (i = 1; i < reg_count; i++)7765 + emit_insn (gen_move_scw (dst_reg, dst_reg, regs[i]));7766 + emit_insn (gen_move_sce (dst_reg, dst_reg));7767 }7768 - else if (c == 'S')7769 +7770 + /* Mop up any left-over bytes. */7771 + if (leftover > 0)7772 {7773 - gcc_assert (code == REG);7774 - if (G16_REG_P (REGNO (op)))7775 - fprintf (file, "!");7776 + src = adjust_address (src, BLKmode, length);7777 + dst = adjust_address (dst, BLKmode, length);7778 + move_by_pieces (dst, src, leftover,7779 + MIN (MEM_ALIGN (src), MEM_ALIGN (dst)), 0);7780 }7781 - else if (c == 'V')7782 +}7783 +7784 +/* Generate loop head when dst or src is unaligned. */7785 +static void7786 +score_block_move_loop_head (rtx dst_reg, HOST_WIDE_INT dst_align,7787 + rtx src_reg, HOST_WIDE_INT src_align,7788 + HOST_WIDE_INT length)7789 +{7790 + bool src_unaligned = (src_align < BITS_PER_WORD);7791 + bool dst_unaligned = (dst_align < BITS_PER_WORD);7792 +7793 + rtx temp = gen_reg_rtx (SImode);7794 +7795 + gcc_assert (length == UNITS_PER_WORD);7796 +7797 + if (src_unaligned)7798 {7799 - gcc_assert (code == REG);7800 - fprintf (file, G16_REG_P (REGNO (op)) ? "v!" : "lfh!");7801 + emit_insn (gen_move_lcb (src_reg, src_reg));7802 + emit_insn (gen_move_lcw (src_reg, src_reg, temp));7803 }7804 - else if (c == 'C')7805 - {7806 - enum machine_mode mode = GET_MODE (XEXP (op, 0));7807 + else7808 + emit_insn (gen_move_lw_a (src_reg,7809 + src_reg, gen_int_mode (4, SImode), temp));7810 7811 - switch (code)7812 - {7813 - case EQ: fputs ("eq", file); break;7814 - case NE: fputs ("ne", file); break;7815 - case GT: fputs ("gt", file); break;7816 - case GE: fputs (mode != CCmode ? "pl" : "ge", file); break;7817 - case LT: fputs (mode != CCmode ? "mi" : "lt", file); break;7818 - case LE: fputs ("le", file); break;7819 - case GTU: fputs ("gtu", file); break;7820 - case GEU: fputs ("cs", file); break;7821 - case LTU: fputs ("cc", file); break;7822 - case LEU: fputs ("leu", file); break;7823 - default:7824 - output_operand_lossage ("invalid operand for code: '%c'", code);7825 - }7826 - }7827 - else if (c == 'E')7828 - {7829 - unsigned HOST_WIDE_INT i;7830 - unsigned HOST_WIDE_INT pow2mask = 1;7831 - unsigned HOST_WIDE_INT val;7832 + if (dst_unaligned)7833 + emit_insn (gen_move_scb (dst_reg, dst_reg, temp));7834 + else7835 + emit_insn (gen_move_sw_a (dst_reg,7836 + dst_reg, gen_int_mode (4, SImode), temp));7837 +}7838 7839 - val = INTVAL (op);7840 - for (i = 0; i < 32; i++)7841 - {7842 - if (val == pow2mask)7843 - break;7844 - pow2mask <<= 1;7845 - }7846 - gcc_assert (i < 32);7847 - fprintf (file, HOST_WIDE_INT_PRINT_HEX, i);7848 +/* Generate loop body, copy length bytes per iteration. */7849 +static void7850 +score_block_move_loop_body (rtx dst_reg, HOST_WIDE_INT dst_align,7851 + rtx src_reg, HOST_WIDE_INT src_align,7852 + HOST_WIDE_INT length)7853 +{7854 + int reg_count = length / UNITS_PER_WORD;7855 + rtx *regs = alloca (sizeof (rtx) * reg_count);7856 + int i;7857 + bool src_unaligned = (src_align < BITS_PER_WORD);7858 + bool dst_unaligned = (dst_align < BITS_PER_WORD);7859 +7860 + for (i = 0; i < reg_count; i++)7861 + regs[i] = gen_reg_rtx (SImode);7862 +7863 + if (src_unaligned)7864 + {7865 + for (i = 0; i < reg_count; i++)7866 + emit_insn (gen_move_lcw (src_reg, src_reg, regs[i]));7867 }7868 - else if (c == 'F')7869 + else7870 {7871 - unsigned HOST_WIDE_INT i;7872 - unsigned HOST_WIDE_INT pow2mask = 1;7873 - unsigned HOST_WIDE_INT val;7874 -7875 - val = ~INTVAL (op);7876 - for (i = 0; i < 32; i++)7877 - {7878 - if (val == pow2mask)7879 - break;7880 - pow2mask <<= 1;7881 - }7882 - gcc_assert (i < 32);7883 - fprintf (file, HOST_WIDE_INT_PRINT_HEX, i);7884 + for (i = 0; i < reg_count; i++)7885 + emit_insn (gen_move_lw_a (src_reg,7886 + src_reg, gen_int_mode (4, SImode), regs[i]));7887 }7888 - else if (code == REG)7889 +7890 + if (dst_unaligned)7891 {7892 - int regnum = REGNO (op);7893 - if ((c == 'H' && !WORDS_BIG_ENDIAN)7894 - || (c == 'L' && WORDS_BIG_ENDIAN))7895 - regnum ++;7896 - fprintf (file, "%s", reg_names[regnum]);7897 + for (i = 0; i < reg_count; i++)7898 + emit_insn (gen_move_scw (dst_reg, dst_reg, regs[i]));7899 }7900 else7901 {7902 - switch (code)7903 - {7904 - case MEM:7905 - score_print_operand_address (file, op);7906 - break;7907 - default:7908 - output_addr_const (file, op);7909 - }7910 + for (i = 0; i < reg_count; i++)7911 + emit_insn (gen_move_sw_a (dst_reg,7912 + dst_reg, gen_int_mode (4, SImode), regs[i]));7913 }7914 }7915 7916 -/* Implement PRINT_OPERAND_ADDRESS macro. */7917 -void7918 -score_print_operand_address (FILE *file, rtx x)7919 +/* Generate loop foot, copy the leftover bytes. */7920 +static void7921 +score_block_move_loop_foot (rtx dst_reg, HOST_WIDE_INT dst_align,7922 + rtx src_reg, HOST_WIDE_INT src_align,7923 + HOST_WIDE_INT length)7924 {7925 - struct score_address_info addr;7926 - enum rtx_code code = GET_CODE (x);7927 - enum machine_mode mode = GET_MODE (x);7928 + bool src_unaligned = (src_align < BITS_PER_WORD);7929 + bool dst_unaligned = (dst_align < BITS_PER_WORD);7930 +7931 + HOST_WIDE_INT leftover;7932 +7933 + leftover = length % UNITS_PER_WORD;7934 + length -= leftover;7935 7936 - if (code == MEM)7937 - x = XEXP (x, 0);7938 + if (length > 0)7939 + score_block_move_loop_body (dst_reg, dst_align,7940 + src_reg, src_align, length);7941 7942 - if (mda_classify_address (&addr, mode, x, true))7943 + if (dst_unaligned)7944 + emit_insn (gen_move_sce (dst_reg, dst_reg));7945 +7946 + if (leftover > 0)7947 {7948 - switch (addr.type)7949 + HOST_WIDE_INT src_adj = src_unaligned ? -4 : 0;7950 + HOST_WIDE_INT dst_adj = dst_unaligned ? -4 : 0;7951 + rtx temp;7952 +7953 + gcc_assert (leftover < UNITS_PER_WORD);7954 +7955 + if (leftover >= UNITS_PER_WORD / 27956 + && src_align >= BITS_PER_WORD / 27957 + && dst_align >= BITS_PER_WORD / 2)7958 {7959 - case ADD_REG:7960 - {7961 - switch (addr.code)7962 - {7963 - case PRE_DEC:7964 - fprintf (file, "[%s,-%ld]+", reg_names[REGNO (addr.reg)],7965 - INTVAL (addr.offset));7966 - break;7967 - case POST_DEC:7968 - fprintf (file, "[%s]+,-%ld", reg_names[REGNO (addr.reg)],7969 - INTVAL (addr.offset));7970 - break;7971 - case PRE_INC:7972 - fprintf (file, "[%s, %ld]+", reg_names[REGNO (addr.reg)],7973 - INTVAL (addr.offset));7974 - break;7975 - case POST_INC:7976 - fprintf (file, "[%s]+, %ld", reg_names[REGNO (addr.reg)],7977 - INTVAL (addr.offset));7978 - break;7979 - default:7980 - if (INTVAL(addr.offset) == 0)7981 - fprintf(file, "[%s]", reg_names[REGNO (addr.reg)]);7982 - else7983 - fprintf(file, "[%s, %ld]", reg_names[REGNO (addr.reg)],7984 - INTVAL(addr.offset));7985 - break;7986 - }7987 - }7988 - return;7989 - case ADD_CONST_INT:7990 - case ADD_SYMBOLIC:7991 - output_addr_const (file, x);7992 - return;7993 + temp = gen_reg_rtx (HImode);7994 + emit_insn (gen_move_lhu_b (src_reg, src_reg,7995 + gen_int_mode (src_adj, SImode), temp));7996 + emit_insn (gen_move_sh_b (dst_reg, dst_reg,7997 + gen_int_mode (dst_adj, SImode), temp));7998 + leftover -= UNITS_PER_WORD / 2;7999 + src_adj = UNITS_PER_WORD / 2;8000 + dst_adj = UNITS_PER_WORD / 2;8001 + }8002 +8003 + while (leftover > 0)8004 + {8005 + temp = gen_reg_rtx (QImode);8006 + emit_insn (gen_move_lbu_b (src_reg, src_reg,8007 + gen_int_mode (src_adj, SImode), temp));8008 + emit_insn (gen_move_sb_b (dst_reg, dst_reg,8009 + gen_int_mode (dst_adj, SImode), temp));8010 + leftover--;8011 + src_adj = 1;8012 + dst_adj = 1;8013 }8014 }8015 - print_rtl (stderr, x);8016 - gcc_unreachable ();8017 }8018 8019 -/* Implement SELECT_CC_MODE macro. */8020 -enum machine_mode8021 -score_select_cc_mode (enum rtx_code op, rtx x, rtx y)8022 +#define MIN_MOVE_REGS 38023 +#define MIN_MOVE_BYTES (MIN_MOVE_REGS * UNITS_PER_WORD)8024 +#define MAX_MOVE_REGS 48025 +#define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)8026 +8027 +/* The length is large, generate a loop if necessary.8028 + The loop is consisted by loop head/body/foot. */8029 +static void8030 +score_block_move_loop (rtx dst, rtx src, HOST_WIDE_INT length)8031 {8032 - if ((op == EQ || op == NE || op == LT || op == GE)8033 - && y == const0_rtx8034 - && GET_MODE (x) == SImode)8035 - {8036 - switch (GET_CODE (x))8037 - {8038 - case PLUS:8039 - case MINUS:8040 - case NEG:8041 - case AND:8042 - case IOR:8043 - case XOR:8044 - case NOT:8045 - case ASHIFT:8046 - case LSHIFTRT:8047 - case ASHIFTRT:8048 - return CC_NZmode;8049 -8050 - case SIGN_EXTEND:8051 - case ZERO_EXTEND:8052 - case ROTATE:8053 - case ROTATERT:8054 - return (op == LT || op == GE) ? CC_Nmode : CCmode;8055 + HOST_WIDE_INT src_align = MEM_ALIGN (src);8056 + HOST_WIDE_INT dst_align = MEM_ALIGN (dst);8057 + HOST_WIDE_INT loop_mov_bytes;8058 + HOST_WIDE_INT iteration = 0;8059 + HOST_WIDE_INT head_length = 0, leftover;8060 + rtx label, src_reg, dst_reg, final_dst;8061 8062 - default:8063 - return CCmode;8064 - }8065 - }8066 + bool gen_loop_head = (src_align < BITS_PER_WORD8067 + || dst_align < BITS_PER_WORD);8068 +8069 + if (gen_loop_head)8070 + head_length += UNITS_PER_WORD;8071 8072 - if ((op == EQ || op == NE)8073 - && (GET_CODE (y) == NEG)8074 - && register_operand (XEXP (y, 0), SImode)8075 - && register_operand (x, SImode))8076 + for (loop_mov_bytes = MAX_MOVE_BYTES;8077 + loop_mov_bytes >= MIN_MOVE_BYTES;8078 + loop_mov_bytes -= UNITS_PER_WORD)8079 + {8080 + iteration = (length - head_length) / loop_mov_bytes;8081 + if (iteration > 1)8082 + break;8083 + }8084 + if (iteration <= 1)8085 {8086 - return CC_NZmode;8087 + score_block_move_straight (dst, src, length);8088 + return;8089 }8090 8091 - return CCmode;8092 + leftover = (length - head_length) % loop_mov_bytes;8093 + length -= leftover;8094 +8095 + src_reg = copy_addr_to_reg (XEXP (src, 0));8096 + dst_reg = copy_addr_to_reg (XEXP (dst, 0));8097 + final_dst = expand_simple_binop (Pmode, PLUS, dst_reg, GEN_INT (length),8098 + 0, 0, OPTAB_WIDEN);8099 +8100 + if (gen_loop_head)8101 + score_block_move_loop_head (dst_reg, dst_align,8102 + src_reg, src_align, head_length);8103 +8104 + label = gen_label_rtx ();8105 + emit_label (label);8106 +8107 + score_block_move_loop_body (dst_reg, dst_align,8108 + src_reg, src_align, loop_mov_bytes);8109 +8110 + emit_insn (gen_cmpsi (dst_reg, final_dst));8111 + emit_jump_insn (gen_bne (label));8112 +8113 + score_block_move_loop_foot (dst_reg, dst_align,8114 + src_reg, src_align, leftover);8115 +}8116 +8117 +/* Generate block move, for misc.md: "movmemsi". */8118 +bool8119 +score_block_move (rtx *ops)8120 +{8121 + rtx dst = ops[0];8122 + rtx src = ops[1];8123 + rtx length = ops[2];8124 +8125 + if (TARGET_LITTLE_ENDIAN8126 + && (MEM_ALIGN (src) < BITS_PER_WORD || MEM_ALIGN (dst) < BITS_PER_WORD)8127 + && INTVAL (length) >= UNITS_PER_WORD)8128 + return false;8129 +8130 + if (GET_CODE (length) == CONST_INT)8131 + {8132 + if (INTVAL (length) <= 2 * MAX_MOVE_BYTES)8133 + {8134 + score_block_move_straight (dst, src, INTVAL (length));8135 + return true;8136 + }8137 + else if (optimize &&8138 + !(flag_unroll_loops || flag_unroll_all_loops))8139 + {8140 + score_block_move_loop (dst, src, INTVAL (length));8141 + return true;8142 + }8143 + }8144 + return false;8145 }8146 8147 struct gcc_target targetm = TARGET_INITIALIZER;8148 diff -Naur gcc-4.2.2.orig/gcc/config/score/score-conv.h gcc-4.2.2/gcc/config/score/score-conv.h8149 --- gcc-4.2.2.orig/gcc/config/score/score-conv.h 2007-09-01 08:28:30.000000000 -07008150 +++ gcc-4.2.2/gcc/config/score/score-conv.h 2007-10-17 23:24:34.000000000 -07008151 @@ -17,11 +17,16 @@8152 along with GCC; see the file COPYING3. If not see8153 <http://www.gnu.org/licenses/>. */8154 8155 -#ifndef SCORE_CONV_06018156 -#define SCORE_CONV_06018157 +#ifndef GCC_SCORE_CONV_H8158 +#define GCC_SCORE_CONV_H8159 8160 extern int target_flags;8161 8162 +/* Define the information needed to generate branch insns. This is8163 + stored from the compare operation. */8164 +extern GTY(()) rtx cmp_op0;8165 +extern GTY(()) rtx cmp_op1;8166 +8167 #define GP_REG_FIRST 0U8168 #define GP_REG_LAST 31U8169 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1U)8170 @@ -40,47 +45,38 @@8171 8172 #define GP_REG_P(REGNO) REG_CONTAIN (REGNO, GP_REG_FIRST, GP_REG_NUM)8173 8174 +#define G8_REG_P(REGNO) REG_CONTAIN (REGNO, GP_REG_FIRST, 8)8175 +8176 #define G16_REG_P(REGNO) REG_CONTAIN (REGNO, GP_REG_FIRST, 16)8177 8178 #define CE_REG_P(REGNO) REG_CONTAIN (REGNO, CE_REG_FIRST, CE_REG_NUM)8179 8180 -#define UIMM_IN_RANGE(V, W) ((V) >= 0 && (V) < ((HOST_WIDE_INT) 1 << (W)))8181 +#define GR_REG_CLASS_P(C) ((C) == G16_REGS || (C) == G32_REGS)8182 +#define SP_REG_CLASS_P(C) \8183 + ((C) == CN_REG || (C) == LC_REG || (C) == SC_REG || (C) == SP_REGS)8184 +#define CP_REG_CLASS_P(C) \8185 + ((C) == CP1_REGS || (C) == CP2_REGS || (C) == CP3_REGS || (C) == CPA_REGS)8186 +#define CE_REG_CLASS_P(C) \8187 + ((C) == HI_REG || (C) == LO_REG || (C) == CE_REGS)8188 +8189 +#define UIMM_IN_RANGE(V, W) ((V) >= 0 && (V) < ((HOST_WIDE_INT) 1 << (W)))8190 8191 #define SIMM_IN_RANGE(V, W) \8192 ((V) >= (-1 * ((HOST_WIDE_INT) 1 << ((W) - 1))) \8193 && (V) < (1 * ((HOST_WIDE_INT) 1 << ((W) - 1))))8194 8195 -#define IMM_IN_RANGE(V, W, S) \8196 +#define IMM_IN_RANGE(V, W, S) \8197 ((S) ? SIMM_IN_RANGE (V, W) : UIMM_IN_RANGE (V, W))8198 8199 -#define IMM_IS_POW_OF_2(V, E1, E2) \8200 +#define IMM_IS_POW_OF_2(V, E1, E2) \8201 ((V) >= ((unsigned HOST_WIDE_INT) 1 << (E1)) \8202 && (V) <= ((unsigned HOST_WIDE_INT) 1 << (E2)) \8203 && ((V) & ((V) - 1)) == 0)8204 8205 -#define SCORE_STACK_ALIGN(LOC) (((LOC) + 3) & ~3)8206 -8207 -#define SCORE_MAX_FIRST_STACK_STEP (0x3ff0)8208 -8209 -#define SCORE_SDATA_MAX score_sdata_max ()8210 -8211 -#define DEFAULT_SDATA_MAX 88212 -8213 -#define CONST_HIGH_PART(VALUE) \8214 - (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)8215 -8216 -#define CONST_LOW_PART(VALUE) ((VALUE) - CONST_HIGH_PART (VALUE))8217 -8218 -#define PROLOGUE_TEMP_REGNUM (GP_REG_FIRST + 8)8219 -8220 -#define EPILOGUE_TEMP_REGNUM (GP_REG_FIRST + 8)8221 -8222 enum score_symbol_type8223 {8224 SYMBOL_GENERAL,8225 - SYMBOL_SMALL_DATA /* The symbol refers to something in a small data section. */8226 + SYMBOL_SMALL_DATA /* The symbol refers to something in a small data section */8227 };8228 8229 -int score_sdata_max (void);8230 -8231 #endif8232 diff -Naur gcc-4.2.2.orig/gcc/config/score/score-generic.md gcc-4.2.2/gcc/config/score/score-generic.md8233 --- gcc-4.2.2.orig/gcc/config/score/score-generic.md 1969-12-31 16:00:00.000000000 -08008234 +++ gcc-4.2.2/gcc/config/score/score-generic.md 2007-10-17 23:24:34.000000000 -07008235 @@ -0,0 +1,45 @@8236 +;; Machine description for Sunplus S+CORE8237 +;; Sunplus S+CORE Pipeline Description8238 +;; Copyright (C) 2005, 20078239 +;; Free Software Foundation, Inc.8240 +;; Contributed by Sunnorth.8241 +8242 +;; This file is part of GCC.8243 +8244 +;; GCC is free software; you can redistribute it and/or modify8245 +;; it under the terms of the GNU General Public License as published by8246 +;; the Free Software Foundation; either version 3, or (at your option)8247 +;; any later version.8248 +8249 +;; GCC is distributed in the hope that it will be useful,8250 +;; but WITHOUT ANY WARRANTY; without even the implied warranty of8251 +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the8252 +;; GNU General Public License for more details.8253 +8254 +;; You should have received a copy of the GNU General Public License8255 +;; along with GCC; see the file COPYING3. If not see8256 +;; <http://www.gnu.org/licenses/>.8257 +8258 +(define_automaton "score")8259 +8260 +(define_cpu_unit "core" "score")8261 +8262 +(define_insn_reservation "memory" 38263 + (eq_attr "type" "load")8264 + "core")8265 +8266 +(define_insn_reservation "mul" 38267 + (eq_attr "type" "mul,div")8268 + "core")8269 +8270 +(define_insn_reservation "fce" 18271 + (eq_attr "type" "fce")8272 + "core")8273 +8274 +(define_insn_reservation "tsr" 18275 + (eq_attr "type" "tsr,fsr")8276 + "core")8277 +8278 +(define_insn_reservation "up_c" 18279 + (eq_attr "up_c" "yes")8280 + "core")8281 diff -Naur gcc-4.2.2.orig/gcc/config/score/score.h gcc-4.2.2/gcc/config/score/score.h8282 --- gcc-4.2.2.orig/gcc/config/score/score.h 2007-09-01 08:28:30.000000000 -07008283 +++ gcc-4.2.2/gcc/config/score/score.h 2007-10-17 23:24:34.000000000 -07008284 @@ -19,30 +19,53 @@8285 <http://www.gnu.org/licenses/>. */8286 8287 #include "score-conv.h"8288 -#include "score-version.h"8289 -8290 -/* Define the information needed to generate branch insns. This is8291 - stored from the compare operation. */8292 -extern GTY(()) rtx cmp_op0;8293 -extern GTY(()) rtx cmp_op1;8294 8295 /* Controlling the Compilation Driver. */8296 #undef SWITCH_TAKES_ARG8297 #define SWITCH_TAKES_ARG(CHAR) \8298 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')8299 8300 -/* CC1_SPEC is the set of arguments to pass to the compiler proper. */8301 +#undef CPP_SPEC8302 +#define CPP_SPEC "%{mscore3:-D__score3__} %{G*}"8303 +8304 #undef CC1_SPEC8305 -#define CC1_SPEC "%{G*} %{!mel:-meb}"8306 +#define CC1_SPEC "%{!mel:-meb} %{mel:-mel } \8307 +%{!mscore*:-mscore7} \8308 +%{mscore3:-mscore3} \8309 +%{mscore3d:-mscore3d} \8310 +%{mscore7:-mscore7} \8311 +%{mscore7d:-mscore7d} \8312 +%{G*}"8313 8314 #undef ASM_SPEC8315 -#define ASM_SPEC \8316 - "%{!mel:-EB} %{mel:-EL} %{mscore5:-SCORE5} %{mscore5u:-SCORE5U} \8317 - %{mscore7:%{!mmac:-SCORE7}} %{mscore7:%{mmac:-SCORE7D}} \8318 - %{mscore7d:-SCORE7D} %{G*}"8319 +#define ASM_SPEC "%{!mel:-EB} %{mel:-EL} \8320 +%{!mscore*:-march=score7} \8321 +%{mscore7:-march=score7} \8322 +%{mscore7d:-march=score7} \8323 +%{mscore3:-march=score3} \8324 +%{mscore3d:-march=score3} \8325 +%{march=score5:-march=score7} \8326 +%{march=score5u:-march=score7} \8327 +%{march=score7:-march=score7} \8328 +%{march=score7d:-march=score7} \8329 +%{march=score3:-march=score3} \8330 +%{march=score3d:-march=score3} \8331 +%{G*}"8332 8333 #undef LINK_SPEC8334 -#define LINK_SPEC "%{!mel:-EB} %{mel:-EL} %{G*}"8335 +#define LINK_SPEC "%{!mel:-EB} %{mel:-EL} \8336 +%{!mscore*:-mscore7_elf} \8337 +%{mscore7:-mscore7_elf} \8338 +%{mscore7d:-mscore7_elf} \8339 +%{mscore3:-mscore3_elf} \8340 +%{mscore3d:-mscore3_elf} \8341 +%{march=score5:-mscore7_elf} \8342 +%{march=score5u:-mscore7_elf} \8343 +%{march=score7:-mscore7_elf} \8344 +%{march=score7d:-mscore7_elf} \8345 +%{march=score3:-mscore3_elf} \8346 +%{march=score3d:-mscore3_elf} \8347 +%{G*}"8348 8349 /* Run-time Target Specification. */8350 #define TARGET_CPU_CPP_BUILTINS() \8351 @@ -54,16 +77,26 @@8352 builtin_define ("__scorele__"); \8353 else \8354 builtin_define ("__scorebe__"); \8355 + if (TARGET_SCORE5) \8356 + builtin_define ("__score5__"); \8357 if (TARGET_SCORE5U) \8358 builtin_define ("__score5u__"); \8359 - else \8360 + if (TARGET_SCORE7) \8361 builtin_define ("__score7__"); \8362 + if (TARGET_SCORE7D) \8363 + builtin_define ("__score7d__"); \8364 + if (TARGET_SCORE3) \8365 + builtin_define ("__score3__"); \8366 + if (TARGET_SCORE3D) \8367 + builtin_define ("__score3d__"); \8368 } while (0)8369 8370 -#define TARGET_DEFAULT MASK_SCORE78371 +#define TARGET_DEFAULT 08372 +8373 +#define SCORE_GCC_VERSION "1.6"8374 8375 #define TARGET_VERSION \8376 - fprintf (stderr, "Sunplus S+CORE %s", SCORE_GCC_VERSION);8377 + fprintf (stderr, "Sunplus S+core rev=%s", SCORE_GCC_VERSION);8378 8379 #define OVERRIDE_OPTIONS score_override_options ()8380 8381 @@ -415,6 +448,7 @@8382 /* The class value for index registers. */8383 #define INDEX_REG_CLASS NO_REGS8384 8385 +extern enum reg_class score_char_to_class[256];8386 #define REG_CLASS_FROM_LETTER(C) score_char_to_class[(unsigned char) (C)]8387 8388 /* Addressing modes, and classification of registers for them. */8389 @@ -545,7 +579,7 @@8390 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect8391 of this macro is to determine whether the space is included in8392 `current_function_outgoing_args_size'. */8393 -#define OUTGOING_REG_PARM_STACK_SPACE 18394 +#define OUTGOING_REG_PARM_STACK_SPACE8395 8396 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACK_SIZE) 08397 8398 @@ -619,28 +653,58 @@8399 /* Generating Code for Profiling */8400 /* Output assembler code to FILE to increment profiler label # LABELNO8401 for profiling a function entry. */8402 -#define FUNCTION_PROFILER(FILE, LABELNO) \8403 -{ \8404 - fprintf (FILE, " .set r1 \n"); \8405 - fprintf (FILE, " mv r%d,r%d \n", AT_REGNUM, RA_REGNUM); \8406 - fprintf (FILE, " subi r%d, %d \n", STACK_POINTER_REGNUM, 8); \8407 - fprintf (FILE, " jl _mcount \n"); \8408 - fprintf (FILE, " .set nor1 \n"); \8409 -}8410 +#define FUNCTION_PROFILER(FILE, LABELNO) \8411 + do { \8412 + if (TARGET_SCORE7) \8413 + { \8414 + fprintf (FILE, " .set r1 \n"); \8415 + fprintf (FILE, " mv r%d,r%d \n", AT_REGNUM, RA_REGNUM); \8416 + fprintf (FILE, " subi r%d, %d \n", STACK_POINTER_REGNUM, 8); \8417 + fprintf (FILE, " jl _mcount \n"); \8418 + fprintf (FILE, " .set nor1 \n"); \8419 + } \8420 + else if (TARGET_SCORE3) \8421 + { \8422 + fprintf (FILE, " .set r1 \n"); \8423 + fprintf (FILE, " mv! r%d,r%d \n", AT_REGNUM, RA_REGNUM); \8424 + fprintf (FILE, " addi! r%d, %d \n", STACK_POINTER_REGNUM, -8);\8425 + fprintf (FILE, " jl _mcount \n"); \8426 + fprintf (FILE, " .set nor1 \n"); \8427 + } \8428 + } while (0)8429 8430 -#define TRAMPOLINE_TEMPLATE(STREAM) \8431 -{ \8432 - fprintf (STREAM, "\t.set r1\n"); \8433 - fprintf (STREAM, "\tmv r31, r3\n"); \8434 - fprintf (STREAM, "\tbl nextinsn\n"); \8435 - fprintf (STREAM, "nextinsn:\n"); \8436 - fprintf (STREAM, "\tlw r1, [r3, 6*4-8]\n"); \8437 - fprintf (STREAM, "\tlw r23, [r3, 6*4-4]\n"); \8438 - fprintf (STREAM, "\tmv r3, r31\n"); \8439 - fprintf (STREAM, "\tbr! r1\n"); \8440 - fprintf (STREAM, "\tnop!\n"); \8441 - fprintf (STREAM, "\t.set nor1\n"); \8442 -}8443 +#define TRAMPOLINE_TEMPLATE(STREAM) \8444 + do { \8445 + if (TARGET_SCORE7) \8446 + { \8447 + fprintf (STREAM, "\t.set r1\n"); \8448 + fprintf (STREAM, "\tmv r31, r3\n"); \8449 + fprintf (STREAM, "\tbl nextinsn\n"); \8450 + fprintf (STREAM, "nextinsn:\n"); \8451 + fprintf (STREAM, "\tlw r1, [r3, 6*4-8]\n"); \8452 + fprintf (STREAM, "\tlw r23, [r3, 6*4-4]\n"); \8453 + fprintf (STREAM, "\tmv r3, r31\n"); \8454 + fprintf (STREAM, "\tbr! r1\n"); \8455 + fprintf (STREAM, "\tnop!\n"); \8456 + fprintf (STREAM, "\t.set nor1\n"); \8457 + } \8458 + else if (TARGET_SCORE3) \8459 + { \8460 + fprintf (STREAM, "\t.set r1\n"); \8461 + fprintf (STREAM, "\tmv! r31, r3\n"); \8462 + fprintf (STREAM, "\tnop!\n"); \8463 + fprintf (STREAM, "\tbl nextinsn\n"); \8464 + fprintf (STREAM, "nextinsn:\n"); \8465 + fprintf (STREAM, "\tlw! r1, [r3, 6*4-8]\n"); \8466 + fprintf (STREAM, "\tnop!\n"); \8467 + fprintf (STREAM, "\tlw r23, [r3, 6*4-4]\n"); \8468 + fprintf (STREAM, "\tmv! r3, r31\n"); \8469 + fprintf (STREAM, "\tnop!\n"); \8470 + fprintf (STREAM, "\tbr! r1\n"); \8471 + fprintf (STREAM, "\tnop!\n"); \8472 + fprintf (STREAM, "\t.set nor1\n"); \8473 + } \8474 + } while (0)8475 8476 /* Trampolines for Nested Functions. */8477 #define TRAMPOLINE_INSNS 68478 @@ -765,17 +829,23 @@8479 /* Output of Uninitialized Variables. */8480 /* This says how to define a global common symbol. */8481 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGN) \8482 - score_declare_object (STREAM, NAME, "\n\t.comm\t", \8483 - ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n", \8484 - SIZE, ALIGN / BITS_PER_UNIT);8485 + do { \8486 + fputs ("\n\t.comm\t", STREAM); \8487 + assemble_name (STREAM, NAME); \8488 + fprintf (STREAM, " , " HOST_WIDE_INT_PRINT_UNSIGNED ", %u\n", \8489 + SIZE, ALIGN / BITS_PER_UNIT); \8490 + } while (0)8491 8492 /* This says how to define a local common symbol (i.e., not visible to8493 linker). */8494 #undef ASM_OUTPUT_ALIGNED_LOCAL8495 -#define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \8496 - score_declare_object (STREAM, NAME, "\n\t.lcomm\t", \8497 - ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n", \8498 - SIZE, ALIGN / BITS_PER_UNIT);8499 +#define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \8500 + do { \8501 + fputs ("\n\t.lcomm\t", STREAM); \8502 + assemble_name (STREAM, NAME); \8503 + fprintf (STREAM, " , " HOST_WIDE_INT_PRINT_UNSIGNED ", %u\n", \8504 + SIZE, ALIGN / BITS_PER_UNIT); \8505 + } while (0)8506 8507 /* Globalizing directive for a label. */8508 #define GLOBAL_ASM_OP "\t.globl\t"8509 @@ -790,8 +860,11 @@8510 #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL)8511 8512 #undef ASM_DECLARE_OBJECT_NAME8513 -#define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \8514 - score_declare_object (STREAM, NAME, "", ":\n", 0)8515 +#define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \8516 + do { \8517 + assemble_name (STREAM, NAME); \8518 + fprintf (STREAM, ":\n"); \8519 + } while (0)8520 8521 /* This says how to output an external. It would be possible not to8522 output anything and let undefined symbol become external. However8523 @@ -808,7 +881,7 @@8524 8525 /* Local compiler-generated symbols must have a prefix that the assembler8526 understands. */8527 -#define LOCAL_LABEL_PREFIX "."8528 +#define LOCAL_LABEL_PREFIX (TARGET_SCORE7 ? "." : "$")8529 8530 #undef ASM_GENERATE_INTERNAL_LABEL8531 #define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \8532 @@ -859,32 +932,88 @@8533 #define USER_LABEL_PREFIX ""8534 8535 /* This is how to output an insn to push a register on the stack. */8536 -#define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \8537 - do { \8538 - fprintf (STREAM, "\tpush! %s,[%s]\n", \8539 - reg_names[REGNO], \8540 - reg_names[STACK_POINTER_REGNUM]); \8541 +#define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \8542 + do { \8543 + if (TARGET_SCORE7) \8544 + fprintf (STREAM, "\tpush! %s,[%s]\n", \8545 + reg_names[REGNO], \8546 + reg_names[STACK_POINTER_REGNUM]); \8547 + else if (TARGET_SCORE3) \8548 + fprintf (STREAM, "\tpush!\t%s\n", \8549 + reg_names[REGNO]); \8550 } while (0)8551 8552 /* This is how to output an insn to pop a register from the stack. */8553 -#define ASM_OUTPUT_REG_POP(STREAM, REGNO) \8554 - do { \8555 - fprintf (STREAM, "\tpop! %s,[%s]\n", \8556 - reg_names[REGNO], \8557 - reg_names[STACK_POINTER_REGNUM]); \8558 +#define ASM_OUTPUT_REG_POP(STREAM, REGNO) \8559 + do { \8560 + if (TARGET_SCORE7) \8561 + fprintf (STREAM, "\tpop! %s,[%s]\n", \8562 + reg_names[REGNO], \8563 + reg_names[STACK_POINTER_REGNUM]); \8564 + else if (TARGET_SCORE3) \8565 + fprintf (STREAM, "\tpop!\t%s\n", \8566 + reg_names[REGNO]); \8567 } while (0)8568 8569 /* Output of Dispatch Tables. */8570 /* This is how to output an element of a case-vector. We can make the8571 entries PC-relative in GP-relative when .gp(d)word is supported. */8572 -#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \8573 +#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \8574 + do { \8575 + if (TARGET_SCORE7) \8576 + if (flag_pic) \8577 + fprintf (STREAM, "\t.gpword %sL%d\n", LOCAL_LABEL_PREFIX, VALUE); \8578 + else \8579 + fprintf (STREAM, "\t.word %sL%d\n", LOCAL_LABEL_PREFIX, VALUE); \8580 + else if (TARGET_SCORE3) \8581 + { \8582 + switch (GET_MODE(BODY)) \8583 + { \8584 + case QImode: /* TBB */ \8585 + asm_fprintf (STREAM, "\t.byte\t(%LL%d-%LL%d_tbb)/2\n", \8586 + VALUE, REL); \8587 + break; \8588 + case HImode: /* TBH */ \8589 + asm_fprintf (STREAM, "\t.2byte\t(%LL%d-%LL%d_tbb)/2\n", \8590 + VALUE, REL); \8591 + break; \8592 + case SImode: \8593 + if (flag_pic) \8594 + fprintf (STREAM, "\t.gpword %sL%d\n", LOCAL_LABEL_PREFIX, VALUE); \8595 + else \8596 + fprintf (STREAM, "\t.word %sL%d\n", LOCAL_LABEL_PREFIX, VALUE); \8597 + break; \8598 + default: \8599 + gcc_unreachable(); \8600 + } \8601 + } \8602 + } while (0)8603 +8604 +/* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */8605 +#define ADDR_VEC_ALIGN(JUMPTABLE) (GET_MODE (PATTERN (JUMPTABLE)) == SImode ? 2 \8606 + : GET_MODE (PATTERN (JUMPTABLE)) == HImode ? 1 : 0)8607 +8608 +/* This is how to output a label which precedes a jumptable. Since8609 + Score3 instructions are 2 bytes, we may need explicit alignment here. */8610 +#undef ASM_OUTPUT_CASE_LABEL8611 +#define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \8612 do { \8613 - if (flag_pic) \8614 - fprintf (STREAM, "\t.gpword %sL%d\n", LOCAL_LABEL_PREFIX, VALUE); \8615 - else \8616 - fprintf (STREAM, "\t.word %sL%d\n", LOCAL_LABEL_PREFIX, VALUE); \8617 + if ((TARGET_SCORE7) && GET_MODE (PATTERN (JUMPTABLE)) == SImode) \8618 + ASM_OUTPUT_ALIGN (FILE, 2); \8619 + (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \8620 } while (0)8621 8622 +/* Specify the machine mode that this machine uses8623 + for the index in the tablejump instruction. */8624 +#define CASE_VECTOR_MODE SImode8625 +8626 +#define CASE_VECTOR_PC_RELATIVE (TARGET_SCORE3)8627 +8628 +#define CASE_VECTOR_SHORTEN_MODE(min, max, body) \8629 + ((min < 0 || max >= 0x2000 || TARGET_SCORE7) ? SImode \8630 + : (max >= 0x200) ? HImode \8631 + : QImode)8632 +8633 /* This is how to output an element of a case-vector that is absolute. */8634 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \8635 fprintf (STREAM, "\t.word %sL%d\n", LOCAL_LABEL_PREFIX, VALUE)8636 @@ -927,10 +1056,6 @@8637 /* The DWARF 2 CFA column which tracks the return address. */8638 #define DWARF_FRAME_RETURN_COLUMN 38639 8640 -/* Specify the machine mode that this machine uses8641 - for the index in the tablejump instruction. */8642 -#define CASE_VECTOR_MODE SImode8643 -8644 /* Define if operations between registers always perform the operation8645 on the full register even if a narrower mode is specified. */8646 #define WORD_REGISTER_OPERATIONS8647 diff -Naur gcc-4.2.2.orig/gcc/config/score/score.md gcc-4.2.2/gcc/config/score/score.md8648 --- gcc-4.2.2.orig/gcc/config/score/score.md 2007-09-01 08:28:30.000000000 -07008649 +++ gcc-4.2.2/gcc/config/score/score.md 2007-10-17 23:24:34.000000000 -07008650 @@ -38,7 +38,6 @@8651 ; tce transfer to hi/lo registers8652 ; fsr transfer from special registers8653 ; tsr transfer to special registers8654 -; pseudo pseudo instruction8655 8656 (define_constants8657 [(CC_REGNUM 33)8658 @@ -73,19 +72,19 @@8659 (SFFS 10)])8660 8661 (define_attr "type"8662 - "unknown,branch,jump,call,load,store,cmp,arith,move,const,nop,mul,div,cndmv,fce,tce,fsr,tsr,fcr,tcr,pseudo"8663 + "unknown,branch,jump,call,load,store,cmp,arith,move,const,nop,mul,div,cndmv,fce,tce,fsr,tsr,fcr,tcr"8664 (const_string "unknown"))8665 8666 -(define_attr "mode" "unknown,none,QI,HI,SI,DI"8667 +(define_attr "mode" "unknown,QI,HI,SI,DI"8668 (const_string "unknown"))8669 8670 +(define_attr "length" "" (const_int 4))8671 +8672 (define_attr "up_c" "yes,no"8673 (const_string "no"))8674 8675 -(include "score7.md")8676 +(include "score-generic.md")8677 (include "predicates.md")8678 -(include "misc.md")8679 -(include "mac.md")8680 8681 (define_expand "movqi"8682 [(set (match_operand:QI 0 "nonimmediate_operand")8683 @@ -99,25 +98,49 @@8684 }8685 })8686 8687 -(define_insn "*movqi_insns"8688 +(define_insn "*movqi_insns_score7"8689 + [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,d,*x,d,*a")8690 + (match_operand:QI 1 "general_operand" "i,d,m,d,*x,d,*a,d"))]8691 + "(!MEM_P (operands[0]) || register_operand (operands[1], QImode))8692 + && (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"8693 +{8694 + switch (which_alternative)8695 + {8696 + case 0: return score_limm (operands);8697 + case 1: return score_move (operands);8698 + case 2: return score_linsn (operands, SCORE_BYTE, false);8699 + case 3: return score_sinsn (operands, SCORE_BYTE);8700 + case 4: return TARGET_SCORE7D ? \"mf%1%S0 %0\" : \"mf%1 %0\";8701 + case 5: return TARGET_SCORE7D ? \"mt%0%S1 %1\" : \"mt%0 %1\";8702 + case 6: return \"mfsr\t%0, %1\";8703 + case 7: return \"mtsr\t%1, %0\";8704 + default: gcc_unreachable ();8705 + }8706 +}8707 + [(set_attr "type" "arith,move,load,store,fce,tce,fsr,tsr")8708 + (set_attr "mode" "QI")])8709 +8710 +(define_insn "*movqi_insns_score3"8711 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,d,*x,d,*a")8712 (match_operand:QI 1 "general_operand" "i,d,m,d,*x,d,*a,d"))]8713 - "!MEM_P (operands[0]) || register_operand (operands[1], QImode)"8714 + "(!MEM_P (operands[0]) || register_operand (operands[1], QImode))8715 + && (TARGET_SCORE3)"8716 {8717 switch (which_alternative)8718 {8719 - case 0: return mdp_limm (operands);8720 - case 1: return mdp_move (operands);8721 - case 2: return mdp_linsn (operands, MDA_BYTE, false);8722 - case 3: return mdp_sinsn (operands, MDA_BYTE);8723 - case 4: return TARGET_MAC ? \"mf%1%S0 %0\" : \"mf%1 %0\";8724 - case 5: return TARGET_MAC ? \"mt%0%S1 %1\" : \"mt%0 %1\";8725 - case 6: return \"mfsr %0, %1\";8726 - case 7: return \"mtsr %1, %0\";8727 + case 0: return score_limm (operands);8728 + case 1: return \"mv!\t%0, %1\";8729 + case 2: return score_linsn (operands, SCORE_BYTE, false);8730 + case 3: return score_sinsn (operands, SCORE_BYTE);8731 + case 4: return TARGET_SCORE3D ? \"mf%1%S0\t%0\" : \"mf%1\t%0\";8732 + case 5: return TARGET_SCORE3D ? \"mt%0%S1\t%1\" : \"mt%0\t%1\";8733 + case 6: return \"mfsr\t%0, %1\";8734 + case 7: return \"mtsr\t%1, %0\";8735 default: gcc_unreachable ();8736 }8737 }8738 [(set_attr "type" "arith,move,load,store,fce,tce,fsr,tsr")8739 + (set_attr "length" "6,2,6,6,4,4,4,4")8740 (set_attr "mode" "QI")])8741 8742 (define_expand "movhi"8743 @@ -132,25 +155,49 @@8744 }8745 })8746 8747 -(define_insn "*movhi_insns"8748 +(define_insn "*movhi_insns_score7"8749 + [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,d,*x,d,*a")8750 + (match_operand:HI 1 "general_operand" "i,d,m,d,*x,d,*a,d"))]8751 + "(!MEM_P (operands[0]) || register_operand (operands[1], HImode))8752 + && (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"8753 +{8754 + switch (which_alternative)8755 + {8756 + case 0: return score_limm (operands);8757 + case 1: return score_move (operands);8758 + case 2: return score_linsn (operands, SCORE_HWORD, false);8759 + case 3: return score_sinsn (operands, SCORE_HWORD);8760 + case 4: return TARGET_SCORE7D ? \"mf%1%S0 %0\" : \"mf%1 %0\";8761 + case 5: return TARGET_SCORE7D ? \"mt%0%S1 %1\" : \"mt%0 %1\";8762 + case 6: return \"mfsr\t%0, %1\";8763 + case 7: return \"mtsr\t%1, %0\";8764 + default: gcc_unreachable ();8765 + }8766 +}8767 + [(set_attr "type" "arith,move,load,store,fce,tce,fsr,tsr")8768 + (set_attr "mode" "HI")])8769 +8770 +(define_insn "*movhi_insns_score3"8771 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,d,*x,d,*a")8772 (match_operand:HI 1 "general_operand" "i,d,m,d,*x,d,*a,d"))]8773 - "!MEM_P (operands[0]) || register_operand (operands[1], HImode)"8774 + "(!MEM_P (operands[0]) || register_operand (operands[1], HImode))8775 + && (TARGET_SCORE3)"8776 {8777 switch (which_alternative)8778 {8779 - case 0: return mdp_limm (operands);8780 - case 1: return mdp_move (operands);8781 - case 2: return mdp_linsn (operands, MDA_HWORD, false);8782 - case 3: return mdp_sinsn (operands, MDA_HWORD);8783 - case 4: return TARGET_MAC ? \"mf%1%S0 %0\" : \"mf%1 %0\";8784 - case 5: return TARGET_MAC ? \"mt%0%S1 %1\" : \"mt%0 %1\";8785 - case 6: return \"mfsr %0, %1\";8786 - case 7: return \"mtsr %1, %0\";8787 + case 0: return score_limm (operands);8788 + case 1: return \"mv!\t%0, %1\";8789 + case 2: return score_linsn (operands, SCORE_HWORD, false);8790 + case 3: return score_sinsn (operands, SCORE_HWORD);8791 + case 4: return TARGET_SCORE3D ? \"mf%1%S0\t%0\" : \"mf%1\t%0\";8792 + case 5: return TARGET_SCORE3D ? \"mt%0%S1\t%1\" : \"mt%0\t%1\";8793 + case 6: return \"mfsr\t%0, %1\";8794 + case 7: return \"mtsr\t%1, %0\";8795 default: gcc_unreachable ();8796 }8797 }8798 [(set_attr "type" "arith,move,load,store,fce,tce,fsr,tsr")8799 + (set_attr "length" "6,2,6,6,4,4,4,4")8800 (set_attr "mode" "HI")])8801 8802 (define_expand "movsi"8803 @@ -165,33 +212,62 @@8804 }8805 })8806 8807 -(define_insn "*movsi_insns"8808 +(define_insn "*movsi_insns_score7"8809 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,m,d,*x,d,*a,d,*c")8810 (match_operand:SI 1 "general_operand" "i,d,m,d,*x,d,*a,d,*c,d"))]8811 - "!MEM_P (operands[0]) || register_operand (operands[1], SImode)"8812 + "(!MEM_P (operands[0]) || register_operand (operands[1], SImode))8813 + && (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"8814 {8815 switch (which_alternative)8816 {8817 case 0:8818 if (GET_CODE (operands[1]) != CONST_INT)8819 - return \"la %0, %1\";8820 + return \"la\t%0, %1\";8821 else8822 - return mdp_limm (operands);8823 - case 1: return mdp_move (operands);8824 - case 2: return mdp_linsn (operands, MDA_WORD, false);8825 - case 3: return mdp_sinsn (operands, MDA_WORD);8826 - case 4: return TARGET_MAC ? \"mf%1%S0 %0\" : \"mf%1 %0\";8827 - case 5: return TARGET_MAC ? \"mt%0%S1 %1\" : \"mt%0 %1\";8828 - case 6: return \"mfsr %0, %1\";8829 - case 7: return \"mtsr %1, %0\";8830 - case 8: return \"mfcr %0, %1\";8831 - case 9: return \"mtcr %1, %0\";8832 + return score_limm (operands);8833 + case 1: return score_move (operands);8834 + case 2: return score_linsn (operands, SCORE_WORD, false);8835 + case 3: return score_sinsn (operands, SCORE_WORD);8836 + case 4: return TARGET_SCORE7D ? \"mf%1%S0 %0\" : \"mf%1 %0\";8837 + case 5: return TARGET_SCORE7D ? \"mt%0%S1 %1\" : \"mt%0 %1\";8838 + case 6: return \"mfsr\t%0, %1\";8839 + case 7: return \"mtsr\t%1, %0\";8840 + case 8: return \"mfcr\t%0, %1\";8841 + case 9: return \"mtcr\t%1, %0\";8842 default: gcc_unreachable ();8843 }8844 }8845 [(set_attr "type" "arith,move,load,store,fce,tce,fsr,tsr,fcr,tcr")8846 (set_attr "mode" "SI")])8847 8848 +(define_insn "*movsi_insns_score3"8849 + [(set (match_operand:SI 0 "nonimmediate_operand" "=ed,e,d,d,m,d,*x,d,*a")8850 + (match_operand:SI 1 "general_operand" "i,e,d,m,d,*x,d,*a,d"))]8851 + "(!MEM_P (operands[0]) || register_operand (operands[1], SImode))8852 + && (TARGET_SCORE3)"8853 +{8854 + switch (which_alternative)8855 + {8856 + case 0:8857 + if (GET_CODE (operands[1]) != CONST_INT)8858 + return \"ldi48\t%0, %1\";8859 + else8860 + return score_limm (operands);8861 + case 1: return \"mv!\t%0, %1\";8862 + case 2: return \"mv!\t%0, %1\";8863 + case 3: return score_linsn (operands, SCORE_WORD, false);8864 + case 4: return score_sinsn (operands, SCORE_WORD);8865 + case 5: return TARGET_SCORE3D ? \"mf%1%S0\t%0\" : \"mf%1\t%0\";8866 + case 6: return TARGET_SCORE3D ? \"mt%0%S1\t%1\" : \"mt%0\t%1\";8867 + case 7: return \"mfsr\t%0, %1\";8868 + case 8: return \"mtsr\t%1, %0\";8869 + default: gcc_unreachable ();8870 + }8871 +}8872 + [(set_attr "type" "arith,move,move,load,store,fce,tce,fsr,tsr")8873 + (set_attr "length" "6,2,2,6,6,4,4,4,4")8874 + (set_attr "mode" "SI")])8875 +8876 (define_insn_and_split "movdi"8877 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,d,*x")8878 (match_operand:DI 1 "general_operand" "i,d,m,d,*x,d"))]8879 @@ -200,7 +276,7 @@8880 "reload_completed"8881 [(const_int 0)]8882 {8883 - mds_movdi (operands);8884 + score_movdi (operands);8885 DONE;8886 })8887 8888 @@ -216,21 +292,41 @@8889 }8890 })8891 8892 -(define_insn "*movsf_insns"8893 +(define_insn "*movsf_insns_score7"8894 + [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,d,m")8895 + (match_operand:SF 1 "general_operand" "i,d,m,d"))]8896 + "(!MEM_P (operands[0]) || register_operand (operands[1], SFmode))8897 + && (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"8898 +{8899 + switch (which_alternative)8900 + {8901 + case 0: return \"li\t%0, %D1\";;8902 + case 1: return score_move (operands);8903 + case 2: return score_linsn (operands, SCORE_WORD, false);8904 + case 3: return score_sinsn (operands, SCORE_WORD);8905 + default: gcc_unreachable ();8906 + }8907 +}8908 + [(set_attr "type" "arith,move,load,store")8909 + (set_attr "mode" "SI")])8910 +8911 +(define_insn "*movsf_insns_score3"8912 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,d,m")8913 (match_operand:SF 1 "general_operand" "i,d,m,d"))]8914 - "!MEM_P (operands[0]) || register_operand (operands[1], SFmode)"8915 + "(!MEM_P (operands[0]) || register_operand (operands[1], SFmode))8916 + && (TARGET_SCORE3)"8917 {8918 switch (which_alternative)8919 {8920 - case 0: return \"li %0, %D1\";;8921 - case 1: return mdp_move (operands);8922 - case 2: return mdp_linsn (operands, MDA_WORD, false);8923 - case 3: return mdp_sinsn (operands, MDA_WORD);8924 + case 0: return \"li\t%0, %D1\";8925 + case 1: return \"mv!\t%0, %1\";8926 + case 2: return score_linsn (operands, SCORE_WORD, false);8927 + case 3: return score_sinsn (operands, SCORE_WORD);8928 default: gcc_unreachable ();8929 }8930 }8931 [(set_attr "type" "arith,move,load,store")8932 + (set_attr "length" "4,2,6,6")8933 (set_attr "mode" "SI")])8934 8935 (define_insn_and_split "movdf"8936 @@ -241,51 +337,101 @@8937 "reload_completed"8938 [(const_int 0)]8939 {8940 - mds_movdi (operands);8941 + score_movdi (operands);8942 DONE;8943 })8944 8945 -(define_insn "addsi3"8946 +(define_expand "addsi3"8947 + [(set (match_operand:SI 0 "score_register_operand" )8948 + (plus:SI (match_operand:SI 1 "score_register_operand")8949 + (match_operand:SI 2 "arith_operand")))]8950 + ""8951 + ""8952 +)8953 +8954 +(define_insn "*addsi3_score7"8955 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")8956 (plus:SI (match_operand:SI 1 "register_operand" "0,0,d,d")8957 (match_operand:SI 2 "arith_operand" "I,L,N,d")))]8958 - ""8959 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"8960 +{8961 + switch (which_alternative)8962 + {8963 + case 0: return \"addis\t%0, %U2\";8964 + case 1: return score_select_add_imm (operands, false);8965 + case 2: return \"addri\t%0, %1, %c2\";8966 + case 3: return score_select (operands, "add", true, "", false);8967 + default: gcc_unreachable ();8968 + }8969 +}8970 + [(set_attr "type" "arith")8971 + (set_attr "mode" "SI")])8972 +8973 +(define_insn "*addsi3_score3"8974 + [(set (match_operand:SI 0 "score_register_operand" "=d,d,d,d")8975 + (plus:SI (match_operand:SI 1 "score_register_operand" "%0,0,d,d")8976 + (match_operand:SI 2 "arith_operand" "I,L,N,d")))]8977 + "(TARGET_SCORE3)"8978 {8979 switch (which_alternative)8980 {8981 - case 0: return \"addis %0, %U2\";8982 - case 1: return mdp_select_add_imm (operands, false);8983 - case 2: return \"addri %0, %1, %c2\";8984 - case 3: return mdp_select (operands, "add", true, "", false);8985 + case 0: return \"addis\t%0, %U2\";8986 + case 1: return score_select_add_imm (operands, false);8987 + case 2: return \"addri\t%0, %1, %c2\";8988 + case 3: return score_select (operands, "add", true, "", false);8989 default: gcc_unreachable ();8990 }8991 }8992 [(set_attr "type" "arith")8993 + (set_attr "length" "4,4,4,4")8994 (set_attr "mode" "SI")])8995 8996 -(define_insn "*addsi3_cmp"8997 +(define_insn "*addsi3_cmp_score7"8998 [(set (reg:CC_NZ CC_REGNUM)8999 (compare:CC_NZ (plus:SI9000 (match_operand:SI 1 "register_operand" "0,0,d,d")9001 (match_operand:SI 2 "arith_operand" "I,L,N,d"))9002 (const_int 0)))9003 (clobber (match_scratch:SI 0 "=d,d,d,d"))]9004 - ""9005 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"9006 +{9007 + switch (which_alternative)9008 + {9009 + case 0: return \"addis.c\t%0, %U2\";9010 + case 1: return score_select_add_imm (operands, true);9011 + case 2: return \"addri.c\t%0, %1, %c2\";9012 + case 3: return score_select (operands, "add", true, "", true);9013 + default: gcc_unreachable ();9014 + }9015 +}9016 + [(set_attr "type" "arith")9017 + (set_attr "up_c" "yes")9018 + (set_attr "mode" "SI")])9019 +9020 +(define_insn "*addsi3_cmp_score3"9021 + [(set (reg:CC_NZ CC_REGNUM)9022 + (compare:CC_NZ (plus:SI9023 + (match_operand:SI 1 "score_register_operand" "0,0,d,d")9024 + (match_operand:SI 2 "arith_operand" "I,L,N,d"))9025 + (const_int 0)))9026 + (clobber (match_scratch:SI 0 "=d,d,d,d"))]9027 + "(TARGET_SCORE3)"9028 {9029 switch (which_alternative)9030 {9031 - case 0: return \"addis.c %0, %U2\";9032 - case 1: return mdp_select_add_imm (operands, true);9033 - case 2: return \"addri.c %0, %1, %c2\";9034 - case 3: return mdp_select (operands, "add", true, "", true);9035 + case 0: return \"addis.c\t%0, %U2\";9036 + case 1: return score_select_add_imm (operands, true);9037 + case 2: return \"addri.c\t%0, %1, %c2\";9038 + case 3: return score_select (operands, "add", true, "", true);9039 default: gcc_unreachable ();9040 }9041 }9042 [(set_attr "type" "arith")9043 + (set_attr "length" "4,4,4,4")9044 (set_attr "up_c" "yes")9045 (set_attr "mode" "SI")])9046 9047 -(define_insn "*addsi3_ucc"9048 +(define_insn "*addsi3_ucc_score7"9049 [(set (reg:CC_NZ CC_REGNUM)9050 (compare:CC_NZ (plus:SI9051 (match_operand:SI 1 "register_operand" "0,0,d,d")9052 @@ -293,55 +439,140 @@9053 (const_int 0)))9054 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")9055 (plus:SI (match_dup 1) (match_dup 2)))]9056 - ""9057 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"9058 +{9059 + switch (which_alternative)9060 + {9061 + case 0: return \"addis.c\t%0, %U2\";9062 + case 1: return score_select_add_imm (operands, true);9063 + case 2: return \"addri.c\t%0, %1, %c2\";9064 + case 3: return score_select (operands, "add", true, "", true);9065 + default: gcc_unreachable ();9066 + }9067 +}9068 + [(set_attr "type" "arith")9069 + (set_attr "up_c" "yes")9070 + (set_attr "mode" "SI")])9071 +9072 +(define_insn "*addsi3_ucc_score3"9073 + [(set (reg:CC_NZ CC_REGNUM)9074 + (compare:CC_NZ (plus:SI9075 + (match_operand:SI 1 "score_register_operand" "0,0,d,d")9076 + (match_operand:SI 2 "arith_operand" "I,L,N,d"))9077 + (const_int 0)))9078 + (set (match_operand:SI 0 "score_register_operand" "=d,d,d,d")9079 + (plus:SI (match_dup 1) (match_dup 2)))]9080 + "(TARGET_SCORE3)"9081 {9082 switch (which_alternative)9083 {9084 - case 0: return \"addis.c %0, %U2\";9085 - case 1: return mdp_select_add_imm (operands, true);9086 - case 2: return \"addri.c %0, %1, %c2\";9087 - case 3: return mdp_select (operands, "add", true, "", true);9088 + case 0: return \"addis.c\t%0, %U2\";9089 + case 1: return score_select_add_imm (operands, true);9090 + case 2: return \"addri.c\t%0, %1, %c2\";9091 + case 3: return score_select (operands, "add", true, "", true);9092 default: gcc_unreachable ();9093 }9094 }9095 [(set_attr "type" "arith")9096 + (set_attr "length" "4,4,4,4")9097 (set_attr "up_c" "yes")9098 (set_attr "mode" "SI")])9099 9100 -(define_insn "adddi3"9101 +(define_expand "adddi3"9102 + [(parallel9103 + [(set (match_operand:DI 0 "score_register_operand")9104 + (plus:DI (match_operand:DI 1 "score_register_operand")9105 + (match_operand:DI 2 "score_register_operand")))9106 + (clobber (reg:CC CC_REGNUM))])]9107 + ""9108 + ""9109 +)9110 +9111 +(define_insn "*adddi3_score7"9112 [(set (match_operand:DI 0 "register_operand" "=e,d")9113 (plus:DI (match_operand:DI 1 "register_operand" "0,d")9114 (match_operand:DI 2 "register_operand" "e,d")))9115 (clobber (reg:CC CC_REGNUM))]9116 - ""9117 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"9118 "@9119 add! %L0, %L2\;addc! %H0, %H29120 add.c %L0, %L1, %L2\;addc %H0, %H1, %H2"9121 [(set_attr "type" "arith")9122 (set_attr "mode" "DI")])9123 9124 -(define_insn "subsi3"9125 +(define_insn "*adddi3_score3"9126 + [(set (match_operand:DI 0 "score_register_operand" "=d")9127 + (plus:DI (match_operand:DI 1 "score_register_operand" "d")9128 + (match_operand:DI 2 "score_register_operand" "d")))9129 + (clobber (reg:CC CC_REGNUM))]9130 + "(TARGET_SCORE3)"9131 + "add.c\t%L0, %L1, %L2\;addc\t%H0, %H1, %H2"9132 + [(set_attr "type" "arith")9133 + (set_attr "length" "8")9134 + (set_attr "mode" "DI")])9135 +9136 +(define_expand "subsi3"9137 + [(set (match_operand:SI 0 "score_register_operand")9138 + (minus:SI (match_operand:SI 1 "score_register_operand")9139 + (match_operand:SI 2 "score_register_operand")))]9140 + ""9141 + ""9142 +)9143 +9144 +(define_insn "*subsi3_score7"9145 [(set (match_operand:SI 0 "register_operand" "=d")9146 (minus:SI (match_operand:SI 1 "register_operand" "d")9147 (match_operand:SI 2 "register_operand" "d")))]9148 - ""9149 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"9150 +{9151 + return score_select (operands, "sub", false, "", false);9152 +}9153 + [(set_attr "type" "arith")9154 + (set_attr "mode" "SI")])9155 +9156 +(define_insn "*subsi3_score3"9157 + [(set (match_operand:SI 0 "score_register_operand" "=e,d")9158 + (minus:SI (match_operand:SI 1 "score_register_operand" "0,d")9159 + (match_operand:SI 2 "score_register_operand" "e,d")))]9160 + "(TARGET_SCORE3)"9161 {9162 - return mdp_select (operands, "sub", false, "", false);9163 + switch (which_alternative)9164 + {9165 + case 0: return \"sub!\t%0, %2\";9166 + case 1: return score_select (operands, "sub", false, "", false);9167 + default: gcc_unreachable ();9168 + }9169 }9170 [(set_attr "type" "arith")9171 + (set_attr "length" "2,4")9172 (set_attr "mode" "SI")])9173 9174 -(define_insn "*subsi3_cmp"9175 +(define_insn "*subsi3_cmp_score7"9176 [(set (reg:CC_NZ CC_REGNUM)9177 (compare:CC_NZ (minus:SI (match_operand:SI 1 "register_operand" "d")9178 (match_operand:SI 2 "register_operand" "d"))9179 (const_int 0)))9180 (clobber (match_scratch:SI 0 "=d"))]9181 - ""9182 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"9183 +{9184 + return score_select (operands, "sub", false, "", true);9185 +}9186 + [(set_attr "type" "arith")9187 + (set_attr "up_c" "yes")9188 + (set_attr "mode" "SI")])9189 +9190 +(define_insn "*subsi3_cmp_score3"9191 + [(set (reg:CC_NZ CC_REGNUM)9192 + (compare:CC_NZ (minus:SI (match_operand:SI 1 "score_register_operand" "d")9193 + (match_operand:SI 2 "score_register_operand" "d"))9194 + (const_int 0)))9195 + (clobber (match_scratch:SI 0 "=d"))]9196 + "(TARGET_SCORE3)"9197 {9198 - return mdp_select (operands, "sub", false, "", true);9199 + return score_select (operands, "sub", false, "", true);9200 }9201 [(set_attr "type" "arith")9202 + (set_attr "length" "4")9203 (set_attr "up_c" "yes")9204 (set_attr "mode" "SI")])9205 9206 @@ -359,86 +590,159 @@9207 9208 (define_insn "subsi3_ucc_pcmp"9209 [(parallel9210 - [(set (reg:CC CC_REGNUM)9211 - (compare:CC (match_operand:SI 1 "register_operand" "d")9212 - (match_operand:SI 2 "register_operand" "d")))9213 - (set (match_operand:SI 0 "register_operand" "=d")9214 - (minus:SI (match_dup 1) (match_dup 2)))])]9215 + [(set (reg:CC CC_REGNUM)9216 + (compare:CC (match_operand:SI 1 "score_register_operand" "d")9217 + (match_operand:SI 2 "score_register_operand" "d")))9218 + (set (match_operand:SI 0 "score_register_operand" "=d")9219 + (minus:SI (match_dup 1) (match_dup 2)))])]9220 ""9221 {9222 - return mdp_select (operands, "sub", false, "", true);9223 + return score_select (operands, "sub", false, "", true);9224 }9225 [(set_attr "type" "arith")9226 + (set_attr "length" "4")9227 (set_attr "up_c" "yes")9228 (set_attr "mode" "SI")])9229 9230 (define_insn "subsi3_ucc"9231 [(set (reg:CC_NZ CC_REGNUM)9232 - (compare:CC_NZ (minus:SI (match_operand:SI 1 "register_operand" "d")9233 - (match_operand:SI 2 "register_operand" "d"))9234 + (compare:CC_NZ (minus:SI (match_operand:SI 1 "score_register_operand" "d")9235 + (match_operand:SI 2 "score_register_operand" "d"))9236 (const_int 0)))9237 - (set (match_operand:SI 0 "register_operand" "=d")9238 + (set (match_operand:SI 0 "score_register_operand" "=d")9239 (minus:SI (match_dup 1) (match_dup 2)))]9240 ""9241 {9242 - return mdp_select (operands, "sub", false, "", true);9243 + return score_select (operands, "sub", false, "", true);9244 }9245 [(set_attr "type" "arith")9246 + (set_attr "length" "4")9247 (set_attr "up_c" "yes")9248 (set_attr "mode" "SI")])9249 9250 -(define_insn "subdi3"9251 +(define_expand "subdi3"9252 + [(parallel9253 + [(set (match_operand:DI 0 "score_register_operand")9254 + (minus:DI (match_operand:DI 1 "score_register_operand")9255 + (match_operand:DI 2 "score_register_operand")))9256 + (clobber (reg:CC CC_REGNUM))])]9257 + ""9258 + ""9259 +)9260 +9261 +(define_insn "*subdi3_score7"9262 [(set (match_operand:DI 0 "register_operand" "=e,d")9263 (minus:DI (match_operand:DI 1 "register_operand" "0,d")9264 (match_operand:DI 2 "register_operand" "e,d")))9265 (clobber (reg:CC CC_REGNUM))]9266 - ""9267 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"9268 "@9269 sub! %L0, %L2\;subc %H0, %H1, %H29270 sub.c %L0, %L1, %L2\;subc %H0, %H1, %H2"9271 [(set_attr "type" "arith")9272 (set_attr "mode" "DI")])9273 9274 -(define_insn "andsi3"9275 +(define_insn "*subdi3_score3"9276 + [(set (match_operand:DI 0 "score_register_operand" "=d")9277 + (minus:DI (match_operand:DI 1 "score_register_operand" "d")9278 + (match_operand:DI 2 "score_register_operand" "d")))9279 + (clobber (reg:CC CC_REGNUM))]9280 + "(TARGET_SCORE3)"9281 + "sub.c\t%L0, %L1, %L2\;subc\t%H0, %H1, %H2"9282 + [(set_attr "type" "arith")9283 + (set_attr "length" "8")9284 + (set_attr "mode" "DI")])9285 +9286 +(define_expand "andsi3"9287 + [(set (match_operand:SI 0 "score_register_operand")9288 + (and:SI (match_operand:SI 1 "score_register_operand")9289 + (match_operand:SI 2 "arith_operand")))]9290 + ""9291 + ""9292 +)9293 +9294 +(define_insn "*andsi3_score7"9295 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")9296 (and:SI (match_operand:SI 1 "register_operand" "0,0,d,d")9297 (match_operand:SI 2 "arith_operand" "I,K,M,d")))]9298 - ""9299 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"9300 {9301 switch (which_alternative)9302 {9303 - case 0: return \"andis %0, %U2\";9304 - case 1: return \"andi %0, %c2";9305 - case 2: return \"andri %0, %1, %c2\";9306 - case 3: return mdp_select (operands, "and", true, "", false);9307 + case 0: return \"andis\t%0, %U2\";9308 + case 1: return \"andi\t%0, %c2";9309 + case 2: return \"andri\t%0, %1, %c2\";9310 + case 3: return score_select (operands, "and", true, "", false);9311 default: gcc_unreachable ();9312 }9313 }9314 [(set_attr "type" "arith")9315 (set_attr "mode" "SI")])9316 9317 -(define_insn "andsi3_cmp"9318 +(define_insn "*andsi3_score3"9319 + [(set (match_operand:SI 0 "score_register_operand" "=e,d,d,d,d")9320 + (and:SI (match_operand:SI 1 "score_register_operand" "%0,0,0,d,d")9321 + (match_operand:SI 2 "arith_operand" "e,I,K,M,d")))]9322 + "(TARGET_SCORE3)"9323 +{9324 + switch (which_alternative)9325 + {9326 + case 0: return \"and!\t%0, %2\";9327 + case 1: return \"andis\t%0, %U2\";9328 + case 2: return \"andi\t%0, %c2";9329 + case 3: return \"andri\t%0, %1, %c2\";9330 + case 4: return score_select (operands, "and", true, "", false);9331 + default: gcc_unreachable ();9332 + }9333 +}9334 + [(set_attr "type" "arith")9335 + (set_attr "length" "2,4,4,4,4")9336 + (set_attr "mode" "SI")])9337 +9338 +(define_insn "andsi3_cmp_score7"9339 [(set (reg:CC_NZ CC_REGNUM)9340 (compare:CC_NZ (and:SI (match_operand:SI 1 "register_operand" "0,0,0,d")9341 (match_operand:SI 2 "arith_operand" "I,K,M,d"))9342 (const_int 0)))9343 (clobber (match_scratch:SI 0 "=d,d,d,d"))]9344 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"9345 +{9346 + switch (which_alternative)9347 + {9348 + case 0: return \"andis.c\t%0, %U2\";9349 + case 1: return \"andi.c\t%0, %c2";9350 + case 2: return \"andri.c\t%0, %1, %c2\";9351 + case 3: return score_select (operands, "and", true, "", true);9352 + default: gcc_unreachable ();9353 + }9354 +}9355 + [(set_attr "type" "arith")9356 + (set_attr "up_c" "yes")9357 + (set_attr "mode" "SI")])9358 +9359 +(define_insn "andsi3_cmp_score3"9360 + [(set (reg:CC_NZ CC_REGNUM)9361 + (compare:CC_NZ (and:SI (match_operand:SI 1 "score_register_operand" "0,0,0,d")9362 + (match_operand:SI 2 "arith_operand" "I,K,M,d"))9363 + (const_int 0)))9364 + (clobber (match_scratch:SI 0 "=d,d,d,d"))]9365 ""9366 {9367 switch (which_alternative)9368 {9369 - case 0: return \"andis.c %0, %U2\";9370 - case 1: return \"andi.c %0, %c2";9371 - case 2: return \"andri.c %0, %1, %c2\";9372 - case 3: return mdp_select (operands, "and", true, "", true);9373 + case 0: return \"andis.c\t%0, %U2\";9374 + case 1: return \"andi.c\t%0, %c2";9375 + case 2: return \"andri.c\t%0, %1, %c2\";9376 + case 3: return score_select (operands, "and", true, "", true);9377 default: gcc_unreachable ();9378 }9379 }9380 [(set_attr "type" "arith")9381 + (set_attr "length" "4,4,4,4")9382 (set_attr "up_c" "yes")9383 (set_attr "mode" "SI")])9384 9385 -(define_insn "*andsi3_ucc"9386 +(define_insn "*andsi3_ucc_score7"9387 [(set (reg:CC_NZ CC_REGNUM)9388 (compare:CC_NZ (and:SI9389 (match_operand:SI 1 "register_operand" "0,0,d,d")9390 @@ -446,25 +750,50 @@9391 (const_int 0)))9392 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")9393 (and:SI (match_dup 1) (match_dup 2)))]9394 - ""9395 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"9396 +{9397 + switch (which_alternative)9398 + {9399 + case 0: return \"andis.c\t%0, %U2\";9400 + case 1: return \"andi.c\t%0, %c2";9401 + case 2: return \"andri.c\t%0, %1, %c2\";9402 + case 3: return score_select (operands, "and", true, "", true);9403 + default: gcc_unreachable ();9404 + }9405 +}9406 + [(set_attr "type" "arith")9407 + (set_attr "up_c" "yes")9408 + (set_attr "mode" "SI")])9409 +9410 +(define_insn "*andsi3_ucc_score3"9411 + [(set (reg:CC_NZ CC_REGNUM)9412 + (compare:CC_NZ (and:SI9413 + (match_operand:SI 1 "score_register_operand" "0,0,d,d")9414 + (match_operand:SI 2 "arith_operand" "I,K,M,d"))9415 + (const_int 0)))9416 + (set (match_operand:SI 0 "score_register_operand" "=d,d,d,d")9417 + (and:SI (match_dup 1) (match_dup 2)))]9418 + "(TARGET_SCORE3)"9419 {9420 switch (which_alternative)9421 {9422 - case 0: return \"andis.c %0, %U2\";9423 - case 1: return \"andi.c %0, %c2";9424 - case 2: return \"andri.c %0, %1, %c2\";9425 - case 3: return mdp_select (operands, "and", true, "", true);9426 + case 0: return \"andis.c\t%0, %U2\";9427 + case 1: return \"andi.c\t%0, %c2";9428 + case 2: return \"andri.c\t%0, %1, %c2\";9429 + case 3: return score_select (operands, "and", true, "", true);9430 default: gcc_unreachable ();9431 }9432 }9433 [(set_attr "type" "arith")9434 + (set_attr "length" "4,4,4,4")9435 (set_attr "up_c" "yes")9436 (set_attr "mode" "SI")])9437 9438 +9439 (define_insn_and_split "*zero_extract_andi"9440 [(set (reg:CC CC_REGNUM)9441 (compare:CC (zero_extract:SI9442 - (match_operand:SI 0 "register_operand" "d")9443 + (match_operand:SI 0 "score_register_operand" "d")9444 (match_operand:SI 1 "const_uimm5" "")9445 (match_operand:SI 2 "const_uimm5" ""))9446 (const_int 0)))]9447 @@ -473,29 +802,57 @@9448 ""9449 [(const_int 1)]9450 {9451 - mds_zero_extract_andi (operands);9452 + score_zero_extract_andi (operands);9453 DONE;9454 })9455 9456 -(define_insn "iorsi3"9457 +(define_expand "iorsi3"9458 + [(set (match_operand:SI 0 "score_register_operand")9459 + (ior:SI (match_operand:SI 1 "score_register_operand")9460 + (match_operand:SI 2 "arith_operand")))]9461 + ""9462 + ""9463 +)9464 +9465 +(define_insn "*iorsi3_score7"9466 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")9467 (ior:SI (match_operand:SI 1 "register_operand" "0,0,d,d")9468 (match_operand:SI 2 "arith_operand" "I,K,M,d")))]9469 - ""9470 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"9471 +{9472 + switch (which_alternative)9473 + {9474 + case 0: return \"oris\t%0, %U2\";9475 + case 1: return \"ori\t%0, %c2\";9476 + case 2: return \"orri\t%0, %1, %c2\";9477 + case 3: return score_select (operands, "or", true, "", false);9478 + default: gcc_unreachable ();9479 + }9480 +}9481 + [(set_attr "type" "arith")9482 + (set_attr "mode" "SI")])9483 +9484 +(define_insn "*iorsi3_score3"9485 + [(set (match_operand:SI 0 "score_register_operand" "=e,d,d,d,d")9486 + (ior:SI (match_operand:SI 1 "score_register_operand" "%0,0,0,d,d")9487 + (match_operand:SI 2 "arith_operand" "e,I,K,M,d")))]9488 + "(TARGET_SCORE3)"9489 {9490 switch (which_alternative)9491 {9492 - case 0: return \"oris %0, %U2\";9493 - case 1: return \"ori %0, %c2\";9494 - case 2: return \"orri %0, %1, %c2\";9495 - case 3: return mdp_select (operands, "or", true, "", false);9496 + case 0: return \"or!\t%0, %2\";9497 + case 1: return \"oris\t%0, %U2\";9498 + case 2: return \"ori\t%0, %c2\";9499 + case 3: return \"orri\t%0, %1, %c2\";9500 + case 4: return score_select (operands, "or", true, "", false);9501 default: gcc_unreachable ();9502 }9503 }9504 [(set_attr "type" "arith")9505 + (set_attr "length" "2,4,4,4,4")9506 (set_attr "mode" "SI")])9507 9508 -(define_insn "iorsi3_ucc"9509 +(define_insn "*iorsi3_ucc_score7"9510 [(set (reg:CC_NZ CC_REGNUM)9511 (compare:CC_NZ (ior:SI9512 (match_operand:SI 1 "register_operand" "0,0,d,d")9513 @@ -503,70 +860,155 @@9514 (const_int 0)))9515 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")9516 (ior:SI (match_dup 1) (match_dup 2)))]9517 - ""9518 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"9519 +{9520 + switch (which_alternative)9521 + {9522 + case 0: return \"oris.c\t%0, %U2\";9523 + case 1: return \"ori.c\t%0, %c2\";9524 + case 2: return \"orri.c\t%0, %1, %c2\";9525 + case 3: return score_select (operands, "or", true, "", true);9526 + default: gcc_unreachable ();9527 + }9528 +}9529 + [(set_attr "type" "arith")9530 + (set_attr "up_c" "yes")9531 + (set_attr "mode" "SI")])9532 +9533 +(define_insn "*iorsi3_ucc_score3"9534 + [(set (reg:CC_NZ CC_REGNUM)9535 + (compare:CC_NZ (ior:SI9536 + (match_operand:SI 1 "score_register_operand" "0,0,d,d")9537 + (match_operand:SI 2 "arith_operand" "I,K,M,d"))9538 + (const_int 0)))9539 + (set (match_operand:SI 0 "score_register_operand" "=d,d,d,d")9540 + (ior:SI (match_dup 1) (match_dup 2)))]9541 + "(TARGET_SCORE3)"9542 {9543 switch (which_alternative)9544 {9545 - case 0: return \"oris.c %0, %U2\";9546 - case 1: return \"ori.c %0, %c2\";9547 - case 2: return \"orri.c %0, %1, %c2\";9548 - case 3: return mdp_select (operands, "or", true, "", true);9549 + case 0: return \"oris.c\t%0, %U2\";9550 + case 1: return \"ori.c\t%0, %c2\";9551 + case 2: return \"orri.c\t%0, %1, %c2\";9552 + case 3: return score_select (operands, "or", true, "", true);9553 default: gcc_unreachable ();9554 }9555 }9556 [(set_attr "type" "arith")9557 + (set_attr "length" "4,4,4,4")9558 (set_attr "up_c" "yes")9559 (set_attr "mode" "SI")])9560 9561 -(define_insn "iorsi3_cmp"9562 +(define_insn "*iorsi3_cmp_score7"9563 [(set (reg:CC_NZ CC_REGNUM)9564 (compare:CC_NZ (ior:SI9565 (match_operand:SI 1 "register_operand" "0,0,d,d")9566 (match_operand:SI 2 "arith_operand" "I,K,M,d"))9567 (const_int 0)))9568 (clobber (match_scratch:SI 0 "=d,d,d,d"))]9569 - ""9570 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"9571 +{9572 + switch (which_alternative)9573 + {9574 + case 0: return \"oris.c\t%0, %U2\";9575 + case 1: return \"ori.c\t%0, %c2\";9576 + case 2: return \"orri.c\t%0, %1, %c2\";9577 + case 3: return score_select (operands, "or", true, "", true);9578 + default: gcc_unreachable ();9579 + }9580 +}9581 + [(set_attr "type" "arith")9582 + (set_attr "up_c" "yes")9583 + (set_attr "mode" "SI")])9584 +9585 +(define_insn "*iorsi3_cmp_score3"9586 + [(set (reg:CC_NZ CC_REGNUM)9587 + (compare:CC_NZ (ior:SI9588 + (match_operand:SI 1 "score_register_operand" "0,0,d,d")9589 + (match_operand:SI 2 "arith_operand" "I,K,M,d"))9590 + (const_int 0)))9591 + (clobber (match_scratch:SI 0 "=d,d,d,d"))]9592 + "(TARGET_SCORE3)"9593 {9594 switch (which_alternative)9595 {9596 - case 0: return \"oris.c %0, %U2\";9597 - case 1: return \"ori.c %0, %c2\";9598 - case 2: return \"orri.c %0, %1, %c2\";9599 - case 3: return mdp_select (operands, "or", true, "", true);9600 + case 0: return \"oris.c\t%0, %U2\";9601 + case 1: return \"ori.c\t%0, %c2\";9602 + case 2: return \"orri.c\t%0, %1, %c2\";9603 + case 3: return score_select (operands, "or", true, "", true);9604 default: gcc_unreachable ();9605 }9606 }9607 [(set_attr "type" "arith")9608 + (set_attr "length" "4,4,4,4")9609 (set_attr "up_c" "yes")9610 (set_attr "mode" "SI")])9611 9612 -(define_insn "xorsi3"9613 +(define_expand "xorsi3"9614 + [(set (match_operand:SI 0 "score_register_operand")9615 + (xor:SI (match_operand:SI 1 "score_register_operand")9616 + (match_operand:SI 2 "score_register_operand")))]9617 + ""9618 + ""9619 +)9620 +9621 +(define_insn "*xorsi3_score7"9622 [(set (match_operand:SI 0 "register_operand" "=d")9623 (xor:SI (match_operand:SI 1 "register_operand" "d")9624 (match_operand:SI 2 "register_operand" "d")))]9625 - ""9626 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"9627 +{9628 + return score_select (operands, "xor", true, "", false);9629 +}9630 + [(set_attr "type" "arith")9631 + (set_attr "mode" "SI")])9632 +9633 +(define_insn "*xorsi3_score3"9634 + [(set (match_operand:SI 0 "score_register_operand" "=d")9635 + (xor:SI (match_operand:SI 1 "score_register_operand" "d")9636 + (match_operand:SI 2 "score_register_operand" "d")))]9637 + "(TARGET_SCORE3)"9638 {9639 - return mdp_select (operands, "xor", true, "", false);9640 + return score_select (operands, "xor", true, "", false);9641 }9642 [(set_attr "type" "arith")9643 + (set_attr "length" "4")9644 (set_attr "mode" "SI")])9645 9646 -(define_insn "xorsi3_ucc"9647 +9648 +(define_insn "*xorsi3_ucc_score7"9649 [(set (reg:CC_NZ CC_REGNUM)9650 (compare:CC_NZ (xor:SI (match_operand:SI 1 "register_operand" "d")9651 (match_operand:SI 2 "register_operand" "d"))9652 (const_int 0)))9653 (set (match_operand:SI 0 "register_operand" "=d")9654 (xor:SI (match_dup 1) (match_dup 2)))]9655 - ""9656 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"9657 +{9658 + return score_select (operands, "xor", true, "", true);9659 +}9660 + [(set_attr "type" "arith")9661 + (set_attr "up_c" "yes")9662 + (set_attr "mode" "SI")])9663 +9664 +(define_insn "*xorsi3_ucc_score3"9665 + [(set (reg:CC_NZ CC_REGNUM)9666 + (compare:CC_NZ (xor:SI (match_operand:SI 1 "score_register_operand" "d")9667 + (match_operand:SI 2 "score_register_operand" "d"))9668 + (const_int 0)))9669 + (set (match_operand:SI 0 "score_register_operand" "=d")9670 + (xor:SI (match_dup 1) (match_dup 2)))]9671 + "(TARGET_SCORE3)"9672 {9673 - return mdp_select (operands, "xor", true, "", true);9674 + return score_select (operands, "xor", true, "", true);9675 }9676 [(set_attr "type" "arith")9677 + (set_attr "length" "4")9678 (set_attr "up_c" "yes")9679 (set_attr "mode" "SI")])9680 9681 -(define_insn "xorsi3_cmp"9682 +9683 +(define_insn "*xorsi3_cmp_score7"9684 [(set (reg:CC_NZ CC_REGNUM)9685 (compare:CC_NZ (xor:SI (match_operand:SI 1 "register_operand" "d")9686 (match_operand:SI 2 "register_operand" "d"))9687 @@ -574,28 +1016,66 @@9688 (clobber (match_scratch:SI 0 "=d"))]9689 ""9690 {9691 - return mdp_select (operands, "xor", true, "", true);9692 + return score_select (operands, "xor", true, "", true);9693 }9694 [(set_attr "type" "arith")9695 (set_attr "up_c" "yes")9696 (set_attr "mode" "SI")])9697 9698 -(define_insn "extendqisi2"9699 - [(set (match_operand:SI 0 "register_operand" "=d,d")9700 - (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]9701 - ""9702 -{9703 +(define_insn "*xorsi3_cmp_score3"9704 + [(set (reg:CC_NZ CC_REGNUM)9705 + (compare:CC_NZ (xor:SI (match_operand:SI 1 "score_register_operand" "d")9706 + (match_operand:SI 2 "score_register_operand" "d"))9707 + (const_int 0)))9708 + (clobber (match_scratch:SI 0 "=d"))]9709 + ""9710 +{9711 + return score_select (operands, "xor", true, "", true);9712 +}9713 + [(set_attr "type" "arith")9714 + (set_attr "length" "4")9715 + (set_attr "up_c" "yes")9716 + (set_attr "mode" "SI")])9717 +9718 +(define_expand "extendqisi2"9719 + [(set (match_operand:SI 0 "score_register_operand")9720 + (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand")))]9721 + ""9722 + ""9723 +)9724 +9725 +(define_insn "*extendqisi2_score7"9726 + [(set (match_operand:SI 0 "register_operand" "=d,d")9727 + (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]9728 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"9729 +{9730 + switch (which_alternative)9731 + {9732 + case 0: return \"extsb\t%0, %1\";9733 + case 1: return score_linsn (operands, SCORE_BYTE, true);9734 + default: gcc_unreachable ();9735 + }9736 +}9737 + [(set_attr "type" "arith,load")9738 + (set_attr "mode" "SI")])9739 +9740 +(define_insn "*extendqisi2_score3"9741 + [(set (match_operand:SI 0 "score_register_operand" "=d,d")9742 + (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]9743 + "(TARGET_SCORE3)"9744 +{9745 switch (which_alternative)9746 {9747 - case 0: return \"extsb %0, %1\";9748 - case 1: return mdp_linsn (operands, MDA_BYTE, true);9749 + case 0: return \"extsb\t%0, %1\";9750 + case 1: return score_linsn (operands, SCORE_BYTE, true);9751 default: gcc_unreachable ();9752 }9753 }9754 [(set_attr "type" "arith,load")9755 + (set_attr "length" "4,4")9756 (set_attr "mode" "SI")])9757 9758 -(define_insn "*extendqisi2_ucc"9759 +(define_insn "*extendqisi2_ucc_score7"9760 [(set (reg:CC_N CC_REGNUM)9761 (compare:CC_N (ashiftrt:SI9762 (ashift:SI (match_operand:SI 1 "register_operand" "d")9763 @@ -604,13 +1084,29 @@9764 (const_int 0)))9765 (set (match_operand:SI 0 "register_operand" "=d")9766 (sign_extend:SI (match_operand:QI 2 "register_operand" "0")))]9767 - ""9768 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"9769 "extsb.c %0, %1"9770 [(set_attr "type" "arith")9771 (set_attr "up_c" "yes")9772 (set_attr "mode" "SI")])9773 9774 -(define_insn "*extendqisi2_cmp"9775 +(define_insn "*extendqisi2_ucc_score3"9776 + [(set (reg:CC_N CC_REGNUM)9777 + (compare:CC_N (ashiftrt:SI9778 + (ashift:SI (match_operand:SI 1 "score_register_operand" "d")9779 + (const_int 24))9780 + (const_int 24))9781 + (const_int 0)))9782 + (set (match_operand:SI 0 "score_register_operand" "=d")9783 + (sign_extend:SI (match_operand:QI 2 "score_register_operand" "0")))]9784 + "(TARGET_SCORE3)"9785 + "extsb.c\t%0, %1"9786 + [(set_attr "type" "arith")9787 + (set_attr "length" "4")9788 + (set_attr "up_c" "yes")9789 + (set_attr "mode" "SI")])9790 +9791 +(define_insn "*extendqisi2_cmp_score7"9792 [(set (reg:CC_N CC_REGNUM)9793 (compare:CC_N (ashiftrt:SI9794 (ashift:SI (match_operand:SI 1 "register_operand" "d")9795 @@ -618,28 +1114,66 @@9796 (const_int 24))9797 (const_int 0)))9798 (clobber (match_scratch:SI 0 "=d"))]9799 - ""9800 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"9801 "extsb.c %0, %1"9802 [(set_attr "type" "arith")9803 (set_attr "up_c" "yes")9804 (set_attr "mode" "SI")])9805 9806 -(define_insn "extendhisi2"9807 +(define_insn "*extendqisi2_cmp_score3"9808 + [(set (reg:CC_N CC_REGNUM)9809 + (compare:CC_N (ashiftrt:SI9810 + (ashift:SI (match_operand:SI 1 "score_register_operand" "d")9811 + (const_int 24))9812 + (const_int 24))9813 + (const_int 0)))9814 + (clobber (match_scratch:SI 0 "=d"))]9815 + "(TARGET_SCORE3)"9816 + "extsb.c\t%0, %1"9817 + [(set_attr "type" "arith")9818 + (set_attr "length" "4")9819 + (set_attr "up_c" "yes")9820 + (set_attr "mode" "SI")])9821 +9822 +(define_expand "extendhisi2"9823 + [(set (match_operand:SI 0 "score_register_operand")9824 + (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand")))]9825 + ""9826 + ""9827 +)9828 +9829 +(define_insn "*extendhisi2_score7"9830 [(set (match_operand:SI 0 "register_operand" "=d,d")9831 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,m")))]9832 - ""9833 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"9834 +{9835 + switch (which_alternative)9836 + {9837 + case 0: return \"extsh\t%0, %1\";9838 + case 1: return score_linsn (operands, SCORE_HWORD, true);9839 + default: gcc_unreachable ();9840 + }9841 +}9842 + [(set_attr "type" "arith, load")9843 + (set_attr "mode" "SI")])9844 +9845 +(define_insn "*extendhisi2_score3"9846 + [(set (match_operand:SI 0 "score_register_operand" "=d,d")9847 + (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,m")))]9848 + "(TARGET_SCORE3)"9849 {9850 switch (which_alternative)9851 {9852 - case 0: return \"extsh %0, %1\";9853 - case 1: return mdp_linsn (operands, MDA_HWORD, true);9854 + case 0: return \"extsh\t%0, %1\";9855 + case 1: return score_linsn (operands, SCORE_HWORD, true);9856 default: gcc_unreachable ();9857 }9858 }9859 [(set_attr "type" "arith, load")9860 + (set_attr "length" "4,4")9861 (set_attr "mode" "SI")])9862 9863 -(define_insn "*extendhisi2_ucc"9864 +(define_insn "*extendhisi2_ucc_score7"9865 [(set (reg:CC_N CC_REGNUM)9866 (compare:CC_N (ashiftrt:SI9867 (ashift:SI (match_operand:SI 1 "register_operand" "d")9868 @@ -648,13 +1182,29 @@9869 (const_int 0)))9870 (set (match_operand:SI 0 "register_operand" "=d")9871 (sign_extend:SI (match_operand:HI 2 "register_operand" "0")))]9872 - ""9873 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"9874 "extsh.c %0, %1"9875 [(set_attr "type" "arith")9876 (set_attr "up_c" "yes")9877 (set_attr "mode" "SI")])9878 9879 -(define_insn "*extendhisi2_cmp"9880 +(define_insn "*extendhisi2_ucc_score3"9881 + [(set (reg:CC_N CC_REGNUM)9882 + (compare:CC_N (ashiftrt:SI9883 + (ashift:SI (match_operand:SI 1 "score_register_operand" "d")9884 + (const_int 16))9885 + (const_int 16))9886 + (const_int 0)))9887 + (set (match_operand:SI 0 "score_register_operand" "=d")9888 + (sign_extend:SI (match_operand:HI 2 "score_register_operand" "0")))]9889 + "(TARGET_SCORE3)"9890 + "extsh.c\t%0, %1"9891 + [(set_attr "type" "arith")9892 + (set_attr "length" "4")9893 + (set_attr "up_c" "yes")9894 + (set_attr "mode" "SI")])9895 +9896 +(define_insn "*extendhisi2_cmp_score7"9897 [(set (reg:CC_N CC_REGNUM)9898 (compare:CC_N (ashiftrt:SI9899 (ashift:SI (match_operand:SI 1 "register_operand" "d")9900 @@ -662,28 +1212,66 @@9901 (const_int 16))9902 (const_int 0)))9903 (clobber (match_scratch:SI 0 "=d"))]9904 - ""9905 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"9906 "extsh.c %0, %1"9907 [(set_attr "type" "arith")9908 (set_attr "up_c" "yes")9909 (set_attr "mode" "SI")])9910 9911 -(define_insn "zero_extendqisi2"9912 +(define_insn "*extendhisi2_cmp_score3"9913 + [(set (reg:CC_N CC_REGNUM)9914 + (compare:CC_N (ashiftrt:SI9915 + (ashift:SI (match_operand:SI 1 "score_register_operand" "d")9916 + (const_int 16))9917 + (const_int 16))9918 + (const_int 0)))9919 + (clobber (match_scratch:SI 0 "=d"))]9920 + "(TARGET_SCORE3)"9921 + "extsh.c\t%0, %1"9922 + [(set_attr "type" "arith")9923 + (set_attr "length" "4")9924 + (set_attr "up_c" "yes")9925 + (set_attr "mode" "SI")])9926 +9927 +(define_expand "zero_extendqisi2"9928 + [(set (match_operand:SI 0 "score_register_operand")9929 + (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand")))]9930 + ""9931 + ""9932 +)9933 +9934 +(define_insn "*zero_extendqisi2_score7"9935 [(set (match_operand:SI 0 "register_operand" "=d,d")9936 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]9937 - ""9938 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"9939 +{9940 + switch (which_alternative)9941 + {9942 + case 0: return \"extzb\t%0, %1\";9943 + case 1: return score_linsn (operands, SCORE_BYTE, false);9944 + default: gcc_unreachable ();9945 + }9946 +}9947 + [(set_attr "type" "arith, load")9948 + (set_attr "mode" "SI")])9949 +9950 +(define_insn "*zero_extendqisi2_score3"9951 + [(set (match_operand:SI 0 "score_register_operand" "=d,d")9952 + (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]9953 + "(TARGET_SCORE3)"9954 {9955 switch (which_alternative)9956 {9957 - case 0: return \"extzb %0, %1\";9958 - case 1: return mdp_linsn (operands, MDA_BYTE, false);9959 + case 0: return \"extzb\t%0, %1\";9960 + case 1: return score_linsn (operands, SCORE_BYTE, false);9961 default: gcc_unreachable ();9962 }9963 - }9964 +}9965 [(set_attr "type" "arith, load")9966 + (set_attr "length" "4,4")9967 (set_attr "mode" "SI")])9968 9969 -(define_insn "*zero_extendqisi2_ucc"9970 +(define_insn "*zero_extendqisi2_ucc_score7"9971 [(set (reg:CC_N CC_REGNUM)9972 (compare:CC_N (lshiftrt:SI9973 (ashift:SI (match_operand:SI 1 "register_operand" "d")9974 @@ -692,13 +1280,29 @@9975 (const_int 0)))9976 (set (match_operand:SI 0 "register_operand" "=d")9977 (zero_extend:SI (match_operand:QI 2 "register_operand" "0")))]9978 - ""9979 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"9980 "extzb.c %0, %1"9981 [(set_attr "type" "arith")9982 (set_attr "up_c" "yes")9983 (set_attr "mode" "SI")])9984 9985 -(define_insn "*zero_extendqisi2_cmp"9986 +(define_insn "*zero_extendqisi2_ucc_score3"9987 + [(set (reg:CC_N CC_REGNUM)9988 + (compare:CC_N (lshiftrt:SI9989 + (ashift:SI (match_operand:SI 1 "score_register_operand" "d")9990 + (const_int 24))9991 + (const_int 24))9992 + (const_int 0)))9993 + (set (match_operand:SI 0 "score_register_operand" "=d")9994 + (zero_extend:SI (match_operand:QI 2 "score_register_operand" "0")))]9995 + "(TARGET_SCORE3)"9996 + "extzb.c\t%0, %1"9997 + [(set_attr "type" "arith")9998 + (set_attr "length" "4")9999 + (set_attr "up_c" "yes")10000 + (set_attr "mode" "SI")])10001 +10002 +(define_insn "*zero_extendqisi2_cmp_score7"10003 [(set (reg:CC_N CC_REGNUM)10004 (compare:CC_N (lshiftrt:SI10005 (ashift:SI (match_operand:SI 1 "register_operand" "d")10006 @@ -706,28 +1310,66 @@10007 (const_int 24))10008 (const_int 0)))10009 (clobber (match_scratch:SI 0 "=d"))]10010 - ""10011 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"10012 "extzb.c %0, %1"10013 [(set_attr "type" "arith")10014 (set_attr "up_c" "yes")10015 (set_attr "mode" "SI")])10016 10017 -(define_insn "zero_extendhisi2"10018 +(define_insn "*zero_extendqisi2_cmp_score3"10019 + [(set (reg:CC_N CC_REGNUM)10020 + (compare:CC_N (lshiftrt:SI10021 + (ashift:SI (match_operand:SI 1 "score_register_operand" "d")10022 + (const_int 24))10023 + (const_int 24))10024 + (const_int 0)))10025 + (clobber (match_scratch:SI 0 "=d"))]10026 + "(TARGET_SCORE3)"10027 + "extzb.c\t%0, %1"10028 + [(set_attr "type" "arith")10029 + (set_attr "length" "4")10030 + (set_attr "up_c" "yes")10031 + (set_attr "mode" "SI")])10032 +10033 +(define_expand "zero_extendhisi2"10034 + [(set (match_operand:SI 0 "score_register_operand")10035 + (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand")))]10036 + ""10037 + ""10038 +)10039 +10040 +(define_insn "*zero_extendhisi2_score7"10041 [(set (match_operand:SI 0 "register_operand" "=d,d")10042 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,m")))]10043 - ""10044 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"10045 +{10046 + switch (which_alternative)10047 + {10048 + case 0: return \"extzh\t%0, %1\";10049 + case 1: return score_linsn (operands, SCORE_HWORD, false);10050 + default: gcc_unreachable ();10051 + }10052 +}10053 + [(set_attr "type" "arith, load")10054 + (set_attr "mode" "SI")])10055 +10056 +(define_insn "*zero_extendhisi2_score3"10057 + [(set (match_operand:SI 0 "score_register_operand" "=d,d")10058 + (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,m")))]10059 + "(TARGET_SCORE3)"10060 {10061 switch (which_alternative)10062 {10063 - case 0: return \"extzh %0, %1\";10064 - case 1: return mdp_linsn (operands, MDA_HWORD, false);10065 + case 0: return \"extzh\t%0, %1\";10066 + case 1: return score_linsn (operands, SCORE_HWORD, false);10067 default: gcc_unreachable ();10068 }10069 - }10070 +}10071 [(set_attr "type" "arith, load")10072 + (set_attr "length" "4,4")10073 (set_attr "mode" "SI")])10074 10075 -(define_insn "*zero_extendhisi2_ucc"10076 +(define_insn "*zero_extendhisi2_ucc_score7"10077 [(set (reg:CC_N CC_REGNUM)10078 (compare:CC_N (lshiftrt:SI10079 (ashift:SI (match_operand:SI 1 "register_operand" "d")10080 @@ -736,13 +1378,29 @@10081 (const_int 0)))10082 (set (match_operand:SI 0 "register_operand" "=d")10083 (zero_extend:SI (match_operand:HI 2 "register_operand" "0")))]10084 - ""10085 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"10086 "extzh.c %0, %1"10087 [(set_attr "type" "arith")10088 (set_attr "up_c" "yes")10089 (set_attr "mode" "SI")])10090 10091 -(define_insn "*zero_extendhisi2_cmp"10092 +(define_insn "*zero_extendhisi2_ucc_score3"10093 + [(set (reg:CC_N CC_REGNUM)10094 + (compare:CC_N (lshiftrt:SI10095 + (ashift:SI (match_operand:SI 1 "score_register_operand" "d")10096 + (const_int 16))10097 + (const_int 16))10098 + (const_int 0)))10099 + (set (match_operand:SI 0 "score_register_operand" "=d")10100 + (zero_extend:SI (match_operand:HI 2 "score_register_operand" "0")))]10101 + "(TARGET_SCORE3)"10102 + "extzh.c\t%0, %1"10103 + [(set_attr "type" "arith")10104 + (set_attr "length" "4")10105 + (set_attr "up_c" "yes")10106 + (set_attr "mode" "SI")])10107 +10108 +(define_insn "*zero_extendhisi2_cmp_score7"10109 [(set (reg:CC_N CC_REGNUM)10110 (compare:CC_N (lshiftrt:SI10111 (ashift:SI (match_operand:SI 1 "register_operand" "d")10112 @@ -750,78 +1408,235 @@10113 (const_int 16))10114 (const_int 0)))10115 (clobber (match_scratch:SI 0 "=d"))]10116 - ""10117 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"10118 "extzh.c %0, %1"10119 [(set_attr "type" "arith")10120 (set_attr "up_c" "yes")10121 (set_attr "mode" "SI")])10122 10123 -(define_insn "mulsi3"10124 +(define_insn "*zero_extendhisi2_cmp_score3"10125 + [(set (reg:CC_N CC_REGNUM)10126 + (compare:CC_N (lshiftrt:SI10127 + (ashift:SI (match_operand:SI 1 "score_register_operand" "d")10128 + (const_int 16))10129 + (const_int 16))10130 + (const_int 0)))10131 + (clobber (match_scratch:SI 0 "=d"))]10132 + "(TARGET_SCORE3)"10133 + "extzh.c\t%0, %1"10134 + [(set_attr "type" "arith")10135 + (set_attr "length" "4")10136 + (set_attr "up_c" "yes")10137 + (set_attr "mode" "SI")])10138 +10139 +(define_expand "mulsi3"10140 + [(set (match_operand:SI 0 "score_register_operand")10141 + (mult:SI (match_operand:SI 1 "score_register_operand")10142 + (match_operand:SI 2 "score_register_operand")))]10143 + ""10144 +{10145 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)10146 + emit_insn (gen_mulsi3_score7 (operands[0], operands[1], operands[2]));10147 + else if (TARGET_SCORE3)10148 + emit_insn (gen_mulsi3_score3 (operands[0], operands[1], operands[2]));10149 + DONE;10150 +})10151 +10152 +(define_insn "mulsi3_score7"10153 [(set (match_operand:SI 0 "register_operand" "=l")10154 (mult:SI (match_operand:SI 1 "register_operand" "d")10155 (match_operand:SI 2 "register_operand" "d")))10156 - (clobber (reg:SI HI_REGNUM))]10157 - "!TARGET_SCORE5U"10158 + (clobber (reg:SI HI_REGNUM))]10159 + "(TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)"10160 "mul %1, %2"10161 [(set_attr "type" "mul")10162 (set_attr "mode" "SI")])10163 10164 -(define_insn "mulsidi3"10165 +(define_insn "mulsi3_score3"10166 + [(set (match_operand:SI 0 "score_register_operand" "=d")10167 + (mult:SI (match_operand:SI 1 "score_register_operand" "d")10168 + (match_operand:SI 2 "score_register_operand" "d")))]10169 + "(TARGET_SCORE3)"10170 + "mulr.l\t%0, %1, %2"10171 + [(set_attr "type" "mul")10172 + (set_attr "length" "4")10173 + (set_attr "mode" "SI")])10174 +10175 +(define_expand "mulsidi3"10176 + [(set (match_operand:DI 0 "score_register_operand")10177 + (mult:DI (sign_extend:DI10178 + (match_operand:SI 1 "score_register_operand"))10179 + (sign_extend:DI10180 + (match_operand:SI 2 "score_register_operand"))))]10181 + ""10182 +{10183 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)10184 + emit_insn (gen_mulsidi3_score7 (operands[0], operands[1], operands[2]));10185 + else if (TARGET_SCORE3)10186 + emit_insn (gen_mulsidi3_score3 (operands[0], operands[1], operands[2]));10187 + DONE;10188 +})10189 +10190 +(define_insn "mulsidi3_score7"10191 [(set (match_operand:DI 0 "register_operand" "=x")10192 (mult:DI (sign_extend:DI10193 (match_operand:SI 1 "register_operand" "d"))10194 (sign_extend:DI10195 (match_operand:SI 2 "register_operand" "d"))))]10196 - "!TARGET_SCORE5U"10197 + "(TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)"10198 "mul %1, %2"10199 [(set_attr "type" "mul")10200 (set_attr "mode" "DI")])10201 10202 -(define_insn "umulsidi3"10203 +(define_insn "mulsidi3_score3"10204 + [(set (match_operand:DI 0 "score_register_operand" "=d")10205 + (mult:DI (sign_extend:DI10206 + (match_operand:SI 1 "score_register_operand" "d"))10207 + (sign_extend:DI10208 + (match_operand:SI 2 "score_register_operand" "d"))))]10209 + "(TARGET_SCORE3)"10210 + "mulr\t%0, %1, %2"10211 + [(set_attr "type" "mul")10212 + (set_attr "length" "4")10213 + (set_attr "mode" "DI")])10214 +10215 +(define_expand "umulsidi3"10216 + [(set (match_operand:DI 0 "score_register_operand")10217 + (mult:DI (zero_extend:DI10218 + (match_operand:SI 1 "score_register_operand"))10219 + (zero_extend:DI10220 + (match_operand:SI 2 "score_register_operand"))))]10221 + ""10222 +{10223 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)10224 + emit_insn (gen_umulsidi3_score7 (operands[0], operands[1], operands[2]));10225 + else if (TARGET_SCORE3)10226 + emit_insn (gen_umulsidi3_score3 (operands[0], operands[1], operands[2]));10227 + DONE;10228 +})10229 +10230 +(define_insn "umulsidi3_score7"10231 [(set (match_operand:DI 0 "register_operand" "=x")10232 (mult:DI (zero_extend:DI10233 (match_operand:SI 1 "register_operand" "d"))10234 (zero_extend:DI10235 (match_operand:SI 2 "register_operand" "d"))))]10236 - "!TARGET_SCORE5U"10237 + "(TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)"10238 "mulu %1, %2"10239 [(set_attr "type" "mul")10240 (set_attr "mode" "DI")])10241 10242 -(define_insn "divmodsi4"10243 +(define_insn "umulsidi3_score3"10244 + [(set (match_operand:DI 0 "score_register_operand" "=d")10245 + (mult:DI (zero_extend:DI10246 + (match_operand:SI 1 "score_register_operand" "d"))10247 + (zero_extend:DI10248 + (match_operand:SI 2 "score_register_operand" "d"))))]10249 + "(TARGET_SCORE3)"10250 + "mulur\t%0, %1, %2"10251 + [(set_attr "type" "mul")10252 + (set_attr "length" "4")10253 + (set_attr "mode" "DI")])10254 +10255 +(define_expand "divmodsi4"10256 + [(parallel10257 + [(set (match_operand:SI 0 "score_register_operand")10258 + (div:SI (match_operand:SI 1 "score_register_operand")10259 + (match_operand:SI 2 "score_register_operand")))10260 + (set (match_operand:SI 3 "score_register_operand")10261 + (mod:SI (match_dup 1) (match_dup 2)))])]10262 + ""10263 + ""10264 +)10265 +10266 +(define_insn "*divmodsi4_score7"10267 [(set (match_operand:SI 0 "register_operand" "=l")10268 (div:SI (match_operand:SI 1 "register_operand" "d")10269 (match_operand:SI 2 "register_operand" "d")))10270 (set (match_operand:SI 3 "register_operand" "=h")10271 (mod:SI (match_dup 1) (match_dup 2)))]10272 - "!TARGET_SCORE5U"10273 + "(TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)"10274 "div %1, %2"10275 [(set_attr "type" "div")10276 (set_attr "mode" "SI")])10277 10278 -(define_insn "udivmodsi4"10279 +(define_insn "*divmodsi4_score3"10280 + [(set (match_operand:SI 0 "score_register_operand" "=l")10281 + (div:SI (match_operand:SI 1 "score_register_operand" "d")10282 + (match_operand:SI 2 "score_register_operand" "d")))10283 + (set (match_operand:SI 3 "score_register_operand" "=h")10284 + (mod:SI (match_dup 1) (match_dup 2)))]10285 + "(TARGET_SCORE3)"10286 + "div\t%1, %2"10287 + [(set_attr "type" "div")10288 + (set_attr "mode" "SI")])10289 +10290 +(define_expand "udivmodsi4"10291 + [(parallel10292 + [(set (match_operand:SI 0 "score_register_operand")10293 + (udiv:SI (match_operand:SI 1 "score_register_operand")10294 + (match_operand:SI 2 "score_register_operand")))10295 + (set (match_operand:SI 3 "score_register_operand")10296 + (umod:SI (match_dup 1) (match_dup 2)))])]10297 + ""10298 + ""10299 +)10300 +10301 +(define_insn "*udivmodsi4_score7"10302 [(set (match_operand:SI 0 "register_operand" "=l")10303 (udiv:SI (match_operand:SI 1 "register_operand" "d")10304 (match_operand:SI 2 "register_operand" "d")))10305 (set (match_operand:SI 3 "register_operand" "=h")10306 (umod:SI (match_dup 1) (match_dup 2)))]10307 - "!TARGET_SCORE5U"10308 + "(TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)"10309 "divu %1, %2"10310 [(set_attr "type" "div")10311 (set_attr "mode" "SI")])10312 10313 -(define_insn "ashlsi3"10314 +(define_insn "*udivmodsi4_score3"10315 + [(set (match_operand:SI 0 "score_register_operand" "=l")10316 + (udiv:SI (match_operand:SI 1 "score_register_operand" "d")10317 + (match_operand:SI 2 "score_register_operand" "d")))10318 + (set (match_operand:SI 3 "score_register_operand" "=h")10319 + (umod:SI (match_dup 1) (match_dup 2)))]10320 + "(TARGET_SCORE3)"10321 + "divu\t%1, %2"10322 + [(set_attr "type" "div")10323 + (set_attr "mode" "SI")])10324 +10325 +(define_expand "ashlsi3"10326 + [(set (match_operand:SI 0 "score_register_operand")10327 + (ashift:SI (match_operand:SI 1 "score_register_operand")10328 + (match_operand:SI 2 "arith_operand")))]10329 + ""10330 + ""10331 +)10332 +10333 +(define_insn "*ashlsi3_score7"10334 [(set (match_operand:SI 0 "register_operand" "=d,d")10335 (ashift:SI (match_operand:SI 1 "register_operand" "d,d")10336 (match_operand:SI 2 "arith_operand" "J,d")))]10337 - ""10338 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"10339 "@10340 slli %0, %1, %c210341 sll %0, %1, %2"10342 [(set_attr "type" "arith")10343 (set_attr "mode" "SI")])10344 10345 -(define_insn "ashlsi3_ucc"10346 +(define_insn "*ashlsi3_score3"10347 + [(set (match_operand:SI 0 "score_register_operand" "=e,d,d")10348 + (ashift:SI (match_operand:SI 1 "score_register_operand" "0,d,d")10349 + (match_operand:SI 2 "arith_operand" "J,J,d")))]10350 + "(TARGET_SCORE3)"10351 + "@10352 + slli!\t%0, %c210353 + slli\t%0, %1, %c210354 + sll\t%0, %1, %2"10355 + [(set_attr "type" "arith")10356 + (set_attr "length" "2,4,4")10357 + (set_attr "mode" "SI")])10358 +10359 +(define_insn "*ashlsi3_ucc_score7"10360 [(set (reg:CC_NZ CC_REGNUM)10361 (compare:CC_NZ (ashift:SI10362 (match_operand:SI 1 "register_operand" "d,d")10363 @@ -829,12 +1644,12 @@10364 (const_int 0)))10365 (set (match_operand:SI 0 "register_operand" "=d,d")10366 (ashift:SI (match_dup 1) (match_dup 2)))]10367 - ""10368 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"10369 {10370 switch (which_alternative)10371 {10372 - case 0: return mdp_select (operands, "slli", false, "c", true);10373 - case 1: return mdp_select (operands, "sll", false, "", true);10374 + case 0: return score_select (operands, "slli", false, "c", true);10375 + case 1: return score_select (operands, "sll", false, "", true);10376 default: gcc_unreachable ();10377 }10378 }10379 @@ -842,51 +1657,41 @@10380 (set_attr "up_c" "yes")10381 (set_attr "mode" "SI")])10382 10383 -(define_insn "ashlsi3_cmp"10384 +(define_insn "*ashlsi3_ucc_score3"10385 [(set (reg:CC_NZ CC_REGNUM)10386 (compare:CC_NZ (ashift:SI10387 - (match_operand:SI 1 "register_operand" "d,d")10388 + (match_operand:SI 1 "score_register_operand" "d,d")10389 (match_operand:SI 2 "arith_operand" "J,d"))10390 (const_int 0)))10391 - (clobber (match_scratch:SI 0 "=d,d"))]10392 - ""10393 + (set (match_operand:SI 0 "score_register_operand" "=d,d")10394 + (ashift:SI (match_dup 1) (match_dup 2)))]10395 + "(TARGET_SCORE3)"10396 {10397 switch (which_alternative)10398 {10399 - case 0: return mdp_select (operands, "slli", false, "c", true);10400 - case 1: return mdp_select (operands, "sll", false, "", true);10401 + case 0: return score_select (operands, "slli", false, "c", true);10402 + case 1: return score_select (operands, "sll", false, "", true);10403 default: gcc_unreachable ();10404 }10405 }10406 [(set_attr "type" "arith")10407 + (set_attr "length" "4,4")10408 (set_attr "up_c" "yes")10409 (set_attr "mode" "SI")])10410 10411 -(define_insn "ashrsi3"10412 - [(set (match_operand:SI 0 "register_operand" "=d,d")10413 - (ashiftrt:SI (match_operand:SI 1 "register_operand" "d,d")10414 - (match_operand:SI 2 "arith_operand" "J,d")))]10415 - ""10416 - "@10417 - srai %0, %1, %c210418 - sra %0, %1, %2"10419 - [(set_attr "type" "arith")10420 - (set_attr "mode" "SI")])10421 -10422 -(define_insn "ashrsi3_ucc"10423 +(define_insn "*ashlsi3_cmp_score7"10424 [(set (reg:CC_NZ CC_REGNUM)10425 - (compare:CC_NZ (ashiftrt:SI10426 + (compare:CC_NZ (ashift:SI10427 (match_operand:SI 1 "register_operand" "d,d")10428 (match_operand:SI 2 "arith_operand" "J,d"))10429 (const_int 0)))10430 - (set (match_operand:SI 0 "register_operand" "=d,d")10431 - (ashiftrt:SI (match_dup 1) (match_dup 2)))]10432 - ""10433 + (clobber (match_scratch:SI 0 "=d,d"))]10434 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"10435 {10436 switch (which_alternative)10437 {10438 - case 0: return \"srai.c %0, %1, %c2\";10439 - case 1: return mdp_select (operands, "sra", false, "", true);10440 + case 0: return score_select (operands, "slli", false, "c", true);10441 + case 1: return score_select (operands, "sll", false, "", true);10442 default: gcc_unreachable ();10443 }10444 }10445 @@ -894,92 +1699,289 @@10446 (set_attr "up_c" "yes")10447 (set_attr "mode" "SI")])10448 10449 -(define_insn "ashrsi3_cmp"10450 +(define_insn "*ashlsi3_cmp_score3"10451 [(set (reg:CC_NZ CC_REGNUM)10452 - (compare:CC_NZ (ashiftrt:SI10453 - (match_operand:SI 1 "register_operand" "d,d")10454 + (compare:CC_NZ (ashift:SI10455 + (match_operand:SI 1 "score_register_operand" "d,d")10456 (match_operand:SI 2 "arith_operand" "J,d"))10457 (const_int 0)))10458 (clobber (match_scratch:SI 0 "=d,d"))]10459 - ""10460 + "(TARGET_SCORE3)"10461 {10462 switch (which_alternative)10463 {10464 - case 0: return \"srai.c %0, %1, %c2\";10465 - case 1: return mdp_select (operands, "sra", false, "", true);10466 + case 0: return score_select (operands, "slli", false, "c", true);10467 + case 1: return score_select (operands, "sll", false, "", true);10468 default: gcc_unreachable ();10469 }10470 }10471 [(set_attr "type" "arith")10472 + (set_attr "length" "4,4")10473 (set_attr "up_c" "yes")10474 (set_attr "mode" "SI")])10475 10476 -(define_insn "lshrsi3"10477 +10478 +(define_expand "ashrsi3"10479 + [(set (match_operand:SI 0 "score_register_operand")10480 + (ashiftrt:SI (match_operand:SI 1 "score_register_operand")10481 + (match_operand:SI 2 "arith_operand")))]10482 + ""10483 + ""10484 +)10485 +10486 +(define_insn "*ashrsi3_score7"10487 [(set (match_operand:SI 0 "register_operand" "=d,d")10488 - (lshiftrt:SI (match_operand:SI 1 "register_operand" "d,d")10489 + (ashiftrt:SI (match_operand:SI 1 "register_operand" "d,d")10490 (match_operand:SI 2 "arith_operand" "J,d")))]10491 - ""10492 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"10493 "@10494 - srli %0, %1, %c210495 - srl %0, %1, %2"10496 + srai %0, %1, %c210497 + sra %0, %1, %2"10498 [(set_attr "type" "arith")10499 (set_attr "mode" "SI")])10500 10501 -(define_insn "lshrsi3_ucc"10502 - [(set (reg:CC_NZ CC_REGNUM)10503 - (compare:CC_NZ (lshiftrt:SI10504 - (match_operand:SI 1 "register_operand" "d,d")10505 - (match_operand:SI 2 "arith_operand" "J,d"))10506 +(define_insn "*ashrsi3_score3"10507 + [(set (match_operand:SI 0 "score_register_operand" "=d,d")10508 + (ashiftrt:SI (match_operand:SI 1 "score_register_operand" "d,d")10509 + (match_operand:SI 2 "arith_operand" "J,d")))]10510 + "(TARGET_SCORE3)"10511 + "@10512 + srai\t%0, %1, %c210513 + sra\t%0, %1, %2"10514 + [(set_attr "type" "arith")10515 + (set_attr "length" "4,4")10516 + (set_attr "mode" "SI")])10517 +10518 +(define_insn "*ashrsi3_ucc_score7"10519 + [(set (reg:CC_NZ CC_REGNUM)10520 + (compare:CC_NZ (ashiftrt:SI10521 + (match_operand:SI 1 "register_operand" "d,d")10522 + (match_operand:SI 2 "arith_operand" "J,d"))10523 (const_int 0)))10524 (set (match_operand:SI 0 "register_operand" "=d,d")10525 - (lshiftrt:SI (match_dup 1) (match_dup 2)))]10526 + (ashiftrt:SI (match_dup 1) (match_dup 2)))]10527 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"10528 +{10529 + switch (which_alternative)10530 + {10531 + case 0: return \"srai.c\t%0, %1, %c2\";10532 + case 1: return score_select (operands, "sra", false, "", true);10533 + default: gcc_unreachable ();10534 + }10535 +}10536 + [(set_attr "type" "arith")10537 + (set_attr "up_c" "yes")10538 + (set_attr "mode" "SI")])10539 +10540 +(define_insn "*ashrsi3_ucc_score3"10541 + [(set (reg:CC_NZ CC_REGNUM)10542 + (compare:CC_NZ (ashiftrt:SI10543 + (match_operand:SI 1 "score_register_operand" "d,d")10544 + (match_operand:SI 2 "arith_operand" "J,d"))10545 + (const_int 0)))10546 + (set (match_operand:SI 0 "score_register_operand" "=d,d")10547 + (ashiftrt:SI (match_dup 1) (match_dup 2)))]10548 + "(TARGET_SCORE3)"10549 +{10550 + switch (which_alternative)10551 + {10552 + case 0: return \"srai.c\t%0, %1, %c2\";10553 + case 1: return score_select (operands, "sra", false, "", true);10554 + default: gcc_unreachable ();10555 + }10556 +}10557 + [(set_attr "type" "arith")10558 + (set_attr "length" "4,4")10559 + (set_attr "up_c" "yes")10560 + (set_attr "mode" "SI")])10561 +10562 +(define_insn "*ashrsi3_cmp_score7"10563 + [(set (reg:CC_NZ CC_REGNUM)10564 + (compare:CC_NZ (ashiftrt:SI10565 + (match_operand:SI 1 "register_operand" "d,d")10566 + (match_operand:SI 2 "arith_operand" "J,d"))10567 + (const_int 0)))10568 + (clobber (match_scratch:SI 0 "=d,d"))]10569 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"10570 +{10571 + switch (which_alternative)10572 + {10573 + case 0: return \"srai.c\t%0, %1, %c2\";10574 + case 1: return score_select (operands, "sra", false, "", true);10575 + default: gcc_unreachable ();10576 + }10577 +}10578 + [(set_attr "type" "arith")10579 + (set_attr "up_c" "yes")10580 + (set_attr "mode" "SI")])10581 +10582 +(define_insn "ashrsi3_cmp_score3"10583 + [(set (reg:CC_NZ CC_REGNUM)10584 + (compare:CC_NZ (ashiftrt:SI10585 + (match_operand:SI 1 "score_register_operand" "d,d")10586 + (match_operand:SI 2 "arith_operand" "J,d"))10587 + (const_int 0)))10588 + (clobber (match_scratch:SI 0 "=d,d"))]10589 + "(TARGET_SCORE3)"10590 +{10591 + switch (which_alternative)10592 + {10593 + case 0: return \"srai.c\t%0, %1, %c2\";10594 + case 1: return score_select (operands, "sra", false, "", true);10595 + default: gcc_unreachable ();10596 + }10597 +}10598 + [(set_attr "type" "arith")10599 + (set_attr "length" "4,4")10600 + (set_attr "up_c" "yes")10601 + (set_attr "mode" "SI")])10602 +10603 +(define_expand "lshrsi3"10604 + [(set (match_operand:SI 0 "score_register_operand")10605 + (lshiftrt:SI (match_operand:SI 1 "score_register_operand")10606 + (match_operand:SI 2 "arith_operand")))]10607 + ""10608 ""10609 +)10610 +10611 +(define_insn "*lshrsi3_score7"10612 + [(set (match_operand:SI 0 "register_operand" "=d,d")10613 + (lshiftrt:SI (match_operand:SI 1 "register_operand" "d,d")10614 + (match_operand:SI 2 "arith_operand" "J,d")))]10615 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"10616 + "@10617 + srli %0, %1, %c210618 + srl %0, %1, %2"10619 + [(set_attr "type" "arith")10620 + (set_attr "mode" "SI")])10621 +10622 +(define_insn "*lshrsi3_score3"10623 + [(set (match_operand:SI 0 "score_register_operand" "=e,d,d")10624 + (lshiftrt:SI (match_operand:SI 1 "score_register_operand" "0,d,d")10625 + (match_operand:SI 2 "arith_operand" "J,J,d")))]10626 + "(TARGET_SCORE3)"10627 + "@10628 + srli!\t%0, %c210629 + srli\t%0, %1, %c210630 + srl\t%0, %1, %2"10631 + [(set_attr "type" "arith")10632 + (set_attr "length" "2,4,4")10633 + (set_attr "mode" "SI")])10634 +10635 +(define_insn "*lshrsi3_ucc_score7"10636 + [(set (reg:CC_NZ CC_REGNUM)10637 + (compare:CC_NZ (lshiftrt:SI10638 + (match_operand:SI 1 "register_operand" "d,d")10639 + (match_operand:SI 2 "arith_operand" "J,d"))10640 + (const_int 0)))10641 + (set (match_operand:SI 0 "register_operand" "=d,d")10642 + (lshiftrt:SI (match_dup 1) (match_dup 2)))]10643 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"10644 +{10645 + switch (which_alternative)10646 + {10647 + case 0: return score_select (operands, "srli", false, "c", true);10648 + case 1: return score_select (operands, "srl", false, "", true);10649 + default: gcc_unreachable ();10650 + }10651 +}10652 + [(set_attr "type" "arith")10653 + (set_attr "up_c" "yes")10654 + (set_attr "mode" "SI")])10655 +10656 +(define_insn "*lshrsi3_ucc_score3"10657 + [(set (reg:CC_NZ CC_REGNUM)10658 + (compare:CC_NZ (lshiftrt:SI10659 + (match_operand:SI 1 "score_register_operand" "d,d")10660 + (match_operand:SI 2 "arith_operand" "J,d"))10661 + (const_int 0)))10662 + (set (match_operand:SI 0 "score_register_operand" "=d,d")10663 + (lshiftrt:SI (match_dup 1) (match_dup 2)))]10664 + "(TARGET_SCORE3)"10665 {10666 switch (which_alternative)10667 {10668 - case 0: return mdp_select (operands, "srli", false, "c", true);10669 - case 1: return mdp_select (operands, "srl", false, "", true);10670 + case 0: return score_select (operands, "srli", false, "c", true);10671 + case 1: return score_select (operands, "srl", false, "", true);10672 default: gcc_unreachable ();10673 }10674 }10675 [(set_attr "type" "arith")10676 + (set_attr "length" "4,4")10677 (set_attr "up_c" "yes")10678 (set_attr "mode" "SI")])10679 10680 -(define_insn "lshrsi3_cmp"10681 +(define_insn "*lshrsi3_cmp_score7"10682 [(set (reg:CC_NZ CC_REGNUM)10683 (compare:CC_NZ (lshiftrt:SI10684 (match_operand:SI 1 "register_operand" "d,d")10685 (match_operand:SI 2 "arith_operand" "J,d"))10686 (const_int 0)))10687 (clobber (match_scratch:SI 0 "=d,d"))]10688 - ""10689 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"10690 +{10691 + switch (which_alternative)10692 + {10693 + case 0: return score_select (operands, "srli", false, "c", true);10694 + case 1: return score_select (operands, "srl", false, "", true);10695 + default: gcc_unreachable ();10696 + }10697 +}10698 + [(set_attr "type" "arith")10699 + (set_attr "up_c" "yes")10700 + (set_attr "mode" "SI")])10701 +10702 +(define_insn "*lshrsi3_cmp_score3"10703 + [(set (reg:CC_NZ CC_REGNUM)10704 + (compare:CC_NZ (lshiftrt:SI10705 + (match_operand:SI 1 "score_register_operand" "d,d")10706 + (match_operand:SI 2 "arith_operand" "J,d"))10707 + (const_int 0)))10708 + (clobber (match_scratch:SI 0 "=d,d"))]10709 + "(TARGET_SCORE3)"10710 {10711 switch (which_alternative)10712 {10713 - case 0: return mdp_select (operands, "srli", false, "c", true);10714 - case 1: return mdp_select (operands, "srl", false, "", true);10715 + case 0: return score_select (operands, "srli", false, "c", true);10716 + case 1: return score_select (operands, "srl", false, "", true);10717 default: gcc_unreachable ();10718 }10719 }10720 [(set_attr "type" "arith")10721 + (set_attr "length" "4,4")10722 (set_attr "up_c" "yes")10723 (set_attr "mode" "SI")])10724 10725 -(define_insn "negsi2"10726 +(define_expand "negsi2"10727 + [(set (match_operand:SI 0 "score_register_operand")10728 + (neg:SI (match_operand:SI 1 "score_register_operand")))]10729 + ""10730 + ""10731 +)10732 +10733 +(define_insn "*negsi2_score7"10734 [(set (match_operand:SI 0 "register_operand" "=d")10735 (neg:SI (match_operand:SI 1 "register_operand" "d")))]10736 - ""10737 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"10738 "neg %0, %1"10739 [(set_attr "type" "arith")10740 (set_attr "mode" "SI")])10741 10742 -(define_insn "*negsi2_cmp"10743 +(define_insn "*negsi2_score3"10744 + [(set (match_operand:SI 0 "score_register_operand" "=d")10745 + (neg:SI (match_operand:SI 1 "score_register_operand" "d")))]10746 + "(TARGET_SCORE3)"10747 + "neg\t%0, %1"10748 + [(set_attr "type" "arith")10749 + (set_attr "length" "4")10750 + (set_attr "mode" "SI")])10751 +10752 +(define_insn "*negsi2_cmp_score7"10753 [(set (reg:CC_NZ CC_REGNUM)10754 (compare:CC_NZ (neg:SI (match_operand:SI 1 "register_operand" "e,d"))10755 (const_int 0)))10756 (clobber (match_scratch:SI 0 "=e,d"))]10757 - ""10758 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"10759 "@10760 neg! %0, %110761 neg.c %0, %1"10762 @@ -987,13 +1989,25 @@10763 (set_attr "up_c" "yes")10764 (set_attr "mode" "SI")])10765 10766 -(define_insn "negsi2_ucc"10767 +(define_insn "*negsi2_cmp_score3"10768 + [(set (reg:CC_NZ CC_REGNUM)10769 + (compare:CC_NZ (neg:SI (match_operand:SI 1 "score_register_operand" "d"))10770 + (const_int 0)))10771 + (clobber (match_scratch:SI 0 "=d"))]10772 + "(TARGET_SCORE3)"10773 + "neg.c\t%0, %1"10774 + [(set_attr "type" "arith")10775 + (set_attr "length" "4")10776 + (set_attr "up_c" "yes")10777 + (set_attr "mode" "SI")])10778 +10779 +(define_insn "*negsi2_ucc_score7"10780 [(set (reg:CC_NZ CC_REGNUM)10781 (compare:CC_NZ (neg:SI (match_operand:SI 1 "register_operand" "e,d"))10782 (const_int 0)))10783 (set (match_operand:SI 0 "register_operand" "=e,d")10784 (neg:SI (match_dup 1)))]10785 - ""10786 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"10787 "@10788 neg! %0, %110789 neg.c %0, %1"10790 @@ -1001,21 +2015,51 @@10791 (set_attr "up_c" "yes")10792 (set_attr "mode" "SI")])10793 10794 -(define_insn "one_cmplsi2"10795 +(define_insn "*negsi2_ucc_score3"10796 + [(set (reg:CC_NZ CC_REGNUM)10797 + (compare:CC_NZ (neg:SI (match_operand:SI 1 "score_register_operand" "d"))10798 + (const_int 0)))10799 + (set (match_operand:SI 0 "score_register_operand" "=d")10800 + (neg:SI (match_dup 1)))]10801 + "(TARGET_SCORE3)"10802 + "neg.c\t%0, %1"10803 + [(set_attr "type" "arith")10804 + (set_attr "length" "4")10805 + (set_attr "up_c" "yes")10806 + (set_attr "mode" "SI")])10807 +10808 +10809 +(define_expand "one_cmplsi2"10810 + [(set (match_operand:SI 0 "score_register_operand")10811 + (not:SI (match_operand:SI 1 "score_register_operand")))]10812 + ""10813 + ""10814 +)10815 +10816 +(define_insn "*one_cmplsi2_score7"10817 [(set (match_operand:SI 0 "register_operand" "=d")10818 (not:SI (match_operand:SI 1 "register_operand" "d")))]10819 - ""10820 - "not %0, %1"10821 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"10822 + "not\t%0, %1"10823 + [(set_attr "type" "arith")10824 + (set_attr "mode" "SI")])10825 +10826 +(define_insn "*one_cmplsi2_score3"10827 + [(set (match_operand:SI 0 "score_register_operand" "=d")10828 + (not:SI (match_operand:SI 1 "score_register_operand" "d")))]10829 + "(TARGET_SCORE3)"10830 + "not\t%0, %1"10831 [(set_attr "type" "arith")10832 + (set_attr "length" "4")10833 (set_attr "mode" "SI")])10834 10835 -(define_insn "one_cmplsi2_ucc"10836 +(define_insn "*one_cmplsi2_ucc_score7"10837 [(set (reg:CC_NZ CC_REGNUM)10838 (compare:CC_NZ (not:SI (match_operand:SI 1 "register_operand" "e,d"))10839 (const_int 0)))10840 (set (match_operand:SI 0 "register_operand" "=e,d")10841 (not:SI (match_dup 1)))]10842 - ""10843 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"10844 "@10845 not! %0, %110846 not.c %0, %1"10847 @@ -1023,12 +2067,25 @@10848 (set_attr "up_c" "yes")10849 (set_attr "mode" "SI")])10850 10851 -(define_insn "one_cmplsi2_cmp"10852 +(define_insn "*one_cmplsi2_ucc_score3"10853 + [(set (reg:CC_NZ CC_REGNUM)10854 + (compare:CC_NZ (not:SI (match_operand:SI 1 "score_register_operand" "d"))10855 + (const_int 0)))10856 + (set (match_operand:SI 0 "score_register_operand" "=d")10857 + (not:SI (match_dup 1)))]10858 + "(TARGET_SCORE3)"10859 + "not.c\t%0, %1"10860 + [(set_attr "type" "arith")10861 + (set_attr "length" "4")10862 + (set_attr "up_c" "yes")10863 + (set_attr "mode" "SI")])10864 +10865 +(define_insn "*one_cmplsi2_cmp_score7"10866 [(set (reg:CC_NZ CC_REGNUM)10867 (compare:CC_NZ (not:SI (match_operand:SI 1 "register_operand" "e,d"))10868 (const_int 0)))10869 (clobber (match_scratch:SI 0 "=e,d"))]10870 - ""10871 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"10872 "@10873 not! %0, %110874 not.c %0, %1"10875 @@ -1036,33 +2093,175 @@10876 (set_attr "up_c" "yes")10877 (set_attr "mode" "SI")])10878 10879 -(define_insn "rotlsi3"10880 +(define_insn "*one_cmplsi2_cmp_score3"10881 + [(set (reg:CC_NZ CC_REGNUM)10882 + (compare:CC_NZ (not:SI (match_operand:SI 1 "score_register_operand" "d"))10883 + (const_int 0)))10884 + (clobber (match_scratch:SI 0 "=d"))]10885 + "(TARGET_SCORE3)"10886 + "not.c\t%0, %1"10887 + [(set_attr "type" "arith")10888 + (set_attr "length" "4")10889 + (set_attr "up_c" "yes")10890 + (set_attr "mode" "SI")])10891 +10892 +(define_expand "rotlsi3"10893 + [(parallel10894 + [(set (match_operand:SI 0 "score_register_operand")10895 + (rotate:SI (match_operand:SI 1 "score_register_operand")10896 + (match_operand:SI 2 "arith_operand")))10897 + (clobber (reg:CC CC_REGNUM))])]10898 + ""10899 + ""10900 +)10901 +10902 +(define_insn "*rotlsi3_score7"10903 [(set (match_operand:SI 0 "register_operand" "=d,d")10904 (rotate:SI (match_operand:SI 1 "register_operand" "d,d")10905 (match_operand:SI 2 "arith_operand" "J,d")))10906 (clobber (reg:CC CC_REGNUM))]10907 - ""10908 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"10909 "@10910 roli.c %0, %1, %c210911 rol.c %0, %1, %2"10912 [(set_attr "type" "arith")10913 (set_attr "mode" "SI")])10914 10915 -(define_insn "rotrsi3"10916 +(define_insn "*rotlsi3_score3"10917 + [(set (match_operand:SI 0 "score_register_operand" "=d,d")10918 + (rotate:SI (match_operand:SI 1 "score_register_operand" "d,d")10919 + (match_operand:SI 2 "arith_operand" "J,d")))10920 + (clobber (reg:CC CC_REGNUM))]10921 + "(TARGET_SCORE3)"10922 + "@10923 + roli.c\t%0, %1, %c210924 + rol.c\t%0, %1, %2"10925 + [(set_attr "type" "arith")10926 + (set_attr "length" "4,4")10927 + (set_attr "mode" "SI")])10928 +10929 +(define_expand "rotrsi3"10930 + [(parallel10931 + [(set (match_operand:SI 0 "score_register_operand")10932 + (rotatert:SI (match_operand:SI 1 "score_register_operand")10933 + (match_operand:SI 2 "arith_operand")))10934 + (clobber (reg:CC CC_REGNUM))])]10935 + ""10936 + ""10937 +)10938 +10939 +(define_insn "*rotrsi3_score7"10940 [(set (match_operand:SI 0 "register_operand" "=d,d")10941 (rotatert:SI (match_operand:SI 1 "register_operand" "d,d")10942 (match_operand:SI 2 "arith_operand" "J,d")))10943 (clobber (reg:CC CC_REGNUM))]10944 - ""10945 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"10946 "@10947 rori.c %0, %1, %c210948 ror.c %0, %1, %2"10949 [(set_attr "type" "arith")10950 (set_attr "mode" "SI")])10951 10952 +(define_insn "*rotrsi3_score3"10953 + [(set (match_operand:SI 0 "score_register_operand" "=d,d")10954 + (rotatert:SI (match_operand:SI 1 "score_register_operand" "d,d")10955 + (match_operand:SI 2 "arith_operand" "J,d")))10956 + (clobber (reg:CC CC_REGNUM))]10957 + "(TARGET_SCORE3)"10958 + "@10959 + rori.c\t%0, %1, %c210960 + ror.c\t%0, %1, %2"10961 + [(set_attr "type" "arith")10962 + (set_attr "length" "4,4")10963 + (set_attr "mode" "SI")])10964 +10965 +(define_insn "cbrancheqz"10966 + [(set (pc) (if_then_else10967 + (eq (match_operand:SI 0 "score_register_operand" "d")10968 + (const_int 0))10969 + (label_ref (match_operand 1 "" ""))10970 + (pc)))10971 + (clobber (reg:CC CC_REGNUM))]10972 + "(TARGET_SCORE3)"10973 +{10974 + if (get_attr_length (insn) == 4)10975 + return \"bcmpeqz\t%0, %1\";10976 + else10977 + return \"cmpi!\t%0, 0\;beq!\t%1\";10978 +}10979 + [(set (attr "length")10980 + (if_then_else10981 + (and (ge (minus (match_dup 1) (pc)) (const_int -504))10982 + (le (minus (match_dup 1) (pc)) (const_int 502)))10983 + (const_int 4)10984 + (const_int 6)))])10985 +10986 +(define_insn "cbrancheq"10987 + [(set (pc) (if_then_else10988 + (eq (match_operand:SI 0 "score_register_operand" "d")10989 + (match_operand:SI 1 "score_register_operand" "d"))10990 + (label_ref (match_operand 2 "" ""))10991 + (pc)))10992 + (clobber (reg:CC CC_REGNUM))]10993 + "(TARGET_SCORE3)"10994 +{10995 + if (get_attr_length (insn) == 4)10996 + return \"bcmpeq\t%0, %1, %2\";10997 + else10998 + return \"cmp!\t%0, %1\;beq!\t%2\";10999 +}11000 + [(set (attr "length")11001 + (if_then_else11002 + (and (ge (minus (match_dup 2) (pc)) (const_int -504))11003 + (le (minus (match_dup 2) (pc)) (const_int 502)))11004 + (const_int 4)11005 + (const_int 6)))])11006 +11007 +(define_insn "cbranchnez"11008 + [(set (pc) (if_then_else11009 + (ne (match_operand:SI 0 "score_register_operand" "d")11010 + (const_int 0))11011 + (label_ref (match_operand 1 "" ""))11012 + (pc)))11013 + (clobber (reg:CC CC_REGNUM))]11014 + "(TARGET_SCORE3)"11015 +{11016 + if (get_attr_length (insn) == 4)11017 + return \"bcmpnez\t%0, %1\";11018 + else11019 + return \"cmpi!\t%0, 0\;bne\t%1\";11020 +}11021 + [(set (attr "length")11022 + (if_then_else11023 + (and (ge (minus (match_dup 1) (pc)) (const_int -504))11024 + (le (minus (match_dup 1) (pc)) (const_int 502)))11025 + (const_int 4)11026 + (const_int 6)))])11027 +11028 +(define_insn "cbranchne"11029 + [(set (pc) (if_then_else11030 + (ne (match_operand:SI 0 "score_register_operand" "d")11031 + (match_operand:SI 1 "score_register_operand" "d"))11032 + (label_ref (match_operand 2 "" ""))11033 + (pc)))11034 + (clobber (reg:CC CC_REGNUM))]11035 + "(TARGET_SCORE3)"11036 +{11037 + if (get_attr_length (insn) == 4)11038 + return \"bcmpne\t%0, %1, %2\";11039 + else11040 + return \"cmp!\t%0, %1\;bne\t%2\";11041 +}11042 + [(set (attr "length")11043 + (if_then_else11044 + (and (ge (minus (match_dup 2) (pc)) (const_int -504))11045 + (le (minus (match_dup 2) (pc)) (const_int 502)))11046 + (const_int 4)11047 + (const_int 6)))])11048 +11049 (define_expand "cmpsi"11050 - [(match_operand:SI 0 "register_operand" "")11051 - (match_operand:SI 1 "arith_operand" "")]11052 + [(match_operand:SI 0 "score_register_operand")11053 + (match_operand:SI 1 "arith_operand")]11054 ""11055 {11056 cmp_op0 = operands[0];11057 @@ -1070,11 +2269,11 @@11058 DONE;11059 })11060 11061 -(define_insn "cmpsi_nz"11062 +(define_insn "cmpsi_nz_score7"11063 [(set (reg:CC_NZ CC_REGNUM)11064 (compare:CC_NZ (match_operand:SI 0 "register_operand" "d,e,d")11065 (match_operand:SI 1 "arith_operand" "L,e,d")))]11066 - ""11067 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"11068 "@11069 cmpi.c %0, %c111070 cmp! %0, %111071 @@ -1083,11 +2282,25 @@11072 (set_attr "up_c" "yes")11073 (set_attr "mode" "SI")])11074 11075 -(define_insn "cmpsi_n"11076 +(define_insn "cmpsi_nz_score3"11077 + [(set (reg:CC_NZ CC_REGNUM)11078 + (compare:CC_NZ (match_operand:SI 0 "score_register_operand" "d,d,d")11079 + (match_operand:SI 1 "arith_operand" "O,L,d")))]11080 + "(TARGET_SCORE3)"11081 + "@11082 + cmpi!\t%0, %c111083 + cmpi.c\t%0, %c111084 + cmp!\t %0, %1"11085 + [(set_attr "type" "cmp")11086 + (set_attr "length" "2,4,2")11087 + (set_attr "up_c" "yes")11088 + (set_attr "mode" "SI")])11089 +11090 +(define_insn "cmpsi_n_score7"11091 [(set (reg:CC_N CC_REGNUM)11092 (compare:CC_N (match_operand:SI 0 "register_operand" "d,e,d")11093 (match_operand:SI 1 "arith_operand" "L,e,d")))]11094 - ""11095 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"11096 "@11097 cmpi.c %0, %c111098 cmp! %0, %111099 @@ -1096,12 +2309,26 @@11100 (set_attr "up_c" "yes")11101 (set_attr "mode" "SI")])11102 11103 -(define_insn "*cmpsi_to_addsi"11104 +(define_insn "cmpsi_n_score3"11105 + [(set (reg:CC_N CC_REGNUM)11106 + (compare:CC_N (match_operand:SI 0 "score_register_operand" "d,d,d")11107 + (match_operand:SI 1 "arith_operand" "O,L,d")))]11108 + "(TARGET_SCORE3)"11109 + "@11110 + cmpi!\t%0, %c111111 + cmpi.c\t%0, %c111112 + cmp!\t%0, %1"11113 + [(set_attr "type" "cmp")11114 + (set_attr "length" "2,4,2")11115 + (set_attr "up_c" "yes")11116 + (set_attr "mode" "SI")])11117 +11118 +(define_insn "*cmpsi_to_addsi_score7"11119 [(set (reg:CC_NZ CC_REGNUM)11120 (compare:CC_NZ (match_operand:SI 1 "register_operand" "0,d")11121 (neg:SI (match_operand:SI 2 "register_operand" "e,d"))))11122 (clobber (match_scratch:SI 0 "=e,d"))]11123 - ""11124 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"11125 "@11126 add! %0, %211127 add.c %0, %1, %2"11128 @@ -1109,11 +2336,23 @@11129 (set_attr "up_c" "yes")11130 (set_attr "mode" "SI")])11131 11132 -(define_insn "cmpsi_cc"11133 +(define_insn "*cmpsi_to_addsi_score3"11134 + [(set (reg:CC_NZ CC_REGNUM)11135 + (compare:CC_NZ (match_operand:SI 1 "score_register_operand" "d")11136 + (neg:SI (match_operand:SI 2 "score_register_operand" "d"))))11137 + (clobber (match_scratch:SI 0 "=d"))]11138 + "(TARGET_SCORE3)"11139 + "add.c\t%0, %1, %2"11140 + [(set_attr "type" "cmp")11141 + (set_attr "length" "4")11142 + (set_attr "up_c" "yes")11143 + (set_attr "mode" "SI")])11144 +11145 +(define_insn "cmpsi_cc_score7"11146 [(set (reg:CC CC_REGNUM)11147 (compare:CC (match_operand:SI 0 "register_operand" "d,e,d")11148 (match_operand:SI 1 "arith_operand" "L,e,d")))]11149 - ""11150 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"11151 "@11152 cmpi.c %0, %c111153 cmp! %0, %111154 @@ -1122,6 +2361,20 @@11155 (set_attr "up_c" "yes")11156 (set_attr "mode" "SI")])11157 11158 +(define_insn "cmpsi_cc_score3"11159 + [(set (reg:CC CC_REGNUM)11160 + (compare:CC (match_operand:SI 0 "score_register_operand" "d,d,d")11161 + (match_operand:SI 1 "arith_operand" "O,L,d")))]11162 + "(TARGET_SCORE3)"11163 + "@11164 + cmpi!\t%0, %c111165 + cmpi.c\t%0, %c111166 + cmp!\t%0, %1"11167 + [(set_attr "type" "cmp")11168 + (set_attr "length" "2,4,2")11169 + (set_attr "up_c" "yes")11170 + (set_attr "mode" "SI")])11171 +11172 (define_expand "beq"11173 [(set (pc)11174 (if_then_else (eq (reg:CC CC_REGNUM) (const_int 0))11175 @@ -1129,7 +2382,7 @@11176 (pc)))]11177 ""11178 {11179 - mda_gen_cmp (CCmode);11180 + score_gen_cmp (CCmode);11181 })11182 11183 (define_expand "bne"11184 @@ -1139,7 +2392,7 @@11185 (pc)))]11186 ""11187 {11188 - mda_gen_cmp (CCmode);11189 + score_gen_cmp (CCmode);11190 })11191 11192 (define_expand "bgt"11193 @@ -1149,7 +2402,7 @@11194 (pc)))]11195 ""11196 {11197 - mda_gen_cmp (CCmode);11198 + score_gen_cmp (CCmode);11199 })11200 11201 (define_expand "ble"11202 @@ -1159,7 +2412,7 @@11203 (pc)))]11204 ""11205 {11206 - mda_gen_cmp (CCmode);11207 + score_gen_cmp (CCmode);11208 })11209 11210 (define_expand "bge"11211 @@ -1169,7 +2422,7 @@11212 (pc)))]11213 ""11214 {11215 - mda_gen_cmp (CCmode);11216 + score_gen_cmp (CCmode);11217 })11218 11219 (define_expand "blt"11220 @@ -1179,7 +2432,7 @@11221 (pc)))]11222 ""11223 {11224 - mda_gen_cmp (CCmode);11225 + score_gen_cmp (CCmode);11226 })11227 11228 (define_expand "bgtu"11229 @@ -1189,7 +2442,7 @@11230 (pc)))]11231 ""11232 {11233 - mda_gen_cmp (CCmode);11234 + score_gen_cmp (CCmode);11235 })11236 11237 (define_expand "bleu"11238 @@ -1199,7 +2452,7 @@11239 (pc)))]11240 ""11241 {11242 - mda_gen_cmp (CCmode);11243 + score_gen_cmp (CCmode);11244 })11245 11246 (define_expand "bgeu"11247 @@ -1209,7 +2462,7 @@11248 (pc)))]11249 ""11250 {11251 - mda_gen_cmp (CCmode);11252 + score_gen_cmp (CCmode);11253 })11254 11255 (define_expand "bltu"11256 @@ -1219,10 +2472,10 @@11257 (pc)))]11258 ""11259 {11260 - mda_gen_cmp (CCmode);11261 + score_gen_cmp (CCmode);11262 })11263 11264 -(define_insn "branch_n"11265 +(define_insn "*branch_n_score7"11266 [(set (pc)11267 (if_then_else11268 (match_operator 0 "branch_n_operator"11269 @@ -1230,11 +2483,24 @@11270 (const_int 0)])11271 (label_ref (match_operand 1 "" ""))11272 (pc)))]11273 - ""11274 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"11275 "b%C0 %1"11276 [(set_attr "type" "branch")])11277 11278 -(define_insn "branch_nz"11279 +(define_insn "*branch_n_score3"11280 + [(set (pc)11281 + (if_then_else11282 + (match_operator 0 "branch_n_operator"11283 + [(reg:CC_N CC_REGNUM)11284 + (const_int 0)])11285 + (label_ref (match_operand 1 "" ""))11286 + (pc)))]11287 + "(TARGET_SCORE3)"11288 + "b%C0\t%1"11289 + [(set_attr "type" "branch")11290 + (set_attr "length" "4")])11291 +11292 +(define_insn "*branch_nz_score7"11293 [(set (pc)11294 (if_then_else11295 (match_operator 0 "branch_nz_operator"11296 @@ -1242,21 +2508,48 @@11297 (const_int 0)])11298 (label_ref (match_operand 1 "" ""))11299 (pc)))]11300 - ""11301 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"11302 "b%C0 %1"11303 [(set_attr "type" "branch")])11304 11305 -(define_insn "branch_cc"11306 +(define_insn "*branch_nz_score3"11307 [(set (pc)11308 (if_then_else11309 - (match_operator 0 "comparison_operator"11310 - [(reg:CC CC_REGNUM)11311 + (match_operator 0 "branch_nz_operator"11312 + [(reg:CC_NZ CC_REGNUM)11313 (const_int 0)])11314 (label_ref (match_operand 1 "" ""))11315 (pc)))]11316 - ""11317 - "b%C0 %1"11318 - [(set_attr "type" "branch")])11319 + "(TARGET_SCORE3)"11320 + "b%C0\t%1"11321 + [(set_attr "type" "branch")11322 + (set_attr "length" "4")])11323 +11324 +11325 +(define_insn "*branch_cc_score7"11326 + [(set (pc)11327 + (if_then_else11328 + (match_operator 0 "comparison_operator"11329 + [(reg:CC CC_REGNUM)11330 + (const_int 0)])11331 + (label_ref (match_operand 1 "" ""))11332 + (pc)))]11333 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"11334 + "b%C0 %1"11335 + [(set_attr "type" "branch")])11336 +11337 +(define_insn "*branch_cc_score3"11338 + [(set (pc)11339 + (if_then_else11340 + (match_operator 0 "comparison_operator"11341 + [(reg:CC CC_REGNUM)11342 + (const_int 0)])11343 + (label_ref (match_operand 1 "" ""))11344 + (pc)))]11345 + "(TARGET_SCORE3)"11346 + "b%C0\t%1"11347 + [(set_attr "type" "branch")11348 + (set_attr "length" "4")])11349 11350 (define_insn "jump"11351 [(set (pc)11352 @@ -1264,11 +2557,12 @@11353 ""11354 {11355 if (!flag_pic)11356 - return \"j %0\";11357 + return \"j\t%0\";11358 else11359 - return \"b %0\";11360 + return \"b\t%0\";11361 }11362 - [(set_attr "type" "jump")])11363 + [(set_attr "type" "jump")11364 + (set_attr "length" "4")])11365 11366 (define_expand "sibcall"11367 [(parallel [(call (match_operand 0 "" "")11368 @@ -1276,135 +2570,235 @@11369 (use (match_operand 2 "" ""))])]11370 ""11371 {11372 - mdx_call (operands, true);11373 + score_call (operands, true);11374 DONE;11375 })11376 11377 -(define_insn "sibcall_internal"11378 +(define_insn "sibcall_internal_score7"11379 [(call (mem:SI (match_operand:SI 0 "call_insn_operand" "t,Z"))11380 (match_operand 1 "" ""))11381 (clobber (reg:SI RT_REGNUM))]11382 - "SIBLING_CALL_P (insn)"11383 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)11384 + && SIBLING_CALL_P (insn)"11385 {11386 if (!flag_pic)11387 switch (which_alternative)11388 {11389 - case 0: return \"br%S0 %0\";11390 - case 1: return \"j %0\";11391 + case 0: return \"br%S0\t%0\";11392 + case 1: return \"j\t%0\";11393 default: gcc_unreachable ();11394 }11395 else11396 switch (which_alternative)11397 {11398 - case 0: return \"mv r29, %0\;br r29\";11399 - case 1: return \"la r29, %0\;br r29\";11400 + case 0: return \"mv\tr29, %0\;br\tr29\";11401 + case 1: return \"la\tr29, %0\;br\tr29\";11402 default: gcc_unreachable ();11403 }11404 }11405 [(set_attr "type" "call")])11406 11407 +(define_insn "sibcall_internal_score3"11408 + [(call (mem:SI (match_operand:SI 0 "call_insn_operand" "t,Z"))11409 + (match_operand 1 "" ""))11410 + (clobber (reg:SI RT_REGNUM))]11411 + "(TARGET_SCORE3) && (SIBLING_CALL_P (insn))"11412 +{11413 + if (!flag_pic)11414 + switch (which_alternative)11415 + {11416 + case 0: return \"br%S0\t%0\";11417 + case 1: return \"j\t%0\";11418 + default: gcc_unreachable ();11419 + }11420 + else11421 + switch (which_alternative)11422 + {11423 + case 0: return \"mv!\tr29, %0\;br!\tr29\";11424 + case 1: return \"ldi48\tr29, %0\;br!\tr29\";11425 + default: gcc_unreachable ();11426 + }11427 +}11428 + [(set_attr "type" "call")11429 + (set_attr "length" "4,8")])11430 +11431 (define_expand "sibcall_value"11432 [(parallel [(set (match_operand 0 "" "")11433 (call (match_operand 1 "" "") (match_operand 2 "" "")))11434 (use (match_operand 3 "" ""))])]11435 ""11436 {11437 - mdx_call_value (operands, true);11438 + score_call_value (operands, true);11439 DONE;11440 })11441 11442 -(define_insn "sibcall_value_internal"11443 +(define_insn "sibcall_value_internal_score7"11444 [(set (match_operand 0 "register_operand" "=d,d")11445 (call (mem:SI (match_operand:SI 1 "call_insn_operand" "t,Z"))11446 (match_operand 2 "" "")))11447 (clobber (reg:SI RT_REGNUM))]11448 - "SIBLING_CALL_P (insn)"11449 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)11450 + && SIBLING_CALL_P (insn)"11451 {11452 if (!flag_pic)11453 switch (which_alternative)11454 {11455 - case 0: return \"br%S1 %1\";11456 - case 1: return \"j %1\";11457 + case 0: return \"br%S1\t%1\";11458 + case 1: return \"j\t%1\";11459 default: gcc_unreachable ();11460 }11461 else11462 switch (which_alternative)11463 {11464 - case 0: return \"mv r29, %1\;br r29\";11465 - case 1: return \"la r29, %1\;br r29\";11466 + case 0: return \"mv\tr29, %1\;br\tr29\";11467 + case 1: return \"la\tr29, %1\;br\tr29\";11468 default: gcc_unreachable ();11469 }11470 }11471 [(set_attr "type" "call")])11472 11473 +(define_insn "sibcall_value_internal_score3"11474 + [(set (match_operand 0 "score_register_operand" "=d,d")11475 + (call (mem:SI (match_operand:SI 1 "call_insn_operand" "t,Z"))11476 + (match_operand 2 "" "")))11477 + (clobber (reg:SI RT_REGNUM))]11478 + "(TARGET_SCORE3) && (SIBLING_CALL_P (insn))"11479 +{11480 + if (!flag_pic)11481 + switch (which_alternative)11482 + {11483 + case 0: return \"br%S1\t%1\";11484 + case 1: return \"j\t%1\";11485 + default: gcc_unreachable ();11486 + }11487 + else11488 + switch (which_alternative)11489 + {11490 + case 0: return \"mv!\tr29, %1\;br!\tr29\";11491 + case 1: return \"ldi48\tr29, %1\;br!\tr29\";11492 + default: gcc_unreachable ();11493 + }11494 +}11495 + [(set_attr "length" "4,8")11496 + (set_attr "type" "call")])11497 +11498 (define_expand "call"11499 [(parallel [(call (match_operand 0 "" "") (match_operand 1 "" ""))11500 (use (match_operand 2 "" ""))])]11501 ""11502 {11503 - mdx_call (operands, false);11504 + score_call (operands, false);11505 DONE;11506 })11507 11508 -(define_insn "call_internal"11509 +(define_insn "call_internal_score7"11510 [(call (mem:SI (match_operand:SI 0 "call_insn_operand" "d,Z"))11511 (match_operand 1 "" ""))11512 (clobber (reg:SI RA_REGNUM))]11513 - ""11514 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"11515 {11516 if (!flag_pic)11517 switch (which_alternative)11518 {11519 - case 0: return \"brl%S0 %0\";11520 - case 1: return \"jl %0\";11521 + case 0: return \"brl%S0\t%0\";11522 + case 1: return \"jl\t%0\";11523 default: gcc_unreachable ();11524 }11525 else11526 switch (which_alternative)11527 {11528 - case 0: return \"mv r29, %0\;brl r29\";11529 - case 1: return \"la r29, %0\;brl r29\";11530 + case 0: return \"mv\tr29, %0\;brl\tr29\";11531 + case 1: return \"la\tr29, %0\;brl\tr29\";11532 default: gcc_unreachable ();11533 }11534 }11535 [(set_attr "type" "call")])11536 11537 +(define_insn "call_internal_score3"11538 + [(call (mem:SI (match_operand:SI 0 "call_insn_operand" "d,Z"))11539 + (match_operand 1 "" ""))11540 + (clobber (reg:SI RA_REGNUM))]11541 + "(TARGET_SCORE3)"11542 +{11543 + if (!flag_pic)11544 + switch (which_alternative)11545 + {11546 + case 0: return \"brl!\t%0\";11547 + case 1: return \"jl\t%0\";11548 + default: gcc_unreachable ();11549 + }11550 + else11551 + switch (which_alternative)11552 + {11553 + case 0: return \"mv!\tr29, %0\;brl!\tr29\";11554 + case 1: return \"ldi48\tr29, %0\;brl!\tr29\";11555 + default: gcc_unreachable ();11556 + }11557 +}11558 + [(set_attr "length" "4,8")11559 + (set_attr "type" "call")])11560 +11561 (define_expand "call_value"11562 [(parallel [(set (match_operand 0 "" "")11563 (call (match_operand 1 "" "") (match_operand 2 "" "")))11564 (use (match_operand 3 "" ""))])]11565 ""11566 {11567 - mdx_call_value (operands, false);11568 + score_call_value (operands, false);11569 DONE;11570 })11571 11572 -(define_insn "call_value_internal"11573 +(define_insn "call_value_internal_score7"11574 [(set (match_operand 0 "register_operand" "=d,d")11575 (call (mem:SI (match_operand:SI 1 "call_insn_operand" "d,Z"))11576 (match_operand 2 "" "")))11577 (clobber (reg:SI RA_REGNUM))]11578 - ""11579 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"11580 {11581 if (!flag_pic)11582 switch (which_alternative)11583 {11584 - case 0: return \"brl%S1 %1\";11585 - case 1: return \"jl %1\";11586 + case 0: return \"brl%S1\t%1\";11587 + case 1: return \"jl\t%1\";11588 default: gcc_unreachable ();11589 }11590 else11591 switch (which_alternative)11592 {11593 - case 0: return \"mv r29, %1\;brl r29\";11594 - case 1: return \"la r29, %1\;brl r29\";11595 + case 0: return \"mv\tr29, %1\;brl\tr29\";11596 + case 1: return \"la\tr29, %1\;brl\tr29\";11597 default: gcc_unreachable ();11598 }11599 }11600 [(set_attr "type" "call")])11601 11602 +(define_insn "call_value_internal_score3"11603 + [(set (match_operand 0 "score_register_operand" "=d,d")11604 + (call (mem:SI (match_operand:SI 1 "call_insn_operand" "d,Z"))11605 + (match_operand 2 "" "")))11606 + (clobber (reg:SI RA_REGNUM))]11607 + "(TARGET_SCORE3)"11608 +{11609 + if (!flag_pic)11610 + switch (which_alternative)11611 + {11612 + case 0: return \"brl!\t%1\";11613 + case 1: return \"jl\t%1\";11614 + default: gcc_unreachable ();11615 + }11616 + else11617 + switch (which_alternative)11618 + {11619 + case 0: return \"mv!\tr29, %1\;brl!\tr29\";11620 + case 1: return \"ldi48\tr29, %1\;brl!\tr29\";11621 + default: gcc_unreachable ();11622 + }11623 +}11624 + [(set_attr "length" "4,8")11625 + (set_attr "type" "call")])11626 +11627 (define_expand "indirect_jump"11628 - [(set (pc) (match_operand 0 "register_operand" "d"))]11629 + [(set (pc) (match_operand 0 "score_register_operand" "d"))]11630 ""11631 {11632 rtx dest;11633 @@ -1413,44 +2807,105 @@11634 || GET_MODE (dest) != Pmode)11635 operands[0] = copy_to_mode_reg (Pmode, dest);11636 11637 - emit_jump_insn (gen_indirect_jump_internal1 (operands[0]));11638 + emit_jump_insn (gen_indirect_jump_internal_score (operands[0]));11639 DONE;11640 })11641 11642 -(define_insn "indirect_jump_internal1"11643 - [(set (pc) (match_operand:SI 0 "register_operand" "d"))]11644 +(define_insn "indirect_jump_internal_score"11645 + [(set (pc) (match_operand:SI 0 "score_register_operand" "d"))]11646 ""11647 "br%S0 %0"11648 [(set_attr "type" "jump")])11649 11650 +(define_expand "casesi"11651 + [(match_operand:SI 0 "score_register_operand" "") ; index to jump on11652 + (match_operand:SI 1 "const_int_operand" "") ; lower bound11653 + (match_operand:SI 2 "const_int_operand" "") ; total range11654 + (match_operand:SI 3 "" "") ; table label11655 + (match_operand:SI 4 "" "")] ; Out of range label11656 + "TARGET_SCORE3"11657 +{11658 + rtx reg;11659 + if (operands[1] != const0_rtx)11660 + {11661 + reg = gen_reg_rtx (SImode);11662 + emit_insn (gen_addsi3 (reg, operands[0],11663 + GEN_INT (-INTVAL (operands[1]))));11664 + operands[0] = reg;11665 + }11666 +11667 + if (!CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'L'))11668 + operands[2] = force_reg (SImode, operands[2]);11669 +11670 + reg = gen_reg_rtx (SImode);11671 + emit_jump_insn (gen_score3_casesi_internal (operands[0], operands[2],11672 + operands[3], operands[4], reg));11673 + DONE;11674 +})11675 +11676 +(define_insn "score3_casesi_internal"11677 + [(parallel [(set (pc)11678 + (if_then_else11679 + (leu (match_operand:SI 0 "score_register_operand" "e")11680 + (match_operand:SI 1 "arith_operand" "dL"))11681 + (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))11682 + (label_ref (match_operand 2 "" ""))))11683 + (label_ref (match_operand 3 "" ""))))11684 + (clobber (reg:CC CC_REGNUM))11685 + (clobber (match_operand:SI 4 "score_register_operand" "=e"))11686 + (use (label_ref (match_dup 2)))])]11687 + "TARGET_SCORE3 && !flag_pic"11688 + "*11689 + return score_output_casesi(operands);11690 + "11691 + [(set_attr "length" "20")])11692 +11693 (define_expand "tablejump"11694 [(set (pc)11695 - (match_operand 0 "register_operand" "d"))11696 + (match_operand 0 "score_register_operand" "d"))11697 (use (label_ref (match_operand 1 "" "")))]11698 ""11699 {11700 - emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1]));11701 + if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)11702 + emit_jump_insn (gen_tablejump_internal_score7 (operands[0], operands[1]));11703 + else if (TARGET_SCORE3)11704 + emit_jump_insn (gen_tablejump_internal_score3 (operands[0], operands[1]));11705 +11706 DONE;11707 })11708 11709 -(define_insn "tablejump_internal1"11710 +(define_insn "tablejump_internal_score7"11711 [(set (pc)11712 (match_operand:SI 0 "register_operand" "d"))11713 (use (label_ref (match_operand 1 "" "")))]11714 - ""11715 - "*11716 - if (flag_pic)11717 - return \"mv r29, %0\;.cpadd r29\;br r29\";11718 - else11719 - return \"br%S0 %0\";11720 - "11721 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"11722 +{11723 + if (flag_pic)11724 + return \"mv\tr29, %0\;.cpadd\tr29\;br\tr29\";11725 + else11726 + return \"br%S0\t%0\";11727 +}11728 [(set_attr "type" "jump")])11729 11730 +(define_insn "tablejump_internal_score3"11731 + [(set (pc)11732 + (match_operand:SI 0 "score_register_operand" "d"))11733 + (use (label_ref (match_operand 1 "" "")))]11734 + "(TARGET_SCORE3)"11735 +{11736 + if (flag_pic)11737 + return \"mv!\tr29, %0\;.cpadd\tr29\;br!\tr29\";11738 + else11739 + return \"br%S0\t%0\";11740 +}11741 + [(set_attr "type" "jump")11742 + (set_attr "length" "8")])11743 +11744 (define_expand "prologue"11745 [(const_int 1)]11746 ""11747 {11748 - mdx_prologue ();11749 + score_prologue ();11750 DONE;11751 })11752 11753 @@ -1458,7 +2913,7 @@11754 [(const_int 2)]11755 ""11756 {11757 - mdx_epilogue (false);11758 + score_epilogue (false);11759 DONE;11760 })11761 11762 @@ -1466,15 +2921,22 @@11763 [(const_int 2)]11764 ""11765 {11766 - mdx_epilogue (true);11767 + score_epilogue (true);11768 DONE;11769 })11770 11771 -(define_insn "return_internal"11772 +(define_insn "return_internal_score7"11773 [(return)11774 (use (match_operand 0 "pmode_register_operand" "d"))]11775 - ""11776 - "br%S0 %0")11777 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"11778 + "br%S0\t%0")11779 +11780 +(define_insn "return_internal_score3"11781 + [(return)11782 + (use (match_operand 0 "pmode_register_operand" "d"))]11783 + "(TARGET_SCORE3)"11784 + "br%S0\t%0"11785 + [(set_attr "length" "4")])11786 11787 (define_insn "nop"11788 [(const_int 0)]11789 @@ -1482,26 +2944,49 @@11790 "#nop!"11791 )11792 11793 -(define_insn "cpload"11794 +(define_insn "cpload_score7"11795 [(unspec_volatile:SI [(const_int 1)] CPLOAD)]11796 - "flag_pic"11797 - ".cpload r29"11798 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)11799 + && flag_pic"11800 + ".cpload\tr29"11801 )11802 11803 -(define_insn "cprestore_use_fp"11804 +(define_insn "cpload_score3"11805 + [(unspec_volatile:SI [(const_int 1)] CPLOAD)]11806 + "(TARGET_SCORE3) && flag_pic"11807 + ".cpload\tr29"11808 + [(set_attr "length" "4")])11809 +11810 +(define_insn "cprestore_use_fp_score7"11811 [(unspec_volatile:SI [(match_operand:SI 0 "" "")] CPRESTORE)11812 (use (reg:SI FP_REGNUM))]11813 - "flag_pic"11814 - ".cprestore r2, %0"11815 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)11816 + && flag_pic"11817 + ".cprestore\tr2, %0"11818 )11819 11820 -(define_insn "cprestore_use_sp"11821 +(define_insn "cprestore_use_fp_score3"11822 + [(unspec_volatile:SI [(match_operand:SI 0 "" "")] CPRESTORE)11823 + (use (reg:SI FP_REGNUM))]11824 + "(TARGET_SCORE3) && flag_pic"11825 + ".cprestore\tr2, %0"11826 + [(set_attr "length" "4")])11827 +11828 +(define_insn "cprestore_use_sp_score7"11829 [(unspec_volatile:SI [(match_operand:SI 0 "" "")] CPRESTORE)11830 (use (reg:SI SP_REGNUM))]11831 - "flag_pic"11832 - ".cprestore r0, %0"11833 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)11834 + && flag_pic"11835 + ".cprestore\tr0, %0"11836 )11837 11838 +(define_insn "cprestore_use_sp_score3"11839 + [(unspec_volatile:SI [(match_operand:SI 0 "" "")] CPRESTORE)11840 + (use (reg:SI SP_REGNUM))]11841 + "(TARGET_SCORE3) && flag_pic"11842 + ".cprestore\tr0, %0"11843 + [(set_attr "length" "4")])11844 +11845 (define_expand "doloop_end"11846 [(use (match_operand 0 "" "")) ; loop pseudo11847 (use (match_operand 1 "" "")) ; iterations; zero if unknown11848 @@ -1509,20 +2994,20 @@11849 (use (match_operand 3 "" "")) ; loop level11850 (use (match_operand 4 "" ""))] ; label11851 "!TARGET_NHWLOOP"11852 - {11853 - if (INTVAL (operands[3]) > 1)11854 - FAIL;11855 +{11856 + if (INTVAL (operands[3]) > 1)11857 + FAIL;11858 11859 - if (GET_MODE (operands[0]) == SImode)11860 - {11861 - rtx sr0 = gen_rtx_REG (SImode, CN_REGNUM);11862 - emit_jump_insn (gen_doloop_end_si (sr0, operands[4]));11863 - }11864 - else11865 - FAIL;11866 + if (GET_MODE (operands[0]) == SImode)11867 + {11868 + rtx sr0 = gen_rtx_REG (SImode, CN_REGNUM);11869 + emit_jump_insn (gen_doloop_end_si (sr0, operands[4]));11870 + }11871 + else11872 + FAIL;11873 11874 - DONE;11875 - })11876 + DONE;11877 +})11878 11879 (define_insn "doloop_end_si"11880 [(set (pc)11881 @@ -1534,8 +3019,692 @@11882 (set (match_dup 0)11883 (plus:SI (match_dup 0)11884 (const_int -1)))11885 - (clobber (reg:CC CC_REGNUM))11886 -]11887 + (clobber (reg:CC CC_REGNUM))]11888 "!TARGET_NHWLOOP"11889 "bcnz %1"11890 - [(set_attr "type" "branch")])11891 + [(set_attr "type" "branch")11892 + (set_attr "length" "4")])11893 +11894 +(define_insn "pushsi_score7"11895 + [(set (match_operand:SI 0 "push_operand" "=<")11896 + (match_operand:SI 1 "register_operand" "d"))]11897 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"11898 + "push!\t%1, [r0]"11899 + [(set_attr "type" "store")11900 + (set_attr "mode" "SI")])11901 +11902 +(define_insn "pushsi_score3"11903 + [(set (match_operand:SI 0 "push_operand" "=<")11904 + (match_operand:SI 1 "register_operand" "d"))]11905 + "(TARGET_SCORE3)"11906 + "push!\t%1"11907 + [(set_attr "type" "store")11908 + (set_attr "length" "2")11909 + (set_attr "mode" "SI")])11910 +11911 +(define_insn "popsi_score7"11912 + [(set (match_operand:SI 0 "register_operand" "=d")11913 + (match_operand:SI 1 "pop_operand" ">"))]11914 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"11915 + "pop!\t%0, [r0]"11916 + [(set_attr "type" "store")11917 + (set_attr "mode" "SI")])11918 +11919 +(define_insn "popsi_score3"11920 + [(set (match_operand:SI 0 "register_operand" "=d")11921 + (match_operand:SI 1 "pop_operand" ">"))]11922 + "(TARGET_SCORE3)"11923 + "pop!\t%0"11924 + [(set_attr "type" "store")11925 + (set_attr "length" "2")11926 + (set_attr "mode" "SI")])11927 +11928 +(define_expand "load_multiple"11929 + [(match_par_dup 3 [(set (match_operand:SI 0 "" "")11930 + (match_operand:SI 1 "" ""))11931 + (use (match_operand:SI 2 "" ""))11932 + (clobber (reg:SI 0))])]11933 + "(TARGET_SCORE3)"11934 +{11935 + int regno, count, i;11936 +11937 + if (GET_CODE (operands[2]) != CONST_INT11938 + || INTVAL (operands[2]) < 211939 + || GET_CODE (operands[1]) != MEM11940 + || XEXP (operands[1], 0) != stack_pointer_rtx11941 + || GET_CODE (operands[0]) != REG)11942 + FAIL;11943 +11944 + count = INTVAL (operands[2]);11945 + regno = REGNO (operands[0]);11946 +11947 + operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));11948 +11949 + for (i = 0; i < count; i++)11950 + XVECEXP (operands[3], 0, i)11951 + = gen_rtx_SET (VOIDmode,11952 + gen_rtx_REG (SImode, regno + i),11953 + gen_rtx_MEM (SImode, gen_rtx_POST_INC (SImode, stack_pointer_rtx)));11954 +})11955 +11956 +(define_insn ""11957 + [(match_parallel 0 "score_load_multiple_operation"11958 + [(set (match_operand:SI 1 "register_operand" "=d")11959 + (mem:SI (post_inc:SI (reg:SI SP_REGNUM))))])]11960 + "(TARGET_SCORE3)"11961 +{11962 + return score_rpop (operands);11963 +}11964 + [(set_attr "length" "2")])11965 +11966 +(define_expand "store_multiple"11967 + [(match_par_dup 3 [(set (match_operand:SI 0 "" "")11968 + (match_operand:SI 1 "" ""))11969 + (use (match_operand:SI 2 "" ""))11970 + (clobber (reg:SI 0))])]11971 + "(TARGET_SCORE3)"11972 +{11973 + int regno, count, i;11974 +11975 + if (GET_CODE (operands[2]) != CONST_INT11976 + || INTVAL (operands[2]) < 211977 + || GET_CODE (operands[0]) != MEM11978 + || XEXP (operands[0], 0) != stack_pointer_rtx11979 + || GET_CODE (operands[1]) != REG)11980 + FAIL;11981 +11982 + count = INTVAL (operands[2]);11983 + regno = REGNO (operands[1]);11984 +11985 + operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));11986 +11987 + for (i = 0; i < count; i++)11988 + XVECEXP (operands[3], 0, i)11989 + = gen_rtx_SET (VOIDmode,11990 + gen_rtx_MEM (SImode, gen_rtx_PRE_DEC (SImode, stack_pointer_rtx)),11991 + gen_rtx_REG (SImode, regno + i));11992 +})11993 +11994 +(define_insn ""11995 + [(match_parallel 0 "score_store_multiple_operation"11996 + [(set (mem:SI (pre_dec:SI (reg:SI SP_REGNUM)))11997 + (match_operand:SI 1 "register_operand" "d"))])]11998 + "(TARGET_SCORE3)"11999 +{12000 + return score_rpush (operands);12001 +}12002 + [(set_attr "length" "2")])12003 +12004 +(define_peephole212005 + [(set (match_operand:SI 0 "g32reg_operand" "")12006 + (match_operand:SI 1 "loreg_operand" ""))12007 + (set (match_operand:SI 2 "g32reg_operand" "")12008 + (match_operand:SI 3 "hireg_operand" ""))]12009 + ""12010 + [(parallel12011 + [(set (match_dup 0) (match_dup 1))12012 + (set (match_dup 2) (match_dup 3))])])12013 +12014 +(define_peephole212015 + [(set (match_operand:SI 0 "g32reg_operand" "")12016 + (match_operand:SI 1 "hireg_operand" ""))12017 + (set (match_operand:SI 2 "g32reg_operand" "")12018 + (match_operand:SI 3 "loreg_operand" ""))]12019 + ""12020 + [(parallel12021 + [(set (match_dup 2) (match_dup 3))12022 + (set (match_dup 0) (match_dup 1))])])12023 +12024 +(define_insn "movhilo"12025 + [(parallel12026 + [(set (match_operand:SI 0 "register_operand" "=d")12027 + (match_operand:SI 1 "loreg_operand" ""))12028 + (set (match_operand:SI 2 "register_operand" "=d")12029 + (match_operand:SI 3 "hireg_operand" ""))])]12030 + ""12031 + "mfcehl\t%2, %0"12032 + [(set_attr "type" "fce")12033 + (set_attr "mode" "SI")])12034 +12035 +(define_expand "movsicc"12036 + [(set (match_operand:SI 0 "register_operand" "")12037 + (if_then_else:SI (match_operator 1 "comparison_operator"12038 + [(reg:CC CC_REGNUM) (const_int 0)])12039 + (match_operand:SI 2 "register_operand" "")12040 + (match_operand:SI 3 "register_operand" "")))]12041 + ""12042 +{12043 + score_movsicc (operands);12044 +})12045 +12046 +(define_insn "movsicc_internal_score7"12047 + [(set (match_operand:SI 0 "register_operand" "=d")12048 + (if_then_else:SI (match_operator 1 "comparison_operator"12049 + [(reg:CC CC_REGNUM) (const_int 0)])12050 + (match_operand:SI 2 "arith_operand" "d")12051 + (match_operand:SI 3 "arith_operand" "0")))]12052 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"12053 + "mv%C1\t%0, %2"12054 + [(set_attr "type" "cndmv")12055 + (set_attr "mode" "SI")])12056 +12057 +(define_insn "movsicc_internal_score3"12058 + [(set (match_operand:SI 0 "register_operand" "=d")12059 + (if_then_else:SI (match_operator 1 "comparison_operator"12060 + [(reg:CC CC_REGNUM) (const_int 0)])12061 + (match_operand:SI 2 "arith_operand" "d")12062 + (match_operand:SI 3 "arith_operand" "0")))]12063 + "(TARGET_SCORE3)"12064 + "mv%G1\t%0, %2"12065 + [(set_attr "type" "cndmv")12066 + (set_attr "length" "4")12067 + (set_attr "mode" "SI")])12068 +12069 +(define_insn "zero_extract_bittst_score7"12070 + [(set (reg:CC_NZ CC_REGNUM)12071 + (compare:CC_NZ (unspec:SI12072 + [(match_operand:SI 0 "register_operand" "*e,d")12073 + (match_operand:SI 1 "const_uimm5" "")]12074 + BITTST)12075 + (const_int 0)))]12076 + "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"12077 + "@12078 + bittst!\t%0, %c112079 + bittst.c\t%0, %c1"12080 + [(set_attr "type" "arith")12081 + (set_attr "up_c" "yes")12082 + (set_attr "mode" "SI")])12083 +12084 +(define_insn "zero_extract_bittst_score3"12085 + [(set (reg:CC_NZ CC_REGNUM)12086 + (compare:CC_NZ (unspec:SI12087 + [(match_operand:SI 0 "register_operand" "e,d")12088 + (match_operand:SI 1 "const_uimm5" "")]12089 + BITTST)12090 + (const_int 0)))]12091 + "(TARGET_SCORE3)"12092 + "@12093 + bittst!\t%0, %c112094 + bittst.c\t%0, %c1"12095 + [(set_attr "type" "arith")12096 + (set_attr "length" "2,4")12097 + (set_attr "up_c" "yes")12098 + (set_attr "mode" "SI")])12099 +12100 +(define_expand "extzv"12101 + [(set (match_operand:SI 0 "register_operand" "")12102 + (zero_extract (match_operand:SI 1 "memory_operand" "")12103 + (match_operand:SI 2 "immediate_operand" "")12104 + (match_operand:SI 3 "immediate_operand" "")))]12105 + "((TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)12106 + && (!TARGET_LITTLE_ENDIAN) && (TARGET_ULS))12107 + || (TARGET_SCORE3 && TARGET_ULS)"12108 +{12109 + if (score_unaligned_load (operands))12110 + DONE;12111 + else12112 + FAIL;12113 +})12114 +12115 +(define_expand "insv"12116 + [(set (zero_extract (match_operand:SI 0 "memory_operand" "")12117 + (match_operand:SI 1 "immediate_operand" "")12118 + (match_operand:SI 2 "immediate_operand" ""))12119 + (match_operand:SI 3 "register_operand" ""))]12120 + "((TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)12121 + && (!TARGET_LITTLE_ENDIAN) && (TARGET_ULS))12122 + || (TARGET_SCORE3 && TARGET_ULS)"12123 +{12124 + if (score_unaligned_store (operands))12125 + DONE;12126 + else12127 + FAIL;12128 +})12129 +12130 +(define_expand "extv"12131 + [(set (match_operand:SI 0 "register_operand" "")12132 + (sign_extract (match_operand:SI 1 "memory_operand" "")12133 + (match_operand:SI 2 "immediate_operand" "")12134 + (match_operand:SI 3 "immediate_operand" "")))]12135 + "((TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)12136 + && (!TARGET_LITTLE_ENDIAN) && (TARGET_ULS))12137 + || (TARGET_SCORE3 && TARGET_ULS)"12138 +{12139 + if (score_unaligned_load (operands))12140 + DONE;12141 + else12142 + FAIL;12143 +})12144 +12145 +(define_expand "movmemsi"12146 + [(parallel [(set (match_operand:BLK 0 "general_operand")12147 + (match_operand:BLK 1 "general_operand"))12148 + (use (match_operand:SI 2 ""))12149 + (use (match_operand:SI 3 "const_int_operand"))])]12150 + "((TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)12151 + && (TARGET_ULS))12152 + || (TARGET_SCORE3 && TARGET_ULS)"12153 +{12154 + if (score_block_move (operands))12155 + DONE;12156 + else12157 + FAIL;12158 +})12159 +12160 +(define_insn "move_lbu_a"12161 + [(set (match_operand:SI 0 "register_operand" "=d")12162 + (plus:SI (match_operand:SI 1 "register_operand" "0")12163 + (match_operand:SI 2 "const_simm12" "")))12164 + (set (match_operand:QI 3 "register_operand" "=d")12165 + (mem:QI (match_dup 1)))]12166 + ""12167 + "lbu\t%3, [%1]+, %2"12168 + [(set_attr "type" "load")12169 + (set_attr "length" "4")12170 + (set_attr "mode" "QI")])12171 +12172 +(define_insn "move_lhu_a"12173 + [(set (match_operand:SI 0 "register_operand" "=d")12174 + (plus:SI (match_operand:SI 1 "register_operand" "0")12175 + (match_operand:SI 2 "const_simm12" "")))12176 + (set (match_operand:HI 3 "register_operand" "=d")12177 + (mem:HI (match_dup 1)))]12178 + ""12179 + "lhu\t%3, [%1]+, %2"12180 + [(set_attr "type" "load")12181 + (set_attr "length" "4")12182 + (set_attr "mode" "HI")])12183 +12184 +(define_insn "move_lw_a"12185 + [(set (match_operand:SI 0 "register_operand" "=d")12186 + (plus:SI (match_operand:SI 1 "register_operand" "0")12187 + (match_operand:SI 2 "const_simm12" "")))12188 + (set (match_operand:SI 3 "register_operand" "=d")12189 + (mem:SI (match_dup 1)))]12190 + ""12191 + "lw\t%3, [%1]+, %2"12192 + [(set_attr "type" "load")12193 + (set_attr "length" "4")12194 + (set_attr "mode" "SI")])12195 +12196 +(define_insn "move_sb_a"12197 + [(set (match_operand:SI 0 "register_operand" "=d")12198 + (plus:SI (match_operand:SI 1 "register_operand" "0")12199 + (match_operand:SI 2 "const_simm12" "")))12200 + (set (mem:QI (match_dup 1))12201 + (match_operand:QI 3 "register_operand" "d"))]12202 + ""12203 + "sb\t%3, [%1]+, %2"12204 + [(set_attr "type" "store")12205 + (set_attr "length" "4")12206 + (set_attr "mode" "QI")])12207 +12208 +(define_insn "move_sh_a"12209 + [(set (match_operand:SI 0 "register_operand" "=d")12210 + (plus:SI (match_operand:SI 1 "register_operand" "0")12211 + (match_operand:SI 2 "const_simm12" "")))12212 + (set (mem:HI (match_dup 1))12213 + (match_operand:HI 3 "register_operand" "d"))]12214 + ""12215 + "sh\t%3, [%1]+, %2"12216 + [(set_attr "type" "store")12217 + (set_attr "length" "4")12218 + (set_attr "mode" "HI")])12219 +12220 +(define_insn "move_sw_a"12221 + [(set (match_operand:SI 0 "register_operand" "=d")12222 + (plus:SI (match_operand:SI 1 "register_operand" "0")12223 + (match_operand:SI 2 "const_simm12" "")))12224 + (set (mem:SI (match_dup 1))12225 + (match_operand:SI 3 "register_operand" "d"))]12226 + ""12227 + "sw\t%3, [%1]+, %2"12228 + [(set_attr "type" "store")12229 + (set_attr "length" "4")12230 + (set_attr "mode" "SI")])12231 +12232 +(define_insn "move_lbu_b"12233 + [(set (match_operand:SI 0 "register_operand" "=d")12234 + (plus:SI (match_operand:SI 1 "register_operand" "0")12235 + (match_operand:SI 2 "const_simm12" "")))12236 + (set (match_operand:QI 3 "register_operand" "=d")12237 + (mem:QI (plus:SI (match_dup 1)12238 + (match_dup 2))))]12239 + ""12240 + "lbu\t%3, [%1, %2]+"12241 + [(set_attr "type" "load")12242 + (set_attr "length" "4")12243 + (set_attr "mode" "QI")])12244 +12245 +(define_insn "move_lhu_b"12246 + [(set (match_operand:SI 0 "register_operand" "=d")12247 + (plus:SI (match_operand:SI 1 "register_operand" "0")12248 + (match_operand:SI 2 "const_simm12" "")))12249 + (set (match_operand:HI 3 "register_operand" "=d")12250 + (mem:HI (plus:SI (match_dup 1)12251 + (match_dup 2))))]12252 + ""12253 + "lhu\t%3, [%1, %2]+"12254 + [(set_attr "type" "load")12255 + (set_attr "length" "4")12256 + (set_attr "mode" "HI")])12257 +12258 +(define_insn "move_lw_b"12259 + [(set (match_operand:SI 0 "register_operand" "=d")12260 + (plus:SI (match_operand:SI 1 "register_operand" "0")12261 + (match_operand:SI 2 "const_simm12" "")))12262 + (set (match_operand:SI 3 "register_operand" "=d")12263 + (mem:SI (plus:SI (match_dup 1)12264 + (match_dup 2))))]12265 + ""12266 + "lw\t%3, [%1, %2]+"12267 + [(set_attr "type" "load")12268 + (set_attr "length" "4")12269 + (set_attr "mode" "SI")])12270 +12271 +(define_insn "move_sb_b"12272 + [(set (match_operand:SI 0 "register_operand" "=d")12273 + (plus:SI (match_operand:SI 1 "register_operand" "0")12274 + (match_operand:SI 2 "const_simm12" "")))12275 + (set (mem:QI (plus:SI (match_dup 1)12276 + (match_dup 2)))12277 + (match_operand:QI 3 "register_operand" "d"))]12278 + ""12279 + "sb\t%3, [%1, %2]+"12280 + [(set_attr "type" "store")12281 + (set_attr "length" "4")12282 + (set_attr "mode" "QI")])12283 +12284 +(define_insn "move_sh_b"12285 + [(set (match_operand:SI 0 "register_operand" "=d")12286 + (plus:SI (match_operand:SI 1 "register_operand" "0")12287 + (match_operand:SI 2 "const_simm12" "")))12288 + (set (mem:HI (plus:SI (match_dup 1)12289 + (match_dup 2)))12290 + (match_operand:HI 3 "register_operand" "d"))]12291 + ""12292 + "sh\t%3, [%1, %2]+"12293 + [(set_attr "type" "store")12294 + (set_attr "length" "4")12295 + (set_attr "mode" "HI")])12296 +12297 +(define_insn "move_sw_b"12298 + [(set (match_operand:SI 0 "register_operand" "=d")12299 + (plus:SI (match_operand:SI 1 "register_operand" "0")12300 + (match_operand:SI 2 "const_simm12" "")))12301 + (set (mem:SI (plus:SI (match_dup 1)12302 + (match_dup 2)))12303 + (match_operand:SI 3 "register_operand" "d"))]12304 + ""12305 + "sw\t%3, [%1, %2]+"12306 + [(set_attr "type" "store")12307 + (set_attr "length" "4")12308 + (set_attr "mode" "SI")])12309 +12310 +(define_insn "move_lcb"12311 + [(set (match_operand:SI 0 "register_operand" "=d")12312 + (plus:SI (match_operand:SI 1 "register_operand" "0")12313 + (const_int 4)))12314 + (set (reg:SI LC_REGNUM)12315 + (unspec:SI [(mem:BLK (match_dup 1))] LCB))]12316 + "((TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)12317 + && (!TARGET_LITTLE_ENDIAN) && (TARGET_ULS))12318 + || (TARGET_SCORE3 && TARGET_ULS)"12319 + "lcb\t[%1]+"12320 + [(set_attr "type" "load")12321 + (set_attr "length" "4")12322 + (set_attr "mode" "SI")])12323 +12324 +(define_insn "move_lcw"12325 + [(set (match_operand:SI 0 "register_operand" "=d")12326 + (plus:SI (match_operand:SI 1 "register_operand" "0")12327 + (const_int 4)))12328 + (set (match_operand:SI 2 "register_operand" "=d")12329 + (unspec:SI [(mem:BLK (match_dup 1))12330 + (reg:SI LC_REGNUM)] LCW))12331 + (set (reg:SI LC_REGNUM)12332 + (unspec:SI [(mem:BLK (match_dup 1))] LCB))]12333 + "((TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)12334 + && (!TARGET_LITTLE_ENDIAN) && (TARGET_ULS))12335 + || (TARGET_SCORE3 && TARGET_ULS)"12336 + "lcw\t%2, [%1]+"12337 + [(set_attr "type" "load")12338 + (set_attr "length" "4")12339 + (set_attr "mode" "SI")])12340 +12341 +(define_insn "move_lce"12342 + [(set (match_operand:SI 0 "register_operand" "=d")12343 + (plus:SI (match_operand:SI 1 "register_operand" "0")12344 + (const_int 4)))12345 + (set (match_operand:SI 2 "register_operand" "=d")12346 + (unspec:SI [(mem:BLK (match_dup 1))12347 + (reg:SI LC_REGNUM)] LCE))]12348 + "((TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)12349 + && (!TARGET_LITTLE_ENDIAN) && (TARGET_ULS))12350 + || (TARGET_SCORE3 && TARGET_ULS)"12351 + "lce\t%2, [%1]+"12352 + [(set_attr "type" "load")12353 + (set_attr "length" "4")12354 + (set_attr "mode" "SI")])12355 +12356 +(define_insn "move_scb"12357 + [(set (match_operand:SI 0 "register_operand" "=d")12358 + (plus:SI (match_operand:SI 1 "register_operand" "0")12359 + (const_int 4)))12360 + (set (mem:BLK (match_dup 1))12361 + (unspec:BLK [(match_operand:SI 2 "register_operand" "d")] SCB))12362 + (set (reg:SI SC_REGNUM)12363 + (unspec:SI [(match_dup 2)] SCLC))]12364 + "((TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)12365 + && (!TARGET_LITTLE_ENDIAN) && (TARGET_ULS))12366 + || (TARGET_SCORE3 && TARGET_ULS)"12367 + "scb\t%2, [%1]+"12368 + [(set_attr "type" "store")12369 + (set_attr "length" "4")12370 + (set_attr "mode" "SI")])12371 +12372 +(define_insn "move_scw"12373 + [(set (match_operand:SI 0 "register_operand" "=d")12374 + (plus:SI (match_operand:SI 1 "register_operand" "0")12375 + (const_int 4)))12376 + (set (mem:BLK (match_dup 1))12377 + (unspec:BLK [(match_operand:SI 2 "register_operand" "d")12378 + (reg:SI SC_REGNUM)] SCW))12379 + (set (reg:SI SC_REGNUM)12380 + (unspec:SI [(match_dup 2)] SCLC))]12381 + "((TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)12382 + && (!TARGET_LITTLE_ENDIAN) && (TARGET_ULS))12383 + || (TARGET_SCORE3 && TARGET_ULS)"12384 + "scw\t%2, [%1]+"12385 + [(set_attr "type" "store")12386 + (set_attr "length" "4")12387 + (set_attr "mode" "SI")])12388 +12389 +(define_insn "move_sce"12390 + [(set (match_operand:SI 0 "register_operand" "=d")12391 + (plus:SI (match_operand:SI 1 "register_operand" "0")12392 + (const_int 4)))12393 + (set (mem:BLK (match_dup 1))12394 + (unspec:BLK [(reg:SI SC_REGNUM)] SCE))]12395 + "((TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)12396 + && (!TARGET_LITTLE_ENDIAN) && (TARGET_ULS))12397 + || (TARGET_SCORE3 && TARGET_ULS)"12398 + "sce [%1]+"12399 + [(set_attr "type" "store")12400 + (set_attr "length" "4")12401 + (set_attr "mode" "SI")])12402 +12403 +(define_insn "andsi3_extzh"12404 + [(set (match_operand:SI 0 "register_operand" "=d")12405 + (and:SI (match_operand:SI 1 "register_operand" "d")12406 + (const_int 65535)))]12407 + ""12408 + "extzh\t%0, %1"12409 + [(set_attr "type" "arith")12410 + (set_attr "length" "4")12411 + (set_attr "mode" "SI")])12412 +12413 +(define_insn "clzsi2"12414 + [(set (match_operand:SI 0 "register_operand" "=d")12415 + (clz:SI (match_operand:SI 1 "register_operand" "d")))]12416 + "(TARGET_SCORE7D || TARGET_SCORE3)"12417 + "clz\t%0, %1"12418 + [(set_attr "type" "arith")12419 + (set_attr "mode" "SI")])12420 +12421 +(define_insn "smaxsi3"12422 + [(set (match_operand:SI 0 "register_operand" "=d")12423 + (smax:SI (match_operand:SI 1 "register_operand" "d")12424 + (match_operand:SI 2 "register_operand" "d")))]12425 + "(TARGET_SCORE7D || TARGET_SCORE3D)"12426 + "max\t%0, %1, %2"12427 + [(set_attr "type" "arith")12428 + (set_attr "mode" "SI")])12429 +12430 +(define_insn "sminsi3"12431 + [(set (match_operand:SI 0 "register_operand" "=d")12432 + (smin:SI (match_operand:SI 1 "register_operand" "d")12433 + (match_operand:SI 2 "register_operand" "d")))]12434 + "(TARGET_SCORE7D || TARGET_SCORE3D)"12435 + "min\t%0, %1, %2"12436 + [(set_attr "type" "arith")12437 + (set_attr "mode" "SI")])12438 +12439 +(define_insn "abssi2"12440 + [(set (match_operand:SI 0 "register_operand" "=d")12441 + (abs:SI (match_operand:SI 1 "register_operand" "d")))]12442 + "(TARGET_SCORE7D || TARGET_SCORE3D)"12443 + "abs\t%0, %1"12444 + [(set_attr "type" "arith")12445 + (set_attr "mode" "SI")])12446 +12447 +(define_insn "sffs"12448 + [(set (match_operand:SI 0 "register_operand" "=d")12449 + (unspec:SI [(match_operand:SI 1 "register_operand" "d")] SFFS))]12450 + "(TARGET_SCORE7D || TARGET_SCORE3D)"12451 + "bitrev\t%0, %1, r0\;clz\t%0, %0\;addi\t%0, 0x1"12452 + [(set_attr "type" "arith")12453 + (set_attr "mode" "SI")])12454 +12455 +(define_expand "ffssi2"12456 + [(set (match_operand:SI 0 "register_operand")12457 + (ffs:SI (match_operand:SI 1 "register_operand")))]12458 + "(TARGET_SCORE7D || TARGET_SCORE3D)"12459 +{12460 + emit_insn (gen_sffs (operands[0], operands[1]));12461 + emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_REG (CC_NZmode, CC_REGNUM),12462 + gen_rtx_COMPARE (CC_NZmode, operands[0],12463 + GEN_INT (33))));12464 + if (TARGET_SCORE7D)12465 + emit_insn (gen_movsicc_internal_score7 (operands[0],12466 + gen_rtx_fmt_ee (EQ, VOIDmode, operands[0], GEN_INT (33)),12467 + GEN_INT (0),12468 + operands[0]));12469 + else12470 + emit_insn (gen_movsicc_internal_score3 (operands[0],12471 + gen_rtx_fmt_ee (EQ, VOIDmode, operands[0], GEN_INT (33)),12472 + GEN_INT (0),12473 + operands[0]));12474 + DONE;12475 +})12476 +12477 +(define_peephole212478 + [(set (match_operand:SI 0 "loreg_operand" "")12479 + (match_operand:SI 1 "register_operand" ""))12480 + (set (match_operand:SI 2 "hireg_operand" "")12481 + (match_operand:SI 3 "register_operand" ""))]12482 + "(TARGET_SCORE7D || TARGET_SCORE3D)"12483 + [(parallel12484 + [(set (match_dup 0) (match_dup 1))12485 + (set (match_dup 2) (match_dup 3))])])12486 +12487 +(define_peephole212488 + [(set (match_operand:SI 0 "hireg_operand" "")12489 + (match_operand:SI 1 "register_operand" ""))12490 + (set (match_operand:SI 2 "loreg_operand" "")12491 + (match_operand:SI 3 "register_operand" ""))]12492 + "(TARGET_SCORE7D || TARGET_SCORE3D)"12493 + [(parallel12494 + [(set (match_dup 2) (match_dup 3))12495 + (set (match_dup 0) (match_dup 1))])])12496 +12497 +(define_insn "movtohilo"12498 + [(parallel12499 + [(set (match_operand:SI 0 "loreg_operand" "=l")12500 + (match_operand:SI 1 "register_operand" "d"))12501 + (set (match_operand:SI 2 "hireg_operand" "=h")12502 + (match_operand:SI 3 "register_operand" "d"))])]12503 + "(TARGET_SCORE7D || TARGET_SCORE3D)"12504 + "mtcehl\t%3, %1"12505 + [(set_attr "type" "fce")12506 + (set_attr "mode" "SI")])12507 +12508 +(define_insn "mulsi3addsi"12509 + [(set (match_operand:SI 0 "register_operand" "=l,l,d")12510 + (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "d,d,d")12511 + (match_operand:SI 3 "register_operand" "d,d,d"))12512 + (match_operand:SI 1 "register_operand" "0,d,l")))12513 + (clobber (reg:SI HI_REGNUM))]12514 + "(TARGET_SCORE7D || TARGET_SCORE3D)"12515 + "@12516 + mad\t%2, %312517 + mtcel%S1\t%1\;mad\t%2, %312518 + mad\t%2, %3\;mfcel%S0\t%0"12519 + [(set_attr "mode" "SI")])12520 +12521 +(define_insn "mulsi3subsi"12522 + [(set (match_operand:SI 0 "register_operand" "=l,l,d")12523 + (minus:SI (match_operand:SI 1 "register_operand" "0,d,l")12524 + (mult:SI (match_operand:SI 2 "register_operand" "d,d,d")12525 + (match_operand:SI 3 "register_operand" "d,d,d"))))12526 + (clobber (reg:SI HI_REGNUM))]12527 + "(TARGET_SCORE7D || TARGET_SCORE3D)"12528 + "@12529 + msb\t%2, %312530 + mtcel%S1\t%1\;msb\t%2, %312531 + msb\t%2, %3\;mfcel%S0\t%0"12532 + [(set_attr "mode" "SI")])12533 +12534 +(define_insn "mulsidi3adddi"12535 + [(set (match_operand:DI 0 "register_operand" "=x")12536 + (plus:DI (mult:DI12537 + (sign_extend:DI (match_operand:SI 2 "register_operand" "%d"))12538 + (sign_extend:DI (match_operand:SI 3 "register_operand" "d")))12539 + (match_operand:DI 1 "register_operand" "0")))]12540 + "(TARGET_SCORE7D || TARGET_SCORE3D)"12541 + "mad\t%2, %3"12542 + [(set_attr "mode" "DI")])12543 +12544 +(define_insn "umulsidi3adddi"12545 + [(set (match_operand:DI 0 "register_operand" "=x")12546 + (plus:DI (mult:DI12547 + (zero_extend:DI (match_operand:SI 2 "register_operand" "%d"))12548 + (zero_extend:DI (match_operand:SI 3 "register_operand" "d")))12549 + (match_operand:DI 1 "register_operand" "0")))]12550 + "(TARGET_SCORE7D || TARGET_SCORE3D)"12551 + "madu\t%2, %3"12552 + [(set_attr "mode" "DI")])12553 +12554 +(define_insn "mulsidi3subdi"12555 + [(set (match_operand:DI 0 "register_operand" "=x")12556 + (minus:DI12557 + (match_operand:DI 1 "register_operand" "0")12558 + (mult:DI12559 + (sign_extend:DI (match_operand:SI 2 "register_operand" "%d"))12560 + (sign_extend:DI (match_operand:SI 3 "register_operand" "d")))))]12561 + "(TARGET_SCORE7D || TARGET_SCORE3D)"12562 + "msb\t%2, %3"12563 + [(set_attr "mode" "DI")])12564 +12565 +(define_insn "umulsidi3subdi"12566 + [(set (match_operand:DI 0 "register_operand" "=x")12567 + (minus:DI12568 + (match_operand:DI 1 "register_operand" "0")12569 + (mult:DI (zero_extend:DI12570 + (match_operand:SI 2 "register_operand" "%d"))12571 + (zero_extend:DI12572 + (match_operand:SI 3 "register_operand" "d")))))]12573 + "(TARGET_SCORE7D || TARGET_SCORE3D)"12574 + "msbu\t%2, %3"12575 + [(set_attr "mode" "DI")])12576 +12577 diff -Naur gcc-4.2.2.orig/gcc/config/score/score-mdaux.c gcc-4.2.2/gcc/config/score/score-mdaux.c12578 --- gcc-4.2.2.orig/gcc/config/score/score-mdaux.c 2007-09-01 08:28:30.000000000 -070012579 +++ gcc-4.2.2/gcc/config/score/score-mdaux.c 1969-12-31 16:00:00.000000000 -080012580 @@ -1,1058 +0,0 @@12581 -/* score-mdaux.c for Sunplus S+CORE processor12582 - Copyright (C) 2005, 2007 Free Software Foundation, Inc.12583 - Contributed by Sunnorth12584 -12585 - This file is part of GCC.12586 -12587 - GCC is free software; you can redistribute it and/or modify it12588 - under the terms of the GNU General Public License as published12589 - by the Free Software Foundation; either version 3, or (at your12590 - option) any later version.12591 -12592 - GCC is distributed in the hope that it will be useful, but WITHOUT12593 - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY12594 - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public12595 - License for more details.12596 -12597 - You should have received a copy of the GNU General Public License12598 - along with GCC; see the file COPYING3. If not see12599 - <http://www.gnu.org/licenses/>. */12600 -12601 -#include "config.h"12602 -#include "system.h"12603 -#include "coretypes.h"12604 -#include "tm.h"12605 -#include <signal.h>12606 -#include "rtl.h"12607 -#include "regs.h"12608 -#include "hard-reg-set.h"12609 -#include "real.h"12610 -#include "insn-config.h"12611 -#include "conditions.h"12612 -#include "insn-attr.h"12613 -#include "recog.h"12614 -#include "toplev.h"12615 -#include "output.h"12616 -#include "tree.h"12617 -#include "function.h"12618 -#include "expr.h"12619 -#include "optabs.h"12620 -#include "flags.h"12621 -#include "reload.h"12622 -#include "tm_p.h"12623 -#include "ggc.h"12624 -#include "gstab.h"12625 -#include "hashtab.h"12626 -#include "debug.h"12627 -#include "target.h"12628 -#include "target-def.h"12629 -#include "integrate.h"12630 -#include "langhooks.h"12631 -#include "cfglayout.h"12632 -#include "score-mdaux.h"12633 -12634 -#define BITSET_P(VALUE, BIT) (((VALUE) & (1L << (BIT))) != 0)12635 -#define INS_BUF_SZ 10012636 -12637 -/* Define the information needed to generate branch insns. This is12638 - stored from the compare operation. */12639 -rtx cmp_op0, cmp_op1;12640 -12641 -static char ins[INS_BUF_SZ + 8];12642 -12643 -/* Return true if SYMBOL is a SYMBOL_REF and OFFSET + SYMBOL points12644 - to the same object as SYMBOL. */12645 -static int12646 -score_offset_within_object_p (rtx symbol, HOST_WIDE_INT offset)12647 -{12648 - if (GET_CODE (symbol) != SYMBOL_REF)12649 - return 0;12650 -12651 - if (CONSTANT_POOL_ADDRESS_P (symbol)12652 - && offset >= 012653 - && offset < (int)GET_MODE_SIZE (get_pool_mode (symbol)))12654 - return 1;12655 -12656 - if (SYMBOL_REF_DECL (symbol) != 012657 - && offset >= 012658 - && offset < int_size_in_bytes (TREE_TYPE (SYMBOL_REF_DECL (symbol))))12659 - return 1;12660 -12661 - return 0;12662 -}12663 -12664 -/* Split X into a base and a constant offset, storing them in *BASE12665 - and *OFFSET respectively. */12666 -static void12667 -score_split_const (rtx x, rtx *base, HOST_WIDE_INT *offset)12668 -{12669 - *offset = 0;12670 -12671 - if (GET_CODE (x) == CONST)12672 - x = XEXP (x, 0);12673 -12674 - if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)12675 - {12676 - *offset += INTVAL (XEXP (x, 1));12677 - x = XEXP (x, 0);12678 - }12679 -12680 - *base = x;12681 -}12682 -12683 -/* Classify symbol X, which must be a SYMBOL_REF or a LABEL_REF. */12684 -static enum12685 -score_symbol_type score_classify_symbol (rtx x)12686 -{12687 - if (GET_CODE (x) == LABEL_REF)12688 - return SYMBOL_GENERAL;12689 -12690 - gcc_assert (GET_CODE (x) == SYMBOL_REF);12691 -12692 - if (CONSTANT_POOL_ADDRESS_P (x))12693 - {12694 - if (GET_MODE_SIZE (get_pool_mode (x)) <= SCORE_SDATA_MAX)12695 - return SYMBOL_SMALL_DATA;12696 - return SYMBOL_GENERAL;12697 - }12698 - if (SYMBOL_REF_SMALL_P (x))12699 - return SYMBOL_SMALL_DATA;12700 - return SYMBOL_GENERAL;12701 -}12702 -12703 -/* Return true if the current function must save REGNO. */12704 -static int12705 -score_save_reg_p (unsigned int regno)12706 -{12707 - /* Check call-saved registers. */12708 - if (regs_ever_live[regno] && !call_used_regs[regno])12709 - return 1;12710 -12711 - /* We need to save the old frame pointer before setting up a new one. */12712 - if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)12713 - return 1;12714 -12715 - /* We need to save the incoming return address if it is ever clobbered12716 - within the function. */12717 - if (regno == RA_REGNUM && regs_ever_live[regno])12718 - return 1;12719 -12720 - return 0;12721 -}12722 -12723 -/* Return one word of double-word value OP, taking into account the fixed12724 - endianness of certain registers. HIGH_P is true to select the high part,12725 - false to select the low part. */12726 -static rtx12727 -subw (rtx op, int high_p)12728 -{12729 - unsigned int byte;12730 - enum machine_mode mode = GET_MODE (op);12731 -12732 - if (mode == VOIDmode)12733 - mode = DImode;12734 -12735 - byte = (TARGET_LITTLE_ENDIAN ? high_p : !high_p) ? UNITS_PER_WORD : 0;12736 -12737 - if (GET_CODE (op) == REG && REGNO (op) == HI_REGNUM)12738 - return gen_rtx_REG (SImode, high_p ? HI_REGNUM : LO_REGNUM);12739 -12740 - if (GET_CODE (op) == MEM)12741 - return adjust_address (op, SImode, byte);12742 -12743 - return simplify_gen_subreg (SImode, op, mode, byte);12744 -}12745 -12746 -struct score_frame_info *12747 -mda_cached_frame (void)12748 -{12749 - static struct score_frame_info _frame_info;12750 - return &_frame_info;12751 -}12752 -12753 -/* Return the bytes needed to compute the frame pointer from the current12754 - stack pointer. SIZE is the size (in bytes) of the local variables. */12755 -struct score_frame_info *12756 -mda_compute_frame_size (HOST_WIDE_INT size)12757 -{12758 - unsigned int regno;12759 - struct score_frame_info *f = mda_cached_frame ();12760 -12761 - memset (f, 0, sizeof (struct score_frame_info));12762 - f->gp_reg_size = 0;12763 - f->mask = 0;12764 - f->var_size = SCORE_STACK_ALIGN (size);12765 - f->args_size = current_function_outgoing_args_size;12766 - f->cprestore_size = flag_pic ? UNITS_PER_WORD : 0;12767 - if (f->var_size == 0 && current_function_is_leaf)12768 - f->args_size = f->cprestore_size = 0;12769 -12770 - if (f->args_size == 0 && current_function_calls_alloca)12771 - f->args_size = UNITS_PER_WORD;12772 -12773 - f->total_size = f->var_size + f->args_size + f->cprestore_size;12774 - for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)12775 - {12776 - if (score_save_reg_p (regno))12777 - {12778 - f->gp_reg_size += GET_MODE_SIZE (SImode);12779 - f->mask |= 1 << (regno - GP_REG_FIRST);12780 - }12781 - }12782 -12783 - if (current_function_calls_eh_return)12784 - {12785 - unsigned int i;12786 - for (i = 0;; ++i)12787 - {12788 - regno = EH_RETURN_DATA_REGNO (i);12789 - if (regno == INVALID_REGNUM)12790 - break;12791 - f->gp_reg_size += GET_MODE_SIZE (SImode);12792 - f->mask |= 1 << (regno - GP_REG_FIRST);12793 - }12794 - }12795 -12796 - f->total_size += f->gp_reg_size;12797 - f->num_gp = f->gp_reg_size / UNITS_PER_WORD;12798 -12799 - if (f->mask)12800 - {12801 - HOST_WIDE_INT offset;12802 - offset = (f->args_size + f->cprestore_size + f->var_size12803 - + f->gp_reg_size - GET_MODE_SIZE (SImode));12804 - f->gp_sp_offset = offset;12805 - }12806 - else12807 - f->gp_sp_offset = 0;12808 -12809 - return f;12810 -}12811 -12812 -/* Generate the prologue instructions for entry into a S+core function. */12813 -void12814 -mdx_prologue (void)12815 -{12816 -#define EMIT_PL(_rtx) RTX_FRAME_RELATED_P (_rtx) = 112817 -12818 - struct score_frame_info *f = mda_compute_frame_size (get_frame_size ());12819 - HOST_WIDE_INT size;12820 - int regno;12821 -12822 - size = f->total_size - f->gp_reg_size;12823 -12824 - if (flag_pic)12825 - emit_insn (gen_cpload ());12826 -12827 - for (regno = (int) GP_REG_LAST; regno >= (int) GP_REG_FIRST; regno--)12828 - {12829 - if (BITSET_P (f->mask, regno - GP_REG_FIRST))12830 - {12831 - rtx mem = gen_rtx_MEM (SImode,12832 - gen_rtx_PRE_DEC (SImode, stack_pointer_rtx));12833 - rtx reg = gen_rtx_REG (SImode, regno);12834 - if (!current_function_calls_eh_return)12835 - MEM_READONLY_P (mem) = 1;12836 - EMIT_PL (emit_insn (gen_pushsi (mem, reg)));12837 - }12838 - }12839 -12840 - if (size > 0)12841 - {12842 - rtx insn;12843 -12844 - if (CONST_OK_FOR_LETTER_P (-size, 'L'))12845 - EMIT_PL (emit_insn (gen_add3_insn (stack_pointer_rtx,12846 - stack_pointer_rtx,12847 - GEN_INT (-size))));12848 - else12849 - {12850 - EMIT_PL (emit_move_insn (gen_rtx_REG (Pmode, PROLOGUE_TEMP_REGNUM),12851 - GEN_INT (size)));12852 - EMIT_PL (emit_insn12853 - (gen_sub3_insn (stack_pointer_rtx,12854 - stack_pointer_rtx,12855 - gen_rtx_REG (Pmode,12856 - PROLOGUE_TEMP_REGNUM))));12857 - }12858 - insn = get_last_insn ();12859 - REG_NOTES (insn) =12860 - alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,12861 - gen_rtx_SET (VOIDmode, stack_pointer_rtx,12862 - plus_constant (stack_pointer_rtx,12863 - -size)),12864 - REG_NOTES (insn));12865 - }12866 -12867 - if (frame_pointer_needed)12868 - EMIT_PL (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx));12869 -12870 - if (flag_pic && f->cprestore_size)12871 - {12872 - if (frame_pointer_needed)12873 - emit_insn (gen_cprestore_use_fp (GEN_INT (size - f->cprestore_size)));12874 - else12875 - emit_insn (gen_cprestore_use_sp (GEN_INT (size - f->cprestore_size)));12876 - }12877 -12878 -#undef EMIT_PL12879 -}12880 -12881 -/* Generate the epilogue instructions in a S+core function. */12882 -void12883 -mdx_epilogue (int sibcall_p)12884 -{12885 - struct score_frame_info *f = mda_compute_frame_size (get_frame_size ());12886 - HOST_WIDE_INT size;12887 - int regno;12888 - rtx base;12889 -12890 - size = f->total_size - f->gp_reg_size;12891 -12892 - if (!frame_pointer_needed)12893 - base = stack_pointer_rtx;12894 - else12895 - base = hard_frame_pointer_rtx;12896 -12897 - if (size)12898 - {12899 - if (CONST_OK_FOR_LETTER_P (size, 'L'))12900 - emit_insn (gen_add3_insn (base, base, GEN_INT (size)));12901 - else12902 - {12903 - emit_move_insn (gen_rtx_REG (Pmode, EPILOGUE_TEMP_REGNUM),12904 - GEN_INT (size));12905 - emit_insn (gen_add3_insn (base, base,12906 - gen_rtx_REG (Pmode,12907 - EPILOGUE_TEMP_REGNUM)));12908 - }12909 - }12910 -12911 - if (base != stack_pointer_rtx)12912 - emit_move_insn (stack_pointer_rtx, base);12913 -12914 - if (current_function_calls_eh_return)12915 - emit_insn (gen_add3_insn (stack_pointer_rtx,12916 - stack_pointer_rtx,12917 - EH_RETURN_STACKADJ_RTX));12918 -12919 - for (regno = (int) GP_REG_FIRST; regno <= (int) GP_REG_LAST; regno++)12920 - {12921 - if (BITSET_P (f->mask, regno - GP_REG_FIRST))12922 - {12923 - rtx mem = gen_rtx_MEM (SImode,12924 - gen_rtx_POST_INC (SImode, stack_pointer_rtx));12925 - rtx reg = gen_rtx_REG (SImode, regno);12926 -12927 - if (!current_function_calls_eh_return)12928 - MEM_READONLY_P (mem) = 1;12929 -12930 - emit_insn (gen_popsi (reg, mem));12931 - }12932 - }12933 -12934 - if (!sibcall_p)12935 - emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, RA_REGNUM)));12936 -}12937 -12938 -/* Return true if X is a valid base register for the given mode.12939 - Allow only hard registers if STRICT. */12940 -int12941 -mda_valid_base_register_p (rtx x, int strict)12942 -{12943 - if (!strict && GET_CODE (x) == SUBREG)12944 - x = SUBREG_REG (x);12945 -12946 - return (GET_CODE (x) == REG12947 - && score_regno_mode_ok_for_base_p (REGNO (x), strict));12948 -}12949 -12950 -/* Return true if X is a valid address for machine mode MODE. If it is,12951 - fill in INFO appropriately. STRICT is true if we should only accept12952 - hard base registers. */12953 -int12954 -mda_classify_address (struct score_address_info *info,12955 - enum machine_mode mode, rtx x, int strict)12956 -{12957 - info->code = GET_CODE (x);12958 -12959 - switch (info->code)12960 - {12961 - case REG:12962 - case SUBREG:12963 - info->type = ADD_REG;12964 - info->reg = x;12965 - info->offset = const0_rtx;12966 - return mda_valid_base_register_p (info->reg, strict);12967 - case PLUS:12968 - info->type = ADD_REG;12969 - info->reg = XEXP (x, 0);12970 - info->offset = XEXP (x, 1);12971 - return (mda_valid_base_register_p (info->reg, strict)12972 - && GET_CODE (info->offset) == CONST_INT12973 - && IMM_IN_RANGE (INTVAL (info->offset), 15, 1));12974 - case PRE_DEC:12975 - case POST_DEC:12976 - case PRE_INC:12977 - case POST_INC:12978 - if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (SImode))12979 - return false;12980 - info->type = ADD_REG;12981 - info->reg = XEXP (x, 0);12982 - info->offset = GEN_INT (GET_MODE_SIZE (mode));12983 - return mda_valid_base_register_p (info->reg, strict);12984 - case CONST_INT:12985 - info->type = ADD_CONST_INT;12986 - return IMM_IN_RANGE (INTVAL (x), 15, 1);12987 - case CONST:12988 - case LABEL_REF:12989 - case SYMBOL_REF:12990 - info->type = ADD_SYMBOLIC;12991 - return (mda_symbolic_constant_p (x, &info->symbol_type)12992 - && (info->symbol_type == SYMBOL_GENERAL12993 - || info->symbol_type == SYMBOL_SMALL_DATA));12994 - default:12995 - return 0;12996 - }12997 -}12998 -12999 -void13000 -mda_gen_cmp (enum machine_mode mode)13001 -{13002 - emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, CC_REGNUM),13003 - gen_rtx_COMPARE (mode, cmp_op0, cmp_op1)));13004 -}13005 -13006 -/* Return true if X is a symbolic constant that can be calculated in13007 - the same way as a bare symbol. If it is, store the type of the13008 - symbol in *SYMBOL_TYPE. */13009 -int13010 -mda_symbolic_constant_p (rtx x, enum score_symbol_type *symbol_type)13011 -{13012 - HOST_WIDE_INT offset;13013 -13014 - score_split_const (x, &x, &offset);13015 - if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)13016 - *symbol_type = score_classify_symbol (x);13017 - else13018 - return 0;13019 -13020 - if (offset == 0)13021 - return 1;13022 -13023 - /* if offset > 15bit, must reload */13024 - if (!IMM_IN_RANGE (offset, 15, 1))13025 - return 0;13026 -13027 - switch (*symbol_type)13028 - {13029 - case SYMBOL_GENERAL:13030 - return 1;13031 - case SYMBOL_SMALL_DATA:13032 - return score_offset_within_object_p (x, offset);13033 - }13034 - gcc_unreachable ();13035 -}13036 -13037 -void13038 -mdx_movsicc (rtx *ops)13039 -{13040 - enum machine_mode mode;13041 -13042 - mode = score_select_cc_mode (GET_CODE (ops[1]), ops[2], ops[3]);13043 - emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, CC_REGNUM),13044 - gen_rtx_COMPARE (mode, cmp_op0, cmp_op1)));13045 -}13046 -13047 -/* Call and sibcall pattern all need call this function. */13048 -void13049 -mdx_call (rtx *ops, bool sib)13050 -{13051 - rtx addr = XEXP (ops[0], 0);13052 - if (!call_insn_operand (addr, VOIDmode))13053 - {13054 - rtx oaddr = addr;13055 - addr = gen_reg_rtx (Pmode);13056 - gen_move_insn (addr, oaddr);13057 - }13058 -13059 - if (sib)13060 - emit_call_insn (gen_sibcall_internal (addr, ops[1]));13061 - else13062 - emit_call_insn (gen_call_internal (addr, ops[1]));13063 -}13064 -13065 -/* Call value and sibcall value pattern all need call this function. */13066 -void13067 -mdx_call_value (rtx *ops, bool sib)13068 -{13069 - rtx result = ops[0];13070 - rtx addr = XEXP (ops[1], 0);13071 - rtx arg = ops[2];13072 -13073 - if (!call_insn_operand (addr, VOIDmode))13074 - {13075 - rtx oaddr = addr;13076 - addr = gen_reg_rtx (Pmode);13077 - gen_move_insn (addr, oaddr);13078 - }13079 -13080 - if (sib)13081 - emit_call_insn (gen_sibcall_value_internal (result, addr, arg));13082 - else13083 - emit_call_insn (gen_call_value_internal (result, addr, arg));13084 -}13085 -13086 -/* Machine Split */13087 -void13088 -mds_movdi (rtx *ops)13089 -{13090 - rtx dst = ops[0];13091 - rtx src = ops[1];13092 - rtx dst0 = subw (dst, 0);13093 - rtx dst1 = subw (dst, 1);13094 - rtx src0 = subw (src, 0);13095 - rtx src1 = subw (src, 1);13096 -13097 - if (GET_CODE (dst0) == REG && reg_overlap_mentioned_p (dst0, src))13098 - {13099 - emit_move_insn (dst1, src1);13100 - emit_move_insn (dst0, src0);13101 - }13102 - else13103 - {13104 - emit_move_insn (dst0, src0);13105 - emit_move_insn (dst1, src1);13106 - }13107 -}13108 -13109 -void13110 -mds_zero_extract_andi (rtx *ops)13111 -{13112 - if (INTVAL (ops[1]) == 1 && const_uimm5 (ops[2], SImode))13113 - emit_insn (gen_zero_extract_bittst (ops[0], ops[2]));13114 - else13115 - {13116 - unsigned HOST_WIDE_INT mask;13117 - mask = (0xffffffffU & ((1U << INTVAL (ops[1])) - 1U));13118 - mask = mask << INTVAL (ops[2]);13119 - emit_insn (gen_andsi3_cmp (ops[3], ops[0],13120 - gen_int_mode (mask, SImode)));13121 - }13122 -}13123 -13124 -/* Check addr could be present as PRE/POST mode. */13125 -static bool13126 -mda_pindex_mem (rtx addr)13127 -{13128 - if (GET_CODE (addr) == MEM)13129 - {13130 - switch (GET_CODE (XEXP (addr, 0)))13131 - {13132 - case PRE_DEC:13133 - case POST_DEC:13134 - case PRE_INC:13135 - case POST_INC:13136 - return true;13137 - default:13138 - break;13139 - }13140 - }13141 - return false;13142 -}13143 -13144 -/* Output asm code for ld/sw insn. */13145 -static int13146 -pr_addr_post (rtx *ops, int idata, int iaddr, char *ip, enum mda_mem_unit unit)13147 -{13148 - struct score_address_info ai;13149 -13150 - gcc_assert (GET_CODE (ops[idata]) == REG);13151 - gcc_assert (mda_classify_address (&ai, SImode, XEXP (ops[iaddr], 0), true));13152 -13153 - if (!mda_pindex_mem (ops[iaddr])13154 - && ai.type == ADD_REG13155 - && GET_CODE (ai.offset) == CONST_INT13156 - && G16_REG_P (REGNO (ops[idata]))13157 - && G16_REG_P (REGNO (ai.reg)))13158 - {13159 - if (INTVAL (ai.offset) == 0)13160 - {13161 - ops[iaddr] = ai.reg;13162 - return snprintf (ip, INS_BUF_SZ,13163 - "! %%%d, [%%%d]", idata, iaddr);13164 - }13165 - if (REGNO (ai.reg) == HARD_FRAME_POINTER_REGNUM)13166 - {13167 - HOST_WIDE_INT offset = INTVAL (ai.offset);13168 - if (MDA_ALIGN_UNIT (offset, unit)13169 - && CONST_OK_FOR_LETTER_P (offset >> unit, 'J'))13170 - {13171 - ops[iaddr] = ai.offset;13172 - return snprintf (ip, INS_BUF_SZ,13173 - "p! %%%d, %%c%d", idata, iaddr);13174 - }13175 - }13176 - }13177 - return snprintf (ip, INS_BUF_SZ, " %%%d, %%a%d", idata, iaddr);13178 -}13179 -13180 -/* Output asm insn for load. */13181 -const char *13182 -mdp_linsn (rtx *ops, enum mda_mem_unit unit, bool sign)13183 -{13184 - const char *pre_ins[] =13185 - {"lbu", "lhu", "lw", "??", "lb", "lh", "lw", "??"};13186 - char *ip;13187 -13188 - strcpy (ins, pre_ins[(sign ? 4 : 0) + unit]);13189 - ip = ins + strlen (ins);13190 -13191 - if ((!sign && unit != MDA_HWORD)13192 - || (sign && unit != MDA_BYTE))13193 - pr_addr_post (ops, 0, 1, ip, unit);13194 - else13195 - snprintf (ip, INS_BUF_SZ, " %%0, %%a1");13196 -13197 - return ins;13198 -}13199 -13200 -/* Output asm insn for store. */13201 -const char *13202 -mdp_sinsn (rtx *ops, enum mda_mem_unit unit)13203 -{13204 - const char *pre_ins[] = {"sb", "sh", "sw"};13205 - char *ip;13206 -13207 - strcpy (ins, pre_ins[unit]);13208 - ip = ins + strlen (ins);13209 - pr_addr_post (ops, 1, 0, ip, unit);13210 - return ins;13211 -}13212 -13213 -/* Output asm insn for load immediate. */13214 -const char *13215 -mdp_limm (rtx *ops)13216 -{13217 - HOST_WIDE_INT v;13218 -13219 - gcc_assert (GET_CODE (ops[0]) == REG);13220 - gcc_assert (GET_CODE (ops[1]) == CONST_INT);13221 -13222 - v = INTVAL (ops[1]);13223 - if (G16_REG_P (REGNO (ops[0])) && IMM_IN_RANGE (v, 8, 0))13224 - return "ldiu! %0, %c1";13225 - else if (IMM_IN_RANGE (v, 16, 1))13226 - return "ldi %0, %c1";13227 - else if ((v & 0xffff) == 0)13228 - return "ldis %0, %U1";13229 - else13230 - return "li %0, %c1";13231 -}13232 -13233 -/* Output asm insn for move. */13234 -const char *13235 -mdp_move (rtx *ops)13236 -{13237 - gcc_assert (GET_CODE (ops[0]) == REG);13238 - gcc_assert (GET_CODE (ops[1]) == REG);13239 -13240 - if (G16_REG_P (REGNO (ops[0])))13241 - {13242 - if (G16_REG_P (REGNO (ops[1])))13243 - return "mv! %0, %1";13244 - else13245 - return "mlfh! %0, %1";13246 - }13247 - else if (G16_REG_P (REGNO (ops[1])))13248 - return "mhfl! %0, %1";13249 - else13250 - return "mv %0, %1";13251 -}13252 -13253 -/* Emit lcb/lce insns. */13254 -bool13255 -mdx_unaligned_load (rtx *ops)13256 -{13257 - rtx dst = ops[0];13258 - rtx src = ops[1];13259 - rtx len = ops[2];13260 - rtx off = ops[3];13261 - rtx addr_reg;13262 -13263 - if (INTVAL (len) != BITS_PER_WORD13264 - || (INTVAL (off) % BITS_PER_UNIT) != 0)13265 - return false;13266 -13267 - gcc_assert (GET_MODE_SIZE (GET_MODE (dst)) == GET_MODE_SIZE (SImode));13268 -13269 - addr_reg = copy_addr_to_reg (XEXP (src, 0));13270 - emit_insn (gen_move_lcb (addr_reg, addr_reg));13271 - emit_insn (gen_move_lce (addr_reg, addr_reg, dst));13272 -13273 - return true;13274 -}13275 -13276 -/* Emit scb/sce insns. */13277 -bool13278 -mdx_unaligned_store (rtx *ops)13279 -{13280 - rtx dst = ops[0];13281 - rtx len = ops[1];13282 - rtx off = ops[2];13283 - rtx src = ops[3];13284 - rtx addr_reg;13285 -13286 - if (INTVAL(len) != BITS_PER_WORD13287 - || (INTVAL(off) % BITS_PER_UNIT) != 0)13288 - return false;13289 -13290 - gcc_assert (GET_MODE_SIZE (GET_MODE (src)) == GET_MODE_SIZE (SImode));13291 -13292 - addr_reg = copy_addr_to_reg (XEXP (dst, 0));13293 - emit_insn (gen_move_scb (addr_reg, addr_reg, src));13294 - emit_insn (gen_move_sce (addr_reg, addr_reg));13295 -13296 - return true;13297 -}13298 -13299 -/* If length is short, generate move insns straight. */13300 -static void13301 -mdx_block_move_straight (rtx dst, rtx src, HOST_WIDE_INT length)13302 -{13303 - HOST_WIDE_INT leftover;13304 - int i, reg_count;13305 - rtx *regs;13306 -13307 - leftover = length % UNITS_PER_WORD;13308 - length -= leftover;13309 - reg_count = length / UNITS_PER_WORD;13310 -13311 - regs = alloca (sizeof (rtx) * reg_count);13312 - for (i = 0; i < reg_count; i++)13313 - regs[i] = gen_reg_rtx (SImode);13314 -13315 - /* Load from src to regs. */13316 - if (MEM_ALIGN (src) >= BITS_PER_WORD)13317 - {13318 - HOST_WIDE_INT offset = 0;13319 - for (i = 0; i < reg_count; offset += UNITS_PER_WORD, i++)13320 - emit_move_insn (regs[i], adjust_address (src, SImode, offset));13321 - }13322 - else if (reg_count >= 1)13323 - {13324 - rtx src_reg = copy_addr_to_reg (XEXP (src, 0));13325 -13326 - emit_insn (gen_move_lcb (src_reg, src_reg));13327 - for (i = 0; i < (reg_count - 1); i++)13328 - emit_insn (gen_move_lcw (src_reg, src_reg, regs[i]));13329 - emit_insn (gen_move_lce (src_reg, src_reg, regs[i]));13330 - }13331 -13332 - /* Store regs to dest. */13333 - if (MEM_ALIGN (dst) >= BITS_PER_WORD)13334 - {13335 - HOST_WIDE_INT offset = 0;13336 - for (i = 0; i < reg_count; offset += UNITS_PER_WORD, i++)13337 - emit_move_insn (adjust_address (dst, SImode, offset), regs[i]);13338 - }13339 - else if (reg_count >= 1)13340 - {13341 - rtx dst_reg = copy_addr_to_reg (XEXP (dst, 0));13342 -13343 - emit_insn (gen_move_scb (dst_reg, dst_reg, regs[0]));13344 - for (i = 1; i < reg_count; i++)13345 - emit_insn (gen_move_scw (dst_reg, dst_reg, regs[i]));13346 - emit_insn (gen_move_sce (dst_reg, dst_reg));13347 - }13348 -13349 - /* Mop up any left-over bytes. */13350 - if (leftover > 0)13351 - {13352 - src = adjust_address (src, BLKmode, length);13353 - dst = adjust_address (dst, BLKmode, length);13354 - move_by_pieces (dst, src, leftover,13355 - MIN (MEM_ALIGN (src), MEM_ALIGN (dst)), 0);13356 - }13357 -}13358 -13359 -/* Generate loop head when dst or src is unaligned. */13360 -static void13361 -mdx_block_move_loop_head (rtx dst_reg, HOST_WIDE_INT dst_align,13362 - rtx src_reg, HOST_WIDE_INT src_align,13363 - HOST_WIDE_INT length)13364 -{13365 - bool src_unaligned = (src_align < BITS_PER_WORD);13366 - bool dst_unaligned = (dst_align < BITS_PER_WORD);13367 -13368 - rtx temp = gen_reg_rtx (SImode);13369 -13370 - gcc_assert (length == UNITS_PER_WORD);13371 -13372 - if (src_unaligned)13373 - {13374 - emit_insn (gen_move_lcb (src_reg, src_reg));13375 - emit_insn (gen_move_lcw (src_reg, src_reg, temp));13376 - }13377 - else13378 - emit_insn (gen_move_lw_a (src_reg,13379 - src_reg, gen_int_mode (4, SImode), temp));13380 -13381 - if (dst_unaligned)13382 - emit_insn (gen_move_scb (dst_reg, dst_reg, temp));13383 - else13384 - emit_insn (gen_move_sw_a (dst_reg,13385 - dst_reg, gen_int_mode (4, SImode), temp));13386 -}13387 -13388 -/* Generate loop body, copy length bytes per iteration. */13389 -static void13390 -mdx_block_move_loop_body (rtx dst_reg, HOST_WIDE_INT dst_align,13391 - rtx src_reg, HOST_WIDE_INT src_align,13392 - HOST_WIDE_INT length)13393 -{13394 - int reg_count = length / UNITS_PER_WORD;13395 - rtx *regs = alloca (sizeof (rtx) * reg_count);13396 - int i;13397 - bool src_unaligned = (src_align < BITS_PER_WORD);13398 - bool dst_unaligned = (dst_align < BITS_PER_WORD);13399 -13400 - for (i = 0; i < reg_count; i++)13401 - regs[i] = gen_reg_rtx (SImode);13402 -13403 - if (src_unaligned)13404 - {13405 - for (i = 0; i < reg_count; i++)13406 - emit_insn (gen_move_lcw (src_reg, src_reg, regs[i]));13407 - }13408 - else13409 - {13410 - for (i = 0; i < reg_count; i++)13411 - emit_insn (gen_move_lw_a (src_reg,13412 - src_reg, gen_int_mode (4, SImode), regs[i]));13413 - }13414 -13415 - if (dst_unaligned)13416 - {13417 - for (i = 0; i < reg_count; i++)13418 - emit_insn (gen_move_scw (dst_reg, dst_reg, regs[i]));13419 - }13420 - else13421 - {13422 - for (i = 0; i < reg_count; i++)13423 - emit_insn (gen_move_sw_a (dst_reg,13424 - dst_reg, gen_int_mode (4, SImode), regs[i]));13425 - }13426 -}13427 -13428 -/* Generate loop foot, copy the leftover bytes. */13429 -static void13430 -mdx_block_move_loop_foot (rtx dst_reg, HOST_WIDE_INT dst_align,13431 - rtx src_reg, HOST_WIDE_INT src_align,13432 - HOST_WIDE_INT length)13433 -{13434 - bool src_unaligned = (src_align < BITS_PER_WORD);13435 - bool dst_unaligned = (dst_align < BITS_PER_WORD);13436 -13437 - HOST_WIDE_INT leftover;13438 -13439 - leftover = length % UNITS_PER_WORD;13440 - length -= leftover;13441 -13442 - if (length > 0)13443 - mdx_block_move_loop_body (dst_reg, dst_align,13444 - src_reg, src_align, length);13445 -13446 - if (dst_unaligned)13447 - emit_insn (gen_move_sce (dst_reg, dst_reg));13448 -13449 - if (leftover > 0)13450 - {13451 - HOST_WIDE_INT src_adj = src_unaligned ? -4 : 0;13452 - HOST_WIDE_INT dst_adj = dst_unaligned ? -4 : 0;13453 - rtx temp;13454 -13455 - gcc_assert (leftover < UNITS_PER_WORD);13456 -13457 - if (leftover >= UNITS_PER_WORD / 213458 - && src_align >= BITS_PER_WORD / 213459 - && dst_align >= BITS_PER_WORD / 2)13460 - {13461 - temp = gen_reg_rtx (HImode);13462 - emit_insn (gen_move_lhu_b (src_reg, src_reg,13463 - gen_int_mode (src_adj, SImode), temp));13464 - emit_insn (gen_move_sh_b (dst_reg, dst_reg,13465 - gen_int_mode (dst_adj, SImode), temp));13466 - leftover -= UNITS_PER_WORD / 2;13467 - src_adj = UNITS_PER_WORD / 2;13468 - dst_adj = UNITS_PER_WORD / 2;13469 - }13470 -13471 - while (leftover > 0)13472 - {13473 - temp = gen_reg_rtx (QImode);13474 - emit_insn (gen_move_lbu_b (src_reg, src_reg,13475 - gen_int_mode (src_adj, SImode), temp));13476 - emit_insn (gen_move_sb_b (dst_reg, dst_reg,13477 - gen_int_mode (dst_adj, SImode), temp));13478 - leftover--;13479 - src_adj = 1;13480 - dst_adj = 1;13481 - }13482 - }13483 -}13484 -13485 -#define MIN_MOVE_REGS 313486 -#define MIN_MOVE_BYTES (MIN_MOVE_REGS * UNITS_PER_WORD)13487 -#define MAX_MOVE_REGS 413488 -#define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)13489 -13490 -/* The length is large, generate a loop if necessary.13491 - The loop is consisted by loop head/body/foot. */13492 -static void13493 -mdx_block_move_loop (rtx dst, rtx src, HOST_WIDE_INT length)13494 -{13495 - HOST_WIDE_INT src_align = MEM_ALIGN (src);13496 - HOST_WIDE_INT dst_align = MEM_ALIGN (dst);13497 - HOST_WIDE_INT loop_mov_bytes;13498 - HOST_WIDE_INT iteration = 0;13499 - HOST_WIDE_INT head_length = 0, leftover;13500 - rtx label, src_reg, dst_reg, final_dst;13501 -13502 - bool gen_loop_head = (src_align < BITS_PER_WORD13503 - || dst_align < BITS_PER_WORD);13504 -13505 - if (gen_loop_head)13506 - head_length += UNITS_PER_WORD;13507 -13508 - for (loop_mov_bytes = MAX_MOVE_BYTES;13509 - loop_mov_bytes >= MIN_MOVE_BYTES;13510 - loop_mov_bytes -= UNITS_PER_WORD)13511 - {13512 - iteration = (length - head_length) / loop_mov_bytes;13513 - if (iteration > 1)13514 - break;13515 - }13516 - if (iteration <= 1)13517 - {13518 - mdx_block_move_straight (dst, src, length);13519 - return;13520 - }13521 -13522 - leftover = (length - head_length) % loop_mov_bytes;13523 - length -= leftover;13524 -13525 - src_reg = copy_addr_to_reg (XEXP (src, 0));13526 - dst_reg = copy_addr_to_reg (XEXP (dst, 0));13527 - final_dst = expand_simple_binop (Pmode, PLUS, dst_reg, GEN_INT (length),13528 - 0, 0, OPTAB_WIDEN);13529 -13530 - if (gen_loop_head)13531 - mdx_block_move_loop_head (dst_reg, dst_align,13532 - src_reg, src_align, head_length);13533 -13534 - label = gen_label_rtx ();13535 - emit_label (label);13536 -13537 - mdx_block_move_loop_body (dst_reg, dst_align,13538 - src_reg, src_align, loop_mov_bytes);13539 -13540 - emit_insn (gen_cmpsi (dst_reg, final_dst));13541 - emit_jump_insn (gen_bne (label));13542 -13543 - mdx_block_move_loop_foot (dst_reg, dst_align,13544 - src_reg, src_align, leftover);13545 -}13546 -13547 -/* Generate block move, for misc.md: "movmemsi". */13548 -bool13549 -mdx_block_move (rtx *ops)13550 -{13551 - rtx dst = ops[0];13552 - rtx src = ops[1];13553 - rtx length = ops[2];13554 -13555 - if (TARGET_LITTLE_ENDIAN13556 - && (MEM_ALIGN (src) < BITS_PER_WORD || MEM_ALIGN (dst) < BITS_PER_WORD)13557 - && INTVAL (length) >= UNITS_PER_WORD)13558 - return false;13559 -13560 - if (GET_CODE (length) == CONST_INT)13561 - {13562 - if (INTVAL (length) <= 2 * MAX_MOVE_BYTES)13563 - {13564 - mdx_block_move_straight (dst, src, INTVAL (length));13565 - return true;13566 - }13567 - else if (optimize &&13568 - !(flag_unroll_loops || flag_unroll_all_loops))13569 - {13570 - mdx_block_move_loop (dst, src, INTVAL (length));13571 - return true;13572 - }13573 - }13574 - return false;13575 -}13576 -13577 -/* Generate add insn. */13578 -const char *13579 -mdp_select_add_imm (rtx *ops, bool set_cc)13580 -{13581 - HOST_WIDE_INT v = INTVAL (ops[2]);13582 -13583 - gcc_assert (GET_CODE (ops[2]) == CONST_INT);13584 - gcc_assert (REGNO (ops[0]) == REGNO (ops[1]));13585 -13586 - if (set_cc && G16_REG_P (REGNO (ops[0])))13587 - {13588 - if (v > 0 && IMM_IS_POW_OF_2 ((unsigned HOST_WIDE_INT) v, 0, 15))13589 - {13590 - ops[2] = GEN_INT (ffs (v) - 1);13591 - return "addei! %0, %c2";13592 - }13593 -13594 - if (v < 0 && IMM_IS_POW_OF_2 ((unsigned HOST_WIDE_INT) (-v), 0, 15))13595 - {13596 - ops[2] = GEN_INT (ffs (-v) - 1);13597 - return "subei! %0, %c2";13598 - }13599 - }13600 -13601 - if (set_cc)13602 - return "addi.c %0, %c2";13603 - else13604 - return "addi %0, %c2";13605 -}13606 -13607 -/* Output arith insn. */13608 -const char *13609 -mdp_select (rtx *ops, const char *inst_pre,13610 - bool commu, const char *letter, bool set_cc)13611 -{13612 - gcc_assert (GET_CODE (ops[0]) == REG);13613 - gcc_assert (GET_CODE (ops[1]) == REG);13614 -13615 - if (set_cc && G16_REG_P (REGNO (ops[0]))13616 - && (GET_CODE (ops[2]) == REG ? G16_REG_P (REGNO (ops[2])) : 1)13617 - && REGNO (ops[0]) == REGNO (ops[1]))13618 - {13619 - snprintf (ins, INS_BUF_SZ, "%s! %%0, %%%s2", inst_pre, letter);13620 - return ins;13621 - }13622 -13623 - if (commu && set_cc && G16_REG_P (REGNO (ops[0]))13624 - && G16_REG_P (REGNO (ops[1]))13625 - && REGNO (ops[0]) == REGNO (ops[2]))13626 - {13627 - gcc_assert (GET_CODE (ops[2]) == REG);13628 - snprintf (ins, INS_BUF_SZ, "%s! %%0, %%%s1", inst_pre, letter);13629 - return ins;13630 - }13631 -13632 - if (set_cc)13633 - snprintf (ins, INS_BUF_SZ, "%s.c %%0, %%1, %%%s2", inst_pre, letter);13634 - else13635 - snprintf (ins, INS_BUF_SZ, "%s %%0, %%1, %%%s2", inst_pre, letter);13636 - return ins;13637 -}13638 -13639 diff -Naur gcc-4.2.2.orig/gcc/config/score/score-mdaux.h gcc-4.2.2/gcc/config/score/score-mdaux.h13640 --- gcc-4.2.2.orig/gcc/config/score/score-mdaux.h 2007-09-01 08:28:30.000000000 -070013641 +++ gcc-4.2.2/gcc/config/score/score-mdaux.h 1969-12-31 16:00:00.000000000 -080013642 @@ -1,115 +0,0 @@13643 -/* score-mdaux.h for Sunplus S+CORE processor13644 - Copyright (C) 2005, 2007 Free Software Foundation, Inc.13645 - Contributed by Sunnorth13646 -13647 - This file is part of GCC.13648 -13649 - GCC is free software; you can redistribute it and/or modify it13650 - under the terms of the GNU General Public License as published13651 - by the Free Software Foundation; either version 3, or (at your13652 - option) any later version.13653 -13654 - GCC is distributed in the hope that it will be useful, but WITHOUT13655 - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY13656 - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public13657 - License for more details.13658 -13659 - You should have received a copy of the GNU General Public License13660 - along with GCC; see the file COPYING3. If not see13661 - <http://www.gnu.org/licenses/>. */13662 -13663 -#ifndef SCORE_MDAUX_062113664 -#define SCORE_MDAUX_062113665 -13666 -/* Machine Auxiliary Functions. */13667 -enum score_address_type13668 -{13669 - ADD_REG,13670 - ADD_CONST_INT,13671 - ADD_SYMBOLIC13672 -};13673 -#ifdef RTX_CODE13674 -struct score_address_info13675 -{13676 - enum score_address_type type;13677 - rtx reg;13678 - rtx offset;13679 - enum rtx_code code;13680 - enum score_symbol_type symbol_type;13681 -};13682 -#endif13683 -13684 -struct score_frame_info13685 -{13686 - HOST_WIDE_INT total_size; /* bytes that the entire frame takes up */13687 - HOST_WIDE_INT var_size; /* bytes that variables take up */13688 - HOST_WIDE_INT args_size; /* bytes that outgoing arguments take up */13689 - HOST_WIDE_INT gp_reg_size; /* bytes needed to store gp regs */13690 - HOST_WIDE_INT gp_sp_offset; /* offset from new sp to store gp registers */13691 - HOST_WIDE_INT cprestore_size; /* # bytes that the .cprestore slot takes up */13692 - unsigned int mask; /* mask of saved gp registers */13693 - int num_gp; /* number of gp registers saved */13694 -};13695 -13696 -typedef void (*score_save_restore_fn) (rtx, rtx);13697 -13698 -int mda_valid_base_register_p (rtx x, int strict);13699 -13700 -#ifdef RTX_CODE13701 -int mda_classify_address (struct score_address_info *info,13702 - enum machine_mode mode, rtx x, int strict);13703 -13704 -struct score_frame_info *mda_compute_frame_size (HOST_WIDE_INT size);13705 -13706 -struct score_frame_info *mda_cached_frame (void);13707 -13708 -void mda_gen_cmp (enum machine_mode mode);13709 -#endif13710 -13711 -int mda_symbolic_constant_p (rtx x, enum score_symbol_type *symbol_type);13712 -13713 -int mda_bp (void);13714 -13715 -/* Machine Expand. */13716 -void mdx_prologue (void);13717 -13718 -void mdx_epilogue (int sibcall_p);13719 -13720 -void mdx_movsicc (rtx *ops);13721 -13722 -void mdx_call (rtx *ops, bool sibcall);13723 -13724 -void mdx_call_value (rtx *ops, bool sibcall);13725 -13726 -/* Machine Split. */13727 -void mds_movdi (rtx *ops);13728 -13729 -void mds_zero_extract_andi (rtx *ops);13730 -13731 -/* Machine Print. */13732 -enum mda_mem_unit {MDA_BYTE = 0, MDA_HWORD = 1, MDA_WORD = 2};13733 -13734 -#define MDA_ALIGN_UNIT(V, UNIT) !(V & ((1 << UNIT) - 1))13735 -13736 -const char * mdp_linsn (rtx *ops, enum mda_mem_unit unit, bool sign);13737 -13738 -const char * mdp_sinsn (rtx *ops, enum mda_mem_unit unit);13739 -13740 -const char * mdp_select_add_imm (rtx *ops, bool set_cc);13741 -13742 -const char * mdp_select (rtx *ops, const char *inst_pre,13743 - bool commu, const char *letter, bool set_cc);13744 -13745 -const char * mdp_limm (rtx *ops);13746 -13747 -const char * mdp_move (rtx *ops);13748 -13749 -/* Machine unaligned memory load/store. */13750 -bool mdx_unaligned_load (rtx* ops);13751 -13752 -bool mdx_unaligned_store (rtx* ops);13753 -13754 -bool mdx_block_move (rtx* ops);13755 -13756 -#endif13757 -13758 diff -Naur gcc-4.2.2.orig/gcc/config/score/score.opt gcc-4.2.2/gcc/config/score/score.opt13759 --- gcc-4.2.2.orig/gcc/config/score/score.opt 2007-09-01 08:28:30.000000000 -070013760 +++ gcc-4.2.2/gcc/config/score/score.opt 2007-10-17 23:24:34.000000000 -070013761 @@ -34,10 +34,6 @@13762 Target RejectNegative Report Mask(ULS)13763 Enable unaligned load/store instruction13764 13765 -mmac13766 -Target RejectNegative Report Mask(MAC)13767 -Enable mac instruction13768 -13769 mscore513770 Target RejectNegative Report Mask(SCORE5)13771 Support SCORE 5 ISA13772 @@ -53,3 +49,15 @@13773 mscore7d13774 Target RejectNegative Report Mask(SCORE7D)13775 Support SCORE 7D ISA13776 +13777 +mscore313778 +Target RejectNegative Report Mask(SCORE3)13779 +Support SCORE 3 ISA13780 +13781 +mscore3d13782 +Target RejectNegative Report Mask(SCORE3D)13783 +Support SCORE 3d ISA13784 +13785 +march=13786 +Target RejectNegative Joined13787 +Specify the name of the target architecture13788 diff -Naur gcc-4.2.2.orig/gcc/config/score/score-protos.h gcc-4.2.2/gcc/config/score/score-protos.h13789 --- gcc-4.2.2.orig/gcc/config/score/score-protos.h 2007-09-01 08:28:30.000000000 -070013790 +++ gcc-4.2.2/gcc/config/score/score-protos.h 2007-10-17 23:24:34.000000000 -070013791 @@ -17,75 +17,80 @@13792 along with GCC; see the file COPYING3. If not see13793 <http://www.gnu.org/licenses/>. */13794 13795 -#ifndef __SCORE_PROTOS_H__13796 -#define __SCORE_PROTOS_H__13797 +#ifndef GCC_SCORE_PROTOS_H13798 +#define GCC_SCORE_PROTOS_H13799 13800 -extern enum reg_class score_char_to_class[];13801 +/* Machine Print. */13802 +enum score_mem_unit {SCORE_BYTE = 0, SCORE_HWORD = 1, SCORE_WORD = 2};13803 13804 -void score_override_options (void);13805 +#define SCORE_ALIGN_UNIT(V, UNIT) !(V & ((1 << UNIT) - 1))13806 13807 -void score_init_expanders (void);13808 -13809 -int score_hard_regno_mode_ok (unsigned int, enum machine_mode);13810 -13811 -int score_reg_class (int regno);13812 -13813 -enum reg_class score_preferred_reload_class (rtx x, enum reg_class class);13814 -13815 -enum reg_class score_secondary_reload_class (enum reg_class class,13816 - enum machine_mode mode, rtx x);13817 -13818 -int score_const_ok_for_letter_p (HOST_WIDE_INT value, char c);13819 -13820 -int score_extra_constraint (rtx op, char c);13821 -13822 -rtx score_return_addr (int count, rtx frame);13823 -13824 -HOST_WIDE_INT score_initial_elimination_offset (int from, int to);13825 -13826 -rtx score_function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,13827 - tree type, int named);13828 -13829 -int score_arg_partial_nregs (const CUMULATIVE_ARGS *cum,13830 - enum machine_mode mode, tree type, int named);13831 -13832 -void score_init_cumulative_args (CUMULATIVE_ARGS *cum,13833 - tree fntype, rtx libname);13834 -13835 -void score_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,13836 - tree type, int named);13837 -13838 -rtx score_function_value (tree valtype, tree func, enum machine_mode mode);13839 -13840 -rtx score_va_arg (tree va_list, tree type);13841 -13842 -void score_initialize_trampoline (rtx ADDR, rtx FUNC, rtx CHAIN);13843 -13844 -int score_address_p (enum machine_mode mode, rtx x, int strict);13845 -13846 -int score_legitimize_address (rtx *xloc);13847 -13848 -int score_regno_mode_ok_for_base_p (int regno, int strict);13849 -13850 -int score_register_move_cost (enum machine_mode mode, enum reg_class to,13851 - enum reg_class from);13852 -13853 -void score_declare_object (FILE *stream, const char *name,13854 - const char *directive, const char *fmt, ...);13855 -13856 -void score_declare_object_name (FILE *stream, const char *name, tree decl);13857 -13858 -int score_output_external (FILE *file, tree decl, const char *name);13859 -13860 -void score_print_operand (FILE *file, rtx op, int letter);13861 -13862 -void score_print_operand_address (FILE *file, rtx addr);13863 +extern void score_gen_cmp (enum machine_mode mode);13864 +extern void score_prologue (void);13865 +extern void score_epilogue (int sibcall_p);13866 +extern void score_call (rtx *ops, bool sib);13867 +extern void score_call_value (rtx *ops, bool sib);13868 +extern void score_movdi (rtx *ops);13869 +extern void score_zero_extract_andi (rtx *ops);13870 +extern const char * score_linsn (rtx *ops, enum score_mem_unit unit, bool sign);13871 +extern const char * score_sinsn (rtx *ops, enum score_mem_unit unit);13872 +extern const char * score_limm (rtx *ops);13873 +extern const char * score_move (rtx *ops);13874 +extern bool score_unaligned_load (rtx* ops);13875 +extern bool score_unaligned_store (rtx* ops);13876 +extern bool score_block_move (rtx* ops);13877 +extern int score_address_cost (rtx addr);13878 +extern rtx score_function_arg (const CUMULATIVE_ARGS *cum,13879 + enum machine_mode mode,13880 + tree type, int named);13881 +extern int score_address_p (enum machine_mode mode, rtx x, int strict);13882 +extern int score_reg_class (int regno);13883 +extern int score_register_move_cost (enum machine_mode mode, enum reg_class to,13884 + enum reg_class from);13885 +extern int score_hard_regno_mode_ok (unsigned int, enum machine_mode);13886 +extern int score_const_ok_for_letter_p (HOST_WIDE_INT value, char c);13887 +extern int score_extra_constraint (rtx op, char c);13888 +extern rtx score_return_addr (int count, rtx frame);13889 +extern void score_initialize_trampoline (rtx ADDR, rtx FUNC, rtx CHAIN);13890 +extern int score_regno_mode_ok_for_base_p (int regno, int strict);13891 +extern void score_function_arg_advance (CUMULATIVE_ARGS *cum,13892 + enum machine_mode mode,13893 + tree type, int named);13894 +extern void score_init_cumulative_args (CUMULATIVE_ARGS *cum,13895 + tree fntype, rtx libname);13896 +extern void score_declare_object (FILE *stream, const char *name,13897 + const char *directive, const char *fmt, ...);13898 +extern int score_output_external (FILE *file, tree decl, const char *name);13899 +extern void score_override_options (void);13900 +extern enum reg_class score_secondary_reload_class (enum reg_class class,13901 + enum machine_mode mode,13902 + rtx x);13903 +extern rtx score_function_value (tree valtype, tree func,13904 + enum machine_mode mode);13905 +extern enum reg_class score_preferred_reload_class (rtx x,13906 + enum reg_class class);13907 +extern HOST_WIDE_INT score_initial_elimination_offset (int from, int to);13908 +extern void score_print_operand (FILE *file, rtx op, int letter);13909 +extern void score_print_operand_address (FILE *file, rtx addr);13910 +extern int score_legitimize_address (rtx *xloc);13911 +extern int score_arg_partial_bytes (CUMULATIVE_ARGS *cum,13912 + enum machine_mode mode,13913 + tree type, bool named);13914 +extern int score_symbolic_constant_p (rtx x,13915 + enum score_symbol_type *symbol_type);13916 +extern void score_movsicc (rtx *ops);13917 +extern const char * score_select_add_imm (rtx *ops, bool set_cc);13918 +extern const char * score_select (rtx *ops, const char *inst_pre, bool commu,13919 + const char *letter, bool set_cc);13920 +extern const char * score_output_casesi (rtx *operands);13921 +extern const char * score_rpush (rtx *ops);13922 +extern const char * score_rpop (rtx *ops);13923 +extern bool score_rtx_costs (rtx x, int code, int outer_code, int *total);13924 13925 #ifdef RTX_CODE13926 -enum machine_mode score_select_cc_mode (enum rtx_code op, rtx x, rtx y);13927 +extern enum machine_mode score_select_cc_mode (enum rtx_code op, rtx x, rtx y);13928 #endif13929 13930 -#include "score-mdaux.h"13931 -13932 -#endif /* __SCORE_PROTOS_H__ */13933 +extern struct extern_list *extern_head;13934 13935 +#endif /* GCC_SCORE_PROTOS_H */13936 diff -Naur gcc-4.2.2.orig/gcc/config/score/score-version.h gcc-4.2.2/gcc/config/score/score-version.h13937 --- gcc-4.2.2.orig/gcc/config/score/score-version.h 2007-09-01 08:28:30.000000000 -070013938 +++ gcc-4.2.2/gcc/config/score/score-version.h 1969-12-31 16:00:00.000000000 -080013939 @@ -1,20 +0,0 @@13940 -/* score-version.h for Sunplus S+CORE processor13941 - Copyright (C) 2005, 2007 Free Software Foundation, Inc.13942 -13943 - This file is part of GCC.13944 -13945 - GCC is free software; you can redistribute it and/or modify it13946 - under the terms of the GNU General Public License as published13947 - by the Free Software Foundation; either version 3, or (at your13948 - option) any later version.13949 -13950 - GCC is distributed in the hope that it will be useful, but WITHOUT13951 - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY13952 - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public13953 - License for more details.13954 -13955 - You should have received a copy of the GNU General Public License13956 - along with GCC; see the file COPYING3. If not see13957 - <http://www.gnu.org/licenses/>. */13958 -13959 -#define SCORE_GCC_VERSION "1.2"13960 14900 diff -Naur gcc-4.2.2.orig/gcc/config/score/t-score-elf gcc-4.2.2/gcc/config/score/t-score-elf 13961 --- gcc-4.2.2.orig/gcc/config/score/t-score-elf 2007-01-07 19:45:03.000000000 -080013962 +++ gcc-4.2.2/gcc/config/score/t-score-elf 2007-10-1 7 23:24:34.000000000 -070014901 --- gcc-4.2.2.orig/gcc/config/score/t-score-elf 2007-01-07 22:45:03.000000000 -0500 14902 +++ gcc-4.2.2/gcc/config/score/t-score-elf 2007-10-18 02:24:34.000000000 -0400 13963 14903 @@ -1,9 +1,16 @@ 13964 14904 # Additional Backend Files … … 13991 14931 EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crti.o crtn.o 13992 14932 14933 diff -Naur gcc-4.2.2.orig/gcc/config/xtensa/xtensa.c gcc-4.2.2/gcc/config/xtensa/xtensa.c 14934 --- gcc-4.2.2.orig/gcc/config/xtensa/xtensa.c 2007-09-12 17:47:59.000000000 -0400 14935 +++ gcc-4.2.2/gcc/config/xtensa/xtensa.c 2007-11-02 12:13:29.000000000 -0400 14936 @@ -1954,12 +1954,13 @@ 14937 { 14938 HOST_WIDE_INT total_size; 14939 rtx size_rtx; 14940 + rtx insn, note_rtx; 14941 14942 total_size = compute_frame_size (get_frame_size ()); 14943 size_rtx = GEN_INT (total_size); 14944 14945 if (total_size < (1 << (12+3))) 14946 - emit_insn (gen_entry (size_rtx, size_rtx)); 14947 + insn = emit_insn (gen_entry (size_rtx, size_rtx)); 14948 else 14949 { 14950 /* Use a8 as a temporary since a0-a7 may be live. */ 14951 @@ -1967,14 +1968,14 @@ 14952 emit_insn (gen_entry (size_rtx, GEN_INT (MIN_FRAME_SIZE))); 14953 emit_move_insn (tmp_reg, GEN_INT (total_size - MIN_FRAME_SIZE)); 14954 emit_insn (gen_subsi3 (tmp_reg, stack_pointer_rtx, tmp_reg)); 14955 - emit_move_insn (stack_pointer_rtx, tmp_reg); 14956 + insn = emit_insn (gen_movsi (stack_pointer_rtx, tmp_reg)); 14957 } 14958 14959 if (frame_pointer_needed) 14960 { 14961 if (cfun->machine->set_frame_ptr_insn) 14962 { 14963 - rtx first, insn; 14964 + rtx first; 14965 14966 push_topmost_sequence (); 14967 first = get_insns (); 14968 @@ -1993,8 +1994,20 @@ 14969 } 14970 } 14971 else 14972 - emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx); 14973 + insn = emit_insn (gen_movsi (hard_frame_pointer_rtx, 14974 + stack_pointer_rtx)); 14975 } 14976 + 14977 + /* Create a note to describe the CFA. Because this is only used to set 14978 + DW_AT_frame_base for debug info, don't bother tracking changes through 14979 + each instruction in the prologue. It just takes up space. */ 14980 + note_rtx = gen_rtx_SET (VOIDmode, (frame_pointer_needed 14981 + ? hard_frame_pointer_rtx 14982 + : stack_pointer_rtx), 14983 + plus_constant (stack_pointer_rtx, -total_size)); 14984 + RTX_FRAME_RELATED_P (insn) = 1; 14985 + REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, 14986 + note_rtx, REG_NOTES (insn)); 14987 } 14988 14989 14990 diff -Naur gcc-4.2.2.orig/gcc/config/xtensa/xtensa.h gcc-4.2.2/gcc/config/xtensa/xtensa.h 14991 --- gcc-4.2.2.orig/gcc/config/xtensa/xtensa.h 2007-09-01 11:28:30.000000000 -0400 14992 +++ gcc-4.2.2/gcc/config/xtensa/xtensa.h 2007-11-02 12:13:29.000000000 -0400 14993 @@ -1208,8 +1208,12 @@ 14994 /* How to start an assembler comment. */ 14995 #define ASM_COMMENT_START "#" 14996 14997 -/* Exception handling TODO!! */ 14998 -#define DWARF_UNWIND_INFO 0 14999 +/* Generate DWARF2 unwind info to get the DW_AT_frame_base set correctly, 15000 + even though we don't yet use it for unwinding. */ 15001 +#define MUST_USE_SJLJ_EXCEPTIONS 1 15002 +#define DWARF2_UNWIND_INFO 1 15003 +#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, 0) 15004 +#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (0) 15005 15006 /* Xtensa constant pool breaks the devices in crtstuff.c to control 15007 section in where code resides. We have to write it as asm code. Use 13993 15008 diff -Naur gcc-4.2.2.orig/gcc/config.gcc gcc-4.2.2/gcc/config.gcc 13994 --- gcc-4.2.2.orig/gcc/config.gcc 2007-09-01 08:28:30.000000000 -070013995 +++ gcc-4.2.2/gcc/config.gcc 2007-10-1 7 23:24:34.000000000 -070015009 --- gcc-4.2.2.orig/gcc/config.gcc 2007-09-01 11:28:30.000000000 -0400 15010 +++ gcc-4.2.2/gcc/config.gcc 2007-10-18 02:24:34.000000000 -0400 13996 15011 @@ -1959,7 +1959,7 @@ 13997 15012 score-*-elf) … … 14003 15018 sh-*-elf* | sh[12346l]*-*-elf* | sh*-*-kaos* | \ 14004 15019 sh-*-symbianelf* | sh[12346l]*-*-symbianelf* | \ 15020 diff -Naur gcc-4.2.2.orig/gcc/cp/ChangeLog gcc-4.2.2/gcc/cp/ChangeLog 15021 --- gcc-4.2.2.orig/gcc/cp/ChangeLog 2007-10-07 17:19:52.000000000 -0400 15022 +++ gcc-4.2.2/gcc/cp/ChangeLog 2007-12-10 17:54:26.000000000 -0500 15023 @@ -1,3 +1,43 @@ 15024 +2007-12-10 Simon Martin <simartin@users.sourceforge.net> 15025 + 15026 + PR c++/34059 15027 + * typeck.c (build_class_member_access_expr): Compute MEMBER_SCOPE from 15028 + MEMBER's BASELINK_ACCESS_BINFO instead of its BASELINK_BINFO. 15029 + 15030 +2007-10-26 Jakub Jelinek <jakub@redhat.com> 15031 + 15032 + PR c++/33744 15033 + * parser.c (cp_parser_parenthesized_expression_list): Set 15034 + greater_than_is_operator_p to true in between the parens. 15035 + 15036 +2007-10-16 Mark Mitchell <mark@codesourcery.com> 15037 + 15038 + * decl.c (start_decl_1): Call cp_apply_type_quals_to_decl after 15039 + completing the type. 15040 + 15041 +2007-10-13 Simon Martin <simartin@users.sourceforge.net> 15042 + 15043 + PR c++/26698 15044 + * call.c (build_user_type_conversion_1): Do not consider conversion 15045 + functions to convert a (possibly cv-qualified) object to the (possibly 15046 + cv-qualified) same object type (or a reference to it), to a (possibly 15047 + cv-qualified) base class of that type (or a reference to it). 15048 + 15049 +2007-10-09 Jason Merrill <jason@redhat.com> 15050 + 15051 + PR c++/32470 15052 + * name-lookup.c (push_namespace_with_attrs): Fold back into... 15053 + (push_namespace): Here. 15054 + (handle_namespace_attrs): New fn for the attr code. 15055 + (leave_scope): Don't pop_visibility. 15056 + * name-lookup.h (struct cp_binding_level): Remove has_visibility. 15057 + * parser.c (cp_parser_namespace_definition): Call 15058 + handle_namespace_attrs and pop_visibility as appropriate. 15059 + 15060 + PR c++/33094 15061 + * decl.c (make_rtl_for_nonlocal_decl): It's ok for a member 15062 + constant to not have DECL_EXTERNAL if it's file-local. 15063 + 15064 2007-10-07 Release Manager 15065 15066 * GCC 4.2.2 released. 14005 15067 diff -Naur gcc-4.2.2.orig/gcc/cp/call.c gcc-4.2.2/gcc/cp/call.c 14006 --- gcc-4.2.2.orig/gcc/cp/call.c 2007-09-11 08:40:51.000000000 -070014007 +++ gcc-4.2.2/gcc/cp/call.c 2007-10-1 2 23:04:57.000000000 -070015068 --- gcc-4.2.2.orig/gcc/cp/call.c 2007-09-11 11:40:51.000000000 -0400 15069 +++ gcc-4.2.2/gcc/cp/call.c 2007-10-13 02:04:57.000000000 -0400 14008 15070 @@ -2550,7 +2550,21 @@ 14009 15071 ctors = lookup_fnfields (totype, complete_ctor_identifier, 0); … … 14029 15091 candidates = 0; 14030 15092 flags |= LOOKUP_NO_CONVERSION; 14031 diff -Naur gcc-4.2.2.orig/gcc/cp/ChangeLog gcc-4.2.2/gcc/cp/ChangeLog14032 --- gcc-4.2.2.orig/gcc/cp/ChangeLog 2007-10-07 14:19:52.000000000 -070014033 +++ gcc-4.2.2/gcc/cp/ChangeLog 2007-10-16 14:09:41.000000000 -070014034 @@ -1,3 +1,31 @@14035 +2007-10-16 Mark Mitchell <mark@codesourcery.com>14036 +14037 + * decl.c (start_decl_1): Call cp_apply_type_quals_to_decl after14038 + completing the type.14039 +14040 +2007-10-13 Simon Martin <simartin@users.sourceforge.net>14041 +14042 + PR c++/2669814043 + * call.c (build_user_type_conversion_1): Do not consider conversion14044 + functions to convert a (possibly cv-qualified) object to the (possibly14045 + cv-qualified) same object type (or a reference to it), to a (possibly14046 + cv-qualified) base class of that type (or a reference to it).14047 +14048 +2007-10-09 Jason Merrill <jason@redhat.com>14049 +14050 + PR c++/3247014051 + * name-lookup.c (push_namespace_with_attrs): Fold back into...14052 + (push_namespace): Here.14053 + (handle_namespace_attrs): New fn for the attr code.14054 + (leave_scope): Don't pop_visibility.14055 + * name-lookup.h (struct cp_binding_level): Remove has_visibility.14056 + * parser.c (cp_parser_namespace_definition): Call14057 + handle_namespace_attrs and pop_visibility as appropriate.14058 +14059 + PR c++/3309414060 + * decl.c (make_rtl_for_nonlocal_decl): It's ok for a member14061 + constant to not have DECL_EXTERNAL if it's file-local.14062 +14063 2007-10-07 Release Manager14064 14065 * GCC 4.2.2 released.14066 15093 diff -Naur gcc-4.2.2.orig/gcc/cp/decl.c gcc-4.2.2/gcc/cp/decl.c 14067 --- gcc-4.2.2.orig/gcc/cp/decl.c 2007-09-06 1 2:19:15.000000000 -070014068 +++ gcc-4.2.2/gcc/cp/decl.c 2007-10-16 1 4:09:41.000000000 -070015094 --- gcc-4.2.2.orig/gcc/cp/decl.c 2007-09-06 15:19:15.000000000 -0400 15095 +++ gcc-4.2.2/gcc/cp/decl.c 2007-10-16 17:09:41.000000000 -0400 14069 15096 @@ -4025,10 +4025,19 @@ 14070 15097 return tem; … … 14177 15204 /* We don't create any RTL for local variables. */ 14178 15205 diff -Naur gcc-4.2.2.orig/gcc/cp/name-lookup.c gcc-4.2.2/gcc/cp/name-lookup.c 14179 --- gcc-4.2.2.orig/gcc/cp/name-lookup.c 2007-08-31 0 1:27:50.000000000 -070014180 +++ gcc-4.2.2/gcc/cp/name-lookup.c 2007-10-09 1 3:52:24.000000000 -070015206 --- gcc-4.2.2.orig/gcc/cp/name-lookup.c 2007-08-31 04:27:50.000000000 -0400 15207 +++ gcc-4.2.2/gcc/cp/name-lookup.c 2007-10-09 16:52:24.000000000 -0400 14181 15208 @@ -1348,11 +1348,6 @@ 14182 15209 is_class_level = 0; … … 14300 15327 14301 15328 diff -Naur gcc-4.2.2.orig/gcc/cp/name-lookup.h gcc-4.2.2/gcc/cp/name-lookup.h 14302 --- gcc-4.2.2.orig/gcc/cp/name-lookup.h 2007-08-31 0 1:27:50.000000000 -070014303 +++ gcc-4.2.2/gcc/cp/name-lookup.h 2007-10-09 1 3:52:24.000000000 -070015329 --- gcc-4.2.2.orig/gcc/cp/name-lookup.h 2007-08-31 04:27:50.000000000 -0400 15330 +++ gcc-4.2.2/gcc/cp/name-lookup.h 2007-10-09 16:52:24.000000000 -0400 14304 15331 @@ -258,11 +258,7 @@ 14305 15332 unsigned more_cleanups_ok : 1; … … 14329 15356 extern tree pushdecl_with_scope (tree, cxx_scope *, bool); 14330 15357 diff -Naur gcc-4.2.2.orig/gcc/cp/parser.c gcc-4.2.2/gcc/cp/parser.c 14331 --- gcc-4.2.2.orig/gcc/cp/parser.c 2007-08-31 01:27:50.000000000 -0700 14332 +++ gcc-4.2.2/gcc/cp/parser.c 2007-10-09 13:52:24.000000000 -0700 14333 @@ -10640,6 +10640,7 @@ 15358 --- gcc-4.2.2.orig/gcc/cp/parser.c 2007-08-31 04:27:50.000000000 -0400 15359 +++ gcc-4.2.2/gcc/cp/parser.c 2007-10-26 08:04:57.000000000 -0400 15360 @@ -4777,6 +4777,7 @@ 15361 tree expression_list = NULL_TREE; 15362 bool fold_expr_p = is_attribute_list; 15363 tree identifier = NULL_TREE; 15364 + bool saved_greater_than_is_operator_p; 15365 15366 /* Assume all the expressions will be constant. */ 15367 if (non_constant_p) 15368 @@ -4785,6 +4786,12 @@ 15369 if (!cp_parser_require (parser, CPP_OPEN_PAREN, "`('")) 15370 return error_mark_node; 15371 15372 + /* Within a parenthesized expression, a `>' token is always 15373 + the greater-than operator. */ 15374 + saved_greater_than_is_operator_p 15375 + = parser->greater_than_is_operator_p; 15376 + parser->greater_than_is_operator_p = true; 15377 + 15378 /* Consume expressions until there are no more. */ 15379 if (cp_lexer_next_token_is_not (parser->lexer, CPP_CLOSE_PAREN)) 15380 while (true) 15381 @@ -4858,9 +4865,16 @@ 15382 if (ending < 0) 15383 goto get_comma; 15384 if (!ending) 15385 - return error_mark_node; 15386 + { 15387 + parser->greater_than_is_operator_p 15388 + = saved_greater_than_is_operator_p; 15389 + return error_mark_node; 15390 + } 15391 } 15392 15393 + parser->greater_than_is_operator_p 15394 + = saved_greater_than_is_operator_p; 15395 + 15396 /* We built up the list in reverse order so we must reverse it now. */ 15397 expression_list = nreverse (expression_list); 15398 if (identifier) 15399 @@ -10640,6 +10654,7 @@ 14334 15400 cp_parser_namespace_definition (cp_parser* parser) 14335 15401 { … … 14339 15405 /* Look for the `namespace' keyword. */ 14340 15406 cp_parser_require_keyword (parser, RID_NAMESPACE, "`namespace'"); 14341 @@ -10659,9 +106 60,18 @@15407 @@ -10659,9 +10674,18 @@ 14342 15408 /* Look for the `{' to start the namespace. */ 14343 15409 cp_parser_require (parser, CPP_OPEN_BRACE, "`{'"); … … 14359 15425 pop_namespace (); 14360 15426 /* Look for the final `}'. */ 14361 diff -Naur gcc-4.2.2.orig/gcc/c-typeck.c gcc-4.2.2/gcc/c-typeck.c 14362 --- gcc-4.2.2.orig/gcc/c-typeck.c 2007-09-01 08:28:30.000000000 -0700 14363 +++ gcc-4.2.2/gcc/c-typeck.c 2007-10-10 11:24:29.000000000 -0700 14364 @@ -1682,14 +1682,19 @@ 14365 if (TREE_NO_WARNING (orig_exp)) 14366 TREE_NO_WARNING (exp) = 1; 14367 14368 - if (INTEGRAL_TYPE_P (type)) 14369 - return perform_integral_promotions (exp); 14370 - 14371 if (code == VOID_TYPE) 14372 { 14373 error ("void value not ignored as it ought to be"); 14374 return error_mark_node; 15427 diff -Naur gcc-4.2.2.orig/gcc/cp/typeck.c gcc-4.2.2/gcc/cp/typeck.c 15428 --- gcc-4.2.2.orig/gcc/cp/typeck.c 2007-08-31 04:27:50.000000000 -0400 15429 +++ gcc-4.2.2/gcc/cp/typeck.c 2007-12-10 17:54:26.000000000 -0500 15430 @@ -1795,7 +1795,7 @@ 15431 warn_deprecated_use (member); 14375 15432 } 14376 + 14377 + exp = require_complete_type (exp); 14378 + if (exp == error_mark_node) 14379 + return error_mark_node; 14380 + 14381 + if (INTEGRAL_TYPE_P (type)) 14382 + return perform_integral_promotions (exp); 14383 + 14384 return exp; 14385 } 14386 14387 14388 @@ -2801,11 +2806,15 @@ 14389 /* No default_conversion here. It causes trouble for ADDR_EXPR. */ 14390 tree arg = xarg; 14391 tree argtype = 0; 14392 - enum tree_code typecode = TREE_CODE (TREE_TYPE (arg)); 14393 + enum tree_code typecode; 14394 tree val; 14395 int noconvert = flag; 14396 const char *invalid_op_diag; 14397 14398 + if (code != ADDR_EXPR) 14399 + arg = require_complete_type (arg); 14400 + 14401 + typecode = TREE_CODE (TREE_TYPE (arg)); 14402 if (typecode == ERROR_MARK) 14403 return error_mark_node; 14404 if (typecode == ENUMERAL_TYPE || typecode == BOOLEAN_TYPE) 14405 @@ -3490,6 +3499,13 @@ 14406 return error_mark_node; 14407 } 14408 14409 + if (!VOID_TYPE_P (type)) 14410 + { 14411 + value = require_complete_type (value); 14412 + if (value == error_mark_node) 14413 + return error_mark_node; 14414 + } 14415 + 14416 if (type == TYPE_MAIN_VARIANT (TREE_TYPE (value))) 14417 { 14418 if (pedantic) 14419 @@ -3900,6 +3916,9 @@ 14420 error ("void value not ignored as it ought to be"); 14421 return error_mark_node; 14422 } 14423 + rhs = require_complete_type (rhs); 14424 + if (rhs == error_mark_node) 14425 + return error_mark_node; 14426 /* A type converts to a reference to it. 14427 This code doesn't fully support references, it's just for the 14428 special case of va_start and va_copy. */ 15433 else 15434 - member_scope = BINFO_TYPE (BASELINK_BINFO (member)); 15435 + member_scope = BINFO_TYPE (BASELINK_ACCESS_BINFO (member)); 15436 /* If MEMBER is from an anonymous aggregate, MEMBER_SCOPE will 15437 presently be the anonymous union. Go outwards until we find a 15438 type related to OBJECT_TYPE. */ 14429 15439 diff -Naur gcc-4.2.2.orig/gcc/df-scan.c gcc-4.2.2/gcc/df-scan.c 14430 --- gcc-4.2.2.orig/gcc/df-scan.c 2007-09-01 08:28:30.000000000 -070014431 +++ gcc-4.2.2/gcc/df-scan.c 2007-10-2 2 21:37:02.000000000 -070015440 --- gcc-4.2.2.orig/gcc/df-scan.c 2007-09-01 11:28:30.000000000 -0400 15441 +++ gcc-4.2.2/gcc/df-scan.c 2007-10-23 00:37:02.000000000 -0400 14432 15442 @@ -1584,12 +1584,19 @@ 14433 15443 so they are recorded as used. */ … … 14455 15465 } 14456 15466 15467 diff -Naur gcc-4.2.2.orig/gcc/doc/invoke.texi gcc-4.2.2/gcc/doc/invoke.texi 15468 --- gcc-4.2.2.orig/gcc/doc/invoke.texi 2007-09-07 06:45:50.000000000 -0400 15469 +++ gcc-4.2.2/gcc/doc/invoke.texi 2007-10-29 12:58:00.000000000 -0400 15470 @@ -301,10 +301,11 @@ 15471 15472 @item Optimization Options 15473 @xref{Optimize Options,,Options that Control Optimization}. 15474 -@gccoptlist{-falign-functions=@var{n} -falign-jumps=@var{n} @gol 15475 --falign-labels=@var{n} -falign-loops=@var{n} @gol 15476 --fbounds-check -fmudflap -fmudflapth -fmudflapir @gol 15477 --fbranch-probabilities -fprofile-values -fvpt -fbranch-target-load-optimize @gol 15478 +@gccoptlist{-falign-functions[=@var{n}] -falign-jumps[=@var{n}] @gol 15479 +-falign-labels[=@var{n}] -falign-loops[=@var{n}] @gol 15480 +-fmudflap -fmudflapth -fmudflapir @gol 15481 +-fbranch-probabilities -fprofile-values -fvpt @gol 15482 +-fbranch-target-load-optimize @gol 15483 -fbranch-target-load-optimize2 -fbtr-bb-exclusive @gol 15484 -fcaller-saves -fcprop-registers -fcse-follow-jumps @gol 15485 -fcse-skip-blocks -fcx-limited-range -fdata-sections @gol 15486 @@ -332,7 +333,7 @@ 15487 -fschedule-insns -fschedule-insns2 @gol 15488 -fno-sched-interblock -fno-sched-spec -fsched-spec-load @gol 15489 -fsched-spec-load-dangerous @gol 15490 --fsched-stalled-insns=@var{n} -fsched-stalled-insns-dep=@var{n} @gol 15491 +-fsched-stalled-insns[=@var{n}] -fsched-stalled-insns-dep[=@var{n}] @gol 15492 -fsched2-use-superblocks @gol 15493 -fsched2-use-traces -fsee -freschedule-modulo-scheduled-loops @gol 15494 -fsection-anchors -fsignaling-nans -fsingle-precision-constant @gol 15495 @@ -346,7 +347,8 @@ 15496 -ftree-dominator-opts -ftree-dse -ftree-copyrename -ftree-sink @gol 15497 -ftree-ch -ftree-sra -ftree-ter -ftree-lrs -ftree-fre -ftree-vectorize @gol 15498 -ftree-vect-loop-version -ftree-salias -fipa-pta -fweb @gol 15499 --ftree-copy-prop -ftree-store-ccp -ftree-store-copy-prop -fwhole-program @gol 15500 +-ftree-copy-prop -ftree-store-ccp -ftree-store-copy-prop -ftree-vrp @gol 15501 +-funit-at-a-time -fwhole-program @gol 15502 --param @var{name}=@var{value} 15503 -O -O0 -O1 -O2 -O3 -Os} 15504 15505 @@ -782,8 +784,8 @@ 15506 -fshort-double -fshort-wchar @gol 15507 -fverbose-asm -fpack-struct[=@var{n}] -fstack-check @gol 15508 -fstack-limit-register=@var{reg} -fstack-limit-symbol=@var{sym} @gol 15509 --fargument-alias -fargument-noalias @gol 15510 --fargument-noalias-global -fargument-noalias-anything 15511 +-fno-stack-limit -fargument-alias -fargument-noalias @gol 15512 +-fargument-noalias-global -fargument-noalias-anything @gol 15513 -fleading-underscore -ftls-model=@var{model} @gol 15514 -ftrapv -fwrapv -fbounds-check @gol 15515 -fvisibility} 15516 @@ -4801,6 +4803,7 @@ 15517 optimization is turned on, use the @option{-fno-keep-static-consts} option. 15518 15519 @item -fmerge-constants 15520 +@opindex fmerge-constants 15521 Attempt to merge identical constants (string constants and floating point 15522 constants) across compilation units. 15523 15524 @@ -4811,6 +4814,7 @@ 15525 Enabled at levels @option{-O}, @option{-O2}, @option{-O3}, @option{-Os}. 15526 15527 @item -fmerge-all-constants 15528 +@opindex fmerge-all-constants 15529 Attempt to merge identical constants and identical variables. 15530 15531 This option implies @option{-fmerge-constants}. In addition to 15532 @@ -4860,13 +4864,6 @@ 15533 15534 The default is @option{-fzero-initialized-in-bss}. 15535 15536 -@item -fbounds-check 15537 -@opindex fbounds-check 15538 -For front-ends that support it, generate additional code to check that 15539 -indices used to access arrays are within the declared range. This is 15540 -currently only supported by the Java and Fortran front-ends, where 15541 -this option defaults to true and false respectively. 15542 - 15543 @item -fmudflap -fmudflapth -fmudflapir 15544 @opindex fmudflap 15545 @opindex fmudflapth 15546 @@ -4985,14 +4982,14 @@ 15547 if it finds this kind of loop. 15548 15549 @item -fcrossjumping 15550 -@opindex crossjumping 15551 +@opindex fcrossjumping 15552 Perform cross-jumping transformation. This transformation unifies equivalent code and save code size. The 15553 resulting code may or may not perform better than without cross-jumping. 15554 15555 Enabled at levels @option{-O2}, @option{-O3}, @option{-Os}. 15556 15557 @item -fif-conversion 15558 -@opindex if-conversion 15559 +@opindex fif-conversion 15560 Attempt to transform conditional jumps into branch-less equivalents. This 15561 include use of conditional moves, min, max, set flags and abs instructions, and 15562 some tricks doable by standard arithmetics. The use of conditional execution 15563 @@ -5001,7 +4998,7 @@ 15564 Enabled at levels @option{-O}, @option{-O2}, @option{-O3}, @option{-Os}. 15565 15566 @item -fif-conversion2 15567 -@opindex if-conversion2 15568 +@opindex fif-conversion2 15569 Use conditional execution (where available) to transform conditional jumps into 15570 branch-less equivalents. 15571 15572 @@ -5092,17 +5089,27 @@ 15573 sense when scheduling before register allocation, i.e.@: with 15574 @option{-fschedule-insns} or at @option{-O2} or higher. 15575 15576 -@item -fsched-stalled-insns=@var{n} 15577 +@item -fsched-stalled-insns 15578 +@itemx -fsched-stalled-insns=@var{n} 15579 @opindex fsched-stalled-insns 15580 Define how many insns (if any) can be moved prematurely from the queue 15581 of stalled insns into the ready list, during the second scheduling pass. 15582 +@option{-fno-fsched-stalled-insns} and @option{-fsched-stalled-insns=0} 15583 +are equivalent and mean that no insns will be moved prematurely. 15584 +If @var{n} is unspecified then there is no limit on how many queued 15585 +insns can be moved prematurely. 15586 15587 -@item -fsched-stalled-insns-dep=@var{n} 15588 +@item -fsched-stalled-insns-dep 15589 +@itemx -fsched-stalled-insns-dep=@var{n} 15590 @opindex fsched-stalled-insns-dep 15591 Define how many insn groups (cycles) will be examined for a dependency 15592 on a stalled insn that is candidate for premature removal from the queue 15593 -of stalled insns. Has an effect only during the second scheduling pass, 15594 +of stalled insns. This has an effect only during the second scheduling pass, 15595 and only if @option{-fsched-stalled-insns} is used and its value is not zero. 15596 +@option{-fno-sched-stalled-insns-dep} is equivalent to 15597 +@option{-fsched-stalled-insns-dep=0}. 15598 +@option{-fsched-stalled-insns-dep} without a value is equivalent to 15599 +@option{-fsched-stalled-insns-dep=1}. 15600 15601 @item -fsched2-use-superblocks 15602 @opindex fsched2-use-superblocks 15603 @@ -5134,7 +5141,7 @@ 15604 ones to optimal placement using LCM. 15605 15606 @item -freschedule-modulo-scheduled-loops 15607 -@opindex fscheduling-in-modulo-scheduled-loops 15608 +@opindex freschedule-modulo-scheduled-loops 15609 The modulo scheduling comes before the traditional scheduling, if a loop was modulo scheduled 15610 we may want to prevent the later scheduling passes from changing its schedule, we use this 15611 option to control that. 15612 @@ -5152,6 +5159,7 @@ 15613 Enabled at levels @option{-O2}, @option{-O3}, @option{-Os}. 15614 15615 @item -ftree-pre 15616 +@opindex ftree-pre 15617 Perform Partial Redundancy Elimination (PRE) on trees. This flag is 15618 enabled by default at @option{-O2} and @option{-O3}. 15619 15620 @@ -5163,6 +5171,7 @@ 15621 This flag is enabled by default at @option{-O} and higher. 15622 15623 @item -ftree-copy-prop 15624 +@opindex ftree-copy-prop 15625 Perform copy propagation on trees. This pass eliminates unnecessary 15626 copy operations. This flag is enabled by default at @option{-O} and 15627 higher. 15628 @@ -5174,32 +5183,39 @@ 15629 default at @option{-O2} and higher. 15630 15631 @item -ftree-salias 15632 +@opindex ftree-salias 15633 Perform structural alias analysis on trees. This flag 15634 is enabled by default at @option{-O} and higher. 15635 15636 @item -fipa-pta 15637 +@opindex fipa-pta 15638 Perform interprocedural pointer analysis. 15639 15640 @item -ftree-sink 15641 +@opindex ftree-sink 15642 Perform forward store motion on trees. This flag is 15643 enabled by default at @option{-O} and higher. 15644 15645 @item -ftree-ccp 15646 +@opindex ftree-ccp 15647 Perform sparse conditional constant propagation (CCP) on trees. This 15648 pass only operates on local scalar variables and is enabled by default 15649 at @option{-O} and higher. 15650 15651 @item -ftree-store-ccp 15652 +@opindex ftree-store-ccp 15653 Perform sparse conditional constant propagation (CCP) on trees. This 15654 pass operates on both local scalar variables and memory stores and 15655 loads (global variables, structures, arrays, etc). This flag is 15656 enabled by default at @option{-O2} and higher. 15657 15658 @item -ftree-dce 15659 +@opindex ftree-dce 15660 Perform dead code elimination (DCE) on trees. This flag is enabled by 15661 default at @option{-O} and higher. 15662 15663 @item -ftree-dominator-opts 15664 +@opindex ftree-dominator-opts 15665 Perform a variety of simple scalar cleanups (constant/copy 15666 propagation, redundancy elimination, range propagation and expression 15667 simplification) based on a dominator tree traversal. This also 15668 @@ -5207,20 +5223,24 @@ 15669 enabled by default at @option{-O} and higher. 15670 15671 @item -ftree-ch 15672 +@opindex ftree-ch 15673 Perform loop header copying on trees. This is beneficial since it increases 15674 effectiveness of code motion optimizations. It also saves one jump. This flag 15675 is enabled by default at @option{-O} and higher. It is not enabled 15676 for @option{-Os}, since it usually increases code size. 15677 15678 @item -ftree-loop-optimize 15679 +@opindex ftree-loop-optimize 15680 Perform loop optimizations on trees. This flag is enabled by default 15681 at @option{-O} and higher. 15682 15683 @item -ftree-loop-linear 15684 +@opindex ftree-loop-linear 15685 Perform linear loop transformations on tree. This flag can improve cache 15686 performance and allow further loop optimizations to take place. 15687 15688 @item -ftree-loop-im 15689 +@opindex ftree-loop-im 15690 Perform loop invariant motion on trees. This pass moves only invariants that 15691 would be hard to handle at RTL level (function calls, operations that expand to 15692 nontrivial sequences of insns). With @option{-funswitch-loops} it also moves 15693 @@ -5229,27 +5249,32 @@ 15694 store motion. 15695 15696 @item -ftree-loop-ivcanon 15697 +@opindex ftree-loop-ivcanon 15698 Create a canonical counter for number of iterations in the loop for that 15699 determining number of iterations requires complicated analysis. Later 15700 optimizations then may determine the number easily. Useful especially 15701 in connection with unrolling. 15702 15703 @item -fivopts 15704 +@opindex fivopts 15705 Perform induction variable optimizations (strength reduction, induction 15706 variable merging and induction variable elimination) on trees. 15707 15708 @item -ftree-sra 15709 +@opindex ftree-sra 15710 Perform scalar replacement of aggregates. This pass replaces structure 15711 references with scalars to prevent committing structures to memory too 15712 early. This flag is enabled by default at @option{-O} and higher. 15713 15714 @item -ftree-copyrename 15715 +@opindex ftree-copyrename 15716 Perform copy renaming on trees. This pass attempts to rename compiler 15717 temporaries to other variables at copy locations, usually resulting in 15718 variable names which more closely resemble the original variables. This flag 15719 is enabled by default at @option{-O} and higher. 15720 15721 @item -ftree-ter 15722 +@opindex ftree-ter 15723 Perform temporary expression replacement during the SSA->normal phase. Single 15724 use/single def temporaries are replaced at their use location with their 15725 defining expression. This results in non-GIMPLE code, but gives the expanders 15726 @@ -5257,11 +5282,13 @@ 15727 enabled by default at @option{-O} and higher. 15728 15729 @item -ftree-lrs 15730 +@opindex ftree-lrs 15731 Perform live range splitting during the SSA->normal phase. Distinct live 15732 ranges of a variable are split into unique variables, allowing for better 15733 optimization later. This is enabled by default at @option{-O} and higher. 15734 15735 @item -ftree-vectorize 15736 +@opindex ftree-vectorize 15737 Perform loop vectorization on trees. 15738 15739 @item -ftree-vect-loop-version 15740 @@ -5274,6 +5301,7 @@ 15741 except at level @option{-Os} where it is disabled. 15742 15743 @item -ftree-vrp 15744 +@opindex ftree-vrp 15745 Perform Value Range Propagation on trees. This is similar to the 15746 constant propagation pass, but instead of values, ranges of values are 15747 propagated. This allows the optimizers to remove unnecessary range 15748 @@ -5601,13 +5629,13 @@ 15749 compilation unit, not for the single source file itself. 15750 15751 15752 -@item -fno-cprop-registers 15753 -@opindex fno-cprop-registers 15754 +@item -fcprop-registers 15755 +@opindex fcprop-registers 15756 After register allocation and post-register allocation instruction splitting, 15757 we perform a copy-propagation pass to try to reduce scheduling dependencies 15758 and occasionally eliminate the copy. 15759 15760 -Disabled at levels @option{-O}, @option{-O2}, @option{-O3}, @option{-Os}. 15761 +Enabled at levels @option{-O}, @option{-O2}, @option{-O3}, @option{-Os}. 15762 15763 @item -fprofile-generate 15764 @opindex fprofile-generate 15765 @@ -5771,9 +5799,7 @@ 15766 implicitly converting it to double precision constant. 15767 15768 @item -fcx-limited-range 15769 -@itemx -fno-cx-limited-range 15770 @opindex fcx-limited-range 15771 -@opindex fno-cx-limited-range 15772 When enabled, this option states that a range reduction step is not 15773 needed when performing complex division. The default is 15774 @option{-fno-cx-limited-range}, but is enabled by @option{-ffast-math}. 15775 @@ -5926,6 +5952,7 @@ 15776 branch target registers in within any basic block. 15777 15778 @item -fstack-protector 15779 +@opindex fstack-protector 15780 Emit extra code to check for buffer overflows, such as stack smashing 15781 attacks. This is done by adding a guard variable to functions with 15782 vulnerable objects. This includes functions that call alloca, and 15783 @@ -5934,6 +5961,7 @@ 15784 If a guard check fails, an error message is printed and the program exits. 15785 15786 @item -fstack-protector-all 15787 +@opindex fstack-protector-all 15788 Like @option{-fstack-protector} except that all functions are protected. 15789 15790 @item -fsection-anchors 15791 @@ -13644,6 +13672,7 @@ 15792 Not all targets provide complete support for this switch. 15793 15794 @item -ftls-model=@var{model} 15795 +@opindex ftls-model=@var{model} 15796 Alter the thread-local storage model to be used (@pxref{Thread-Local}). 15797 The @var{model} argument should be one of @code{global-dynamic}, 15798 @code{local-dynamic}, @code{initial-exec} or @code{local-exec}. 14457 15799 diff -Naur gcc-4.2.2.orig/gcc/doc/rtl.texi gcc-4.2.2/gcc/doc/rtl.texi 14458 --- gcc-4.2.2.orig/gcc/doc/rtl.texi 2006-09-16 0 1:46:22.000000000 -070014459 +++ gcc-4.2.2/gcc/doc/rtl.texi 2007-10-23 1 2:24:59.000000000 -070015800 --- gcc-4.2.2.orig/gcc/doc/rtl.texi 2006-09-16 04:46:22.000000000 -0400 15801 +++ gcc-4.2.2/gcc/doc/rtl.texi 2007-10-23 15:24:59.000000000 -0400 14460 15802 @@ -648,8 +648,8 @@ 14461 15803 Stored in the @code{jump} field and printed as @samp{/j}. … … 14573 15915 In an RTL dump, this flag is represented as @samp{/i}. 14574 15916 diff -Naur gcc-4.2.2.orig/gcc/dwarf2out.c gcc-4.2.2/gcc/dwarf2out.c 14575 --- gcc-4.2.2.orig/gcc/dwarf2out.c 2007-09-24 0 2:17:10.000000000 -070014576 +++ gcc-4.2.2/gcc/dwarf2out.c 2007-10-10 0 2:29:13.000000000 -070015917 --- gcc-4.2.2.orig/gcc/dwarf2out.c 2007-09-24 05:17:10.000000000 -0400 15918 +++ gcc-4.2.2/gcc/dwarf2out.c 2007-10-10 05:29:13.000000000 -0400 14577 15919 @@ -10005,9 +10005,12 @@ 14578 15920 return *tp; … … 14589 15931 { 14590 15932 struct cgraph_varpool_node *node = cgraph_varpool_node (*tp); 15933 diff -Naur gcc-4.2.2.orig/gcc/fold-const.c gcc-4.2.2/gcc/fold-const.c 15934 --- gcc-4.2.2.orig/gcc/fold-const.c 2007-09-01 11:28:30.000000000 -0400 15935 +++ gcc-4.2.2/gcc/fold-const.c 2007-11-22 10:34:03.000000000 -0500 15936 @@ -5660,6 +5660,9 @@ 15937 } 15938 break; 15939 } 15940 + /* If the constant is negative, we cannot simplify this. */ 15941 + if (tree_int_cst_sgn (c) == -1) 15942 + break; 15943 /* FALLTHROUGH */ 15944 case NEGATE_EXPR: 15945 if ((t1 = extract_muldiv (op0, c, code, wide_type, strict_overflow_p)) 15946 @@ -10643,24 +10646,24 @@ 15947 tree arg01 = TREE_OPERAND (arg0, 1); 15948 if (TREE_CODE (arg00) == LSHIFT_EXPR 15949 && integer_onep (TREE_OPERAND (arg00, 0))) 15950 - return 15951 - fold_build2 (code, type, 15952 - build2 (BIT_AND_EXPR, TREE_TYPE (arg0), 15953 - build2 (RSHIFT_EXPR, TREE_TYPE (arg00), 15954 - arg01, TREE_OPERAND (arg00, 1)), 15955 - fold_convert (TREE_TYPE (arg0), 15956 - integer_one_node)), 15957 - arg1); 15958 - else if (TREE_CODE (TREE_OPERAND (arg0, 1)) == LSHIFT_EXPR 15959 - && integer_onep (TREE_OPERAND (TREE_OPERAND (arg0, 1), 0))) 15960 - return 15961 - fold_build2 (code, type, 15962 - build2 (BIT_AND_EXPR, TREE_TYPE (arg0), 15963 - build2 (RSHIFT_EXPR, TREE_TYPE (arg01), 15964 - arg00, TREE_OPERAND (arg01, 1)), 15965 - fold_convert (TREE_TYPE (arg0), 15966 - integer_one_node)), 15967 - arg1); 15968 + { 15969 + tree tem = fold_build2 (RSHIFT_EXPR, TREE_TYPE (arg00), 15970 + arg01, TREE_OPERAND (arg00, 1)); 15971 + tem = fold_build2 (BIT_AND_EXPR, TREE_TYPE (arg0), tem, 15972 + build_int_cst (TREE_TYPE (arg0), 1)); 15973 + return fold_build2 (code, type, 15974 + fold_convert (TREE_TYPE (arg1), tem), arg1); 15975 + } 15976 + else if (TREE_CODE (arg01) == LSHIFT_EXPR 15977 + && integer_onep (TREE_OPERAND (arg01, 0))) 15978 + { 15979 + tree tem = fold_build2 (RSHIFT_EXPR, TREE_TYPE (arg01), 15980 + arg00, TREE_OPERAND (arg01, 1)); 15981 + tem = fold_build2 (BIT_AND_EXPR, TREE_TYPE (arg0), tem, 15982 + build_int_cst (TREE_TYPE (arg0), 1)); 15983 + return fold_build2 (code, type, 15984 + fold_convert (TREE_TYPE (arg1), tem), arg1); 15985 + } 15986 } 15987 15988 /* If this is an NE or EQ comparison of zero against the result of a 14591 15989 diff -Naur gcc-4.2.2.orig/gcc/fortran/ChangeLog gcc-4.2.2/gcc/fortran/ChangeLog 14592 --- gcc-4.2.2.orig/gcc/fortran/ChangeLog 2007-10-07 1 4:19:56.000000000 -070014593 +++ gcc-4.2.2/gcc/fortran/ChangeLog 2007-10-15 1 1:23:39.000000000 -070015990 --- gcc-4.2.2.orig/gcc/fortran/ChangeLog 2007-10-07 17:19:56.000000000 -0400 15991 +++ gcc-4.2.2/gcc/fortran/ChangeLog 2007-10-15 14:23:39.000000000 -0400 14594 15992 @@ -1,3 +1,16 @@ 14595 15993 +2007-10-25 Thomas Koenig <tkoenig@gcc.gnu.org> … … 14610 16008 * GCC 4.2.2 released. 14611 16009 diff -Naur gcc-4.2.2.orig/gcc/fortran/trans-intrinsic.c gcc-4.2.2/gcc/fortran/trans-intrinsic.c 14612 --- gcc-4.2.2.orig/gcc/fortran/trans-intrinsic.c 2007-08-31 0 1:27:50.000000000 -070014613 +++ gcc-4.2.2/gcc/fortran/trans-intrinsic.c 2007-10-15 1 1:23:39.000000000 -070016010 --- gcc-4.2.2.orig/gcc/fortran/trans-intrinsic.c 2007-08-31 04:27:50.000000000 -0400 16011 +++ gcc-4.2.2/gcc/fortran/trans-intrinsic.c 2007-10-15 14:23:39.000000000 -0400 14614 16012 @@ -1878,6 +1878,7 @@ 14615 16013 tree tmp; … … 14676 16074 14677 16075 static void 16076 diff -Naur gcc-4.2.2.orig/gcc/ifcvt.c gcc-4.2.2/gcc/ifcvt.c 16077 --- gcc-4.2.2.orig/gcc/ifcvt.c 2007-09-01 11:28:30.000000000 -0400 16078 +++ gcc-4.2.2/gcc/ifcvt.c 2007-10-30 00:32:06.000000000 -0400 16079 @@ -2163,6 +2163,46 @@ 16080 return false; 16081 } 16082 16083 +/* Return whether we can use store speculation for MEM. TOP_BB is the 16084 + basic block above the conditional block where we are considering 16085 + doing the speculative store. We look for whether MEM is set 16086 + unconditionally later in the function. */ 16087 + 16088 +static bool 16089 +noce_can_store_speculate_p (basic_block top_bb, rtx mem) 16090 +{ 16091 + basic_block dominator; 16092 + 16093 + for (dominator = get_immediate_dominator (CDI_POST_DOMINATORS, top_bb); 16094 + dominator != NULL; 16095 + dominator = get_immediate_dominator (CDI_POST_DOMINATORS, dominator)) 16096 + { 16097 + rtx insn; 16098 + 16099 + FOR_BB_INSNS (dominator, insn) 16100 + { 16101 + /* If we see something that might be a memory barrier, we 16102 + have to stop looking. Even if the MEM is set later in 16103 + the function, we still don't want to set it 16104 + unconditionally before the barrier. */ 16105 + if (INSN_P (insn) 16106 + && (volatile_insn_p (PATTERN (insn)) 16107 + || (CALL_P (insn) 16108 + && (!CONST_OR_PURE_CALL_P (insn) 16109 + || pure_call_p (insn))))) 16110 + return false; 16111 + 16112 + if (memory_modified_in_insn_p (mem, insn)) 16113 + return true; 16114 + if (modified_in_p (XEXP (mem, 0), insn)) 16115 + return false; 16116 + 16117 + } 16118 + } 16119 + 16120 + return false; 16121 +} 16122 + 16123 /* Given a simple IF-THEN or IF-THEN-ELSE block, attempt to convert it 16124 without using conditional execution. Return TRUE if we were 16125 successful at converting the block. */ 16126 @@ -2321,17 +2361,31 @@ 16127 goto success; 16128 } 16129 16130 - /* Disallow the "if (...) x = a;" form (with an implicit "else x = x;") 16131 - for optimizations if writing to x may trap or fault, i.e. it's a memory 16132 - other than a static var or a stack slot, is misaligned on strict 16133 - aligned machines or is read-only. 16134 - If x is a read-only memory, then the program is valid only if we 16135 - avoid the store into it. If there are stores on both the THEN and 16136 - ELSE arms, then we can go ahead with the conversion; either the 16137 - program is broken, or the condition is always false such that the 16138 - other memory is selected. */ 16139 - if (!set_b && MEM_P (orig_x) && noce_mem_write_may_trap_or_fault_p (orig_x)) 16140 - return FALSE; 16141 + if (!set_b && MEM_P (orig_x)) 16142 + { 16143 + /* Disallow the "if (...) x = a;" form (implicit "else x = x;") 16144 + for optimizations if writing to x may trap or fault, 16145 + i.e. it's a memory other than a static var or a stack slot, 16146 + is misaligned on strict aligned machines or is read-only. If 16147 + x is a read-only memory, then the program is valid only if we 16148 + avoid the store into it. If there are stores on both the 16149 + THEN and ELSE arms, then we can go ahead with the conversion; 16150 + either the program is broken, or the condition is always 16151 + false such that the other memory is selected. */ 16152 + if (noce_mem_write_may_trap_or_fault_p (orig_x)) 16153 + return FALSE; 16154 + 16155 + /* Avoid store speculation: given "if (...) x = a" where x is a 16156 + MEM, we only want to do the store if x is always set 16157 + somewhere in the function. This avoids cases like 16158 + if (pthread_mutex_trylock(mutex)) 16159 + ++global_variable; 16160 + where we only want global_variable to be changed if the mutex 16161 + is held. FIXME: This should ideally be expressed directly in 16162 + RTL somehow. */ 16163 + if (!noce_can_store_speculate_p (test_bb, orig_x)) 16164 + return FALSE; 16165 + } 16166 16167 if (noce_try_move (&if_info)) 16168 goto success; 16169 @@ -2847,7 +2901,8 @@ 16170 && find_cond_trap (test_bb, then_edge, else_edge)) 16171 goto success; 16172 16173 - if (dom_computed[CDI_POST_DOMINATORS] >= DOM_NO_FAST_QUERY 16174 + if (life_data_ok 16175 + && dom_computed[CDI_POST_DOMINATORS] >= DOM_NO_FAST_QUERY 16176 && (! HAVE_conditional_execution || reload_completed)) 16177 { 16178 if (find_if_case_1 (test_bb, then_edge, else_edge)) 16179 @@ -3862,9 +3917,8 @@ 16180 free_dominance_info (CDI_DOMINATORS); 16181 } 16182 16183 - /* Compute postdominators if we think we'll use them. */ 16184 - if (HAVE_conditional_execution || life_data_ok) 16185 - calculate_dominance_info (CDI_POST_DOMINATORS); 16186 + /* Compute postdominators. */ 16187 + calculate_dominance_info (CDI_POST_DOMINATORS); 16188 16189 if (life_data_ok) 16190 clear_bb_flags (); 14678 16191 diff -Naur gcc-4.2.2.orig/gcc/po/ChangeLog gcc-4.2.2/gcc/po/ChangeLog 14679 --- gcc-4.2.2.orig/gcc/po/ChangeLog 2007-10-07 1 4:20:00.000000000 -070014680 +++ gcc-4.2.2/gcc/po/ChangeLog 2007-10-21 1 0:56:56.000000000 -070016192 --- gcc-4.2.2.orig/gcc/po/ChangeLog 2007-10-07 17:20:00.000000000 -0400 16193 +++ gcc-4.2.2/gcc/po/ChangeLog 2007-10-21 13:56:56.000000000 -0400 14681 16194 @@ -1,3 +1,12 @@ 14682 16195 +2007-10-21 Joseph S. Myers <joseph@codesourcery.com> … … 14692 16205 14693 16206 * GCC 4.2.2 released. 16207 diff -Naur gcc-4.2.2.orig/gcc/reload.c gcc-4.2.2/gcc/reload.c 16208 --- gcc-4.2.2.orig/gcc/reload.c 2007-09-01 11:28:30.000000000 -0400 16209 +++ gcc-4.2.2/gcc/reload.c 2007-11-22 04:27:55.000000000 -0500 16210 @@ -6158,17 +6158,16 @@ 16211 } 16212 #endif /* ENABLE_CHECKING */ 16213 16214 - /* If we're replacing a LABEL_REF with a register, add a 16215 - REG_LABEL note to indicate to flow which label this 16216 + /* If we're replacing a LABEL_REF jump target with a register, 16217 + add a REG_LABEL note to indicate to flow which label this 16218 register refers to. */ 16219 if (GET_CODE (*r->where) == LABEL_REF 16220 - && JUMP_P (insn)) 16221 - { 16222 - REG_NOTES (insn) = gen_rtx_INSN_LIST (REG_LABEL, 16223 - XEXP (*r->where, 0), 16224 - REG_NOTES (insn)); 16225 - JUMP_LABEL (insn) = XEXP (*r->where, 0); 16226 - } 16227 + && JUMP_P (insn) 16228 + && JUMP_LABEL (insn) == XEXP (*r->where, 0) 16229 + && !find_reg_note (insn, REG_LABEL, XEXP (*r->where, 0))) 16230 + REG_NOTES (insn) = gen_rtx_INSN_LIST (REG_LABEL, 16231 + XEXP (*r->where, 0), 16232 + REG_NOTES (insn)); 16233 16234 /* Encapsulate RELOADREG so its machine mode matches what 16235 used to be there. Note that gen_lowpart_common will 16236 diff -Naur gcc-4.2.2.orig/gcc/resource.c gcc-4.2.2/gcc/resource.c 16237 --- gcc-4.2.2.orig/gcc/resource.c 2007-09-01 11:28:30.000000000 -0400 16238 +++ gcc-4.2.2/gcc/resource.c 2007-12-19 05:04:28.000000000 -0500 16239 @@ -663,9 +663,8 @@ 16240 rtx link; 16241 16242 res->cc = res->memory = 1; 16243 - for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) 16244 - if (call_used_regs[r] || global_regs[r]) 16245 - SET_HARD_REG_BIT (res->regs, r); 16246 + 16247 + IOR_HARD_REG_SET (res->regs, regs_invalidated_by_call); 16248 16249 for (link = CALL_INSN_FUNCTION_USAGE (x); 16250 link; link = XEXP (link, 1)) 16251 diff -Naur gcc-4.2.2.orig/gcc/rtl.h gcc-4.2.2/gcc/rtl.h 16252 --- gcc-4.2.2.orig/gcc/rtl.h 2007-09-01 11:28:30.000000000 -0400 16253 +++ gcc-4.2.2/gcc/rtl.h 2007-11-07 15:48:38.000000000 -0500 16254 @@ -1183,8 +1183,8 @@ 16255 refer to part of a DECL. */ 16256 #define REG_EXPR(RTX) (REG_ATTRS (RTX) == 0 ? 0 : REG_ATTRS (RTX)->decl) 16257 16258 -/* For a MEM rtx, the offset from the start of MEM_DECL, if known, as a 16259 - RTX that is always a CONST_INT. */ 16260 +/* For a REG rtx, the offset from the start of REG_EXPR, if known, as an 16261 + HOST_WIDE_INT. */ 16262 #define REG_OFFSET(RTX) (REG_ATTRS (RTX) == 0 ? 0 : REG_ATTRS (RTX)->offset) 16263 16264 /* Copy the attributes that apply to memory locations from RHS to LHS. */ 14694 16265 diff -Naur gcc-4.2.2.orig/gcc/testsuite/ChangeLog gcc-4.2.2/gcc/testsuite/ChangeLog 14695 --- gcc-4.2.2.orig/gcc/testsuite/ChangeLog 2007-10-07 14:19:47.000000000 -0700 14696 +++ gcc-4.2.2/gcc/testsuite/ChangeLog 2007-10-24 10:54:40.000000000 -0700 14697 @@ -1,3 +1,83 @@ 16266 --- gcc-4.2.2.orig/gcc/testsuite/ChangeLog 2007-10-07 17:19:47.000000000 -0400 16267 +++ gcc-4.2.2/gcc/testsuite/ChangeLog 2007-12-19 05:04:28.000000000 -0500 16268 @@ -1,3 +1,149 @@ 16269 +2007-12-19 Richard Sandiford <rsandifo@nildram.co.uk> 16270 + 16271 + PR rtl-optimization/34456 16272 + * gcc.c-torture/execute/pr34456.c: New test. 16273 + 16274 +2007-12-17 Jakub Jelinek <jakub@redhat.com> 16275 + 16276 + PR bootstrap/34003 16277 + * gcc.dg/pr34003-1.c: New test. 16278 + * gcc.dg/pr34003-2.c: New. 16279 + 16280 +2007-12-10 Simon Martin <simartin@users.sourceforge.net> 16281 + 16282 + PR c++/34059 16283 + * g++.dg/parse/crash40.C: New test. 16284 + 16285 +2007-11-28 Rask Ingemann Lambertsen <rask@sygehus.dk> 16286 + 16287 + Backport from mainline: 16288 + 2007-11-26 Rask Ingemann Lambertsen <rask@sygehus.dk> 16289 + 16290 + PR target/34174 16291 + * gcc.dg/pr34174-1.c: New. 16292 + 16293 +2007-11-26 Uros Bizjak <ubizjak@gmail.com> 16294 + 16295 + PR target/34215 16296 + * gcc.target/i386/pr34215.c: New test. 16297 + 16298 +2007-11-22 Matthias Klose <doko@ubuntu.com> 16299 + 16300 + Backport from mainline: 16301 + 2007-11-17 Richard Guenther <rguenther@suse.de> 16302 + 16303 + PR middle-end/34130 16304 + * gcc.c-torture/execute/pr34130.c: New testcase. 16305 + 16306 +2007-11-22 Richard Sandiford <rsandifo@nildram.co.uk> 16307 + 16308 + PR rtl-optimization/33848 16309 + * gcc.dg/torture/pr33848.c: New test. 16310 + 16311 +2007-11-16 Richard Guenther <rguenther@suse.de> 16312 + 16313 + PR middle-end/34030 16314 + * gcc.c-torture/compile/pr34030.c: New testcase. 16315 + 16316 +2007-11-07 Eric Botcazou <ebotcazou@libertysurf.fr> 16317 + 16318 + * gcc.dg/out-of-bounds-1.c: New test. 16319 + 16320 +2007-11-02 Eric Botcazou <ebotcazou@libertysurf.fr> 16321 + 16322 + PR rtl-optimization/28062 16323 + * gcc.c-torture/compile/20071102-1.c: New test. 16324 + 16325 +2007-10-30 Ed Schouten <ed@fxq.nl> 16326 + 16327 + PR tree-optimization/32500 16328 + * gcc.c-torture/execute/pr32500.c: Fix buffer overflow in testcase. 16329 + 16330 +2007-10-26 Jakub Jelinek <jakub@redhat.com> 16331 + 16332 + PR c++/33744 16333 + * g++.dg/template/arg6.C: New test. 16334 + 14698 16335 +2007-10-24 Richard Sandiford <rsandifo@nildram.co.uk> 14699 16336 + … … 14779 16416 14780 16417 * GCC 4.2.2 released. 16418 diff -Naur gcc-4.2.2.orig/gcc/testsuite/g++.dg/conversion/op4.C gcc-4.2.2/gcc/testsuite/g++.dg/conversion/op4.C 16419 --- gcc-4.2.2.orig/gcc/testsuite/g++.dg/conversion/op4.C 1969-12-31 19:00:00.000000000 -0500 16420 +++ gcc-4.2.2/gcc/testsuite/g++.dg/conversion/op4.C 2007-10-13 02:04:57.000000000 -0400 16421 @@ -0,0 +1,19 @@ 16422 +/* PR c++/26698 */ 16423 +/* { dg-do "compile" } */ 16424 + 16425 +struct X { 16426 + int x; 16427 + X (int i = 0) : x (i) {} 16428 + operator X& (void) const { 16429 + return *(new X); 16430 + } 16431 +}; 16432 + 16433 +void add_one (X & ref) { /* { dg-error "in passing argument" } */ 16434 + ++ ref.x; 16435 +} 16436 + 16437 +void foo() { 16438 + X const a (2); 16439 + add_one(a); /* { dg-error "invalid initialization of reference of type" } */ 16440 +} 16441 diff -Naur gcc-4.2.2.orig/gcc/testsuite/g++.dg/debug/using3.C gcc-4.2.2/gcc/testsuite/g++.dg/debug/using3.C 16442 --- gcc-4.2.2.orig/gcc/testsuite/g++.dg/debug/using3.C 1969-12-31 19:00:00.000000000 -0500 16443 +++ gcc-4.2.2/gcc/testsuite/g++.dg/debug/using3.C 2007-10-10 05:29:13.000000000 -0400 16444 @@ -0,0 +1,8 @@ 16445 +// PR debug/31899 16446 + 16447 +namespace NS { 16448 + int x = 0; 16449 + int &ref = x; 16450 +} 16451 + 16452 +using NS::ref; 16453 diff -Naur gcc-4.2.2.orig/gcc/testsuite/g++.dg/ext/visibility/anon6.C gcc-4.2.2/gcc/testsuite/g++.dg/ext/visibility/anon6.C 16454 --- gcc-4.2.2.orig/gcc/testsuite/g++.dg/ext/visibility/anon6.C 1969-12-31 19:00:00.000000000 -0500 16455 +++ gcc-4.2.2/gcc/testsuite/g++.dg/ext/visibility/anon6.C 2007-10-09 16:52:24.000000000 -0400 16456 @@ -0,0 +1,28 @@ 16457 +// PR c++/33094 16458 +// { dg-final { scan-assembler "1BIiE1cE" } } 16459 +// { dg-final { scan-assembler-not "globl.*1BIiE1cE" } } 16460 +// { dg-final { scan-assembler-not "1CIiE1cE" } } 16461 + 16462 +// Test that B<int>::c is emitted as an internal symbol, and C<int>::c is 16463 +// not emitted. 16464 + 16465 +namespace 16466 +{ 16467 + template <typename T> 16468 + class A 16469 + { 16470 + virtual T f1() { return c; } 16471 + static const T c = 0; 16472 + }; 16473 + 16474 + template <typename T> 16475 + class B 16476 + { 16477 + static const T c = 0; 16478 + }; 16479 + 16480 + template <typename T> const T B<T>::c; 16481 + 16482 + template class A<int>; 16483 + template class B<int>; 16484 +} 16485 diff -Naur gcc-4.2.2.orig/gcc/testsuite/g++.dg/ext/visibility/namespace2.C gcc-4.2.2/gcc/testsuite/g++.dg/ext/visibility/namespace2.C 16486 --- gcc-4.2.2.orig/gcc/testsuite/g++.dg/ext/visibility/namespace2.C 1969-12-31 19:00:00.000000000 -0500 16487 +++ gcc-4.2.2/gcc/testsuite/g++.dg/ext/visibility/namespace2.C 2007-10-09 16:52:24.000000000 -0400 16488 @@ -0,0 +1,20 @@ 16489 +// PR c++/32470 16490 + 16491 +// { dg-require-visibility } 16492 +// { dg-options "-fvisibility=hidden" } 16493 +// { dg-final { scan-hidden "_ZN4Test4testEv" } } 16494 + 16495 +namespace std __attribute__((__visibility__("default"))) { 16496 + template<typename _CharT> 16497 + class basic_streambuf 16498 + { 16499 + friend void getline(); 16500 + }; 16501 + extern template class basic_streambuf<char>; 16502 +} 16503 + 16504 +class Test 16505 +{ 16506 + void test(); 16507 +}; 16508 +void Test::test() { } 16509 diff -Naur gcc-4.2.2.orig/gcc/testsuite/g++.dg/opt/const5.C gcc-4.2.2/gcc/testsuite/g++.dg/opt/const5.C 16510 --- gcc-4.2.2.orig/gcc/testsuite/g++.dg/opt/const5.C 1969-12-31 19:00:00.000000000 -0500 16511 +++ gcc-4.2.2/gcc/testsuite/g++.dg/opt/const5.C 2007-10-16 17:09:41.000000000 -0400 16512 @@ -0,0 +1,13 @@ 16513 +// We don't have a good way of determining how ".rodata" is spelled on 16514 +// all targets, so we limit this test to a few common targets where we 16515 +// do know the spelling. 16516 +// { dg-do compile { target i?86-*-linux* x86_64-*-linux* } } 16517 +// { dg-final { scan-assembler "\\.rodata" } } 16518 + 16519 +template <typename T> 16520 +struct B { 16521 + int i; 16522 +}; 16523 + 16524 +// This declaration should be placed in .rodata. 16525 +const B<int> const_B __attribute__((used)) = { 3 }; 16526 diff -Naur gcc-4.2.2.orig/gcc/testsuite/g++.dg/parse/crash40.C gcc-4.2.2/gcc/testsuite/g++.dg/parse/crash40.C 16527 --- gcc-4.2.2.orig/gcc/testsuite/g++.dg/parse/crash40.C 1969-12-31 19:00:00.000000000 -0500 16528 +++ gcc-4.2.2/gcc/testsuite/g++.dg/parse/crash40.C 2007-12-10 17:54:26.000000000 -0500 16529 @@ -0,0 +1,42 @@ 16530 +/* PR c++/34059 */ 16531 +/* { dg-do "compile" } */ 16532 + 16533 +struct A 16534 +{ 16535 + template<int> void foo(); 16536 +}; 16537 +struct B : A {}; 16538 +struct C : A {}; 16539 + 16540 +class AA 16541 +{ 16542 + template<int> void foo(); /* { dg-error "is private" } */ 16543 +}; 16544 +struct BB : AA {}; 16545 + 16546 +class AAA { 16547 + int get() const {} 16548 +}; 16549 +struct BBB { 16550 + static BBB *foo(); 16551 +private: 16552 + int get() const {} /* { dg-error "is private" } */ 16553 +}; 16554 +template<bool> struct S { 16555 + S(unsigned int = BBB::foo()->AAA::get()); /* { dg-error "is not a base of" } */ 16556 +}; 16557 +template<bool> struct SS { 16558 + SS(unsigned int = BBB::foo()->get()); 16559 +}; 16560 + 16561 +void bar() 16562 +{ 16563 + B().C::foo<0>(); /* { dg-error "is not a member of" } */ 16564 + BB().AA::foo<0>(); /* { dg-error "within this context" } */ 16565 + 16566 + int i; 16567 + i.C::foo<0>(); /* { dg-error "which is of non-class type" } */ 16568 + 16569 + S<false> s; 16570 + SS<false> ss; /* { dg-error "within this context" } */ 16571 +} 16572 diff -Naur gcc-4.2.2.orig/gcc/testsuite/g++.dg/template/arg6.C gcc-4.2.2/gcc/testsuite/g++.dg/template/arg6.C 16573 --- gcc-4.2.2.orig/gcc/testsuite/g++.dg/template/arg6.C 1969-12-31 19:00:00.000000000 -0500 16574 +++ gcc-4.2.2/gcc/testsuite/g++.dg/template/arg6.C 2007-10-26 08:04:57.000000000 -0400 16575 @@ -0,0 +1,15 @@ 16576 +// PR c++/33744 16577 +// { dg-do run } 16578 + 16579 +template <bool B> struct A { bool b; A() : b(B) {}; }; 16580 +A<bool(1)> a; 16581 +A<bool(1<2)> b; 16582 +A<(bool)(2>1)> c; 16583 +A<bool((2>1))> d; 16584 +A<bool(2>1)> e; 16585 + 16586 +int 16587 +main () 16588 +{ 16589 + return (a.b && b.b && c.b && d.b && e.b) ? 0 : 1; 16590 +} 16591 diff -Naur gcc-4.2.2.orig/gcc/testsuite/gcc.c-torture/compile/20071102-1.c gcc-4.2.2/gcc/testsuite/gcc.c-torture/compile/20071102-1.c 16592 --- gcc-4.2.2.orig/gcc/testsuite/gcc.c-torture/compile/20071102-1.c 1969-12-31 19:00:00.000000000 -0500 16593 +++ gcc-4.2.2/gcc/testsuite/gcc.c-torture/compile/20071102-1.c 2007-11-02 07:57:28.000000000 -0400 16594 @@ -0,0 +1,32 @@ 16595 +/* PR rtl-optimization/28062 */ 16596 +/* Original testcase by Martin Michlmayr <tbm@cyrius.com> */ 16597 +/* C testcase by Andrew Pinski <pinskia@gcc.gnu.org> */ 16598 + 16599 +struct _NSPoint 16600 +{ 16601 + float x; 16602 + float y; 16603 +}; 16604 + 16605 +typedef struct _NSPoint NSPoint; 16606 + 16607 +static inline NSPoint 16608 +NSMakePoint (float x, float y) 16609 +{ 16610 + NSPoint point; 16611 + point.x = x; 16612 + point.y = y; 16613 + return point; 16614 +} 16615 + 16616 +static inline NSPoint 16617 +RelativePoint (NSPoint point, NSPoint refPoint) 16618 +{ 16619 + return NSMakePoint (refPoint.x + point.x, refPoint.y + point.y); 16620 +} 16621 + 16622 +NSPoint g(NSPoint refPoint) 16623 +{ 16624 + float pointA, pointB; 16625 + return RelativePoint (NSMakePoint (0, pointA), refPoint); 16626 +} 16627 diff -Naur gcc-4.2.2.orig/gcc/testsuite/gcc.c-torture/compile/pr34030.c gcc-4.2.2/gcc/testsuite/gcc.c-torture/compile/pr34030.c 16628 --- gcc-4.2.2.orig/gcc/testsuite/gcc.c-torture/compile/pr34030.c 1969-12-31 19:00:00.000000000 -0500 16629 +++ gcc-4.2.2/gcc/testsuite/gcc.c-torture/compile/pr34030.c 2007-11-16 16:44:58.000000000 -0500 16630 @@ -0,0 +1,8 @@ 16631 +int myvar; 16632 + 16633 +int foo(int mynum) 16634 +{ 16635 + if ((((void *)0) == (myvar & ((1U<<0) << mynum))) && (mynum > 0)) 16636 + return 1; 16637 + return 0; 16638 +} 16639 diff -Naur gcc-4.2.2.orig/gcc/testsuite/gcc.c-torture/execute/pr32500.c gcc-4.2.2/gcc/testsuite/gcc.c-torture/execute/pr32500.c 16640 --- gcc-4.2.2.orig/gcc/testsuite/gcc.c-torture/execute/pr32500.c 2007-07-04 08:38:23.000000000 -0400 16641 +++ gcc-4.2.2/gcc/testsuite/gcc.c-torture/execute/pr32500.c 2007-10-30 16:29:22.000000000 -0400 16642 @@ -16,7 +16,7 @@ 16643 16644 for (i = 1; i <= 12; i++) { 16645 if (i <= 4) 16646 - foo(numbers[i]); 16647 + foo(numbers[i-1]); 16648 else if (i >= 7 && i <= 9) 16649 bar(); 16650 } 14781 16651 diff -Naur gcc-4.2.2.orig/gcc/testsuite/gcc.c-torture/execute/pr33099.c gcc-4.2.2/gcc/testsuite/gcc.c-torture/execute/pr33099.c 14782 --- gcc-4.2.2.orig/gcc/testsuite/gcc.c-torture/execute/pr33099.c 1969-12-31 1 6:00:00.000000000 -080014783 +++ gcc-4.2.2/gcc/testsuite/gcc.c-torture/execute/pr33099.c 2007-10-10 0 2:24:43.000000000 -070016652 --- gcc-4.2.2.orig/gcc/testsuite/gcc.c-torture/execute/pr33099.c 1969-12-31 19:00:00.000000000 -0500 16653 +++ gcc-4.2.2/gcc/testsuite/gcc.c-torture/execute/pr33099.c 2007-10-10 05:24:43.000000000 -0400 14784 16654 @@ -0,0 +1,26 @@ 14785 16655 +extern void abort (void); … … 14810 16680 +} 14811 16681 diff -Naur gcc-4.2.2.orig/gcc/testsuite/gcc.c-torture/execute/pr33381.c gcc-4.2.2/gcc/testsuite/gcc.c-torture/execute/pr33381.c 14812 --- gcc-4.2.2.orig/gcc/testsuite/gcc.c-torture/execute/pr33381.c 1969-12-31 1 6:00:00.000000000 -080014813 +++ gcc-4.2.2/gcc/testsuite/gcc.c-torture/execute/pr33381.c 2007-10-10 0 2:24:43.000000000 -070016682 --- gcc-4.2.2.orig/gcc/testsuite/gcc.c-torture/execute/pr33381.c 1969-12-31 19:00:00.000000000 -0500 16683 +++ gcc-4.2.2/gcc/testsuite/gcc.c-torture/execute/pr33381.c 2007-10-10 05:24:43.000000000 -0400 14814 16684 @@ -0,0 +1,15 @@ 14815 16685 +extern void abort(void); … … 14828 16698 +} 14829 16699 + 16700 diff -Naur gcc-4.2.2.orig/gcc/testsuite/gcc.c-torture/execute/pr34130.c gcc-4.2.2/gcc/testsuite/gcc.c-torture/execute/pr34130.c 16701 --- gcc-4.2.2.orig/gcc/testsuite/gcc.c-torture/execute/pr34130.c 1969-12-31 19:00:00.000000000 -0500 16702 +++ gcc-4.2.2/gcc/testsuite/gcc.c-torture/execute/pr34130.c 2007-11-22 10:34:03.000000000 -0500 16703 @@ -0,0 +1,12 @@ 16704 +extern void abort (void); 16705 +int foo (int i) 16706 +{ 16707 + return -2 * __builtin_abs(i - 2); 16708 +} 16709 +int main() 16710 +{ 16711 + if (foo(1) != -2 16712 + || foo(3) != -2) 16713 + abort (); 16714 + return 0; 16715 +} 16716 diff -Naur gcc-4.2.2.orig/gcc/testsuite/gcc.c-torture/execute/pr34456.c gcc-4.2.2/gcc/testsuite/gcc.c-torture/execute/pr34456.c 16717 --- gcc-4.2.2.orig/gcc/testsuite/gcc.c-torture/execute/pr34456.c 1969-12-31 19:00:00.000000000 -0500 16718 +++ gcc-4.2.2/gcc/testsuite/gcc.c-torture/execute/pr34456.c 2007-12-19 05:04:28.000000000 -0500 16719 @@ -0,0 +1,30 @@ 16720 +#include <stdlib.h> 16721 + 16722 +int __attribute__ ((noinline)) debug (void) { return 1; } 16723 +int errors; 16724 + 16725 +struct s { int elt; int (*compare) (int); }; 16726 + 16727 +static int 16728 +compare (const void *x, const void *y) 16729 +{ 16730 + const struct s *s1 = x, *s2 = y; 16731 + int (*compare1) (int); 16732 + int elt2; 16733 + 16734 + compare1 = s1->compare; 16735 + elt2 = s2->elt; 16736 + if (elt2 != 0 && debug () && compare1 (s1->elt) != 0) 16737 + errors++; 16738 + return compare1 (elt2); 16739 +} 16740 + 16741 +int bad_compare (int x) { return -x; } 16742 +struct s array[2] = { { 1, bad_compare }, { -1, bad_compare } }; 16743 + 16744 +int 16745 +main (void) 16746 +{ 16747 + qsort (array, 2, sizeof (struct s), compare); 16748 + return errors == 0; 16749 +} 14830 16750 diff -Naur gcc-4.2.2.orig/gcc/testsuite/gcc.dg/enum-incomplete-1.c gcc-4.2.2/gcc/testsuite/gcc.dg/enum-incomplete-1.c 14831 --- gcc-4.2.2.orig/gcc/testsuite/gcc.dg/enum-incomplete-1.c 1969-12-31 1 6:00:00.000000000 -080014832 +++ gcc-4.2.2/gcc/testsuite/gcc.dg/enum-incomplete-1.c 2007-10-10 1 1:24:29.000000000 -070016751 --- gcc-4.2.2.orig/gcc/testsuite/gcc.dg/enum-incomplete-1.c 1969-12-31 19:00:00.000000000 -0500 16752 +++ gcc-4.2.2/gcc/testsuite/gcc.dg/enum-incomplete-1.c 2007-10-10 14:24:29.000000000 -0400 14833 16753 @@ -0,0 +1,86 @@ 14834 16754 +/* Test for uses of incomplete enum variables: should be allowed just … … 14919 16839 +} 14920 16840 diff -Naur gcc-4.2.2.orig/gcc/testsuite/gcc.dg/globalreg-1.c gcc-4.2.2/gcc/testsuite/gcc.dg/globalreg-1.c 14921 --- gcc-4.2.2.orig/gcc/testsuite/gcc.dg/globalreg-1.c 1969-12-31 1 6:00:00.000000000 -080014922 +++ gcc-4.2.2/gcc/testsuite/gcc.dg/globalreg-1.c 2007-10-2 2 21:37:02.000000000 -070016841 --- gcc-4.2.2.orig/gcc/testsuite/gcc.dg/globalreg-1.c 1969-12-31 19:00:00.000000000 -0500 16842 +++ gcc-4.2.2/gcc/testsuite/gcc.dg/globalreg-1.c 2007-10-23 00:37:02.000000000 -0400 14923 16843 @@ -0,0 +1,54 @@ 14924 16844 +/* { dg-do run { target sparc*-*-* } } */ … … 14977 16897 +} 14978 16898 diff -Naur gcc-4.2.2.orig/gcc/testsuite/gcc.dg/large-size-array-2.c gcc-4.2.2/gcc/testsuite/gcc.dg/large-size-array-2.c 14979 --- gcc-4.2.2.orig/gcc/testsuite/gcc.dg/large-size-array-2.c 2006-04-28 1 2:59:57.000000000 -070014980 +++ gcc-4.2.2/gcc/testsuite/gcc.dg/large-size-array-2.c 2007-10-10 1 3:46:11.000000000 -070016899 --- gcc-4.2.2.orig/gcc/testsuite/gcc.dg/large-size-array-2.c 2006-04-28 15:59:57.000000000 -0400 16900 +++ gcc-4.2.2/gcc/testsuite/gcc.dg/large-size-array-2.c 2007-10-10 16:46:11.000000000 -0400 14981 16901 @@ -4,4 +4,4 @@ 14982 16902 static char * name[] = { … … 14986 16906 +/* { dg-error "too large" "" { target { ! lp64 } } 6 } */ 14987 16907 diff -Naur gcc-4.2.2.orig/gcc/testsuite/gcc.dg/large-size-array-4.c gcc-4.2.2/gcc/testsuite/gcc.dg/large-size-array-4.c 14988 --- gcc-4.2.2.orig/gcc/testsuite/gcc.dg/large-size-array-4.c 1969-12-31 1 6:00:00.000000000 -080014989 +++ gcc-4.2.2/gcc/testsuite/gcc.dg/large-size-array-4.c 2007-10-10 1 3:46:11.000000000 -070016908 --- gcc-4.2.2.orig/gcc/testsuite/gcc.dg/large-size-array-4.c 1969-12-31 19:00:00.000000000 -0500 16909 +++ gcc-4.2.2/gcc/testsuite/gcc.dg/large-size-array-4.c 2007-10-10 16:46:11.000000000 -0400 14990 16910 @@ -0,0 +1,7 @@ 14991 16911 +/* PR c/25309 */ … … 14996 16916 + }; 14997 16917 +/* { dg-error "too large" "" { target { ! lp64 } } 6 } */ 16918 diff -Naur gcc-4.2.2.orig/gcc/testsuite/gcc.dg/out-of-bounds-1.c gcc-4.2.2/gcc/testsuite/gcc.dg/out-of-bounds-1.c 16919 --- gcc-4.2.2.orig/gcc/testsuite/gcc.dg/out-of-bounds-1.c 1969-12-31 19:00:00.000000000 -0500 16920 +++ gcc-4.2.2/gcc/testsuite/gcc.dg/out-of-bounds-1.c 2007-11-07 15:48:38.000000000 -0500 16921 @@ -0,0 +1,13 @@ 16922 +/* PR rtl-optimization/33822 */ 16923 +/* Origin: Andrew Pinski <pinskia@gcc.gnu.org> */ 16924 + 16925 +/* { dg-do compile } */ 16926 +/* { dg-options "-O -g" } */ 16927 +/* { dg-options "-O -g -mstrict-align" { target powerpc*-*-* } } */ 16928 + 16929 +void ProjectOverlay(const float localTextureAxis[2], char *lump) 16930 +{ 16931 + const void *d = &localTextureAxis; 16932 + int size = sizeof(float)*8 ; 16933 + __builtin_memcpy( &lump[ 0 ], d, size ); 16934 +} 16935 diff -Naur gcc-4.2.2.orig/gcc/testsuite/gcc.dg/pr34003-1.c gcc-4.2.2/gcc/testsuite/gcc.dg/pr34003-1.c 16936 --- gcc-4.2.2.orig/gcc/testsuite/gcc.dg/pr34003-1.c 1969-12-31 19:00:00.000000000 -0500 16937 +++ gcc-4.2.2/gcc/testsuite/gcc.dg/pr34003-1.c 2007-12-18 00:05:43.000000000 -0500 16938 @@ -0,0 +1,8 @@ 16939 +/* PR bootstrap/34003 */ 16940 +/* { dg-do link } */ 16941 +/* { dg-options "-O0" } */ 16942 +/* { dg-additional-sources "pr34003-2.c" } */ 16943 + 16944 +extern void foo (void); 16945 +int bar (void) { foo (); return 1; } 16946 +extern void foo (void); 16947 diff -Naur gcc-4.2.2.orig/gcc/testsuite/gcc.dg/pr34003-2.c gcc-4.2.2/gcc/testsuite/gcc.dg/pr34003-2.c 16948 --- gcc-4.2.2.orig/gcc/testsuite/gcc.dg/pr34003-2.c 1969-12-31 19:00:00.000000000 -0500 16949 +++ gcc-4.2.2/gcc/testsuite/gcc.dg/pr34003-2.c 2007-12-18 00:05:43.000000000 -0500 16950 @@ -0,0 +1,20 @@ 16951 +/* PR bootstrap/34003 */ 16952 +/* { dg-do compile } */ 16953 +/* { dg-options "-O0" } */ 16954 + 16955 +extern void abort (void); 16956 + 16957 +int seen = 0; 16958 + 16959 +void foo (void) 16960 +{ 16961 + ++seen; 16962 +} 16963 + 16964 +int main (void) 16965 +{ 16966 + extern int bar (void); 16967 + if (bar () != 1 || seen != 1) 16968 + abort (); 16969 + return 0; 16970 +} 16971 diff -Naur gcc-4.2.2.orig/gcc/testsuite/gcc.dg/pr34174-1.c gcc-4.2.2/gcc/testsuite/gcc.dg/pr34174-1.c 16972 --- gcc-4.2.2.orig/gcc/testsuite/gcc.dg/pr34174-1.c 1969-12-31 19:00:00.000000000 -0500 16973 +++ gcc-4.2.2/gcc/testsuite/gcc.dg/pr34174-1.c 2007-11-27 20:44:10.000000000 -0500 16974 @@ -0,0 +1,45 @@ 16975 +/* { dg-do run } */ 16976 +/* { dg-options "-std=gnu89" } */ 16977 +/* Based on PR target/27386 testcase by Joerg Wunsch. */ 16978 + 16979 +extern void abort (void); 16980 +extern void exit (int); 16981 + 16982 +#if __INT_MAX__ >= 9223372036854775807LL 16983 +typedef unsigned int uint64_t; 16984 +#elif __LONG_MAX__ >= 9223372036854775807LL 16985 +typedef unsigned long int uint64_t; 16986 +#elif __LONG_LONG_MAX__ >= 9223372036854775807LL 16987 +typedef unsigned long long int uint64_t; 16988 +#else 16989 +int 16990 +main (void) 16991 +{ 16992 + exit (0); 16993 +} 16994 +#endif 16995 + 16996 +uint64_t a, b, c; 16997 + 16998 +int 16999 +foo (uint64_t x, uint64_t y, uint64_t z, int i) 17000 +{ 17001 + a = x; 17002 + b = y; 17003 + c = z; 17004 + return 2 * i; 17005 +} 17006 + 17007 +int 17008 +main (void) 17009 +{ 17010 + if (foo (1234512345123ull, 3456734567345ull, 7897897897897ull, 42) != 84) 17011 + abort (); 17012 + if (a != 1234512345123ull) 17013 + abort (); 17014 + if (b != 3456734567345ull) 17015 + abort (); 17016 + if (c != 7897897897897ull) 17017 + abort (); 17018 + exit (0); 17019 +} 17020 diff -Naur gcc-4.2.2.orig/gcc/testsuite/gcc.dg/torture/pr33848.c gcc-4.2.2/gcc/testsuite/gcc.dg/torture/pr33848.c 17021 --- gcc-4.2.2.orig/gcc/testsuite/gcc.dg/torture/pr33848.c 1969-12-31 19:00:00.000000000 -0500 17022 +++ gcc-4.2.2/gcc/testsuite/gcc.dg/torture/pr33848.c 2007-11-22 04:27:55.000000000 -0500 17023 @@ -0,0 +1,43 @@ 17024 +/* &&foo should be hoisted, but on most targets, excess register pressure 17025 + forces it to be rematerialized before "data != &&foo". On targets that 17026 + have a "branch if registers are equal" instruction, this leads to the 17027 + branch having two LABEL_REFs: one for the branch target and one for 17028 + &&foo. When reloading &&foo into a register, reload would wrongly 17029 + say that &&foo was the target of the branch, and the real target would 17030 + then be removed as dead. */ 17031 +/* { dg-do link } */ 17032 +#define NVARS 30 17033 +#define MULTI(X) \ 17034 + X( 0), X( 1), X( 2), X( 3), X( 4), X( 5), X( 6), X( 7), X( 8), X( 9), \ 17035 + X(10), X(11), X(12), X(13), X(14), X(15), X(16), X(17), X(18), X(19), \ 17036 + X(20), X(21), X(22), X(23), X(24), X(25), X(26), X(27), X(28), X(29) 17037 + 17038 +#define DECLARE(INDEX) i##INDEX = gv[INDEX] 17039 +#define COPY(INDEX) gv[INDEX] = i##INDEX 17040 + 17041 +volatile int gv[NVARS]; 17042 +void *volatile data; 17043 + 17044 +int 17045 +main (void) 17046 +{ 17047 + __label__ foo; 17048 + 17049 + if (gv[0] == 1) 17050 + goto foo; 17051 + data = &&foo; 17052 + do 17053 + { 17054 + int MULTI (DECLARE); 17055 + MULTI (COPY); 17056 + MULTI (COPY); 17057 + MULTI (COPY); 17058 + if (data != &&foo) 17059 + gv[0] = 1; 17060 + else 17061 + gv[1] = 2; 17062 + } 17063 + while (gv[0] > 0); 17064 + foo: 17065 + return 0; 17066 +} 14998 17067 diff -Naur gcc-4.2.2.orig/gcc/testsuite/gcc.dg/tree-ssa/pr33714.c gcc-4.2.2/gcc/testsuite/gcc.dg/tree-ssa/pr33714.c 14999 --- gcc-4.2.2.orig/gcc/testsuite/gcc.dg/tree-ssa/pr33714.c 1969-12-31 1 6:00:00.000000000 -080015000 +++ gcc-4.2.2/gcc/testsuite/gcc.dg/tree-ssa/pr33714.c 2007-10-12 1 5:26:47.000000000 -070017068 --- gcc-4.2.2.orig/gcc/testsuite/gcc.dg/tree-ssa/pr33714.c 1969-12-31 19:00:00.000000000 -0500 17069 +++ gcc-4.2.2/gcc/testsuite/gcc.dg/tree-ssa/pr33714.c 2007-10-12 18:26:47.000000000 -0400 15001 17070 @@ -0,0 +1,59 @@ 15002 17071 +/* { dg-do run } */ … … 15060 17129 +} 15061 17130 diff -Naur gcc-4.2.2.orig/gcc/testsuite/gcc.dg/vect/pr33369.c gcc-4.2.2/gcc/testsuite/gcc.dg/vect/pr33369.c 15062 --- gcc-4.2.2.orig/gcc/testsuite/gcc.dg/vect/pr33369.c 1969-12-31 1 6:00:00.000000000 -080015063 +++ gcc-4.2.2/gcc/testsuite/gcc.dg/vect/pr33369.c 2007-10-10 0 3:01:53.000000000 -070017131 --- gcc-4.2.2.orig/gcc/testsuite/gcc.dg/vect/pr33369.c 1969-12-31 19:00:00.000000000 -0500 17132 +++ gcc-4.2.2/gcc/testsuite/gcc.dg/vect/pr33369.c 2007-10-10 06:01:53.000000000 -0400 15064 17133 @@ -0,0 +1,21 @@ 15065 17134 +/* { dg-do compile } */ … … 15085 17154 +/* { dg-final { cleanup-tree-dump "vect" } } */ 15086 17155 diff -Naur gcc-4.2.2.orig/gcc/testsuite/gcc.target/i386/pr31167.c gcc-4.2.2/gcc/testsuite/gcc.target/i386/pr31167.c 15087 --- gcc-4.2.2.orig/gcc/testsuite/gcc.target/i386/pr31167.c 2007-05-21 0 4:31:14.000000000 -070015088 +++ gcc-4.2.2/gcc/testsuite/gcc.target/i386/pr31167.c 2007-10-18 0 1:59:31.000000000 -070017156 --- gcc-4.2.2.orig/gcc/testsuite/gcc.target/i386/pr31167.c 2007-05-21 07:31:14.000000000 -0400 17157 +++ gcc-4.2.2/gcc/testsuite/gcc.target/i386/pr31167.c 2007-10-18 04:59:31.000000000 -0400 15089 17158 @@ -1,4 +1,5 @@ 15090 17159 -/* { dg-do compile { target x86_64-*-* } } */ … … 15095 17164 typedef int int32_t; 15096 17165 diff -Naur gcc-4.2.2.orig/gcc/testsuite/gcc.target/i386/pr32961.c gcc-4.2.2/gcc/testsuite/gcc.target/i386/pr32961.c 15097 --- gcc-4.2.2.orig/gcc/testsuite/gcc.target/i386/pr32961.c 1969-12-31 1 6:00:00.000000000 -080015098 +++ gcc-4.2.2/gcc/testsuite/gcc.target/i386/pr32961.c 2007-10-18 0 2:12:30.000000000 -070017166 --- gcc-4.2.2.orig/gcc/testsuite/gcc.target/i386/pr32961.c 1969-12-31 19:00:00.000000000 -0500 17167 +++ gcc-4.2.2/gcc/testsuite/gcc.target/i386/pr32961.c 2007-10-18 05:12:30.000000000 -0400 15099 17168 @@ -0,0 +1,10 @@ 15100 17169 +/* { dg-do compile } */ … … 15109 17178 +} 15110 17179 diff -Naur gcc-4.2.2.orig/gcc/testsuite/gcc.target/i386/pr33483.c gcc-4.2.2/gcc/testsuite/gcc.target/i386/pr33483.c 15111 --- gcc-4.2.2.orig/gcc/testsuite/gcc.target/i386/pr33483.c 1969-12-31 1 6:00:00.000000000 -080015112 +++ gcc-4.2.2/gcc/testsuite/gcc.target/i386/pr33483.c 2007-10-10 0 3:01:53.000000000 -070017180 --- gcc-4.2.2.orig/gcc/testsuite/gcc.target/i386/pr33483.c 1969-12-31 19:00:00.000000000 -0500 17181 +++ gcc-4.2.2/gcc/testsuite/gcc.target/i386/pr33483.c 2007-10-10 06:01:53.000000000 -0400 15113 17182 @@ -0,0 +1,12 @@ 15114 17183 +/* { dg-do compile } */ … … 15124 17193 + return __builtin_remainderl (x, x); 15125 17194 +} 17195 diff -Naur gcc-4.2.2.orig/gcc/testsuite/gcc.target/i386/pr34215.c gcc-4.2.2/gcc/testsuite/gcc.target/i386/pr34215.c 17196 --- gcc-4.2.2.orig/gcc/testsuite/gcc.target/i386/pr34215.c 1969-12-31 19:00:00.000000000 -0500 17197 +++ gcc-4.2.2/gcc/testsuite/gcc.target/i386/pr34215.c 2007-11-26 09:22:59.000000000 -0500 17198 @@ -0,0 +1,18 @@ 17199 +/* Testcase by Martin Michlmayr <tbm@cyrius.com> */ 17200 + 17201 +/* { dg-do compile { target { { i?86-*-* x86_64-*-* } && ilp32 } } } */ 17202 +/* { dg-options "-O2" } */ 17203 + 17204 +double pow (double, double); 17205 + 17206 +void calc_score_dist (int mxdlen, long double d, long double **dist) 17207 +{ 17208 + unsigned long i, scr2; 17209 + for (i = 1; i <= mxdlen; i++) 17210 + { 17211 + for (scr2 = mxdlen; scr2 <= mxdlen + 10; scr2++) 17212 + { 17213 + } 17214 + dist[i][scr2] *= pow (1.0 / d, i); 17215 + } 17216 +} 15126 17217 diff -Naur gcc-4.2.2.orig/gcc/testsuite/gcc.target/mips/pr33755.c gcc-4.2.2/gcc/testsuite/gcc.target/mips/pr33755.c 15127 --- gcc-4.2.2.orig/gcc/testsuite/gcc.target/mips/pr33755.c 1969-12-31 1 6:00:00.000000000 -080015128 +++ gcc-4.2.2/gcc/testsuite/gcc.target/mips/pr33755.c 2007-10-24 1 0:54:40.000000000 -070017218 --- gcc-4.2.2.orig/gcc/testsuite/gcc.target/mips/pr33755.c 1969-12-31 19:00:00.000000000 -0500 17219 +++ gcc-4.2.2/gcc/testsuite/gcc.target/mips/pr33755.c 2007-10-24 13:54:40.000000000 -0400 15129 17220 @@ -0,0 +1,30 @@ 15130 17221 +/* { dg-do link } */ … … 15158 17249 + return 0; 15159 17250 +} 15160 diff -Naur gcc-4.2.2.orig/gcc/testsuite/g++.dg/conversion/op4.C gcc-4.2.2/gcc/testsuite/g++.dg/conversion/op4.C15161 --- gcc-4.2.2.orig/gcc/testsuite/g++.dg/conversion/op4.C 1969-12-31 16:00:00.000000000 -080015162 +++ gcc-4.2.2/gcc/testsuite/g++.dg/conversion/op4.C 2007-10-12 23:04:57.000000000 -070015163 @@ -0,0 +1,19 @@15164 +/* PR c++/26698 */15165 +/* { dg-do "compile" } */15166 +15167 +struct X {15168 + int x;15169 + X (int i = 0) : x (i) {}15170 + operator X& (void) const {15171 + return *(new X);15172 + }15173 +};15174 +15175 +void add_one (X & ref) { /* { dg-error "in passing argument" } */15176 + ++ ref.x;15177 +}15178 +15179 +void foo() {15180 + X const a (2);15181 + add_one(a); /* { dg-error "invalid initialization of reference of type" } */15182 +}15183 diff -Naur gcc-4.2.2.orig/gcc/testsuite/g++.dg/debug/using3.C gcc-4.2.2/gcc/testsuite/g++.dg/debug/using3.C15184 --- gcc-4.2.2.orig/gcc/testsuite/g++.dg/debug/using3.C 1969-12-31 16:00:00.000000000 -080015185 +++ gcc-4.2.2/gcc/testsuite/g++.dg/debug/using3.C 2007-10-10 02:29:13.000000000 -070015186 @@ -0,0 +1,8 @@15187 +// PR debug/3189915188 +15189 +namespace NS {15190 + int x = 0;15191 + int &ref = x;15192 +}15193 +15194 +using NS::ref;15195 diff -Naur gcc-4.2.2.orig/gcc/testsuite/g++.dg/ext/visibility/anon6.C gcc-4.2.2/gcc/testsuite/g++.dg/ext/visibility/anon6.C15196 --- gcc-4.2.2.orig/gcc/testsuite/g++.dg/ext/visibility/anon6.C 1969-12-31 16:00:00.000000000 -080015197 +++ gcc-4.2.2/gcc/testsuite/g++.dg/ext/visibility/anon6.C 2007-10-09 13:52:24.000000000 -070015198 @@ -0,0 +1,28 @@15199 +// PR c++/3309415200 +// { dg-final { scan-assembler "1BIiE1cE" } }15201 +// { dg-final { scan-assembler-not "globl.*1BIiE1cE" } }15202 +// { dg-final { scan-assembler-not "1CIiE1cE" } }15203 +15204 +// Test that B<int>::c is emitted as an internal symbol, and C<int>::c is15205 +// not emitted.15206 +15207 +namespace15208 +{15209 + template <typename T>15210 + class A15211 + {15212 + virtual T f1() { return c; }15213 + static const T c = 0;15214 + };15215 +15216 + template <typename T>15217 + class B15218 + {15219 + static const T c = 0;15220 + };15221 +15222 + template <typename T> const T B<T>::c;15223 +15224 + template class A<int>;15225 + template class B<int>;15226 +}15227 diff -Naur gcc-4.2.2.orig/gcc/testsuite/g++.dg/ext/visibility/namespace2.C gcc-4.2.2/gcc/testsuite/g++.dg/ext/visibility/namespace2.C15228 --- gcc-4.2.2.orig/gcc/testsuite/g++.dg/ext/visibility/namespace2.C 1969-12-31 16:00:00.000000000 -080015229 +++ gcc-4.2.2/gcc/testsuite/g++.dg/ext/visibility/namespace2.C 2007-10-09 13:52:24.000000000 -070015230 @@ -0,0 +1,20 @@15231 +// PR c++/3247015232 +15233 +// { dg-require-visibility }15234 +// { dg-options "-fvisibility=hidden" }15235 +// { dg-final { scan-hidden "_ZN4Test4testEv" } }15236 +15237 +namespace std __attribute__((__visibility__("default"))) {15238 + template<typename _CharT>15239 + class basic_streambuf15240 + {15241 + friend void getline();15242 + };15243 + extern template class basic_streambuf<char>;15244 +}15245 +15246 +class Test15247 +{15248 + void test();15249 +};15250 +void Test::test() { }15251 diff -Naur gcc-4.2.2.orig/gcc/testsuite/g++.dg/opt/const5.C gcc-4.2.2/gcc/testsuite/g++.dg/opt/const5.C15252 --- gcc-4.2.2.orig/gcc/testsuite/g++.dg/opt/const5.C 1969-12-31 16:00:00.000000000 -080015253 +++ gcc-4.2.2/gcc/testsuite/g++.dg/opt/const5.C 2007-10-16 14:09:41.000000000 -070015254 @@ -0,0 +1,13 @@15255 +// We don't have a good way of determining how ".rodata" is spelled on15256 +// all targets, so we limit this test to a few common targets where we15257 +// do know the spelling.15258 +// { dg-do compile { target i?86-*-linux* x86_64-*-linux* } }15259 +// { dg-final { scan-assembler "\\.rodata" } }15260 +15261 +template <typename T>15262 +struct B {15263 + int i;15264 +};15265 +15266 +// This declaration should be placed in .rodata.15267 +const B<int> const_B __attribute__((used)) = { 3 };15268 17251 diff -Naur gcc-4.2.2.orig/gcc/testsuite/gfortran.dg/minmaxloc_4.f90 gcc-4.2.2/gcc/testsuite/gfortran.dg/minmaxloc_4.f90 15269 --- gcc-4.2.2.orig/gcc/testsuite/gfortran.dg/minmaxloc_4.f90 1969-12-31 1 6:00:00.000000000 -080015270 +++ gcc-4.2.2/gcc/testsuite/gfortran.dg/minmaxloc_4.f90 2007-10-15 1 1:23:39.000000000 -070017252 --- gcc-4.2.2.orig/gcc/testsuite/gfortran.dg/minmaxloc_4.f90 1969-12-31 19:00:00.000000000 -0500 17253 +++ gcc-4.2.2/gcc/testsuite/gfortran.dg/minmaxloc_4.f90 2007-10-15 14:23:39.000000000 -0400 15271 17254 @@ -0,0 +1,21 @@ 15272 17255 +! { dg-do run } … … 15292 17275 +END PROGRAM TST 15293 17276 diff -Naur gcc-4.2.2.orig/gcc/tree-ssa-loop-ivopts.c gcc-4.2.2/gcc/tree-ssa-loop-ivopts.c 15294 --- gcc-4.2.2.orig/gcc/tree-ssa-loop-ivopts.c 2007-09-01 08:28:30.000000000 -070015295 +++ gcc-4.2.2/gcc/tree-ssa-loop-ivopts.c 2007-10-12 1 5:26:47.000000000 -070017277 --- gcc-4.2.2.orig/gcc/tree-ssa-loop-ivopts.c 2007-09-01 11:28:30.000000000 -0400 17278 +++ gcc-4.2.2/gcc/tree-ssa-loop-ivopts.c 2007-10-12 18:26:47.000000000 -0400 15296 17279 @@ -2608,8 +2608,8 @@ 15297 17280 if (TREE_CODE (bot) != INTEGER_CST) … … 15306 17289 *mul = double_int_sext (double_int_sdivmod (p0, p1, FLOOR_DIV_EXPR, &res), 15307 17290 diff -Naur gcc-4.2.2.orig/gcc/tree-vrp.c gcc-4.2.2/gcc/tree-vrp.c 15308 --- gcc-4.2.2.orig/gcc/tree-vrp.c 2007-09-01 08:28:30.000000000 -070015309 +++ gcc-4.2.2/gcc/tree-vrp.c 2007-10-10 0 2:24:43.000000000 -070017291 --- gcc-4.2.2.orig/gcc/tree-vrp.c 2007-09-01 11:28:30.000000000 -0400 17292 +++ gcc-4.2.2/gcc/tree-vrp.c 2007-10-10 05:24:43.000000000 -0400 15310 17293 @@ -2486,6 +2486,10 @@ 15311 17294 if (TREE_CODE (chrec) != POLYNOMIAL_CHREC) … … 15319 17302 step = evolution_part_in_loop_num (chrec, loop->num); 15320 17303 17304 diff -Naur gcc-4.2.2.orig/gcc/var-tracking.c gcc-4.2.2/gcc/var-tracking.c 17305 --- gcc-4.2.2.orig/gcc/var-tracking.c 2007-09-01 11:28:30.000000000 -0400 17306 +++ gcc-4.2.2/gcc/var-tracking.c 2007-11-07 15:48:38.000000000 -0500 17307 @@ -258,6 +258,9 @@ 17308 /* Pointer to the BB's information specific to variable tracking pass. */ 17309 #define VTI(BB) ((variable_tracking_info) (BB)->aux) 17310 17311 +/* Macro to access MEM_OFFSET as an HOST_WIDE_INT. Evaluates MEM twice. */ 17312 +#define INT_MEM_OFFSET(mem) (MEM_OFFSET (mem) ? INTVAL (MEM_OFFSET (mem)) : 0) 17313 + 17314 /* Alloc pool for struct attrs_def. */ 17315 static alloc_pool attrs_pool; 17316 17317 @@ -926,7 +929,7 @@ 17318 var_mem_set (dataflow_set *set, rtx loc) 17319 { 17320 tree decl = MEM_EXPR (loc); 17321 - HOST_WIDE_INT offset = MEM_OFFSET (loc) ? INTVAL (MEM_OFFSET (loc)) : 0; 17322 + HOST_WIDE_INT offset = INT_MEM_OFFSET (loc); 17323 17324 decl = var_debug_decl (decl); 17325 17326 @@ -944,7 +947,7 @@ 17327 var_mem_delete_and_set (dataflow_set *set, rtx loc, bool modify) 17328 { 17329 tree decl = MEM_EXPR (loc); 17330 - HOST_WIDE_INT offset = MEM_OFFSET (loc) ? INTVAL (MEM_OFFSET (loc)) : 0; 17331 + HOST_WIDE_INT offset = INT_MEM_OFFSET (loc); 17332 17333 decl = var_debug_decl (decl); 17334 17335 @@ -961,7 +964,7 @@ 17336 var_mem_delete (dataflow_set *set, rtx loc, bool clobber) 17337 { 17338 tree decl = MEM_EXPR (loc); 17339 - HOST_WIDE_INT offset = MEM_OFFSET (loc) ? INTVAL (MEM_OFFSET (loc)) : 0; 17340 + HOST_WIDE_INT offset = INT_MEM_OFFSET (loc); 17341 17342 decl = var_debug_decl (decl); 17343 if (clobber) 17344 @@ -1539,6 +1542,18 @@ 17345 return 1; 17346 } 17347 17348 +/* Return true if OFFSET is a valid offset for a register or memory 17349 + access we want to track. This is used to reject out-of-bounds 17350 + accesses that can cause assertions to fail later. Note that we 17351 + don't reject negative offsets because they can be generated for 17352 + paradoxical subregs on big-endian architectures. */ 17353 + 17354 +static inline bool 17355 +offset_valid_for_tracked_p (HOST_WIDE_INT offset) 17356 +{ 17357 + return (-MAX_VAR_PARTS < offset) && (offset < MAX_VAR_PARTS); 17358 +} 17359 + 17360 /* Determine whether a given LOC refers to the same variable part as 17361 EXPR+OFFSET. */ 17362 17363 @@ -1559,7 +1574,7 @@ 17364 else if (MEM_P (loc)) 17365 { 17366 expr2 = MEM_EXPR (loc); 17367 - offset2 = MEM_OFFSET (loc) ? INTVAL (MEM_OFFSET (loc)) : 0; 17368 + offset2 = INT_MEM_OFFSET (loc); 17369 } 17370 else 17371 return false; 17372 @@ -1589,7 +1604,8 @@ 17373 } 17374 else if (MEM_P (*loc) 17375 && MEM_EXPR (*loc) 17376 - && track_expr_p (MEM_EXPR (*loc))) 17377 + && track_expr_p (MEM_EXPR (*loc)) 17378 + && offset_valid_for_tracked_p (INT_MEM_OFFSET (*loc))) 17379 { 17380 VTI (bb)->n_mos++; 17381 } 17382 @@ -1625,14 +1641,19 @@ 17383 basic_block bb = BLOCK_FOR_INSN ((rtx) insn); 17384 micro_operation *mo = VTI (bb)->mos + VTI (bb)->n_mos++; 17385 17386 - mo->type = ((REG_EXPR (*loc) && track_expr_p (REG_EXPR (*loc))) 17387 - ? MO_USE : MO_USE_NO_VAR); 17388 + if (REG_EXPR (*loc) 17389 + && track_expr_p (REG_EXPR (*loc)) 17390 + && offset_valid_for_tracked_p (REG_OFFSET (*loc))) 17391 + mo->type = MO_USE; 17392 + else 17393 + mo->type = MO_USE_NO_VAR; 17394 mo->u.loc = *loc; 17395 mo->insn = (rtx) insn; 17396 } 17397 else if (MEM_P (*loc) 17398 && MEM_EXPR (*loc) 17399 - && track_expr_p (MEM_EXPR (*loc))) 17400 + && track_expr_p (MEM_EXPR (*loc)) 17401 + && offset_valid_for_tracked_p (INT_MEM_OFFSET (*loc))) 17402 { 17403 basic_block bb = BLOCK_FOR_INSN ((rtx) insn); 17404 micro_operation *mo = VTI (bb)->mos + VTI (bb)->n_mos++; 17405 @@ -1666,8 +1687,9 @@ 17406 micro_operation *mo = VTI (bb)->mos + VTI (bb)->n_mos++; 17407 17408 if (GET_CODE (expr) == CLOBBER 17409 - || ! REG_EXPR (loc) 17410 - || ! track_expr_p (REG_EXPR (loc))) 17411 + || !(REG_EXPR (loc) 17412 + && track_expr_p (REG_EXPR (loc)) 17413 + && offset_valid_for_tracked_p (REG_OFFSET (loc)))) 17414 mo->type = MO_CLOBBER; 17415 else if (GET_CODE (expr) == SET 17416 && SET_DEST (expr) == loc 17417 @@ -1682,7 +1704,8 @@ 17418 } 17419 else if (MEM_P (loc) 17420 && MEM_EXPR (loc) 17421 - && track_expr_p (MEM_EXPR (loc))) 17422 + && track_expr_p (MEM_EXPR (loc)) 17423 + && offset_valid_for_tracked_p (INT_MEM_OFFSET (loc))) 17424 { 17425 basic_block bb = BLOCK_FOR_INSN ((rtx) insn); 17426 micro_operation *mo = VTI (bb)->mos + VTI (bb)->n_mos++; 17427 @@ -1693,8 +1716,7 @@ 17428 && SET_DEST (expr) == loc 17429 && same_variable_part_p (SET_SRC (expr), 17430 MEM_EXPR (loc), 17431 - MEM_OFFSET (loc) 17432 - ? INTVAL (MEM_OFFSET (loc)) : 0)) 17433 + INT_MEM_OFFSET (loc))) 17434 mo->type = MO_COPY; 17435 else 17436 mo->type = MO_SET; 17437 @@ -2725,7 +2747,7 @@ 17438 if (MEM_ATTRS (rtl)) 17439 { 17440 *declp = MEM_EXPR (rtl); 17441 - *offsetp = MEM_OFFSET (rtl) ? INTVAL (MEM_OFFSET (rtl)) : 0; 17442 + *offsetp = INT_MEM_OFFSET (rtl); 17443 return true; 17444 } 17445 } 15321 17446 diff -Naur gcc-4.2.2.orig/libcpp/po/ChangeLog gcc-4.2.2/libcpp/po/ChangeLog 15322 --- gcc-4.2.2.orig/libcpp/po/ChangeLog 2007-10-07 1 4:20:42.000000000 -070015323 +++ gcc-4.2.2/libcpp/po/ChangeLog 2007-10-21 1 0:58:45.000000000 -070017447 --- gcc-4.2.2.orig/libcpp/po/ChangeLog 2007-10-07 17:20:42.000000000 -0400 17448 +++ gcc-4.2.2/libcpp/po/ChangeLog 2007-10-21 13:58:45.000000000 -0400 15324 17449 @@ -1,3 +1,12 @@ 15325 17450 +2007-10-21 Joseph S. Myers <joseph@codesourcery.com> … … 15335 17460 15336 17461 * GCC 4.2.2 released. 17462 diff -Naur gcc-4.2.2.orig/libgomp/ChangeLog gcc-4.2.2/libgomp/ChangeLog 17463 --- gcc-4.2.2.orig/libgomp/ChangeLog 2007-10-07 17:19:35.000000000 -0400 17464 +++ gcc-4.2.2/libgomp/ChangeLog 2007-11-23 04:30:22.000000000 -0500 17465 @@ -1,3 +1,8 @@ 17466 +2007-11-23 Matthias Klose <doko@ubuntu.com> 17467 + 17468 + * configure.ac: Adjust makeinfo version check. 17469 + * configure: Regenerate. 17470 + 17471 2007-10-07 Release Manager 17472 17473 * GCC 4.2.2 released. 17474 diff -Naur gcc-4.2.2.orig/libgomp/configure gcc-4.2.2/libgomp/configure 17475 --- gcc-4.2.2.orig/libgomp/configure 2007-10-07 17:23:16.000000000 -0400 17476 +++ gcc-4.2.2/libgomp/configure 2007-11-23 04:30:22.000000000 -0500 17477 @@ -718,13 +718,13 @@ 17478 /^X\(\/\).*/{ s//\1/; q; } 17479 s/.*/./; q'` 17480 srcdir=$ac_confdir 17481 - if test ! -r "$srcdir/$ac_unique_file"; then 17482 + if test ! -r $srcdir/$ac_unique_file; then 17483 srcdir=.. 17484 fi 17485 else 17486 ac_srcdir_defaulted=no 17487 fi 17488 -if test ! -r "$srcdir/$ac_unique_file"; then 17489 +if test ! -r $srcdir/$ac_unique_file; then 17490 if test "$ac_srcdir_defaulted" = yes; then 17491 { echo "$as_me: error: cannot find sources ($ac_unique_file) in $ac_confdir or .." >&2 17492 { (exit 1); exit 1; }; } 17493 @@ -733,7 +733,7 @@ 17494 { (exit 1); exit 1; }; } 17495 fi 17496 fi 17497 -(cd $srcdir && test -r "./$ac_unique_file") 2>/dev/null || 17498 +(cd $srcdir && test -r ./$ac_unique_file) 2>/dev/null || 17499 { echo "$as_me: error: sources are in $srcdir, but \`cd $srcdir' does not work" >&2 17500 { (exit 1); exit 1; }; } 17501 srcdir=`echo "$srcdir" | sed 's%\([^\\/]\)[\\/]*$%\1%'` 17502 @@ -3527,7 +3527,7 @@ 17503 17504 case $ac_prog_version in 17505 '') gcc_cv_prog_makeinfo_modern=no;; 17506 - 4.[4-9]*) gcc_cv_prog_makeinfo_modern=yes;; 17507 + 4.[4-9]*|4.[1-9][0-9]*|[5-9]*|[1-9][0-9]*) gcc_cv_prog_makeinfo_modern=yes;; 17508 *) gcc_cv_prog_makeinfo_modern=no;; 17509 esac 17510 if test $gcc_cv_prog_makeinfo_modern = no; then 17511 diff -Naur gcc-4.2.2.orig/libgomp/configure.ac gcc-4.2.2/libgomp/configure.ac 17512 --- gcc-4.2.2.orig/libgomp/configure.ac 2007-02-06 13:49:55.000000000 -0500 17513 +++ gcc-4.2.2/libgomp/configure.ac 2007-11-23 04:30:22.000000000 -0500 17514 @@ -135,7 +135,7 @@ 17515 # that we can use it. 17516 ACX_CHECK_PROG_VER([MAKEINFO], [makeinfo], [--version], 17517 [GNU texinfo.* \([0-9][0-9.]*\)], 17518 - [4.[4-9]*]) 17519 + [4.[4-9]*|4.[1-9][0-9]*|[5-9]*|[1-9][0-9]*]) 17520 AM_CONDITIONAL(BUILD_INFO, test $gcc_cv_prog_makeinfo_modern = "yes") 17521 17522 15337 17523 diff -Naur gcc-4.2.2.orig/libjava/ChangeLog gcc-4.2.2/libjava/ChangeLog 15338 --- gcc-4.2.2.orig/libjava/ChangeLog 2007-10-07 1 4:20:40.000000000 -070015339 +++ gcc-4.2.2/libjava/ChangeLog 2007-10-10 1 0:51:17.000000000 -070017524 --- gcc-4.2.2.orig/libjava/ChangeLog 2007-10-07 17:20:40.000000000 -0400 17525 +++ gcc-4.2.2/libjava/ChangeLog 2007-10-10 13:51:17.000000000 -0400 15340 17526 @@ -1,3 +1,9 @@ 15341 17527 +2007-10-10 Roger Sayle <roger@eyesopen.com> … … 15349 17535 * GCC 4.2.2 released. 15350 17536 diff -Naur gcc-4.2.2.orig/libjava/java/lang/natPosixProcess.cc gcc-4.2.2/libjava/java/lang/natPosixProcess.cc 15351 --- gcc-4.2.2.orig/libjava/java/lang/natPosixProcess.cc 2007-03-2 5 23:07:13.000000000 -070015352 +++ gcc-4.2.2/libjava/java/lang/natPosixProcess.cc 2007-10-10 1 0:51:17.000000000 -070017537 --- gcc-4.2.2.orig/libjava/java/lang/natPosixProcess.cc 2007-03-26 02:07:13.000000000 -0400 17538 +++ gcc-4.2.2/libjava/java/lang/natPosixProcess.cc 2007-10-10 13:51:17.000000000 -0400 15353 17539 @@ -17,6 +17,9 @@ 15354 17540 #include <fcntl.h> … … 15362 17548 #endif 15363 17549 diff -Naur gcc-4.2.2.orig/libstdc++-v3/ChangeLog gcc-4.2.2/libstdc++-v3/ChangeLog 15364 --- gcc-4.2.2.orig/libstdc++-v3/ChangeLog 2007-10-07 14:20:04.000000000 -0700 15365 +++ gcc-4.2.2/libstdc++-v3/ChangeLog 2007-10-20 03:03:10.000000000 -0700 15366 @@ -1,3 +1,50 @@ 17550 --- gcc-4.2.2.orig/libstdc++-v3/ChangeLog 2007-10-07 17:20:04.000000000 -0400 17551 +++ gcc-4.2.2/libstdc++-v3/ChangeLog 2007-12-17 18:56:23.000000000 -0500 17552 @@ -1,3 +1,78 @@ 17553 +2007-12-17 Jonathan Wakely <jwakely.gcc@gmail.com> 17554 + 17555 + * include/bits/locale_facets.tcc (has_facet, use_facet): Simplify 17556 + RTTI checks. 17557 + 17558 +2007-12-17 Benjamin Kosnik <bkoz@redhat.com> 17559 + 17560 + * testsuite/22_locale/global_templates/ 17561 + standard_facet_hierarchies.cc: Fix for generic locale model. 17562 + 17563 +2007-12-14 Benjamin Kosnik <bkoz@redhat.com> 17564 + 17565 + PR libstdc++/30127 17566 + PR libstdc++/34449 17567 + * include/bits/locale_classes.h (use_facet): Check facet hierarchy. 17568 + (has_facet): Same. 17569 + * testsuite/22_locale/global_templates/user_facet_hierarchies.cc: New. 17570 + * testsuite/22_locale/global_templates/ 17571 + standard_facet_hierarchies.cc: New. 17572 + 17573 +2007-11-26 Paolo Carlini <pcarlini@suse.de> 17574 + 17575 + * include/bits/locale_facets.tcc (num_put<>::_M_insert_int): When 17576 + ios_base::showpos and the type is signed and the value is zero, 17577 + prepend +. 17578 + * testsuite/22_locale/num_put/put/char/12.cc: New. 17579 + * testsuite/22_locale/num_put/put/wchar_t/12.cc: Likewise. 17580 + 15367 17581 +2007-10-20 Paolo Carlini <pcarlini@suse.de> 15368 17582 + … … 15416 17630 * GCC 4.2.2 released. 15417 17631 diff -Naur gcc-4.2.2.orig/libstdc++-v3/docs/html/Makefile gcc-4.2.2/libstdc++-v3/docs/html/Makefile 15418 --- gcc-4.2.2.orig/libstdc++-v3/docs/html/Makefile 2003-08-04 18:20:15.000000000 -070015419 +++ gcc-4.2.2/libstdc++-v3/docs/html/Makefile 2007-10-14 1 1:28:35.000000000 -070017632 --- gcc-4.2.2.orig/libstdc++-v3/docs/html/Makefile 2003-08-04 21:20:15.000000000 -0400 17633 +++ gcc-4.2.2/libstdc++-v3/docs/html/Makefile 2007-10-14 14:28:35.000000000 -0400 15420 17634 @@ -31,10 +31,6 @@ 15421 17635 17_intro/porting.html: 17_intro/porting.texi … … 15430 17644 15431 17645 diff -Naur gcc-4.2.2.orig/libstdc++-v3/include/bits/allocator.h gcc-4.2.2/libstdc++-v3/include/bits/allocator.h 15432 --- gcc-4.2.2.orig/libstdc++-v3/include/bits/allocator.h 2006-01-18 0 6:30:16.000000000 -080015433 +++ gcc-4.2.2/libstdc++-v3/include/bits/allocator.h 2007-10-18 1 0:58:13.000000000 -070017646 --- gcc-4.2.2.orig/libstdc++-v3/include/bits/allocator.h 2006-01-18 09:30:16.000000000 -0500 17647 +++ gcc-4.2.2/libstdc++-v3/include/bits/allocator.h 2007-10-18 13:58:13.000000000 -0400 15434 17648 @@ -115,11 +115,21 @@ 15435 17649 operator==(const allocator<_T1>&, const allocator<_T2>&) … … 15455 17669 // NB: This syntax is a GNU extension. 15456 17670 diff -Naur gcc-4.2.2.orig/libstdc++-v3/include/bits/basic_string.h gcc-4.2.2/libstdc++-v3/include/bits/basic_string.h 15457 --- gcc-4.2.2.orig/libstdc++-v3/include/bits/basic_string.h 2007-04-12 1 6:06:37.000000000 -070015458 +++ gcc-4.2.2/libstdc++-v3/include/bits/basic_string.h 2007-10-14 1 1:22:22.000000000 -070017671 --- gcc-4.2.2.orig/libstdc++-v3/include/bits/basic_string.h 2007-04-12 19:06:37.000000000 -0400 17672 +++ gcc-4.2.2/libstdc++-v3/include/bits/basic_string.h 2007-10-14 14:22:22.000000000 -0400 15459 17673 @@ -1672,7 +1672,7 @@ 15460 17674 /** … … 15542 17756 * @a c within this string. If found, returns the index where it was 15543 17757 diff -Naur gcc-4.2.2.orig/libstdc++-v3/include/bits/fstream.tcc gcc-4.2.2/libstdc++-v3/include/bits/fstream.tcc 15544 --- gcc-4.2.2.orig/libstdc++-v3/include/bits/fstream.tcc 2006-03-22 07:13:46.000000000 -080015545 +++ gcc-4.2.2/libstdc++-v3/include/bits/fstream.tcc 2007-10-14 1 1:22:22.000000000 -070017758 --- gcc-4.2.2.orig/libstdc++-v3/include/bits/fstream.tcc 2006-03-22 10:13:46.000000000 -0500 17759 +++ gcc-4.2.2/libstdc++-v3/include/bits/fstream.tcc 2007-10-14 14:22:22.000000000 -0400 15546 17760 @@ -194,7 +194,7 @@ 15547 17761 const bool __testin = _M_mode & ios_base::in; … … 15553 17767 // fileops happen... 15554 17768 _M_destroy_pback(); 17769 diff -Naur gcc-4.2.2.orig/libstdc++-v3/include/bits/locale_facets.tcc gcc-4.2.2/libstdc++-v3/include/bits/locale_facets.tcc 17770 --- gcc-4.2.2.orig/libstdc++-v3/include/bits/locale_facets.tcc 2006-10-17 12:43:47.000000000 -0400 17771 +++ gcc-4.2.2/libstdc++-v3/include/bits/locale_facets.tcc 2007-12-17 18:56:23.000000000 -0500 17772 @@ -90,7 +90,8 @@ 17773 { 17774 const size_t __i = _Facet::id._M_id(); 17775 const locale::facet** __facets = __loc._M_impl->_M_facets; 17776 - return (__i < __loc._M_impl->_M_facets_size && __facets[__i]); 17777 + return __i < __loc._M_impl->_M_facets_size 17778 + && dynamic_cast<const _Facet*>(__facets[__i]) != NULL; 17779 } 17780 17781 /** 17782 @@ -112,11 +113,12 @@ 17783 { 17784 const size_t __i = _Facet::id._M_id(); 17785 const locale::facet** __facets = __loc._M_impl->_M_facets; 17786 - if (!(__i < __loc._M_impl->_M_facets_size && __facets[__i])) 17787 + if (__i >= __loc._M_impl->_M_facets_size || __facets[__i] == NULL) 17788 __throw_bad_cast(); 17789 - return static_cast<const _Facet&>(*__facets[__i]); 17790 + return dynamic_cast<const _Facet&>(*__facets[__i]); 17791 } 17792 17793 + 17794 // Routine to access a cache for the facet. If the cache didn't 17795 // exist before, it gets constructed on the fly. 17796 template<typename _Facet> 17797 @@ -1015,13 +1017,13 @@ 17798 if (__builtin_expect(__dec, true)) 17799 { 17800 // Decimal. 17801 - if (__v > 0) 17802 + if (__v >= 0) 17803 { 17804 if (__flags & ios_base::showpos 17805 && numeric_limits<_ValueT>::is_signed) 17806 *--__cs = __lit[__num_base::_S_oplus], ++__len; 17807 } 17808 - else if (__v) 17809 + else 17810 *--__cs = __lit[__num_base::_S_ominus], ++__len; 17811 } 17812 else if (__flags & ios_base::showbase && __v) 15555 17813 diff -Naur gcc-4.2.2.orig/libstdc++-v3/include/ext/atomicity.h gcc-4.2.2/libstdc++-v3/include/ext/atomicity.h 15556 --- gcc-4.2.2.orig/libstdc++-v3/include/ext/atomicity.h 2006-09-14 0 2:48:15.000000000 -070015557 +++ gcc-4.2.2/libstdc++-v3/include/ext/atomicity.h 2007-10-14 1 1:22:22.000000000 -070017814 --- gcc-4.2.2.orig/libstdc++-v3/include/ext/atomicity.h 2006-09-14 05:48:15.000000000 -0400 17815 +++ gcc-4.2.2/libstdc++-v3/include/ext/atomicity.h 2007-10-14 14:22:22.000000000 -0400 15558 17816 @@ -42,7 +42,7 @@ 15559 17817 _GLIBCXX_BEGIN_NAMESPACE(__gnu_cxx) … … 15566 17824 #ifdef _GLIBCXX_ATOMIC_BUILTINS 15567 17825 diff -Naur gcc-4.2.2.orig/libstdc++-v3/include/ext/codecvt_specializations.h gcc-4.2.2/libstdc++-v3/include/ext/codecvt_specializations.h 15568 --- gcc-4.2.2.orig/libstdc++-v3/include/ext/codecvt_specializations.h 2006-07-30 09:42:39.000000000 -070015569 +++ gcc-4.2.2/libstdc++-v3/include/ext/codecvt_specializations.h 2007-10-11 08:23:11.000000000 -070017826 --- gcc-4.2.2.orig/libstdc++-v3/include/ext/codecvt_specializations.h 2006-07-30 12:42:39.000000000 -0400 17827 +++ gcc-4.2.2/libstdc++-v3/include/ext/codecvt_specializations.h 2007-10-11 11:23:11.000000000 -0400 15570 17828 @@ -128,7 +128,7 @@ 15571 17829 bool … … 15596 17854 iconv_close(_M_in_desc); 15597 17855 diff -Naur gcc-4.2.2.orig/libstdc++-v3/include/ext/concurrence.h gcc-4.2.2/libstdc++-v3/include/ext/concurrence.h 15598 --- gcc-4.2.2.orig/libstdc++-v3/include/ext/concurrence.h 2006-11-13 0 1:18:24.000000000 -080015599 +++ gcc-4.2.2/libstdc++-v3/include/ext/concurrence.h 2007-10-14 1 1:22:22.000000000 -070017856 --- gcc-4.2.2.orig/libstdc++-v3/include/ext/concurrence.h 2006-11-13 04:18:24.000000000 -0500 17857 +++ gcc-4.2.2/libstdc++-v3/include/ext/concurrence.h 2007-10-14 14:22:22.000000000 -0400 15600 17858 @@ -46,7 +46,7 @@ 15601 17859 // Available locking policies: … … 15608 17866 15609 17867 diff -Naur gcc-4.2.2.orig/libstdc++-v3/include/ext/vstring.h gcc-4.2.2/libstdc++-v3/include/ext/vstring.h 15610 --- gcc-4.2.2.orig/libstdc++-v3/include/ext/vstring.h 2007-04-12 1 6:06:37.000000000 -070015611 +++ gcc-4.2.2/libstdc++-v3/include/ext/vstring.h 2007-10-14 1 1:22:22.000000000 -070017868 --- gcc-4.2.2.orig/libstdc++-v3/include/ext/vstring.h 2007-04-12 19:06:37.000000000 -0400 17869 +++ gcc-4.2.2/libstdc++-v3/include/ext/vstring.h 2007-10-14 14:22:22.000000000 -0400 15612 17870 @@ -1407,7 +1407,7 @@ 15613 17871 /** … … 15695 17953 * @a c within this string. If found, returns the index where it was 15696 17954 diff -Naur gcc-4.2.2.orig/libstdc++-v3/include/tr1/boost_shared_ptr.h gcc-4.2.2/libstdc++-v3/include/tr1/boost_shared_ptr.h 15697 --- gcc-4.2.2.orig/libstdc++-v3/include/tr1/boost_shared_ptr.h 2006-12-07 0 1:33:51.000000000 -080015698 +++ gcc-4.2.2/libstdc++-v3/include/tr1/boost_shared_ptr.h 2007-10-14 1 0:40:50.000000000 -070017955 --- gcc-4.2.2.orig/libstdc++-v3/include/tr1/boost_shared_ptr.h 2006-12-07 04:33:51.000000000 -0500 17956 +++ gcc-4.2.2/libstdc++-v3/include/tr1/boost_shared_ptr.h 2007-10-14 13:40:50.000000000 -0400 15699 17957 @@ -857,7 +857,7 @@ 15700 17958 // Q: How can we get here? … … 15707 17965 #else 15708 17966 diff -Naur gcc-4.2.2.orig/libstdc++-v3/include/tr1/random gcc-4.2.2/libstdc++-v3/include/tr1/random 15709 --- gcc-4.2.2.orig/libstdc++-v3/include/tr1/random 2007-08-28 0 1:48:54.000000000 -070015710 +++ gcc-4.2.2/libstdc++-v3/include/tr1/random 2007-10-20 0 3:02:34.000000000 -070017967 --- gcc-4.2.2.orig/libstdc++-v3/include/tr1/random 2007-08-28 04:48:54.000000000 -0400 17968 +++ gcc-4.2.2/libstdc++-v3/include/tr1/random 2007-10-20 06:02:34.000000000 -0400 15711 17969 @@ -1618,10 +1618,15 @@ 15712 17970 result_type … … 15728 17986 template<typename _UniformRandomNumberGenerator> 15729 17987 diff -Naur gcc-4.2.2.orig/libstdc++-v3/src/valarray-inst.cc gcc-4.2.2/libstdc++-v3/src/valarray-inst.cc 15730 --- gcc-4.2.2.orig/libstdc++-v3/src/valarray-inst.cc 2005-12-18 1 6:56:05.000000000 -080015731 +++ gcc-4.2.2/libstdc++-v3/src/valarray-inst.cc 2007-10-14 1 1:22:22.000000000 -070017988 --- gcc-4.2.2.orig/libstdc++-v3/src/valarray-inst.cc 2005-12-18 19:56:05.000000000 -0500 17989 +++ gcc-4.2.2/libstdc++-v3/src/valarray-inst.cc 2007-10-14 14:22:22.000000000 -0400 15732 17990 @@ -68,7 +68,7 @@ 15733 17991 __gslice_to_index(size_t __o, const valarray<size_t>& __l, … … 15740 17998 // Get a buffer to hold current multi-index as we go through 15741 17999 diff -Naur gcc-4.2.2.orig/libstdc++-v3/testsuite/20_util/memory/allocator/33807.cc gcc-4.2.2/libstdc++-v3/testsuite/20_util/memory/allocator/33807.cc 15742 --- gcc-4.2.2.orig/libstdc++-v3/testsuite/20_util/memory/allocator/33807.cc 1969-12-31 1 6:00:00.000000000 -080015743 +++ gcc-4.2.2/libstdc++-v3/testsuite/20_util/memory/allocator/33807.cc 2007-10-18 1 0:58:13.000000000 -070018000 --- gcc-4.2.2.orig/libstdc++-v3/testsuite/20_util/memory/allocator/33807.cc 1969-12-31 19:00:00.000000000 -0500 18001 +++ gcc-4.2.2/libstdc++-v3/testsuite/20_util/memory/allocator/33807.cc 2007-10-18 13:58:13.000000000 -0400 15744 18002 @@ -0,0 +1,33 @@ 15745 18003 +// { dg-do compile } … … 15776 18034 + l1 = l2; 15777 18035 +} 18036 diff -Naur gcc-4.2.2.orig/libstdc++-v3/testsuite/22_locale/global_templates/standard_facet_hierarchies.cc gcc-4.2.2/libstdc++-v3/testsuite/22_locale/global_templates/standard_facet_hierarchies.cc 18037 --- gcc-4.2.2.orig/libstdc++-v3/testsuite/22_locale/global_templates/standard_facet_hierarchies.cc 1969-12-31 19:00:00.000000000 -0500 18038 +++ gcc-4.2.2/libstdc++-v3/testsuite/22_locale/global_templates/standard_facet_hierarchies.cc 2007-12-17 15:30:47.000000000 -0500 18039 @@ -0,0 +1,84 @@ 18040 +// Copyright (C) 2007 Free Software Foundation 18041 +// 18042 +// This file is part of the GNU ISO C++ Library. This library is free 18043 +// software; you can redistribute it and/or modify it under the 18044 +// terms of the GNU General Public License as published by the 18045 +// Free Software Foundation; either version 2, or (at your option) 18046 +// any later version. 18047 + 18048 +// This library is distributed in the hope that it will be useful, 18049 +// but WITHOUT ANY WARRANTY; without even the implied warranty of 18050 +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18051 +// GNU General Public License for more details. 18052 + 18053 +// You should have received a copy of the GNU General Public License along 18054 +// with this library; see the file COPYING. If not, write to the Free 18055 +// Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, 18056 +// USA. 18057 + 18058 +#include <string> 18059 +#include <locale> 18060 +#include <cassert> 18061 +#include <testsuite_hooks.h> 18062 + 18063 +// Based on Langer Kreft "Standard C++ IOStreams and Locales" p 316-318 18064 +// PR libstdc++/30127 18065 +// PR libstdc++/34449 18066 +int main() 18067 +{ 18068 + bool test __attribute__((unused)) = true; 18069 + 18070 + using std::locale; 18071 + using std::has_facet; 18072 + using std::use_facet; 18073 + typedef std::ctype<char> base_facet; 18074 + typedef std::ctype_byname<char> derived_facet; 18075 + 18076 + locale loc_c = locale::classic(); 18077 + locale loc_base = loc_c; 18078 + locale loc_derived(loc_c, new derived_facet("C")); 18079 + 18080 + bool b; 18081 + 18082 + // Standard base facet. 18083 + VERIFY( has_facet<base_facet>(loc_c) ); 18084 + VERIFY( has_facet<base_facet>(loc_base) ); 18085 + VERIFY( has_facet<base_facet>(loc_derived) ); 18086 + 18087 + // Standard derived facet. 18088 + VERIFY( !has_facet<derived_facet>(loc_c) ); 18089 + VERIFY( !has_facet<derived_facet>(loc_base) ); 18090 + VERIFY( has_facet<derived_facet>(loc_derived) ); 18091 + 18092 + 18093 + // 1 18094 + try 18095 + { 18096 + if (has_facet<derived_facet>(loc_base)) 18097 + { 18098 + use_facet<derived_facet>(loc_base).widen('k'); 18099 + VERIFY( true ); 18100 + } 18101 + } 18102 + catch (...) 18103 + { 18104 + // Expect no exception. 18105 + VERIFY( true ); 18106 + } 18107 + 18108 + // 2 18109 + try 18110 + { 18111 + if (has_facet<base_facet>(loc_derived)) 18112 + use_facet<base_facet>(loc_derived).widen('k'); 18113 + else 18114 + VERIFY( true ); 18115 + } 18116 + catch (...) 18117 + { 18118 + // Expect no exception. 18119 + VERIFY( true ); 18120 + } 18121 + 18122 + return 0; 18123 +} 18124 diff -Naur gcc-4.2.2.orig/libstdc++-v3/testsuite/22_locale/global_templates/user_facet_hierarchies.cc gcc-4.2.2/libstdc++-v3/testsuite/22_locale/global_templates/user_facet_hierarchies.cc 18125 --- gcc-4.2.2.orig/libstdc++-v3/testsuite/22_locale/global_templates/user_facet_hierarchies.cc 1969-12-31 19:00:00.000000000 -0500 18126 +++ gcc-4.2.2/libstdc++-v3/testsuite/22_locale/global_templates/user_facet_hierarchies.cc 2007-12-14 16:27:09.000000000 -0500 18127 @@ -0,0 +1,108 @@ 18128 +// Copyright (C) 2007 Free Software Foundation 18129 +// 18130 +// This file is part of the GNU ISO C++ Library. This library is free 18131 +// software; you can redistribute it and/or modify it under the 18132 +// terms of the GNU General Public License as published by the 18133 +// Free Software Foundation; either version 2, or (at your option) 18134 +// any later version. 18135 + 18136 +// This library is distributed in the hope that it will be useful, 18137 +// but WITHOUT ANY WARRANTY; without even the implied warranty of 18138 +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18139 +// GNU General Public License for more details. 18140 + 18141 +// You should have received a copy of the GNU General Public License along 18142 +// with this library; see the file COPYING. If not, write to the Free 18143 +// Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, 18144 +// USA. 18145 + 18146 +#include <string> 18147 +#include <locale> 18148 +#include <cassert> 18149 +#include <testsuite_hooks.h> 18150 + 18151 +// Based on Langer Kreft "Standard C++ IOStreams and Locales" p 316-318 18152 +struct base_facet: public std::locale::facet 18153 +{ 18154 + virtual std::string msg() const 18155 + { return "base class"; } 18156 + 18157 + static std::locale::id id; 18158 +}; 18159 + 18160 +std::locale::id base_facet::id; 18161 + 18162 + 18163 +struct derived_facet: public base_facet 18164 +{ 18165 + virtual std::string msg() const 18166 + { return "derived class"; } 18167 + 18168 + virtual std::string msg_repeater() const 18169 + { return "derived class derived class"; } 18170 + 18171 +}; 18172 + 18173 +// PR libstdc++/30127 18174 +// PR libstdc++/34449 18175 +int main() 18176 +{ 18177 + bool test __attribute__((unused)) = true; 18178 + 18179 + using std::locale; 18180 + using std::has_facet; 18181 + using std::use_facet; 18182 + 18183 + locale loc_c = locale::classic(); 18184 + locale loc_base(loc_c, new base_facet); 18185 + locale loc_derived(loc_c, new derived_facet); 18186 + 18187 + bool b; 18188 + 18189 + // Standard facets. 18190 + VERIFY( has_facet<std::ctype<char> >(loc_c) ); 18191 + VERIFY( has_facet<std::ctype<char> >(loc_base) ); 18192 + VERIFY( has_facet<std::ctype<char> >(loc_derived) ); 18193 + 18194 + // User defined base facet. 18195 + VERIFY( !has_facet<base_facet>(loc_c) ); 18196 + VERIFY( has_facet<base_facet>(loc_base) ); 18197 + VERIFY( has_facet<base_facet>(loc_derived) ); 18198 + 18199 + // User defined derived facet. 18200 + VERIFY( !has_facet<derived_facet>(loc_c) ); 18201 + VERIFY( !has_facet<derived_facet>(loc_base) ); 18202 + VERIFY( has_facet<derived_facet>(loc_derived) ); 18203 + 18204 + 18205 + // 1 18206 + try 18207 + { 18208 + if (has_facet<derived_facet>(loc_base)) 18209 + { 18210 + use_facet<derived_facet>(loc_base).msg_repeater(); 18211 + VERIFY( false ); 18212 + } 18213 + } 18214 + catch (...) 18215 + { 18216 + // Expect no exception. 18217 + VERIFY( true ); 18218 + } 18219 + 18220 + // 2 18221 + try 18222 + { 18223 + if (has_facet<base_facet>(loc_derived)) 18224 + use_facet<base_facet>(loc_derived).msg(); 18225 + else 18226 + VERIFY( true ); 18227 + } 18228 + catch (...) 18229 + { 18230 + // Expect no exception. 18231 + VERIFY( true ); 18232 + } 18233 + 18234 + return 0; 18235 +} 18236 diff -Naur gcc-4.2.2.orig/libstdc++-v3/testsuite/22_locale/num_put/put/char/12.cc gcc-4.2.2/libstdc++-v3/testsuite/22_locale/num_put/put/char/12.cc 18237 --- gcc-4.2.2.orig/libstdc++-v3/testsuite/22_locale/num_put/put/char/12.cc 1969-12-31 19:00:00.000000000 -0500 18238 +++ gcc-4.2.2/libstdc++-v3/testsuite/22_locale/num_put/put/char/12.cc 2007-11-26 20:59:59.000000000 -0500 18239 @@ -0,0 +1,64 @@ 18240 +// 2007-11-26 Paolo Carlini <pcarlini@suse.de> 18241 + 18242 +// Copyright (C) 2007 Free Software Foundation 18243 +// 18244 +// This file is part of the GNU ISO C++ Library. This library is free 18245 +// software; you can redistribute it and/or modify it under the 18246 +// terms of the GNU General Public License as published by the 18247 +// Free Software Foundation; either version 2, or (at your option) 18248 +// any later version. 18249 + 18250 +// This library is distributed in the hope that it will be useful, 18251 +// but WITHOUT ANY WARRANTY; without even the implied warranty of 18252 +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18253 +// GNU General Public License for more details. 18254 + 18255 +// You should have received a copy of the GNU General Public License along 18256 +// with this library; see the file COPYING. If not, write to the Free 18257 +// Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, 18258 +// USA. 18259 + 18260 +// 22.2.2.2.1 num_put members 18261 + 18262 +#include <locale> 18263 +#include <sstream> 18264 +#include <testsuite_hooks.h> 18265 + 18266 +// http://gcc.gnu.org/ml/libstdc++/2007-11/msg00074.html 18267 +void test01() 18268 +{ 18269 + using namespace std; 18270 + bool test __attribute__((unused)) = true; 18271 + 18272 + ostringstream oss1, oss2, oss3; 18273 + const num_put<char>& np1 = use_facet<num_put<char> >(oss1.getloc()); 18274 + const num_put<char>& np2 = use_facet<num_put<char> >(oss2.getloc()); 18275 + const num_put<char>& np3 = use_facet<num_put<char> >(oss3.getloc()); 18276 + 18277 + string result1, result2, result3; 18278 + 18279 + long int li1 = 0; 18280 + long int li2 = 5; 18281 + double d1 = 0.0; 18282 + 18283 + oss1.setf(ios_base::showpos); 18284 + np1.put(oss1.rdbuf(), oss1, '*', li1); 18285 + result1 = oss1.str(); 18286 + VERIFY( result1 == "+0" ); 18287 + 18288 + oss2.setf(ios_base::showpos); 18289 + np2.put(oss2.rdbuf(), oss2, '*', li2); 18290 + result2 = oss2.str(); 18291 + VERIFY( result2 == "+5" ); 18292 + 18293 + oss3.setf(ios_base::showpos); 18294 + np3.put(oss3.rdbuf(), oss3, '*', d1); 18295 + result3 = oss3.str(); 18296 + VERIFY( result3 == "+0" ); 18297 +} 18298 + 18299 +int main() 18300 +{ 18301 + test01(); 18302 + return 0; 18303 +} 18304 diff -Naur gcc-4.2.2.orig/libstdc++-v3/testsuite/22_locale/num_put/put/wchar_t/12.cc gcc-4.2.2/libstdc++-v3/testsuite/22_locale/num_put/put/wchar_t/12.cc 18305 --- gcc-4.2.2.orig/libstdc++-v3/testsuite/22_locale/num_put/put/wchar_t/12.cc 1969-12-31 19:00:00.000000000 -0500 18306 +++ gcc-4.2.2/libstdc++-v3/testsuite/22_locale/num_put/put/wchar_t/12.cc 2007-11-26 20:59:59.000000000 -0500 18307 @@ -0,0 +1,64 @@ 18308 +// 2007-11-26 Paolo Carlini <pcarlini@suse.de> 18309 + 18310 +// Copyright (C) 2007 Free Software Foundation 18311 +// 18312 +// This file is part of the GNU ISO C++ Library. This library is free 18313 +// software; you can redistribute it and/or modify it under the 18314 +// terms of the GNU General Public License as published by the 18315 +// Free Software Foundation; either version 2, or (at your option) 18316 +// any later version. 18317 + 18318 +// This library is distributed in the hope that it will be useful, 18319 +// but WITHOUT ANY WARRANTY; without even the implied warranty of 18320 +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18321 +// GNU General Public License for more details. 18322 + 18323 +// You should have received a copy of the GNU General Public License along 18324 +// with this library; see the file COPYING. If not, write to the Free 18325 +// Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, 18326 +// USA. 18327 + 18328 +// 22.2.2.2.1 num_put members 18329 + 18330 +#include <locale> 18331 +#include <sstream> 18332 +#include <testsuite_hooks.h> 18333 + 18334 +// http://gcc.gnu.org/ml/libstdc++/2007-11/msg00074.html 18335 +void test01() 18336 +{ 18337 + using namespace std; 18338 + bool test __attribute__((unused)) = true; 18339 + 18340 + wostringstream oss1, oss2, oss3; 18341 + const num_put<wchar_t>& np1 = use_facet<num_put<wchar_t> >(oss1.getloc()); 18342 + const num_put<wchar_t>& np2 = use_facet<num_put<wchar_t> >(oss2.getloc()); 18343 + const num_put<wchar_t>& np3 = use_facet<num_put<wchar_t> >(oss3.getloc()); 18344 + 18345 + wstring result1, result2, result3; 18346 + 18347 + long int li1 = 0; 18348 + long int li2 = 5; 18349 + double d1 = 0.0; 18350 + 18351 + oss1.setf(ios_base::showpos); 18352 + np1.put(oss1.rdbuf(), oss1, L'*', li1); 18353 + result1 = oss1.str(); 18354 + VERIFY( result1 == L"+0" ); 18355 + 18356 + oss2.setf(ios_base::showpos); 18357 + np2.put(oss2.rdbuf(), oss2, L'*', li2); 18358 + result2 = oss2.str(); 18359 + VERIFY( result2 == L"+5" ); 18360 + 18361 + oss3.setf(ios_base::showpos); 18362 + np3.put(oss3.rdbuf(), oss3, L'*', d1); 18363 + result3 = oss3.str(); 18364 + VERIFY( result3 == L"+0" ); 18365 +} 18366 + 18367 +int main() 18368 +{ 18369 + test01(); 18370 + return 0; 18371 +} 15778 18372 diff -Naur gcc-4.2.2.orig/libstdc++-v3/testsuite/tr1/2_general_utilities/memory/shared_ptr/explicit_instantiation/2.cc gcc-4.2.2/libstdc++-v3/testsuite/tr1/2_general_utilities/memory/shared_ptr/explicit_instantiation/2.cc 15779 --- gcc-4.2.2.orig/libstdc++-v3/testsuite/tr1/2_general_utilities/memory/shared_ptr/explicit_instantiation/2.cc 1969-12-31 1 6:00:00.000000000 -080015780 +++ gcc-4.2.2/libstdc++-v3/testsuite/tr1/2_general_utilities/memory/shared_ptr/explicit_instantiation/2.cc 2007-10-14 1 0:40:50.000000000 -070018373 --- gcc-4.2.2.orig/libstdc++-v3/testsuite/tr1/2_general_utilities/memory/shared_ptr/explicit_instantiation/2.cc 1969-12-31 19:00:00.000000000 -0500 18374 +++ gcc-4.2.2/libstdc++-v3/testsuite/tr1/2_general_utilities/memory/shared_ptr/explicit_instantiation/2.cc 2007-10-14 13:40:50.000000000 -0400 15781 18375 @@ -0,0 +1,34 @@ 15782 18376 +// Copyright (C) 2007 Free Software Foundation … … 15815 18409 +template class __shared_ptr<IncompleteClass, _S_single>; 15816 18410 diff -Naur gcc-4.2.2.orig/libstdc++-v3/testsuite/tr1/2_general_utilities/memory/weak_ptr/explicit_instantiation/2.cc gcc-4.2.2/libstdc++-v3/testsuite/tr1/2_general_utilities/memory/weak_ptr/explicit_instantiation/2.cc 15817 --- gcc-4.2.2.orig/libstdc++-v3/testsuite/tr1/2_general_utilities/memory/weak_ptr/explicit_instantiation/2.cc 1969-12-31 1 6:00:00.000000000 -080015818 +++ gcc-4.2.2/libstdc++-v3/testsuite/tr1/2_general_utilities/memory/weak_ptr/explicit_instantiation/2.cc 2007-10-14 1 0:40:50.000000000 -070018411 --- gcc-4.2.2.orig/libstdc++-v3/testsuite/tr1/2_general_utilities/memory/weak_ptr/explicit_instantiation/2.cc 1969-12-31 19:00:00.000000000 -0500 18412 +++ gcc-4.2.2/libstdc++-v3/testsuite/tr1/2_general_utilities/memory/weak_ptr/explicit_instantiation/2.cc 2007-10-14 13:40:50.000000000 -0400 15819 18413 @@ -0,0 +1,35 @@ 15820 18414 +// Copyright (C) 2007 Free Software Foundation
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