[50361f7] | 1 | Submitted By: Jim Gifford (patches at jg555 dot com) |
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| 2 | Date: 2007-02-24 |
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| 3 | Initial Package Version: 2.6.20.1 |
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| 4 | Origin: Linux-MIPS Mailing List |
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| 5 | Upstream Status: Not Applied |
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| 6 | Description: These are patches that have not been accepted by |
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| 7 | Linux-MIPS. |
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| 8 | |
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| 9 | 1 - Cobalt ide fixes |
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| 10 | 2 - Updates to Support N32 only builds |
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| 11 | |
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| 12 | diff -Naur linux-2.6.20.1/arch/mips/kernel/Makefile linux-mips-2.6.20.1/arch/mips/kernel/Makefile |
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| 13 | --- linux-2.6.20.1/arch/mips/kernel/Makefile 2007-02-24 10:29:49.000000000 -0800 |
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| 14 | +++ linux-mips-2.6.20.1/arch/mips/kernel/Makefile 2007-02-24 10:27:47.000000000 -0800 |
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| 15 | @@ -56,7 +56,7 @@ |
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| 16 | obj-$(CONFIG_64BIT) += scall64-64.o |
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| 17 | obj-$(CONFIG_BINFMT_IRIX) += binfmt_irix.o |
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| 18 | obj-$(CONFIG_MIPS32_COMPAT) += linux32.o ptrace32.o signal32.o |
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| 19 | -obj-$(CONFIG_MIPS32_N32) += binfmt_elfn32.o scall64-n32.o signal_n32.o |
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| 20 | +obj-$(CONFIG_MIPS32_N32) += binfmt_elfn32.o scall64-n32.o ptrace32.o signal_n32.o |
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| 21 | obj-$(CONFIG_MIPS32_O32) += binfmt_elfo32.o scall64-o32.o |
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| 22 | |
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| 23 | obj-$(CONFIG_KGDB) += gdb-low.o gdb-stub.o |
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| 24 | diff -Naur linux-2.6.20.1/include/asm-mips/mach-cobalt/ide.h linux-mips-2.6.20.1/include/asm-mips/mach-cobalt/ide.h |
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| 25 | --- linux-2.6.20.1/include/asm-mips/mach-cobalt/ide.h 1969-12-31 16:00:00.000000000 -0800 |
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| 26 | +++ linux-mips-2.6.20.1/include/asm-mips/mach-cobalt/ide.h 2007-02-24 10:26:19.000000000 -0800 |
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| 27 | @@ -0,0 +1,83 @@ |
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| 28 | + |
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| 29 | +/* |
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| 30 | + * PIO "in" transfers can cause D-cache lines to be allocated |
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| 31 | + * to the data being read. If the target is the page cache then |
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| 32 | + * the kernel can create a user space mapping of the same page |
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| 33 | + * without flushing it from the D-cache. This has large potential |
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| 34 | + * to create cache aliases. The Cobalts seem to trigger this |
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| 35 | + * problem easily. |
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| 36 | + * |
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| 37 | + * MIPs doesn't have a flush_dcache_range() so we roll |
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| 38 | + * our own. |
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| 39 | + * |
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| 40 | + * -- pdh |
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| 41 | + */ |
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| 42 | + |
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| 43 | +#define MAX_HWIFS 2 |
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| 44 | + |
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| 45 | +#include <asm/r4kcache.h> |
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| 46 | + |
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| 47 | +static inline void __flush_dcache(void) |
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| 48 | +{ |
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| 49 | + unsigned long dc_size, dc_line, addr, end; |
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| 50 | + |
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| 51 | + dc_size = current_cpu_data.dcache.ways << current_cpu_data.dcache.waybit; |
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| 52 | + dc_line = current_cpu_data.dcache.linesz; |
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| 53 | + |
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| 54 | + addr = CKSEG0; |
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| 55 | + end = addr + dc_size; |
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| 56 | + |
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| 57 | + for (; addr < end; addr += dc_line) |
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| 58 | + flush_dcache_line_indexed(addr); |
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| 59 | +} |
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| 60 | + |
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| 61 | +static inline void __flush_dcache_range(unsigned long start, unsigned long end) |
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| 62 | +{ |
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| 63 | + unsigned long dc_size, dc_line, addr; |
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| 64 | + |
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| 65 | + dc_size = current_cpu_data.dcache.ways << current_cpu_data.dcache.waybit; |
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| 66 | + dc_line = current_cpu_data.dcache.linesz; |
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| 67 | + |
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| 68 | + addr = start & ~(dc_line - 1); |
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| 69 | + end += dc_line - 1; |
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| 70 | + |
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| 71 | + if (end - addr < dc_size) |
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| 72 | + for (; addr < end; addr += dc_line) |
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| 73 | + flush_dcache_line(addr); |
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| 74 | + else |
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| 75 | + __flush_dcache(); |
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| 76 | +} |
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| 77 | + |
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| 78 | +static inline void __ide_insw(unsigned long port, void *addr, unsigned int count) |
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| 79 | +{ |
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| 80 | + insw(port, addr, count); |
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| 81 | + |
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| 82 | + __flush_dcache_range((unsigned long) addr, (unsigned long) addr + count * 2); |
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| 83 | +} |
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| 84 | + |
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| 85 | +static inline void __ide_insl(unsigned long port, void *addr, unsigned int count) |
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| 86 | +{ |
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| 87 | + insl(port, addr, count); |
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| 88 | + |
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| 89 | + __flush_dcache_range((unsigned long) addr, (unsigned long) addr + count * 4); |
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| 90 | +} |
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| 91 | + |
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| 92 | +static inline void __ide_mm_insw(volatile void __iomem *port, void *addr, unsigned int count) |
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| 93 | +{ |
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| 94 | + readsw(port, addr, count); |
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| 95 | + |
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| 96 | + __flush_dcache_range((unsigned long) addr, (unsigned long) addr + count * 2); |
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| 97 | +} |
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| 98 | + |
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| 99 | +static inline void __ide_mm_insl(volatile void __iomem *port, void *addr, unsigned int count) |
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| 100 | +{ |
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| 101 | + readsl(port, addr, count); |
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| 102 | + |
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| 103 | + __flush_dcache_range((unsigned long) addr, (unsigned long) addr + count * 4); |
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| 104 | +} |
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| 105 | + |
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| 106 | +#define insw __ide_insw |
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| 107 | +#define insl __ide_insl |
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| 108 | + |
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| 109 | +#define __ide_mm_outsw writesw |
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| 110 | +#define __ide_mm_outsl writesl |
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