source: patches/linux-2.6.20.1-mips_fixes-1.patch @ 50361f7

clfs-1.2clfs-2.1clfs-3.0.0-systemdclfs-3.0.0-sysvinitsystemdsysvinit
Last change on this file since 50361f7 was 50361f7, checked in by Jim Gifford <clfs@…>, 17 years ago

Updates to Linux 2.6.20.1

  • Property mode set to 100644
File size: 3.7 KB
  • .6.20.1/arch/mips/kernel/Makefile

    Submitted By: Jim Gifford (patches at jg555 dot com)
    Date: 2007-02-24
    Initial Package Version: 2.6.20.1
    Origin: Linux-MIPS Mailing List
    Upstream Status: Not Applied
    Description: These are patches that have not been accepted by
                 Linux-MIPS.
    
            1 - Cobalt ide fixes
            2 - Updates to Support N32 only builds
    
    diff -Naur linux-2.6.20.1/arch/mips/kernel/Makefile linux-mips-2.6.20.1/arch/mips/kernel/Makefile
    old new  
    5656obj-$(CONFIG_64BIT)             += scall64-64.o
    5757obj-$(CONFIG_BINFMT_IRIX)       += binfmt_irix.o
    5858obj-$(CONFIG_MIPS32_COMPAT)     += linux32.o ptrace32.o signal32.o
    59 obj-$(CONFIG_MIPS32_N32)        += binfmt_elfn32.o scall64-n32.o signal_n32.o
     59obj-$(CONFIG_MIPS32_N32)        += binfmt_elfn32.o scall64-n32.o ptrace32.o signal_n32.o
    6060obj-$(CONFIG_MIPS32_O32)        += binfmt_elfo32.o scall64-o32.o
    6161
    6262obj-$(CONFIG_KGDB)              += gdb-low.o gdb-stub.o
  • .6.20.1/include/asm-mips/mach-cobalt/ide.h

    diff -Naur linux-2.6.20.1/include/asm-mips/mach-cobalt/ide.h linux-mips-2.6.20.1/include/asm-mips/mach-cobalt/ide.h
    old new  
     1
     2/*
     3 * PIO "in" transfers can cause D-cache lines to be allocated
     4 * to the data being read. If the target is the page cache then
     5 * the kernel can create a user space mapping of the same page
     6 * without flushing it from the D-cache. This has large potential
     7 * to create cache aliases. The Cobalts seem to trigger this
     8 * problem easily.
     9 *
     10 * MIPs doesn't have a flush_dcache_range() so we roll
     11 * our own.
     12 *
     13 * -- pdh
     14 */
     15
     16#define MAX_HWIFS                      2
     17
     18#include <asm/r4kcache.h>
     19
     20static inline void __flush_dcache(void)
     21{
     22       unsigned long dc_size, dc_line, addr, end;
     23
     24       dc_size = current_cpu_data.dcache.ways << current_cpu_data.dcache.waybit;
     25       dc_line = current_cpu_data.dcache.linesz;
     26
     27       addr = CKSEG0;
     28       end = addr + dc_size;
     29
     30       for (; addr < end; addr += dc_line)
     31               flush_dcache_line_indexed(addr);
     32}
     33
     34static inline void __flush_dcache_range(unsigned long start, unsigned long end)
     35{
     36       unsigned long dc_size, dc_line, addr;
     37
     38       dc_size = current_cpu_data.dcache.ways << current_cpu_data.dcache.waybit;
     39       dc_line = current_cpu_data.dcache.linesz;
     40
     41       addr = start & ~(dc_line - 1);
     42       end += dc_line - 1;
     43
     44       if (end - addr < dc_size)
     45               for (; addr < end; addr += dc_line)
     46                       flush_dcache_line(addr);
     47       else
     48               __flush_dcache();
     49}
     50
     51static inline void __ide_insw(unsigned long port, void *addr, unsigned int count)
     52{
     53       insw(port, addr, count);
     54
     55       __flush_dcache_range((unsigned long) addr, (unsigned long) addr + count * 2);
     56}
     57
     58static inline void __ide_insl(unsigned long port, void *addr, unsigned int count)
     59{
     60       insl(port, addr, count);
     61
     62       __flush_dcache_range((unsigned long) addr, (unsigned long) addr + count * 4);
     63}
     64
     65static inline void __ide_mm_insw(volatile void __iomem *port, void *addr, unsigned int count)
     66{
     67       readsw(port, addr, count);
     68
     69       __flush_dcache_range((unsigned long) addr, (unsigned long) addr + count * 2);
     70}
     71
     72static inline void __ide_mm_insl(volatile void __iomem *port, void *addr, unsigned int count)
     73{
     74       readsl(port, addr, count);
     75
     76       __flush_dcache_range((unsigned long) addr, (unsigned long) addr + count * 4);
     77}
     78
     79#define insw                   __ide_insw
     80#define insl                   __ide_insl
     81
     82#define __ide_mm_outsw         writesw
     83#define __ide_mm_outsl         writesl
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