Changes between Initial Version and Version 1 of Ticket #1100


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Timestamp:
Apr 14, 2017, 1:01:47 PM (8 years ago)
Author:
William Harrington
Comment:

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  • Ticket #1100

    • Property Milestone → CLFS Standard 3.1.0
    • Property Summary GMP 6.1.0 → GMP 6.1.2
    • Property Version → CLFS Standard GIT

  • Ticket #1100 – Description

    initial v1  
    22
    33{{{
     4Copyright 1996, 1999-2016 Free Software Foundation, Inc.
     5
     6Verbatim copying and distribution of this entire article is permitted in any
     7medium, provided this notice is preserved.
     8
     9
     10Changes between GMP version 6.1.1 and 6.1.2
     11
     12  BUGS FIXED
     13  * Mini-GMP: Fixed a division bug, which on a machine with 64-bit
     14    unsigned long affects approximately 1 out of 2^32 divisors.
     15
     16  * Mini-GMP: Fix mpz_set_str crash on inputs with a large number of
     17    leading zeros. Also stricter input validation, rejecting inputs
     18    with no digits.
     19
     20  FEATURES
     21  * Handle more systems which require PIC code in static libraries (e.g.,
     22    "hardened" Gentoo and Debian 9).
     23
     24  * Configuration for arm (-32 and -64) has been rewritten, fixing poor
     25    code selection for many CPUs.
     26
     27  * Mini-GMP: Updated to the latest development version, including
     28    new functions mpn_com and mpn_neg.
     29
     30  SPEEDUPS
     31  * None, except for arm CPUs affected by the configuration rewrite.
     32
     33  MISC
     34  -
     35
     36Changes between GMP version 6.1.0 and 6.1.1
     37
     38  BUGS FIXED
     39  * Make Intel Broadwell configurations work on Windows.
     40
     41  FEATURES
     42  * Work around faulty cpuid on some recent Intel chips (this allows GMP to run
     43    on Skylake Pentiums).
     44
     45  * Support thumb-less ARM chips.
     46
    447Changes between GMP version 6.0.* and 6.1.0
    548
    … …  
    2265
    2366  SPEEDUPS
    24   * Speedup for Intel Broadwell and Skylake though assembly code making use of
     67  * Speedup for Intel Broadwell and Skylake through assembly code making use of
    2568    new ADX instructions.
    2669