Index: tches/linux-2.6.17-mips-1.patch
===================================================================
--- patches/linux-2.6.17-mips-1.patch	(revision cb8d2472b6ab2dd9d9ee1310646004e2212b5469)
+++ 	(revision )
@@ -1,34976 +1,0 @@
-Submitted By: Jim Gifford (patches at jg555 dot com)
-Date: 2006-06-19
-Initial Package Version: 2.6.17
-Origin: Linux-MIPS GIT and Mailling Lists
-Upstream Status: N/A
-Description: Merges Linux-MIPS and Kernel.org Tree's
-
-diff -Naur linux-2.6.17.orig/arch/mips/au1000/common/au1xxx_irqmap.c linux-2.6.17/arch/mips/au1000/common/au1xxx_irqmap.c
---- linux-2.6.17.orig/arch/mips/au1000/common/au1xxx_irqmap.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/au1000/common/au1xxx_irqmap.c	2006-06-19 18:16:12.000000000 -0700
-@@ -55,7 +55,7 @@
-  * Careful if you change match 2 request!
-  * The interrupt handler is called directly from the low level dispatch code.
-  */
--au1xxx_irq_map_t au1xxx_ic0_map[] = {
-+au1xxx_irq_map_t __initdata au1xxx_ic0_map[] = {
- 
- #if defined(CONFIG_SOC_AU1000)
- 	{ AU1000_UART0_INT, INTC_INT_HIGH_LEVEL, 0},
-@@ -220,5 +220,5 @@
- 
- };
- 
--int au1xxx_ic0_nr_irqs = sizeof(au1xxx_ic0_map)/sizeof(au1xxx_irq_map_t);
-+int __initdata au1xxx_ic0_nr_irqs = ARRAY_SIZE(au1xxx_ic0_map);
- 
-diff -Naur linux-2.6.17.orig/arch/mips/au1000/common/pci.c linux-2.6.17/arch/mips/au1000/common/pci.c
---- linux-2.6.17.orig/arch/mips/au1000/common/pci.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/au1000/common/pci.c	2006-06-19 18:16:12.000000000 -0700
-@@ -40,17 +40,17 @@
- 
- /* TBD */
- static struct resource pci_io_resource = {
--	"pci IO space",
--	(u32)PCI_IO_START,
--	(u32)PCI_IO_END,
--	IORESOURCE_IO
-+	.start	= PCI_IO_START,
-+	.end	= PCI_IO_END,
-+	.name	= "PCI IO space",
-+	.flags	= IORESOURCE_IO
- };
- 
- static struct resource pci_mem_resource = {
--	"pci memory space",
--	(u32)PCI_MEM_START,
--	(u32)PCI_MEM_END,
--	IORESOURCE_MEM
-+	.start	= PCI_MEM_START,
-+	.end	= PCI_MEM_END,
-+	.name	= "PCI memory space",
-+	.flags	= IORESOURCE_MEM
- };
- 
- extern struct pci_ops au1x_pci_ops;
-diff -Naur linux-2.6.17.orig/arch/mips/au1000/common/setup.c linux-2.6.17/arch/mips/au1000/common/setup.c
---- linux-2.6.17.orig/arch/mips/au1000/common/setup.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/au1000/common/setup.c	2006-06-19 18:16:12.000000000 -0700
-@@ -49,17 +49,13 @@
- extern void au1000_restart(char *);
- extern void au1000_halt(void);
- extern void au1000_power_off(void);
--extern struct resource ioport_resource;
--extern struct resource iomem_resource;
--extern void (*board_time_init)(void);
- extern void au1x_time_init(void);
--extern void (*board_timer_setup)(struct irqaction *irq);
- extern void au1x_timer_setup(struct irqaction *irq);
- extern void au1xxx_time_init(void);
- extern void au1xxx_timer_setup(struct irqaction *irq);
- extern void set_cpuspec(void);
- 
--void __init plat_setup(void)
-+void __init plat_mem_setup(void)
- {
- 	struct	cpu_spec *sp;
- 	char *argptr;
-diff -Naur linux-2.6.17.orig/arch/mips/au1000/common/time.c linux-2.6.17/arch/mips/au1000/common/time.c
---- linux-2.6.17.orig/arch/mips/au1000/common/time.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/au1000/common/time.c	2006-06-19 18:16:12.000000000 -0700
-@@ -50,10 +50,6 @@
- #include <linux/mc146818rtc.h>
- #include <linux/timex.h>
- 
--extern void do_softirq(void);
--extern volatile unsigned long wall_jiffies;
--unsigned long missed_heart_beats = 0;
--
- static unsigned long r4k_offset; /* Amount to increment compare reg each time */
- static unsigned long r4k_cur;    /* What counter should be at next timer irq */
- int	no_au1xxx_32khz;
-@@ -388,10 +384,9 @@
- }
- #endif
- 
--void au1xxx_timer_setup(struct irqaction *irq)
-+void __init au1xxx_timer_setup(struct irqaction *irq)
- {
--        unsigned int est_freq;
--	extern unsigned long (*do_gettimeoffset)(void);
-+	unsigned int est_freq;
- 
- 	printk("calculating r4koff... ");
- 	r4k_offset = cal_r4koff();
-diff -Naur linux-2.6.17.orig/arch/mips/au1000/csb250/irqmap.c linux-2.6.17/arch/mips/au1000/csb250/irqmap.c
---- linux-2.6.17.orig/arch/mips/au1000/csb250/irqmap.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/au1000/csb250/irqmap.c	2006-06-19 18:16:12.000000000 -0700
-@@ -47,7 +47,7 @@
- #include <asm/system.h>
- #include <asm/au1000.h>
- 
--au1xxx_irq_map_t au1xxx_irq_map[] = {
-+au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
- 
- 	{ AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0},
- 	{ AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 },
-@@ -57,4 +57,4 @@
- 	{ AU1500_GPIO_207, INTC_INT_LOW_LEVEL, 0 },
- };
- 
--int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t);
-+int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
-diff -Naur linux-2.6.17.orig/arch/mips/au1000/db1x00/irqmap.c linux-2.6.17/arch/mips/au1000/db1x00/irqmap.c
---- linux-2.6.17.orig/arch/mips/au1000/db1x00/irqmap.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/au1000/db1x00/irqmap.c	2006-06-19 18:16:12.000000000 -0700
-@@ -80,7 +80,7 @@
- #endif
- 
- 
--au1xxx_irq_map_t au1xxx_irq_map[] = {
-+au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
- 
- #ifndef CONFIG_MIPS_MIRAGE
- #ifdef CONFIG_MIPS_DB1550
-@@ -101,4 +101,4 @@
- 
- };
- 
--int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t);
-+int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
-diff -Naur linux-2.6.17.orig/arch/mips/au1000/hydrogen3/irqmap.c linux-2.6.17/arch/mips/au1000/hydrogen3/irqmap.c
---- linux-2.6.17.orig/arch/mips/au1000/hydrogen3/irqmap.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/au1000/hydrogen3/irqmap.c	2006-06-19 18:16:12.000000000 -0700
-@@ -47,10 +47,10 @@
- #include <asm/system.h>
- #include <asm/au1000.h>
- 
--au1xxx_irq_map_t au1xxx_irq_map[] = {
-+au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
- 
- 	/* { AU1500_GPIO_205, INTC_INT_LOW_LEVEL, 0 }, */
- 	{ AU1000_GPIO_21, INTC_INT_LOW_LEVEL, 0 },
- };
- 
--int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t);
-+int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
-diff -Naur linux-2.6.17.orig/arch/mips/au1000/mtx-1/irqmap.c linux-2.6.17/arch/mips/au1000/mtx-1/irqmap.c
---- linux-2.6.17.orig/arch/mips/au1000/mtx-1/irqmap.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/au1000/mtx-1/irqmap.c	2006-06-19 18:16:12.000000000 -0700
-@@ -58,7 +58,7 @@
-  [7] = { -1, INTD, INTC, INTX, INTX},   /* IDSEL 07 - AdapterD-Slot1 (bottom) */
- };
- 
--au1xxx_irq_map_t au1xxx_irq_map[] = {
-+au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
-        { AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0},
-        { AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 },
-        { AU1500_GPIO_202, INTC_INT_LOW_LEVEL, 0 },
-@@ -66,4 +66,4 @@
-        { AU1500_GPIO_205, INTC_INT_LOW_LEVEL, 0 },
- };
- 
--int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t);
-+int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
-diff -Naur linux-2.6.17.orig/arch/mips/au1000/pb1000/irqmap.c linux-2.6.17/arch/mips/au1000/pb1000/irqmap.c
---- linux-2.6.17.orig/arch/mips/au1000/pb1000/irqmap.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/au1000/pb1000/irqmap.c	2006-06-19 18:16:12.000000000 -0700
-@@ -47,8 +47,8 @@
- #include <asm/system.h>
- #include <asm/mach-au1x00/au1000.h>
- 
--au1xxx_irq_map_t au1xxx_irq_map[] = {
-+au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
- 	{ AU1000_GPIO_15, INTC_INT_LOW_LEVEL, 0 },
- };
- 
--int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t);
-+int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
-diff -Naur linux-2.6.17.orig/arch/mips/au1000/pb1100/irqmap.c linux-2.6.17/arch/mips/au1000/pb1100/irqmap.c
---- linux-2.6.17.orig/arch/mips/au1000/pb1100/irqmap.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/au1000/pb1100/irqmap.c	2006-06-19 18:16:12.000000000 -0700
-@@ -47,11 +47,11 @@
- #include <asm/system.h>
- #include <asm/mach-au1x00/au1000.h>
- 
--au1xxx_irq_map_t au1xxx_irq_map[] = {
-+au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
- 	{ AU1000_GPIO_9, INTC_INT_LOW_LEVEL, 0 }, // PCMCIA Card Fully_Interted#
- 	{ AU1000_GPIO_10, INTC_INT_LOW_LEVEL, 0 }, // PCMCIA Card STSCHG#
- 	{ AU1000_GPIO_11, INTC_INT_LOW_LEVEL, 0 }, // PCMCIA Card IRQ#
- 	{ AU1000_GPIO_13, INTC_INT_LOW_LEVEL, 0 }, // DC_IRQ#
- };
- 
--int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t);
-+int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
-diff -Naur linux-2.6.17.orig/arch/mips/au1000/pb1200/irqmap.c linux-2.6.17/arch/mips/au1000/pb1200/irqmap.c
---- linux-2.6.17.orig/arch/mips/au1000/pb1200/irqmap.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/au1000/pb1200/irqmap.c	2006-06-19 18:16:12.000000000 -0700
-@@ -55,11 +55,11 @@
- #define PB1200_INT_END DB1200_INT_END
- #endif
- 
--au1xxx_irq_map_t au1xxx_irq_map[] = {
-+au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
- 	{ AU1000_GPIO_7, INTC_INT_LOW_LEVEL, 0 }, // This is exteranl interrupt cascade
- };
- 
--int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t);
-+int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
- 
- /*
-  *	Support for External interrupts on the PbAu1200 Development platform.
-diff -Naur linux-2.6.17.orig/arch/mips/au1000/pb1500/irqmap.c linux-2.6.17/arch/mips/au1000/pb1500/irqmap.c
---- linux-2.6.17.orig/arch/mips/au1000/pb1500/irqmap.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/au1000/pb1500/irqmap.c	2006-06-19 18:16:12.000000000 -0700
-@@ -52,7 +52,7 @@
-  [13] = { -1, INTA, INTB, INTC, INTD},   /* IDSEL 13 - PCI slot */
- };
- 
--au1xxx_irq_map_t au1xxx_irq_map[] = {
-+au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
- 	{ AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0},
- 	{ AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 },
- 	{ AU1500_GPIO_202, INTC_INT_LOW_LEVEL, 0 },
-@@ -60,4 +60,4 @@
- 	{ AU1500_GPIO_205, INTC_INT_LOW_LEVEL, 0 },
- };
- 
--int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t);
-+int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
-diff -Naur linux-2.6.17.orig/arch/mips/au1000/pb1550/irqmap.c linux-2.6.17/arch/mips/au1000/pb1550/irqmap.c
---- linux-2.6.17.orig/arch/mips/au1000/pb1550/irqmap.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/au1000/pb1550/irqmap.c	2006-06-19 18:16:12.000000000 -0700
-@@ -52,9 +52,9 @@
-  [13] =	{ -1, INTA, INTB, INTC, INTD},   /* IDSEL 13 - PCI slot 1 (right) */
- };
- 
--au1xxx_irq_map_t au1xxx_irq_map[] = {
-+au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
- 	{ AU1000_GPIO_0, INTC_INT_LOW_LEVEL, 0 },
- 	{ AU1000_GPIO_1, INTC_INT_LOW_LEVEL, 0 },
- };
- 
--int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t);
-+int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
-diff -Naur linux-2.6.17.orig/arch/mips/au1000/xxs1500/irqmap.c linux-2.6.17/arch/mips/au1000/xxs1500/irqmap.c
---- linux-2.6.17.orig/arch/mips/au1000/xxs1500/irqmap.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/au1000/xxs1500/irqmap.c	2006-06-19 18:16:12.000000000 -0700
-@@ -47,7 +47,7 @@
- #include <asm/system.h>
- #include <asm/au1000.h>
- 
--au1xxx_irq_map_t au1xxx_irq_map[] = {
-+au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
- 	{ AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0},
- 	{ AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 },
- 	{ AU1500_GPIO_202, INTC_INT_LOW_LEVEL, 0 },
-@@ -63,4 +63,4 @@
- 	{ AU1000_GPIO_5, INTC_INT_LOW_LEVEL, 0 },
- };
- 
--int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t);
-+int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
-diff -Naur linux-2.6.17.orig/arch/mips/basler/excite/excite_dbg_io.c linux-2.6.17/arch/mips/basler/excite/excite_dbg_io.c
---- linux-2.6.17.orig/arch/mips/basler/excite/excite_dbg_io.c	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/arch/mips/basler/excite/excite_dbg_io.c	2006-06-19 18:16:12.000000000 -0700
-@@ -0,0 +1,122 @@
-+/*
-+ *  Copyright (C) 2004 by Basler Vision Technologies AG
-+ *  Author: Thomas Koeller <thomas.koeller@baslerweb.com>
-+ *
-+ *  This program is free software; you can redistribute it and/or modify
-+ *  it under the terms of the GNU General Public License as published by
-+ *  the Free Software Foundation; either version 2 of the License, or
-+ *  (at your option) any later version.
-+ *
-+ *  This program is distributed in the hope that it will be useful,
-+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ *  GNU General Public License for more details.
-+ *
-+ *  You should have received a copy of the GNU General Public License
-+ *  along with this program; if not, write to the Free Software
-+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-+ */
-+
-+#include <linux/config.h>
-+#include <linux/linkage.h>
-+#include <linux/init.h>
-+#include <linux/kernel.h>
-+#include <asm/gdb-stub.h>
-+#include <asm/rm9k-ocd.h>
-+#include <excite.h>
-+
-+#if defined(CONFIG_SERIAL_8250) && CONFIG_SERIAL_8250_NR_UARTS > 1
-+#error Debug port used by serial driver
-+#endif
-+
-+#define UART_CLK		25000000
-+#define BASE_BAUD		(UART_CLK / 16)
-+#define REGISTER_BASE_0		0x0208UL
-+#define REGISTER_BASE_1		0x0238UL
-+
-+#define REGISTER_BASE_DBG	REGISTER_BASE_1
-+
-+#define CPRR	0x0004
-+#define UACFG	0x0200
-+#define UAINTS	0x0204
-+#define UARBR	(REGISTER_BASE_DBG + 0x0000)
-+#define UATHR	(REGISTER_BASE_DBG + 0x0004)
-+#define UADLL	(REGISTER_BASE_DBG + 0x0008)
-+#define UAIER	(REGISTER_BASE_DBG + 0x000c)
-+#define UADLH	(REGISTER_BASE_DBG + 0x0010)
-+#define UAIIR	(REGISTER_BASE_DBG + 0x0014)
-+#define UAFCR	(REGISTER_BASE_DBG + 0x0018)
-+#define UALCR	(REGISTER_BASE_DBG + 0x001c)
-+#define UAMCR	(REGISTER_BASE_DBG + 0x0020)
-+#define UALSR	(REGISTER_BASE_DBG + 0x0024)
-+#define UAMSR	(REGISTER_BASE_DBG + 0x0028)
-+#define UASCR	(REGISTER_BASE_DBG + 0x002c)
-+
-+#define	PARITY_NONE	0
-+#define	PARITY_ODD	0x08
-+#define	PARITY_EVEN	0x18
-+#define	PARITY_MARK	0x28
-+#define	PARITY_SPACE	0x38
-+
-+#define	DATA_5BIT	0x0
-+#define	DATA_6BIT	0x1
-+#define	DATA_7BIT	0x2
-+#define	DATA_8BIT	0x3
-+
-+#define	STOP_1BIT	0x0
-+#define	STOP_2BIT	0x4
-+
-+#define BAUD_DBG	57600
-+#define	PARITY_DBG	PARITY_NONE
-+#define	DATA_DBG	DATA_8BIT
-+#define	STOP_DBG	STOP_1BIT
-+
-+/* Initialize the serial port for KGDB debugging */
-+void __init excite_kgdb_init(void)
-+{
-+	const u32 divisor = BASE_BAUD / BAUD_DBG;
-+
-+	/* Take the UART out of reset */
-+	titan_writel(0x00ff1cff, CPRR);
-+	titan_writel(0x00000000, UACFG);
-+	titan_writel(0x00000002, UACFG);
-+
-+	titan_writel(0x0, UALCR);
-+	titan_writel(0x0, UAIER);
-+
-+	/* Disable FIFOs */
-+	titan_writel(0x00, UAFCR);
-+
-+	titan_writel(0x80, UALCR);
-+	titan_writel(divisor & 0xff, UADLL);
-+	titan_writel((divisor & 0xff00) >> 8, UADLH);
-+	titan_writel(0x0, UALCR);
-+
-+	titan_writel(DATA_DBG | PARITY_DBG | STOP_DBG, UALCR);
-+
-+	/* Enable receiver interrupt */
-+	titan_readl(UARBR);
-+	titan_writel(0x1, UAIER);
-+}
-+
-+int getDebugChar(void)
-+{
-+	while (!(titan_readl(UALSR) & 0x1));
-+	return titan_readl(UARBR);
-+}
-+
-+int putDebugChar(int data)
-+{
-+	while (!(titan_readl(UALSR) & 0x20));
-+	titan_writel(data, UATHR);
-+	return 1;
-+}
-+
-+/* KGDB interrupt handler */
-+asmlinkage void excite_kgdb_inthdl(struct pt_regs *regs)
-+{
-+	if (unlikely(
-+		((titan_readl(UAIIR) & 0x7) == 4)
-+		&& ((titan_readl(UARBR) & 0xff) == 0x3)))
-+			set_async_breakpoint(&regs->cp0_epc);
-+}
-diff -Naur linux-2.6.17.orig/arch/mips/basler/excite/excite_device.c linux-2.6.17/arch/mips/basler/excite/excite_device.c
---- linux-2.6.17.orig/arch/mips/basler/excite/excite_device.c	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/arch/mips/basler/excite/excite_device.c	2006-06-19 18:16:12.000000000 -0700
-@@ -0,0 +1,404 @@
-+/*
-+ *  Copyright (C) 2004 by Basler Vision Technologies AG
-+ *  Author: Thomas Koeller <thomas.koeller@baslerweb.com>
-+ *
-+ *  This program is free software; you can redistribute it and/or modify
-+ *  it under the terms of the GNU General Public License as published by
-+ *  the Free Software Foundation; either version 2 of the License, or
-+ *  (at your option) any later version.
-+ *
-+ *  This program is distributed in the hope that it will be useful,
-+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ *  GNU General Public License for more details.
-+ *
-+ *  You should have received a copy of the GNU General Public License
-+ *  along with this program; if not, write to the Free Software
-+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-+ */
-+
-+#include <linux/config.h>
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/platform_device.h>
-+#include <linux/ioport.h>
-+#include <linux/err.h>
-+#include <linux/jiffies.h>
-+#include <linux/sched.h>
-+#include <asm/types.h>
-+#include <asm/rm9k-ocd.h>
-+
-+#include <excite.h>
-+#include <rm9k_eth.h>
-+#include <rm9k_wdt.h>
-+#include <rm9k_xicap.h>
-+#include <excite_nandflash.h>
-+
-+#include "excite_iodev.h"
-+
-+#define RM9K_GE_UNIT	0
-+#define XICAP_UNIT	0
-+#define NAND_UNIT	0
-+
-+#define DLL_TIMEOUT	3		/* seconds */
-+
-+
-+#define RINIT(__start__, __end__, __name__, __parent__) {	\
-+	.name	= __name__ "_0",				\
-+	.start	= (__start__),					\
-+	.end	= (__end__),					\
-+	.flags	= 0,						\
-+	.parent	= (__parent__)					\
-+}
-+
-+#define RINIT_IRQ(__irq__, __name__) {	\
-+	.name	= __name__ "_0",	\
-+	.start	= (__irq__),		\
-+	.end	= (__irq__),		\
-+	.flags	= IORESOURCE_IRQ,	\
-+	.parent	= NULL			\
-+}
-+
-+
-+
-+enum {
-+	slice_xicap,
-+	slice_eth
-+};
-+
-+
-+
-+static struct resource
-+	excite_ctr_resource = {
-+		.name		= "GPI counters",
-+		.start		= 0,
-+		.end		= 5,
-+		.flags		= 0,
-+		.parent		= NULL,
-+		.sibling	= NULL,
-+		.child		= NULL
-+	},
-+	excite_gpislice_resource = {
-+		.name		= "GPI slices",
-+		.start		= 0,
-+		.end		= 1,
-+		.flags		= 0,
-+		.parent		= NULL,
-+		.sibling	= NULL,
-+		.child		= NULL
-+	},
-+	excite_mdio_channel_resource = {
-+		.name		= "MDIO channels",
-+		.start		= 0,
-+		.end		= 1,
-+		.flags		= 0,
-+		.parent		= NULL,
-+		.sibling	= NULL,
-+		.child		= NULL
-+	},
-+	excite_fifomem_resource = {
-+		.name		= "FIFO memory",
-+		.start		= 0,
-+		.end		= 767,
-+		.flags		= 0,
-+		.parent		= NULL,
-+		.sibling	= NULL,
-+		.child		= NULL
-+	},
-+	excite_scram_resource = {
-+		.name		= "Scratch RAM",
-+		.start		= EXCITE_PHYS_SCRAM,
-+		.end		= EXCITE_PHYS_SCRAM + EXCITE_SIZE_SCRAM - 1,
-+		.flags		= IORESOURCE_MEM,
-+		.parent		= NULL,
-+		.sibling	= NULL,
-+		.child		= NULL
-+	},
-+	excite_fpga_resource = {
-+		.name		= "System FPGA",
-+		.start		= EXCITE_PHYS_FPGA,
-+		.end		= EXCITE_PHYS_FPGA + EXCITE_SIZE_FPGA - 1,
-+		.flags		= IORESOURCE_MEM,
-+		.parent		= NULL,
-+		.sibling	= NULL,
-+		.child		= NULL
-+	},
-+	excite_nand_resource = {
-+		.name		= "NAND flash control",
-+		.start		= EXCITE_PHYS_NAND,
-+		.end		= EXCITE_PHYS_NAND + EXCITE_SIZE_NAND - 1,
-+		.flags		= IORESOURCE_MEM,
-+		.parent		= NULL,
-+		.sibling	= NULL,
-+		.child		= NULL
-+	},
-+	excite_titan_resource = {
-+		.name		= "TITAN registers",
-+		.start		= EXCITE_PHYS_TITAN,
-+		.end		= EXCITE_PHYS_TITAN + EXCITE_SIZE_TITAN - 1,
-+		.flags		= IORESOURCE_MEM,
-+		.parent		= NULL,
-+		.sibling	= NULL,
-+		.child		= NULL
-+	};
-+
-+
-+
-+static void adjust_resources(struct resource *res, unsigned int n)
-+{
-+	struct resource *p;
-+	const unsigned long mask = IORESOURCE_IO | IORESOURCE_MEM
-+				   | IORESOURCE_IRQ | IORESOURCE_DMA;
-+
-+	for (p = res; p < res + n; p++) {
-+		const struct resource * const parent = p->parent;
-+		if (parent) {
-+			p->start += parent->start;
-+			p->end   += parent->start;
-+			p->flags =  parent->flags & mask;
-+		}
-+	}
-+}
-+
-+
-+
-+#if defined(CONFIG_EXCITE_FCAP_GPI) || defined(CONFIG_EXCITE_FCAP_GPI_MODULE)
-+static struct resource xicap_rsrc[] = {
-+	RINIT(0x4840, 0x486f, XICAP_RESOURCE_FIFO_RX, &excite_titan_resource),
-+	RINIT(0x4940, 0x494b, XICAP_RESOURCE_FIFO_TX, &excite_titan_resource),
-+	RINIT(0x5040, 0x5127, XICAP_RESOURCE_XDMA, &excite_titan_resource),
-+	RINIT(0x1000, 0x112f, XICAP_RESOURCE_PKTPROC, &excite_titan_resource),
-+	RINIT(0x1100, 0x110f, XICAP_RESOURCE_PKT_STREAM, &excite_fpga_resource),
-+	RINIT(0x0800, 0x0bff, XICAP_RESOURCE_DMADESC, &excite_scram_resource),
-+	RINIT(slice_xicap, slice_xicap, XICAP_RESOURCE_GPI_SLICE, &excite_gpislice_resource),
-+	RINIT(0x0100, 0x02ff, XICAP_RESOURCE_FIFO_BLK, &excite_fifomem_resource),
-+	RINIT_IRQ(TITAN_IRQ,  XICAP_RESOURCE_IRQ)
-+};
-+
-+static struct platform_device xicap_pdev = {
-+	.name		= XICAP_NAME,
-+	.id		= XICAP_UNIT,
-+	.num_resources	= ARRAY_SIZE(xicap_rsrc),
-+	.resource	= xicap_rsrc
-+};
-+
-+/*
-+ * Create a platform device for the GPI port that receives the
-+ * image data from the embedded camera.
-+ */
-+static int __init xicap_devinit(void)
-+{
-+	unsigned long tend;
-+	u32 reg;
-+	int retval;
-+
-+	adjust_resources(xicap_rsrc, ARRAY_SIZE(xicap_rsrc));
-+
-+	/* Power up the slice and configure it. */
-+	reg = titan_readl(CPTC1R);
-+	reg &= ~(0x11100 << slice_xicap);
-+	titan_writel(reg, CPTC1R);
-+
-+	/* Enable slice & DLL. */
-+	reg= titan_readl(CPRR);
-+	reg &= ~(0x00030003 << (slice_xicap * 2));
-+	titan_writel(reg, CPRR);
-+
-+	/* Wait for DLLs to lock */
-+	tend = jiffies + DLL_TIMEOUT * HZ;
-+	while (time_before(jiffies, tend)) {
-+		if (!(~titan_readl(CPDSR) & (0x1 << (slice_xicap * 4))))
-+			break;
-+		yield();
-+	}
-+
-+	if (~titan_readl(CPDSR) & (0x1 << (slice_xicap * 4))) {
-+		printk(KERN_ERR "%s: DLL not locked after %u seconds\n",
-+		       xicap_pdev.name, DLL_TIMEOUT);
-+		retval = -ETIME;
-+	} else {
-+		/* Register platform device */
-+		retval = platform_device_register(&xicap_pdev);
-+	}
-+
-+	return retval;
-+}
-+
-+device_initcall(xicap_devinit);
-+#endif /* defined(CONFIG_EXCITE_FCAP_GPI) || defined(CONFIG_EXCITE_FCAP_GPI_MODULE) */
-+
-+
-+
-+#if defined(CONFIG_WDT_RM9K_GPI) || defined(CONFIG_WDT_RM9K_GPI_MODULE)
-+static struct resource wdt_rsrc[] = {
-+	RINIT(0, 0, WDT_RESOURCE_COUNTER, &excite_ctr_resource),
-+	RINIT(0x0084, 0x008f, WDT_RESOURCE_REGS, &excite_titan_resource),
-+	RINIT_IRQ(TITAN_IRQ,  WDT_RESOURCE_IRQ)
-+};
-+
-+static struct platform_device wdt_pdev = {
-+	.name		= WDT_NAME,
-+	.id		= -1,
-+	.num_resources	= ARRAY_SIZE(wdt_rsrc),
-+	.resource	= wdt_rsrc
-+};
-+
-+/*
-+ * Create a platform device for the GPI port that receives the
-+ * image data from the embedded camera.
-+ */
-+static int __init wdt_devinit(void)
-+{
-+	adjust_resources(wdt_rsrc, ARRAY_SIZE(wdt_rsrc));
-+	return platform_device_register(&wdt_pdev);
-+}
-+
-+device_initcall(wdt_devinit);
-+#endif /* defined(CONFIG_WDT_RM9K_GPI) || defined(CONFIG_WDT_RM9K_GPI_MODULE) */
-+
-+
-+
-+static struct resource excite_nandflash_rsrc[] = {
-+ 	RINIT(0x2000, 0x201f, EXCITE_NANDFLASH_RESOURCE_REGS,  &excite_nand_resource)
-+};
-+
-+static struct platform_device excite_nandflash_pdev = {
-+	.name		= "excite_nand",
-+	.id		= NAND_UNIT,
-+	.num_resources	= ARRAY_SIZE(excite_nandflash_rsrc),
-+	.resource	= excite_nandflash_rsrc
-+};
-+
-+/*
-+ * Create a platform device for the access to the nand-flash
-+ * port
-+ */
-+static int __init excite_nandflash_devinit(void)
-+{
-+	adjust_resources(excite_nandflash_rsrc, ARRAY_SIZE(excite_nandflash_rsrc));
-+
-+        /* nothing to be done here */
-+
-+        /* Register platform device */
-+	return platform_device_register(&excite_nandflash_pdev);
-+}
-+
-+device_initcall(excite_nandflash_devinit);
-+
-+
-+
-+static struct resource iodev_rsrc[] = {
-+	RINIT_IRQ(FPGA1_IRQ,  IODEV_RESOURCE_IRQ)
-+};
-+
-+static struct platform_device io_pdev = {
-+	.name		= IODEV_NAME,
-+	.id		= -1,
-+	.num_resources	= ARRAY_SIZE(iodev_rsrc),
-+	.resource	= iodev_rsrc
-+};
-+
-+/*
-+ * Create a platform device for the external I/O ports.
-+ */
-+static int __init io_devinit(void)
-+{
-+	adjust_resources(iodev_rsrc, ARRAY_SIZE(iodev_rsrc));
-+	return platform_device_register(&io_pdev);
-+}
-+
-+device_initcall(io_devinit);
-+
-+
-+
-+
-+#if defined(CONFIG_RM9K_GE) || defined(CONFIG_RM9K_GE_MODULE)
-+static struct resource rm9k_ge_rsrc[] = {
-+	RINIT(0x2200, 0x27ff, RM9K_GE_RESOURCE_MAC, &excite_titan_resource),
-+	RINIT(0x1800, 0x1fff, RM9K_GE_RESOURCE_MSTAT, &excite_titan_resource),
-+	RINIT(0x2000, 0x212f, RM9K_GE_RESOURCE_PKTPROC, &excite_titan_resource),
-+	RINIT(0x5140, 0x5227, RM9K_GE_RESOURCE_XDMA, &excite_titan_resource),
-+	RINIT(0x4870, 0x489f, RM9K_GE_RESOURCE_FIFO_RX, &excite_titan_resource),
-+	RINIT(0x494c, 0x4957, RM9K_GE_RESOURCE_FIFO_TX, &excite_titan_resource),
-+	RINIT(0x0000, 0x007f, RM9K_GE_RESOURCE_FIFOMEM_RX, &excite_fifomem_resource),
-+	RINIT(0x0080, 0x00ff, RM9K_GE_RESOURCE_FIFOMEM_TX, &excite_fifomem_resource),
-+	RINIT(0x0180, 0x019f, RM9K_GE_RESOURCE_PHY, &excite_titan_resource),
-+	RINIT(0x0000, 0x03ff, RM9K_GE_RESOURCE_DMADESC_RX, &excite_scram_resource),
-+	RINIT(0x0400, 0x07ff, RM9K_GE_RESOURCE_DMADESC_TX, &excite_scram_resource),
-+	RINIT(slice_eth, slice_eth, RM9K_GE_RESOURCE_GPI_SLICE, &excite_gpislice_resource),
-+	RINIT(0, 0, RM9K_GE_RESOURCE_MDIO_CHANNEL, &excite_mdio_channel_resource),
-+	RINIT_IRQ(TITAN_IRQ,  RM9K_GE_RESOURCE_IRQ_MAIN),
-+	RINIT_IRQ(PHY_IRQ, RM9K_GE_RESOURCE_IRQ_PHY)
-+};
-+
-+static struct platform_device rm9k_ge_pdev = {
-+	.name		= RM9K_GE_NAME,
-+	.id		= RM9K_GE_UNIT,
-+	.num_resources	= ARRAY_SIZE(rm9k_ge_rsrc),
-+	.resource	= rm9k_ge_rsrc
-+};
-+
-+
-+
-+/*
-+ * Create a platform device for the Ethernet port.
-+ */
-+static int __init rm9k_ge_devinit(void)
-+{
-+	u32 reg;
-+
-+	adjust_resources(rm9k_ge_rsrc, ARRAY_SIZE(rm9k_ge_rsrc));
-+
-+	/* Power up the slice and configure it. */
-+	reg = titan_readl(CPTC1R);
-+	reg &= ~(0x11000 << slice_eth);
-+	reg |= 0x100 << slice_eth;
-+	titan_writel(reg, CPTC1R);
-+
-+	/* Take the MAC out of reset, reset the DLLs. */
-+	reg = titan_readl(CPRR);
-+	reg &= ~(0x00030000 << (slice_eth * 2));
-+	reg |= 0x3 << (slice_eth * 2);
-+	titan_writel(reg, CPRR);
-+
-+	return platform_device_register(&rm9k_ge_pdev);
-+}
-+
-+device_initcall(rm9k_ge_devinit);
-+#endif /* defined(CONFIG_RM9K_GE) || defined(CONFIG_RM9K_GE_MODULE) */
-+
-+
-+
-+static int __init excite_setup_devs(void)
-+{
-+	int res;
-+	u32 reg;
-+
-+	/* Enable xdma and fifo interrupts */
-+	reg = titan_readl(0x0050);
-+	titan_writel(reg | 0x18000000, 0x0050);
-+
-+	res = request_resource(&iomem_resource, &excite_titan_resource);
-+	if (res)
-+		return res;
-+	res = request_resource(&iomem_resource, &excite_scram_resource);
-+	if (res)
-+		return res;
-+	res = request_resource(&iomem_resource, &excite_fpga_resource);
-+	if (res)
-+		return res;
-+	res = request_resource(&iomem_resource, &excite_nand_resource);
-+	if (res)
-+		return res;
-+	excite_fpga_resource.flags = excite_fpga_resource.parent->flags &
-+				   ( IORESOURCE_IO | IORESOURCE_MEM
-+				   | IORESOURCE_IRQ | IORESOURCE_DMA);
-+	excite_nand_resource.flags = excite_nand_resource.parent->flags &
-+				   ( IORESOURCE_IO | IORESOURCE_MEM
-+				   | IORESOURCE_IRQ | IORESOURCE_DMA);
-+
-+	return 0;
-+}
-+
-+arch_initcall(excite_setup_devs);
-+
-diff -Naur linux-2.6.17.orig/arch/mips/basler/excite/excite_flashtest.c linux-2.6.17/arch/mips/basler/excite/excite_flashtest.c
---- linux-2.6.17.orig/arch/mips/basler/excite/excite_flashtest.c	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/arch/mips/basler/excite/excite_flashtest.c	2006-06-19 18:16:12.000000000 -0700
-@@ -0,0 +1,294 @@
-+/*
-+*  Copyright (C) 2005 by Basler Vision Technologies AG
-+*  Author: Thies Moeller <thies.moeller@baslerweb.com>
-+*
-+*  This program is free software; you can redistribute it and/or modify
-+*  it under the terms of the GNU General Public License as published by
-+*  the Free Software Foundation; either version 2 of the License, or
-+*  (at your option) any later version.
-+*
-+*  This program is distributed in the hope that it will be useful,
-+*  but WITHOUT ANY WARRANTY; without even the implied warranty of
-+*  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+*  GNU General Public License for more details.
-+*
-+*  You should have received a copy of the GNU General Public License
-+*  along with this program; if not, write to the Free Software
-+*  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-+*/
-+
-+#include <linux/module.h>
-+#include <linux/types.h>
-+#include <linux/init.h>
-+#include <linux/kernel.h>
-+#include <linux/string.h>
-+#include <linux/ioport.h>
-+#include <linux/device.h>
-+#include <linux/delay.h>
-+#include <linux/err.h>
-+#include <linux/kernel.h>
-+
-+#include <excite.h>
-+
-+#include <asm/io.h>
-+
-+#include <linux/mtd/mtd.h>
-+#include <linux/mtd/nand.h>
-+#include <linux/mtd/nand_ecc.h>
-+#include <linux/mtd/partitions.h>
-+#include <asm/rm9k-ocd.h> // for ocd_write
-+#include <linux/workqueue.h> // for queue
-+
-+#include "excite_nandflash.h"
-+#include "nandflash.h"
-+
-+#define PFX "excite flashtest: "
-+typedef void __iomem *io_reg_t;
-+
-+#define io_readb(__a__)		__raw_readb((__a__))
-+#define io_writeb(__v__, __a__)	__raw_writeb((__v__), (__a__))
-+
-+
-+
-+static inline const struct resource *excite_nandflash_get_resource(
-+	struct platform_device *d, unsigned long flags, const char *basename)
-+{
-+	const char fmt[] = "%s_%u";
-+	char buf[80];
-+
-+	if (unlikely(snprintf(buf, sizeof buf, fmt, basename, d->id) >= sizeof buf))
-+		return NULL;
-+
-+	return platform_get_resource_byname(d, flags, buf);
-+}
-+
-+static inline io_reg_t
-+excite_nandflash_map_regs(struct platform_device *d, const char *basename)
-+{
-+	void *result = NULL;
-+	const struct resource *const r =
-+	    excite_nandflash_get_resource(d, IORESOURCE_MEM, basename);
-+	if (r)
-+	   result = ioremap_nocache(r->start, r->end + 1 - r->start);
-+	return result;
-+}
-+
-+/* controller and mtd information */
-+
-+struct excite_nandflash_drvdata {
-+	struct mtd_info board_mtd;
-+	struct nand_chip board_chip;
-+	io_reg_t regs;
-+};
-+
-+
-+/* command and control functions */
-+static void excite_nandflash_hwcontrol(struct mtd_info *mtd, int cmd)
-+{
-+	struct nand_chip *this = mtd->priv;
-+	io_reg_t regs = container_of(mtd,struct excite_nandflash_drvdata,board_mtd)->regs;
-+
-+	switch (cmd) {
-+	/* Select the command latch */
-+	case NAND_CTL_SETCLE: this->IO_ADDR_W = regs + EXCITE_NANDFLASH_CMD;
-+		break;
-+	/* Deselect the command latch */
-+	case NAND_CTL_CLRCLE: this->IO_ADDR_W = regs + EXCITE_NANDFLASH_DATA;
-+		break;
-+	/* Select the address latch */
-+	case NAND_CTL_SETALE: this->IO_ADDR_W = regs + EXCITE_NANDFLASH_ADDR;
-+		break;
-+	/* Deselect the address latch */
-+	case NAND_CTL_CLRALE: this->IO_ADDR_W = regs  + EXCITE_NANDFLASH_DATA;
-+		break;
-+	/* Select the chip  -- not used */
-+	case NAND_CTL_SETNCE:
-+		break;
-+	/* Deselect the chip -- not used */
-+	case NAND_CTL_CLRNCE:
-+		break;
-+	}
-+
-+	this->IO_ADDR_R = this->IO_ADDR_W;
-+}
-+
-+/* excite_nandflash_devready()
-+ *
-+ * returns 0 if the nand is busy, 1 if it is ready
-+ */
-+static int excite_nandflash_devready(struct mtd_info *mtd)
-+{
-+	struct excite_nandflash_drvdata *drvdata =
-+	    container_of(mtd, struct excite_nandflash_drvdata, board_mtd);
-+
-+	return io_readb(drvdata->regs + EXCITE_NANDFLASH_STATUS);
-+}
-+
-+/* device management functions */
-+
-+/* excite_nandflash_remove
-+ *
-+ * called by device layer to remove the driver
-+ * the binding to the mtd and all allocated
-+ * resources are released
-+ */
-+static int excite_nandflash_remove(struct device *dev)
-+{
-+	struct excite_nandflash_drvdata *this = dev_get_drvdata(dev);
-+
-+	pr_info(PFX "remove");
-+
-+	dev_set_drvdata(dev, NULL);
-+
-+	if (this == NULL) {
-+		pr_debug(PFX "call remove without private data!!");
-+		return 0;
-+	}
-+
-+
-+	/* free the common resources */
-+	if (this->regs != NULL) {
-+		iounmap(this->regs);
-+		this->regs = NULL;
-+	}
-+
-+	kfree(this);
-+
-+	return 0;
-+}
-+
-+static int elapsed;
-+
-+void my_workqueue_handler(void *arg)
-+{
-+	elapsed = 1;
-+}
-+
-+DECLARE_WORK(sigElapsed, my_workqueue_handler, 0);
-+
-+
-+/* excite_nandflash_probe
-+ *
-+ * called by device layer when it finds a device matching
-+ * one our driver can handled. This code checks to see if
-+ * it can allocate all necessary resources then calls the
-+ * nand layer to look for devices
-+*/
-+static int excite_nandflash_probe(struct device *dev)
-+{
-+	struct platform_device *pdev = to_platform_device(dev);
-+
-+	struct excite_nandflash_drvdata *drvdata;	    /* private driver data     */
-+	struct nand_chip              *board_chip;  /* private flash chip data */
-+	struct mtd_info               *board_mtd;   /* mtd info for this board */
-+
-+	int err      = 0;
-+	int count    = 0;
-+	struct timeval tv,endtv;
-+	unsigned int dt;
-+
-+	pr_info(PFX "probe dev: (%p)\n", dev);
-+
-+	pr_info(PFX "adjust LB timing\n");
-+	ocd_writel(0x00000330, LDP2);
-+
-+	drvdata = kmalloc(sizeof(*drvdata), GFP_KERNEL);
-+	if (unlikely(!drvdata)) {
-+		printk(KERN_ERR PFX "no memory for drvdata\n");
-+		err = -ENOMEM;
-+		goto mem_error;
-+	}
-+
-+	/* Initialize structures */
-+	memset(drvdata, 0, sizeof(*drvdata));
-+
-+	/* bind private data into driver */
-+	dev_set_drvdata(dev, drvdata);
-+
-+	/* allocate and map the resource */
-+	drvdata->regs =
-+	    excite_nandflash_map_regs(pdev, EXCITE_NANDFLASH_RESOURCE_REGS);
-+
-+	if (unlikely(!drvdata->regs)) {
-+		printk(KERN_ERR PFX "cannot reserve register region\n");
-+		err = -ENXIO;
-+		goto io_error;
-+	}
-+
-+	/* initialise our chip */
-+	board_chip = &drvdata->board_chip;
-+
-+	board_chip->IO_ADDR_R = drvdata->regs + EXCITE_NANDFLASH_DATA;
-+	board_chip->IO_ADDR_W = drvdata->regs + EXCITE_NANDFLASH_DATA;
-+
-+	board_chip->hwcontrol = excite_nandflash_hwcontrol;
-+	board_chip->dev_ready = excite_nandflash_devready;
-+
-+	board_chip->chip_delay = 25;
-+	#if 0
-+	/* TODO: speedup the initial scan */
-+	board_chip->options = NAND_USE_FLASH_BBT;
-+	#endif
-+	board_chip->eccmode = NAND_ECC_SOFT;
-+
-+	/* link chip to mtd */
-+	board_mtd = &drvdata->board_mtd;
-+	board_mtd->priv = board_chip;
-+
-+
-+	pr_info(PFX "FlashTest\n");
-+	elapsed = 0;
-+/*	schedule_delayed_work(&sigElapsed, 1*HZ);
-+	while (!elapsed) {
-+		io_readb(drvdata->regs + EXCITE_NANDFLASH_STATUS);
-+		count++;
-+	}
-+	pr_info(PFX "reads in 1 sec --> %d\n",count);
-+*/
-+	do_gettimeofday(&tv);
-+	for (count = 0 ; count < 1000000; count ++) {
-+		io_readb(drvdata->regs + EXCITE_NANDFLASH_STATUS);
-+	}
-+	do_gettimeofday(&endtv);
-+	dt = (endtv.tv_sec - tv.tv_sec) * 1000000 + endtv.tv_usec  - tv.tv_usec;
-+	pr_info(PFX "%8d us timeval\n",dt);
-+	pr_info(PFX "EndFlashTest\n");
-+
-+/*      return with error to unload everything
-+*/
-+io_error:
-+	iounmap(drvdata->regs);
-+
-+mem_error:
-+	kfree(drvdata);
-+
-+	if (err == 0)
-+		err = -EINVAL;
-+	return err;
-+}
-+
-+static struct device_driver excite_nandflash_driver = {
-+	.name = "excite_nand",
-+	.bus = &platform_bus_type,
-+	.probe = excite_nandflash_probe,
-+	.remove = excite_nandflash_remove,
-+};
-+
-+static int __init excite_nandflash_init(void)
-+{
-+	pr_info(PFX "register Driver (Rev: $Revision:$)\n");
-+	return driver_register(&excite_nandflash_driver);
-+}
-+
-+static void __exit excite_nandflash_exit(void)
-+{
-+	driver_unregister(&excite_nandflash_driver);
-+	pr_info(PFX "Driver unregistered");
-+}
-+
-+module_init(excite_nandflash_init);
-+module_exit(excite_nandflash_exit);
-+
-+MODULE_AUTHOR("Thies Moeller <thies.moeller@baslerweb.com>");
-+MODULE_DESCRIPTION("Basler eXcite NAND-Flash driver");
-+MODULE_LICENSE("GPL");
-diff -Naur linux-2.6.17.orig/arch/mips/basler/excite/excite_fpga.h linux-2.6.17/arch/mips/basler/excite/excite_fpga.h
---- linux-2.6.17.orig/arch/mips/basler/excite/excite_fpga.h	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/arch/mips/basler/excite/excite_fpga.h	2006-06-19 18:16:12.000000000 -0700
-@@ -0,0 +1,80 @@
-+#ifndef EXCITE_FPGA_H_INCLUDED
-+#define EXCITE_FPGA_H_INCLUDED
-+
-+
-+/**
-+ * Adress alignment of the individual FPGA bytes.
-+ * The address arrangement of the individual bytes of the FPGA is two
-+ * byte aligned at the embedded MK2 platform.
-+ */
-+#ifdef EXCITE_CCI_FPGA_MK2
-+typedef unsigned char excite_cci_fpga_align_t __attribute__ ((aligned(2)));
-+#else
-+typedef unsigned char excite_cci_fpga_align_t;
-+#endif
-+
-+
-+/**
-+ * Size of Dual Ported RAM.
-+ */
-+#define EXCITE_DPR_SIZE 263
-+
-+
-+/**
-+ * Size of Reserved Status Fields in Dual Ported RAM.
-+ */
-+#define EXCITE_DPR_STATUS_SIZE 7
-+
-+
-+
-+/**
-+ * FPGA.
-+ * Hardware register layout of the FPGA interface. The FPGA must accessed
-+ * byte wise solely.
-+ * @see EXCITE_CCI_DPR_MK2
-+ */
-+typedef struct excite_fpga {
-+
-+	/**
-+	 * Dual Ported RAM.
-+	 */
-+	excite_cci_fpga_align_t dpr[EXCITE_DPR_SIZE];
-+
-+	/**
-+	 * Status.
-+	 */
-+	excite_cci_fpga_align_t status[EXCITE_DPR_STATUS_SIZE];
-+
-+#ifdef EXCITE_CCI_FPGA_MK2
-+	/**
-+	 * RM9000 Interrupt.
-+	 * Write access initiates interrupt at the RM9000 (MIPS) processor of the eXcite.
-+	 */
-+	excite_cci_fpga_align_t rm9k_int;
-+#else
-+	/**
-+	 * MK2 Interrupt.
-+	 * Write access initiates interrupt at the ARM processor of the MK2.
-+	 */
-+	excite_cci_fpga_align_t mk2_int;
-+
-+	excite_cci_fpga_align_t gap[0x1000-0x10f];
-+
-+	/**
-+	 * IRQ Source/Acknowledge.
-+	 */
-+	excite_cci_fpga_align_t rm9k_irq_src;
-+
-+	/**
-+	 * IRQ Mask.
-+	 * Set bits enable the related interrupt.
-+	 */
-+	excite_cci_fpga_align_t rm9k_irq_mask;
-+#endif
-+
-+
-+} excite_fpga;
-+
-+
-+
-+#endif	/* ndef EXCITE_FPGA_H_INCLUDED */
-diff -Naur linux-2.6.17.orig/arch/mips/basler/excite/excite_iodev.c linux-2.6.17/arch/mips/basler/excite/excite_iodev.c
---- linux-2.6.17.orig/arch/mips/basler/excite/excite_iodev.c	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/arch/mips/basler/excite/excite_iodev.c	2006-06-19 18:16:12.000000000 -0700
-@@ -0,0 +1,183 @@
-+/*
-+ *  Copyright (C) 2005 by Basler Vision Technologies AG
-+ *  Author: Thomas Koeller <thomas.koeller@baslerweb.com>
-+ *
-+ *  This program is free software; you can redistribute it and/or modify
-+ *  it under the terms of the GNU General Public License as published by
-+ *  the Free Software Foundation; either version 2 of the License, or
-+ *  (at your option) any later version.
-+ *
-+ *  This program is distributed in the hope that it will be useful,
-+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ *  GNU General Public License for more details.
-+ *
-+ *  You should have received a copy of the GNU General Public License
-+ *  along with this program; if not, write to the Free Software
-+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-+ */
-+
-+#include <linux/config.h>
-+#include <linux/compiler.h>
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/sched.h>
-+#include <linux/wait.h>
-+#include <linux/poll.h>
-+#include <linux/interrupt.h>
-+#include <linux/platform_device.h>
-+#include <linux/miscdevice.h>
-+
-+#include "excite_iodev.h"
-+
-+
-+
-+static const struct resource *iodev_get_resource(struct platform_device *, const char *, unsigned int);
-+static int __init iodev_probe(struct device *);
-+static int __exit iodev_remove(struct device *);
-+static int iodev_open(struct inode *, struct file *);
-+static int iodev_release(struct inode *, struct file *);
-+static ssize_t iodev_read(struct file *, char __user *, size_t s, loff_t *);
-+static unsigned int iodev_poll(struct file *, struct poll_table_struct *);
-+static irqreturn_t iodev_irqhdl(int, void *, struct pt_regs *);
-+
-+
-+
-+static const char iodev_name[] = "iodev";
-+static unsigned int iodev_irq;
-+static DECLARE_WAIT_QUEUE_HEAD(wq);
-+
-+
-+
-+static struct file_operations fops =
-+{
-+	.owner		= THIS_MODULE,
-+	.open		= iodev_open,
-+	.release	= iodev_release,
-+	.read		= iodev_read,
-+	.poll		= iodev_poll
-+};
-+
-+static struct miscdevice miscdev =
-+{
-+	.minor		= MISC_DYNAMIC_MINOR,
-+	.name		= iodev_name,
-+	.fops		= &fops
-+};
-+
-+static struct device_driver iodev_driver =
-+{
-+	.name		= (char *) iodev_name,
-+	.bus		= &platform_bus_type,
-+	.owner		= THIS_MODULE,
-+	.probe		= iodev_probe,
-+	.remove		= __exit_p(iodev_remove)
-+};
-+
-+
-+
-+static const struct resource *
-+iodev_get_resource(struct platform_device *pdv, const char *name,
-+		     unsigned int type)
-+{
-+	char buf[80];
-+	if (snprintf(buf, sizeof buf, "%s_0", name) >= sizeof buf)
-+		return NULL;
-+	return platform_get_resource_byname(pdv, type, buf);
-+}
-+
-+
-+
-+/* No hotplugging on the platform bus - use __init */
-+static int __init iodev_probe(struct device *dev)
-+{
-+	struct platform_device * const pdv = to_platform_device(dev);
-+	const struct resource * const ri =
-+		iodev_get_resource(pdv, IODEV_RESOURCE_IRQ, IORESOURCE_IRQ);
-+
-+	if (unlikely(!ri))
-+		return -ENXIO;
-+
-+	iodev_irq = ri->start;
-+	return misc_register(&miscdev);
-+}
-+
-+
-+
-+static int __exit iodev_remove(struct device *dev)
-+{
-+	return misc_deregister(&miscdev);
-+}
-+
-+
-+
-+static int iodev_open(struct inode *i, struct file *f)
-+{
-+	return request_irq(iodev_irq, iodev_irqhdl, SA_INTERRUPT,
-+			   iodev_name, &miscdev);
-+}
-+
-+
-+
-+static int iodev_release(struct inode *i, struct file *f)
-+{
-+	free_irq(iodev_irq, &miscdev);
-+	return 0;
-+}
-+
-+
-+
-+
-+static ssize_t
-+iodev_read(struct file *f, char __user *d, size_t s, loff_t *o)
-+{
-+	ssize_t ret;
-+	DEFINE_WAIT(w);
-+
-+	prepare_to_wait(&wq, &w, TASK_INTERRUPTIBLE);
-+	if (!signal_pending(current))
-+		schedule();
-+	ret = signal_pending(current) ? -ERESTARTSYS : 0;
-+	finish_wait(&wq, &w);
-+	return ret;
-+}
-+
-+
-+static unsigned int iodev_poll(struct file *f, struct poll_table_struct *p)
-+{
-+	poll_wait(f, &wq, p);
-+	return POLLOUT | POLLWRNORM;
-+}
-+
-+
-+
-+
-+static irqreturn_t iodev_irqhdl(int irq, void *ctxt, struct pt_regs *regs)
-+{
-+	wake_up(&wq);
-+	return IRQ_HANDLED;
-+}
-+
-+
-+
-+static int __init iodev_init_module(void)
-+{
-+	return driver_register(&iodev_driver);
-+}
-+
-+
-+
-+static void __exit iodev_cleanup_module(void)
-+{
-+	driver_unregister(&iodev_driver);
-+}
-+
-+module_init(iodev_init_module);
-+module_exit(iodev_cleanup_module);
-+
-+
-+
-+MODULE_AUTHOR("Thomas Koeller <thomas.koeller@baslerweb.com>");
-+MODULE_DESCRIPTION("Basler eXcite i/o interrupt handler");
-+MODULE_VERSION("0.0");
-+MODULE_LICENSE("GPL");
-diff -Naur linux-2.6.17.orig/arch/mips/basler/excite/excite_iodev.h linux-2.6.17/arch/mips/basler/excite/excite_iodev.h
---- linux-2.6.17.orig/arch/mips/basler/excite/excite_iodev.h	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/arch/mips/basler/excite/excite_iodev.h	2006-06-19 18:16:12.000000000 -0700
-@@ -0,0 +1,10 @@
-+#ifndef __EXCITE_IODEV_H__
-+#define __EXCITE_IODEV_H__
-+
-+/* Device name */
-+#define IODEV_NAME		"iodev"
-+
-+/* Resource names */
-+#define IODEV_RESOURCE_IRQ	"excite_iodev_irq"
-+
-+#endif /* __EXCITE_IODEV_H__ */
-diff -Naur linux-2.6.17.orig/arch/mips/basler/excite/excite_irq.c linux-2.6.17/arch/mips/basler/excite/excite_irq.c
---- linux-2.6.17.orig/arch/mips/basler/excite/excite_irq.c	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/arch/mips/basler/excite/excite_irq.c	2006-06-19 18:16:12.000000000 -0700
-@@ -0,0 +1,129 @@
-+/*
-+ *  Copyright (C) by Basler Vision Technologies AG
-+ *  Author: Thomas Koeller <thomas.koeller@baslereb.com>
-+ *
-+ *  This program is free software; you can redistribute it and/or modify
-+ *  it under the terms of the GNU General Public License as published by
-+ *  the Free Software Foundation; either version 2 of the License, or
-+ *  (at your option) any later version.
-+ *
-+ *  This program is distributed in the hope that it will be useful,
-+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ *  GNU General Public License for more details.
-+ *
-+ *  You should have received a copy of the GNU General Public License
-+ *  along with this program; if not, write to the Free Software
-+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-+ */
-+
-+#include <linux/errno.h>
-+#include <linux/init.h>
-+#include <linux/kernel_stat.h>
-+#include <linux/module.h>
-+#include <linux/signal.h>
-+#include <linux/sched.h>
-+#include <linux/types.h>
-+#include <linux/interrupt.h>
-+#include <linux/ioport.h>
-+#include <linux/timex.h>
-+#include <linux/slab.h>
-+#include <linux/random.h>
-+#include <asm/bitops.h>
-+#include <asm/bootinfo.h>
-+#include <asm/io.h>
-+#include <asm/irq.h>
-+#include <asm/irq_cpu.h>
-+#include <asm/mipsregs.h>
-+#include <asm/system.h>
-+#include <asm/rm9k-ocd.h>
-+
-+#include <excite.h>
-+
-+extern asmlinkage void excite_handle_int(void);
-+
-+/*
-+ * Initialize the interrupt handler
-+ */
-+void __init arch_init_irq(void)
-+{
-+	mips_cpu_irq_init(0);
-+	rm7k_cpu_irq_init(8);
-+	rm9k_cpu_irq_init(12);
-+
-+#ifdef CONFIG_KGDB
-+	excite_kgdb_init();
-+#endif
-+}
-+
-+asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
-+{
-+	const u32
-+		interrupts = read_c0_cause() >> 8,
-+		mask = ((read_c0_status() >> 8) & 0x000000ff) |
-+		       (read_c0_intcontrol() & 0x0000ff00),
-+		pending = interrupts & mask;
-+	u32 msgintflags, msgintmask, msgint;
-+
-+	/* process timer interrupt */
-+	if (pending & (1 << TIMER_IRQ)) {
-+		do_IRQ(TIMER_IRQ, regs);
-+		return;
-+	}
-+
-+	/* Process PCI interrupts */
-+#if USB_IRQ < 10
-+	msgintflags = ocd_readl(INTP0Status0 + (USB_MSGINT / 0x20 * 0x10));
-+	msgintmask  = ocd_readl(INTP0Mask0 + (USB_MSGINT / 0x20 * 0x10));
-+	msgint	    = msgintflags & msgintmask & (0x1 << (USB_MSGINT % 0x20));
-+	if ((pending & (1 << USB_IRQ)) && msgint) {
-+#else
-+	if (pending & (1 << USB_IRQ)) {
-+#endif
-+		do_IRQ(USB_IRQ, regs);
-+		return;
-+	}
-+
-+	/* Process TITAN interrupts */
-+	msgintflags = ocd_readl(INTP0Status0 + (TITAN_MSGINT / 0x20 * 0x10));
-+	msgintmask  = ocd_readl(INTP0Mask0 + (TITAN_MSGINT / 0x20 * 0x10));
-+	msgint	    = msgintflags & msgintmask & (0x1 << (TITAN_MSGINT % 0x20));
-+	if ((pending & (1 << TITAN_IRQ)) && msgint) {
-+		ocd_writel(msgint, INTP0Clear0 + (TITAN_MSGINT / 0x20 * 0x10));
-+#if defined(CONFIG_KGDB)
-+		excite_kgdb_inthdl(regs);
-+#endif
-+		do_IRQ(TITAN_IRQ, regs);
-+		return;
-+	}
-+
-+	/* Process FPGA line #0 interrupts */
-+	msgintflags = ocd_readl(INTP0Status0 + (FPGA0_MSGINT / 0x20 * 0x10));
-+	msgintmask  = ocd_readl(INTP0Mask0 + (FPGA0_MSGINT / 0x20 * 0x10));
-+	msgint	    = msgintflags & msgintmask & (0x1 << (FPGA0_MSGINT % 0x20));
-+	if ((pending & (1 << FPGA0_IRQ)) && msgint) {
-+		do_IRQ(FPGA0_IRQ, regs);
-+		return;
-+	}
-+
-+	/* Process FPGA line #1 interrupts */
-+	msgintflags = ocd_readl(INTP0Status0 + (FPGA1_MSGINT / 0x20 * 0x10));
-+	msgintmask  = ocd_readl(INTP0Mask0 + (FPGA1_MSGINT / 0x20 * 0x10));
-+	msgint	    = msgintflags & msgintmask & (0x1 << (FPGA1_MSGINT % 0x20));
-+	if ((pending & (1 << FPGA1_IRQ)) && msgint) {
-+		do_IRQ(FPGA1_IRQ, regs);
-+		return;
-+	}
-+
-+	/* Process PHY interrupts */
-+	msgintflags = ocd_readl(INTP0Status0 + (PHY_MSGINT / 0x20 * 0x10));
-+	msgintmask  = ocd_readl(INTP0Mask0 + (PHY_MSGINT / 0x20 * 0x10));
-+	msgint	    = msgintflags & msgintmask & (0x1 << (PHY_MSGINT % 0x20));
-+	if ((pending & (1 << PHY_IRQ)) && msgint) {
-+		do_IRQ(PHY_IRQ, regs);
-+		return;
-+	}
-+
-+	/* Process spurious interrupts */
-+	spurious_interrupt(regs);
-+}
-diff -Naur linux-2.6.17.orig/arch/mips/basler/excite/excite_procfs.c linux-2.6.17/arch/mips/basler/excite/excite_procfs.c
---- linux-2.6.17.orig/arch/mips/basler/excite/excite_procfs.c	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/arch/mips/basler/excite/excite_procfs.c	2006-06-19 18:16:12.000000000 -0700
-@@ -0,0 +1,81 @@
-+/*
-+ *  Copyright (C) 2004, 2005 by Basler Vision Technologies AG
-+ *  Author: Thomas Koeller <thomas.koeller@baslerweb.com>
-+ *
-+ *  Procfs support for Basler eXcite
-+ *
-+ *  This program is free software; you can redistribute it and/or modify
-+ *  it under the terms of the GNU General Public License as published by
-+ *  the Free Software Foundation; either version 2 of the License, or
-+ *  (at your option) any later version.
-+ *
-+ *  This program is distributed in the hope that it will be useful,
-+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ *  GNU General Public License for more details.
-+ *
-+ *  You should have received a copy of the GNU General Public License
-+ *  along with this program; if not, write to the Free Software
-+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-+ */
-+
-+#include <linux/config.h>
-+#include <linux/proc_fs.h>
-+#include <linux/stat.h>
-+#include <asm/page.h>
-+#include <asm/io.h>
-+#include <asm/system.h>
-+#include <asm/rm9k-ocd.h>
-+
-+#include <excite.h>
-+
-+static int excite_get_unit_id(char *buf, char **addr, off_t offs, int size)
-+{
-+	const int len = snprintf(buf, PAGE_SIZE, "%06x", unit_id);
-+	const int w = len - offs;
-+	*addr = buf + offs;
-+	return w < size ? w : size;
-+}
-+
-+static int
-+excite_bootrom_read(char *page, char **start, off_t off, int count,
-+		  int *eof, void *data)
-+{
-+	void __iomem * src;
-+
-+	if (off >= EXCITE_SIZE_BOOTROM) {
-+		*eof = 1;
-+		return 0;
-+	}
-+
-+	if ((off + count) > EXCITE_SIZE_BOOTROM)
-+		count = EXCITE_SIZE_BOOTROM - off;
-+
-+	src = ioremap(EXCITE_PHYS_BOOTROM + off, count);
-+	if (src) {
-+		memcpy_fromio(page, src, count);
-+		iounmap(src);
-+		*start = page;
-+	} else {
-+		count = -ENOMEM;
-+	}
-+
-+	return count;
-+}
-+
-+void excite_procfs_init(void)
-+{
-+	/* Create & populate /proc/excite */
-+	struct proc_dir_entry * const pdir = proc_mkdir("excite", &proc_root);
-+	if (pdir) {
-+		struct proc_dir_entry * e;
-+
-+		e = create_proc_info_entry("unit_id", S_IRUGO, pdir,
-+					   excite_get_unit_id);
-+		if (e) e->size = 6;
-+
-+		e = create_proc_read_entry("bootrom", S_IRUGO, pdir,
-+					   excite_bootrom_read, NULL);
-+		if (e) e->size = EXCITE_SIZE_BOOTROM;
-+	}
-+}
-diff -Naur linux-2.6.17.orig/arch/mips/basler/excite/excite_prom.c linux-2.6.17/arch/mips/basler/excite/excite_prom.c
---- linux-2.6.17.orig/arch/mips/basler/excite/excite_prom.c	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/arch/mips/basler/excite/excite_prom.c	2006-06-19 18:16:12.000000000 -0700
-@@ -0,0 +1,148 @@
-+/*
-+ *  Copyright (C) 2004, 2005 by Thomas Koeller (thomas.koeller@baslerweb.com)
-+ *  Based on the PMC-Sierra Yosemite board support by Ralf Baechle and
-+ *  Manish Lachwani.
-+ *
-+ *  This program is free software; you can redistribute it and/or modify
-+ *  it under the terms of the GNU General Public License as published by
-+ *  the Free Software Foundation; either version 2 of the License, or
-+ *  (at your option) any later version.
-+ *
-+ *  This program is distributed in the hope that it will be useful,
-+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ *  GNU General Public License for more details.
-+ *
-+ *  You should have received a copy of the GNU General Public License
-+ *  along with this program; if not, write to the Free Software
-+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-+ */
-+
-+#include <linux/config.h>
-+#include <linux/init.h>
-+#include <linux/sched.h>
-+#include <linux/mm.h>
-+#include <linux/delay.h>
-+#include <linux/smp.h>
-+#include <linux/module.h>
-+#include <asm/io.h>
-+#include <asm/pgtable.h>
-+#include <asm/processor.h>
-+#include <asm/reboot.h>
-+#include <asm/system.h>
-+#include <asm/bootinfo.h>
-+#include <asm/string.h>
-+
-+#include <excite.h>
-+
-+/* This struct is used by Redboot to pass arguments to the kernel */
-+typedef struct
-+{
-+	char *name;
-+	char *val;
-+} t_env_var;
-+
-+struct parmblock {
-+	t_env_var memsize;
-+	t_env_var modetty0;
-+	t_env_var ethaddr;
-+	t_env_var env_end;
-+	char *argv[2];
-+	char text[0];
-+};
-+
-+static unsigned int prom_argc;
-+static const char ** prom_argv;
-+static const t_env_var * prom_env;
-+
-+static void prom_halt(void) __attribute__((noreturn));
-+static void prom_exit(void) __attribute__((noreturn));
-+
-+
-+
-+const char *get_system_type(void)
-+{
-+	return "Basler eXcite";
-+}
-+
-+/*
-+ * Halt the system
-+ */
-+static void prom_halt(void)
-+{
-+	printk(KERN_NOTICE "\n** System halted.\n");
-+	while (1)
-+		asm volatile (
-+			"\t.set\tmips3\n"
-+			"\twait\n"
-+			"\t.set\tmips0\n"
-+		);
-+}
-+
-+/*
-+ * Reset the CPU and re-enter Redboot
-+ */
-+static void prom_exit(void)
-+{
-+	unsigned int i;
-+	volatile unsigned char * const flg =
-+		(volatile unsigned char *) (EXCITE_ADDR_FPGA + EXCITE_FPGA_DPR);
-+
-+	/* Clear the watchdog reset flag, set the reboot flag */
-+	*flg &= ~0x01;
-+	*flg |= 0x80;
-+
-+	for (i = 0; i < 10; i++) {
-+		*(volatile unsigned char *)  (EXCITE_ADDR_FPGA + EXCITE_FPGA_SYSCTL) = 0x02;
-+		iob();
-+		mdelay(1000);
-+	}
-+
-+	printk(KERN_NOTICE "Reset failed\n");
-+	prom_halt();
-+}
-+
-+static const char __init *prom_getenv(char *name)
-+{
-+	const t_env_var * p;
-+	for (p = prom_env; p->name != NULL; p++)
-+		if(strcmp(name, p->name) == 0)
-+			break;
-+	return p->val;
-+}
-+
-+/*
-+ * Init routine which accepts the variables from Redboot
-+ */
-+void __init prom_init(void)
-+{
-+	const struct parmblock * const pb = (struct parmblock *) fw_arg2;
-+
-+	prom_argc = fw_arg0;
-+	prom_argv = (const char **) fw_arg1;
-+	prom_env = &pb->memsize;
-+
-+	/* Callbacks for halt, restart */
-+	_machine_restart = (void (*)(char *)) prom_exit;
-+	_machine_halt = prom_halt;
-+
-+#ifdef CONFIG_32BIT
-+	/* copy command line */
-+	strcpy(arcs_cmdline, prom_argv[1]);
-+	memsize = simple_strtol(prom_getenv("memsize"), NULL, 16);
-+	strcpy(modetty, prom_getenv("modetty0"));
-+#endif /* CONFIG_32BIT */
-+
-+#ifdef CONFIG_64BIT
-+#	error 64 bit support not implemented
-+#endif /* CONFIG_64BIT */
-+
-+	mips_machgroup = MACH_GROUP_TITAN;
-+	mips_machtype = MACH_TITAN_EXCITE;
-+}
-+
-+/* This is called from free_initmem(), so we need to provide it */
-+void __init prom_free_prom_memory(void)
-+{
-+	/* Nothing to do */
-+}
-diff -Naur linux-2.6.17.orig/arch/mips/basler/excite/excite_setup.c linux-2.6.17/arch/mips/basler/excite/excite_setup.c
---- linux-2.6.17.orig/arch/mips/basler/excite/excite_setup.c	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/arch/mips/basler/excite/excite_setup.c	2006-06-19 18:16:12.000000000 -0700
-@@ -0,0 +1,307 @@
-+/*
-+ *  Copyright (C) 2004, 2005 by Basler Vision Technologies AG
-+ *  Author: Thomas Koeller <thomas.koeller@baslerweb.com>
-+ *  Based on the PMC-Sierra Yosemite board support by Ralf Baechle and
-+ *  Manish Lachwani.
-+ *
-+ *  This program is free software; you can redistribute it and/or modify
-+ *  it under the terms of the GNU General Public License as published by
-+ *  the Free Software Foundation; either version 2 of the License, or
-+ *  (at your option) any later version.
-+ *
-+ *  This program is distributed in the hope that it will be useful,
-+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ *  GNU General Public License for more details.
-+ *
-+ *  You should have received a copy of the GNU General Public License
-+ *  along with this program; if not, write to the Free Software
-+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-+ */
-+
-+#include <linux/config.h>
-+#include <linux/types.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/string.h>
-+#include <linux/tty.h>
-+#include <linux/serial_core.h>
-+#include <linux/serial.h>
-+#include <linux/ioport.h>
-+#include <linux/spinlock.h>
-+#include <asm/bootinfo.h>
-+#include <asm/mipsregs.h>
-+#include <asm/pgtable-32.h>
-+#include <asm/io.h>
-+#include <asm/time.h>
-+#include <asm/rm9k-ocd.h>
-+
-+#include <excite.h>
-+
-+#define TITAN_UART_CLK	25000000
-+
-+#if 1
-+/* normal serial port assignment */
-+#define REGBASE_SER0	0x0208
-+#define REGBASE_SER1	0x0238
-+#define MASK_SER0	0x1
-+#define MASK_SER1	0x2
-+#else
-+/* serial ports swapped */
-+#define REGBASE_SER0	0x0238
-+#define REGBASE_SER1	0x0208
-+#define MASK_SER0	0x2
-+#define MASK_SER1	0x1
-+#endif
-+
-+unsigned long memsize;
-+char modetty[30];
-+unsigned int titan_irq = TITAN_IRQ;
-+static void __iomem * ctl_regs;
-+u32 unit_id;
-+
-+volatile void __iomem * const ocd_base = (void *) (EXCITE_ADDR_OCD);
-+volatile void __iomem * const titan_base = (void *) (EXCITE_ADDR_TITAN);
-+
-+/* Protect access to shared GPI registers */
-+spinlock_t titan_lock = SPIN_LOCK_UNLOCKED;
-+int titan_irqflags;
-+
-+
-+static void excite_timer_init(void)
-+{
-+	const u32 modebit5 = ocd_readl(0x00e4);
-+	unsigned int
-+		mult = ((modebit5 >> 11) & 0x1f) + 2,
-+		div = ((modebit5 >> 16) & 0x1f) + 2;
-+
-+	if (div == 33) div = 1;
-+	mips_hpt_frequency = EXCITE_CPU_EXT_CLOCK * mult / div / 2;
-+}
-+
-+static void excite_timer_setup(struct irqaction *irq)
-+{
-+	/* The eXcite platform uses the alternate timer interrupt */
-+	set_c0_intcontrol(0x80);
-+	setup_irq(TIMER_IRQ, irq);
-+}
-+
-+static int __init excite_init_console(void)
-+{
-+#if defined(CONFIG_SERIAL_8250)
-+	static __initdata char serr[] =
-+		KERN_ERR "Serial port #%u setup failed\n";
-+	struct uart_port up;
-+
-+	/* Take the DUART out of reset */
-+	titan_writel(0x00ff1cff, CPRR);
-+
-+#if defined(CONFIG_KGDB) || (CONFIG_SERIAL_8250_NR_UARTS > 1)
-+	/* Enable both ports */
-+	titan_writel(MASK_SER0 | MASK_SER1, UACFG);
-+#else
-+	/* Enable port #0 only */
-+	titan_writel(MASK_SER0, UACFG);
-+#endif	/* defined(CONFIG_KGDB) */
-+
-+ 	/*
-+	 * Set up serial port #0. Do not use autodetection; the result is
-+	 * not what we want.
-+ 	 */
-+	memset(&up, 0, sizeof(up));
-+	up.membase	= (char *) titan_addr(REGBASE_SER0);
-+	up.irq		= TITAN_IRQ;
-+	up.uartclk	= TITAN_UART_CLK;
-+	up.regshift	= 0;
-+	up.iotype	= UPIO_MEM32;
-+	up.type		= PORT_RM9000;
-+	up.flags	= UPF_SHARE_IRQ;
-+	up.line		= 0;
-+	if (early_serial_setup(&up))
-+		printk(serr, up.line);
-+
-+#if CONFIG_SERIAL_8250_NR_UARTS > 1
-+	/* And now for port #1. */
-+	up.membase	= (char *) titan_addr(REGBASE_SER1);
-+	up.line		= 1;
-+ 	if (early_serial_setup(&up))
-+		printk(serr, up.line);
-+#endif /* CONFIG_SERIAL_8250_NR_UARTS > 1 */
-+#else
-+	/* Leave the DUART in reset */
-+	titan_writel(0x00ff3cff, CPRR);
-+#endif  /* defined(CONFIG_SERIAL_8250) */
-+
-+	return 0;
-+}
-+
-+static int __init excite_platform_init(void)
-+{
-+	unsigned int i;
-+	unsigned char buf[3];
-+	u8 reg;
-+	void __iomem * dpr;
-+
-+	/* BIU buffer allocations */
-+	ocd_writel(8, CPURSLMT);	/* CPU */
-+	titan_writel(4, CPGRWL);	/* GPI / Ethernet */
-+
-+	/* Map control registers located in FPGA */
-+	ctl_regs = ioremap_nocache(EXCITE_PHYS_FPGA + EXCITE_FPGA_SYSCTL, 16);
-+	if (!ctl_regs)
-+		panic("eXcite: failed to map platform control registers\n");
-+	memcpy_fromio(buf, ctl_regs + 2, ARRAY_SIZE(buf));
-+	unit_id = buf[0] | (buf[1] << 8) | (buf[2] << 16);
-+
-+	/* Clear the reboot flag */
-+	dpr = ioremap_nocache(EXCITE_PHYS_FPGA + EXCITE_FPGA_DPR, 1);
-+	reg = __raw_readb(dpr);
-+	__raw_writeb(reg & 0x7f, dpr);
-+	iounmap(dpr);
-+
-+	/* Interrupt controller setup */
-+	for (i = INTP0Status0; i < INTP0Status0 + 0x80; i += 0x10) {
-+		ocd_writel(0x00000000, i + 0x04);
-+		ocd_writel(0xffffffff, i + 0x0c);
-+	}
-+	ocd_writel(0x2, NMICONFIG);
-+
-+	ocd_writel(0x1 << (TITAN_MSGINT % 0x20),
-+		   INTP0Mask0 + (0x10 * (TITAN_MSGINT / 0x20)));
-+	ocd_writel((0x1 << (FPGA0_MSGINT % 0x20))
-+		   | ocd_readl(INTP0Mask0 + (0x10 * (FPGA0_MSGINT / 0x20))),
-+		   INTP0Mask0 + (0x10 * (FPGA0_MSGINT / 0x20)));
-+	ocd_writel((0x1 << (FPGA1_MSGINT % 0x20))
-+		   | ocd_readl(INTP0Mask0 + (0x10 * (FPGA1_MSGINT / 0x20))),
-+		   INTP0Mask0 + (0x10 * (FPGA1_MSGINT / 0x20)));
-+	ocd_writel((0x1 << (PHY_MSGINT % 0x20))
-+		   | ocd_readl(INTP0Mask0 + (0x10 * (PHY_MSGINT / 0x20))),
-+		   INTP0Mask0 + (0x10 * (PHY_MSGINT / 0x20)));
-+#if USB_IRQ < 10
-+	ocd_writel((0x1 << (USB_MSGINT % 0x20))
-+		   | ocd_readl(INTP0Mask0 + (0x10 * (USB_MSGINT / 0x20))),
-+		   INTP0Mask0 + (0x10 * (USB_MSGINT / 0x20)));
-+#endif
-+	/* Enable the packet FIFO, XDMA and XDMA arbiter */
-+	titan_writel(0x00ff18ff, CPRR);
-+
-+	/*
-+	 * Set up the PADMUX. Power down all ethernet slices,
-+	 * they will be powered up and configured at device startup.
-+	 */
-+	titan_writel(0x00878206, CPTC1R);
-+	titan_writel(0x00001100, CPTC0R); /* latch PADMUX, enable WCIMODE */
-+
-+	/* Reset and enable the FIFO block */
-+	titan_writel(0x00000001, SDRXFCIE);
-+	titan_writel(0x00000001, SDTXFCIE);
-+	titan_writel(0x00000100, SDRXFCIE);
-+	titan_writel(0x00000000, SDTXFCIE);
-+
-+	/*
-+	 * Initialize the common interrupt shared by all components of
-+	 * the GPI/Ethernet subsystem.
-+	 */
-+	titan_writel((EXCITE_PHYS_OCD >> 12), CPCFG0);
-+	titan_writel(TITAN_MSGINT, CPCFG1);
-+
-+	/*
-+	 * XDMA configuration.
-+	 * In order for the XDMA to be sharable among multiple drivers,
-+	 * the setup must be done here in the platform. The reason is that
-+	 * this setup can only be done while the XDMA is in reset. If this
-+	 * were done in a driver, it would interrupt all other drivers
-+	 * using the XDMA.
-+	 */
-+	titan_writel(0x80021dff, GXCFG);	/* XDMA reset */
-+	titan_writel(0x00000000, CPXCISRA);
-+	titan_writel(0x00000000, CPXCISRB);	/* clear pending interrupts */
-+#if defined (CONFIG_HIGHMEM)
-+#	error change for HIGHMEM support!
-+#else
-+	titan_writel(0x00000000, GXDMADRPFX);	/* buffer address prefix */
-+#endif
-+	titan_writel(0, GXDMA_DESCADR);
-+
-+	for (i = 0x5040; i <= 0x5300; i += 0x0040)
-+		titan_writel(0x80080000, i);	/* reset channel */
-+
-+	titan_writel((0x1 << 29)			/* no sparse tx descr. */
-+		     | (0x1 << 28)			/* no sparse rx descr. */
-+		     | (0x1 << 23) | (0x1 << 24)	/* descriptor coherency */
-+		     | (0x1 << 21) | (0x1 << 22)	/* data coherency */
-+		     | (0x1 << 17)
-+		     | 0x1dff,
-+		     GXCFG);
-+
-+#if defined(CONFIG_SMP)
-+#	error No SMP support
-+#else
-+	/* All interrupts go to core #0 only. */
-+	titan_writel(0x1f007fff, CPDST0A);
-+	titan_writel(0x00000000, CPDST0B);
-+	titan_writel(0x0000ff3f, CPDST1A);
-+	titan_writel(0x00000000, CPDST1B);
-+	titan_writel(0x00ffffff, CPXDSTA);
-+	titan_writel(0x00000000, CPXDSTB);
-+#endif
-+
-+	/* Enable DUART interrupts, disable everything else. */
-+	titan_writel(0x04000000, CPGIG0ER);
-+	titan_writel(0x000000c0, CPGIG1ER);
-+
-+	excite_procfs_init();
-+	return 0;
-+}
-+
-+void __init plat_setup(void)
-+{
-+	volatile u32 * const boot_ocd_base = (u32 *) 0xbf7fc000;
-+
-+	/* Announce RAM to system */
-+	add_memory_region(0x00000000, memsize, BOOT_MEM_RAM);
-+
-+	/* Set up timer initialization hooks */
-+	board_time_init = excite_timer_init;
-+	board_timer_setup = excite_timer_setup;
-+
-+	/* Set up the peripheral address map */
-+	*(boot_ocd_base + (LKB9 / sizeof (u32))) = 0;
-+	*(boot_ocd_base + (LKB10 / sizeof (u32))) = 0;
-+	*(boot_ocd_base + (LKB11 / sizeof (u32))) = 0;
-+	*(boot_ocd_base + (LKB12 / sizeof (u32))) = 0;
-+	wmb();
-+	*(boot_ocd_base + (LKB0 / sizeof (u32))) = EXCITE_PHYS_OCD >> 4;
-+	wmb();
-+
-+	ocd_writel((EXCITE_PHYS_TITAN >> 4) | 0x1UL, LKB5);
-+	ocd_writel(((EXCITE_SIZE_TITAN >> 4) & 0x7fffff00) - 0x100, LKM5);
-+	ocd_writel((EXCITE_PHYS_SCRAM >> 4) | 0x1UL, LKB13);
-+	ocd_writel(((EXCITE_SIZE_SCRAM >> 4) & 0xffffff00) - 0x100, LKM13);
-+
-+	/* Local bus slot #0 */
-+	ocd_writel(0x00040510, LDP0);
-+	ocd_writel((EXCITE_PHYS_BOOTROM >> 4) | 0x1UL, LKB9);
-+	ocd_writel(((EXCITE_SIZE_BOOTROM >> 4) & 0x03ffff00) - 0x100, LKM9);
-+
-+	/* Local bus slot #2 */
-+	ocd_writel(0x00000330, LDP2);
-+	ocd_writel((EXCITE_PHYS_FPGA >> 4) | 0x1, LKB11);
-+	ocd_writel(((EXCITE_SIZE_FPGA >> 4) - 0x100) & 0x03ffff00, LKM11);
-+
-+	/* Local bus slot #3 */
-+	ocd_writel(0x00123413, LDP3);
-+	ocd_writel((EXCITE_PHYS_NAND >> 4) | 0x1, LKB12);
-+	ocd_writel(((EXCITE_SIZE_NAND >> 4) - 0x100) & 0x03ffff00, LKM12);
-+}
-+
-+
-+
-+console_initcall(excite_init_console);
-+arch_initcall(excite_platform_init);
-+
-+EXPORT_SYMBOL(titan_lock);
-+EXPORT_SYMBOL(titan_irqflags);
-+EXPORT_SYMBOL(titan_irq);
-+EXPORT_SYMBOL(ocd_base);
-+EXPORT_SYMBOL(titan_base);
-diff -Naur linux-2.6.17.orig/arch/mips/basler/excite/Makefile linux-2.6.17/arch/mips/basler/excite/Makefile
---- linux-2.6.17.orig/arch/mips/basler/excite/Makefile	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/arch/mips/basler/excite/Makefile	2006-06-19 18:16:12.000000000 -0700
-@@ -0,0 +1,9 @@
-+#
-+# Makefile for Basler eXcite
-+#
-+
-+obj-$(CONFIG_BASLER_EXCITE)	+= excite_irq.o excite_prom.o excite_setup.o \
-+				   excite_device.o excite_procfs.o
-+
-+obj-$(CONFIG_KGDB)		+= excite_dbg_io.o
-+obj-m				+= excite_iodev.o
-diff -Naur linux-2.6.17.orig/arch/mips/cobalt/console.c linux-2.6.17/arch/mips/cobalt/console.c
---- linux-2.6.17.orig/arch/mips/cobalt/console.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/cobalt/console.c	2006-06-19 18:16:12.000000000 -0700
-@@ -41,3 +41,8 @@
- 
- 	printk("Cobalt: early console registered\n");
- }
-+
-+void __init disable_early_printk(void)
-+{
-+	unregister_console(&cons_info);
-+}
-diff -Naur linux-2.6.17.orig/arch/mips/cobalt/setup.c linux-2.6.17/arch/mips/cobalt/setup.c
---- linux-2.6.17.orig/arch/mips/cobalt/setup.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/cobalt/setup.c	2006-06-19 18:16:12.000000000 -0700
-@@ -68,19 +68,46 @@
- extern struct pci_ops gt64111_pci_ops;
- 
- static struct resource cobalt_mem_resource = {
--	"PCI memory", GT64111_MEM_BASE, GT64111_MEM_END, IORESOURCE_MEM
-+	.start	= GT64111_MEM_BASE,
-+	.end	= GT64111_MEM_END,
-+	.name	= "PCI memory",
-+	.flags	= IORESOURCE_MEM
- };
- 
- static struct resource cobalt_io_resource = {
--	"PCI I/O", 0x1000, 0xffff, IORESOURCE_IO
-+	.start	= 0x1000,
-+	.end	= 0xffff,
-+	.name	= "PCI I/O",
-+	.flags	= IORESOURCE_IO
- };
- 
- static struct resource cobalt_io_resources[] = {
--	{ "dma1", 0x00, 0x1f, IORESOURCE_BUSY },
--	{ "timer", 0x40, 0x5f, IORESOURCE_BUSY },
--	{ "keyboard", 0x60, 0x6f, IORESOURCE_BUSY },
--	{ "dma page reg", 0x80, 0x8f, IORESOURCE_BUSY },
--	{ "dma2", 0xc0, 0xdf, IORESOURCE_BUSY },
-+	{
-+		.start	= 0x00,
-+		.end	= 0x1f,
-+		.name	= "dma1",
-+		.flags	= IORESOURCE_BUSY
-+	}, {
-+		.start	= 0x40,
-+		.end	= 0x5f,
-+		.name	= "timer",
-+		.flags	= IORESOURCE_BUSY
-+	}, {
-+		.start	= 0x60,
-+		.end	= 0x6f,
-+		.name	= "keyboard",
-+		.flags	= IORESOURCE_BUSY
-+	}, {
-+		.start	= 0x80,
-+		.end	= 0x8f,
-+		.name	= "dma page reg",
-+		.flags	= IORESOURCE_BUSY
-+	}, {
-+		.start	= 0xc0,
-+		.end	= 0xdf,
-+		.name	= "dma2",
-+		.flags	= IORESOURCE_BUSY
-+	},
- };
- 
- #define COBALT_IO_RESOURCES (sizeof(cobalt_io_resources)/sizeof(struct resource))
-@@ -93,7 +120,7 @@
- 	.io_offset	= 0 - GT64111_IO_BASE
- };
- 
--void __init plat_setup(void)
-+void __init plat_mem_setup(void)
- {
- 	static struct uart_port uart;
- 	unsigned int devfn = PCI_DEVFN(COBALT_PCICONF_VIA, 0);
-diff -Naur linux-2.6.17.orig/arch/mips/configs/atlas_defconfig linux-2.6.17/arch/mips/configs/atlas_defconfig
---- linux-2.6.17.orig/arch/mips/configs/atlas_defconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/configs/atlas_defconfig	2006-06-19 18:16:12.000000000 -0700
-@@ -41,8 +41,6 @@
- # CONFIG_MIPS_XXS1500 is not set
- # CONFIG_PNX8550_V2PCI is not set
- # CONFIG_PNX8550_JBS is not set
--# CONFIG_DDB5074 is not set
--# CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
- # CONFIG_MACH_VR41XX is not set
- # CONFIG_PMC_YOSEMITE is not set
-@@ -67,6 +65,7 @@
- CONFIG_GENERIC_FIND_NEXT_BIT=y
- CONFIG_GENERIC_HWEIGHT=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
- CONFIG_DMA_NONCOHERENT=y
- CONFIG_DMA_NEED_PCI_MAP_STATE=y
- CONFIG_MIPS_BONITO64=y
-diff -Naur linux-2.6.17.orig/arch/mips/configs/bigsur_defconfig linux-2.6.17/arch/mips/configs/bigsur_defconfig
---- linux-2.6.17.orig/arch/mips/configs/bigsur_defconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/configs/bigsur_defconfig	2006-06-19 18:16:12.000000000 -0700
-@@ -41,8 +41,6 @@
- # CONFIG_MIPS_XXS1500 is not set
- # CONFIG_PNX8550_V2PCI is not set
- # CONFIG_PNX8550_JBS is not set
--# CONFIG_DDB5074 is not set
--# CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
- # CONFIG_MACH_VR41XX is not set
- # CONFIG_PMC_YOSEMITE is not set
-@@ -83,6 +81,7 @@
- CONFIG_GENERIC_FIND_NEXT_BIT=y
- CONFIG_GENERIC_HWEIGHT=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
- CONFIG_DMA_COHERENT=y
- CONFIG_CPU_BIG_ENDIAN=y
- # CONFIG_CPU_LITTLE_ENDIAN is not set
-diff -Naur linux-2.6.17.orig/arch/mips/configs/capcella_defconfig linux-2.6.17/arch/mips/configs/capcella_defconfig
---- linux-2.6.17.orig/arch/mips/configs/capcella_defconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/configs/capcella_defconfig	2006-06-19 18:16:12.000000000 -0700
-@@ -41,8 +41,6 @@
- # CONFIG_MIPS_XXS1500 is not set
- # CONFIG_PNX8550_V2PCI is not set
- # CONFIG_PNX8550_JBS is not set
--# CONFIG_DDB5074 is not set
--# CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
- CONFIG_MACH_VR41XX=y
- # CONFIG_PMC_YOSEMITE is not set
-@@ -75,6 +73,7 @@
- CONFIG_GENERIC_FIND_NEXT_BIT=y
- CONFIG_GENERIC_HWEIGHT=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
- CONFIG_DMA_NONCOHERENT=y
- CONFIG_DMA_NEED_PCI_MAP_STATE=y
- # CONFIG_CPU_BIG_ENDIAN is not set
-diff -Naur linux-2.6.17.orig/arch/mips/configs/cobalt_defconfig linux-2.6.17/arch/mips/configs/cobalt_defconfig
---- linux-2.6.17.orig/arch/mips/configs/cobalt_defconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/configs/cobalt_defconfig	2006-06-19 18:16:12.000000000 -0700
-@@ -41,8 +41,6 @@
- # CONFIG_MIPS_XXS1500 is not set
- # CONFIG_PNX8550_V2PCI is not set
- # CONFIG_PNX8550_JBS is not set
--# CONFIG_DDB5074 is not set
--# CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
- # CONFIG_MACH_VR41XX is not set
- # CONFIG_PMC_YOSEMITE is not set
-@@ -68,6 +66,7 @@
- CONFIG_GENERIC_FIND_NEXT_BIT=y
- CONFIG_GENERIC_HWEIGHT=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
- CONFIG_DMA_NONCOHERENT=y
- CONFIG_DMA_NEED_PCI_MAP_STATE=y
- CONFIG_I8259=y
-diff -Naur linux-2.6.17.orig/arch/mips/configs/db1000_defconfig linux-2.6.17/arch/mips/configs/db1000_defconfig
---- linux-2.6.17.orig/arch/mips/configs/db1000_defconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/configs/db1000_defconfig	2006-06-19 18:16:12.000000000 -0700
-@@ -41,8 +41,6 @@
- # CONFIG_MIPS_XXS1500 is not set
- # CONFIG_PNX8550_V2PCI is not set
- # CONFIG_PNX8550_JBS is not set
--# CONFIG_DDB5074 is not set
--# CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
- # CONFIG_MACH_VR41XX is not set
- # CONFIG_PMC_YOSEMITE is not set
-@@ -67,6 +65,7 @@
- CONFIG_GENERIC_FIND_NEXT_BIT=y
- CONFIG_GENERIC_HWEIGHT=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
- CONFIG_DMA_NONCOHERENT=y
- CONFIG_DMA_NEED_PCI_MAP_STATE=y
- # CONFIG_CPU_BIG_ENDIAN is not set
-diff -Naur linux-2.6.17.orig/arch/mips/configs/db1100_defconfig linux-2.6.17/arch/mips/configs/db1100_defconfig
---- linux-2.6.17.orig/arch/mips/configs/db1100_defconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/configs/db1100_defconfig	2006-06-19 18:16:12.000000000 -0700
-@@ -41,8 +41,6 @@
- # CONFIG_MIPS_XXS1500 is not set
- # CONFIG_PNX8550_V2PCI is not set
- # CONFIG_PNX8550_JBS is not set
--# CONFIG_DDB5074 is not set
--# CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
- # CONFIG_MACH_VR41XX is not set
- # CONFIG_PMC_YOSEMITE is not set
-@@ -67,6 +65,7 @@
- CONFIG_GENERIC_FIND_NEXT_BIT=y
- CONFIG_GENERIC_HWEIGHT=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
- CONFIG_DMA_NONCOHERENT=y
- CONFIG_DMA_NEED_PCI_MAP_STATE=y
- # CONFIG_CPU_BIG_ENDIAN is not set
-diff -Naur linux-2.6.17.orig/arch/mips/configs/db1200_defconfig linux-2.6.17/arch/mips/configs/db1200_defconfig
---- linux-2.6.17.orig/arch/mips/configs/db1200_defconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/configs/db1200_defconfig	2006-06-19 18:16:12.000000000 -0700
-@@ -41,8 +41,6 @@
- # CONFIG_MIPS_XXS1500 is not set
- # CONFIG_PNX8550_V2PCI is not set
- # CONFIG_PNX8550_JBS is not set
--# CONFIG_DDB5074 is not set
--# CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
- # CONFIG_MACH_VR41XX is not set
- # CONFIG_PMC_YOSEMITE is not set
-@@ -67,6 +65,7 @@
- CONFIG_GENERIC_FIND_NEXT_BIT=y
- CONFIG_GENERIC_HWEIGHT=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
- CONFIG_DMA_COHERENT=y
- CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y
- # CONFIG_CPU_BIG_ENDIAN is not set
-diff -Naur linux-2.6.17.orig/arch/mips/configs/db1500_defconfig linux-2.6.17/arch/mips/configs/db1500_defconfig
---- linux-2.6.17.orig/arch/mips/configs/db1500_defconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/configs/db1500_defconfig	2006-06-19 18:16:12.000000000 -0700
-@@ -41,8 +41,6 @@
- # CONFIG_MIPS_XXS1500 is not set
- # CONFIG_PNX8550_V2PCI is not set
- # CONFIG_PNX8550_JBS is not set
--# CONFIG_DDB5074 is not set
--# CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
- # CONFIG_MACH_VR41XX is not set
- # CONFIG_PMC_YOSEMITE is not set
-@@ -67,6 +65,7 @@
- CONFIG_GENERIC_FIND_NEXT_BIT=y
- CONFIG_GENERIC_HWEIGHT=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
- CONFIG_DMA_NONCOHERENT=y
- CONFIG_DMA_NEED_PCI_MAP_STATE=y
- CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y
-diff -Naur linux-2.6.17.orig/arch/mips/configs/db1550_defconfig linux-2.6.17/arch/mips/configs/db1550_defconfig
---- linux-2.6.17.orig/arch/mips/configs/db1550_defconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/configs/db1550_defconfig	2006-06-19 18:16:12.000000000 -0700
-@@ -41,8 +41,6 @@
- # CONFIG_MIPS_XXS1500 is not set
- # CONFIG_PNX8550_V2PCI is not set
- # CONFIG_PNX8550_JBS is not set
--# CONFIG_DDB5074 is not set
--# CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
- # CONFIG_MACH_VR41XX is not set
- # CONFIG_PMC_YOSEMITE is not set
-@@ -67,6 +65,7 @@
- CONFIG_GENERIC_FIND_NEXT_BIT=y
- CONFIG_GENERIC_HWEIGHT=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
- CONFIG_DMA_NONCOHERENT=y
- CONFIG_DMA_NEED_PCI_MAP_STATE=y
- CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y
-diff -Naur linux-2.6.17.orig/arch/mips/configs/ddb5476_defconfig linux-2.6.17/arch/mips/configs/ddb5476_defconfig
---- linux-2.6.17.orig/arch/mips/configs/ddb5476_defconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/configs/ddb5476_defconfig	1969-12-31 16:00:00.000000000 -0800
-@@ -1,917 +0,0 @@
--#
--# Automatically generated make config: don't edit
--# Linux kernel version: 2.6.17-rc2
--# Mon Apr 24 14:51:00 2006
--#
--CONFIG_MIPS=y
--
--#
--# Machine selection
--#
--# CONFIG_MIPS_MTX1 is not set
--# CONFIG_MIPS_BOSPORUS is not set
--# CONFIG_MIPS_PB1000 is not set
--# CONFIG_MIPS_PB1100 is not set
--# CONFIG_MIPS_PB1500 is not set
--# CONFIG_MIPS_PB1550 is not set
--# CONFIG_MIPS_PB1200 is not set
--# CONFIG_MIPS_DB1000 is not set
--# CONFIG_MIPS_DB1100 is not set
--# CONFIG_MIPS_DB1500 is not set
--# CONFIG_MIPS_DB1550 is not set
--# CONFIG_MIPS_DB1200 is not set
--# CONFIG_MIPS_MIRAGE is not set
--# CONFIG_MIPS_COBALT is not set
--# CONFIG_MACH_DECSTATION is not set
--# CONFIG_MIPS_EV64120 is not set
--# CONFIG_MIPS_EV96100 is not set
--# CONFIG_MIPS_IVR is not set
--# CONFIG_MIPS_ITE8172 is not set
--# CONFIG_MACH_JAZZ is not set
--# CONFIG_LASAT is not set
--# CONFIG_MIPS_ATLAS is not set
--# CONFIG_MIPS_MALTA is not set
--# CONFIG_MIPS_SEAD is not set
--# CONFIG_MIPS_SIM is not set
--# CONFIG_MOMENCO_JAGUAR_ATX is not set
--# CONFIG_MOMENCO_OCELOT is not set
--# CONFIG_MOMENCO_OCELOT_3 is not set
--# CONFIG_MOMENCO_OCELOT_C is not set
--# CONFIG_MOMENCO_OCELOT_G is not set
--# CONFIG_MIPS_XXS1500 is not set
--# CONFIG_PNX8550_V2PCI is not set
--# CONFIG_PNX8550_JBS is not set
--# CONFIG_DDB5074 is not set
--CONFIG_DDB5476=y
--# CONFIG_DDB5477 is not set
--# CONFIG_MACH_VR41XX is not set
--# CONFIG_PMC_YOSEMITE is not set
--# CONFIG_QEMU is not set
--# CONFIG_SGI_IP22 is not set
--# CONFIG_SGI_IP27 is not set
--# CONFIG_SGI_IP32 is not set
--# CONFIG_SIBYTE_BIGSUR is not set
--# CONFIG_SIBYTE_SWARM is not set
--# CONFIG_SIBYTE_SENTOSA is not set
--# CONFIG_SIBYTE_RHONE is not set
--# CONFIG_SIBYTE_CARMEL is not set
--# CONFIG_SIBYTE_PTSWARM is not set
--# CONFIG_SIBYTE_LITTLESUR is not set
--# CONFIG_SIBYTE_CRHINE is not set
--# CONFIG_SIBYTE_CRHONE is not set
--# CONFIG_SNI_RM200_PCI is not set
--# CONFIG_TOSHIBA_JMR3927 is not set
--# CONFIG_TOSHIBA_RBTX4927 is not set
--# CONFIG_TOSHIBA_RBTX4938 is not set
--CONFIG_RWSEM_GENERIC_SPINLOCK=y
--CONFIG_GENERIC_FIND_NEXT_BIT=y
--CONFIG_GENERIC_HWEIGHT=y
--CONFIG_GENERIC_CALIBRATE_DELAY=y
--CONFIG_DMA_NONCOHERENT=y
--CONFIG_DMA_NEED_PCI_MAP_STATE=y
--CONFIG_I8259=y
--# CONFIG_CPU_BIG_ENDIAN is not set
--CONFIG_CPU_LITTLE_ENDIAN=y
--CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
--CONFIG_IRQ_CPU=y
--CONFIG_DDB5XXX_COMMON=y
--CONFIG_MIPS_L1_CACHE_SHIFT=5
--CONFIG_HAVE_STD_PC_SERIAL_PORT=y
--
--#
--# CPU selection
--#
--# CONFIG_CPU_MIPS32_R1 is not set
--# CONFIG_CPU_MIPS32_R2 is not set
--# CONFIG_CPU_MIPS64_R1 is not set
--# CONFIG_CPU_MIPS64_R2 is not set
--# CONFIG_CPU_R3000 is not set
--# CONFIG_CPU_TX39XX is not set
--# CONFIG_CPU_VR41XX is not set
--# CONFIG_CPU_R4300 is not set
--# CONFIG_CPU_R4X00 is not set
--# CONFIG_CPU_TX49XX is not set
--# CONFIG_CPU_R5000 is not set
--CONFIG_CPU_R5432=y
--# CONFIG_CPU_R6000 is not set
--# CONFIG_CPU_NEVADA is not set
--# CONFIG_CPU_R8000 is not set
--# CONFIG_CPU_R10000 is not set
--# CONFIG_CPU_RM7000 is not set
--# CONFIG_CPU_RM9000 is not set
--# CONFIG_CPU_SB1 is not set
--CONFIG_SYS_HAS_CPU_R5432=y
--CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
--CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
--CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
--CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
--
--#
--# Kernel type
--#
--CONFIG_32BIT=y
--# CONFIG_64BIT is not set
--CONFIG_PAGE_SIZE_4KB=y
--# CONFIG_PAGE_SIZE_8KB is not set
--# CONFIG_PAGE_SIZE_16KB is not set
--# CONFIG_PAGE_SIZE_64KB is not set
--# CONFIG_MIPS_MT is not set
--CONFIG_CPU_HAS_LLSC=y
--CONFIG_CPU_HAS_SYNC=y
--CONFIG_GENERIC_HARDIRQS=y
--CONFIG_GENERIC_IRQ_PROBE=y
--CONFIG_ARCH_FLATMEM_ENABLE=y
--CONFIG_SELECT_MEMORY_MODEL=y
--CONFIG_FLATMEM_MANUAL=y
--# CONFIG_DISCONTIGMEM_MANUAL is not set
--# CONFIG_SPARSEMEM_MANUAL is not set
--CONFIG_FLATMEM=y
--CONFIG_FLAT_NODE_MEM_MAP=y
--# CONFIG_SPARSEMEM_STATIC is not set
--CONFIG_SPLIT_PTLOCK_CPUS=4
--CONFIG_PREEMPT_NONE=y
--# CONFIG_PREEMPT_VOLUNTARY is not set
--# CONFIG_PREEMPT is not set
--
--#
--# Code maturity level options
--#
--CONFIG_EXPERIMENTAL=y
--CONFIG_BROKEN_ON_SMP=y
--CONFIG_INIT_ENV_ARG_LIMIT=32
--
--#
--# General setup
--#
--CONFIG_LOCALVERSION=""
--CONFIG_LOCALVERSION_AUTO=y
--CONFIG_SWAP=y
--CONFIG_SYSVIPC=y
--# CONFIG_POSIX_MQUEUE is not set
--# CONFIG_BSD_PROCESS_ACCT is not set
--CONFIG_SYSCTL=y
--# CONFIG_AUDIT is not set
--# CONFIG_IKCONFIG is not set
--CONFIG_RELAY=y
--CONFIG_INITRAMFS_SOURCE=""
--# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
--CONFIG_EMBEDDED=y
--CONFIG_KALLSYMS=y
--# CONFIG_KALLSYMS_EXTRA_PASS is not set
--CONFIG_HOTPLUG=y
--CONFIG_PRINTK=y
--CONFIG_BUG=y
--CONFIG_ELF_CORE=y
--CONFIG_BASE_FULL=y
--CONFIG_FUTEX=y
--CONFIG_EPOLL=y
--CONFIG_SHMEM=y
--CONFIG_SLAB=y
--# CONFIG_TINY_SHMEM is not set
--CONFIG_BASE_SMALL=0
--# CONFIG_SLOB is not set
--
--#
--# Loadable module support
--#
--# CONFIG_MODULES is not set
--
--#
--# Block layer
--#
--# CONFIG_LBD is not set
--# CONFIG_BLK_DEV_IO_TRACE is not set
--# CONFIG_LSF is not set
--
--#
--# IO Schedulers
--#
--CONFIG_IOSCHED_NOOP=y
--CONFIG_IOSCHED_AS=y
--CONFIG_IOSCHED_DEADLINE=y
--CONFIG_IOSCHED_CFQ=y
--CONFIG_DEFAULT_AS=y
--# CONFIG_DEFAULT_DEADLINE is not set
--# CONFIG_DEFAULT_CFQ is not set
--# CONFIG_DEFAULT_NOOP is not set
--CONFIG_DEFAULT_IOSCHED="anticipatory"
--
--#
--# Bus options (PCI, PCMCIA, EISA, ISA, TC)
--#
--CONFIG_HW_HAS_PCI=y
--CONFIG_PCI=y
--CONFIG_ISA=y
--CONFIG_MMU=y
--
--#
--# PCCARD (PCMCIA/CardBus) support
--#
--# CONFIG_PCCARD is not set
--
--#
--# PCI Hotplug Support
--#
--# CONFIG_HOTPLUG_PCI is not set
--
--#
--# Executable file formats
--#
--CONFIG_BINFMT_ELF=y
--# CONFIG_BINFMT_MISC is not set
--CONFIG_TRAD_SIGNALS=y
--
--#
--# Networking
--#
--CONFIG_NET=y
--
--#
--# Networking options
--#
--# CONFIG_NETDEBUG is not set
--CONFIG_PACKET=y
--# CONFIG_PACKET_MMAP is not set
--CONFIG_UNIX=y
--CONFIG_XFRM=y
--CONFIG_XFRM_USER=y
--CONFIG_NET_KEY=y
--CONFIG_INET=y
--# CONFIG_IP_MULTICAST is not set
--# CONFIG_IP_ADVANCED_ROUTER is not set
--CONFIG_IP_FIB_HASH=y
--CONFIG_IP_PNP=y
--# CONFIG_IP_PNP_DHCP is not set
--CONFIG_IP_PNP_BOOTP=y
--# CONFIG_IP_PNP_RARP is not set
--# CONFIG_NET_IPIP is not set
--# CONFIG_NET_IPGRE is not set
--# CONFIG_ARPD is not set
--# CONFIG_SYN_COOKIES is not set
--# CONFIG_INET_AH is not set
--# CONFIG_INET_ESP is not set
--# CONFIG_INET_IPCOMP is not set
--# CONFIG_INET_XFRM_TUNNEL is not set
--# CONFIG_INET_TUNNEL is not set
--CONFIG_INET_DIAG=y
--CONFIG_INET_TCP_DIAG=y
--# CONFIG_TCP_CONG_ADVANCED is not set
--CONFIG_TCP_CONG_BIC=y
--# CONFIG_IPV6 is not set
--# CONFIG_INET6_XFRM_TUNNEL is not set
--# CONFIG_INET6_TUNNEL is not set
--# CONFIG_NETFILTER is not set
--
--#
--# DCCP Configuration (EXPERIMENTAL)
--#
--# CONFIG_IP_DCCP is not set
--
--#
--# SCTP Configuration (EXPERIMENTAL)
--#
--# CONFIG_IP_SCTP is not set
--
--#
--# TIPC Configuration (EXPERIMENTAL)
--#
--# CONFIG_TIPC is not set
--# CONFIG_ATM is not set
--# CONFIG_BRIDGE is not set
--# CONFIG_VLAN_8021Q is not set
--# CONFIG_DECNET is not set
--# CONFIG_LLC2 is not set
--# CONFIG_IPX is not set
--# CONFIG_ATALK is not set
--# CONFIG_X25 is not set
--# CONFIG_LAPB is not set
--# CONFIG_NET_DIVERT is not set
--# CONFIG_ECONET is not set
--# CONFIG_WAN_ROUTER is not set
--
--#
--# QoS and/or fair queueing
--#
--# CONFIG_NET_SCHED is not set
--
--#
--# Network testing
--#
--# CONFIG_NET_PKTGEN is not set
--# CONFIG_HAMRADIO is not set
--# CONFIG_IRDA is not set
--# CONFIG_BT is not set
--CONFIG_IEEE80211=y
--# CONFIG_IEEE80211_DEBUG is not set
--CONFIG_IEEE80211_CRYPT_WEP=y
--CONFIG_IEEE80211_CRYPT_CCMP=y
--CONFIG_IEEE80211_SOFTMAC=y
--# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
--CONFIG_WIRELESS_EXT=y
--
--#
--# Device Drivers
--#
--
--#
--# Generic Driver Options
--#
--CONFIG_STANDALONE=y
--CONFIG_PREVENT_FIRMWARE_BUILD=y
--CONFIG_FW_LOADER=y
--
--#
--# Connector - unified userspace <-> kernelspace linker
--#
--CONFIG_CONNECTOR=y
--CONFIG_PROC_EVENTS=y
--
--#
--# Memory Technology Devices (MTD)
--#
--# CONFIG_MTD is not set
--
--#
--# Parallel port support
--#
--# CONFIG_PARPORT is not set
--
--#
--# Plug and Play support
--#
--# CONFIG_PNP is not set
--
--#
--# Block devices
--#
--# CONFIG_BLK_CPQ_DA is not set
--# CONFIG_BLK_CPQ_CISS_DA is not set
--# CONFIG_BLK_DEV_DAC960 is not set
--# CONFIG_BLK_DEV_UMEM is not set
--# CONFIG_BLK_DEV_COW_COMMON is not set
--# CONFIG_BLK_DEV_LOOP is not set
--# CONFIG_BLK_DEV_NBD is not set
--# CONFIG_BLK_DEV_SX8 is not set
--# CONFIG_BLK_DEV_RAM is not set
--# CONFIG_BLK_DEV_INITRD is not set
--CONFIG_CDROM_PKTCDVD=y
--CONFIG_CDROM_PKTCDVD_BUFFERS=8
--# CONFIG_CDROM_PKTCDVD_WCACHE is not set
--CONFIG_ATA_OVER_ETH=y
--
--#
--# ATA/ATAPI/MFM/RLL support
--#
--CONFIG_IDE=y
--CONFIG_BLK_DEV_IDE=y
--
--#
--# Please see Documentation/ide.txt for help/info on IDE drives
--#
--# CONFIG_BLK_DEV_IDE_SATA is not set
--CONFIG_BLK_DEV_IDEDISK=y
--# CONFIG_IDEDISK_MULTI_MODE is not set
--# CONFIG_BLK_DEV_IDECD is not set
--# CONFIG_BLK_DEV_IDETAPE is not set
--# CONFIG_BLK_DEV_IDEFLOPPY is not set
--# CONFIG_IDE_TASK_IOCTL is not set
--
--#
--# IDE chipset support/bugfixes
--#
--CONFIG_IDE_GENERIC=y
--# CONFIG_BLK_DEV_IDEPCI is not set
--# CONFIG_IDE_ARM is not set
--# CONFIG_IDE_CHIPSETS is not set
--# CONFIG_BLK_DEV_IDEDMA is not set
--# CONFIG_IDEDMA_AUTO is not set
--# CONFIG_BLK_DEV_HD is not set
--
--#
--# SCSI device support
--#
--CONFIG_RAID_ATTRS=y
--# CONFIG_SCSI is not set
--
--#
--# Old CD-ROM drivers (not SCSI, not IDE)
--#
--# CONFIG_CD_NO_IDESCSI is not set
--
--#
--# Multi-device support (RAID and LVM)
--#
--# CONFIG_MD is not set
--
--#
--# Fusion MPT device support
--#
--# CONFIG_FUSION is not set
--
--#
--# IEEE 1394 (FireWire) support
--#
--# CONFIG_IEEE1394 is not set
--
--#
--# I2O device support
--#
--# CONFIG_I2O is not set
--
--#
--# Network device support
--#
--CONFIG_NETDEVICES=y
--# CONFIG_DUMMY is not set
--# CONFIG_BONDING is not set
--# CONFIG_EQUALIZER is not set
--# CONFIG_TUN is not set
--
--#
--# ARCnet devices
--#
--# CONFIG_ARCNET is not set
--
--#
--# PHY device support
--#
--CONFIG_PHYLIB=y
--
--#
--# MII PHY device drivers
--#
--CONFIG_MARVELL_PHY=y
--CONFIG_DAVICOM_PHY=y
--CONFIG_QSEMI_PHY=y
--CONFIG_LXT_PHY=y
--CONFIG_CICADA_PHY=y
--
--#
--# Ethernet (10 or 100Mbit)
--#
--CONFIG_NET_ETHERNET=y
--# CONFIG_MII is not set
--# CONFIG_HAPPYMEAL is not set
--# CONFIG_SUNGEM is not set
--# CONFIG_CASSINI is not set
--# CONFIG_NET_VENDOR_3COM is not set
--# CONFIG_NET_VENDOR_SMC is not set
--# CONFIG_DM9000 is not set
--# CONFIG_NET_VENDOR_RACAL is not set
--
--#
--# Tulip family network device support
--#
--# CONFIG_NET_TULIP is not set
--# CONFIG_AT1700 is not set
--# CONFIG_DEPCA is not set
--# CONFIG_HP100 is not set
--# CONFIG_NET_ISA is not set
--# CONFIG_NET_PCI is not set
--
--#
--# Ethernet (1000 Mbit)
--#
--# CONFIG_ACENIC is not set
--# CONFIG_DL2K is not set
--# CONFIG_E1000 is not set
--# CONFIG_NS83820 is not set
--# CONFIG_HAMACHI is not set
--# CONFIG_YELLOWFIN is not set
--# CONFIG_R8169 is not set
--# CONFIG_SIS190 is not set
--# CONFIG_SKGE is not set
--# CONFIG_SKY2 is not set
--# CONFIG_SK98LIN is not set
--# CONFIG_TIGON3 is not set
--# CONFIG_BNX2 is not set
--
--#
--# Ethernet (10000 Mbit)
--#
--# CONFIG_CHELSIO_T1 is not set
--# CONFIG_IXGB is not set
--# CONFIG_S2IO is not set
--
--#
--# Token Ring devices
--#
--# CONFIG_TR is not set
--
--#
--# Wireless LAN (non-hamradio)
--#
--# CONFIG_NET_RADIO is not set
--
--#
--# Wan interfaces
--#
--# CONFIG_WAN is not set
--# CONFIG_FDDI is not set
--# CONFIG_HIPPI is not set
--# CONFIG_PPP is not set
--# CONFIG_SLIP is not set
--# CONFIG_SHAPER is not set
--# CONFIG_NETCONSOLE is not set
--# CONFIG_NETPOLL is not set
--# CONFIG_NET_POLL_CONTROLLER is not set
--
--#
--# ISDN subsystem
--#
--# CONFIG_ISDN is not set
--
--#
--# Telephony Support
--#
--# CONFIG_PHONE is not set
--
--#
--# Input device support
--#
--CONFIG_INPUT=y
--
--#
--# Userland interfaces
--#
--CONFIG_INPUT_MOUSEDEV=y
--CONFIG_INPUT_MOUSEDEV_PSAUX=y
--CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
--CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
--# CONFIG_INPUT_JOYDEV is not set
--# CONFIG_INPUT_TSDEV is not set
--# CONFIG_INPUT_EVDEV is not set
--# CONFIG_INPUT_EVBUG is not set
--
--#
--# Input Device Drivers
--#
--# CONFIG_INPUT_KEYBOARD is not set
--# CONFIG_INPUT_MOUSE is not set
--# CONFIG_INPUT_JOYSTICK is not set
--# CONFIG_INPUT_TOUCHSCREEN is not set
--# CONFIG_INPUT_MISC is not set
--
--#
--# Hardware I/O ports
--#
--CONFIG_SERIO=y
--# CONFIG_SERIO_I8042 is not set
--CONFIG_SERIO_SERPORT=y
--# CONFIG_SERIO_PCIPS2 is not set
--# CONFIG_SERIO_LIBPS2 is not set
--CONFIG_SERIO_RAW=y
--# CONFIG_GAMEPORT is not set
--
--#
--# Character devices
--#
--CONFIG_VT=y
--CONFIG_VT_CONSOLE=y
--CONFIG_HW_CONSOLE=y
--# CONFIG_SERIAL_NONSTANDARD is not set
--
--#
--# Serial drivers
--#
--CONFIG_SERIAL_8250=y
--CONFIG_SERIAL_8250_CONSOLE=y
--CONFIG_SERIAL_8250_PCI=y
--CONFIG_SERIAL_8250_NR_UARTS=4
--CONFIG_SERIAL_8250_RUNTIME_UARTS=4
--# CONFIG_SERIAL_8250_EXTENDED is not set
--
--#
--# Non-8250 serial port support
--#
--CONFIG_SERIAL_CORE=y
--CONFIG_SERIAL_CORE_CONSOLE=y
--# CONFIG_SERIAL_JSM is not set
--CONFIG_UNIX98_PTYS=y
--CONFIG_LEGACY_PTYS=y
--CONFIG_LEGACY_PTY_COUNT=256
--
--#
--# IPMI
--#
--# CONFIG_IPMI_HANDLER is not set
--
--#
--# Watchdog Cards
--#
--# CONFIG_WATCHDOG is not set
--# CONFIG_RTC is not set
--# CONFIG_GEN_RTC is not set
--# CONFIG_DTLK is not set
--# CONFIG_R3964 is not set
--# CONFIG_APPLICOM is not set
--
--#
--# Ftape, the floppy tape device driver
--#
--# CONFIG_DRM is not set
--# CONFIG_RAW_DRIVER is not set
--
--#
--# TPM devices
--#
--# CONFIG_TCG_TPM is not set
--# CONFIG_TELCLOCK is not set
--
--#
--# I2C support
--#
--# CONFIG_I2C is not set
--
--#
--# SPI support
--#
--# CONFIG_SPI is not set
--# CONFIG_SPI_MASTER is not set
--
--#
--# Dallas's 1-wire bus
--#
--# CONFIG_W1 is not set
--
--#
--# Hardware Monitoring support
--#
--# CONFIG_HWMON is not set
--# CONFIG_HWMON_VID is not set
--
--#
--# Misc devices
--#
--
--#
--# Multimedia devices
--#
--# CONFIG_VIDEO_DEV is not set
--
--#
--# Digital Video Broadcasting Devices
--#
--# CONFIG_DVB is not set
--
--#
--# Graphics support
--#
--CONFIG_FB=y
--# CONFIG_FB_CFB_FILLRECT is not set
--# CONFIG_FB_CFB_COPYAREA is not set
--# CONFIG_FB_CFB_IMAGEBLIT is not set
--# CONFIG_FB_MACMODES is not set
--CONFIG_FB_FIRMWARE_EDID=y
--# CONFIG_FB_MODE_HELPERS is not set
--# CONFIG_FB_TILEBLITTING is not set
--# CONFIG_FB_CIRRUS is not set
--# CONFIG_FB_PM2 is not set
--# CONFIG_FB_CYBER2000 is not set
--# CONFIG_FB_ASILIANT is not set
--# CONFIG_FB_IMSTT is not set
--# CONFIG_FB_S1D13XXX is not set
--# CONFIG_FB_NVIDIA is not set
--# CONFIG_FB_RIVA is not set
--# CONFIG_FB_MATROX is not set
--# CONFIG_FB_RADEON is not set
--# CONFIG_FB_ATY128 is not set
--# CONFIG_FB_ATY is not set
--# CONFIG_FB_SAVAGE is not set
--# CONFIG_FB_SIS is not set
--# CONFIG_FB_NEOMAGIC is not set
--# CONFIG_FB_KYRO is not set
--# CONFIG_FB_3DFX is not set
--# CONFIG_FB_VOODOO1 is not set
--# CONFIG_FB_SMIVGX is not set
--# CONFIG_FB_TRIDENT is not set
--# CONFIG_FB_VIRTUAL is not set
--
--#
--# Console display driver support
--#
--# CONFIG_VGA_CONSOLE is not set
--# CONFIG_MDA_CONSOLE is not set
--CONFIG_DUMMY_CONSOLE=y
--# CONFIG_FRAMEBUFFER_CONSOLE is not set
--
--#
--# Logo configuration
--#
--# CONFIG_LOGO is not set
--# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
--
--#
--# Sound
--#
--# CONFIG_SOUND is not set
--
--#
--# USB support
--#
--CONFIG_USB_ARCH_HAS_HCD=y
--CONFIG_USB_ARCH_HAS_OHCI=y
--CONFIG_USB_ARCH_HAS_EHCI=y
--# CONFIG_USB is not set
--
--#
--# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
--#
--
--#
--# USB Gadget Support
--#
--# CONFIG_USB_GADGET is not set
--
--#
--# MMC/SD Card support
--#
--# CONFIG_MMC is not set
--
--#
--# LED devices
--#
--# CONFIG_NEW_LEDS is not set
--
--#
--# LED drivers
--#
--
--#
--# LED Triggers
--#
--
--#
--# InfiniBand support
--#
--# CONFIG_INFINIBAND is not set
--
--#
--# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
--#
--
--#
--# Real Time Clock
--#
--# CONFIG_RTC_CLASS is not set
--
--#
--# File systems
--#
--CONFIG_EXT2_FS=y
--# CONFIG_EXT2_FS_XATTR is not set
--# CONFIG_EXT2_FS_XIP is not set
--# CONFIG_EXT3_FS is not set
--# CONFIG_REISERFS_FS is not set
--# CONFIG_JFS_FS is not set
--# CONFIG_FS_POSIX_ACL is not set
--# CONFIG_XFS_FS is not set
--# CONFIG_OCFS2_FS is not set
--# CONFIG_MINIX_FS is not set
--# CONFIG_ROMFS_FS is not set
--CONFIG_INOTIFY=y
--# CONFIG_QUOTA is not set
--CONFIG_DNOTIFY=y
--# CONFIG_AUTOFS_FS is not set
--# CONFIG_AUTOFS4_FS is not set
--CONFIG_FUSE_FS=y
--
--#
--# CD-ROM/DVD Filesystems
--#
--# CONFIG_ISO9660_FS is not set
--# CONFIG_UDF_FS is not set
--
--#
--# DOS/FAT/NT Filesystems
--#
--# CONFIG_MSDOS_FS is not set
--# CONFIG_VFAT_FS is not set
--# CONFIG_NTFS_FS is not set
--
--#
--# Pseudo filesystems
--#
--CONFIG_PROC_FS=y
--CONFIG_PROC_KCORE=y
--CONFIG_SYSFS=y
--# CONFIG_TMPFS is not set
--# CONFIG_HUGETLB_PAGE is not set
--CONFIG_RAMFS=y
--# CONFIG_CONFIGFS_FS is not set
--
--#
--# Miscellaneous filesystems
--#
--# CONFIG_ADFS_FS is not set
--# CONFIG_AFFS_FS is not set
--# CONFIG_HFS_FS is not set
--# CONFIG_HFSPLUS_FS is not set
--# CONFIG_BEFS_FS is not set
--# CONFIG_BFS_FS is not set
--# CONFIG_EFS_FS is not set
--# CONFIG_CRAMFS is not set
--# CONFIG_VXFS_FS is not set
--# CONFIG_HPFS_FS is not set
--# CONFIG_QNX4FS_FS is not set
--# CONFIG_SYSV_FS is not set
--# CONFIG_UFS_FS is not set
--
--#
--# Network File Systems
--#
--CONFIG_NFS_FS=y
--# CONFIG_NFS_V3 is not set
--# CONFIG_NFS_V4 is not set
--# CONFIG_NFS_DIRECTIO is not set
--# CONFIG_NFSD is not set
--CONFIG_ROOT_NFS=y
--CONFIG_LOCKD=y
--CONFIG_NFS_COMMON=y
--CONFIG_SUNRPC=y
--# CONFIG_RPCSEC_GSS_KRB5 is not set
--# CONFIG_RPCSEC_GSS_SPKM3 is not set
--# CONFIG_SMB_FS is not set
--# CONFIG_CIFS is not set
--# CONFIG_NCP_FS is not set
--# CONFIG_CODA_FS is not set
--# CONFIG_AFS_FS is not set
--# CONFIG_9P_FS is not set
--
--#
--# Partition Types
--#
--# CONFIG_PARTITION_ADVANCED is not set
--CONFIG_MSDOS_PARTITION=y
--
--#
--# Native Language Support
--#
--# CONFIG_NLS is not set
--
--#
--# Profiling support
--#
--# CONFIG_PROFILING is not set
--
--#
--# Kernel hacking
--#
--# CONFIG_PRINTK_TIME is not set
--# CONFIG_MAGIC_SYSRQ is not set
--# CONFIG_DEBUG_KERNEL is not set
--CONFIG_LOG_BUF_SHIFT=14
--# CONFIG_DEBUG_FS is not set
--# CONFIG_UNWIND_INFO is not set
--CONFIG_CROSSCOMPILE=y
--CONFIG_CMDLINE="ip=any"
--
--#
--# Security options
--#
--CONFIG_KEYS=y
--CONFIG_KEYS_DEBUG_PROC_KEYS=y
--# CONFIG_SECURITY is not set
--
--#
--# Cryptographic options
--#
--CONFIG_CRYPTO=y
--CONFIG_CRYPTO_HMAC=y
--CONFIG_CRYPTO_NULL=y
--CONFIG_CRYPTO_MD4=y
--CONFIG_CRYPTO_MD5=y
--CONFIG_CRYPTO_SHA1=y
--CONFIG_CRYPTO_SHA256=y
--CONFIG_CRYPTO_SHA512=y
--CONFIG_CRYPTO_WP512=y
--CONFIG_CRYPTO_TGR192=y
--CONFIG_CRYPTO_DES=y
--CONFIG_CRYPTO_BLOWFISH=y
--CONFIG_CRYPTO_TWOFISH=y
--CONFIG_CRYPTO_SERPENT=y
--CONFIG_CRYPTO_AES=y
--CONFIG_CRYPTO_CAST5=y
--CONFIG_CRYPTO_CAST6=y
--CONFIG_CRYPTO_TEA=y
--CONFIG_CRYPTO_ARC4=y
--CONFIG_CRYPTO_KHAZAD=y
--CONFIG_CRYPTO_ANUBIS=y
--CONFIG_CRYPTO_DEFLATE=y
--CONFIG_CRYPTO_MICHAEL_MIC=y
--CONFIG_CRYPTO_CRC32C=y
--# CONFIG_CRYPTO_TEST is not set
--
--#
--# Hardware crypto devices
--#
--
--#
--# Library routines
--#
--# CONFIG_CRC_CCITT is not set
--CONFIG_CRC16=y
--CONFIG_CRC32=y
--CONFIG_LIBCRC32C=y
--CONFIG_ZLIB_INFLATE=y
--CONFIG_ZLIB_DEFLATE=y
-diff -Naur linux-2.6.17.orig/arch/mips/configs/ddb5477_defconfig linux-2.6.17/arch/mips/configs/ddb5477_defconfig
---- linux-2.6.17.orig/arch/mips/configs/ddb5477_defconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/configs/ddb5477_defconfig	2006-06-19 18:16:13.000000000 -0700
-@@ -41,8 +41,6 @@
- # CONFIG_MIPS_XXS1500 is not set
- # CONFIG_PNX8550_V2PCI is not set
- # CONFIG_PNX8550_JBS is not set
--# CONFIG_DDB5074 is not set
--# CONFIG_DDB5476 is not set
- CONFIG_DDB5477=y
- # CONFIG_MACH_VR41XX is not set
- # CONFIG_PMC_YOSEMITE is not set
-@@ -68,6 +66,7 @@
- CONFIG_GENERIC_FIND_NEXT_BIT=y
- CONFIG_GENERIC_HWEIGHT=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
- CONFIG_DMA_NONCOHERENT=y
- CONFIG_DMA_NEED_PCI_MAP_STATE=y
- CONFIG_I8259=y
-diff -Naur linux-2.6.17.orig/arch/mips/configs/decstation_defconfig linux-2.6.17/arch/mips/configs/decstation_defconfig
---- linux-2.6.17.orig/arch/mips/configs/decstation_defconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/configs/decstation_defconfig	2006-06-19 18:16:13.000000000 -0700
-@@ -41,8 +41,6 @@
- # CONFIG_MIPS_XXS1500 is not set
- # CONFIG_PNX8550_V2PCI is not set
- # CONFIG_PNX8550_JBS is not set
--# CONFIG_DDB5074 is not set
--# CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
- # CONFIG_MACH_VR41XX is not set
- # CONFIG_PMC_YOSEMITE is not set
-@@ -68,6 +66,7 @@
- CONFIG_GENERIC_FIND_NEXT_BIT=y
- CONFIG_GENERIC_HWEIGHT=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
- CONFIG_DMA_NONCOHERENT=y
- CONFIG_DMA_NEED_PCI_MAP_STATE=y
- # CONFIG_CPU_BIG_ENDIAN is not set
-diff -Naur linux-2.6.17.orig/arch/mips/configs/e55_defconfig linux-2.6.17/arch/mips/configs/e55_defconfig
---- linux-2.6.17.orig/arch/mips/configs/e55_defconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/configs/e55_defconfig	2006-06-19 18:16:13.000000000 -0700
-@@ -41,8 +41,6 @@
- # CONFIG_MIPS_XXS1500 is not set
- # CONFIG_PNX8550_V2PCI is not set
- # CONFIG_PNX8550_JBS is not set
--# CONFIG_DDB5074 is not set
--# CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
- CONFIG_MACH_VR41XX=y
- # CONFIG_PMC_YOSEMITE is not set
-@@ -73,6 +71,7 @@
- CONFIG_GENERIC_FIND_NEXT_BIT=y
- CONFIG_GENERIC_HWEIGHT=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
- CONFIG_DMA_NONCOHERENT=y
- CONFIG_DMA_NEED_PCI_MAP_STATE=y
- # CONFIG_CPU_BIG_ENDIAN is not set
-diff -Naur linux-2.6.17.orig/arch/mips/configs/emma2rh_defconfig linux-2.6.17/arch/mips/configs/emma2rh_defconfig
---- linux-2.6.17.orig/arch/mips/configs/emma2rh_defconfig	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/arch/mips/configs/emma2rh_defconfig	2006-06-19 18:16:13.000000000 -0700
-@@ -0,0 +1,1198 @@
-+#
-+# Automatically generated make config: don't edit
-+# Linux kernel version: 2.6.17
-+# Sun Jun 18 13:46:53 2006
-+#
-+CONFIG_MIPS=y
-+
-+#
-+# Machine selection
-+#
-+# CONFIG_MIPS_MTX1 is not set
-+# CONFIG_MIPS_BOSPORUS is not set
-+# CONFIG_MIPS_PB1000 is not set
-+# CONFIG_MIPS_PB1100 is not set
-+# CONFIG_MIPS_PB1500 is not set
-+# CONFIG_MIPS_PB1550 is not set
-+# CONFIG_MIPS_PB1200 is not set
-+# CONFIG_MIPS_DB1000 is not set
-+# CONFIG_MIPS_DB1100 is not set
-+# CONFIG_MIPS_DB1500 is not set
-+# CONFIG_MIPS_DB1550 is not set
-+# CONFIG_MIPS_DB1200 is not set
-+# CONFIG_MIPS_MIRAGE is not set
-+# CONFIG_MIPS_COBALT is not set
-+# CONFIG_MACH_DECSTATION is not set
-+# CONFIG_MIPS_EV64120 is not set
-+# CONFIG_MIPS_EV96100 is not set
-+# CONFIG_MIPS_IVR is not set
-+# CONFIG_MIPS_ITE8172 is not set
-+# CONFIG_MACH_JAZZ is not set
-+# CONFIG_LASAT is not set
-+# CONFIG_MIPS_ATLAS is not set
-+# CONFIG_MIPS_MALTA is not set
-+# CONFIG_MIPS_SEAD is not set
-+# CONFIG_WR_PPMC is not set
-+# CONFIG_MIPS_SIM is not set
-+# CONFIG_MOMENCO_JAGUAR_ATX is not set
-+# CONFIG_MOMENCO_OCELOT is not set
-+# CONFIG_MOMENCO_OCELOT_3 is not set
-+# CONFIG_MOMENCO_OCELOT_C is not set
-+# CONFIG_MOMENCO_OCELOT_G is not set
-+# CONFIG_MIPS_XXS1500 is not set
-+# CONFIG_PNX8550_V2PCI is not set
-+# CONFIG_PNX8550_JBS is not set
-+# CONFIG_DDB5477 is not set
-+# CONFIG_MACH_VR41XX is not set
-+# CONFIG_PMC_YOSEMITE is not set
-+# CONFIG_QEMU is not set
-+CONFIG_MARKEINS=y
-+# CONFIG_SGI_IP22 is not set
-+# CONFIG_SGI_IP27 is not set
-+# CONFIG_SGI_IP32 is not set
-+# CONFIG_SIBYTE_BIGSUR is not set
-+# CONFIG_SIBYTE_SWARM is not set
-+# CONFIG_SIBYTE_SENTOSA is not set
-+# CONFIG_SIBYTE_RHONE is not set
-+# CONFIG_SIBYTE_CARMEL is not set
-+# CONFIG_SIBYTE_PTSWARM is not set
-+# CONFIG_SIBYTE_LITTLESUR is not set
-+# CONFIG_SIBYTE_CRHINE is not set
-+# CONFIG_SIBYTE_CRHONE is not set
-+# CONFIG_SNI_RM200_PCI is not set
-+# CONFIG_TOSHIBA_JMR3927 is not set
-+# CONFIG_TOSHIBA_RBTX4927 is not set
-+# CONFIG_TOSHIBA_RBTX4938 is not set
-+CONFIG_RWSEM_GENERIC_SPINLOCK=y
-+CONFIG_GENERIC_FIND_NEXT_BIT=y
-+CONFIG_GENERIC_HWEIGHT=y
-+CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
-+CONFIG_DMA_NONCOHERENT=y
-+CONFIG_DMA_NEED_PCI_MAP_STATE=y
-+CONFIG_CPU_BIG_ENDIAN=y
-+# CONFIG_CPU_LITTLE_ENDIAN is not set
-+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
-+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-+CONFIG_IRQ_CPU=y
-+CONFIG_SWAP_IO_SPACE=y
-+CONFIG_EMMA2RH=y
-+CONFIG_MIPS_L1_CACHE_SHIFT=5
-+
-+#
-+# CPU selection
-+#
-+# CONFIG_CPU_MIPS32_R1 is not set
-+# CONFIG_CPU_MIPS32_R2 is not set
-+# CONFIG_CPU_MIPS64_R1 is not set
-+# CONFIG_CPU_MIPS64_R2 is not set
-+# CONFIG_CPU_R3000 is not set
-+# CONFIG_CPU_TX39XX is not set
-+# CONFIG_CPU_VR41XX is not set
-+# CONFIG_CPU_R4300 is not set
-+# CONFIG_CPU_R4X00 is not set
-+# CONFIG_CPU_TX49XX is not set
-+CONFIG_CPU_R5000=y
-+# CONFIG_CPU_R5432 is not set
-+# CONFIG_CPU_R6000 is not set
-+# CONFIG_CPU_NEVADA is not set
-+# CONFIG_CPU_R8000 is not set
-+# CONFIG_CPU_R10000 is not set
-+# CONFIG_CPU_RM7000 is not set
-+# CONFIG_CPU_RM9000 is not set
-+# CONFIG_CPU_SB1 is not set
-+CONFIG_SYS_HAS_CPU_R5000=y
-+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
-+
-+#
-+# Kernel type
-+#
-+CONFIG_32BIT=y
-+# CONFIG_64BIT is not set
-+CONFIG_PAGE_SIZE_4KB=y
-+# CONFIG_PAGE_SIZE_8KB is not set
-+# CONFIG_PAGE_SIZE_16KB is not set
-+# CONFIG_PAGE_SIZE_64KB is not set
-+CONFIG_MIPS_MT_DISABLED=y
-+# CONFIG_MIPS_MT_SMTC is not set
-+# CONFIG_MIPS_MT_SMP is not set
-+# CONFIG_MIPS_VPE_LOADER is not set
-+# CONFIG_64BIT_PHYS_ADDR is not set
-+CONFIG_CPU_HAS_LLSC=y
-+CONFIG_CPU_HAS_SYNC=y
-+CONFIG_GENERIC_HARDIRQS=y
-+CONFIG_GENERIC_IRQ_PROBE=y
-+CONFIG_ARCH_FLATMEM_ENABLE=y
-+CONFIG_SELECT_MEMORY_MODEL=y
-+CONFIG_FLATMEM_MANUAL=y
-+# CONFIG_DISCONTIGMEM_MANUAL is not set
-+# CONFIG_SPARSEMEM_MANUAL is not set
-+CONFIG_FLATMEM=y
-+CONFIG_FLAT_NODE_MEM_MAP=y
-+# CONFIG_SPARSEMEM_STATIC is not set
-+CONFIG_SPLIT_PTLOCK_CPUS=4
-+# CONFIG_PREEMPT_NONE is not set
-+# CONFIG_PREEMPT_VOLUNTARY is not set
-+CONFIG_PREEMPT=y
-+CONFIG_PREEMPT_BKL=y
-+
-+#
-+# Code maturity level options
-+#
-+CONFIG_EXPERIMENTAL=y
-+CONFIG_BROKEN_ON_SMP=y
-+CONFIG_LOCK_KERNEL=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-+
-+#
-+# General setup
-+#
-+CONFIG_LOCALVERSION=""
-+CONFIG_LOCALVERSION_AUTO=y
-+CONFIG_SWAP=y
-+CONFIG_SYSVIPC=y
-+CONFIG_POSIX_MQUEUE=y
-+CONFIG_BSD_PROCESS_ACCT=y
-+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
-+CONFIG_SYSCTL=y
-+# CONFIG_AUDIT is not set
-+CONFIG_IKCONFIG=y
-+CONFIG_IKCONFIG_PROC=y
-+# CONFIG_RELAY is not set
-+CONFIG_INITRAMFS_SOURCE=""
-+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-+CONFIG_EMBEDDED=y
-+CONFIG_KALLSYMS=y
-+# CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_HOTPLUG=y
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_ELF_CORE=y
-+CONFIG_BASE_FULL=y
-+CONFIG_FUTEX=y
-+CONFIG_EPOLL=y
-+CONFIG_SHMEM=y
-+CONFIG_SLAB=y
-+# CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=0
-+# CONFIG_SLOB is not set
-+CONFIG_OBSOLETE_INTERMODULE=y
-+
-+#
-+# Loadable module support
-+#
-+CONFIG_MODULES=y
-+CONFIG_MODULE_UNLOAD=y
-+CONFIG_MODULE_FORCE_UNLOAD=y
-+CONFIG_MODVERSIONS=y
-+# CONFIG_MODULE_SRCVERSION_ALL is not set
-+CONFIG_KMOD=y
-+
-+#
-+# Block layer
-+#
-+CONFIG_LBD=y
-+# CONFIG_BLK_DEV_IO_TRACE is not set
-+# CONFIG_LSF is not set
-+
-+#
-+# IO Schedulers
-+#
-+CONFIG_IOSCHED_NOOP=y
-+CONFIG_IOSCHED_AS=y
-+CONFIG_IOSCHED_DEADLINE=y
-+CONFIG_IOSCHED_CFQ=y
-+CONFIG_DEFAULT_AS=y
-+# CONFIG_DEFAULT_DEADLINE is not set
-+# CONFIG_DEFAULT_CFQ is not set
-+# CONFIG_DEFAULT_NOOP is not set
-+CONFIG_DEFAULT_IOSCHED="anticipatory"
-+
-+#
-+# Bus options (PCI, PCMCIA, EISA, ISA, TC)
-+#
-+CONFIG_HW_HAS_PCI=y
-+CONFIG_PCI=y
-+CONFIG_MMU=y
-+
-+#
-+# PCCARD (PCMCIA/CardBus) support
-+#
-+# CONFIG_PCCARD is not set
-+
-+#
-+# PCI Hotplug Support
-+#
-+# CONFIG_HOTPLUG_PCI is not set
-+
-+#
-+# Executable file formats
-+#
-+CONFIG_BINFMT_ELF=y
-+# CONFIG_BINFMT_MISC is not set
-+CONFIG_TRAD_SIGNALS=y
-+
-+#
-+# Networking
-+#
-+CONFIG_NET=y
-+
-+#
-+# Networking options
-+#
-+# CONFIG_NETDEBUG is not set
-+CONFIG_PACKET=y
-+CONFIG_PACKET_MMAP=y
-+CONFIG_UNIX=y
-+CONFIG_XFRM=y
-+# CONFIG_XFRM_USER is not set
-+CONFIG_NET_KEY=y
-+CONFIG_INET=y
-+CONFIG_IP_MULTICAST=y
-+CONFIG_IP_ADVANCED_ROUTER=y
-+CONFIG_ASK_IP_FIB_HASH=y
-+# CONFIG_IP_FIB_TRIE is not set
-+CONFIG_IP_FIB_HASH=y
-+CONFIG_IP_MULTIPLE_TABLES=y
-+# CONFIG_IP_ROUTE_FWMARK is not set
-+CONFIG_IP_ROUTE_MULTIPATH=y
-+# CONFIG_IP_ROUTE_MULTIPATH_CACHED is not set
-+CONFIG_IP_ROUTE_VERBOSE=y
-+CONFIG_IP_PNP=y
-+# CONFIG_IP_PNP_DHCP is not set
-+CONFIG_IP_PNP_BOOTP=y
-+# CONFIG_IP_PNP_RARP is not set
-+# CONFIG_NET_IPIP is not set
-+# CONFIG_NET_IPGRE is not set
-+# CONFIG_IP_MROUTE is not set
-+# CONFIG_ARPD is not set
-+CONFIG_SYN_COOKIES=y
-+# CONFIG_INET_AH is not set
-+# CONFIG_INET_ESP is not set
-+# CONFIG_INET_IPCOMP is not set
-+# CONFIG_INET_XFRM_TUNNEL is not set
-+# CONFIG_INET_TUNNEL is not set
-+CONFIG_INET_DIAG=y
-+CONFIG_INET_TCP_DIAG=y
-+# CONFIG_TCP_CONG_ADVANCED is not set
-+CONFIG_TCP_CONG_BIC=y
-+
-+#
-+# IP: Virtual Server Configuration
-+#
-+# CONFIG_IP_VS is not set
-+CONFIG_IPV6=m
-+# CONFIG_IPV6_PRIVACY is not set
-+# CONFIG_IPV6_ROUTER_PREF is not set
-+# CONFIG_INET6_AH is not set
-+# CONFIG_INET6_ESP is not set
-+# CONFIG_INET6_IPCOMP is not set
-+# CONFIG_INET6_XFRM_TUNNEL is not set
-+# CONFIG_INET6_TUNNEL is not set
-+# CONFIG_IPV6_TUNNEL is not set
-+CONFIG_NETFILTER=y
-+# CONFIG_NETFILTER_DEBUG is not set
-+
-+#
-+# Core Netfilter Configuration
-+#
-+# CONFIG_NETFILTER_NETLINK is not set
-+# CONFIG_NF_CONNTRACK is not set
-+# CONFIG_NETFILTER_XTABLES is not set
-+
-+#
-+# IP: Netfilter Configuration
-+#
-+# CONFIG_IP_NF_CONNTRACK is not set
-+# CONFIG_IP_NF_QUEUE is not set
-+
-+#
-+# IPv6: Netfilter Configuration (EXPERIMENTAL)
-+#
-+# CONFIG_IP6_NF_QUEUE is not set
-+
-+#
-+# DCCP Configuration (EXPERIMENTAL)
-+#
-+# CONFIG_IP_DCCP is not set
-+
-+#
-+# SCTP Configuration (EXPERIMENTAL)
-+#
-+CONFIG_IP_SCTP=m
-+# CONFIG_SCTP_DBG_MSG is not set
-+# CONFIG_SCTP_DBG_OBJCNT is not set
-+# CONFIG_SCTP_HMAC_NONE is not set
-+# CONFIG_SCTP_HMAC_SHA1 is not set
-+CONFIG_SCTP_HMAC_MD5=y
-+
-+#
-+# TIPC Configuration (EXPERIMENTAL)
-+#
-+# CONFIG_TIPC is not set
-+# CONFIG_ATM is not set
-+# CONFIG_BRIDGE is not set
-+# CONFIG_VLAN_8021Q is not set
-+# CONFIG_DECNET is not set
-+# CONFIG_LLC2 is not set
-+# CONFIG_IPX is not set
-+# CONFIG_ATALK is not set
-+# CONFIG_X25 is not set
-+# CONFIG_LAPB is not set
-+# CONFIG_NET_DIVERT is not set
-+# CONFIG_ECONET is not set
-+# CONFIG_WAN_ROUTER is not set
-+
-+#
-+# QoS and/or fair queueing
-+#
-+# CONFIG_NET_SCHED is not set
-+
-+#
-+# Network testing
-+#
-+# CONFIG_NET_PKTGEN is not set
-+# CONFIG_HAMRADIO is not set
-+# CONFIG_IRDA is not set
-+# CONFIG_BT is not set
-+# CONFIG_IEEE80211 is not set
-+
-+#
-+# Device Drivers
-+#
-+
-+#
-+# Generic Driver Options
-+#
-+CONFIG_STANDALONE=y
-+CONFIG_PREVENT_FIRMWARE_BUILD=y
-+# CONFIG_FW_LOADER is not set
-+
-+#
-+# Connector - unified userspace <-> kernelspace linker
-+#
-+# CONFIG_CONNECTOR is not set
-+
-+#
-+# Memory Technology Devices (MTD)
-+#
-+CONFIG_MTD=y
-+# CONFIG_MTD_DEBUG is not set
-+# CONFIG_MTD_CONCAT is not set
-+CONFIG_MTD_PARTITIONS=y
-+# CONFIG_MTD_REDBOOT_PARTS is not set
-+CONFIG_MTD_CMDLINE_PARTS=y
-+
-+#
-+# User Modules And Translation Layers
-+#
-+CONFIG_MTD_CHAR=y
-+CONFIG_MTD_BLOCK=y
-+# CONFIG_FTL is not set
-+# CONFIG_NFTL is not set
-+# CONFIG_INFTL is not set
-+# CONFIG_RFD_FTL is not set
-+
-+#
-+# RAM/ROM/Flash chip drivers
-+#
-+CONFIG_MTD_CFI=y
-+# CONFIG_MTD_JEDECPROBE is not set
-+CONFIG_MTD_GEN_PROBE=y
-+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
-+CONFIG_MTD_MAP_BANK_WIDTH_1=y
-+CONFIG_MTD_MAP_BANK_WIDTH_2=y
-+CONFIG_MTD_MAP_BANK_WIDTH_4=y
-+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-+CONFIG_MTD_CFI_I1=y
-+CONFIG_MTD_CFI_I2=y
-+# CONFIG_MTD_CFI_I4 is not set
-+# CONFIG_MTD_CFI_I8 is not set
-+# CONFIG_MTD_CFI_INTELEXT is not set
-+CONFIG_MTD_CFI_AMDSTD=y
-+# CONFIG_MTD_CFI_STAA is not set
-+CONFIG_MTD_CFI_UTIL=y
-+# CONFIG_MTD_RAM is not set
-+# CONFIG_MTD_ROM is not set
-+# CONFIG_MTD_ABSENT is not set
-+# CONFIG_MTD_OBSOLETE_CHIPS is not set
-+
-+#
-+# Mapping drivers for chip access
-+#
-+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-+CONFIG_MTD_PHYSMAP=y
-+CONFIG_MTD_PHYSMAP_START=0x1e000000
-+CONFIG_MTD_PHYSMAP_LEN=0x02000000
-+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
-+# CONFIG_MTD_PLATRAM is not set
-+
-+#
-+# Self-contained MTD device drivers
-+#
-+# CONFIG_MTD_PMC551 is not set
-+# CONFIG_MTD_SLRAM is not set
-+# CONFIG_MTD_PHRAM is not set
-+# CONFIG_MTD_MTDRAM is not set
-+# CONFIG_MTD_BLOCK2MTD is not set
-+
-+#
-+# Disk-On-Chip Device Drivers
-+#
-+# CONFIG_MTD_DOC2000 is not set
-+# CONFIG_MTD_DOC2001 is not set
-+# CONFIG_MTD_DOC2001PLUS is not set
-+
-+#
-+# NAND Flash Device Drivers
-+#
-+# CONFIG_MTD_NAND is not set
-+
-+#
-+# OneNAND Flash Device Drivers
-+#
-+# CONFIG_MTD_ONENAND is not set
-+
-+#
-+# Parallel port support
-+#
-+# CONFIG_PARPORT is not set
-+
-+#
-+# Plug and Play support
-+#
-+
-+#
-+# Block devices
-+#
-+# CONFIG_BLK_CPQ_DA is not set
-+# CONFIG_BLK_CPQ_CISS_DA is not set
-+# CONFIG_BLK_DEV_DAC960 is not set
-+# CONFIG_BLK_DEV_UMEM is not set
-+# CONFIG_BLK_DEV_COW_COMMON is not set
-+CONFIG_BLK_DEV_LOOP=m
-+CONFIG_BLK_DEV_CRYPTOLOOP=m
-+# CONFIG_BLK_DEV_NBD is not set
-+# CONFIG_BLK_DEV_SX8 is not set
-+# CONFIG_BLK_DEV_RAM is not set
-+# CONFIG_BLK_DEV_INITRD is not set
-+# CONFIG_CDROM_PKTCDVD is not set
-+# CONFIG_ATA_OVER_ETH is not set
-+
-+#
-+# ATA/ATAPI/MFM/RLL support
-+#
-+# CONFIG_IDE is not set
-+
-+#
-+# SCSI device support
-+#
-+# CONFIG_RAID_ATTRS is not set
-+CONFIG_SCSI=m
-+# CONFIG_SCSI_PROC_FS is not set
-+
-+#
-+# SCSI support type (disk, tape, CD-ROM)
-+#
-+CONFIG_BLK_DEV_SD=m
-+# CONFIG_CHR_DEV_ST is not set
-+# CONFIG_CHR_DEV_OSST is not set
-+# CONFIG_BLK_DEV_SR is not set
-+CONFIG_CHR_DEV_SG=m
-+# CONFIG_CHR_DEV_SCH is not set
-+
-+#
-+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-+#
-+# CONFIG_SCSI_MULTI_LUN is not set
-+# CONFIG_SCSI_CONSTANTS is not set
-+# CONFIG_SCSI_LOGGING is not set
-+
-+#
-+# SCSI Transport Attributes
-+#
-+# CONFIG_SCSI_SPI_ATTRS is not set
-+# CONFIG_SCSI_FC_ATTRS is not set
-+# CONFIG_SCSI_ISCSI_ATTRS is not set
-+# CONFIG_SCSI_SAS_ATTRS is not set
-+
-+#
-+# SCSI low-level drivers
-+#
-+# CONFIG_ISCSI_TCP is not set
-+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
-+# CONFIG_SCSI_3W_9XXX is not set
-+# CONFIG_SCSI_ACARD is not set
-+# CONFIG_SCSI_AACRAID is not set
-+# CONFIG_SCSI_AIC7XXX is not set
-+# CONFIG_SCSI_AIC7XXX_OLD is not set
-+# CONFIG_SCSI_AIC79XX is not set
-+# CONFIG_SCSI_DPT_I2O is not set
-+# CONFIG_MEGARAID_NEWGEN is not set
-+# CONFIG_MEGARAID_LEGACY is not set
-+# CONFIG_MEGARAID_SAS is not set
-+# CONFIG_SCSI_SATA is not set
-+# CONFIG_SCSI_DMX3191D is not set
-+# CONFIG_SCSI_FUTURE_DOMAIN is not set
-+# CONFIG_SCSI_IPS is not set
-+# CONFIG_SCSI_INITIO is not set
-+# CONFIG_SCSI_INIA100 is not set
-+# CONFIG_SCSI_SYM53C8XX_2 is not set
-+# CONFIG_SCSI_IPR is not set
-+# CONFIG_SCSI_QLOGIC_1280 is not set
-+# CONFIG_SCSI_QLA_FC is not set
-+# CONFIG_SCSI_LPFC is not set
-+# CONFIG_SCSI_DC395x is not set
-+# CONFIG_SCSI_DC390T is not set
-+# CONFIG_SCSI_NSP32 is not set
-+# CONFIG_SCSI_DEBUG is not set
-+
-+#
-+# Multi-device support (RAID and LVM)
-+#
-+# CONFIG_MD is not set
-+
-+#
-+# Fusion MPT device support
-+#
-+# CONFIG_FUSION is not set
-+# CONFIG_FUSION_SPI is not set
-+# CONFIG_FUSION_FC is not set
-+# CONFIG_FUSION_SAS is not set
-+
-+#
-+# IEEE 1394 (FireWire) support
-+#
-+# CONFIG_IEEE1394 is not set
-+
-+#
-+# I2O device support
-+#
-+# CONFIG_I2O is not set
-+
-+#
-+# Network device support
-+#
-+CONFIG_NETDEVICES=y
-+# CONFIG_DUMMY is not set
-+# CONFIG_BONDING is not set
-+# CONFIG_EQUALIZER is not set
-+CONFIG_TUN=m
-+
-+#
-+# ARCnet devices
-+#
-+# CONFIG_ARCNET is not set
-+
-+#
-+# PHY device support
-+#
-+# CONFIG_PHYLIB is not set
-+
-+#
-+# Ethernet (10 or 100Mbit)
-+#
-+CONFIG_NET_ETHERNET=y
-+CONFIG_MII=y
-+# CONFIG_HAPPYMEAL is not set
-+# CONFIG_SUNGEM is not set
-+# CONFIG_CASSINI is not set
-+# CONFIG_NET_VENDOR_3COM is not set
-+# CONFIG_DM9000 is not set
-+
-+#
-+# Tulip family network device support
-+#
-+# CONFIG_NET_TULIP is not set
-+# CONFIG_HP100 is not set
-+CONFIG_NET_PCI=y
-+# CONFIG_PCNET32 is not set
-+# CONFIG_AMD8111_ETH is not set
-+# CONFIG_ADAPTEC_STARFIRE is not set
-+# CONFIG_B44 is not set
-+# CONFIG_FORCEDETH is not set
-+# CONFIG_DGRS is not set
-+# CONFIG_EEPRO100 is not set
-+# CONFIG_E100 is not set
-+# CONFIG_FEALNX is not set
-+CONFIG_NATSEMI=y
-+# CONFIG_NE2K_PCI is not set
-+# CONFIG_8139CP is not set
-+# CONFIG_8139TOO is not set
-+# CONFIG_SIS900 is not set
-+# CONFIG_EPIC100 is not set
-+# CONFIG_SUNDANCE is not set
-+# CONFIG_TLAN is not set
-+# CONFIG_VIA_RHINE is not set
-+# CONFIG_LAN_SAA9730 is not set
-+
-+#
-+# Ethernet (1000 Mbit)
-+#
-+# CONFIG_ACENIC is not set
-+# CONFIG_DL2K is not set
-+# CONFIG_E1000 is not set
-+# CONFIG_NS83820 is not set
-+# CONFIG_HAMACHI is not set
-+# CONFIG_YELLOWFIN is not set
-+# CONFIG_R8169 is not set
-+# CONFIG_SIS190 is not set
-+# CONFIG_SKGE is not set
-+# CONFIG_SKY2 is not set
-+# CONFIG_SK98LIN is not set
-+# CONFIG_VIA_VELOCITY is not set
-+# CONFIG_TIGON3 is not set
-+# CONFIG_BNX2 is not set
-+
-+#
-+# Ethernet (10000 Mbit)
-+#
-+# CONFIG_CHELSIO_T1 is not set
-+# CONFIG_IXGB is not set
-+# CONFIG_S2IO is not set
-+
-+#
-+# Token Ring devices
-+#
-+# CONFIG_TR is not set
-+
-+#
-+# Wireless LAN (non-hamradio)
-+#
-+# CONFIG_NET_RADIO is not set
-+
-+#
-+# Wan interfaces
-+#
-+# CONFIG_WAN is not set
-+# CONFIG_FDDI is not set
-+# CONFIG_HIPPI is not set
-+CONFIG_PPP=m
-+# CONFIG_PPP_MULTILINK is not set
-+# CONFIG_PPP_FILTER is not set
-+CONFIG_PPP_ASYNC=m
-+CONFIG_PPP_SYNC_TTY=m
-+CONFIG_PPP_DEFLATE=m
-+# CONFIG_PPP_BSDCOMP is not set
-+# CONFIG_PPP_MPPE is not set
-+# CONFIG_PPPOE is not set
-+# CONFIG_SLIP is not set
-+# CONFIG_NET_FC is not set
-+# CONFIG_SHAPER is not set
-+# CONFIG_NETCONSOLE is not set
-+# CONFIG_NETPOLL is not set
-+# CONFIG_NET_POLL_CONTROLLER is not set
-+
-+#
-+# ISDN subsystem
-+#
-+# CONFIG_ISDN is not set
-+
-+#
-+# Telephony Support
-+#
-+# CONFIG_PHONE is not set
-+
-+#
-+# Input device support
-+#
-+CONFIG_INPUT=y
-+
-+#
-+# Userland interfaces
-+#
-+# CONFIG_INPUT_MOUSEDEV is not set
-+# CONFIG_INPUT_JOYDEV is not set
-+# CONFIG_INPUT_TSDEV is not set
-+CONFIG_INPUT_EVDEV=m
-+# CONFIG_INPUT_EVBUG is not set
-+
-+#
-+# Input Device Drivers
-+#
-+# CONFIG_INPUT_KEYBOARD is not set
-+# CONFIG_INPUT_MOUSE is not set
-+# CONFIG_INPUT_JOYSTICK is not set
-+# CONFIG_INPUT_TOUCHSCREEN is not set
-+# CONFIG_INPUT_MISC is not set
-+
-+#
-+# Hardware I/O ports
-+#
-+# CONFIG_SERIO is not set
-+# CONFIG_GAMEPORT is not set
-+
-+#
-+# Character devices
-+#
-+# CONFIG_VT is not set
-+# CONFIG_SERIAL_NONSTANDARD is not set
-+
-+#
-+# Serial drivers
-+#
-+CONFIG_SERIAL_8250=y
-+CONFIG_SERIAL_8250_CONSOLE=y
-+CONFIG_SERIAL_8250_PCI=y
-+CONFIG_SERIAL_8250_NR_UARTS=4
-+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-+# CONFIG_SERIAL_8250_EXTENDED is not set
-+
-+#
-+# Non-8250 serial port support
-+#
-+CONFIG_SERIAL_CORE=y
-+CONFIG_SERIAL_CORE_CONSOLE=y
-+# CONFIG_SERIAL_JSM is not set
-+CONFIG_UNIX98_PTYS=y
-+CONFIG_LEGACY_PTYS=y
-+CONFIG_LEGACY_PTY_COUNT=256
-+
-+#
-+# IPMI
-+#
-+# CONFIG_IPMI_HANDLER is not set
-+
-+#
-+# Watchdog Cards
-+#
-+# CONFIG_WATCHDOG is not set
-+CONFIG_RTC=m
-+CONFIG_GEN_RTC=m
-+CONFIG_GEN_RTC_X=y
-+# CONFIG_DTLK is not set
-+# CONFIG_R3964 is not set
-+# CONFIG_APPLICOM is not set
-+
-+#
-+# Ftape, the floppy tape device driver
-+#
-+# CONFIG_DRM is not set
-+# CONFIG_RAW_DRIVER is not set
-+
-+#
-+# TPM devices
-+#
-+# CONFIG_TCG_TPM is not set
-+# CONFIG_TELCLOCK is not set
-+
-+#
-+# I2C support
-+#
-+CONFIG_I2C=y
-+CONFIG_I2C_CHARDEV=y
-+
-+#
-+# I2C Algorithms
-+#
-+# CONFIG_I2C_ALGOBIT is not set
-+# CONFIG_I2C_ALGOPCF is not set
-+# CONFIG_I2C_ALGOPCA is not set
-+
-+#
-+# I2C Hardware Bus support
-+#
-+# CONFIG_I2C_ALI1535 is not set
-+# CONFIG_I2C_ALI1563 is not set
-+# CONFIG_I2C_ALI15X3 is not set
-+# CONFIG_I2C_AMD756 is not set
-+# CONFIG_I2C_AMD8111 is not set
-+# CONFIG_I2C_I801 is not set
-+# CONFIG_I2C_I810 is not set
-+# CONFIG_I2C_PIIX4 is not set
-+# CONFIG_I2C_NFORCE2 is not set
-+# CONFIG_I2C_PARPORT_LIGHT is not set
-+# CONFIG_I2C_PROSAVAGE is not set
-+# CONFIG_I2C_SAVAGE4 is not set
-+# CONFIG_I2C_SIS5595 is not set
-+# CONFIG_I2C_SIS630 is not set
-+# CONFIG_I2C_SIS96X is not set
-+# CONFIG_I2C_STUB is not set
-+# CONFIG_I2C_VIA is not set
-+# CONFIG_I2C_VIAPRO is not set
-+# CONFIG_I2C_VOODOO3 is not set
-+# CONFIG_I2C_PCA_ISA is not set
-+
-+#
-+# Miscellaneous I2C Chip support
-+#
-+# CONFIG_SENSORS_DS1337 is not set
-+# CONFIG_SENSORS_DS1374 is not set
-+# CONFIG_SENSORS_EEPROM is not set
-+# CONFIG_SENSORS_PCF8574 is not set
-+# CONFIG_SENSORS_PCA9539 is not set
-+# CONFIG_SENSORS_PCF8591 is not set
-+# CONFIG_SENSORS_MAX6875 is not set
-+CONFIG_I2C_DEBUG_CORE=y
-+# CONFIG_I2C_DEBUG_ALGO is not set
-+CONFIG_I2C_DEBUG_BUS=y
-+# CONFIG_I2C_DEBUG_CHIP is not set
-+
-+#
-+# SPI support
-+#
-+# CONFIG_SPI is not set
-+# CONFIG_SPI_MASTER is not set
-+
-+#
-+# Dallas's 1-wire bus
-+#
-+# CONFIG_W1 is not set
-+
-+#
-+# Hardware Monitoring support
-+#
-+CONFIG_HWMON=y
-+# CONFIG_HWMON_VID is not set
-+# CONFIG_SENSORS_ADM1021 is not set
-+# CONFIG_SENSORS_ADM1025 is not set
-+# CONFIG_SENSORS_ADM1026 is not set
-+# CONFIG_SENSORS_ADM1031 is not set
-+# CONFIG_SENSORS_ADM9240 is not set
-+# CONFIG_SENSORS_ASB100 is not set
-+# CONFIG_SENSORS_ATXP1 is not set
-+# CONFIG_SENSORS_DS1621 is not set
-+# CONFIG_SENSORS_F71805F is not set
-+# CONFIG_SENSORS_FSCHER is not set
-+# CONFIG_SENSORS_FSCPOS is not set
-+# CONFIG_SENSORS_GL518SM is not set
-+# CONFIG_SENSORS_GL520SM is not set
-+# CONFIG_SENSORS_IT87 is not set
-+# CONFIG_SENSORS_LM63 is not set
-+# CONFIG_SENSORS_LM75 is not set
-+# CONFIG_SENSORS_LM77 is not set
-+# CONFIG_SENSORS_LM78 is not set
-+# CONFIG_SENSORS_LM80 is not set
-+# CONFIG_SENSORS_LM83 is not set
-+# CONFIG_SENSORS_LM85 is not set
-+# CONFIG_SENSORS_LM87 is not set
-+# CONFIG_SENSORS_LM90 is not set
-+# CONFIG_SENSORS_LM92 is not set
-+# CONFIG_SENSORS_MAX1619 is not set
-+# CONFIG_SENSORS_PC87360 is not set
-+# CONFIG_SENSORS_SIS5595 is not set
-+# CONFIG_SENSORS_SMSC47M1 is not set
-+# CONFIG_SENSORS_SMSC47B397 is not set
-+# CONFIG_SENSORS_VIA686A is not set
-+# CONFIG_SENSORS_VT8231 is not set
-+# CONFIG_SENSORS_W83781D is not set
-+# CONFIG_SENSORS_W83792D is not set
-+# CONFIG_SENSORS_W83L785TS is not set
-+# CONFIG_SENSORS_W83627HF is not set
-+# CONFIG_SENSORS_W83627EHF is not set
-+# CONFIG_HWMON_DEBUG_CHIP is not set
-+
-+#
-+# Misc devices
-+#
-+
-+#
-+# Multimedia devices
-+#
-+# CONFIG_VIDEO_DEV is not set
-+CONFIG_VIDEO_V4L2=y
-+
-+#
-+# Digital Video Broadcasting Devices
-+#
-+# CONFIG_DVB is not set
-+
-+#
-+# Graphics support
-+#
-+# CONFIG_FB is not set
-+
-+#
-+# Sound
-+#
-+# CONFIG_SOUND is not set
-+
-+#
-+# USB support
-+#
-+CONFIG_USB_ARCH_HAS_HCD=y
-+CONFIG_USB_ARCH_HAS_OHCI=y
-+CONFIG_USB_ARCH_HAS_EHCI=y
-+# CONFIG_USB is not set
-+
-+#
-+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-+#
-+
-+#
-+# USB Gadget Support
-+#
-+# CONFIG_USB_GADGET is not set
-+
-+#
-+# MMC/SD Card support
-+#
-+# CONFIG_MMC is not set
-+
-+#
-+# LED devices
-+#
-+# CONFIG_NEW_LEDS is not set
-+
-+#
-+# LED drivers
-+#
-+
-+#
-+# LED Triggers
-+#
-+
-+#
-+# InfiniBand support
-+#
-+# CONFIG_INFINIBAND is not set
-+
-+#
-+# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
-+#
-+
-+#
-+# Real Time Clock
-+#
-+# CONFIG_RTC_CLASS is not set
-+
-+#
-+# File systems
-+#
-+CONFIG_EXT2_FS=y
-+CONFIG_EXT2_FS_XATTR=y
-+CONFIG_EXT2_FS_POSIX_ACL=y
-+CONFIG_EXT2_FS_SECURITY=y
-+# CONFIG_EXT2_FS_XIP is not set
-+CONFIG_EXT3_FS=m
-+CONFIG_EXT3_FS_XATTR=y
-+# CONFIG_EXT3_FS_POSIX_ACL is not set
-+# CONFIG_EXT3_FS_SECURITY is not set
-+CONFIG_JBD=m
-+# CONFIG_JBD_DEBUG is not set
-+CONFIG_FS_MBCACHE=y
-+# CONFIG_REISERFS_FS is not set
-+# CONFIG_JFS_FS is not set
-+CONFIG_FS_POSIX_ACL=y
-+CONFIG_XFS_FS=m
-+CONFIG_XFS_EXPORT=y
-+# CONFIG_XFS_QUOTA is not set
-+# CONFIG_XFS_SECURITY is not set
-+# CONFIG_XFS_POSIX_ACL is not set
-+# CONFIG_XFS_RT is not set
-+# CONFIG_OCFS2_FS is not set
-+# CONFIG_MINIX_FS is not set
-+# CONFIG_ROMFS_FS is not set
-+CONFIG_INOTIFY=y
-+# CONFIG_QUOTA is not set
-+# CONFIG_DNOTIFY is not set
-+# CONFIG_AUTOFS_FS is not set
-+CONFIG_AUTOFS4_FS=m
-+# CONFIG_FUSE_FS is not set
-+
-+#
-+# CD-ROM/DVD Filesystems
-+#
-+# CONFIG_ISO9660_FS is not set
-+# CONFIG_UDF_FS is not set
-+
-+#
-+# DOS/FAT/NT Filesystems
-+#
-+CONFIG_FAT_FS=y
-+CONFIG_MSDOS_FS=y
-+CONFIG_VFAT_FS=y
-+CONFIG_FAT_DEFAULT_CODEPAGE=437
-+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-+CONFIG_NTFS_FS=m
-+# CONFIG_NTFS_DEBUG is not set
-+# CONFIG_NTFS_RW is not set
-+
-+#
-+# Pseudo filesystems
-+#
-+CONFIG_PROC_FS=y
-+CONFIG_PROC_KCORE=y
-+CONFIG_SYSFS=y
-+CONFIG_TMPFS=y
-+# CONFIG_HUGETLB_PAGE is not set
-+CONFIG_RAMFS=y
-+# CONFIG_CONFIGFS_FS is not set
-+
-+#
-+# Miscellaneous filesystems
-+#
-+# CONFIG_ADFS_FS is not set
-+# CONFIG_AFFS_FS is not set
-+# CONFIG_HFS_FS is not set
-+# CONFIG_HFSPLUS_FS is not set
-+# CONFIG_BEFS_FS is not set
-+# CONFIG_BFS_FS is not set
-+# CONFIG_EFS_FS is not set
-+# CONFIG_JFFS_FS is not set
-+CONFIG_JFFS2_FS=y
-+CONFIG_JFFS2_FS_DEBUG=0
-+CONFIG_JFFS2_FS_WRITEBUFFER=y
-+# CONFIG_JFFS2_SUMMARY is not set
-+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-+CONFIG_JFFS2_ZLIB=y
-+CONFIG_JFFS2_RTIME=y
-+# CONFIG_JFFS2_RUBIN is not set
-+# CONFIG_JFFS2_CMODE_NONE is not set
-+CONFIG_JFFS2_CMODE_PRIORITY=y
-+# CONFIG_JFFS2_CMODE_SIZE is not set
-+CONFIG_CRAMFS=y
-+# CONFIG_VXFS_FS is not set
-+# CONFIG_HPFS_FS is not set
-+# CONFIG_QNX4FS_FS is not set
-+# CONFIG_SYSV_FS is not set
-+# CONFIG_UFS_FS is not set
-+
-+#
-+# Network File Systems
-+#
-+CONFIG_NFS_FS=y
-+CONFIG_NFS_V3=y
-+# CONFIG_NFS_V3_ACL is not set
-+CONFIG_NFS_V4=y
-+CONFIG_NFS_DIRECTIO=y
-+CONFIG_NFSD=m
-+CONFIG_NFSD_V3=y
-+# CONFIG_NFSD_V3_ACL is not set
-+# CONFIG_NFSD_V4 is not set
-+CONFIG_NFSD_TCP=y
-+CONFIG_ROOT_NFS=y
-+CONFIG_LOCKD=y
-+CONFIG_LOCKD_V4=y
-+CONFIG_EXPORTFS=m
-+CONFIG_NFS_COMMON=y
-+CONFIG_SUNRPC=y
-+CONFIG_SUNRPC_GSS=y
-+CONFIG_RPCSEC_GSS_KRB5=y
-+# CONFIG_RPCSEC_GSS_SPKM3 is not set
-+CONFIG_SMB_FS=m
-+# CONFIG_SMB_NLS_DEFAULT is not set
-+# CONFIG_CIFS is not set
-+# CONFIG_NCP_FS is not set
-+# CONFIG_CODA_FS is not set
-+# CONFIG_AFS_FS is not set
-+# CONFIG_9P_FS is not set
-+
-+#
-+# Partition Types
-+#
-+# CONFIG_PARTITION_ADVANCED is not set
-+CONFIG_MSDOS_PARTITION=y
-+
-+#
-+# Native Language Support
-+#
-+CONFIG_NLS=y
-+CONFIG_NLS_DEFAULT=""
-+CONFIG_NLS_CODEPAGE_437=m
-+# CONFIG_NLS_CODEPAGE_737 is not set
-+# CONFIG_NLS_CODEPAGE_775 is not set
-+# CONFIG_NLS_CODEPAGE_850 is not set
-+# CONFIG_NLS_CODEPAGE_852 is not set
-+# CONFIG_NLS_CODEPAGE_855 is not set
-+# CONFIG_NLS_CODEPAGE_857 is not set
-+# CONFIG_NLS_CODEPAGE_860 is not set
-+# CONFIG_NLS_CODEPAGE_861 is not set
-+# CONFIG_NLS_CODEPAGE_862 is not set
-+# CONFIG_NLS_CODEPAGE_863 is not set
-+# CONFIG_NLS_CODEPAGE_864 is not set
-+# CONFIG_NLS_CODEPAGE_865 is not set
-+# CONFIG_NLS_CODEPAGE_866 is not set
-+# CONFIG_NLS_CODEPAGE_869 is not set
-+# CONFIG_NLS_CODEPAGE_936 is not set
-+# CONFIG_NLS_CODEPAGE_950 is not set
-+# CONFIG_NLS_CODEPAGE_932 is not set
-+# CONFIG_NLS_CODEPAGE_949 is not set
-+# CONFIG_NLS_CODEPAGE_874 is not set
-+# CONFIG_NLS_ISO8859_8 is not set
-+# CONFIG_NLS_CODEPAGE_1250 is not set
-+# CONFIG_NLS_CODEPAGE_1251 is not set
-+CONFIG_NLS_ASCII=m
-+CONFIG_NLS_ISO8859_1=m
-+# CONFIG_NLS_ISO8859_2 is not set
-+# CONFIG_NLS_ISO8859_3 is not set
-+# CONFIG_NLS_ISO8859_4 is not set
-+# CONFIG_NLS_ISO8859_5 is not set
-+# CONFIG_NLS_ISO8859_6 is not set
-+# CONFIG_NLS_ISO8859_7 is not set
-+# CONFIG_NLS_ISO8859_9 is not set
-+# CONFIG_NLS_ISO8859_13 is not set
-+# CONFIG_NLS_ISO8859_14 is not set
-+# CONFIG_NLS_ISO8859_15 is not set
-+# CONFIG_NLS_KOI8_R is not set
-+# CONFIG_NLS_KOI8_U is not set
-+CONFIG_NLS_UTF8=m
-+
-+#
-+# Profiling support
-+#
-+# CONFIG_PROFILING is not set
-+
-+#
-+# Kernel hacking
-+#
-+# CONFIG_PRINTK_TIME is not set
-+# CONFIG_MAGIC_SYSRQ is not set
-+# CONFIG_DEBUG_KERNEL is not set
-+CONFIG_LOG_BUF_SHIFT=14
-+# CONFIG_DEBUG_FS is not set
-+CONFIG_CROSSCOMPILE=y
-+CONFIG_CMDLINE="console=ttyS0,115200 mem=192m ip=bootp root=/dev/nfs rw"
-+
-+#
-+# Security options
-+#
-+# CONFIG_KEYS is not set
-+# CONFIG_SECURITY is not set
-+
-+#
-+# Cryptographic options
-+#
-+CONFIG_CRYPTO=y
-+CONFIG_CRYPTO_HMAC=y
-+# CONFIG_CRYPTO_NULL is not set
-+# CONFIG_CRYPTO_MD4 is not set
-+CONFIG_CRYPTO_MD5=y
-+# CONFIG_CRYPTO_SHA1 is not set
-+# CONFIG_CRYPTO_SHA256 is not set
-+# CONFIG_CRYPTO_SHA512 is not set
-+# CONFIG_CRYPTO_WP512 is not set
-+# CONFIG_CRYPTO_TGR192 is not set
-+CONFIG_CRYPTO_DES=y
-+# CONFIG_CRYPTO_BLOWFISH is not set
-+# CONFIG_CRYPTO_TWOFISH is not set
-+# CONFIG_CRYPTO_SERPENT is not set
-+# CONFIG_CRYPTO_AES is not set
-+# CONFIG_CRYPTO_CAST5 is not set
-+# CONFIG_CRYPTO_CAST6 is not set
-+# CONFIG_CRYPTO_TEA is not set
-+# CONFIG_CRYPTO_ARC4 is not set
-+# CONFIG_CRYPTO_KHAZAD is not set
-+# CONFIG_CRYPTO_ANUBIS is not set
-+# CONFIG_CRYPTO_DEFLATE is not set
-+# CONFIG_CRYPTO_MICHAEL_MIC is not set
-+# CONFIG_CRYPTO_CRC32C is not set
-+# CONFIG_CRYPTO_TEST is not set
-+
-+#
-+# Hardware crypto devices
-+#
-+
-+#
-+# Library routines
-+#
-+CONFIG_CRC_CCITT=m
-+# CONFIG_CRC16 is not set
-+CONFIG_CRC32=y
-+# CONFIG_LIBCRC32C is not set
-+CONFIG_ZLIB_INFLATE=y
-+CONFIG_ZLIB_DEFLATE=y
-diff -Naur linux-2.6.17.orig/arch/mips/configs/ev64120_defconfig linux-2.6.17/arch/mips/configs/ev64120_defconfig
---- linux-2.6.17.orig/arch/mips/configs/ev64120_defconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/configs/ev64120_defconfig	2006-06-19 18:16:13.000000000 -0700
-@@ -41,8 +41,6 @@
- # CONFIG_MIPS_XXS1500 is not set
- # CONFIG_PNX8550_V2PCI is not set
- # CONFIG_PNX8550_JBS is not set
--# CONFIG_DDB5074 is not set
--# CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
- # CONFIG_MACH_VR41XX is not set
- # CONFIG_PMC_YOSEMITE is not set
-@@ -68,6 +66,7 @@
- CONFIG_GENERIC_FIND_NEXT_BIT=y
- CONFIG_GENERIC_HWEIGHT=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
- CONFIG_DMA_NONCOHERENT=y
- CONFIG_DMA_NEED_PCI_MAP_STATE=y
- CONFIG_CPU_BIG_ENDIAN=y
-diff -Naur linux-2.6.17.orig/arch/mips/configs/ev96100_defconfig linux-2.6.17/arch/mips/configs/ev96100_defconfig
---- linux-2.6.17.orig/arch/mips/configs/ev96100_defconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/configs/ev96100_defconfig	2006-06-19 18:16:13.000000000 -0700
-@@ -41,8 +41,6 @@
- # CONFIG_MIPS_XXS1500 is not set
- # CONFIG_PNX8550_V2PCI is not set
- # CONFIG_PNX8550_JBS is not set
--# CONFIG_DDB5074 is not set
--# CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
- # CONFIG_MACH_VR41XX is not set
- # CONFIG_PMC_YOSEMITE is not set
-@@ -67,6 +65,7 @@
- CONFIG_GENERIC_FIND_NEXT_BIT=y
- CONFIG_GENERIC_HWEIGHT=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
- CONFIG_DMA_NONCOHERENT=y
- CONFIG_DMA_NEED_PCI_MAP_STATE=y
- CONFIG_CPU_BIG_ENDIAN=y
-diff -Naur linux-2.6.17.orig/arch/mips/configs/excite_defconfig linux-2.6.17/arch/mips/configs/excite_defconfig
---- linux-2.6.17.orig/arch/mips/configs/excite_defconfig	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/arch/mips/configs/excite_defconfig	2006-06-19 18:16:13.000000000 -0700
-@@ -0,0 +1,1211 @@
-+#
-+# Automatically generated make config: don't edit
-+# Linux kernel version: 2.6.16-rc4
-+# Thu Feb 23 13:15:27 2006
-+#
-+CONFIG_MIPS=y
-+
-+#
-+# Machine selection
-+#
-+# CONFIG_MIPS_MTX1 is not set
-+# CONFIG_MIPS_BOSPORUS is not set
-+# CONFIG_MIPS_PB1000 is not set
-+# CONFIG_MIPS_PB1100 is not set
-+# CONFIG_MIPS_PB1500 is not set
-+# CONFIG_MIPS_PB1550 is not set
-+# CONFIG_MIPS_PB1200 is not set
-+# CONFIG_MIPS_DB1000 is not set
-+# CONFIG_MIPS_DB1100 is not set
-+# CONFIG_MIPS_DB1500 is not set
-+# CONFIG_MIPS_DB1550 is not set
-+# CONFIG_MIPS_DB1200 is not set
-+# CONFIG_MIPS_MIRAGE is not set
-+# CONFIG_MIPS_COBALT is not set
-+# CONFIG_MACH_DECSTATION is not set
-+# CONFIG_MIPS_EV64120 is not set
-+# CONFIG_MIPS_EV96100 is not set
-+# CONFIG_MIPS_IVR is not set
-+# CONFIG_MIPS_ITE8172 is not set
-+# CONFIG_MACH_JAZZ is not set
-+# CONFIG_LASAT is not set
-+# CONFIG_MIPS_ATLAS is not set
-+# CONFIG_MIPS_MALTA is not set
-+# CONFIG_MIPS_SEAD is not set
-+# CONFIG_MIPS_SIM is not set
-+# CONFIG_MOMENCO_JAGUAR_ATX is not set
-+# CONFIG_MOMENCO_OCELOT is not set
-+# CONFIG_MOMENCO_OCELOT_3 is not set
-+# CONFIG_MOMENCO_OCELOT_C is not set
-+# CONFIG_MOMENCO_OCELOT_G is not set
-+# CONFIG_MIPS_XXS1500 is not set
-+# CONFIG_PNX8550_V2PCI is not set
-+# CONFIG_PNX8550_JBS is not set
-+CONFIG_BASLER_EXCITE=y
-+# CONFIG_BASLER_EXCITE_PROTOTYPE is not set
-+# CONFIG_DDB5074 is not set
-+# CONFIG_DDB5476 is not set
-+# CONFIG_DDB5477 is not set
-+# CONFIG_MACH_VR41XX is not set
-+# CONFIG_PMC_YOSEMITE is not set
-+# CONFIG_QEMU is not set
-+# CONFIG_SGI_IP22 is not set
-+# CONFIG_SGI_IP27 is not set
-+# CONFIG_SGI_IP32 is not set
-+# CONFIG_SIBYTE_BIGSUR is not set
-+# CONFIG_SIBYTE_SWARM is not set
-+# CONFIG_SIBYTE_SENTOSA is not set
-+# CONFIG_SIBYTE_RHONE is not set
-+# CONFIG_SIBYTE_CARMEL is not set
-+# CONFIG_SIBYTE_PTSWARM is not set
-+# CONFIG_SIBYTE_LITTLESUR is not set
-+# CONFIG_SIBYTE_CRHINE is not set
-+# CONFIG_SIBYTE_CRHONE is not set
-+# CONFIG_SNI_RM200_PCI is not set
-+# CONFIG_TOSHIBA_JMR3927 is not set
-+# CONFIG_TOSHIBA_RBTX4927 is not set
-+# CONFIG_TOSHIBA_RBTX4938 is not set
-+CONFIG_RWSEM_GENERIC_SPINLOCK=y
-+CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_DMA_COHERENT=y
-+CONFIG_SERIAL_RM9000=y
-+CONFIG_CPU_BIG_ENDIAN=y
-+# CONFIG_CPU_LITTLE_ENDIAN is not set
-+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
-+CONFIG_IRQ_CPU=y
-+CONFIG_IRQ_CPU_RM7K=y
-+CONFIG_IRQ_CPU_RM9K=y
-+CONFIG_MIPS_L1_CACHE_SHIFT=5
-+
-+#
-+# CPU selection
-+#
-+# CONFIG_CPU_MIPS32_R1 is not set
-+# CONFIG_CPU_MIPS32_R2 is not set
-+# CONFIG_CPU_MIPS64_R1 is not set
-+# CONFIG_CPU_MIPS64_R2 is not set
-+# CONFIG_CPU_R3000 is not set
-+# CONFIG_CPU_TX39XX is not set
-+# CONFIG_CPU_VR41XX is not set
-+# CONFIG_CPU_R4300 is not set
-+# CONFIG_CPU_R4X00 is not set
-+# CONFIG_CPU_TX49XX is not set
-+# CONFIG_CPU_R5000 is not set
-+# CONFIG_CPU_R5432 is not set
-+# CONFIG_CPU_R6000 is not set
-+# CONFIG_CPU_NEVADA is not set
-+# CONFIG_CPU_R8000 is not set
-+# CONFIG_CPU_R10000 is not set
-+# CONFIG_CPU_RM7000 is not set
-+CONFIG_CPU_RM9000=y
-+# CONFIG_CPU_SB1 is not set
-+CONFIG_SYS_HAS_CPU_RM9000=y
-+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
-+
-+#
-+# Kernel type
-+#
-+CONFIG_32BIT=y
-+# CONFIG_64BIT is not set
-+CONFIG_PAGE_SIZE_4KB=y
-+# CONFIG_PAGE_SIZE_8KB is not set
-+# CONFIG_PAGE_SIZE_16KB is not set
-+# CONFIG_PAGE_SIZE_64KB is not set
-+CONFIG_CPU_HAS_PREFETCH=y
-+# CONFIG_MIPS_MT is not set
-+# CONFIG_64BIT_PHYS_ADDR is not set
-+# CONFIG_CPU_ADVANCED is not set
-+CONFIG_CPU_HAS_LLSC=y
-+CONFIG_CPU_HAS_SYNC=y
-+CONFIG_GENERIC_HARDIRQS=y
-+CONFIG_GENERIC_IRQ_PROBE=y
-+CONFIG_CPU_SUPPORTS_HIGHMEM=y
-+CONFIG_ARCH_FLATMEM_ENABLE=y
-+CONFIG_SELECT_MEMORY_MODEL=y
-+CONFIG_FLATMEM_MANUAL=y
-+# CONFIG_DISCONTIGMEM_MANUAL is not set
-+# CONFIG_SPARSEMEM_MANUAL is not set
-+CONFIG_FLATMEM=y
-+CONFIG_FLAT_NODE_MEM_MAP=y
-+# CONFIG_SPARSEMEM_STATIC is not set
-+CONFIG_SPLIT_PTLOCK_CPUS=4
-+# CONFIG_SMP is not set
-+# CONFIG_PREEMPT_NONE is not set
-+# CONFIG_PREEMPT_VOLUNTARY is not set
-+CONFIG_PREEMPT=y
-+CONFIG_PREEMPT_BKL=y
-+
-+#
-+# Code maturity level options
-+#
-+CONFIG_EXPERIMENTAL=y
-+CONFIG_BROKEN_ON_SMP=y
-+CONFIG_LOCK_KERNEL=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-+
-+#
-+# General setup
-+#
-+CONFIG_LOCALVERSION=""
-+# CONFIG_LOCALVERSION_AUTO is not set
-+CONFIG_SWAP=y
-+CONFIG_SYSVIPC=y
-+CONFIG_POSIX_MQUEUE=y
-+# CONFIG_BSD_PROCESS_ACCT is not set
-+CONFIG_SYSCTL=y
-+# CONFIG_AUDIT is not set
-+# CONFIG_IKCONFIG is not set
-+CONFIG_INITRAMFS_SOURCE=""
-+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-+CONFIG_EMBEDDED=y
-+CONFIG_KALLSYMS=y
-+# CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_HOTPLUG=y
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_ELF_CORE=y
-+CONFIG_BASE_FULL=y
-+CONFIG_FUTEX=y
-+CONFIG_EPOLL=y
-+CONFIG_SHMEM=y
-+CONFIG_CC_ALIGN_FUNCTIONS=0
-+CONFIG_CC_ALIGN_LABELS=0
-+CONFIG_CC_ALIGN_LOOPS=0
-+CONFIG_CC_ALIGN_JUMPS=0
-+CONFIG_SLAB=y
-+# CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=0
-+# CONFIG_SLOB is not set
-+
-+#
-+# Loadable module support
-+#
-+CONFIG_MODULES=y
-+CONFIG_MODULE_UNLOAD=y
-+# CONFIG_MODULE_FORCE_UNLOAD is not set
-+CONFIG_OBSOLETE_MODPARM=y
-+# CONFIG_MODVERSIONS is not set
-+# CONFIG_MODULE_SRCVERSION_ALL is not set
-+CONFIG_KMOD=y
-+
-+#
-+# Block layer
-+#
-+# CONFIG_LBD is not set
-+
-+#
-+# IO Schedulers
-+#
-+CONFIG_IOSCHED_NOOP=y
-+CONFIG_IOSCHED_AS=y
-+CONFIG_IOSCHED_DEADLINE=y
-+CONFIG_IOSCHED_CFQ=y
-+CONFIG_DEFAULT_AS=y
-+# CONFIG_DEFAULT_DEADLINE is not set
-+# CONFIG_DEFAULT_CFQ is not set
-+# CONFIG_DEFAULT_NOOP is not set
-+CONFIG_DEFAULT_IOSCHED="anticipatory"
-+
-+#
-+# Bus options (PCI, PCMCIA, EISA, ISA, TC)
-+#
-+CONFIG_HW_HAS_PCI=y
-+CONFIG_PCI=y
-+# CONFIG_PCI_LEGACY_PROC is not set
-+CONFIG_MMU=y
-+
-+#
-+# PCCARD (PCMCIA/CardBus) support
-+#
-+# CONFIG_PCCARD is not set
-+
-+#
-+# PCI Hotplug Support
-+#
-+# CONFIG_HOTPLUG_PCI is not set
-+
-+#
-+# Executable file formats
-+#
-+CONFIG_BINFMT_ELF=y
-+# CONFIG_BINFMT_MISC is not set
-+CONFIG_TRAD_SIGNALS=y
-+
-+#
-+# Networking
-+#
-+CONFIG_NET=y
-+
-+#
-+# Networking options
-+#
-+# CONFIG_NETDEBUG is not set
-+CONFIG_PACKET=y
-+CONFIG_PACKET_MMAP=y
-+CONFIG_UNIX=y
-+# CONFIG_NET_KEY is not set
-+CONFIG_INET=y
-+# CONFIG_IP_MULTICAST is not set
-+# CONFIG_IP_ADVANCED_ROUTER is not set
-+CONFIG_IP_FIB_HASH=y
-+CONFIG_IP_PNP=y
-+CONFIG_IP_PNP_DHCP=y
-+# CONFIG_IP_PNP_BOOTP is not set
-+# CONFIG_IP_PNP_RARP is not set
-+# CONFIG_NET_IPIP is not set
-+# CONFIG_NET_IPGRE is not set
-+# CONFIG_ARPD is not set
-+# CONFIG_SYN_COOKIES is not set
-+# CONFIG_INET_AH is not set
-+# CONFIG_INET_ESP is not set
-+# CONFIG_INET_IPCOMP is not set
-+# CONFIG_INET_TUNNEL is not set
-+CONFIG_INET_DIAG=y
-+CONFIG_INET_TCP_DIAG=y
-+# CONFIG_TCP_CONG_ADVANCED is not set
-+CONFIG_TCP_CONG_BIC=y
-+# CONFIG_IPV6 is not set
-+# CONFIG_NETFILTER is not set
-+
-+#
-+# DCCP Configuration (EXPERIMENTAL)
-+#
-+# CONFIG_IP_DCCP is not set
-+
-+#
-+# SCTP Configuration (EXPERIMENTAL)
-+#
-+# CONFIG_IP_SCTP is not set
-+
-+#
-+# TIPC Configuration (EXPERIMENTAL)
-+#
-+# CONFIG_TIPC is not set
-+# CONFIG_ATM is not set
-+# CONFIG_BRIDGE is not set
-+# CONFIG_VLAN_8021Q is not set
-+# CONFIG_DECNET is not set
-+# CONFIG_LLC2 is not set
-+# CONFIG_IPX is not set
-+# CONFIG_ATALK is not set
-+# CONFIG_X25 is not set
-+# CONFIG_LAPB is not set
-+# CONFIG_NET_DIVERT is not set
-+# CONFIG_ECONET is not set
-+# CONFIG_WAN_ROUTER is not set
-+
-+#
-+# QoS and/or fair queueing
-+#
-+# CONFIG_NET_SCHED is not set
-+
-+#
-+# Network testing
-+#
-+# CONFIG_NET_PKTGEN is not set
-+# CONFIG_HAMRADIO is not set
-+# CONFIG_IRDA is not set
-+# CONFIG_BT is not set
-+# CONFIG_IEEE80211 is not set
-+
-+#
-+# Device Drivers
-+#
-+
-+#
-+# Generic Driver Options
-+#
-+CONFIG_STANDALONE=y
-+CONFIG_PREVENT_FIRMWARE_BUILD=y
-+# CONFIG_FW_LOADER is not set
-+
-+#
-+# Connector - unified userspace <-> kernelspace linker
-+#
-+# CONFIG_CONNECTOR is not set
-+
-+#
-+# Memory Technology Devices (MTD)
-+#
-+CONFIG_MTD=y
-+# CONFIG_MTD_DEBUG is not set
-+# CONFIG_MTD_CONCAT is not set
-+CONFIG_MTD_PARTITIONS=y
-+# CONFIG_MTD_REDBOOT_PARTS is not set
-+# CONFIG_MTD_CMDLINE_PARTS is not set
-+
-+#
-+# User Modules And Translation Layers
-+#
-+CONFIG_MTD_CHAR=y
-+CONFIG_MTD_BLOCK=y
-+# CONFIG_FTL is not set
-+# CONFIG_NFTL is not set
-+# CONFIG_INFTL is not set
-+# CONFIG_RFD_FTL is not set
-+
-+#
-+# RAM/ROM/Flash chip drivers
-+#
-+# CONFIG_MTD_CFI is not set
-+# CONFIG_MTD_JEDECPROBE is not set
-+CONFIG_MTD_MAP_BANK_WIDTH_1=y
-+CONFIG_MTD_MAP_BANK_WIDTH_2=y
-+CONFIG_MTD_MAP_BANK_WIDTH_4=y
-+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-+CONFIG_MTD_CFI_I1=y
-+CONFIG_MTD_CFI_I2=y
-+# CONFIG_MTD_CFI_I4 is not set
-+# CONFIG_MTD_CFI_I8 is not set
-+# CONFIG_MTD_RAM is not set
-+# CONFIG_MTD_ROM is not set
-+# CONFIG_MTD_ABSENT is not set
-+# CONFIG_MTD_OBSOLETE_CHIPS is not set
-+
-+#
-+# Mapping drivers for chip access
-+#
-+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-+# CONFIG_MTD_PLATRAM is not set
-+
-+#
-+# Self-contained MTD device drivers
-+#
-+# CONFIG_MTD_PMC551 is not set
-+# CONFIG_MTD_SLRAM is not set
-+# CONFIG_MTD_PHRAM is not set
-+# CONFIG_MTD_MTDRAM is not set
-+# CONFIG_MTD_BLKMTD is not set
-+# CONFIG_MTD_BLOCK2MTD is not set
-+
-+#
-+# Disk-On-Chip Device Drivers
-+#
-+# CONFIG_MTD_DOC2000 is not set
-+# CONFIG_MTD_DOC2001 is not set
-+# CONFIG_MTD_DOC2001PLUS is not set
-+
-+#
-+# NAND Flash Device Drivers
-+#
-+CONFIG_MTD_NAND=y
-+CONFIG_MTD_NAND_VERIFY_WRITE=y
-+CONFIG_MTD_NAND_IDS=y
-+# CONFIG_MTD_NAND_DISKONCHIP is not set
-+CONFIG_MTD_NAND_BASLER_EXCITE=y
-+# CONFIG_MTD_NAND_BASLER_EXCITE_RDNBY is not set
-+# CONFIG_MTD_NAND_BASLER_EXCITE_PERF is not set
-+# CONFIG_MTD_NAND_NANDSIM is not set
-+
-+#
-+# OneNAND Flash Device Drivers
-+#
-+# CONFIG_MTD_ONENAND is not set
-+
-+#
-+# Parallel port support
-+#
-+# CONFIG_PARPORT is not set
-+
-+#
-+# Plug and Play support
-+#
-+
-+#
-+# Block devices
-+#
-+# CONFIG_BLK_CPQ_DA is not set
-+# CONFIG_BLK_CPQ_CISS_DA is not set
-+# CONFIG_BLK_DEV_DAC960 is not set
-+# CONFIG_BLK_DEV_UMEM is not set
-+# CONFIG_BLK_DEV_COW_COMMON is not set
-+CONFIG_BLK_DEV_LOOP=m
-+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-+# CONFIG_BLK_DEV_NBD is not set
-+# CONFIG_BLK_DEV_SX8 is not set
-+# CONFIG_BLK_DEV_UB is not set
-+# CONFIG_BLK_DEV_RAM is not set
-+CONFIG_BLK_DEV_RAM_COUNT=16
-+# CONFIG_CDROM_PKTCDVD is not set
-+# CONFIG_ATA_OVER_ETH is not set
-+
-+#
-+# ATA/ATAPI/MFM/RLL support
-+#
-+# CONFIG_IDE is not set
-+
-+#
-+# SCSI device support
-+#
-+# CONFIG_RAID_ATTRS is not set
-+CONFIG_SCSI=y
-+# CONFIG_SCSI_PROC_FS is not set
-+
-+#
-+# SCSI support type (disk, tape, CD-ROM)
-+#
-+CONFIG_BLK_DEV_SD=y
-+# CONFIG_CHR_DEV_ST is not set
-+# CONFIG_CHR_DEV_OSST is not set
-+# CONFIG_BLK_DEV_SR is not set
-+# CONFIG_CHR_DEV_SG is not set
-+# CONFIG_CHR_DEV_SCH is not set
-+
-+#
-+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-+#
-+# CONFIG_SCSI_MULTI_LUN is not set
-+# CONFIG_SCSI_CONSTANTS is not set
-+# CONFIG_SCSI_LOGGING is not set
-+
-+#
-+# SCSI Transport Attributes
-+#
-+# CONFIG_SCSI_SPI_ATTRS is not set
-+# CONFIG_SCSI_FC_ATTRS is not set
-+# CONFIG_SCSI_ISCSI_ATTRS is not set
-+# CONFIG_SCSI_SAS_ATTRS is not set
-+
-+#
-+# SCSI low-level drivers
-+#
-+# CONFIG_ISCSI_TCP is not set
-+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
-+# CONFIG_SCSI_3W_9XXX is not set
-+# CONFIG_SCSI_ACARD is not set
-+# CONFIG_SCSI_AACRAID is not set
-+# CONFIG_SCSI_AIC7XXX is not set
-+# CONFIG_SCSI_AIC7XXX_OLD is not set
-+# CONFIG_SCSI_AIC79XX is not set
-+# CONFIG_SCSI_DPT_I2O is not set
-+# CONFIG_MEGARAID_NEWGEN is not set
-+# CONFIG_MEGARAID_LEGACY is not set
-+# CONFIG_MEGARAID_SAS is not set
-+# CONFIG_SCSI_SATA is not set
-+# CONFIG_SCSI_DMX3191D is not set
-+# CONFIG_SCSI_FUTURE_DOMAIN is not set
-+# CONFIG_SCSI_IPS is not set
-+# CONFIG_SCSI_INITIO is not set
-+# CONFIG_SCSI_INIA100 is not set
-+# CONFIG_SCSI_SYM53C8XX_2 is not set
-+# CONFIG_SCSI_IPR is not set
-+# CONFIG_SCSI_QLOGIC_FC is not set
-+# CONFIG_SCSI_QLOGIC_1280 is not set
-+# CONFIG_SCSI_QLA_FC is not set
-+# CONFIG_SCSI_LPFC is not set
-+# CONFIG_SCSI_DC395x is not set
-+# CONFIG_SCSI_DC390T is not set
-+# CONFIG_SCSI_NSP32 is not set
-+# CONFIG_SCSI_DEBUG is not set
-+
-+#
-+# Multi-device support (RAID and LVM)
-+#
-+# CONFIG_MD is not set
-+
-+#
-+# Fusion MPT device support
-+#
-+# CONFIG_FUSION is not set
-+# CONFIG_FUSION_SPI is not set
-+# CONFIG_FUSION_FC is not set
-+# CONFIG_FUSION_SAS is not set
-+
-+#
-+# IEEE 1394 (FireWire) support
-+#
-+# CONFIG_IEEE1394 is not set
-+
-+#
-+# I2O device support
-+#
-+# CONFIG_I2O is not set
-+
-+#
-+# Network device support
-+#
-+CONFIG_NETDEVICES=y
-+# CONFIG_DUMMY is not set
-+# CONFIG_BONDING is not set
-+# CONFIG_EQUALIZER is not set
-+# CONFIG_TUN is not set
-+
-+#
-+# ARCnet devices
-+#
-+# CONFIG_ARCNET is not set
-+
-+#
-+# PHY device support
-+#
-+
-+#
-+# Ethernet (10 or 100Mbit)
-+#
-+# CONFIG_NET_ETHERNET is not set
-+
-+#
-+# Ethernet (1000 Mbit)
-+#
-+# CONFIG_ACENIC is not set
-+# CONFIG_DL2K is not set
-+# CONFIG_E1000 is not set
-+# CONFIG_NS83820 is not set
-+# CONFIG_HAMACHI is not set
-+# CONFIG_YELLOWFIN is not set
-+# CONFIG_R8169 is not set
-+# CONFIG_SIS190 is not set
-+# CONFIG_SKGE is not set
-+# CONFIG_SKY2 is not set
-+# CONFIG_SK98LIN is not set
-+# CONFIG_TIGON3 is not set
-+# CONFIG_BNX2 is not set
-+# CONFIG_TITAN_GE is not set
-+CONFIG_RM9K_GE=m
-+
-+#
-+# Ethernet (10000 Mbit)
-+#
-+# CONFIG_CHELSIO_T1 is not set
-+# CONFIG_IXGB is not set
-+# CONFIG_S2IO is not set
-+
-+#
-+# Token Ring devices
-+#
-+# CONFIG_TR is not set
-+
-+#
-+# Wireless LAN (non-hamradio)
-+#
-+# CONFIG_NET_RADIO is not set
-+
-+#
-+# Wan interfaces
-+#
-+# CONFIG_WAN is not set
-+# CONFIG_FDDI is not set
-+# CONFIG_HIPPI is not set
-+# CONFIG_PPP is not set
-+# CONFIG_SLIP is not set
-+# CONFIG_NET_FC is not set
-+# CONFIG_SHAPER is not set
-+# CONFIG_NETCONSOLE is not set
-+# CONFIG_NETPOLL is not set
-+# CONFIG_NET_POLL_CONTROLLER is not set
-+
-+#
-+# ISDN subsystem
-+#
-+# CONFIG_ISDN is not set
-+
-+#
-+# Telephony Support
-+#
-+# CONFIG_PHONE is not set
-+
-+#
-+# Input device support
-+#
-+CONFIG_INPUT=y
-+
-+#
-+# Userland interfaces
-+#
-+CONFIG_INPUT_MOUSEDEV=m
-+CONFIG_INPUT_MOUSEDEV_PSAUX=y
-+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-+# CONFIG_INPUT_JOYDEV is not set
-+# CONFIG_INPUT_TSDEV is not set
-+CONFIG_INPUT_EVDEV=m
-+# CONFIG_INPUT_EVBUG is not set
-+
-+#
-+# Input Device Drivers
-+#
-+# CONFIG_INPUT_KEYBOARD is not set
-+# CONFIG_INPUT_MOUSE is not set
-+# CONFIG_INPUT_JOYSTICK is not set
-+# CONFIG_INPUT_TOUCHSCREEN is not set
-+# CONFIG_INPUT_MISC is not set
-+
-+#
-+# Hardware I/O ports
-+#
-+# CONFIG_SERIO is not set
-+# CONFIG_GAMEPORT is not set
-+
-+#
-+# Character devices
-+#
-+CONFIG_VT=y
-+CONFIG_VT_CONSOLE=y
-+CONFIG_HW_CONSOLE=y
-+# CONFIG_SERIAL_NONSTANDARD is not set
-+
-+#
-+# Serial drivers
-+#
-+CONFIG_SERIAL_8250=y
-+CONFIG_SERIAL_8250_CONSOLE=y
-+CONFIG_SERIAL_8250_NR_UARTS=2
-+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
-+CONFIG_SERIAL_8250_EXTENDED=y
-+# CONFIG_SERIAL_8250_MANY_PORTS is not set
-+CONFIG_SERIAL_8250_SHARE_IRQ=y
-+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
-+# CONFIG_SERIAL_8250_RSA is not set
-+
-+#
-+# Non-8250 serial port support
-+#
-+CONFIG_SERIAL_CORE=y
-+CONFIG_SERIAL_CORE_CONSOLE=y
-+# CONFIG_SERIAL_JSM is not set
-+CONFIG_UNIX98_PTYS=y
-+# CONFIG_LEGACY_PTYS is not set
-+
-+#
-+# IPMI
-+#
-+# CONFIG_IPMI_HANDLER is not set
-+
-+#
-+# Watchdog Cards
-+#
-+CONFIG_WATCHDOG=y
-+# CONFIG_WATCHDOG_NOWAYOUT is not set
-+
-+#
-+# Watchdog Device Drivers
-+#
-+# CONFIG_SOFT_WATCHDOG is not set
-+CONFIG_WDT_RM9K_GPI=m
-+
-+#
-+# PCI-based Watchdog Cards
-+#
-+# CONFIG_PCIPCWATCHDOG is not set
-+# CONFIG_WDTPCI is not set
-+
-+#
-+# USB-based Watchdog Cards
-+#
-+# CONFIG_USBPCWATCHDOG is not set
-+# CONFIG_RTC is not set
-+# CONFIG_GEN_RTC is not set
-+# CONFIG_DTLK is not set
-+# CONFIG_R3964 is not set
-+# CONFIG_APPLICOM is not set
-+
-+#
-+# Ftape, the floppy tape device driver
-+#
-+# CONFIG_DRM is not set
-+# CONFIG_RAW_DRIVER is not set
-+
-+#
-+# TPM devices
-+#
-+# CONFIG_TCG_TPM is not set
-+# CONFIG_TELCLOCK is not set
-+
-+#
-+# I2C support
-+#
-+# CONFIG_I2C is not set
-+
-+#
-+# SPI support
-+#
-+# CONFIG_SPI is not set
-+# CONFIG_SPI_MASTER is not set
-+
-+#
-+# Dallas's 1-wire bus
-+#
-+# CONFIG_W1 is not set
-+
-+#
-+# Hardware Monitoring support
-+#
-+# CONFIG_HWMON is not set
-+# CONFIG_HWMON_VID is not set
-+
-+#
-+# Misc devices
-+#
-+
-+#
-+# Multimedia Capabilities Port drivers
-+#
-+
-+#
-+# Multimedia devices
-+#
-+# CONFIG_VIDEO_DEV is not set
-+
-+#
-+# Digital Video Broadcasting Devices
-+#
-+# CONFIG_DVB is not set
-+
-+#
-+# Graphics support
-+#
-+CONFIG_FB=y
-+CONFIG_FB_CFB_FILLRECT=y
-+CONFIG_FB_CFB_COPYAREA=y
-+CONFIG_FB_CFB_IMAGEBLIT=y
-+# CONFIG_FB_MACMODES is not set
-+# CONFIG_FB_MODE_HELPERS is not set
-+# CONFIG_FB_TILEBLITTING is not set
-+# CONFIG_FB_CIRRUS is not set
-+# CONFIG_FB_PM2 is not set
-+# CONFIG_FB_CYBER2000 is not set
-+# CONFIG_FB_ASILIANT is not set
-+# CONFIG_FB_IMSTT is not set
-+# CONFIG_FB_S1D13XXX is not set
-+# CONFIG_FB_NVIDIA is not set
-+# CONFIG_FB_RIVA is not set
-+# CONFIG_FB_MATROX is not set
-+# CONFIG_FB_RADEON_OLD is not set
-+# CONFIG_FB_RADEON is not set
-+# CONFIG_FB_ATY128 is not set
-+# CONFIG_FB_ATY is not set
-+# CONFIG_FB_SAVAGE is not set
-+# CONFIG_FB_SIS is not set
-+# CONFIG_FB_NEOMAGIC is not set
-+# CONFIG_FB_KYRO is not set
-+# CONFIG_FB_3DFX is not set
-+# CONFIG_FB_VOODOO1 is not set
-+# CONFIG_FB_SMIVGX is not set
-+# CONFIG_FB_TRIDENT is not set
-+# CONFIG_FB_VIRTUAL is not set
-+CONFIG_FB_DD=y
-+
-+#
-+# Console display driver support
-+#
-+# CONFIG_VGA_CONSOLE is not set
-+CONFIG_DUMMY_CONSOLE=y
-+CONFIG_FRAMEBUFFER_CONSOLE=m
-+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
-+# CONFIG_FONTS is not set
-+CONFIG_FONT_8x8=y
-+CONFIG_FONT_8x16=y
-+
-+#
-+# Logo configuration
-+#
-+# CONFIG_LOGO is not set
-+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-+
-+#
-+# Sound
-+#
-+# CONFIG_SOUND is not set
-+
-+#
-+# USB support
-+#
-+CONFIG_USB_ARCH_HAS_HCD=y
-+CONFIG_USB_ARCH_HAS_OHCI=y
-+CONFIG_USB=y
-+# CONFIG_USB_DEBUG is not set
-+
-+#
-+# Miscellaneous USB options
-+#
-+CONFIG_USB_DEVICEFS=y
-+# CONFIG_USB_BANDWIDTH is not set
-+# CONFIG_USB_DYNAMIC_MINORS is not set
-+# CONFIG_USB_OTG is not set
-+
-+#
-+# USB Host Controller Drivers
-+#
-+CONFIG_USB_EHCI_HCD=y
-+# CONFIG_USB_EHCI_SPLIT_ISO is not set
-+# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
-+# CONFIG_USB_ISP116X_HCD is not set
-+CONFIG_USB_OHCI_HCD=y
-+# CONFIG_USB_OHCI_BIG_ENDIAN is not set
-+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
-+# CONFIG_USB_UHCI_HCD is not set
-+# CONFIG_USB_SL811_HCD is not set
-+
-+#
-+# USB Device Class drivers
-+#
-+# CONFIG_USB_ACM is not set
-+# CONFIG_USB_PRINTER is not set
-+
-+#
-+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-+#
-+
-+#
-+# may also be needed; see USB_STORAGE Help for more information
-+#
-+CONFIG_USB_STORAGE=y
-+# CONFIG_USB_STORAGE_DEBUG is not set
-+# CONFIG_USB_STORAGE_DATAFAB is not set
-+# CONFIG_USB_STORAGE_FREECOM is not set
-+# CONFIG_USB_STORAGE_DPCM is not set
-+# CONFIG_USB_STORAGE_USBAT is not set
-+# CONFIG_USB_STORAGE_SDDR09 is not set
-+# CONFIG_USB_STORAGE_SDDR55 is not set
-+# CONFIG_USB_STORAGE_JUMPSHOT is not set
-+# CONFIG_USB_STORAGE_ALAUDA is not set
-+# CONFIG_USB_STORAGE_ONETOUCH is not set
-+# CONFIG_USB_LIBUSUAL is not set
-+
-+#
-+# USB Input Devices
-+#
-+CONFIG_USB_HID=m
-+CONFIG_USB_HIDINPUT=y
-+# CONFIG_USB_HIDINPUT_POWERBOOK is not set
-+# CONFIG_HID_FF is not set
-+# CONFIG_USB_HIDDEV is not set
-+
-+#
-+# USB HID Boot Protocol drivers
-+#
-+# CONFIG_USB_KBD is not set
-+# CONFIG_USB_MOUSE is not set
-+# CONFIG_USB_AIPTEK is not set
-+# CONFIG_USB_WACOM is not set
-+# CONFIG_USB_ACECAD is not set
-+# CONFIG_USB_KBTAB is not set
-+# CONFIG_USB_POWERMATE is not set
-+# CONFIG_USB_MTOUCH is not set
-+# CONFIG_USB_ITMTOUCH is not set
-+# CONFIG_USB_EGALAX is not set
-+# CONFIG_USB_YEALINK is not set
-+# CONFIG_USB_XPAD is not set
-+# CONFIG_USB_ATI_REMOTE is not set
-+# CONFIG_USB_ATI_REMOTE2 is not set
-+# CONFIG_USB_KEYSPAN_REMOTE is not set
-+# CONFIG_USB_APPLETOUCH is not set
-+
-+#
-+# USB Imaging devices
-+#
-+# CONFIG_USB_MDC800 is not set
-+# CONFIG_USB_MICROTEK is not set
-+
-+#
-+# USB Multimedia devices
-+#
-+# CONFIG_USB_DABUSB is not set
-+
-+#
-+# Video4Linux support is needed for USB Multimedia device support
-+#
-+
-+#
-+# USB Network Adapters
-+#
-+# CONFIG_USB_CATC is not set
-+# CONFIG_USB_KAWETH is not set
-+# CONFIG_USB_PEGASUS is not set
-+# CONFIG_USB_RTL8150 is not set
-+# CONFIG_USB_USBNET is not set
-+# CONFIG_USB_MON is not set
-+
-+#
-+# USB port drivers
-+#
-+
-+#
-+# USB Serial Converter support
-+#
-+# CONFIG_USB_SERIAL is not set
-+
-+#
-+# USB Miscellaneous drivers
-+#
-+# CONFIG_USB_EMI62 is not set
-+# CONFIG_USB_EMI26 is not set
-+# CONFIG_USB_AUERSWALD is not set
-+# CONFIG_USB_RIO500 is not set
-+CONFIG_USB_ARTTFT=m
-+# CONFIG_USB_ARTTOUCH is not set
-+# CONFIG_USB_LEGOTOWER is not set
-+# CONFIG_USB_LCD is not set
-+# CONFIG_USB_LED is not set
-+# CONFIG_USB_CYTHERM is not set
-+# CONFIG_USB_PHIDGETKIT is not set
-+# CONFIG_USB_PHIDGETSERVO is not set
-+# CONFIG_USB_IDMOUSE is not set
-+# CONFIG_USB_SISUSBVGA is not set
-+# CONFIG_USB_LD is not set
-+# CONFIG_USB_TEST is not set
-+
-+#
-+# USB DSL modem support
-+#
-+
-+#
-+# USB Gadget Support
-+#
-+# CONFIG_USB_GADGET is not set
-+
-+#
-+# MMC/SD Card support
-+#
-+# CONFIG_MMC is not set
-+
-+#
-+# InfiniBand support
-+#
-+# CONFIG_INFINIBAND is not set
-+
-+#
-+# SN Devices
-+#
-+
-+#
-+# EDAC - error detection and reporting (RAS)
-+#
-+
-+#
-+# eXcite frame capture support
-+#
-+CONFIG_EXCITE_FCAP=m
-+CONFIG_EXCITE_FCAP_GPI=m
-+
-+#
-+# File systems
-+#
-+CONFIG_EXT2_FS=y
-+# CONFIG_EXT2_FS_XATTR is not set
-+# CONFIG_EXT2_FS_XIP is not set
-+# CONFIG_EXT3_FS is not set
-+# CONFIG_REISERFS_FS is not set
-+# CONFIG_JFS_FS is not set
-+# CONFIG_FS_POSIX_ACL is not set
-+# CONFIG_XFS_FS is not set
-+# CONFIG_OCFS2_FS is not set
-+# CONFIG_MINIX_FS is not set
-+# CONFIG_ROMFS_FS is not set
-+CONFIG_INOTIFY=y
-+# CONFIG_QUOTA is not set
-+# CONFIG_DNOTIFY is not set
-+# CONFIG_AUTOFS_FS is not set
-+# CONFIG_AUTOFS4_FS is not set
-+# CONFIG_FUSE_FS is not set
-+
-+#
-+# CD-ROM/DVD Filesystems
-+#
-+# CONFIG_ISO9660_FS is not set
-+# CONFIG_UDF_FS is not set
-+
-+#
-+# DOS/FAT/NT Filesystems
-+#
-+CONFIG_FAT_FS=m
-+CONFIG_MSDOS_FS=m
-+CONFIG_VFAT_FS=m
-+CONFIG_FAT_DEFAULT_CODEPAGE=437
-+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-+# CONFIG_NTFS_FS is not set
-+
-+#
-+# Pseudo filesystems
-+#
-+CONFIG_PROC_FS=y
-+CONFIG_PROC_KCORE=y
-+CONFIG_SYSFS=y
-+CONFIG_TMPFS=y
-+# CONFIG_HUGETLB_PAGE is not set
-+CONFIG_RAMFS=y
-+# CONFIG_RELAYFS_FS is not set
-+# CONFIG_CONFIGFS_FS is not set
-+
-+#
-+# Miscellaneous filesystems
-+#
-+# CONFIG_ADFS_FS is not set
-+# CONFIG_AFFS_FS is not set
-+# CONFIG_HFS_FS is not set
-+# CONFIG_HFSPLUS_FS is not set
-+# CONFIG_BEFS_FS is not set
-+# CONFIG_BFS_FS is not set
-+# CONFIG_EFS_FS is not set
-+# CONFIG_JFFS_FS is not set
-+CONFIG_JFFS2_FS=y
-+CONFIG_JFFS2_FS_DEBUG=0
-+CONFIG_JFFS2_FS_WRITEBUFFER=y
-+# CONFIG_JFFS2_SUMMARY is not set
-+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
-+CONFIG_JFFS2_ZLIB=y
-+CONFIG_JFFS2_RTIME=y
-+# CONFIG_JFFS2_RUBIN is not set
-+# CONFIG_CRAMFS is not set
-+# CONFIG_VXFS_FS is not set
-+# CONFIG_HPFS_FS is not set
-+# CONFIG_QNX4FS_FS is not set
-+# CONFIG_SYSV_FS is not set
-+# CONFIG_UFS_FS is not set
-+
-+#
-+# Network File Systems
-+#
-+CONFIG_NFS_FS=y
-+CONFIG_NFS_V3=y
-+# CONFIG_NFS_V3_ACL is not set
-+# CONFIG_NFS_V4 is not set
-+# CONFIG_NFS_DIRECTIO is not set
-+# CONFIG_NFSD is not set
-+CONFIG_ROOT_NFS=y
-+CONFIG_LOCKD=y
-+CONFIG_LOCKD_V4=y
-+CONFIG_NFS_COMMON=y
-+CONFIG_SUNRPC=y
-+# CONFIG_RPCSEC_GSS_KRB5 is not set
-+# CONFIG_RPCSEC_GSS_SPKM3 is not set
-+# CONFIG_SMB_FS is not set
-+# CONFIG_CIFS is not set
-+# CONFIG_NCP_FS is not set
-+# CONFIG_CODA_FS is not set
-+# CONFIG_AFS_FS is not set
-+# CONFIG_9P_FS is not set
-+
-+#
-+# Partition Types
-+#
-+CONFIG_PARTITION_ADVANCED=y
-+# CONFIG_ACORN_PARTITION is not set
-+# CONFIG_OSF_PARTITION is not set
-+# CONFIG_AMIGA_PARTITION is not set
-+# CONFIG_ATARI_PARTITION is not set
-+# CONFIG_MAC_PARTITION is not set
-+CONFIG_MSDOS_PARTITION=y
-+# CONFIG_BSD_DISKLABEL is not set
-+# CONFIG_MINIX_SUBPARTITION is not set
-+# CONFIG_SOLARIS_X86_PARTITION is not set
-+# CONFIG_UNIXWARE_DISKLABEL is not set
-+# CONFIG_LDM_PARTITION is not set
-+# CONFIG_SGI_PARTITION is not set
-+# CONFIG_ULTRIX_PARTITION is not set
-+# CONFIG_SUN_PARTITION is not set
-+# CONFIG_KARMA_PARTITION is not set
-+# CONFIG_EFI_PARTITION is not set
-+
-+#
-+# Native Language Support
-+#
-+CONFIG_NLS=y
-+CONFIG_NLS_DEFAULT="iso8859-1"
-+CONFIG_NLS_CODEPAGE_437=m
-+# CONFIG_NLS_CODEPAGE_737 is not set
-+# CONFIG_NLS_CODEPAGE_775 is not set
-+CONFIG_NLS_CODEPAGE_850=m
-+# CONFIG_NLS_CODEPAGE_852 is not set
-+# CONFIG_NLS_CODEPAGE_855 is not set
-+# CONFIG_NLS_CODEPAGE_857 is not set
-+# CONFIG_NLS_CODEPAGE_860 is not set
-+# CONFIG_NLS_CODEPAGE_861 is not set
-+# CONFIG_NLS_CODEPAGE_862 is not set
-+# CONFIG_NLS_CODEPAGE_863 is not set
-+# CONFIG_NLS_CODEPAGE_864 is not set
-+# CONFIG_NLS_CODEPAGE_865 is not set
-+# CONFIG_NLS_CODEPAGE_866 is not set
-+# CONFIG_NLS_CODEPAGE_869 is not set
-+# CONFIG_NLS_CODEPAGE_936 is not set
-+# CONFIG_NLS_CODEPAGE_950 is not set
-+# CONFIG_NLS_CODEPAGE_932 is not set
-+# CONFIG_NLS_CODEPAGE_949 is not set
-+# CONFIG_NLS_CODEPAGE_874 is not set
-+# CONFIG_NLS_ISO8859_8 is not set
-+# CONFIG_NLS_CODEPAGE_1250 is not set
-+# CONFIG_NLS_CODEPAGE_1251 is not set
-+# CONFIG_NLS_ASCII is not set
-+CONFIG_NLS_ISO8859_1=m
-+# CONFIG_NLS_ISO8859_2 is not set
-+# CONFIG_NLS_ISO8859_3 is not set
-+# CONFIG_NLS_ISO8859_4 is not set
-+# CONFIG_NLS_ISO8859_5 is not set
-+# CONFIG_NLS_ISO8859_6 is not set
-+# CONFIG_NLS_ISO8859_7 is not set
-+# CONFIG_NLS_ISO8859_9 is not set
-+# CONFIG_NLS_ISO8859_13 is not set
-+# CONFIG_NLS_ISO8859_14 is not set
-+# CONFIG_NLS_ISO8859_15 is not set
-+# CONFIG_NLS_KOI8_R is not set
-+# CONFIG_NLS_KOI8_U is not set
-+# CONFIG_NLS_UTF8 is not set
-+
-+#
-+# Profiling support
-+#
-+# CONFIG_PROFILING is not set
-+
-+#
-+# Kernel hacking
-+#
-+# CONFIG_PRINTK_TIME is not set
-+# CONFIG_MAGIC_SYSRQ is not set
-+# CONFIG_DEBUG_KERNEL is not set
-+CONFIG_LOG_BUF_SHIFT=14
-+CONFIG_CROSSCOMPILE=y
-+CONFIG_CMDLINE=""
-+
-+#
-+# Security options
-+#
-+# CONFIG_KEYS is not set
-+# CONFIG_SECURITY is not set
-+
-+#
-+# Cryptographic options
-+#
-+CONFIG_CRYPTO=y
-+# CONFIG_CRYPTO_HMAC is not set
-+# CONFIG_CRYPTO_NULL is not set
-+# CONFIG_CRYPTO_MD4 is not set
-+# CONFIG_CRYPTO_MD5 is not set
-+# CONFIG_CRYPTO_SHA1 is not set
-+# CONFIG_CRYPTO_SHA256 is not set
-+# CONFIG_CRYPTO_SHA512 is not set
-+# CONFIG_CRYPTO_WP512 is not set
-+# CONFIG_CRYPTO_TGR192 is not set
-+# CONFIG_CRYPTO_DES is not set
-+# CONFIG_CRYPTO_BLOWFISH is not set
-+# CONFIG_CRYPTO_TWOFISH is not set
-+# CONFIG_CRYPTO_SERPENT is not set
-+# CONFIG_CRYPTO_AES is not set
-+# CONFIG_CRYPTO_CAST5 is not set
-+# CONFIG_CRYPTO_CAST6 is not set
-+# CONFIG_CRYPTO_TEA is not set
-+# CONFIG_CRYPTO_ARC4 is not set
-+# CONFIG_CRYPTO_KHAZAD is not set
-+# CONFIG_CRYPTO_ANUBIS is not set
-+# CONFIG_CRYPTO_DEFLATE is not set
-+# CONFIG_CRYPTO_MICHAEL_MIC is not set
-+# CONFIG_CRYPTO_CRC32C is not set
-+# CONFIG_CRYPTO_TEST is not set
-+
-+#
-+# Hardware crypto devices
-+#
-+
-+#
-+# Library routines
-+#
-+# CONFIG_CRC_CCITT is not set
-+# CONFIG_CRC16 is not set
-+CONFIG_CRC32=y
-+# CONFIG_LIBCRC32C is not set
-+CONFIG_ZLIB_INFLATE=y
-+CONFIG_ZLIB_DEFLATE=y
-diff -Naur linux-2.6.17.orig/arch/mips/configs/ip22_defconfig linux-2.6.17/arch/mips/configs/ip22_defconfig
---- linux-2.6.17.orig/arch/mips/configs/ip22_defconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/configs/ip22_defconfig	2006-06-19 18:16:13.000000000 -0700
-@@ -41,8 +41,6 @@
- # CONFIG_MIPS_XXS1500 is not set
- # CONFIG_PNX8550_V2PCI is not set
- # CONFIG_PNX8550_JBS is not set
--# CONFIG_DDB5074 is not set
--# CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
- # CONFIG_MACH_VR41XX is not set
- # CONFIG_PMC_YOSEMITE is not set
-@@ -67,6 +65,7 @@
- CONFIG_GENERIC_FIND_NEXT_BIT=y
- CONFIG_GENERIC_HWEIGHT=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
- CONFIG_ARC=y
- CONFIG_DMA_NONCOHERENT=y
- CONFIG_DMA_NEED_PCI_MAP_STATE=y
-diff -Naur linux-2.6.17.orig/arch/mips/configs/ip27_defconfig linux-2.6.17/arch/mips/configs/ip27_defconfig
---- linux-2.6.17.orig/arch/mips/configs/ip27_defconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/configs/ip27_defconfig	2006-06-19 18:16:13.000000000 -0700
-@@ -41,8 +41,6 @@
- # CONFIG_MIPS_XXS1500 is not set
- # CONFIG_PNX8550_V2PCI is not set
- # CONFIG_PNX8550_JBS is not set
--# CONFIG_DDB5074 is not set
--# CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
- # CONFIG_MACH_VR41XX is not set
- # CONFIG_PMC_YOSEMITE is not set
-@@ -63,7 +61,7 @@
- # CONFIG_TOSHIBA_JMR3927 is not set
- # CONFIG_TOSHIBA_RBTX4927 is not set
- # CONFIG_TOSHIBA_RBTX4938 is not set
--# CONFIG_SGI_SN0_N_MODE is not set
-+# CONFIG_SGI_SN_N_MODE is not set
- CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
- CONFIG_NUMA=y
- # CONFIG_MAPPED_KERNEL is not set
-@@ -73,6 +71,7 @@
- CONFIG_GENERIC_FIND_NEXT_BIT=y
- CONFIG_GENERIC_HWEIGHT=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
- CONFIG_ARC=y
- CONFIG_DMA_IP27=y
- CONFIG_CPU_BIG_ENDIAN=y
-diff -Naur linux-2.6.17.orig/arch/mips/configs/ip32_defconfig linux-2.6.17/arch/mips/configs/ip32_defconfig
---- linux-2.6.17.orig/arch/mips/configs/ip32_defconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/configs/ip32_defconfig	2006-06-19 18:16:13.000000000 -0700
-@@ -41,8 +41,6 @@
- # CONFIG_MIPS_XXS1500 is not set
- # CONFIG_PNX8550_V2PCI is not set
- # CONFIG_PNX8550_JBS is not set
--# CONFIG_DDB5074 is not set
--# CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
- # CONFIG_MACH_VR41XX is not set
- # CONFIG_PMC_YOSEMITE is not set
-@@ -67,6 +65,7 @@
- CONFIG_GENERIC_FIND_NEXT_BIT=y
- CONFIG_GENERIC_HWEIGHT=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
- CONFIG_ARC=y
- CONFIG_DMA_IP32=y
- CONFIG_DMA_NONCOHERENT=y
-diff -Naur linux-2.6.17.orig/arch/mips/configs/it8172_defconfig linux-2.6.17/arch/mips/configs/it8172_defconfig
---- linux-2.6.17.orig/arch/mips/configs/it8172_defconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/configs/it8172_defconfig	2006-06-19 18:16:13.000000000 -0700
-@@ -41,8 +41,6 @@
- # CONFIG_MIPS_XXS1500 is not set
- # CONFIG_PNX8550_V2PCI is not set
- # CONFIG_PNX8550_JBS is not set
--# CONFIG_DDB5074 is not set
--# CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
- # CONFIG_MACH_VR41XX is not set
- # CONFIG_PMC_YOSEMITE is not set
-@@ -68,6 +66,7 @@
- CONFIG_GENERIC_FIND_NEXT_BIT=y
- CONFIG_GENERIC_HWEIGHT=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
- CONFIG_DMA_NONCOHERENT=y
- CONFIG_DMA_NEED_PCI_MAP_STATE=y
- # CONFIG_CPU_BIG_ENDIAN is not set
-diff -Naur linux-2.6.17.orig/arch/mips/configs/ivr_defconfig linux-2.6.17/arch/mips/configs/ivr_defconfig
---- linux-2.6.17.orig/arch/mips/configs/ivr_defconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/configs/ivr_defconfig	2006-06-19 18:16:13.000000000 -0700
-@@ -41,8 +41,6 @@
- # CONFIG_MIPS_XXS1500 is not set
- # CONFIG_PNX8550_V2PCI is not set
- # CONFIG_PNX8550_JBS is not set
--# CONFIG_DDB5074 is not set
--# CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
- # CONFIG_MACH_VR41XX is not set
- # CONFIG_PMC_YOSEMITE is not set
-@@ -67,6 +65,7 @@
- CONFIG_GENERIC_FIND_NEXT_BIT=y
- CONFIG_GENERIC_HWEIGHT=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
- CONFIG_DMA_NONCOHERENT=y
- CONFIG_DMA_NEED_PCI_MAP_STATE=y
- # CONFIG_CPU_BIG_ENDIAN is not set
-diff -Naur linux-2.6.17.orig/arch/mips/configs/jaguar-atx_defconfig linux-2.6.17/arch/mips/configs/jaguar-atx_defconfig
---- linux-2.6.17.orig/arch/mips/configs/jaguar-atx_defconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/configs/jaguar-atx_defconfig	2006-06-19 18:16:13.000000000 -0700
-@@ -41,8 +41,6 @@
- # CONFIG_MIPS_XXS1500 is not set
- # CONFIG_PNX8550_V2PCI is not set
- # CONFIG_PNX8550_JBS is not set
--# CONFIG_DDB5074 is not set
--# CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
- # CONFIG_MACH_VR41XX is not set
- # CONFIG_PMC_YOSEMITE is not set
-@@ -68,6 +66,7 @@
- CONFIG_GENERIC_FIND_NEXT_BIT=y
- CONFIG_GENERIC_HWEIGHT=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
- CONFIG_DMA_NONCOHERENT=y
- CONFIG_DMA_NEED_PCI_MAP_STATE=y
- CONFIG_LIMITED_DMA=y
-diff -Naur linux-2.6.17.orig/arch/mips/configs/jmr3927_defconfig linux-2.6.17/arch/mips/configs/jmr3927_defconfig
---- linux-2.6.17.orig/arch/mips/configs/jmr3927_defconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/configs/jmr3927_defconfig	2006-06-19 18:16:13.000000000 -0700
-@@ -41,8 +41,6 @@
- # CONFIG_MIPS_XXS1500 is not set
- # CONFIG_PNX8550_V2PCI is not set
- # CONFIG_PNX8550_JBS is not set
--# CONFIG_DDB5074 is not set
--# CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
- # CONFIG_MACH_VR41XX is not set
- # CONFIG_PMC_YOSEMITE is not set
-@@ -67,6 +65,7 @@
- CONFIG_GENERIC_FIND_NEXT_BIT=y
- CONFIG_GENERIC_HWEIGHT=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
- CONFIG_DMA_NONCOHERENT=y
- CONFIG_DMA_NEED_PCI_MAP_STATE=y
- CONFIG_CPU_BIG_ENDIAN=y
-diff -Naur linux-2.6.17.orig/arch/mips/configs/lasat200_defconfig linux-2.6.17/arch/mips/configs/lasat200_defconfig
---- linux-2.6.17.orig/arch/mips/configs/lasat200_defconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/configs/lasat200_defconfig	2006-06-19 18:16:13.000000000 -0700
-@@ -41,8 +41,6 @@
- # CONFIG_MIPS_XXS1500 is not set
- # CONFIG_PNX8550_V2PCI is not set
- # CONFIG_PNX8550_JBS is not set
--# CONFIG_DDB5074 is not set
--# CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
- # CONFIG_MACH_VR41XX is not set
- # CONFIG_PMC_YOSEMITE is not set
-@@ -71,6 +69,7 @@
- CONFIG_GENERIC_FIND_NEXT_BIT=y
- CONFIG_GENERIC_HWEIGHT=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
- CONFIG_DMA_NONCOHERENT=y
- CONFIG_DMA_NEED_PCI_MAP_STATE=y
- CONFIG_MIPS_NILE4=y
-diff -Naur linux-2.6.17.orig/arch/mips/configs/malta_defconfig linux-2.6.17/arch/mips/configs/malta_defconfig
---- linux-2.6.17.orig/arch/mips/configs/malta_defconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/configs/malta_defconfig	2006-06-19 18:16:13.000000000 -0700
-@@ -41,8 +41,6 @@
- # CONFIG_MIPS_XXS1500 is not set
- # CONFIG_PNX8550_V2PCI is not set
- # CONFIG_PNX8550_JBS is not set
--# CONFIG_DDB5074 is not set
--# CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
- # CONFIG_MACH_VR41XX is not set
- # CONFIG_PMC_YOSEMITE is not set
-@@ -67,6 +65,7 @@
- CONFIG_GENERIC_FIND_NEXT_BIT=y
- CONFIG_GENERIC_HWEIGHT=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
- CONFIG_ARCH_MAY_HAVE_PC_FDC=y
- CONFIG_DMA_NONCOHERENT=y
- CONFIG_DMA_NEED_PCI_MAP_STATE=y
-diff -Naur linux-2.6.17.orig/arch/mips/configs/mipssim_defconfig linux-2.6.17/arch/mips/configs/mipssim_defconfig
---- linux-2.6.17.orig/arch/mips/configs/mipssim_defconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/configs/mipssim_defconfig	2006-06-19 18:16:13.000000000 -0700
-@@ -41,8 +41,6 @@
- # CONFIG_MIPS_XXS1500 is not set
- # CONFIG_PNX8550_V2PCI is not set
- # CONFIG_PNX8550_JBS is not set
--# CONFIG_DDB5074 is not set
--# CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
- # CONFIG_MACH_VR41XX is not set
- # CONFIG_PMC_YOSEMITE is not set
-@@ -67,6 +65,7 @@
- CONFIG_GENERIC_FIND_NEXT_BIT=y
- CONFIG_GENERIC_HWEIGHT=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
- CONFIG_DMA_NONCOHERENT=y
- CONFIG_DMA_NEED_PCI_MAP_STATE=y
- # CONFIG_CPU_BIG_ENDIAN is not set
-diff -Naur linux-2.6.17.orig/arch/mips/configs/mpc30x_defconfig linux-2.6.17/arch/mips/configs/mpc30x_defconfig
---- linux-2.6.17.orig/arch/mips/configs/mpc30x_defconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/configs/mpc30x_defconfig	2006-06-19 18:16:13.000000000 -0700
-@@ -41,8 +41,6 @@
- # CONFIG_MIPS_XXS1500 is not set
- # CONFIG_PNX8550_V2PCI is not set
- # CONFIG_PNX8550_JBS is not set
--# CONFIG_DDB5074 is not set
--# CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
- CONFIG_MACH_VR41XX=y
- # CONFIG_PMC_YOSEMITE is not set
-@@ -75,6 +73,7 @@
- CONFIG_GENERIC_FIND_NEXT_BIT=y
- CONFIG_GENERIC_HWEIGHT=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
- CONFIG_DMA_NONCOHERENT=y
- CONFIG_DMA_NEED_PCI_MAP_STATE=y
- # CONFIG_CPU_BIG_ENDIAN is not set
-diff -Naur linux-2.6.17.orig/arch/mips/configs/ocelot_3_defconfig linux-2.6.17/arch/mips/configs/ocelot_3_defconfig
---- linux-2.6.17.orig/arch/mips/configs/ocelot_3_defconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/configs/ocelot_3_defconfig	2006-06-19 18:16:13.000000000 -0700
-@@ -41,8 +41,6 @@
- # CONFIG_MIPS_XXS1500 is not set
- # CONFIG_PNX8550_V2PCI is not set
- # CONFIG_PNX8550_JBS is not set
--# CONFIG_DDB5074 is not set
--# CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
- # CONFIG_MACH_VR41XX is not set
- # CONFIG_PMC_YOSEMITE is not set
-@@ -67,6 +65,7 @@
- CONFIG_GENERIC_FIND_NEXT_BIT=y
- CONFIG_GENERIC_HWEIGHT=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
- CONFIG_DMA_NONCOHERENT=y
- CONFIG_DMA_NEED_PCI_MAP_STATE=y
- CONFIG_CPU_BIG_ENDIAN=y
-diff -Naur linux-2.6.17.orig/arch/mips/configs/ocelot_c_defconfig linux-2.6.17/arch/mips/configs/ocelot_c_defconfig
---- linux-2.6.17.orig/arch/mips/configs/ocelot_c_defconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/configs/ocelot_c_defconfig	2006-06-19 18:16:13.000000000 -0700
-@@ -41,8 +41,6 @@
- # CONFIG_MIPS_XXS1500 is not set
- # CONFIG_PNX8550_V2PCI is not set
- # CONFIG_PNX8550_JBS is not set
--# CONFIG_DDB5074 is not set
--# CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
- # CONFIG_MACH_VR41XX is not set
- # CONFIG_PMC_YOSEMITE is not set
-@@ -67,6 +65,7 @@
- CONFIG_GENERIC_FIND_NEXT_BIT=y
- CONFIG_GENERIC_HWEIGHT=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
- CONFIG_DMA_NONCOHERENT=y
- CONFIG_DMA_NEED_PCI_MAP_STATE=y
- CONFIG_CPU_BIG_ENDIAN=y
-diff -Naur linux-2.6.17.orig/arch/mips/configs/ocelot_defconfig linux-2.6.17/arch/mips/configs/ocelot_defconfig
---- linux-2.6.17.orig/arch/mips/configs/ocelot_defconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/configs/ocelot_defconfig	2006-06-19 18:16:13.000000000 -0700
-@@ -41,8 +41,6 @@
- # CONFIG_MIPS_XXS1500 is not set
- # CONFIG_PNX8550_V2PCI is not set
- # CONFIG_PNX8550_JBS is not set
--# CONFIG_DDB5074 is not set
--# CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
- # CONFIG_MACH_VR41XX is not set
- # CONFIG_PMC_YOSEMITE is not set
-@@ -67,6 +65,7 @@
- CONFIG_GENERIC_FIND_NEXT_BIT=y
- CONFIG_GENERIC_HWEIGHT=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
- CONFIG_DMA_NONCOHERENT=y
- CONFIG_DMA_NEED_PCI_MAP_STATE=y
- CONFIG_CPU_BIG_ENDIAN=y
-diff -Naur linux-2.6.17.orig/arch/mips/configs/ocelot_g_defconfig linux-2.6.17/arch/mips/configs/ocelot_g_defconfig
---- linux-2.6.17.orig/arch/mips/configs/ocelot_g_defconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/configs/ocelot_g_defconfig	2006-06-19 18:16:13.000000000 -0700
-@@ -41,8 +41,6 @@
- # CONFIG_MIPS_XXS1500 is not set
- # CONFIG_PNX8550_V2PCI is not set
- # CONFIG_PNX8550_JBS is not set
--# CONFIG_DDB5074 is not set
--# CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
- # CONFIG_MACH_VR41XX is not set
- # CONFIG_PMC_YOSEMITE is not set
-@@ -67,6 +65,7 @@
- CONFIG_GENERIC_FIND_NEXT_BIT=y
- CONFIG_GENERIC_HWEIGHT=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
- CONFIG_DMA_NONCOHERENT=y
- CONFIG_DMA_NEED_PCI_MAP_STATE=y
- CONFIG_CPU_BIG_ENDIAN=y
-diff -Naur linux-2.6.17.orig/arch/mips/configs/pb1100_defconfig linux-2.6.17/arch/mips/configs/pb1100_defconfig
---- linux-2.6.17.orig/arch/mips/configs/pb1100_defconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/configs/pb1100_defconfig	2006-06-19 18:16:13.000000000 -0700
-@@ -41,8 +41,6 @@
- # CONFIG_MIPS_XXS1500 is not set
- # CONFIG_PNX8550_V2PCI is not set
- # CONFIG_PNX8550_JBS is not set
--# CONFIG_DDB5074 is not set
--# CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
- # CONFIG_MACH_VR41XX is not set
- # CONFIG_PMC_YOSEMITE is not set
-@@ -67,6 +65,7 @@
- CONFIG_GENERIC_FIND_NEXT_BIT=y
- CONFIG_GENERIC_HWEIGHT=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
- CONFIG_DMA_NONCOHERENT=y
- CONFIG_DMA_NEED_PCI_MAP_STATE=y
- # CONFIG_CPU_BIG_ENDIAN is not set
-diff -Naur linux-2.6.17.orig/arch/mips/configs/pb1500_defconfig linux-2.6.17/arch/mips/configs/pb1500_defconfig
---- linux-2.6.17.orig/arch/mips/configs/pb1500_defconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/configs/pb1500_defconfig	2006-06-19 18:16:13.000000000 -0700
-@@ -41,8 +41,6 @@
- # CONFIG_MIPS_XXS1500 is not set
- # CONFIG_PNX8550_V2PCI is not set
- # CONFIG_PNX8550_JBS is not set
--# CONFIG_DDB5074 is not set
--# CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
- # CONFIG_MACH_VR41XX is not set
- # CONFIG_PMC_YOSEMITE is not set
-@@ -67,6 +65,7 @@
- CONFIG_GENERIC_FIND_NEXT_BIT=y
- CONFIG_GENERIC_HWEIGHT=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
- CONFIG_DMA_NONCOHERENT=y
- CONFIG_DMA_NEED_PCI_MAP_STATE=y
- # CONFIG_CPU_BIG_ENDIAN is not set
-diff -Naur linux-2.6.17.orig/arch/mips/configs/pb1550_defconfig linux-2.6.17/arch/mips/configs/pb1550_defconfig
---- linux-2.6.17.orig/arch/mips/configs/pb1550_defconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/configs/pb1550_defconfig	2006-06-19 18:16:13.000000000 -0700
-@@ -41,8 +41,6 @@
- # CONFIG_MIPS_XXS1500 is not set
- # CONFIG_PNX8550_V2PCI is not set
- # CONFIG_PNX8550_JBS is not set
--# CONFIG_DDB5074 is not set
--# CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
- # CONFIG_MACH_VR41XX is not set
- # CONFIG_PMC_YOSEMITE is not set
-@@ -67,6 +65,7 @@
- CONFIG_GENERIC_FIND_NEXT_BIT=y
- CONFIG_GENERIC_HWEIGHT=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
- CONFIG_DMA_NONCOHERENT=y
- CONFIG_DMA_NEED_PCI_MAP_STATE=y
- CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y
-diff -Naur linux-2.6.17.orig/arch/mips/configs/pnx8550-jbs_defconfig linux-2.6.17/arch/mips/configs/pnx8550-jbs_defconfig
---- linux-2.6.17.orig/arch/mips/configs/pnx8550-jbs_defconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/configs/pnx8550-jbs_defconfig	2006-06-19 18:16:13.000000000 -0700
-@@ -41,8 +41,6 @@
- # CONFIG_MIPS_XXS1500 is not set
- # CONFIG_PNX8550_V2PCI is not set
- CONFIG_PNX8550_JBS=y
--# CONFIG_DDB5074 is not set
--# CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
- # CONFIG_MACH_VR41XX is not set
- # CONFIG_PMC_YOSEMITE is not set
-@@ -67,6 +65,7 @@
- CONFIG_GENERIC_FIND_NEXT_BIT=y
- CONFIG_GENERIC_HWEIGHT=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
- CONFIG_DMA_NONCOHERENT=y
- CONFIG_DMA_NEED_PCI_MAP_STATE=y
- # CONFIG_CPU_BIG_ENDIAN is not set
-diff -Naur linux-2.6.17.orig/arch/mips/configs/pnx8550-v2pci_defconfig linux-2.6.17/arch/mips/configs/pnx8550-v2pci_defconfig
---- linux-2.6.17.orig/arch/mips/configs/pnx8550-v2pci_defconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/configs/pnx8550-v2pci_defconfig	2006-06-19 18:16:13.000000000 -0700
-@@ -41,8 +41,6 @@
- # CONFIG_MIPS_XXS1500 is not set
- CONFIG_PNX8550_V2PCI=y
- # CONFIG_PNX8550_JBS is not set
--# CONFIG_DDB5074 is not set
--# CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
- # CONFIG_MACH_VR41XX is not set
- # CONFIG_PMC_YOSEMITE is not set
-@@ -67,6 +65,7 @@
- CONFIG_GENERIC_FIND_NEXT_BIT=y
- CONFIG_GENERIC_HWEIGHT=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
- CONFIG_DMA_NONCOHERENT=y
- CONFIG_DMA_NEED_PCI_MAP_STATE=y
- # CONFIG_CPU_BIG_ENDIAN is not set
-diff -Naur linux-2.6.17.orig/arch/mips/configs/qemu_defconfig linux-2.6.17/arch/mips/configs/qemu_defconfig
---- linux-2.6.17.orig/arch/mips/configs/qemu_defconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/configs/qemu_defconfig	2006-06-19 18:16:13.000000000 -0700
-@@ -41,8 +41,6 @@
- # CONFIG_MIPS_XXS1500 is not set
- # CONFIG_PNX8550_V2PCI is not set
- # CONFIG_PNX8550_JBS is not set
--# CONFIG_DDB5074 is not set
--# CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
- # CONFIG_MACH_VR41XX is not set
- # CONFIG_PMC_YOSEMITE is not set
-@@ -67,6 +65,7 @@
- CONFIG_GENERIC_FIND_NEXT_BIT=y
- CONFIG_GENERIC_HWEIGHT=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
- CONFIG_DMA_COHERENT=y
- CONFIG_GENERIC_ISA_DMA=y
- CONFIG_I8259=y
-diff -Naur linux-2.6.17.orig/arch/mips/configs/rbhma4500_defconfig linux-2.6.17/arch/mips/configs/rbhma4500_defconfig
---- linux-2.6.17.orig/arch/mips/configs/rbhma4500_defconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/configs/rbhma4500_defconfig	2006-06-19 18:16:13.000000000 -0700
-@@ -41,8 +41,6 @@
- # CONFIG_MIPS_XXS1500 is not set
- # CONFIG_PNX8550_V2PCI is not set
- # CONFIG_PNX8550_JBS is not set
--# CONFIG_DDB5074 is not set
--# CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
- # CONFIG_MACH_VR41XX is not set
- # CONFIG_PMC_YOSEMITE is not set
-@@ -74,6 +72,7 @@
- CONFIG_GENERIC_FIND_NEXT_BIT=y
- CONFIG_GENERIC_HWEIGHT=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
- CONFIG_DMA_NONCOHERENT=y
- CONFIG_DMA_NEED_PCI_MAP_STATE=y
- CONFIG_GENERIC_ISA_DMA=y
-diff -Naur linux-2.6.17.orig/arch/mips/configs/rm200_defconfig linux-2.6.17/arch/mips/configs/rm200_defconfig
---- linux-2.6.17.orig/arch/mips/configs/rm200_defconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/configs/rm200_defconfig	2006-06-19 18:16:13.000000000 -0700
-@@ -41,8 +41,6 @@
- # CONFIG_MIPS_XXS1500 is not set
- # CONFIG_PNX8550_V2PCI is not set
- # CONFIG_PNX8550_JBS is not set
--# CONFIG_DDB5074 is not set
--# CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
- # CONFIG_MACH_VR41XX is not set
- # CONFIG_PMC_YOSEMITE is not set
-@@ -67,6 +65,7 @@
- CONFIG_GENERIC_FIND_NEXT_BIT=y
- CONFIG_GENERIC_HWEIGHT=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
- CONFIG_ARC=y
- CONFIG_ARCH_MAY_HAVE_PC_FDC=y
- CONFIG_DMA_NONCOHERENT=y
-diff -Naur linux-2.6.17.orig/arch/mips/configs/sb1250-swarm_defconfig linux-2.6.17/arch/mips/configs/sb1250-swarm_defconfig
---- linux-2.6.17.orig/arch/mips/configs/sb1250-swarm_defconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/configs/sb1250-swarm_defconfig	2006-06-19 18:16:13.000000000 -0700
-@@ -41,8 +41,6 @@
- # CONFIG_MIPS_XXS1500 is not set
- # CONFIG_PNX8550_V2PCI is not set
- # CONFIG_PNX8550_JBS is not set
--# CONFIG_DDB5074 is not set
--# CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
- # CONFIG_MACH_VR41XX is not set
- # CONFIG_PMC_YOSEMITE is not set
-@@ -84,6 +82,7 @@
- CONFIG_GENERIC_FIND_NEXT_BIT=y
- CONFIG_GENERIC_HWEIGHT=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
- CONFIG_DMA_COHERENT=y
- CONFIG_CPU_BIG_ENDIAN=y
- # CONFIG_CPU_LITTLE_ENDIAN is not set
-diff -Naur linux-2.6.17.orig/arch/mips/configs/sead_defconfig linux-2.6.17/arch/mips/configs/sead_defconfig
---- linux-2.6.17.orig/arch/mips/configs/sead_defconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/configs/sead_defconfig	2006-06-19 18:16:13.000000000 -0700
-@@ -41,8 +41,6 @@
- # CONFIG_MIPS_XXS1500 is not set
- # CONFIG_PNX8550_V2PCI is not set
- # CONFIG_PNX8550_JBS is not set
--# CONFIG_DDB5074 is not set
--# CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
- # CONFIG_MACH_VR41XX is not set
- # CONFIG_PMC_YOSEMITE is not set
-@@ -67,6 +65,7 @@
- CONFIG_GENERIC_FIND_NEXT_BIT=y
- CONFIG_GENERIC_HWEIGHT=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
- CONFIG_DMA_NONCOHERENT=y
- CONFIG_DMA_NEED_PCI_MAP_STATE=y
- # CONFIG_CPU_BIG_ENDIAN is not set
-diff -Naur linux-2.6.17.orig/arch/mips/configs/tb0226_defconfig linux-2.6.17/arch/mips/configs/tb0226_defconfig
---- linux-2.6.17.orig/arch/mips/configs/tb0226_defconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/configs/tb0226_defconfig	2006-06-19 18:16:13.000000000 -0700
-@@ -41,8 +41,6 @@
- # CONFIG_MIPS_XXS1500 is not set
- # CONFIG_PNX8550_V2PCI is not set
- # CONFIG_PNX8550_JBS is not set
--# CONFIG_DDB5074 is not set
--# CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
- CONFIG_MACH_VR41XX=y
- # CONFIG_PMC_YOSEMITE is not set
-@@ -77,6 +75,7 @@
- CONFIG_GENERIC_FIND_NEXT_BIT=y
- CONFIG_GENERIC_HWEIGHT=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
- CONFIG_DMA_NONCOHERENT=y
- CONFIG_DMA_NEED_PCI_MAP_STATE=y
- # CONFIG_CPU_BIG_ENDIAN is not set
-diff -Naur linux-2.6.17.orig/arch/mips/configs/tb0229_defconfig linux-2.6.17/arch/mips/configs/tb0229_defconfig
---- linux-2.6.17.orig/arch/mips/configs/tb0229_defconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/configs/tb0229_defconfig	2006-06-19 18:16:13.000000000 -0700
-@@ -41,8 +41,6 @@
- # CONFIG_MIPS_XXS1500 is not set
- # CONFIG_PNX8550_V2PCI is not set
- # CONFIG_PNX8550_JBS is not set
--# CONFIG_DDB5074 is not set
--# CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
- CONFIG_MACH_VR41XX=y
- # CONFIG_PMC_YOSEMITE is not set
-@@ -77,6 +75,7 @@
- CONFIG_GENERIC_FIND_NEXT_BIT=y
- CONFIG_GENERIC_HWEIGHT=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
- CONFIG_DMA_NONCOHERENT=y
- CONFIG_DMA_NEED_PCI_MAP_STATE=y
- # CONFIG_CPU_BIG_ENDIAN is not set
-diff -Naur linux-2.6.17.orig/arch/mips/configs/tb0287_defconfig linux-2.6.17/arch/mips/configs/tb0287_defconfig
---- linux-2.6.17.orig/arch/mips/configs/tb0287_defconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/configs/tb0287_defconfig	2006-06-19 18:16:13.000000000 -0700
-@@ -41,8 +41,6 @@
- # CONFIG_MIPS_XXS1500 is not set
- # CONFIG_PNX8550_V2PCI is not set
- # CONFIG_PNX8550_JBS is not set
--# CONFIG_DDB5074 is not set
--# CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
- CONFIG_MACH_VR41XX=y
- # CONFIG_PMC_YOSEMITE is not set
-diff -Naur linux-2.6.17.orig/arch/mips/configs/workpad_defconfig linux-2.6.17/arch/mips/configs/workpad_defconfig
---- linux-2.6.17.orig/arch/mips/configs/workpad_defconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/configs/workpad_defconfig	2006-06-19 18:16:13.000000000 -0700
-@@ -41,8 +41,6 @@
- # CONFIG_MIPS_XXS1500 is not set
- # CONFIG_PNX8550_V2PCI is not set
- # CONFIG_PNX8550_JBS is not set
--# CONFIG_DDB5074 is not set
--# CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
- CONFIG_MACH_VR41XX=y
- # CONFIG_PMC_YOSEMITE is not set
-@@ -73,6 +71,7 @@
- CONFIG_GENERIC_FIND_NEXT_BIT=y
- CONFIG_GENERIC_HWEIGHT=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
- CONFIG_DMA_NONCOHERENT=y
- CONFIG_DMA_NEED_PCI_MAP_STATE=y
- # CONFIG_CPU_BIG_ENDIAN is not set
-diff -Naur linux-2.6.17.orig/arch/mips/configs/wrppmc_defconfig linux-2.6.17/arch/mips/configs/wrppmc_defconfig
---- linux-2.6.17.orig/arch/mips/configs/wrppmc_defconfig	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/arch/mips/configs/wrppmc_defconfig	2006-06-19 18:16:13.000000000 -0700
-@@ -0,0 +1,799 @@
-+#
-+# Automatically generated make config: don't edit
-+# Linux kernel version: 2.6.16.11
-+# Fri May  5 17:11:22 2006
-+#
-+CONFIG_MIPS=y
-+
-+#
-+# Machine selection
-+#
-+# CONFIG_MIPS_MTX1 is not set
-+# CONFIG_MIPS_BOSPORUS is not set
-+# CONFIG_MIPS_PB1000 is not set
-+# CONFIG_MIPS_PB1100 is not set
-+# CONFIG_MIPS_PB1500 is not set
-+# CONFIG_MIPS_PB1550 is not set
-+# CONFIG_MIPS_PB1200 is not set
-+# CONFIG_MIPS_DB1000 is not set
-+# CONFIG_MIPS_DB1100 is not set
-+# CONFIG_MIPS_DB1500 is not set
-+# CONFIG_MIPS_DB1550 is not set
-+# CONFIG_MIPS_DB1200 is not set
-+# CONFIG_MIPS_MIRAGE is not set
-+# CONFIG_MIPS_COBALT is not set
-+# CONFIG_MACH_DECSTATION is not set
-+# CONFIG_MIPS_EV64120 is not set
-+# CONFIG_MIPS_EV96100 is not set
-+# CONFIG_MIPS_IVR is not set
-+# CONFIG_MIPS_ITE8172 is not set
-+# CONFIG_MACH_JAZZ is not set
-+# CONFIG_LASAT is not set
-+# CONFIG_MIPS_ATLAS is not set
-+# CONFIG_MIPS_MALTA is not set
-+# CONFIG_MIPS_SEAD is not set
-+CONFIG_WR_PPMC=y
-+# CONFIG_MIPS_SIM is not set
-+# CONFIG_MOMENCO_JAGUAR_ATX is not set
-+# CONFIG_MOMENCO_OCELOT is not set
-+# CONFIG_MOMENCO_OCELOT_3 is not set
-+# CONFIG_MOMENCO_OCELOT_C is not set
-+# CONFIG_MOMENCO_OCELOT_G is not set
-+# CONFIG_MIPS_XXS1500 is not set
-+# CONFIG_PNX8550_V2PCI is not set
-+# CONFIG_PNX8550_JBS is not set
-+# CONFIG_DDB5477 is not set
-+# CONFIG_MACH_VR41XX is not set
-+# CONFIG_PMC_YOSEMITE is not set
-+# CONFIG_QEMU is not set
-+# CONFIG_SGI_IP22 is not set
-+# CONFIG_SGI_IP27 is not set
-+# CONFIG_SGI_IP32 is not set
-+# CONFIG_SIBYTE_BIGSUR is not set
-+# CONFIG_SIBYTE_SWARM is not set
-+# CONFIG_SIBYTE_SENTOSA is not set
-+# CONFIG_SIBYTE_RHONE is not set
-+# CONFIG_SIBYTE_CARMEL is not set
-+# CONFIG_SIBYTE_PTSWARM is not set
-+# CONFIG_SIBYTE_LITTLESUR is not set
-+# CONFIG_SIBYTE_CRHINE is not set
-+# CONFIG_SIBYTE_CRHONE is not set
-+# CONFIG_SNI_RM200_PCI is not set
-+# CONFIG_TOSHIBA_JMR3927 is not set
-+# CONFIG_TOSHIBA_RBTX4927 is not set
-+# CONFIG_TOSHIBA_RBTX4938 is not set
-+CONFIG_RWSEM_GENERIC_SPINLOCK=y
-+CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_DMA_NONCOHERENT=y
-+CONFIG_DMA_NEED_PCI_MAP_STATE=y
-+CONFIG_CPU_BIG_ENDIAN=y
-+# CONFIG_CPU_LITTLE_ENDIAN is not set
-+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
-+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-+CONFIG_IRQ_CPU=y
-+CONFIG_MIPS_GT64120=y
-+CONFIG_SWAP_IO_SPACE=y
-+CONFIG_BOOT_ELF32=y
-+CONFIG_MIPS_L1_CACHE_SHIFT=5
-+
-+#
-+# CPU selection
-+#
-+CONFIG_CPU_MIPS32_R1=y
-+# CONFIG_CPU_MIPS32_R2 is not set
-+# CONFIG_CPU_MIPS64_R1 is not set
-+# CONFIG_CPU_MIPS64_R2 is not set
-+# CONFIG_CPU_R3000 is not set
-+# CONFIG_CPU_TX39XX is not set
-+# CONFIG_CPU_VR41XX is not set
-+# CONFIG_CPU_R4300 is not set
-+# CONFIG_CPU_R4X00 is not set
-+# CONFIG_CPU_TX49XX is not set
-+# CONFIG_CPU_R5000 is not set
-+# CONFIG_CPU_R5432 is not set
-+# CONFIG_CPU_R6000 is not set
-+# CONFIG_CPU_NEVADA is not set
-+# CONFIG_CPU_R8000 is not set
-+# CONFIG_CPU_R10000 is not set
-+# CONFIG_CPU_RM7000 is not set
-+# CONFIG_CPU_RM9000 is not set
-+# CONFIG_CPU_SB1 is not set
-+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
-+CONFIG_SYS_HAS_CPU_MIPS64_R1=y
-+CONFIG_SYS_HAS_CPU_NEVADA=y
-+CONFIG_SYS_HAS_CPU_RM7000=y
-+CONFIG_CPU_MIPS32=y
-+CONFIG_CPU_MIPSR1=y
-+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
-+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-+
-+#
-+# Kernel type
-+#
-+CONFIG_32BIT=y
-+# CONFIG_64BIT is not set
-+CONFIG_PAGE_SIZE_4KB=y
-+# CONFIG_PAGE_SIZE_8KB is not set
-+# CONFIG_PAGE_SIZE_16KB is not set
-+# CONFIG_PAGE_SIZE_64KB is not set
-+CONFIG_CPU_HAS_PREFETCH=y
-+# CONFIG_MIPS_MT is not set
-+# CONFIG_64BIT_PHYS_ADDR is not set
-+# CONFIG_CPU_ADVANCED is not set
-+CONFIG_CPU_HAS_LLSC=y
-+CONFIG_CPU_HAS_SYNC=y
-+CONFIG_GENERIC_HARDIRQS=y
-+CONFIG_GENERIC_IRQ_PROBE=y
-+CONFIG_CPU_SUPPORTS_HIGHMEM=y
-+CONFIG_ARCH_FLATMEM_ENABLE=y
-+CONFIG_SELECT_MEMORY_MODEL=y
-+CONFIG_FLATMEM_MANUAL=y
-+# CONFIG_DISCONTIGMEM_MANUAL is not set
-+# CONFIG_SPARSEMEM_MANUAL is not set
-+CONFIG_FLATMEM=y
-+CONFIG_FLAT_NODE_MEM_MAP=y
-+# CONFIG_SPARSEMEM_STATIC is not set
-+CONFIG_SPLIT_PTLOCK_CPUS=4
-+CONFIG_PREEMPT_NONE=y
-+# CONFIG_PREEMPT_VOLUNTARY is not set
-+# CONFIG_PREEMPT is not set
-+
-+#
-+# Code maturity level options
-+#
-+CONFIG_EXPERIMENTAL=y
-+CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-+
-+#
-+# General setup
-+#
-+CONFIG_LOCALVERSION=""
-+CONFIG_LOCALVERSION_AUTO=y
-+# CONFIG_SWAP is not set
-+CONFIG_SYSVIPC=y
-+# CONFIG_POSIX_MQUEUE is not set
-+CONFIG_BSD_PROCESS_ACCT=y
-+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
-+CONFIG_SYSCTL=y
-+# CONFIG_AUDIT is not set
-+# CONFIG_IKCONFIG is not set
-+CONFIG_INITRAMFS_SOURCE=""
-+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-+CONFIG_EMBEDDED=y
-+CONFIG_KALLSYMS=y
-+CONFIG_KALLSYMS_EXTRA_PASS=y
-+CONFIG_HOTPLUG=y
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_ELF_CORE=y
-+CONFIG_BASE_FULL=y
-+CONFIG_FUTEX=y
-+# CONFIG_EPOLL is not set
-+CONFIG_SHMEM=y
-+CONFIG_CC_ALIGN_FUNCTIONS=0
-+CONFIG_CC_ALIGN_LABELS=0
-+CONFIG_CC_ALIGN_LOOPS=0
-+CONFIG_CC_ALIGN_JUMPS=0
-+CONFIG_SLAB=y
-+# CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=0
-+# CONFIG_SLOB is not set
-+
-+#
-+# Loadable module support
-+#
-+CONFIG_MODULES=y
-+CONFIG_MODULE_UNLOAD=y
-+# CONFIG_MODULE_FORCE_UNLOAD is not set
-+CONFIG_OBSOLETE_MODPARM=y
-+CONFIG_MODVERSIONS=y
-+CONFIG_MODULE_SRCVERSION_ALL=y
-+# CONFIG_KMOD is not set
-+
-+#
-+# Block layer
-+#
-+# CONFIG_LBD is not set
-+
-+#
-+# IO Schedulers
-+#
-+CONFIG_IOSCHED_NOOP=y
-+CONFIG_IOSCHED_AS=y
-+CONFIG_IOSCHED_DEADLINE=y
-+CONFIG_IOSCHED_CFQ=y
-+CONFIG_DEFAULT_AS=y
-+# CONFIG_DEFAULT_DEADLINE is not set
-+# CONFIG_DEFAULT_CFQ is not set
-+# CONFIG_DEFAULT_NOOP is not set
-+CONFIG_DEFAULT_IOSCHED="anticipatory"
-+
-+#
-+# Bus options (PCI, PCMCIA, EISA, ISA, TC)
-+#
-+CONFIG_HW_HAS_PCI=y
-+CONFIG_PCI=y
-+CONFIG_PCI_LEGACY_PROC=y
-+CONFIG_MMU=y
-+
-+#
-+# PCCARD (PCMCIA/CardBus) support
-+#
-+# CONFIG_PCCARD is not set
-+
-+#
-+# PCI Hotplug Support
-+#
-+CONFIG_HOTPLUG_PCI=y
-+# CONFIG_HOTPLUG_PCI_FAKE is not set
-+# CONFIG_HOTPLUG_PCI_CPCI is not set
-+# CONFIG_HOTPLUG_PCI_SHPC is not set
-+
-+#
-+# Executable file formats
-+#
-+CONFIG_BINFMT_ELF=y
-+CONFIG_BINFMT_MISC=y
-+CONFIG_TRAD_SIGNALS=y
-+
-+#
-+# Networking
-+#
-+CONFIG_NET=y
-+
-+#
-+# Networking options
-+#
-+# CONFIG_NETDEBUG is not set
-+CONFIG_PACKET=y
-+CONFIG_PACKET_MMAP=y
-+CONFIG_UNIX=y
-+# CONFIG_NET_KEY is not set
-+CONFIG_INET=y
-+CONFIG_IP_MULTICAST=y
-+# CONFIG_IP_ADVANCED_ROUTER is not set
-+CONFIG_IP_FIB_HASH=y
-+CONFIG_IP_PNP=y
-+CONFIG_IP_PNP_DHCP=y
-+CONFIG_IP_PNP_BOOTP=y
-+CONFIG_IP_PNP_RARP=y
-+# CONFIG_NET_IPIP is not set
-+# CONFIG_NET_IPGRE is not set
-+CONFIG_IP_MROUTE=y
-+# CONFIG_IP_PIMSM_V1 is not set
-+# CONFIG_IP_PIMSM_V2 is not set
-+CONFIG_ARPD=y
-+# CONFIG_SYN_COOKIES is not set
-+# CONFIG_INET_AH is not set
-+# CONFIG_INET_ESP is not set
-+# CONFIG_INET_IPCOMP is not set
-+# CONFIG_INET_TUNNEL is not set
-+CONFIG_INET_DIAG=y
-+CONFIG_INET_TCP_DIAG=y
-+# CONFIG_TCP_CONG_ADVANCED is not set
-+CONFIG_TCP_CONG_BIC=y
-+# CONFIG_IPV6 is not set
-+# CONFIG_NETFILTER is not set
-+
-+#
-+# DCCP Configuration (EXPERIMENTAL)
-+#
-+# CONFIG_IP_DCCP is not set
-+
-+#
-+# SCTP Configuration (EXPERIMENTAL)
-+#
-+# CONFIG_IP_SCTP is not set
-+
-+#
-+# TIPC Configuration (EXPERIMENTAL)
-+#
-+# CONFIG_TIPC is not set
-+# CONFIG_ATM is not set
-+# CONFIG_BRIDGE is not set
-+# CONFIG_VLAN_8021Q is not set
-+# CONFIG_DECNET is not set
-+# CONFIG_LLC2 is not set
-+# CONFIG_IPX is not set
-+# CONFIG_ATALK is not set
-+# CONFIG_X25 is not set
-+# CONFIG_LAPB is not set
-+# CONFIG_NET_DIVERT is not set
-+# CONFIG_ECONET is not set
-+# CONFIG_WAN_ROUTER is not set
-+
-+#
-+# QoS and/or fair queueing
-+#
-+# CONFIG_NET_SCHED is not set
-+
-+#
-+# Network testing
-+#
-+# CONFIG_NET_PKTGEN is not set
-+# CONFIG_HAMRADIO is not set
-+# CONFIG_IRDA is not set
-+# CONFIG_BT is not set
-+# CONFIG_IEEE80211 is not set
-+
-+#
-+# Device Drivers
-+#
-+
-+#
-+# Generic Driver Options
-+#
-+CONFIG_STANDALONE=y
-+CONFIG_PREVENT_FIRMWARE_BUILD=y
-+# CONFIG_FW_LOADER is not set
-+
-+#
-+# Connector - unified userspace <-> kernelspace linker
-+#
-+# CONFIG_CONNECTOR is not set
-+
-+#
-+# Memory Technology Devices (MTD)
-+#
-+# CONFIG_MTD is not set
-+
-+#
-+# Parallel port support
-+#
-+# CONFIG_PARPORT is not set
-+
-+#
-+# Plug and Play support
-+#
-+
-+#
-+# Block devices
-+#
-+# CONFIG_BLK_CPQ_DA is not set
-+# CONFIG_BLK_CPQ_CISS_DA is not set
-+# CONFIG_BLK_DEV_DAC960 is not set
-+# CONFIG_BLK_DEV_UMEM is not set
-+# CONFIG_BLK_DEV_COW_COMMON is not set
-+# CONFIG_BLK_DEV_LOOP is not set
-+# CONFIG_BLK_DEV_NBD is not set
-+# CONFIG_BLK_DEV_SX8 is not set
-+CONFIG_BLK_DEV_RAM=y
-+CONFIG_BLK_DEV_RAM_COUNT=16
-+CONFIG_BLK_DEV_RAM_SIZE=4096
-+CONFIG_BLK_DEV_INITRD=y
-+# CONFIG_CDROM_PKTCDVD is not set
-+# CONFIG_ATA_OVER_ETH is not set
-+
-+#
-+# ATA/ATAPI/MFM/RLL support
-+#
-+# CONFIG_IDE is not set
-+
-+#
-+# SCSI device support
-+#
-+# CONFIG_RAID_ATTRS is not set
-+# CONFIG_SCSI is not set
-+
-+#
-+# Multi-device support (RAID and LVM)
-+#
-+# CONFIG_MD is not set
-+
-+#
-+# Fusion MPT device support
-+#
-+# CONFIG_FUSION is not set
-+
-+#
-+# IEEE 1394 (FireWire) support
-+#
-+# CONFIG_IEEE1394 is not set
-+
-+#
-+# I2O device support
-+#
-+# CONFIG_I2O is not set
-+
-+#
-+# Network device support
-+#
-+CONFIG_NETDEVICES=y
-+# CONFIG_DUMMY is not set
-+# CONFIG_BONDING is not set
-+# CONFIG_EQUALIZER is not set
-+# CONFIG_TUN is not set
-+
-+#
-+# ARCnet devices
-+#
-+# CONFIG_ARCNET is not set
-+
-+#
-+# PHY device support
-+#
-+CONFIG_PHYLIB=y
-+
-+#
-+# MII PHY device drivers
-+#
-+# CONFIG_MARVELL_PHY is not set
-+# CONFIG_DAVICOM_PHY is not set
-+# CONFIG_QSEMI_PHY is not set
-+# CONFIG_LXT_PHY is not set
-+# CONFIG_CICADA_PHY is not set
-+
-+#
-+# Ethernet (10 or 100Mbit)
-+#
-+CONFIG_NET_ETHERNET=y
-+CONFIG_MII=y
-+# CONFIG_HAPPYMEAL is not set
-+# CONFIG_SUNGEM is not set
-+# CONFIG_CASSINI is not set
-+# CONFIG_NET_VENDOR_3COM is not set
-+# CONFIG_DM9000 is not set
-+
-+#
-+# Tulip family network device support
-+#
-+# CONFIG_NET_TULIP is not set
-+# CONFIG_HP100 is not set
-+CONFIG_NET_PCI=y
-+# CONFIG_PCNET32 is not set
-+# CONFIG_AMD8111_ETH is not set
-+# CONFIG_ADAPTEC_STARFIRE is not set
-+# CONFIG_B44 is not set
-+# CONFIG_FORCEDETH is not set
-+# CONFIG_DGRS is not set
-+# CONFIG_EEPRO100 is not set
-+CONFIG_E100=y
-+# CONFIG_FEALNX is not set
-+# CONFIG_NATSEMI is not set
-+# CONFIG_NE2K_PCI is not set
-+# CONFIG_8139CP is not set
-+# CONFIG_8139TOO is not set
-+# CONFIG_SIS900 is not set
-+# CONFIG_EPIC100 is not set
-+# CONFIG_SUNDANCE is not set
-+# CONFIG_TLAN is not set
-+# CONFIG_VIA_RHINE is not set
-+# CONFIG_LAN_SAA9730 is not set
-+
-+#
-+# Ethernet (1000 Mbit)
-+#
-+# CONFIG_ACENIC is not set
-+# CONFIG_DL2K is not set
-+# CONFIG_E1000 is not set
-+# CONFIG_NS83820 is not set
-+# CONFIG_HAMACHI is not set
-+# CONFIG_YELLOWFIN is not set
-+# CONFIG_R8169 is not set
-+# CONFIG_SIS190 is not set
-+# CONFIG_SKGE is not set
-+# CONFIG_SKY2 is not set
-+# CONFIG_SK98LIN is not set
-+# CONFIG_VIA_VELOCITY is not set
-+# CONFIG_TIGON3 is not set
-+# CONFIG_BNX2 is not set
-+
-+#
-+# Ethernet (10000 Mbit)
-+#
-+# CONFIG_CHELSIO_T1 is not set
-+# CONFIG_IXGB is not set
-+# CONFIG_S2IO is not set
-+
-+#
-+# Token Ring devices
-+#
-+# CONFIG_TR is not set
-+
-+#
-+# Wireless LAN (non-hamradio)
-+#
-+# CONFIG_NET_RADIO is not set
-+
-+#
-+# Wan interfaces
-+#
-+# CONFIG_WAN is not set
-+# CONFIG_FDDI is not set
-+# CONFIG_HIPPI is not set
-+# CONFIG_PPP is not set
-+# CONFIG_SLIP is not set
-+# CONFIG_SHAPER is not set
-+# CONFIG_NETCONSOLE is not set
-+# CONFIG_NETPOLL is not set
-+# CONFIG_NET_POLL_CONTROLLER is not set
-+
-+#
-+# ISDN subsystem
-+#
-+# CONFIG_ISDN is not set
-+
-+#
-+# Telephony Support
-+#
-+# CONFIG_PHONE is not set
-+
-+#
-+# Input device support
-+#
-+# CONFIG_INPUT is not set
-+
-+#
-+# Hardware I/O ports
-+#
-+# CONFIG_SERIO is not set
-+# CONFIG_GAMEPORT is not set
-+
-+#
-+# Character devices
-+#
-+# CONFIG_VT is not set
-+# CONFIG_SERIAL_NONSTANDARD is not set
-+
-+#
-+# Serial drivers
-+#
-+CONFIG_SERIAL_8250=y
-+CONFIG_SERIAL_8250_CONSOLE=y
-+CONFIG_SERIAL_8250_NR_UARTS=1
-+CONFIG_SERIAL_8250_RUNTIME_UARTS=1
-+# CONFIG_SERIAL_8250_EXTENDED is not set
-+
-+#
-+# Non-8250 serial port support
-+#
-+CONFIG_SERIAL_CORE=y
-+CONFIG_SERIAL_CORE_CONSOLE=y
-+# CONFIG_SERIAL_JSM is not set
-+CONFIG_UNIX98_PTYS=y
-+CONFIG_LEGACY_PTYS=y
-+CONFIG_LEGACY_PTY_COUNT=256
-+
-+#
-+# IPMI
-+#
-+# CONFIG_IPMI_HANDLER is not set
-+
-+#
-+# Watchdog Cards
-+#
-+# CONFIG_WATCHDOG is not set
-+CONFIG_RTC=y
-+# CONFIG_DTLK is not set
-+# CONFIG_R3964 is not set
-+# CONFIG_APPLICOM is not set
-+
-+#
-+# Ftape, the floppy tape device driver
-+#
-+# CONFIG_DRM is not set
-+# CONFIG_RAW_DRIVER is not set
-+
-+#
-+# TPM devices
-+#
-+# CONFIG_TCG_TPM is not set
-+# CONFIG_TELCLOCK is not set
-+
-+#
-+# I2C support
-+#
-+# CONFIG_I2C is not set
-+
-+#
-+# SPI support
-+#
-+# CONFIG_SPI is not set
-+# CONFIG_SPI_MASTER is not set
-+
-+#
-+# Dallas's 1-wire bus
-+#
-+# CONFIG_W1 is not set
-+
-+#
-+# Hardware Monitoring support
-+#
-+CONFIG_HWMON=y
-+# CONFIG_HWMON_VID is not set
-+# CONFIG_SENSORS_F71805F is not set
-+# CONFIG_HWMON_DEBUG_CHIP is not set
-+
-+#
-+# Misc devices
-+#
-+
-+#
-+# Multimedia Capabilities Port drivers
-+#
-+
-+#
-+# Multimedia devices
-+#
-+# CONFIG_VIDEO_DEV is not set
-+
-+#
-+# Digital Video Broadcasting Devices
-+#
-+# CONFIG_DVB is not set
-+
-+#
-+# Graphics support
-+#
-+# CONFIG_FB is not set
-+
-+#
-+# Sound
-+#
-+# CONFIG_SOUND is not set
-+
-+#
-+# USB support
-+#
-+CONFIG_USB_ARCH_HAS_HCD=y
-+CONFIG_USB_ARCH_HAS_OHCI=y
-+# CONFIG_USB is not set
-+
-+#
-+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-+#
-+
-+#
-+# USB Gadget Support
-+#
-+# CONFIG_USB_GADGET is not set
-+
-+#
-+# MMC/SD Card support
-+#
-+# CONFIG_MMC is not set
-+
-+#
-+# InfiniBand support
-+#
-+# CONFIG_INFINIBAND is not set
-+
-+#
-+# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
-+#
-+
-+#
-+# File systems
-+#
-+# CONFIG_EXT2_FS is not set
-+# CONFIG_EXT3_FS is not set
-+# CONFIG_REISERFS_FS is not set
-+# CONFIG_JFS_FS is not set
-+# CONFIG_FS_POSIX_ACL is not set
-+# CONFIG_XFS_FS is not set
-+# CONFIG_OCFS2_FS is not set
-+# CONFIG_MINIX_FS is not set
-+# CONFIG_ROMFS_FS is not set
-+CONFIG_INOTIFY=y
-+# CONFIG_QUOTA is not set
-+CONFIG_DNOTIFY=y
-+# CONFIG_AUTOFS_FS is not set
-+# CONFIG_AUTOFS4_FS is not set
-+# CONFIG_FUSE_FS is not set
-+
-+#
-+# CD-ROM/DVD Filesystems
-+#
-+# CONFIG_ISO9660_FS is not set
-+# CONFIG_UDF_FS is not set
-+
-+#
-+# DOS/FAT/NT Filesystems
-+#
-+# CONFIG_MSDOS_FS is not set
-+# CONFIG_VFAT_FS is not set
-+# CONFIG_NTFS_FS is not set
-+
-+#
-+# Pseudo filesystems
-+#
-+CONFIG_PROC_FS=y
-+CONFIG_PROC_KCORE=y
-+CONFIG_SYSFS=y
-+CONFIG_TMPFS=y
-+# CONFIG_HUGETLB_PAGE is not set
-+CONFIG_RAMFS=y
-+# CONFIG_RELAYFS_FS is not set
-+# CONFIG_CONFIGFS_FS is not set
-+
-+#
-+# Miscellaneous filesystems
-+#
-+# CONFIG_ADFS_FS is not set
-+# CONFIG_AFFS_FS is not set
-+# CONFIG_HFS_FS is not set
-+# CONFIG_HFSPLUS_FS is not set
-+# CONFIG_BEFS_FS is not set
-+# CONFIG_BFS_FS is not set
-+# CONFIG_EFS_FS is not set
-+# CONFIG_CRAMFS is not set
-+# CONFIG_VXFS_FS is not set
-+# CONFIG_HPFS_FS is not set
-+# CONFIG_QNX4FS_FS is not set
-+# CONFIG_SYSV_FS is not set
-+# CONFIG_UFS_FS is not set
-+
-+#
-+# Network File Systems
-+#
-+CONFIG_NFS_FS=y
-+CONFIG_NFS_V3=y
-+# CONFIG_NFS_V3_ACL is not set
-+# CONFIG_NFS_V4 is not set
-+# CONFIG_NFS_DIRECTIO is not set
-+# CONFIG_NFSD is not set
-+CONFIG_ROOT_NFS=y
-+CONFIG_LOCKD=y
-+CONFIG_LOCKD_V4=y
-+CONFIG_NFS_COMMON=y
-+CONFIG_SUNRPC=y
-+# CONFIG_RPCSEC_GSS_KRB5 is not set
-+# CONFIG_RPCSEC_GSS_SPKM3 is not set
-+# CONFIG_SMB_FS is not set
-+# CONFIG_CIFS is not set
-+# CONFIG_NCP_FS is not set
-+# CONFIG_CODA_FS is not set
-+# CONFIG_AFS_FS is not set
-+# CONFIG_9P_FS is not set
-+
-+#
-+# Partition Types
-+#
-+# CONFIG_PARTITION_ADVANCED is not set
-+CONFIG_MSDOS_PARTITION=y
-+
-+#
-+# Native Language Support
-+#
-+# CONFIG_NLS is not set
-+
-+#
-+# Profiling support
-+#
-+# CONFIG_PROFILING is not set
-+
-+#
-+# Kernel hacking
-+#
-+# CONFIG_PRINTK_TIME is not set
-+# CONFIG_MAGIC_SYSRQ is not set
-+# CONFIG_DEBUG_KERNEL is not set
-+CONFIG_LOG_BUF_SHIFT=14
-+CONFIG_CROSSCOMPILE=y
-+CONFIG_CMDLINE="console=ttyS0,115200n8"
-+
-+#
-+# Security options
-+#
-+# CONFIG_KEYS is not set
-+# CONFIG_SECURITY is not set
-+
-+#
-+# Cryptographic options
-+#
-+# CONFIG_CRYPTO is not set
-+
-+#
-+# Hardware crypto devices
-+#
-+
-+#
-+# Library routines
-+#
-+CONFIG_CRC_CCITT=y
-+CONFIG_CRC16=y
-+CONFIG_CRC32=y
-+CONFIG_LIBCRC32C=y
-diff -Naur linux-2.6.17.orig/arch/mips/configs/yosemite_defconfig linux-2.6.17/arch/mips/configs/yosemite_defconfig
---- linux-2.6.17.orig/arch/mips/configs/yosemite_defconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/configs/yosemite_defconfig	2006-06-19 18:16:13.000000000 -0700
-@@ -41,8 +41,6 @@
- # CONFIG_MIPS_XXS1500 is not set
- # CONFIG_PNX8550_V2PCI is not set
- # CONFIG_PNX8550_JBS is not set
--# CONFIG_DDB5074 is not set
--# CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
- # CONFIG_MACH_VR41XX is not set
- CONFIG_PMC_YOSEMITE=y
-@@ -68,6 +66,7 @@
- CONFIG_GENERIC_FIND_NEXT_BIT=y
- CONFIG_GENERIC_HWEIGHT=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
- CONFIG_DMA_COHERENT=y
- CONFIG_CPU_BIG_ENDIAN=y
- # CONFIG_CPU_LITTLE_ENDIAN is not set
-diff -Naur linux-2.6.17.orig/arch/mips/ddb5xxx/common/prom.c linux-2.6.17/arch/mips/ddb5xxx/common/prom.c
---- linux-2.6.17.orig/arch/mips/ddb5xxx/common/prom.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/ddb5xxx/common/prom.c	2006-06-19 18:16:13.000000000 -0700
-@@ -56,13 +56,7 @@
- 
- 	mips_machgroup = MACH_GROUP_NEC_DDB;
- 
--#if defined(CONFIG_DDB5074)
--	mips_machtype = MACH_NEC_DDB5074;
--	add_memory_region(0, DDB_SDRAM_SIZE, BOOT_MEM_RAM);
--#elif defined(CONFIG_DDB5476)
--	mips_machtype = MACH_NEC_DDB5476;
--	add_memory_region(0, DDB_SDRAM_SIZE, BOOT_MEM_RAM);
--#elif defined(CONFIG_DDB5477)
-+#if defined(CONFIG_DDB5477)
- 	ddb5477_runtime_detection();
- 	add_memory_region(0, board_ram_size, BOOT_MEM_RAM);
- #endif
-diff -Naur linux-2.6.17.orig/arch/mips/ddb5xxx/ddb5074/irq.c linux-2.6.17/arch/mips/ddb5xxx/ddb5074/irq.c
---- linux-2.6.17.orig/arch/mips/ddb5xxx/ddb5074/irq.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/ddb5xxx/ddb5074/irq.c	1969-12-31 16:00:00.000000000 -0800
-@@ -1,169 +0,0 @@
--/*
-- *  arch/mips/ddb5074/irq.c -- NEC DDB Vrc-5074 interrupt routines
-- *
-- *  Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
-- *                     Sony Software Development Center Europe (SDCE), Brussels
-- */
--#include <linux/init.h>
--#include <linux/irq.h>
--#include <linux/signal.h>
--#include <linux/sched.h>
--#include <linux/types.h>
--#include <linux/interrupt.h>
--#include <linux/ioport.h>
--
--#include <asm/i8259.h>
--#include <asm/io.h>
--#include <asm/irq_cpu.h>
--#include <asm/ptrace.h>
--#include <asm/nile4.h>
--#include <asm/ddb5xxx/ddb5xxx.h>
--#include <asm/ddb5xxx/ddb5074.h>
--
--
--static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL };
--
--#define M1543_PNP_CONFIG	0x03f0	/* PnP Config Port */
--#define M1543_PNP_INDEX		0x03f0	/* PnP Index Port */
--#define M1543_PNP_DATA		0x03f1	/* PnP Data Port */
--
--#define M1543_PNP_ALT_CONFIG	0x0370	/* Alternative PnP Config Port */
--#define M1543_PNP_ALT_INDEX	0x0370	/* Alternative PnP Index Port */
--#define M1543_PNP_ALT_DATA	0x0371	/* Alternative PnP Data Port */
--
--#define M1543_INT1_MASTER_CTRL	0x0020	/* INT_1 (master) Control Register */
--#define M1543_INT1_MASTER_MASK	0x0021	/* INT_1 (master) Mask Register */
--
--#define M1543_INT1_SLAVE_CTRL	0x00a0	/* INT_1 (slave) Control Register */
--#define M1543_INT1_SLAVE_MASK	0x00a1	/* INT_1 (slave) Mask Register */
--
--#define M1543_INT1_MASTER_ELCR	0x04d0	/* INT_1 (master) Edge/Level Control */
--#define M1543_INT1_SLAVE_ELCR	0x04d1	/* INT_1 (slave) Edge/Level Control */
--
--
--static void m1543_irq_setup(void)
--{
--	/*
--	 *  The ALI M1543 has 13 interrupt inputs, IRQ1..IRQ13.  Not all
--	 *  the possible IO sources in the M1543 are in use by us.  We will
--	 *  use the following mapping:
--	 *
--	 *      IRQ1  - keyboard (default set by M1543)
--	 *      IRQ3  - reserved for UART B (default set by M1543) (note that
--	 *              the schematics for the DDB Vrc-5074 board seem to
--	 *              indicate that IRQ3 is connected to the DS1386
--	 *              watchdog timer interrupt output so we might have
--	 *              a conflict)
--	 *      IRQ4  - reserved for UART A (default set by M1543)
--	 *      IRQ5  - parallel (default set by M1543)
--	 *      IRQ8  - DS1386 time of day (RTC) interrupt
--	 *      IRQ12 - mouse
--	 */
--
--	/*
--	 *  Assing mouse interrupt to IRQ12
--	 */
--
--	/* Enter configuration mode */
--	outb(0x51, M1543_PNP_CONFIG);
--	outb(0x23, M1543_PNP_CONFIG);
--
--	/* Select logical device 7 (Keyboard) */
--	outb(0x07, M1543_PNP_INDEX);
--	outb(0x07, M1543_PNP_DATA);
--
--	/* Select IRQ12 */
--	outb(0x72, M1543_PNP_INDEX);
--	outb(0x0c, M1543_PNP_DATA);
--
--	outb(0x30, M1543_PNP_INDEX);
--	printk("device 7, 0x30: %02x\n",inb(M1543_PNP_DATA));
--
--	outb(0x70, M1543_PNP_INDEX);
--	printk("device 7, 0x70: %02x\n",inb(M1543_PNP_DATA));
--
--	/* Leave configration mode */
--	outb(0xbb, M1543_PNP_CONFIG);
--
--
--}
--
--static void ddb_local0_irqdispatch(struct pt_regs *regs)
--{
--	u32 mask;
--	int nile4_irq;
--
--	mask = nile4_get_irq_stat(0);
--
--	/* Handle the timer interrupt first */
--#if 0
--	if (mask & (1 << NILE4_INT_GPT)) {
--		do_IRQ(nile4_to_irq(NILE4_INT_GPT), regs);
--		mask &= ~(1 << NILE4_INT_GPT);
--	}
--#endif
--	for (nile4_irq = 0; mask; nile4_irq++, mask >>= 1)
--		if (mask & 1) {
--			if (nile4_irq == NILE4_INT_INTE) {
--				int i8259_irq;
--
--				nile4_clear_irq(NILE4_INT_INTE);
--				i8259_irq = nile4_i8259_iack();
--				do_IRQ(i8259_irq, regs);
--			} else
--				do_IRQ(nile4_to_irq(nile4_irq), regs);
--
--		}
--}
--
--static void ddb_local1_irqdispatch(void)
--{
--	printk("ddb_local1_irqdispatch called\n");
--}
--
--static void ddb_buserror_irq(void)
--{
--	printk("ddb_buserror_irq called\n");
--}
--
--static void ddb_8254timer_irq(void)
--{
--	printk("ddb_8254timer_irq called\n");
--}
--
--asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
--{
--	unsigned int pending = read_c0_cause() & read_c0_status();
--
--	if (pending & CAUSEF_IP2)
--		ddb_local0_irqdispatch(regs);
--	else if (pending & CAUSEF_IP3)
--		ddb_local1_irqdispatch();
--	else if (pending & CAUSEF_IP6)
--		ddb_buserror_irq();
--	else if (pending & (CAUSEF_IP4 | CAUSEF_IP5))
--		ddb_8254timer_irq();
--}
--
--void __init arch_init_irq(void)
--{
--	/* setup cascade interrupts */
--	setup_irq(NILE4_IRQ_BASE  + NILE4_INT_INTE, &irq_cascade);
--	setup_irq(CPU_IRQ_BASE + CPU_NILE4_CASCADE, &irq_cascade);
--
--	nile4_irq_setup(NILE4_IRQ_BASE);
--	m1543_irq_setup();
--	init_i8259_irqs();
--
--
--	printk("CPU_IRQ_BASE: %d\n",CPU_IRQ_BASE);
--
--	mips_cpu_irq_init(CPU_IRQ_BASE);
--
--	printk("enabling 8259 cascade\n");
--
--	ddb5074_led_hex(0);
--
--	/* Enable the interrupt cascade */
--	nile4_enable_irq(NILE4_IRQ_BASE+IRQ_I8259_CASCADE);
--}
-diff -Naur linux-2.6.17.orig/arch/mips/ddb5xxx/ddb5074/Makefile linux-2.6.17/arch/mips/ddb5xxx/ddb5074/Makefile
---- linux-2.6.17.orig/arch/mips/ddb5xxx/ddb5074/Makefile	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/ddb5xxx/ddb5074/Makefile	1969-12-31 16:00:00.000000000 -0800
-@@ -1,8 +0,0 @@
--#
--# Makefile for the NEC DDB Vrc-5074 specific kernel interface routines
--# under Linux.
--#
--
--obj-y			+= setup.o irq.o nile4_pic.o
--
--EXTRA_AFLAGS := $(CFLAGS)
-diff -Naur linux-2.6.17.orig/arch/mips/ddb5xxx/ddb5074/nile4_pic.c linux-2.6.17/arch/mips/ddb5xxx/ddb5074/nile4_pic.c
---- linux-2.6.17.orig/arch/mips/ddb5xxx/ddb5074/nile4_pic.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/ddb5xxx/ddb5074/nile4_pic.c	1969-12-31 16:00:00.000000000 -0800
-@@ -1,286 +0,0 @@
--/*
-- *  arch/mips/ddb5476/nile4.c --
-- *  	low-level PIC code for NEC Vrc-5476 (Nile 4)
-- *
-- *  Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
-- *                     Sony Software Development Center Europe (SDCE), Brussels
-- *
-- *  Copyright 2001 MontaVista Software Inc.
-- *  Author: jsun@mvista.com or jsun@junsun.net
-- *
-- */
--#include <linux/config.h>
--#include <linux/kernel.h>
--#include <linux/types.h>
--#include <linux/interrupt.h>
--#include <linux/ioport.h>
--
--#include <asm/addrspace.h>
--
--#include <asm/ddb5xxx/ddb5xxx.h>
--
--static int irq_base;
--
--/*
-- *  Interrupt Programming
-- */
--void nile4_map_irq(int nile4_irq, int cpu_irq)
--{
--	u32 offset, t;
--
--	offset = DDB_INTCTRL;
--	if (nile4_irq >= 8) {
--		offset += 4;
--		nile4_irq -= 8;
--	}
--	t = ddb_in32(offset);
--	t &= ~(7 << (nile4_irq * 4));
--	t |= cpu_irq << (nile4_irq * 4);
--	ddb_out32(offset, t);
--}
--
--void nile4_map_irq_all(int cpu_irq)
--{
--	u32 all, t;
--
--	all = cpu_irq;
--	all |= all << 4;
--	all |= all << 8;
--	all |= all << 16;
--	t = ddb_in32(DDB_INTCTRL);
--	t &= 0x88888888;
--	t |= all;
--	ddb_out32(DDB_INTCTRL, t);
--	t = ddb_in32(DDB_INTCTRL + 4);
--	t &= 0x88888888;
--	t |= all;
--	ddb_out32(DDB_INTCTRL + 4, t);
--}
--
--void nile4_enable_irq(unsigned int nile4_irq)
--{
--	u32 offset, t;
--
--	nile4_irq-=irq_base;
--
--	ddb5074_led_hex(8);
--
--	offset = DDB_INTCTRL;
--	if (nile4_irq >= 8) {
--		offset += 4;
--		nile4_irq -= 8;
--	}
--	ddb5074_led_hex(9);
--	t = ddb_in32(offset);
--	ddb5074_led_hex(0xa);
--	t |= 8 << (nile4_irq * 4);
--	ddb_out32(offset, t);
--	ddb5074_led_hex(0xb);
--}
--
--void nile4_disable_irq(unsigned int nile4_irq)
--{
--	u32 offset, t;
--
--	nile4_irq-=irq_base;
--
--	offset = DDB_INTCTRL;
--	if (nile4_irq >= 8) {
--		offset += 4;
--		nile4_irq -= 8;
--	}
--	t = ddb_in32(offset);
--	t &= ~(8 << (nile4_irq * 4));
--	ddb_out32(offset, t);
--}
--
--void nile4_disable_irq_all(void)
--{
--	ddb_out32(DDB_INTCTRL, 0);
--	ddb_out32(DDB_INTCTRL + 4, 0);
--}
--
--u16 nile4_get_irq_stat(int cpu_irq)
--{
--	return ddb_in16(DDB_INTSTAT0 + cpu_irq * 2);
--}
--
--void nile4_enable_irq_output(int cpu_irq)
--{
--	u32 t;
--
--	t = ddb_in32(DDB_INTSTAT1 + 4);
--	t |= 1 << (16 + cpu_irq);
--	ddb_out32(DDB_INTSTAT1, t);
--}
--
--void nile4_disable_irq_output(int cpu_irq)
--{
--	u32 t;
--
--	t = ddb_in32(DDB_INTSTAT1 + 4);
--	t &= ~(1 << (16 + cpu_irq));
--	ddb_out32(DDB_INTSTAT1, t);
--}
--
--void nile4_set_pci_irq_polarity(int pci_irq, int high)
--{
--	u32 t;
--
--	t = ddb_in32(DDB_INTPPES);
--	if (high)
--		t &= ~(1 << (pci_irq * 2));
--	else
--		t |= 1 << (pci_irq * 2);
--	ddb_out32(DDB_INTPPES, t);
--}
--
--void nile4_set_pci_irq_level_or_edge(int pci_irq, int level)
--{
--	u32 t;
--
--	t = ddb_in32(DDB_INTPPES);
--	if (level)
--		t |= 2 << (pci_irq * 2);
--	else
--		t &= ~(2 << (pci_irq * 2));
--	ddb_out32(DDB_INTPPES, t);
--}
--
--void nile4_clear_irq(int nile4_irq)
--{
--	nile4_irq-=irq_base;
--	ddb_out32(DDB_INTCLR, 1 << nile4_irq);
--}
--
--void nile4_clear_irq_mask(u32 mask)
--{
--	ddb_out32(DDB_INTCLR, mask);
--}
--
--u8 nile4_i8259_iack(void)
--{
--	u8 irq;
--	u32 reg;
--
--	/* Set window 0 for interrupt acknowledge */
--	reg = ddb_in32(DDB_PCIINIT0);
--
--	ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IACK, 0, DDB_PCI_ACCESS_32);
--	irq = *(volatile u8 *) KSEG1ADDR(DDB_PCI_IACK_BASE);
--	/* restore window 0 for PCI I/O space */
--	// ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32);
--	ddb_out32(DDB_PCIINIT0, reg);
--
--	/* i8269.c set the base vector to be 0x0 */
--	return irq ;
--}
--
--static unsigned int nile4_irq_startup(unsigned int irq) {
--
--	nile4_enable_irq(irq);
--	return 0;
--
--}
--
--static void nile4_ack_irq(unsigned int irq) {
--
--    ddb5074_led_hex(4);
--
--	nile4_clear_irq(irq);
--    ddb5074_led_hex(2);
--	nile4_disable_irq(irq);
--
--    ddb5074_led_hex(0);
--}
--
--static void nile4_irq_end(unsigned int irq) {
--
--	ddb5074_led_hex(3);
--	if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
--	ddb5074_led_hex(5);
--		nile4_enable_irq(irq);
--	ddb5074_led_hex(7);
--	}
--
--	ddb5074_led_hex(1);
--}
--
--#define nile4_irq_shutdown nile4_disable_irq
--
--static hw_irq_controller nile4_irq_controller = {
--	.typename = "nile4",
--	.startup = nile4_irq_startup,
--	.shutdown = nile4_irq_shutdown,
--	.enable = nile4_enable_irq,
--	.disable = nile4_disable_irq,
--	.ack = nile4_ack_irq,
--	.end = nile4_irq_end,
--};
--
--void nile4_irq_setup(u32 base) {
--
--	int i;
--
--	irq_base=base;
--
--	/* Map all interrupts to CPU int #0 */
--	nile4_map_irq_all(0);
--
--	/* PCI INTA#-E# must be level triggered */
--	nile4_set_pci_irq_level_or_edge(0, 1);
--	nile4_set_pci_irq_level_or_edge(1, 1);
--	nile4_set_pci_irq_level_or_edge(2, 1);
--	nile4_set_pci_irq_level_or_edge(3, 1);
--	nile4_set_pci_irq_level_or_edge(4, 1);
--
--	/* PCI INTA#-D# must be active low, INTE# must be active high */
--	nile4_set_pci_irq_polarity(0, 0);
--	nile4_set_pci_irq_polarity(1, 0);
--	nile4_set_pci_irq_polarity(2, 0);
--	nile4_set_pci_irq_polarity(3, 0);
--	nile4_set_pci_irq_polarity(4, 1);
--
--
--	for (i = 0; i < 16; i++) {
--		nile4_clear_irq(i);
--		nile4_disable_irq(i);
--	}
--
--	/* Enable CPU int #0 */
--	nile4_enable_irq_output(0);
--
--	for (i= base; i< base + NUM_NILE4_INTERRUPTS; i++) {
--		irq_desc[i].status = IRQ_DISABLED;
--		irq_desc[i].action = NULL;
--		irq_desc[i].depth = 1;
--		irq_desc[i].handler = &nile4_irq_controller;
--	}
--}
--
--#if defined(CONFIG_RUNTIME_DEBUG)
--void nile4_dump_irq_status(void)
--{
--	printk(KERN_DEBUG "
--	       CPUSTAT = %p:%p\n", (void *) ddb_in32(DDB_CPUSTAT + 4),
--	       (void *) ddb_in32(DDB_CPUSTAT));
--	printk(KERN_DEBUG "
--	       INTCTRL = %p:%p\n", (void *) ddb_in32(DDB_INTCTRL + 4),
--	       (void *) ddb_in32(DDB_INTCTRL));
--	printk(KERN_DEBUG
--	       "INTSTAT0 = %p:%p\n",
--	       (void *) ddb_in32(DDB_INTSTAT0 + 4),
--	       (void *) ddb_in32(DDB_INTSTAT0));
--	printk(KERN_DEBUG
--	       "INTSTAT1 = %p:%p\n",
--	       (void *) ddb_in32(DDB_INTSTAT1 + 4),
--	       (void *) ddb_in32(DDB_INTSTAT1));
--	printk(KERN_DEBUG
--	       "INTCLR = %p:%p\n", (void *) ddb_in32(DDB_INTCLR + 4),
--	       (void *) ddb_in32(DDB_INTCLR));
--	printk(KERN_DEBUG
--	       "INTPPES = %p:%p\n", (void *) ddb_in32(DDB_INTPPES + 4),
--	       (void *) ddb_in32(DDB_INTPPES));
--}
--
--#endif
-diff -Naur linux-2.6.17.orig/arch/mips/ddb5xxx/ddb5074/setup.c linux-2.6.17/arch/mips/ddb5xxx/ddb5074/setup.c
---- linux-2.6.17.orig/arch/mips/ddb5xxx/ddb5074/setup.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/ddb5xxx/ddb5074/setup.c	1969-12-31 16:00:00.000000000 -0800
-@@ -1,234 +0,0 @@
--/*
-- *  arch/mips/ddb5074/setup.c -- NEC DDB Vrc-5074 setup routines
-- *
-- *  Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
-- *                     Sony Software Development Center Europe (SDCE), Brussels
-- */
--#include <linux/init.h>
--#include <linux/kbd_ll.h>
--#include <linux/kernel.h>
--#include <linux/kdev_t.h>
--#include <linux/types.h>
--#include <linux/sched.h>
--#include <linux/pci.h>
--#include <linux/ide.h>
--#include <linux/ioport.h>
--#include <linux/irq.h>
--#include <linux/pm.h>
--
--#include <asm/addrspace.h>
--#include <asm/bcache.h>
--#include <asm/irq.h>
--#include <asm/reboot.h>
--#include <asm/gdb-stub.h>
--#include <asm/time.h>
--#include <asm/nile4.h>
--#include <asm/ddb5xxx/ddb5074.h>
--#include <asm/ddb5xxx/ddb5xxx.h>
--
--static void (*back_to_prom) (void) = (void (*)(void)) 0xbfc00000;
--
--static void ddb_machine_restart(char *command)
--{
--	u32 t;
--
--	/* PCI cold reset */
--	t = nile4_in32(NILE4_PCICTRL + 4);
--	t |= 0x40000000;
--	nile4_out32(NILE4_PCICTRL + 4, t);
--	/* CPU cold reset */
--	t = nile4_in32(NILE4_CPUSTAT);
--	t |= 1;
--	nile4_out32(NILE4_CPUSTAT, t);
--	/* Call the PROM */
--	back_to_prom();
--}
--
--static void ddb_machine_halt(void)
--{
--	printk("DDB Vrc-5074 halted.\n");
--	do {
--	} while (1);
--}
--
--static void ddb_machine_power_off(void)
--{
--	printk("DDB Vrc-5074 halted. Please turn off the power.\n");
--	do {
--	} while (1);
--}
--
--extern void rtc_ds1386_init(unsigned long base);
--
--extern void (*board_timer_setup) (struct irqaction * irq);
--
--static void __init ddb_timer_init(struct irqaction *irq)
--{
--	/* set the clock to 1 Hz */
--	nile4_out32(NILE4_T2CTRL, 1000000);
--	/* enable the General-Purpose Timer */
--	nile4_out32(NILE4_T2CTRL + 4, 0x00000001);
--	/* reset timer */
--	nile4_out32(NILE4_T2CNTR, 0);
--	/* enable interrupt */
--	setup_irq(nile4_to_irq(NILE4_INT_GPT), irq);
--	nile4_enable_irq(nile4_to_irq(NILE4_INT_GPT));
--	change_c0_status(ST0_IM,
--		          IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4);
--
--}
--
--static void __init ddb_time_init(void)
--{
--	/* we have ds1396 RTC chip */
--	rtc_ds1386_init(KSEG1ADDR(DDB_PCI_MEM_BASE));
--}
--
--
--
--void __init plat_setup(void)
--{
--	set_io_port_base(NILE4_PCI_IO_BASE);
--	isa_slot_offset = NILE4_PCI_MEM_BASE;
--	board_timer_setup = ddb_timer_init;
--	board_time_init = ddb_time_init;
--
--
--	_machine_restart = ddb_machine_restart;
--	_machine_halt = ddb_machine_halt;
--	pm_power_off = ddb_machine_power_off;
--
--	ddb_out32(DDB_BAR0, 0);
--
--	ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, 0x10);
--	ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_MEM, DDB_PCI_MEM_BASE , 0x10);
--
--	/* Reboot on panic */
--	panic_timeout = 180;
--}
--
--#define USE_NILE4_SERIAL	0
--
--#if USE_NILE4_SERIAL
--#define ns16550_in(reg)		nile4_in8((reg)*8)
--#define ns16550_out(reg, val)	nile4_out8((reg)*8, (val))
--#else
--#define NS16550_BASE		(NILE4_PCI_IO_BASE+0x03f8)
--static inline u8 ns16550_in(u32 reg)
--{
--	return *(volatile u8 *) (NS16550_BASE + reg);
--}
--
--static inline void ns16550_out(u32 reg, u8 val)
--{
--	*(volatile u8 *) (NS16550_BASE + reg) = val;
--}
--#endif
--
--#define NS16550_RBR		0
--#define NS16550_THR		0
--#define NS16550_DLL		0
--#define NS16550_IER		1
--#define NS16550_DLM		1
--#define NS16550_FCR		2
--#define NS16550_IIR		2
--#define NS16550_LCR		3
--#define NS16550_MCR		4
--#define NS16550_LSR		5
--#define NS16550_MSR		6
--#define NS16550_SCR		7
--
--#define NS16550_LSR_DR		0x01	/* Data ready */
--#define NS16550_LSR_OE		0x02	/* Overrun */
--#define NS16550_LSR_PE		0x04	/* Parity error */
--#define NS16550_LSR_FE		0x08	/* Framing error */
--#define NS16550_LSR_BI		0x10	/* Break */
--#define NS16550_LSR_THRE	0x20	/* Xmit holding register empty */
--#define NS16550_LSR_TEMT	0x40	/* Xmitter empty */
--#define NS16550_LSR_ERR		0x80	/* Error */
--
--
--void _serinit(void)
--{
--#if USE_NILE4_SERIAL
--	ns16550_out(NS16550_LCR, 0x80);
--	ns16550_out(NS16550_DLM, 0x00);
--	ns16550_out(NS16550_DLL, 0x36);	/* 9600 baud */
--	ns16550_out(NS16550_LCR, 0x00);
--	ns16550_out(NS16550_LCR, 0x03);
--	ns16550_out(NS16550_FCR, 0x47);
--#else
--	/* done by PMON */
--#endif
--}
--
--void _putc(char c)
--{
--	while (!(ns16550_in(NS16550_LSR) & NS16550_LSR_THRE));
--	ns16550_out(NS16550_THR, c);
--	if (c == '\n') {
--		while (!(ns16550_in(NS16550_LSR) & NS16550_LSR_THRE));
--		ns16550_out(NS16550_THR, '\r');
--	}
--}
--
--void _puts(const char *s)
--{
--	char c;
--	while ((c = *s++))
--		_putc(c);
--}
--
--char _getc(void)
--{
--	while (!(ns16550_in(NS16550_LSR) & NS16550_LSR_DR));
--	return ns16550_in(NS16550_RBR);
--}
--
--int _testc(void)
--{
--	return (ns16550_in(NS16550_LSR) & NS16550_LSR_DR) != 0;
--}
--
--
--/*
-- *  Hexadecimal 7-segment LED
-- */
--void ddb5074_led_hex(int hex)
--{
--	outb(hex, 0x80);
--}
--
--
--/*
-- *  LEDs D2 and D3, connected to the GPIO pins of the PMU in the ALi M1543
-- */
--struct pci_dev *pci_pmu = NULL;
--
--void ddb5074_led_d2(int on)
--{
--	u8 t;
--
--	if (pci_pmu) {
--		pci_read_config_byte(pci_pmu, 0x7e, &t);
--		if (on)
--			t &= 0x7f;
--		else
--			t |= 0x80;
--		pci_write_config_byte(pci_pmu, 0x7e, t);
--	}
--}
--
--void ddb5074_led_d3(int on)
--{
--	u8 t;
--
--	if (pci_pmu) {
--		pci_read_config_byte(pci_pmu, 0x7e, &t);
--		if (on)
--			t &= 0xbf;
--		else
--			t |= 0x40;
--		pci_write_config_byte(pci_pmu, 0x7e, t);
--	}
--}
-diff -Naur linux-2.6.17.orig/arch/mips/ddb5xxx/ddb5476/dbg_io.c linux-2.6.17/arch/mips/ddb5xxx/ddb5476/dbg_io.c
---- linux-2.6.17.orig/arch/mips/ddb5xxx/ddb5476/dbg_io.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/ddb5xxx/ddb5476/dbg_io.c	1969-12-31 16:00:00.000000000 -0800
-@@ -1,136 +0,0 @@
--/*
-- * kgdb io functions for DDB5476.  We use the second serial port.
-- *
-- * Copyright (C) 2001 MontaVista Software Inc.
-- * Author: jsun@mvista.com or jsun@junsun.net
-- *
-- * This program is free software; you can redistribute  it and/or modify it
-- * under  the terms of  the GNU General  Public License as published by the
-- * Free Software Foundation;  either version 2 of the  License, or (at your
-- * option) any later version.
-- *
-- */
--
--/* ======================= CONFIG ======================== */
--
--/* [jsun] we use the second serial port for kdb */
--#define         BASE                    0xa60002f8
--#define         MAX_BAUD                115200
--
--/* distance in bytes between two serial registers */
--#define         REG_OFFSET              1
--
--/*
-- * 0 - kgdb does serial init
-- * 1 - kgdb skip serial init
-- */
--static int remoteDebugInitialized = 0;
--
--/*
-- * the default baud rate *if* kgdb does serial init
-- */
--#define		BAUD_DEFAULT		UART16550_BAUD_38400
--
--/* ======================= END OF CONFIG ======================== */
--
--typedef unsigned char uint8;
--typedef unsigned int uint32;
--
--#define         UART16550_BAUD_2400             2400
--#define         UART16550_BAUD_4800             4800
--#define         UART16550_BAUD_9600             9600
--#define         UART16550_BAUD_19200            19200
--#define         UART16550_BAUD_38400            38400
--#define         UART16550_BAUD_57600            57600
--#define         UART16550_BAUD_115200           115200
--
--#define         UART16550_PARITY_NONE           0
--#define         UART16550_PARITY_ODD            0x08
--#define         UART16550_PARITY_EVEN           0x18
--#define         UART16550_PARITY_MARK           0x28
--#define         UART16550_PARITY_SPACE          0x38
--
--#define         UART16550_DATA_5BIT             0x0
--#define         UART16550_DATA_6BIT             0x1
--#define         UART16550_DATA_7BIT             0x2
--#define         UART16550_DATA_8BIT             0x3
--
--#define         UART16550_STOP_1BIT             0x0
--#define         UART16550_STOP_2BIT             0x4
--
--/* register offset */
--#define         OFS_RCV_BUFFER          0
--#define         OFS_TRANS_HOLD          0
--#define         OFS_SEND_BUFFER         0
--#define         OFS_INTR_ENABLE         (1*REG_OFFSET)
--#define         OFS_INTR_ID             (2*REG_OFFSET)
--#define         OFS_DATA_FORMAT         (3*REG_OFFSET)
--#define         OFS_LINE_CONTROL        (3*REG_OFFSET)
--#define         OFS_MODEM_CONTROL       (4*REG_OFFSET)
--#define         OFS_RS232_OUTPUT        (4*REG_OFFSET)
--#define         OFS_LINE_STATUS         (5*REG_OFFSET)
--#define         OFS_MODEM_STATUS        (6*REG_OFFSET)
--#define         OFS_RS232_INPUT         (6*REG_OFFSET)
--#define         OFS_SCRATCH_PAD         (7*REG_OFFSET)
--
--#define         OFS_DIVISOR_LSB         (0*REG_OFFSET)
--#define         OFS_DIVISOR_MSB         (1*REG_OFFSET)
--
--
--/* memory-mapped read/write of the port */
--#define         UART16550_READ(y)    (*((volatile uint8*)(BASE + y)))
--#define         UART16550_WRITE(y, z)  ((*((volatile uint8*)(BASE + y))) = z)
--
--void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
--{
--        /* disable interrupts */
--        UART16550_WRITE(OFS_INTR_ENABLE, 0);
--
--        /* set up baud rate */
--        {
--                uint32 divisor;
--
--                /* set DIAB bit */
--                UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
--
--                /* set divisor */
--                divisor = MAX_BAUD / baud;
--                UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
--                UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
--
--                /* clear DIAB bit */
--                UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
--        }
--
--        /* set data format */
--        UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
--}
--
--
--uint8 getDebugChar(void)
--{
--        if (!remoteDebugInitialized) {
--                remoteDebugInitialized = 1;
--                debugInit(BAUD_DEFAULT,
--                          UART16550_DATA_8BIT,
--                          UART16550_PARITY_NONE, UART16550_STOP_1BIT);
--        }
--
--        while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
--        return UART16550_READ(OFS_RCV_BUFFER);
--}
--
--
--int putDebugChar(uint8 byte)
--{
--        if (!remoteDebugInitialized) {
--                remoteDebugInitialized = 1;
--                debugInit(BAUD_DEFAULT,
--                          UART16550_DATA_8BIT,
--                          UART16550_PARITY_NONE, UART16550_STOP_1BIT);
--        }
--
--        while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
--        UART16550_WRITE(OFS_SEND_BUFFER, byte);
--        return 1;
--}
-diff -Naur linux-2.6.17.orig/arch/mips/ddb5xxx/ddb5476/irq.c linux-2.6.17/arch/mips/ddb5xxx/ddb5476/irq.c
---- linux-2.6.17.orig/arch/mips/ddb5xxx/ddb5476/irq.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/ddb5xxx/ddb5476/irq.c	1969-12-31 16:00:00.000000000 -0800
-@@ -1,165 +0,0 @@
--/*
-- *  arch/mips/ddb5476/irq.c -- NEC DDB Vrc-5476 interrupt routines
-- *
-- *  Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
-- *                     Sony Software Development Center Europe (SDCE), Brussels
-- *
-- * Re-write the whole thing to use new irq.c file.
-- * Copyright (C) 2001 MontaVista Software Inc.
-- * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
-- *
-- */
--#include <linux/init.h>
--#include <linux/sched.h>
--#include <linux/types.h>
--#include <linux/interrupt.h>
--
--#include <asm/i8259.h>
--#include <asm/io.h>
--#include <asm/ptrace.h>
--
--#include <asm/ddb5xxx/ddb5xxx.h>
--
--#define M1543_PNP_CONFIG	0x03f0	/* PnP Config Port */
--#define M1543_PNP_INDEX		0x03f0	/* PnP Index Port */
--#define M1543_PNP_DATA		0x03f1	/* PnP Data Port */
--
--#define M1543_PNP_ALT_CONFIG	0x0370	/* Alternative PnP Config Port */
--#define M1543_PNP_ALT_INDEX	0x0370	/* Alternative PnP Index Port */
--#define M1543_PNP_ALT_DATA	0x0371	/* Alternative PnP Data Port */
--
--#define M1543_INT1_MASTER_CTRL	0x0020	/* INT_1 (master) Control Register */
--#define M1543_INT1_MASTER_MASK	0x0021	/* INT_1 (master) Mask Register */
--
--#define M1543_INT1_SLAVE_CTRL	0x00a0	/* INT_1 (slave) Control Register */
--#define M1543_INT1_SLAVE_MASK	0x00a1	/* INT_1 (slave) Mask Register */
--
--#define M1543_INT1_MASTER_ELCR	0x04d0	/* INT_1 (master) Edge/Level Control */
--#define M1543_INT1_SLAVE_ELCR	0x04d1	/* INT_1 (slave) Edge/Level Control */
--
--static void m1543_irq_setup(void)
--{
--	/*
--	 *  The ALI M1543 has 13 interrupt inputs, IRQ1..IRQ13.  Not all
--	 *  the possible IO sources in the M1543 are in use by us.  We will
--	 *  use the following mapping:
--	 *
--	 *      IRQ1  - keyboard (default set by M1543)
--	 *      IRQ3  - reserved for UART B (default set by M1543) (note that
--	 *              the schematics for the DDB Vrc-5476 board seem to
--	 *              indicate that IRQ3 is connected to the DS1386
--	 *              watchdog timer interrupt output so we might have
--	 *              a conflict)
--	 *      IRQ4  - reserved for UART A (default set by M1543)
--	 *      IRQ5  - parallel (default set by M1543)
--	 *      IRQ8  - DS1386 time of day (RTC) interrupt
--	 *      IRQ9  - USB (hardwired in ddb_setup)
--	 *      IRQ10 - PMU (hardwired in ddb_setup)
--	 *      IRQ12 - mouse
--	 *      IRQ14,15 - IDE controller (need to be confirmed, jsun)
--	 */
--
--	/*
--	 *  Assing mouse interrupt to IRQ12
--	 */
--
--	/* Enter configuration mode */
--	outb(0x51, M1543_PNP_CONFIG);
--	outb(0x23, M1543_PNP_CONFIG);
--
--	/* Select logical device 7 (Keyboard) */
--	outb(0x07, M1543_PNP_INDEX);
--	outb(0x07, M1543_PNP_DATA);
--
--	/* Select IRQ12 */
--	outb(0x72, M1543_PNP_INDEX);
--	outb(0x0c, M1543_PNP_DATA);
--
--	/* Leave configration mode */
--	outb(0xbb, M1543_PNP_CONFIG);
--}
--
--static void nile4_irq_setup(void)
--{
--	int i;
--
--	/* Map all interrupts to CPU int #0 (IP2) */
--	nile4_map_irq_all(0);
--
--	/* PCI INTA#-E# must be level triggered */
--	nile4_set_pci_irq_level_or_edge(0, 1);
--	nile4_set_pci_irq_level_or_edge(1, 1);
--	nile4_set_pci_irq_level_or_edge(2, 1);
--	nile4_set_pci_irq_level_or_edge(3, 1);
--
--	/* PCI INTA#, B#, D# must be active low, INTC# must be active high */
--	nile4_set_pci_irq_polarity(0, 0);
--	nile4_set_pci_irq_polarity(1, 0);
--	nile4_set_pci_irq_polarity(2, 1);
--	nile4_set_pci_irq_polarity(3, 0);
--
--	for (i = 0; i < 16; i++)
--		nile4_clear_irq(i);
--
--	/* Enable CPU int #0 */
--	nile4_enable_irq_output(0);
--
--	/* memory resource acquire in ddb_setup */
--}
--
--static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL };
--static struct irqaction irq_error = { no_action, 0, CPU_MASK_NONE, "error", NULL, NULL };
--
--extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
--extern void mips_cpu_irq_init(u32 irq_base);
--extern void vrc5476_irq_init(u32 irq_base);
--
--extern void vrc5476_irq_dispatch(struct pt_regs *regs);
--
--asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
--{
--	unsigned int pending = read_c0_cause() & read_c0_status();
--
--	if (pending & STATUSF_IP7)
--		do_IRQ(CPU_IRQ_BASE + 7, regs);
--	else if (pending & STATUSF_IP2)
--		vrc5476_irq_dispatch(regs);
--	else if (pending & STATUSF_IP3)
--		do_IRQ(CPU_IRQ_BASE + 3, regs);
--	else if (pending & STATUSF_IP4)
--		do_IRQ(CPU_IRQ_BASE + 4, regs);
--	else if (pending & STATUSF_IP5)
--		do_IRQ(CPU_IRQ_BASE + 5, regs);
--	else if (pending & STATUSF_IP6)
--		do_IRQ(CPU_IRQ_BASE + 6, regs);
--	else if (pending & STATUSF_IP0)
--		do_IRQ(CPU_IRQ_BASE, regs);
--	else if (pending & STATUSF_IP1)
--		do_IRQ(CPU_IRQ_BASE + 1, regs);
--
--	vrc5476_irq_dispatch(regs);
--}
--
--void __init arch_init_irq(void)
--{
--	/* hardware initialization */
--	nile4_irq_setup();
--	m1543_irq_setup();
--
--	/* controller setup */
--	init_i8259_irqs();
--	vrc5476_irq_init(VRC5476_IRQ_BASE);
--	mips_cpu_irq_init(CPU_IRQ_BASE);
--
--	/* setup cascade interrupts */
--	setup_irq(VRC5476_IRQ_BASE + VRC5476_I8259_CASCADE, &irq_cascade);
--	setup_irq(CPU_IRQ_BASE + CPU_VRC5476_CASCADE, &irq_cascade);
--
--	/* setup error interrupts for debugging */
--	setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_CPCE, &irq_error);
--	setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_CNTD, &irq_error);
--	setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_MCE, &irq_error);
--	setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_LBRT, &irq_error);
--	setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_PCIS, &irq_error);
--	setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_PCI, &irq_error);
--}
-diff -Naur linux-2.6.17.orig/arch/mips/ddb5xxx/ddb5476/Makefile linux-2.6.17/arch/mips/ddb5xxx/ddb5476/Makefile
---- linux-2.6.17.orig/arch/mips/ddb5xxx/ddb5476/Makefile	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/ddb5xxx/ddb5476/Makefile	1969-12-31 16:00:00.000000000 -0800
-@@ -1,9 +0,0 @@
--#
--# Makefile for the NEC DDB Vrc-5476 specific kernel interface routines
--# under Linux.
--#
--
--obj-y			+= setup.o irq.o nile4_pic.o vrc5476_irq.o
--obj-$(CONFIG_KGDB)	+= dbg_io.o
--
--EXTRA_AFLAGS := $(CFLAGS)
-diff -Naur linux-2.6.17.orig/arch/mips/ddb5xxx/ddb5476/nile4_pic.c linux-2.6.17/arch/mips/ddb5xxx/ddb5476/nile4_pic.c
---- linux-2.6.17.orig/arch/mips/ddb5xxx/ddb5476/nile4_pic.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/ddb5xxx/ddb5476/nile4_pic.c	1969-12-31 16:00:00.000000000 -0800
-@@ -1,190 +0,0 @@
--/*
-- *  arch/mips/ddb5476/nile4.c --
-- *  	low-level PIC code for NEC Vrc-5476 (Nile 4)
-- *
-- *  Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
-- *                     Sony Software Development Center Europe (SDCE), Brussels
-- *
-- *  Copyright 2001 MontaVista Software Inc.
-- *  Author: jsun@mvista.com or jsun@junsun.net
-- *
-- */
--#include <linux/config.h>
--#include <linux/kernel.h>
--#include <linux/types.h>
--
--#include <asm/addrspace.h>
--
--#include <asm/ddb5xxx/ddb5xxx.h>
--
--
--/*
-- *  Interrupt Programming
-- */
--void nile4_map_irq(int nile4_irq, int cpu_irq)
--{
--	u32 offset, t;
--
--	offset = DDB_INTCTRL;
--	if (nile4_irq >= 8) {
--		offset += 4;
--		nile4_irq -= 8;
--	}
--	t = ddb_in32(offset);
--	t &= ~(7 << (nile4_irq * 4));
--	t |= cpu_irq << (nile4_irq * 4);
--	ddb_out32(offset, t);
--}
--
--void nile4_map_irq_all(int cpu_irq)
--{
--	u32 all, t;
--
--	all = cpu_irq;
--	all |= all << 4;
--	all |= all << 8;
--	all |= all << 16;
--	t = ddb_in32(DDB_INTCTRL);
--	t &= 0x88888888;
--	t |= all;
--	ddb_out32(DDB_INTCTRL, t);
--	t = ddb_in32(DDB_INTCTRL + 4);
--	t &= 0x88888888;
--	t |= all;
--	ddb_out32(DDB_INTCTRL + 4, t);
--}
--
--void nile4_enable_irq(int nile4_irq)
--{
--	u32 offset, t;
--
--	offset = DDB_INTCTRL;
--	if (nile4_irq >= 8) {
--		offset += 4;
--		nile4_irq -= 8;
--	}
--	t = ddb_in32(offset);
--	t |= 8 << (nile4_irq * 4);
--	ddb_out32(offset, t);
--}
--
--void nile4_disable_irq(int nile4_irq)
--{
--	u32 offset, t;
--
--	offset = DDB_INTCTRL;
--	if (nile4_irq >= 8) {
--		offset += 4;
--		nile4_irq -= 8;
--	}
--	t = ddb_in32(offset);
--	t &= ~(8 << (nile4_irq * 4));
--	ddb_out32(offset, t);
--}
--
--void nile4_disable_irq_all(void)
--{
--	ddb_out32(DDB_INTCTRL, 0);
--	ddb_out32(DDB_INTCTRL + 4, 0);
--}
--
--u16 nile4_get_irq_stat(int cpu_irq)
--{
--	return ddb_in16(DDB_INTSTAT0 + cpu_irq * 2);
--}
--
--void nile4_enable_irq_output(int cpu_irq)
--{
--	u32 t;
--
--	t = ddb_in32(DDB_INTSTAT1 + 4);
--	t |= 1 << (16 + cpu_irq);
--	ddb_out32(DDB_INTSTAT1, t);
--}
--
--void nile4_disable_irq_output(int cpu_irq)
--{
--	u32 t;
--
--	t = ddb_in32(DDB_INTSTAT1 + 4);
--	t &= ~(1 << (16 + cpu_irq));
--	ddb_out32(DDB_INTSTAT1, t);
--}
--
--void nile4_set_pci_irq_polarity(int pci_irq, int high)
--{
--	u32 t;
--
--	t = ddb_in32(DDB_INTPPES);
--	if (high)
--		t &= ~(1 << (pci_irq * 2));
--	else
--		t |= 1 << (pci_irq * 2);
--	ddb_out32(DDB_INTPPES, t);
--}
--
--void nile4_set_pci_irq_level_or_edge(int pci_irq, int level)
--{
--	u32 t;
--
--	t = ddb_in32(DDB_INTPPES);
--	if (level)
--		t |= 2 << (pci_irq * 2);
--	else
--		t &= ~(2 << (pci_irq * 2));
--	ddb_out32(DDB_INTPPES, t);
--}
--
--void nile4_clear_irq(int nile4_irq)
--{
--	ddb_out32(DDB_INTCLR, 1 << nile4_irq);
--}
--
--void nile4_clear_irq_mask(u32 mask)
--{
--	ddb_out32(DDB_INTCLR, mask);
--}
--
--u8 nile4_i8259_iack(void)
--{
--	u8 irq;
--	u32 reg;
--
--	/* Set window 0 for interrupt acknowledge */
--	reg = ddb_in32(DDB_PCIINIT0);
--
--	ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IACK, 0, DDB_PCI_ACCESS_32);
--	irq = *(volatile u8 *) KSEG1ADDR(DDB_PCI_IACK_BASE);
--	/* restore window 0 for PCI I/O space */
--	// ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32);
--	ddb_out32(DDB_PCIINIT0, reg);
--
--	/* i8269.c set the base vector to be 0x0 */
--	return irq + I8259_IRQ_BASE;
--}
--
--#if defined(CONFIG_RUNTIME_DEBUG)
--void nile4_dump_irq_status(void)
--{
--	printk(KERN_DEBUG "
--	       CPUSTAT = %p:%p\n", (void *) ddb_in32(DDB_CPUSTAT + 4),
--	       (void *) ddb_in32(DDB_CPUSTAT));
--	printk(KERN_DEBUG "
--	       INTCTRL = %p:%p\n", (void *) ddb_in32(DDB_INTCTRL + 4),
--	       (void *) ddb_in32(DDB_INTCTRL));
--	printk(KERN_DEBUG
--	       "INTSTAT0 = %p:%p\n",
--	       (void *) ddb_in32(DDB_INTSTAT0 + 4),
--	       (void *) ddb_in32(DDB_INTSTAT0));
--	printk(KERN_DEBUG
--	       "INTSTAT1 = %p:%p\n",
--	       (void *) ddb_in32(DDB_INTSTAT1 + 4),
--	       (void *) ddb_in32(DDB_INTSTAT1));
--	printk(KERN_DEBUG
--	       "INTCLR = %p:%p\n", (void *) ddb_in32(DDB_INTCLR + 4),
--	       (void *) ddb_in32(DDB_INTCLR));
--	printk(KERN_DEBUG
--	       "INTPPES = %p:%p\n", (void *) ddb_in32(DDB_INTPPES + 4),
--	       (void *) ddb_in32(DDB_INTPPES));
--}
--#endif
-diff -Naur linux-2.6.17.orig/arch/mips/ddb5xxx/ddb5476/setup.c linux-2.6.17/arch/mips/ddb5xxx/ddb5476/setup.c
---- linux-2.6.17.orig/arch/mips/ddb5xxx/ddb5476/setup.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/ddb5xxx/ddb5476/setup.c	1969-12-31 16:00:00.000000000 -0800
-@@ -1,296 +0,0 @@
--/*
-- *  arch/mips/ddb5476/setup.c -- NEC DDB Vrc-5476 setup routines
-- *
-- *  Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
-- *                     Sony Software Development Center Europe (SDCE), Brussels
-- */
--#include <linux/init.h>
--#include <linux/kbd_ll.h>
--#include <linux/kernel.h>
--#include <linux/kdev_t.h>
--#include <linux/types.h>
--#include <linux/sched.h>
--#include <linux/pci.h>
--#include <linux/pm.h>
--
--#include <asm/addrspace.h>
--#include <asm/bcache.h>
--#include <asm/irq.h>
--#include <asm/reboot.h>
--#include <asm/gdb-stub.h>
--#include <asm/time.h>
--#include <asm/debug.h>
--#include <asm/traps.h>
--
--#include <asm/ddb5xxx/ddb5xxx.h>
--
--// #define USE_CPU_COUNTER_TIMER	/* whether we use cpu counter */
--
--#ifdef USE_CPU_COUNTER_TIMER
--
--#define CPU_COUNTER_FREQUENCY           83000000
--#else
--/* otherwise we use general purpose timer */
--#define TIMER_FREQUENCY			83000000
--#define TIMER_BASE			DDB_T2CTRL
--#define TIMER_IRQ			(VRC5476_IRQ_BASE + VRC5476_IRQ_GPT)
--#endif
--
--static void (*back_to_prom) (void) = (void (*)(void)) 0xbfc00000;
--
--static void ddb_machine_restart(char *command)
--{
--	u32 t;
--
--	/* PCI cold reset */
--	t = ddb_in32(DDB_PCICTRL + 4);
--	t |= 0x40000000;
--	ddb_out32(DDB_PCICTRL + 4, t);
--	/* CPU cold reset */
--	t = ddb_in32(DDB_CPUSTAT);
--	t |= 1;
--	ddb_out32(DDB_CPUSTAT, t);
--	/* Call the PROM */
--	back_to_prom();
--}
--
--static void ddb_machine_halt(void)
--{
--	printk(KERN_NOTICE "DDB Vrc-5476 halted.\n");
--	while (1);
--}
--
--static void ddb_machine_power_off(void)
--{
--	printk(KERN_NOTICE "DDB Vrc-5476 halted. Please turn off the power.\n");
--	while (1);
--}
--
--extern void rtc_ds1386_init(unsigned long base);
--
--static void __init ddb_time_init(void)
--{
--#if defined(USE_CPU_COUNTER_TIMER)
--	mips_hpt_frequency = CPU_COUNTER_FREQUENCY;
--#endif
--
--	/* we have ds1396 RTC chip */
--	rtc_ds1386_init(KSEG1ADDR(DDB_PCI_MEM_BASE));
--}
--
--
--extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
--static void __init ddb_timer_setup(struct irqaction *irq)
--{
--#if defined(USE_CPU_COUNTER_TIMER)
--
--	unsigned int count;
--
--	/* we are using the cpu counter for timer interrupts */
--	setup_irq(CPU_IRQ_BASE + 7, irq);
--
--	/* to generate the first timer interrupt */
--	count = read_c0_count();
--	write_c0_compare(count + 1000);
--
--#else
--
--	ddb_out32(TIMER_BASE, TIMER_FREQUENCY/HZ);
--	ddb_out32(TIMER_BASE+4, 0x1);	/* enable timer */
--	setup_irq(TIMER_IRQ, irq);
--#endif
--}
--
--static struct {
--	struct resource dma1;
--	struct resource timer;
--	struct resource rtc;
--	struct resource dma_page_reg;
--	struct resource dma2;
--} ddb5476_ioport = {
--	{
--	"dma1", 0x00, 0x1f, IORESOURCE_BUSY}, {
--	"timer", 0x40, 0x5f, IORESOURCE_BUSY}, {
--	"rtc", 0x70, 0x7f, IORESOURCE_BUSY}, {
--	"dma page reg", 0x80, 0x8f, IORESOURCE_BUSY}, {
--	"dma2", 0xc0, 0xdf, IORESOURCE_BUSY}
--};
--
--static struct {
--	struct resource nile4;
--} ddb5476_iomem = {
--	{ "Nile 4", DDB_BASE, DDB_BASE + DDB_SIZE - 1, IORESOURCE_BUSY}
--};
--
--
--static void ddb5476_board_init(void);
--
--void __init plat_setup(void)
--{
--	set_io_port_base(KSEG1ADDR(DDB_PCI_IO_BASE));
--
--	board_time_init = ddb_time_init;
--	board_timer_setup = ddb_timer_setup;
--
--	_machine_restart = ddb_machine_restart;
--	_machine_halt = ddb_machine_halt;
--	pm_power_off = ddb_machine_power_off;
--
--	/* request io port/mem resources  */
--	if (request_resource(&ioport_resource, &ddb5476_ioport.dma1) ||
--	    request_resource(&ioport_resource, &ddb5476_ioport.timer) ||
--	    request_resource(&ioport_resource, &ddb5476_ioport.rtc) ||
--	    request_resource(&ioport_resource,
--			     &ddb5476_ioport.dma_page_reg)
--	    || request_resource(&ioport_resource, &ddb5476_ioport.dma2)
--	    || request_resource(&iomem_resource, &ddb5476_iomem.nile4)) {
--		printk
--		    ("ddb_setup - requesting oo port resources failed.\n");
--		for (;;);
--	}
--
--	/* Reboot on panic */
--	panic_timeout = 180;
--
--	/* [jsun] we need to set BAR0 so that SDRAM 0 appears at 0x0 in PCI */
--	/* *(long*)0xbfa00218 = 0x8; */
--
--	/* board initialization stuff */
--	ddb5476_board_init();
--}
--
--/*
-- * We don't trust bios.  We essentially does hardware re-initialization
-- * as complete as possible, as far as we know we can safely do.
-- */
--static void ddb5476_board_init(void)
--{
--	/* ----------- setup PDARs ------------ */
--	/* check SDRAM0, whether we are on MEM bus does not matter */
--	db_assert((ddb_in32(DDB_SDRAM0) & 0xffffffef) ==
--		  ddb_calc_pdar(DDB_SDRAM_BASE, DDB_SDRAM_SIZE, 32, 0, 1));
--
--	/* SDRAM1 should be turned off.  What is this for anyway ? */
--	db_assert( (ddb_in32(DDB_SDRAM1) & 0xf) == 0);
--
--	/* flash 1&2, DDB status, DDB control */
--	ddb_set_pdar(DDB_DCS2, DDB_DCS2_BASE, DDB_DCS2_SIZE, 16, 0, 0);
--	ddb_set_pdar(DDB_DCS3, DDB_DCS3_BASE, DDB_DCS3_SIZE, 16, 0, 0);
--	ddb_set_pdar(DDB_DCS4, DDB_DCS4_BASE, DDB_DCS4_SIZE, 8, 0, 0);
--	ddb_set_pdar(DDB_DCS5, DDB_DCS5_BASE, DDB_DCS5_SIZE, 8, 0, 0);
--
--	/* shut off other pdar so they don't accidentally get into the way */
--	ddb_set_pdar(DDB_DCS6, 0xffffffff, 0, 32, 0, 0);
--	ddb_set_pdar(DDB_DCS7, 0xffffffff, 0, 32, 0, 0);
--	ddb_set_pdar(DDB_DCS8, 0xffffffff, 0, 32, 0, 0);
--
--	/* verify VRC5477 base addr */
--	/* don't care about some details */
--	db_assert((ddb_in32(DDB_INTCS) & 0xffffff0f) ==
--		  ddb_calc_pdar(DDB_INTCS_BASE, DDB_INTCS_SIZE, 8, 0, 0));
--
--	/* verify BOOT ROM addr */
--	/* don't care about some details */
--	db_assert((ddb_in32(DDB_BOOTCS) & 0xffffff0f) ==
--		  ddb_calc_pdar(DDB_BOOTCS_BASE, DDB_BOOTCS_SIZE, 8, 0, 0));
--
--	/* setup PCI windows - window1 for MEM/config, window0 for IO */
--	ddb_set_pdar(DDB_PCIW0, DDB_PCI_IO_BASE, DDB_PCI_IO_SIZE, 32, 0, 1);
--	ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32);
--
--	ddb_set_pdar(DDB_PCIW1, DDB_PCI_MEM_BASE, DDB_PCI_MEM_SIZE, 32, 0, 1);
--	ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_MEM, DDB_PCI_MEM_BASE, DDB_PCI_ACCESS_32);
--
--	/* ----------- setup PDARs ------------ */
--	/* this is problematic - it will reset Aladin which cause we loose
--	 * serial port, and we don't know how to set up Aladin chip again.
--	 */
--	// ddb_pci_reset_bus();
--
--	ddb_out32(DDB_BAR0, 0x00000008);
--
--	ddb_out32(DDB_BARC, 0xffffffff);
--	ddb_out32(DDB_BARB, 0xffffffff);
--	ddb_out32(DDB_BAR1, 0xffffffff);
--	ddb_out32(DDB_BAR2, 0xffffffff);
--	ddb_out32(DDB_BAR3, 0xffffffff);
--	ddb_out32(DDB_BAR4, 0xffffffff);
--	ddb_out32(DDB_BAR5, 0xffffffff);
--	ddb_out32(DDB_BAR6, 0xffffffff);
--	ddb_out32(DDB_BAR7, 0xffffffff);
--	ddb_out32(DDB_BAR8, 0xffffffff);
--
--	/* ----------- switch PCI1 to PCI CONFIG space  ------------ */
--	ddb_set_pdar(DDB_PCIW1, DDB_PCI_CONFIG_BASE, DDB_PCI_CONFIG_SIZE, 32, 0, 1);
--	ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_CFG, 0x0, DDB_PCI_ACCESS_32);
--
--	/* ----- M1543 PCI setup ------ */
--
--	/* we know M1543 PCI-ISA controller is at addr:18 */
--	/* xxxx1010 makes USB at addr:13 and PMU at addr:14 */
--	*(volatile unsigned char *) 0xa8040072 &= 0xf0;
--	*(volatile unsigned char *) 0xa8040072 |= 0xa;
--
--	/* setup USB interrupt to IRQ 9, (bit 0:3 - 0001)
--	 * no IOCHRDY signal, (bit 7 - 1)
--	 * M1543C & M7101 VID and Subsys Device ID are read-only (bit 6 - 1)
--	 * Make USB Master INTAJ level to edge conversion (bit 4 - 1)
--	 */
--	*(unsigned char *) 0xa8040074 = 0xd1;
--
--	/* setup PMU(SCI to IRQ 10 (bit 0:3 - 0011)
--	 * SCI routing to IRQ 13 disabled (bit 7 - 1)
--	 * SCI interrupt level to edge conversion bypassed (bit 4 - 0)
--	 */
--	*(unsigned char *) 0xa8040076 = 0x83;
--
--	/* setup IDE controller
--	 * enable IDE controller (bit 6 - 1)
--	 * IDE IDSEL to be addr:24 (bit 4:5 - 11)
--	 * no IDE ATA Secondary Bus Signal Pad Control (bit 3 - 0)
--	 * no IDE ATA Primary Bus Signal Pad Control (bit 2 - 0)
--	 * primary IRQ is 14, secondary is 15 (bit 1:0 - 01
--	 */
--	// *(unsigned char*)0xa8040058 = 0x71;
--	// *(unsigned char*)0xa8040058 = 0x79;
--	// *(unsigned char*)0xa8040058 = 0x74;              // use SIRQ, primary tri-state
--	*(unsigned char *) 0xa8040058 = 0x75;	// primary tri-state
--
--#if 0
--	/* this is not necessary if M5229 does not use SIRQ */
--	*(unsigned char *) 0xa8040044 = 0x0d;	// primary to IRQ 14
--	*(unsigned char *) 0xa8040075 = 0x0d;	// secondary to IRQ 14
--#endif
--
--	/* enable IDE in the M5229 config register 0x50 (bit 0 - 1) */
--	/* M5229 IDSEL is addr:24; see above setting */
--	*(unsigned char *) 0xa9000050 |= 0x1;
--
--	/* enable bus master (bit 2)  and IO decoding  (bit 0) */
--	*(unsigned char *) 0xa9000004 |= 0x5;
--
--	/* enable native, copied from arch/ppc/k2boot/head.S */
--	/* TODO - need volatile, need to be portable */
--	*(unsigned char *) 0xa9000009 = 0xff;
--
--	/* ----- end of M1543 PCI setup ------ */
--
--	/* ----- reset on-board ether chip  ------ */
--	*((volatile u32 *) 0xa8020004) |= 1;	/* decode I/O */
--	*((volatile u32 *) 0xa8020010) = 0;	/* set BAR address */
--
--	/* send reset command */
--	*((volatile u32 *) 0xa6000000) = 1;	/* do a soft reset */
--
--	/* disable ether chip */
--	*((volatile u32 *) 0xa8020004) = 0;	/* disable any decoding */
--
--	/* put it into sleep */
--	*((volatile u32 *) 0xa8020040) = 0x80000000;
--
--	/* ----- end of reset on-board ether chip  ------ */
--
--	/* ----------- switch PCI1 back to PCI MEM space  ------------ */
--	ddb_set_pdar(DDB_PCIW1, DDB_PCI_MEM_BASE, DDB_PCI_MEM_SIZE, 32, 0, 1);
--	ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_MEM, DDB_PCI_MEM_BASE, DDB_PCI_ACCESS_32);
--}
-diff -Naur linux-2.6.17.orig/arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c linux-2.6.17/arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c
---- linux-2.6.17.orig/arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c	1969-12-31 16:00:00.000000000 -0800
-@@ -1,109 +0,0 @@
--/*
-- * The irq controller for vrc5476.
-- *
-- * Copyright (C) 2001 MontaVista Software Inc.
-- * Author: jsun@mvista.com or jsun@junsun.net
-- *
-- * This program is free software; you can redistribute  it and/or modify it
-- * under  the terms of  the GNU General  Public License as published by the
-- * Free Software Foundation;  either version 2 of the  License, or (at your
-- * option) any later version.
-- *
-- */
--#include <linux/init.h>
--#include <linux/interrupt.h>
--#include <linux/irq.h>
--#include <linux/types.h>
--#include <linux/ptrace.h>
--
--#include <asm/system.h>
--
--#include <asm/ddb5xxx/ddb5xxx.h>
--
--static int irq_base;
--
--static void vrc5476_irq_enable(uint irq)
--{
--	nile4_enable_irq(irq - irq_base);
--}
--
--static void vrc5476_irq_disable(uint irq)
--{
--	nile4_disable_irq(irq - irq_base);
--}
--
--static unsigned int vrc5476_irq_startup(uint irq)
--{
--	nile4_enable_irq(irq - irq_base);
--	return 0;
--}
--
--#define vrc5476_irq_shutdown	vrc5476_irq_disable
--
--static void vrc5476_irq_ack(uint irq)
--{
--	nile4_clear_irq(irq - irq_base);
--	nile4_disable_irq(irq - irq_base);
--}
--
--static void vrc5476_irq_end(uint irq)
--{
--	if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
--		vrc5476_irq_enable(irq);
--}
--
--static hw_irq_controller vrc5476_irq_controller = {
--	.typename = "vrc5476",
--	.startup = vrc5476_irq_startup,
--	.shutdown = vrc5476_irq_shutdown,
--	.enable = vrc5476_irq_enable,
--	.disable = vrc5476_irq_disable,
--	.ack = vrc5476_irq_ack,
--	.end = vrc5476_irq_end
--};
--
--void __init
--vrc5476_irq_init(u32 base)
--{
--	u32 i;
--
--	irq_base = base;
--	for (i= base; i< base + NUM_VRC5476_IRQ; i++) {
--		irq_desc[i].status = IRQ_DISABLED;
--		irq_desc[i].action = NULL;
--		irq_desc[i].depth = 1;
--		irq_desc[i].handler = &vrc5476_irq_controller;
--	}
--}
--
--
--void
--vrc5476_irq_dispatch(struct pt_regs *regs)
--{
--	u32 mask;
--	int nile4_irq;
--
--	mask = nile4_get_irq_stat(0);
--
--	/* quick check for possible time interrupt */
--	if (mask & (1 << VRC5476_IRQ_GPT)) {
--		do_IRQ(VRC5476_IRQ_BASE + VRC5476_IRQ_GPT, regs);
--		return;
--	}
--
--	/* check for i8259 interrupts */
--	if (mask & (1 << VRC5476_I8259_CASCADE)) {
--		int i8259_irq = nile4_i8259_iack();
--		do_IRQ(I8259_IRQ_BASE + i8259_irq, regs);
--		return;
--	}
--
--	/* regular nile4 interrupts (we should not really have any */
--	for (nile4_irq = 0; mask; nile4_irq++, mask >>= 1) {
--		if (mask & 1) {
--			do_IRQ(VRC5476_IRQ_BASE + nile4_irq, regs);
--			return;
--		}
--	}
--	spurious_interrupt(regs);
--}
-diff -Naur linux-2.6.17.orig/arch/mips/ddb5xxx/ddb5477/setup.c linux-2.6.17/arch/mips/ddb5xxx/ddb5477/setup.c
---- linux-2.6.17.orig/arch/mips/ddb5xxx/ddb5477/setup.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/ddb5xxx/ddb5477/setup.c	2006-06-19 18:16:13.000000000 -0700
-@@ -171,7 +171,7 @@
- extern struct pci_controller ddb5477_ext_controller;
- extern struct pci_controller ddb5477_io_controller;
- 
--void __init plat_setup(void)
-+void __init plat_mem_setup(void)
- {
- 	/* initialize board - we don't trust the loader */
-         ddb5477_board_init();
-diff -Naur linux-2.6.17.orig/arch/mips/dec/setup.c linux-2.6.17/arch/mips/dec/setup.c
---- linux-2.6.17.orig/arch/mips/dec/setup.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/dec/setup.c	2006-06-19 18:16:13.000000000 -0700
-@@ -147,7 +147,7 @@
- extern void dec_time_init(void);
- extern void dec_timer_setup(struct irqaction *);
- 
--void __init plat_setup(void)
-+void __init plat_mem_setup(void)
- {
- 	board_be_init = dec_be_init;
- 	board_time_init = dec_time_init;
-diff -Naur linux-2.6.17.orig/arch/mips/defconfig linux-2.6.17/arch/mips/defconfig
---- linux-2.6.17.orig/arch/mips/defconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/defconfig	2006-06-19 18:16:13.000000000 -0700
-@@ -41,8 +41,6 @@
- # CONFIG_MIPS_XXS1500 is not set
- # CONFIG_PNX8550_V2PCI is not set
- # CONFIG_PNX8550_JBS is not set
--# CONFIG_DDB5074 is not set
--# CONFIG_DDB5476 is not set
- # CONFIG_DDB5477 is not set
- # CONFIG_MACH_VR41XX is not set
- # CONFIG_PMC_YOSEMITE is not set
-@@ -67,6 +65,7 @@
- CONFIG_GENERIC_FIND_NEXT_BIT=y
- CONFIG_GENERIC_HWEIGHT=y
- CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
- CONFIG_ARC=y
- CONFIG_DMA_NONCOHERENT=y
- CONFIG_DMA_NEED_PCI_MAP_STATE=y
-diff -Naur linux-2.6.17.orig/arch/mips/emma2rh/common/irq.c linux-2.6.17/arch/mips/emma2rh/common/irq.c
---- linux-2.6.17.orig/arch/mips/emma2rh/common/irq.c	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/arch/mips/emma2rh/common/irq.c	2006-06-19 18:16:13.000000000 -0700
-@@ -0,0 +1,108 @@
-+/*
-+ *  arch/mips/emma2rh/common/irq.c
-+ *      This file is common irq dispatcher.
-+ *
-+ *  Copyright (C) NEC Electronics Corporation 2005-2006
-+ *
-+ *  This file is based on the arch/mips/ddb5xxx/ddb5477/irq.c
-+ *
-+ *	Copyright 2001 MontaVista Software Inc.
-+ *
-+ *  This program is free software; you can redistribute it and/or modify
-+ *  it under the terms of the GNU General Public License as published by
-+ *  the Free Software Foundation; either version 2 of the License, or
-+ *  (at your option) any later version.
-+ *
-+ *  This program is distributed in the hope that it will be useful,
-+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ *  GNU General Public License for more details.
-+ *
-+ *  You should have received a copy of the GNU General Public License
-+ *  along with this program; if not, write to the Free Software
-+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-+ */
-+#include <linux/config.h>
-+#include <linux/init.h>
-+#include <linux/interrupt.h>
-+#include <linux/irq.h>
-+#include <linux/types.h>
-+
-+#include <asm/i8259.h>
-+#include <asm/system.h>
-+#include <asm/mipsregs.h>
-+#include <asm/debug.h>
-+#include <asm/addrspace.h>
-+#include <asm/bootinfo.h>
-+
-+#include <asm/emma2rh/emma2rh.h>
-+
-+/*
-+ * the first level int-handler will jump here if it is a emma2rh irq
-+ */
-+asmlinkage void emma2rh_irq_dispatch(struct pt_regs *regs)
-+{
-+	u32 intStatus;
-+	u32 bitmask;
-+	u32 i;
-+
-+	intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_0)
-+	    & emma2rh_in32(EMMA2RH_BHIF_INT_EN_0);
-+
-+#ifdef EMMA2RH_SW_CASCADE
-+	if (intStatus &
-+	    (1 << ((EMMA2RH_SW_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) {
-+		u32 swIntStatus;
-+		swIntStatus = emma2rh_in32(EMMA2RH_BHIF_SW_INT)
-+		    & emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
-+		for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
-+			if (swIntStatus & bitmask) {
-+				do_IRQ(EMMA2RH_SW_IRQ_BASE + i, regs);
-+				return;
-+			}
-+		}
-+	}
-+#endif
-+
-+	for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
-+		if (intStatus & bitmask) {
-+			do_IRQ(EMMA2RH_IRQ_BASE + i, regs);
-+			return;
-+		}
-+	}
-+
-+	intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_1)
-+	    & emma2rh_in32(EMMA2RH_BHIF_INT_EN_1);
-+
-+#ifdef EMMA2RH_GPIO_CASCADE
-+	if (intStatus &
-+	    (1 << ((EMMA2RH_GPIO_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) {
-+		u32 gpioIntStatus;
-+		gpioIntStatus = emma2rh_in32(EMMA2RH_GPIO_INT_ST)
-+		    & emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
-+		for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
-+			if (gpioIntStatus & bitmask) {
-+				do_IRQ(EMMA2RH_GPIO_IRQ_BASE + i, regs);
-+				return;
-+			}
-+		}
-+	}
-+#endif
-+
-+	for (i = 32, bitmask = 1; i < 64; i++, bitmask <<= 1) {
-+		if (intStatus & bitmask) {
-+			do_IRQ(EMMA2RH_IRQ_BASE + i, regs);
-+			return;
-+		}
-+	}
-+
-+	intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_2)
-+	    & emma2rh_in32(EMMA2RH_BHIF_INT_EN_2);
-+
-+	for (i = 64, bitmask = 1; i < 96; i++, bitmask <<= 1) {
-+		if (intStatus & bitmask) {
-+			do_IRQ(EMMA2RH_IRQ_BASE + i, regs);
-+			return;
-+		}
-+	}
-+}
-diff -Naur linux-2.6.17.orig/arch/mips/emma2rh/common/irq_emma2rh.c linux-2.6.17/arch/mips/emma2rh/common/irq_emma2rh.c
---- linux-2.6.17.orig/arch/mips/emma2rh/common/irq_emma2rh.c	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/arch/mips/emma2rh/common/irq_emma2rh.c	2006-06-19 18:16:13.000000000 -0700
-@@ -0,0 +1,134 @@
-+/*
-+ *  arch/mips/emma2rh/common/irq_emma2rh.c
-+ *      This file defines the irq handler for EMMA2RH.
-+ *
-+ *  Copyright (C) NEC Electronics Corporation 2005-2006
-+ *
-+ *  This file is based on the arch/mips/ddb5xxx/ddb5477/irq_5477.c
-+ *
-+ *	Copyright 2001 MontaVista Software Inc.
-+ *
-+ *  This program is free software; you can redistribute it and/or modify
-+ *  it under the terms of the GNU General Public License as published by
-+ *  the Free Software Foundation; either version 2 of the License, or
-+ *  (at your option) any later version.
-+ *
-+ *  This program is distributed in the hope that it will be useful,
-+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ *  GNU General Public License for more details.
-+ *
-+ *  You should have received a copy of the GNU General Public License
-+ *  along with this program; if not, write to the Free Software
-+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-+ */
-+
-+/*
-+ * EMMA2RH defines 64 IRQs.
-+ *
-+ * This file exports one function:
-+ *	emma2rh_irq_init(u32 irq_base);
-+ */
-+
-+#include <linux/interrupt.h>
-+#include <linux/types.h>
-+#include <linux/ptrace.h>
-+
-+#include <asm/debug.h>
-+
-+#include <asm/emma2rh/emma2rh.h>
-+
-+/* number of total irqs supported by EMMA2RH */
-+#define	NUM_EMMA2RH_IRQ		96
-+
-+static int emma2rh_irq_base = -1;
-+
-+void ll_emma2rh_irq_enable(int);
-+void ll_emma2rh_irq_disable(int);
-+
-+static void emma2rh_irq_enable(unsigned int irq)
-+{
-+	ll_emma2rh_irq_enable(irq - emma2rh_irq_base);
-+}
-+
-+static void emma2rh_irq_disable(unsigned int irq)
-+{
-+	ll_emma2rh_irq_disable(irq - emma2rh_irq_base);
-+}
-+
-+static unsigned int emma2rh_irq_startup(unsigned int irq)
-+{
-+	emma2rh_irq_enable(irq);
-+	return 0;
-+}
-+
-+#define	emma2rh_irq_shutdown	emma2rh_irq_disable
-+
-+static void emma2rh_irq_ack(unsigned int irq)
-+{
-+	/* disable interrupt - some handler will re-enable the irq
-+	 * and if the interrupt is leveled, we will have infinite loop
-+	 */
-+	ll_emma2rh_irq_disable(irq - emma2rh_irq_base);
-+}
-+
-+static void emma2rh_irq_end(unsigned int irq)
-+{
-+	if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
-+		ll_emma2rh_irq_enable(irq - emma2rh_irq_base);
-+}
-+
-+hw_irq_controller emma2rh_irq_controller = {
-+	.typename = "emma2rh_irq",
-+	.startup = emma2rh_irq_startup,
-+	.shutdown = emma2rh_irq_shutdown,
-+	.enable = emma2rh_irq_enable,
-+	.disable = emma2rh_irq_disable,
-+	.ack = emma2rh_irq_ack,
-+	.end = emma2rh_irq_end,
-+	.set_affinity = NULL	/* no affinity stuff for UP */
-+};
-+
-+void emma2rh_irq_init(u32 irq_base)
-+{
-+	u32 i;
-+
-+	for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ; i++) {
-+		irq_desc[i].status = IRQ_DISABLED;
-+		irq_desc[i].action = NULL;
-+		irq_desc[i].depth = 1;
-+		irq_desc[i].handler = &emma2rh_irq_controller;
-+	}
-+
-+	emma2rh_irq_base = irq_base;
-+}
-+
-+void ll_emma2rh_irq_enable(int emma2rh_irq)
-+{
-+	u32 reg_value;
-+	u32 reg_bitmask;
-+	u32 reg_index;
-+
-+	reg_index = EMMA2RH_BHIF_INT_EN_0
-+	    + (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0)
-+	    * (emma2rh_irq / 32);
-+	reg_value = emma2rh_in32(reg_index);
-+	reg_bitmask = 0x1 << (emma2rh_irq % 32);
-+	db_assert((reg_value & reg_bitmask) == 0);
-+	emma2rh_out32(reg_index, reg_value | reg_bitmask);
-+}
-+
-+void ll_emma2rh_irq_disable(int emma2rh_irq)
-+{
-+	u32 reg_value;
-+	u32 reg_bitmask;
-+	u32 reg_index;
-+
-+	reg_index = EMMA2RH_BHIF_INT_EN_0
-+	    + (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0)
-+	    * (emma2rh_irq / 32);
-+	reg_value = emma2rh_in32(reg_index);
-+	reg_bitmask = 0x1 << (emma2rh_irq % 32);
-+	db_assert((reg_value & reg_bitmask) != 0);
-+	emma2rh_out32(reg_index, reg_value & ~reg_bitmask);
-+}
-diff -Naur linux-2.6.17.orig/arch/mips/emma2rh/common/Makefile linux-2.6.17/arch/mips/emma2rh/common/Makefile
---- linux-2.6.17.orig/arch/mips/emma2rh/common/Makefile	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/arch/mips/emma2rh/common/Makefile	2006-06-19 18:16:13.000000000 -0700
-@@ -0,0 +1,13 @@
-+#
-+#  arch/mips/emma2rh/common/Makefile
-+#       Makefile for the common code of NEC EMMA2RH based board.
-+#
-+#  Copyright (C) NEC Electronics Corporation 2005-2006
-+#
-+#  This program is free software; you can redistribute it and/or modify
-+#  it under the terms of the GNU General Public License as published by
-+#  the Free Software Foundation; either version 2 of the License, or
-+#  (at your option) any later version.
-+#
-+
-+obj-$(CONFIG_MARKEINS)	+= irq.o irq_emma2rh.o prom.o
-diff -Naur linux-2.6.17.orig/arch/mips/emma2rh/common/prom.c linux-2.6.17/arch/mips/emma2rh/common/prom.c
---- linux-2.6.17.orig/arch/mips/emma2rh/common/prom.c	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/arch/mips/emma2rh/common/prom.c	2006-06-19 18:16:13.000000000 -0700
-@@ -0,0 +1,77 @@
-+/*
-+ *  arch/mips/emma2rh/common/prom.c
-+ *      This file is prom file.
-+ *
-+ *  Copyright (C) NEC Electronics Corporation 2004-2006
-+ *
-+ *  This file is based on the arch/mips/ddb5xxx/common/prom.c
-+ *
-+ *	Copyright 2001 MontaVista Software Inc.
-+ *
-+ *  This program is free software; you can redistribute it and/or modify
-+ *  it under the terms of the GNU General Public License as published by
-+ *  the Free Software Foundation; either version 2 of the License, or
-+ *  (at your option) any later version.
-+ *
-+ *  This program is distributed in the hope that it will be useful,
-+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ *  GNU General Public License for more details.
-+ *
-+ *  You should have received a copy of the GNU General Public License
-+ *  along with this program; if not, write to the Free Software
-+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-+ */
-+#include <linux/config.h>
-+#include <linux/init.h>
-+#include <linux/mm.h>
-+#include <linux/sched.h>
-+#include <linux/bootmem.h>
-+
-+#include <asm/addrspace.h>
-+#include <asm/bootinfo.h>
-+#include <asm/emma2rh/emma2rh.h>
-+#include <asm/debug.h>
-+
-+const char *get_system_type(void)
-+{
-+	switch (mips_machtype) {
-+	case MACH_NEC_MARKEINS:
-+		return "NEC EMMA2RH Mark-eins";
-+	default:
-+		return "Unknown NEC board";
-+	}
-+}
-+
-+/* [jsun@junsun.net] PMON passes arguments in C main() style */
-+void __init prom_init(void)
-+{
-+	int argc = fw_arg0;
-+	char **arg = (char **)fw_arg1;
-+	int i;
-+
-+	/* if user passes kernel args, ignore the default one */
-+	if (argc > 1)
-+		arcs_cmdline[0] = '\0';
-+
-+	/* arg[0] is "g", the rest is boot parameters */
-+	for (i = 1; i < argc; i++) {
-+		if (strlen(arcs_cmdline) + strlen(arg[i] + 1)
-+		    >= sizeof(arcs_cmdline))
-+			break;
-+		strcat(arcs_cmdline, arg[i]);
-+		strcat(arcs_cmdline, " ");
-+	}
-+
-+	mips_machgroup = MACH_GROUP_NEC_EMMA2RH;
-+
-+#if defined(CONFIG_MARKEINS)
-+	mips_machtype = MACH_NEC_MARKEINS;
-+	add_memory_region(0, EMMA2RH_RAM_SIZE, BOOT_MEM_RAM);
-+#endif
-+
-+}
-+
-+void __init prom_free_prom_memory(void)
-+{
-+}
-diff -Naur linux-2.6.17.orig/arch/mips/emma2rh/markeins/irq.c linux-2.6.17/arch/mips/emma2rh/markeins/irq.c
---- linux-2.6.17.orig/arch/mips/emma2rh/markeins/irq.c	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/arch/mips/emma2rh/markeins/irq.c	2006-06-19 18:16:13.000000000 -0700
-@@ -0,0 +1,134 @@
-+/*
-+ *  arch/mips/emma2rh/markeins/irq.c
-+ *      This file defines the irq handler for EMMA2RH.
-+ *
-+ *  Copyright (C) NEC Electronics Corporation 2004-2006
-+ *
-+ *  This file is based on the arch/mips/ddb5xxx/ddb5477/irq.c
-+ *
-+ *	Copyright 2001 MontaVista Software Inc.
-+ *
-+ *  This program is free software; you can redistribute it and/or modify
-+ *  it under the terms of the GNU General Public License as published by
-+ *  the Free Software Foundation; either version 2 of the License, or
-+ *  (at your option) any later version.
-+ *
-+ *  This program is distributed in the hope that it will be useful,
-+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ *  GNU General Public License for more details.
-+ *
-+ *  You should have received a copy of the GNU General Public License
-+ *  along with this program; if not, write to the Free Software
-+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-+ */
-+#include <linux/config.h>
-+#include <linux/init.h>
-+#include <linux/interrupt.h>
-+#include <linux/irq.h>
-+#include <linux/types.h>
-+#include <linux/ptrace.h>
-+#include <linux/delay.h>
-+
-+#include <asm/i8259.h>
-+#include <asm/irq_cpu.h>
-+#include <asm/system.h>
-+#include <asm/mipsregs.h>
-+#include <asm/debug.h>
-+#include <asm/addrspace.h>
-+#include <asm/bootinfo.h>
-+
-+#include <asm/emma2rh/emma2rh.h>
-+
-+/*
-+ * IRQ mapping
-+ *
-+ *  0-7: 8 CPU interrupts
-+ *	0 -	software interrupt 0
-+ *	1 - 	software interrupt 1
-+ *	2 - 	most Vrc5477 interrupts are routed to this pin
-+ *	3 - 	(optional) some other interrupts routed to this pin for debugg
-+ *	4 - 	not used
-+ *	5 - 	not used
-+ *	6 - 	not used
-+ *	7 - 	cpu timer (used by default)
-+ *
-+ */
-+
-+extern void emma2rh_sw_irq_init(u32 base);
-+extern void emma2rh_gpio_irq_init(u32 base);
-+extern void emma2rh_irq_init(u32 base);
-+extern asmlinkage void emma2rh_irq_dispatch(struct pt_regs *regs);
-+
-+static struct irqaction irq_cascade = {
-+	   .handler = no_action,
-+	   .flags = 0,
-+	   .mask = CPU_MASK_NONE,
-+	   .name = "cascade",
-+	   .dev_id = NULL,
-+	   .next = NULL,
-+};
-+
-+void __init arch_init_irq(void)
-+{
-+	u32 reg;
-+
-+	db_run(printk("markeins_irq_setup invoked.\n"));
-+
-+	/* by default, interrupts are disabled. */
-+	emma2rh_out32(EMMA2RH_BHIF_INT_EN_0, 0);
-+	emma2rh_out32(EMMA2RH_BHIF_INT_EN_1, 0);
-+	emma2rh_out32(EMMA2RH_BHIF_INT_EN_2, 0);
-+	emma2rh_out32(EMMA2RH_BHIF_INT1_EN_0, 0);
-+	emma2rh_out32(EMMA2RH_BHIF_INT1_EN_1, 0);
-+	emma2rh_out32(EMMA2RH_BHIF_INT1_EN_2, 0);
-+	emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, 0);
-+
-+	clear_c0_status(0xff00);
-+	set_c0_status(0x0400);
-+
-+#define GPIO_PCI (0xf<<15)
-+	/* setup GPIO interrupt for PCI interface */
-+	/* direction input */
-+	reg = emma2rh_in32(EMMA2RH_GPIO_DIR);
-+	emma2rh_out32(EMMA2RH_GPIO_DIR, reg & ~GPIO_PCI);
-+	/* disable interrupt */
-+	reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
-+	emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg & ~GPIO_PCI);
-+	/* level triggerd */
-+	reg = emma2rh_in32(EMMA2RH_GPIO_INT_MODE);
-+	emma2rh_out32(EMMA2RH_GPIO_INT_MODE, reg | GPIO_PCI);
-+	reg = emma2rh_in32(EMMA2RH_GPIO_INT_CND_A);
-+	emma2rh_out32(EMMA2RH_GPIO_INT_CND_A, reg & (~GPIO_PCI));
-+	/* interrupt clear */
-+	emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~GPIO_PCI);
-+
-+	/* init all controllers */
-+	emma2rh_irq_init(EMMA2RH_IRQ_BASE);
-+	emma2rh_sw_irq_init(EMMA2RH_SW_IRQ_BASE);
-+	emma2rh_gpio_irq_init(EMMA2RH_GPIO_IRQ_BASE);
-+	mips_cpu_irq_init(CPU_IRQ_BASE);
-+
-+	/* setup cascade interrupts */
-+	setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_SW_CASCADE, &irq_cascade);
-+	setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_GPIO_CASCADE, &irq_cascade);
-+	setup_irq(CPU_IRQ_BASE + CPU_EMMA2RH_CASCADE, &irq_cascade);
-+}
-+
-+asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
-+{
-+        unsigned int pending = read_c0_status() & read_c0_cause();
-+
-+	if (pending & STATUSF_IP7)
-+		do_IRQ(CPU_IRQ_BASE + 7, regs);
-+	else if (pending & STATUSF_IP2)
-+		emma2rh_irq_dispatch(regs);
-+	else if (pending & STATUSF_IP1)
-+		do_IRQ(CPU_IRQ_BASE + 1, regs);
-+	else if (pending & STATUSF_IP0)
-+		do_IRQ(CPU_IRQ_BASE + 0, regs);
-+	else
-+		spurious_interrupt(regs);
-+}
-+
-+
-diff -Naur linux-2.6.17.orig/arch/mips/emma2rh/markeins/irq_markeins.c linux-2.6.17/arch/mips/emma2rh/markeins/irq_markeins.c
---- linux-2.6.17.orig/arch/mips/emma2rh/markeins/irq_markeins.c	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/arch/mips/emma2rh/markeins/irq_markeins.c	2006-06-19 18:16:13.000000000 -0700
-@@ -0,0 +1,197 @@
-+/*
-+ *  arch/mips/emma2rh/markeins/irq_markeins.c
-+ *      This file defines the irq handler for Mark-eins.
-+ *
-+ *  Copyright (C) NEC Electronics Corporation 2004-2006
-+ *
-+ *  This file is based on the arch/mips/ddb5xxx/ddb5477/irq_5477.c
-+ *
-+ *	Copyright 2001 MontaVista Software Inc.
-+ *
-+ *  This program is free software; you can redistribute it and/or modify
-+ *  it under the terms of the GNU General Public License as published by
-+ *  the Free Software Foundation; either version 2 of the License, or
-+ *  (at your option) any later version.
-+ *
-+ *  This program is distributed in the hope that it will be useful,
-+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ *  GNU General Public License for more details.
-+ *
-+ *  You should have received a copy of the GNU General Public License
-+ *  along with this program; if not, write to the Free Software
-+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-+ */
-+#include <linux/interrupt.h>
-+#include <linux/irq.h>
-+#include <linux/types.h>
-+#include <linux/ptrace.h>
-+
-+#include <asm/debug.h>
-+#include <asm/emma2rh/emma2rh.h>
-+
-+static int emma2rh_sw_irq_base = -1;
-+static int emma2rh_gpio_irq_base = -1;
-+
-+void ll_emma2rh_sw_irq_enable(int reg);
-+void ll_emma2rh_sw_irq_disable(int reg);
-+void ll_emma2rh_gpio_irq_enable(int reg);
-+void ll_emma2rh_gpio_irq_disable(int reg);
-+
-+static void emma2rh_sw_irq_enable(unsigned int irq)
-+{
-+	ll_emma2rh_sw_irq_enable(irq - emma2rh_sw_irq_base);
-+}
-+
-+static void emma2rh_sw_irq_disable(unsigned int irq)
-+{
-+	ll_emma2rh_sw_irq_disable(irq - emma2rh_sw_irq_base);
-+}
-+
-+static unsigned int emma2rh_sw_irq_startup(unsigned int irq)
-+{
-+	emma2rh_sw_irq_enable(irq);
-+	return 0;
-+}
-+
-+#define emma2rh_sw_irq_shutdown emma2rh_sw_irq_disable
-+
-+static void emma2rh_sw_irq_ack(unsigned int irq)
-+{
-+	ll_emma2rh_sw_irq_disable(irq - emma2rh_sw_irq_base);
-+}
-+
-+static void emma2rh_sw_irq_end(unsigned int irq)
-+{
-+	if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
-+		ll_emma2rh_sw_irq_enable(irq - emma2rh_sw_irq_base);
-+}
-+
-+hw_irq_controller emma2rh_sw_irq_controller = {
-+	.typename = "emma2rh_sw_irq",
-+	.startup = emma2rh_sw_irq_startup,
-+	.shutdown = emma2rh_sw_irq_shutdown,
-+	.enable = emma2rh_sw_irq_enable,
-+	.disable = emma2rh_sw_irq_disable,
-+	.ack = emma2rh_sw_irq_ack,
-+	.end = emma2rh_sw_irq_end,
-+	.set_affinity = NULL,
-+};
-+
-+void emma2rh_sw_irq_init(u32 irq_base)
-+{
-+	u32 i;
-+
-+	for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ_SW; i++) {
-+		irq_desc[i].status = IRQ_DISABLED;
-+		irq_desc[i].action = NULL;
-+		irq_desc[i].depth = 2;
-+		irq_desc[i].handler = &emma2rh_sw_irq_controller;
-+	}
-+
-+	emma2rh_sw_irq_base = irq_base;
-+}
-+
-+void ll_emma2rh_sw_irq_enable(int irq)
-+{
-+	u32 reg;
-+
-+	db_assert(irq >= 0);
-+	db_assert(irq < NUM_EMMA2RH_IRQ_SW);
-+
-+	reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
-+	reg |= 1 << irq;
-+	emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg);
-+}
-+
-+void ll_emma2rh_sw_irq_disable(int irq)
-+{
-+	u32 reg;
-+
-+	db_assert(irq >= 0);
-+	db_assert(irq < 32);
-+
-+	reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
-+	reg &= ~(1 << irq);
-+	emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg);
-+}
-+
-+static void emma2rh_gpio_irq_enable(unsigned int irq)
-+{
-+	ll_emma2rh_gpio_irq_enable(irq - emma2rh_gpio_irq_base);
-+}
-+
-+static void emma2rh_gpio_irq_disable(unsigned int irq)
-+{
-+	ll_emma2rh_gpio_irq_disable(irq - emma2rh_gpio_irq_base);
-+}
-+
-+static unsigned int emma2rh_gpio_irq_startup(unsigned int irq)
-+{
-+	emma2rh_gpio_irq_enable(irq);
-+	return 0;
-+}
-+
-+#define emma2rh_gpio_irq_shutdown emma2rh_gpio_irq_disable
-+
-+static void emma2rh_gpio_irq_ack(unsigned int irq)
-+{
-+	irq -= emma2rh_gpio_irq_base;
-+	emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq));
-+	ll_emma2rh_gpio_irq_disable(irq);
-+}
-+
-+static void emma2rh_gpio_irq_end(unsigned int irq)
-+{
-+	if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
-+		ll_emma2rh_gpio_irq_enable(irq - emma2rh_gpio_irq_base);
-+}
-+
-+hw_irq_controller emma2rh_gpio_irq_controller = {
-+	.typename = "emma2rh_gpio_irq",
-+	.startup = emma2rh_gpio_irq_startup,
-+	.shutdown = emma2rh_gpio_irq_shutdown,
-+	.enable = emma2rh_gpio_irq_enable,
-+	.disable = emma2rh_gpio_irq_disable,
-+	.ack = emma2rh_gpio_irq_ack,
-+	.end = emma2rh_gpio_irq_end,
-+	.set_affinity = NULL,
-+};
-+
-+void emma2rh_gpio_irq_init(u32 irq_base)
-+{
-+	u32 i;
-+
-+	for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ_GPIO; i++) {
-+		irq_desc[i].status = IRQ_DISABLED;
-+		irq_desc[i].action = NULL;
-+		irq_desc[i].depth = 2;
-+		irq_desc[i].handler = &emma2rh_gpio_irq_controller;
-+	}
-+
-+	emma2rh_gpio_irq_base = irq_base;
-+}
-+
-+void ll_emma2rh_gpio_irq_enable(int irq)
-+{
-+	u32 reg;
-+
-+	db_assert(irq >= 0);
-+	db_assert(irq < NUM_EMMA2RH_IRQ_GPIO);
-+
-+	reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
-+	reg |= 1 << irq;
-+	emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
-+}
-+
-+void ll_emma2rh_gpio_irq_disable(int irq)
-+{
-+	u32 reg;
-+
-+	db_assert(irq >= 0);
-+	db_assert(irq < NUM_EMMA2RH_IRQ_GPIO);
-+
-+	reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
-+	reg &= ~(1 << irq);
-+	emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
-+}
-diff -Naur linux-2.6.17.orig/arch/mips/emma2rh/markeins/led.c linux-2.6.17/arch/mips/emma2rh/markeins/led.c
---- linux-2.6.17.orig/arch/mips/emma2rh/markeins/led.c	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/arch/mips/emma2rh/markeins/led.c	2006-06-19 18:16:13.000000000 -0700
-@@ -0,0 +1,60 @@
-+/*
-+ *  arch/mips/emma2rh/markeins/led.c
-+ *      This file defines the led display for Mark-eins.
-+ *
-+ *  Copyright (C) NEC Electronics Corporation 2004-2006
-+ *
-+ *  This program is free software; you can redistribute it and/or modify
-+ *  it under the terms of the GNU General Public License as published by
-+ *  the Free Software Foundation; either version 2 of the License, or
-+ *  (at your option) any later version.
-+ *
-+ *  This program is distributed in the hope that it will be useful,
-+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ *  GNU General Public License for more details.
-+ *
-+ *  You should have received a copy of the GNU General Public License
-+ *  along with this program; if not, write to the Free Software
-+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-+ */
-+#include <linux/kernel.h>
-+#include <linux/types.h>
-+#include <linux/string.h>
-+#include <asm/emma2rh/emma2rh.h>
-+
-+const unsigned long clear = 0x20202020;
-+
-+#define LED_BASE 0xb1400038
-+
-+void markeins_led_clear(void)
-+{
-+	emma2rh_out32(LED_BASE, clear);
-+	emma2rh_out32(LED_BASE + 4, clear);
-+}
-+
-+void markeins_led(const char *str)
-+{
-+	int i;
-+	int len = strlen(str);
-+
-+	markeins_led_clear();
-+	if (len > 8)
-+		len = 8;
-+
-+	if (emma2rh_in32(0xb0000800) & (0x1 << 18))
-+		for (i = 0; i < len; i++)
-+			emma2rh_out8(LED_BASE + i, str[i]);
-+	else
-+		for (i = 0; i < len; i++)
-+			emma2rh_out8(LED_BASE + (i & 4) + (3 - (i & 3)),
-+				     str[i]);
-+}
-+
-+void markeins_led_hex(u32 val)
-+{
-+	char str[10];
-+
-+	sprintf(str, "%08x", val);
-+	markeins_led(str);
-+}
-diff -Naur linux-2.6.17.orig/arch/mips/emma2rh/markeins/Makefile linux-2.6.17/arch/mips/emma2rh/markeins/Makefile
---- linux-2.6.17.orig/arch/mips/emma2rh/markeins/Makefile	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/arch/mips/emma2rh/markeins/Makefile	2006-06-19 18:16:13.000000000 -0700
-@@ -0,0 +1,13 @@
-+#
-+#  arch/mips/emma2rh/markeins/Makefile
-+#       Makefile for the common code of NEC EMMA2RH based board.
-+#
-+#  Copyright (C) NEC Electronics Corporation 2005-2006
-+#
-+#  This program is free software; you can redistribute it and/or modify
-+#  it under the terms of the GNU General Public License as published by
-+#  the Free Software Foundation; either version 2 of the License, or
-+#  (at your option) any later version.
-+#
-+
-+obj-$(CONFIG_MARKEINS) += irq.o irq_markeins.o setup.o led.o platform.o
-diff -Naur linux-2.6.17.orig/arch/mips/emma2rh/markeins/platform.c linux-2.6.17/arch/mips/emma2rh/markeins/platform.c
---- linux-2.6.17.orig/arch/mips/emma2rh/markeins/platform.c	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/arch/mips/emma2rh/markeins/platform.c	2006-06-19 18:16:13.000000000 -0700
-@@ -0,0 +1,170 @@
-+/*
-+ *  arch/mips/emma2rh/markeins/platofrm.c
-+ *      This file sets up platform devices for EMMA2RH Mark-eins.
-+ *
-+ *  Copyright(C) MontaVista Software Inc, 2006
-+ *
-+ *  Author: dmitry pervushin <dpervushin@ru.mvista.com>
-+ *
-+ *  This program is free software; you can redistribute it and/or modify
-+ *  it under the terms of the GNU General Public License as published by
-+ *  the Free Software Foundation; either version 2 of the License, or
-+ *  (at your option) any later version.
-+ *
-+ *  This program is distributed in the hope that it will be useful,
-+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ *  GNU General Public License for more details.
-+ *
-+ *  You should have received a copy of the GNU General Public License
-+ *  along with this program; if not, write to the Free Software
-+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-+ */
-+#include <linux/config.h>
-+#include <linux/init.h>
-+#include <linux/kernel.h>
-+#include <linux/types.h>
-+#include <linux/ioport.h>
-+#include <linux/serial_8250.h>
-+#include <linux/mtd/physmap.h>
-+
-+#include <asm/cpu.h>
-+#include <asm/bootinfo.h>
-+#include <asm/addrspace.h>
-+#include <asm/time.h>
-+#include <asm/bcache.h>
-+#include <asm/irq.h>
-+#include <asm/reboot.h>
-+#include <asm/gdb-stub.h>
-+#include <asm/traps.h>
-+#include <asm/debug.h>
-+
-+#include <asm/emma2rh/emma2rh.h>
-+
-+
-+#define I2C_EMMA2RH "emma2rh-iic" /* must be in sync with IIC driver */
-+
-+static struct resource i2c_emma_resources_0[] = {
-+	{ NULL, EMMA2RH_IRQ_PIIC0, EMMA2RH_IRQ_PIIC0, IORESOURCE_IRQ },
-+	{ NULL, KSEG1ADDR(EMMA2RH_PIIC0_BASE), KSEG1ADDR(EMMA2RH_PIIC0_BASE + 0x1000), 0 },
-+};
-+
-+struct resource i2c_emma_resources_1[] = {
-+	{ NULL, EMMA2RH_IRQ_PIIC1, EMMA2RH_IRQ_PIIC1, IORESOURCE_IRQ },
-+	{ NULL, KSEG1ADDR(EMMA2RH_PIIC1_BASE), KSEG1ADDR(EMMA2RH_PIIC1_BASE + 0x1000), 0 },
-+};
-+
-+struct resource i2c_emma_resources_2[] = {
-+	{ NULL, EMMA2RH_IRQ_PIIC2, EMMA2RH_IRQ_PIIC2, IORESOURCE_IRQ },
-+	{ NULL, KSEG1ADDR(EMMA2RH_PIIC2_BASE), KSEG1ADDR(EMMA2RH_PIIC2_BASE + 0x1000), 0 },
-+};
-+
-+struct platform_device i2c_emma_devices[] = {
-+	[0] = {
-+		.name = I2C_EMMA2RH,
-+		.id = 0,
-+		.resource = i2c_emma_resources_0,
-+		.num_resources = ARRAY_SIZE(i2c_emma_resources_0),
-+	},
-+	[1] = {
-+		.name = I2C_EMMA2RH,
-+		.id = 1,
-+		.resource = i2c_emma_resources_1,
-+		.num_resources = ARRAY_SIZE(i2c_emma_resources_1),
-+	},
-+	[2] = {
-+		.name = I2C_EMMA2RH,
-+		.id = 2,
-+		.resource = i2c_emma_resources_2,
-+		.num_resources = ARRAY_SIZE(i2c_emma_resources_2),
-+	},
-+};
-+
-+#define EMMA2RH_SERIAL_CLOCK 18544000
-+#define EMMA2RH_SERIAL_FLAGS UPF_BOOT_AUTOCONF | UPF_SKIP_TEST
-+
-+static struct  plat_serial8250_port platform_serial_ports[] = {
-+       [0] = {
-+         .membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR0_BASE + 3),
-+         .irq = EMMA2RH_IRQ_PFUR0,
-+         .uartclk = EMMA2RH_SERIAL_CLOCK,
-+         .regshift = 4,
-+         .iotype = UPIO_MEM,
-+         .flags = EMMA2RH_SERIAL_FLAGS,
-+       },
-+       [1] = {
-+         .membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR1_BASE + 3),
-+         .irq = EMMA2RH_IRQ_PFUR1,
-+         .uartclk = EMMA2RH_SERIAL_CLOCK,
-+         .regshift = 4,
-+         .iotype = UPIO_MEM,
-+         .flags = EMMA2RH_SERIAL_FLAGS,
-+       },
-+       [2] = {
-+         .membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR2_BASE + 3),
-+         .irq = EMMA2RH_IRQ_PFUR2,
-+         .uartclk = EMMA2RH_SERIAL_CLOCK,
-+         .regshift = 4,
-+         .iotype = UPIO_MEM,
-+         .flags = EMMA2RH_SERIAL_FLAGS,
-+       },
-+       [3] = {
-+	 .flags = 0,
-+       },
-+};
-+
-+static struct  platform_device serial_emma = {
-+	.name = "serial8250",
-+	.dev = {
-+		.platform_data = &platform_serial_ports,
-+	},
-+};
-+
-+static struct platform_device *devices[] = {
-+	&i2c_emma_devices[0],
-+	&i2c_emma_devices[1],
-+	&i2c_emma_devices[2],
-+	&serial_emma,
-+};
-+
-+static struct mtd_partition markeins_parts[] = {
-+	[0] = {
-+		.name = "RootFS",
-+		.offset = 0x00000000,
-+		.size = 0x00c00000,
-+	},
-+	[1] = {
-+		.name = "boot code area",
-+		.offset = MTDPART_OFS_APPEND,
-+		.size = 0x00100000,
-+	},
-+	[2] = {
-+		.name = "kernel image",
-+		.offset = MTDPART_OFS_APPEND,
-+		.size = 0x00300000,
-+	},
-+	[3] = {
-+		.name = "RootFS2",
-+		.offset = MTDPART_OFS_APPEND,
-+		.size = 0x00c00000,
-+	},
-+	[4] = {
-+		.name = "boot code area2",
-+		.offset = MTDPART_OFS_APPEND,
-+		.size = 0x00100000,
-+	},
-+	[5] = {
-+		.name = "kernel image2",
-+		.offset = MTDPART_OFS_APPEND,
-+		.size = MTDPART_SIZ_FULL,
-+	},
-+};
-+
-+static int __init platform_devices_setup(void)
-+{
-+	physmap_set_partitions(markeins_parts, ARRAY_SIZE(markeins_parts));
-+	return platform_add_devices(devices, ARRAY_SIZE(devices));
-+}
-+
-+arch_initcall(platform_devices_setup);
-+
-diff -Naur linux-2.6.17.orig/arch/mips/emma2rh/markeins/setup.c linux-2.6.17/arch/mips/emma2rh/markeins/setup.c
---- linux-2.6.17.orig/arch/mips/emma2rh/markeins/setup.c	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/arch/mips/emma2rh/markeins/setup.c	2006-06-19 18:16:13.000000000 -0700
-@@ -0,0 +1,182 @@
-+/*
-+ *  arch/mips/emma2rh/markeins/setup.c
-+ *      This file is setup for EMMA2RH Mark-eins.
-+ *
-+ *  Copyright (C) NEC Electronics Corporation 2004-2006
-+ *
-+ *  This file is based on the arch/mips/ddb5xxx/ddb5477/setup.c.
-+ *
-+ *	Copyright 2001 MontaVista Software Inc.
-+ *
-+ *  This program is free software; you can redistribute it and/or modify
-+ *  it under the terms of the GNU General Public License as published by
-+ *  the Free Software Foundation; either version 2 of the License, or
-+ *  (at your option) any later version.
-+ *
-+ *  This program is distributed in the hope that it will be useful,
-+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ *  GNU General Public License for more details.
-+ *
-+ *  You should have received a copy of the GNU General Public License
-+ *  along with this program; if not, write to the Free Software
-+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-+ */
-+#include <linux/config.h>
-+#include <linux/init.h>
-+#include <linux/kernel.h>
-+#include <linux/types.h>
-+#include <linux/initrd.h>
-+#include <linux/irq.h>
-+#include <linux/ide.h>
-+#include <linux/ioport.h>
-+#include <linux/param.h>	/* for HZ */
-+#include <linux/root_dev.h>
-+#include <linux/serial.h>
-+#include <linux/serial_core.h>
-+
-+#include <asm/cpu.h>
-+#include <asm/bootinfo.h>
-+#include <asm/addrspace.h>
-+#include <asm/time.h>
-+#include <asm/bcache.h>
-+#include <asm/irq.h>
-+#include <asm/reboot.h>
-+#include <asm/gdb-stub.h>
-+#include <asm/traps.h>
-+#include <asm/debug.h>
-+
-+#include <asm/emma2rh/emma2rh.h>
-+
-+#define	USE_CPU_COUNTER_TIMER	/* whether we use cpu counter */
-+
-+extern void markeins_led(const char *);
-+
-+static int bus_frequency = 0;
-+
-+static void markeins_machine_restart(char *command)
-+{
-+	static void (*back_to_prom) (void) = (void (*)(void))0xbfc00000;
-+
-+	printk("cannot EMMA2RH Mark-eins restart.\n");
-+	markeins_led("restart.");
-+	back_to_prom();
-+}
-+
-+static void markeins_machine_halt(void)
-+{
-+	printk("EMMA2RH Mark-eins halted.\n");
-+	markeins_led("halted.");
-+	while (1) ;
-+}
-+
-+static void markeins_machine_power_off(void)
-+{
-+	printk("EMMA2RH Mark-eins halted. Please turn off the power.\n");
-+	markeins_led("poweroff.");
-+	while (1) ;
-+}
-+
-+static unsigned long clock[4] = { 166500000, 187312500, 199800000, 210600000 };
-+
-+static unsigned int __init detect_bus_frequency(unsigned long rtc_base)
-+{
-+	u32 reg;
-+
-+	/* detect from boot strap */
-+	reg = emma2rh_in32(EMMA2RH_BHIF_STRAP_0);
-+	reg = (reg >> 4) & 0x3;
-+	return clock[reg];
-+}
-+
-+static void __init emma2rh_time_init(void)
-+{
-+	u32 reg;
-+	if (bus_frequency == 0)
-+		bus_frequency = detect_bus_frequency(0);
-+
-+	reg = emma2rh_in32(EMMA2RH_BHIF_STRAP_0);
-+	if ((reg & 0x3) == 0)
-+		reg = (reg >> 6) & 0x3;
-+	else {
-+		reg = emma2rh_in32(EMMA2RH_BHIF_MAIN_CTRL);
-+		reg = (reg >> 4) & 0x3;
-+	}
-+	mips_hpt_frequency = (bus_frequency * (4 + reg)) / 4 / 2;
-+}
-+
-+static void __init emma2rh_timer_setup(struct irqaction *irq)
-+{
-+	/* we are using the cpu counter for timer interrupts */
-+	setup_irq(CPU_IRQ_BASE + 7, irq);
-+}
-+
-+static void markeins_board_init(void);
-+extern void markeins_irq_setup(void);
-+
-+static void inline __init markeins_sio_setup(void)
-+{
-+#ifdef CONFIG_KGDB_8250
-+	struct uart_port emma_port;
-+
-+	memset(&emma_port, 0, sizeof(emma_port));
-+
-+	emma_port.flags =
-+	    UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
-+	emma_port.iotype = UPIO_MEM;
-+	emma_port.regshift = 4;	/* I/O addresses are every 8 bytes */
-+	emma_port.uartclk = 18544000;	/* Clock rate of the chip */
-+
-+	emma_port.line = 0;
-+	emma_port.mapbase = KSEG1ADDR(EMMA2RH_PFUR0_BASE + 3);
-+	emma_port.membase = (u8*)emma_port.mapbase;
-+	early_serial_setup(&emma_port);
-+
-+	emma_port.line = 1;
-+	emma_port.mapbase = KSEG1ADDR(EMMA2RH_PFUR1_BASE + 3);
-+	emma_port.membase = (u8*)emma_port.mapbase;
-+	early_serial_setup(&emma_port);
-+
-+	emma_port.irq = EMMA2RH_IRQ_PFUR1;
-+	kgdb8250_add_port(1, &emma_port);
-+#endif
-+}
-+
-+void __init plat_mem_setup(void)
-+{
-+	/* initialize board - we don't trust the loader */
-+	markeins_board_init();
-+
-+	set_io_port_base(KSEG1ADDR(EMMA2RH_PCI_IO_BASE));
-+
-+	board_time_init = emma2rh_time_init;
-+	board_timer_setup = emma2rh_timer_setup;
-+
-+	_machine_restart = markeins_machine_restart;
-+	_machine_halt = markeins_machine_halt;
-+	pm_power_off = markeins_machine_power_off;
-+
-+	/* setup resource limits */
-+	ioport_resource.start = EMMA2RH_PCI_IO_BASE;
-+	ioport_resource.end = EMMA2RH_PCI_IO_BASE + EMMA2RH_PCI_IO_SIZE - 1;
-+	iomem_resource.start = EMMA2RH_IO_BASE;
-+	iomem_resource.end = EMMA2RH_ROM_BASE - 1;
-+
-+	/* Reboot on panic */
-+	panic_timeout = 180;
-+
-+	markeins_sio_setup();
-+}
-+
-+static void __init markeins_board_init(void)
-+{
-+	u32 val;
-+
-+	val = emma2rh_in32(EMMA2RH_PBRD_INT_EN);	/* open serial interrupts. */
-+	emma2rh_out32(EMMA2RH_PBRD_INT_EN, val | 0xaa);
-+	val = emma2rh_in32(EMMA2RH_PBRD_CLKSEL);	/* set serial clocks. */
-+	emma2rh_out32(EMMA2RH_PBRD_CLKSEL, val | 0x5);	/* 18MHz */
-+	emma2rh_out32(EMMA2RH_PCI_CONTROL, 0);
-+
-+	markeins_led("MVL E2RH");
-+}
-diff -Naur linux-2.6.17.orig/arch/mips/galileo-boards/ev96100/setup.c linux-2.6.17/arch/mips/galileo-boards/ev96100/setup.c
---- linux-2.6.17.orig/arch/mips/galileo-boards/ev96100/setup.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/galileo-boards/ev96100/setup.c	2006-06-19 18:16:13.000000000 -0700
-@@ -55,7 +55,7 @@
- 
- unsigned char mac_0_1[12];
- 
--void __init plat_setup(void)
-+void __init plat_mem_setup(void)
- {
- 	unsigned int config = read_c0_config();
- 	unsigned int status = read_c0_status();
-diff -Naur linux-2.6.17.orig/arch/mips/gt64120/ev64120/setup.c linux-2.6.17/arch/mips/gt64120/ev64120/setup.c
---- linux-2.6.17.orig/arch/mips/gt64120/ev64120/setup.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/gt64120/ev64120/setup.c	2006-06-19 18:16:13.000000000 -0700
-@@ -71,7 +71,7 @@
-  */
- extern void gt64120_time_init(void);
- 
--void __init plat_setup(void)
-+void __init plat_mem_setup(void)
- {
- 	_machine_restart = galileo_machine_restart;
- 	_machine_halt = galileo_machine_halt;
-diff -Naur linux-2.6.17.orig/arch/mips/gt64120/momenco_ocelot/setup.c linux-2.6.17/arch/mips/gt64120/momenco_ocelot/setup.c
---- linux-2.6.17.orig/arch/mips/gt64120/momenco_ocelot/setup.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/gt64120/momenco_ocelot/setup.c	2006-06-19 18:16:13.000000000 -0700
-@@ -152,7 +152,7 @@
- 	gt64120_base = 0xe0000000;
- }
- 
--void __init plat_setup(void)
-+void __init plat_mem_setup(void)
- {
- 	void (*l3func)(unsigned long)=KSEG1ADDR(&setup_l3cache);
- 	unsigned int tmpword;
-diff -Naur linux-2.6.17.orig/arch/mips/gt64120/wrppmc/int-handler.S linux-2.6.17/arch/mips/gt64120/wrppmc/int-handler.S
---- linux-2.6.17.orig/arch/mips/gt64120/wrppmc/int-handler.S	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/arch/mips/gt64120/wrppmc/int-handler.S	2006-06-19 18:16:13.000000000 -0700
-@@ -0,0 +1,59 @@
-+/*
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License.  See the file "COPYING" in the main directory of this archive
-+ * for more details.
-+ *
-+ * Copyright (C) 1995, 1996, 1997, 2003 by Ralf Baechle
-+ * Copyright (C) Wind River System Inc. Rongkai.Zhan <rongkai.zhan@windriver.com>
-+ */
-+#include <asm/asm.h>
-+#include <asm/mipsregs.h>
-+#include <asm/addrspace.h>
-+#include <asm/regdef.h>
-+#include <asm/stackframe.h>
-+#include <asm/mach-wrppmc/mach-gt64120.h>
-+
-+	.align	5
-+	.set	noat
-+NESTED(handle_IRQ, PT_SIZE, sp)
-+	SAVE_ALL
-+	CLI				# Important: mark KERNEL mode !
-+	.set	at
-+
-+	mfc0	t0, CP0_CAUSE		# get pending interrupts
-+	mfc0	t1, CP0_STATUS		# get enabled interrupts
-+	and	t0, t0, t1		# get allowed interrupts
-+	andi	t0, t0, 0xFF00
-+	beqz	t0, 1f
-+	move	a1, sp			# Prepare 'struct pt_regs *regs' pointer
-+
-+	andi	t1, t0, CAUSEF_IP7	# CPU Compare/Count internal timer
-+	bnez	t1, handle_cputimer_irq
-+	andi	t1, t0, CAUSEF_IP6	# UART 16550 port
-+	bnez	t1, handle_uart_irq
-+	andi	t1, t0, CAUSEF_IP3	# PCI INT_A
-+	bnez	t1, handle_pci_intA_irq
-+
-+	/* wrong alarm or masked ... */
-+1:	j	spurious_interrupt
-+	nop
-+END(handle_IRQ)
-+
-+	.align	5
-+handle_cputimer_irq:
-+	li	a0, WRPPMC_MIPS_TIMER_IRQ
-+	jal	do_IRQ
-+	j	ret_from_irq
-+
-+	.align	5
-+handle_uart_irq:
-+	li	a0, WRPPMC_UART16550_IRQ
-+	jal	do_IRQ
-+	j	ret_from_irq
-+
-+	.align	5
-+handle_pci_intA_irq:
-+	li	a0, WRPPMC_PCI_INTA_IRQ
-+	jal	do_IRQ
-+	j	ret_from_irq
-+
-diff -Naur linux-2.6.17.orig/arch/mips/gt64120/wrppmc/irq.c linux-2.6.17/arch/mips/gt64120/wrppmc/irq.c
---- linux-2.6.17.orig/arch/mips/gt64120/wrppmc/irq.c	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/arch/mips/gt64120/wrppmc/irq.c	2006-06-19 18:16:13.000000000 -0700
-@@ -0,0 +1,63 @@
-+/*
-+ * irq.c: GT64120 Interrupt Controller
-+ *
-+ * Copyright (C) 2006, Wind River System Inc.
-+ * Author: Rongkai.Zhan, <rongkai.zhan@windriver.com>
-+ *
-+ * This program is free software; you can redistribute  it and/or modify it
-+ * under  the terms of  the GNU General  Public License as published by the
-+ * Free Software Foundation;  either version 2 of the  License, or (at your
-+ * option) any later version.
-+ */
-+#include <linux/errno.h>
-+#include <linux/init.h>
-+#include <linux/kernel_stat.h>
-+#include <linux/module.h>
-+#include <linux/signal.h>
-+#include <linux/sched.h>
-+#include <linux/types.h>
-+#include <linux/interrupt.h>
-+#include <linux/ioport.h>
-+#include <linux/timex.h>
-+#include <linux/slab.h>
-+#include <linux/random.h>
-+#include <linux/bitops.h>
-+#include <asm/bootinfo.h>
-+#include <asm/io.h>
-+#include <asm/bitops.h>
-+#include <asm/mipsregs.h>
-+#include <asm/system.h>
-+#include <asm/irq_cpu.h>
-+#include <asm/gt64120.h>
-+
-+extern asmlinkage void handle_IRQ(void);
-+
-+/**
-+ * Initialize GT64120 Interrupt Controller
-+ */
-+void gt64120_init_pic(void)
-+{
-+	/* clear CPU Interrupt Cause Registers */
-+	GT_WRITE(GT_INTRCAUSE_OFS, (0x1F << 21));
-+	GT_WRITE(GT_HINTRCAUSE_OFS, 0x00);
-+
-+	/* Disable all interrupts from GT64120 bridge chip */
-+	GT_WRITE(GT_INTRMASK_OFS, 0x00);
-+	GT_WRITE(GT_HINTRMASK_OFS, 0x00);
-+	GT_WRITE(GT_PCI0_ICMASK_OFS, 0x00);
-+	GT_WRITE(GT_PCI0_HICMASK_OFS, 0x00);
-+}
-+
-+void __init arch_init_irq(void)
-+{
-+	/* enable all CPU interrupt bits. */
-+	set_c0_status(ST0_IM);	/* IE bit is still 0 */
-+
-+	/* Install MIPS Interrupt Trap Vector */
-+	set_except_vector(0, handle_IRQ);
-+
-+	/* IRQ 0 - 7 are for MIPS common irq_cpu controller */
-+	mips_cpu_irq_init(0);
-+
-+	gt64120_init_pic();
-+}
-diff -Naur linux-2.6.17.orig/arch/mips/gt64120/wrppmc/Makefile linux-2.6.17/arch/mips/gt64120/wrppmc/Makefile
---- linux-2.6.17.orig/arch/mips/gt64120/wrppmc/Makefile	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/arch/mips/gt64120/wrppmc/Makefile	2006-06-19 18:16:13.000000000 -0700
-@@ -0,0 +1,14 @@
-+#
-+# This file is subject to the terms and conditions of the GNU General Public
-+# License.  See the file "COPYING" in the main directory of this archive
-+# for more details.
-+#
-+# Copyright 2006 Wind River System, Inc.
-+# Author: Rongkai.Zhan <rongkai.zhan@windriver.com>
-+#
-+# Makefile for the Wind River MIPS 4KC PPMC Eval Board
-+#
-+
-+obj-y	+= int-handler.o irq.o reset.o setup.o time.o pci.o
-+
-+EXTRA_AFLAGS := $(CFLAGS)
-diff -Naur linux-2.6.17.orig/arch/mips/gt64120/wrppmc/pci.c linux-2.6.17/arch/mips/gt64120/wrppmc/pci.c
---- linux-2.6.17.orig/arch/mips/gt64120/wrppmc/pci.c	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/arch/mips/gt64120/wrppmc/pci.c	2006-06-19 18:16:13.000000000 -0700
-@@ -0,0 +1,53 @@
-+/*
-+ * pci.c: GT64120 PCI support.
-+ *
-+ * Copyright (C) 2006, Wind River System Inc. Rongkai.Zhan <rongkai.zhan@windriver.com>
-+ *
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License.  See the file "COPYING" in the main directory of this archive
-+ * for more details.
-+ */
-+#include <linux/init.h>
-+#include <linux/types.h>
-+#include <linux/pci.h>
-+#include <linux/kernel.h>
-+#include <asm/gt64120.h>
-+
-+extern struct pci_ops gt64120_pci_ops;
-+
-+static struct resource pci0_io_resource = {
-+	.name  = "pci_0 io",
-+	.start = GT_PCI_IO_BASE,
-+	.end   = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1,
-+	.flags = IORESOURCE_IO,
-+};
-+
-+static struct resource pci0_mem_resource = {
-+	.name  = "pci_0 memory",
-+	.start = GT_PCI_MEM_BASE,
-+	.end   = GT_PCI_MEM_BASE + GT_PCI_MEM_SIZE - 1,
-+	.flags = IORESOURCE_MEM,
-+};
-+
-+static struct pci_controller hose_0 = {
-+	.pci_ops	= &gt64120_pci_ops,
-+	.io_resource	= &pci0_io_resource,
-+	.mem_resource	= &pci0_mem_resource,
-+};
-+
-+static int __init gt64120_pci_init(void)
-+{
-+	u32 tmp;
-+
-+	tmp = GT_READ(GT_PCI0_CMD_OFS);		/* Huh??? -- Ralf  */
-+	tmp = GT_READ(GT_PCI0_BARE_OFS);
-+
-+	/* reset the whole PCI I/O space range */
-+	ioport_resource.start = GT_PCI_IO_BASE;
-+	ioport_resource.end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1;
-+
-+	register_pci_controller(&hose_0);
-+	return 0;
-+}
-+
-+arch_initcall(gt64120_pci_init);
-diff -Naur linux-2.6.17.orig/arch/mips/gt64120/wrppmc/reset.c linux-2.6.17/arch/mips/gt64120/wrppmc/reset.c
---- linux-2.6.17.orig/arch/mips/gt64120/wrppmc/reset.c	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/arch/mips/gt64120/wrppmc/reset.c	2006-06-19 18:16:13.000000000 -0700
-@@ -0,0 +1,50 @@
-+/*
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License.  See the file "COPYING" in the main directory of this archive
-+ * for more details.
-+ *
-+ * Copyright (C) 1997 Ralf Baechle
-+ */
-+#include <linux/sched.h>
-+#include <linux/mm.h>
-+#include <asm/io.h>
-+#include <asm/pgtable.h>
-+#include <asm/processor.h>
-+#include <asm/reboot.h>
-+#include <asm/system.h>
-+#include <asm/cacheflush.h>
-+
-+void wrppmc_machine_restart(char *command)
-+{
-+	/*
-+	 * Ouch, we're still alive ... This time we take the silver bullet ...
-+	 * ... and find that we leave the hardware in a state in which the
-+	 * kernel in the flush locks up somewhen during of after the PCI
-+	 * detection stuff.
-+	 */
-+	local_irq_disable();
-+	set_c0_status(ST0_BEV | ST0_ERL);
-+	change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
-+	flush_cache_all();
-+	write_c0_wired(0);
-+	__asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
-+}
-+
-+void wrppmc_machine_halt(void)
-+{
-+	local_irq_disable();
-+
-+	printk(KERN_NOTICE "You can safely turn off the power\n");
-+	while (1) {
-+		__asm__(
-+			".set\tmips3\n\t"
-+			"wait\n\t"
-+			".set\tmips0"
-+		);
-+	}
-+}
-+
-+void wrppmc_machine_power_off(void)
-+{
-+	wrppmc_machine_halt();
-+}
-diff -Naur linux-2.6.17.orig/arch/mips/gt64120/wrppmc/setup.c linux-2.6.17/arch/mips/gt64120/wrppmc/setup.c
---- linux-2.6.17.orig/arch/mips/gt64120/wrppmc/setup.c	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/arch/mips/gt64120/wrppmc/setup.c	2006-06-19 18:16:13.000000000 -0700
-@@ -0,0 +1,173 @@
-+/*
-+ * setup.c: Setup pointers to hardware dependent routines.
-+ *
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License.  See the file "COPYING" in the main directory of this archive
-+ * for more details.
-+ *
-+ * Copyright (C) 1996, 1997, 2004 by Ralf Baechle (ralf@linux-mips.org)
-+ * Copyright (C) 2006, Wind River System Inc. Rongkai.zhan <rongkai.zhan@windriver.com>
-+ */
-+#include <linux/config.h>
-+#include <linux/init.h>
-+#include <linux/string.h>
-+#include <linux/kernel.h>
-+#include <linux/tty.h>
-+#include <linux/serial.h>
-+#include <linux/serial_core.h>
-+#include <linux/pm.h>
-+
-+#include <asm/io.h>
-+#include <asm/bootinfo.h>
-+#include <asm/reboot.h>
-+#include <asm/time.h>
-+#include <asm/gt64120.h>
-+
-+unsigned long gt64120_base = KSEG1ADDR(0x14000000);
-+
-+#ifdef WRPPMC_EARLY_DEBUG
-+
-+static volatile unsigned char * wrppmc_led = \
-+	(volatile unsigned char *)KSEG1ADDR(WRPPMC_LED_BASE);
-+
-+/*
-+ * PPMC LED control register:
-+ * -) bit[0] controls DS1 LED (1 - OFF, 0 - ON)
-+ * -) bit[1] controls DS2 LED (1 - OFF, 0 - ON)
-+ * -) bit[2] controls DS4 LED (1 - OFF, 0 - ON)
-+ */
-+void wrppmc_led_on(int mask)
-+{
-+	unsigned char value = *wrppmc_led;
-+
-+	value &= (0xF8 | mask);
-+	*wrppmc_led = value;
-+}
-+
-+/* If mask = 0, turn off all LEDs */
-+void wrppmc_led_off(int mask)
-+{
-+	unsigned char value = *wrppmc_led;
-+
-+	value |= (0x7 & mask);
-+	*wrppmc_led = value;
-+}
-+
-+/*
-+ * We assume that bootloader has initialized UART16550 correctly
-+ */
-+void __init wrppmc_early_putc(char ch)
-+{
-+	static volatile unsigned char *wrppmc_uart = \
-+		(volatile unsigned char *)KSEG1ADDR(WRPPMC_UART16550_BASE);
-+	unsigned char value;
-+
-+	/* Wait until Transmit-Holding-Register is empty */
-+	while (1) {
-+		value = *(wrppmc_uart + 5);
-+		if (value & 0x20)
-+			break;
-+	}
-+
-+	*wrppmc_uart = ch;
-+}
-+
-+void __init wrppmc_early_printk(const char *fmt, ...)
-+{
-+	static char pbuf[256] = {'\0', };
-+	char *ch = pbuf;
-+	va_list args;
-+	unsigned int i;
-+
-+	memset(pbuf, 0, 256);
-+	va_start(args, fmt);
-+	i = vsprintf(pbuf, fmt, args);
-+	va_end(args);
-+
-+	/* Print the string */
-+	while (*ch != '\0') {
-+		wrppmc_early_putc(*ch);
-+		/* if print '\n', also print '\r' */
-+		if (*ch++ == '\n')
-+			wrppmc_early_putc('\r');
-+	}
-+}
-+#endif /* WRPPMC_EARLY_DEBUG */
-+
-+unsigned long __init prom_free_prom_memory(void)
-+{
-+	return 0;
-+}
-+
-+#ifdef CONFIG_SERIAL_8250
-+static void wrppmc_setup_serial(void)
-+{
-+	struct uart_port up;
-+
-+	memset(&up, 0x00, sizeof(struct uart_port));
-+
-+	/*
-+	 * A note about mapbase/membase
-+	 * -) mapbase is the physical address of the IO port.
-+	 * -) membase is an 'ioremapped' cookie.
-+	 */
-+	up.line = 0;
-+	up.type = PORT_16550;
-+	up.iotype = UPIO_MEM;
-+	up.mapbase = WRPPMC_UART16550_BASE;
-+	up.membase = ioremap(up.mapbase, 8);
-+	up.irq = WRPPMC_UART16550_IRQ;
-+	up.uartclk = WRPPMC_UART16550_CLOCK;
-+	up.flags = UPF_SKIP_TEST/* | UPF_BOOT_AUTOCONF */;
-+	up.regshift = 0;
-+
-+	early_serial_setup(&up);
-+}
-+#endif
-+
-+void __init plat_setup(void)
-+{
-+	extern void wrppmc_time_init(void);
-+	extern void wrppmc_timer_setup(struct irqaction *);
-+	extern void wrppmc_machine_restart(char *command);
-+	extern void wrppmc_machine_halt(void);
-+	extern void wrppmc_machine_power_off(void);
-+
-+	_machine_restart = wrppmc_machine_restart;
-+	_machine_halt	 = wrppmc_machine_halt;
-+	pm_power_off	 = wrppmc_machine_power_off;
-+
-+	/* Use MIPS Count/Compare Timer */
-+	board_time_init   = wrppmc_time_init;
-+	board_timer_setup = wrppmc_timer_setup;
-+
-+	/* This makes the operations of 'in/out[bwl]' to the
-+	 * physical address ( < KSEG0) can work via KSEG1
-+	 */
-+	set_io_port_base(KSEG1);
-+
-+#ifdef CONFIG_SERIAL_8250
-+	wrppmc_setup_serial();
-+#endif
-+}
-+
-+const char *get_system_type(void)
-+{
-+	return "Wind River PPMC (GT64120)";
-+}
-+
-+/*
-+ * Initializes basic routines and structures pointers, memory size (as
-+ * given by the bios and saves the command line.
-+ */
-+void __init prom_init(void)
-+{
-+	mips_machgroup = MACH_GROUP_GALILEO;
-+	mips_machtype = MACH_EV64120A;
-+
-+	add_memory_region(WRPPMC_SDRAM_SCS0_BASE, WRPPMC_SDRAM_SCS0_SIZE, BOOT_MEM_RAM);
-+	add_memory_region(WRPPMC_BOOTROM_BASE, WRPPMC_BOOTROM_SIZE, BOOT_MEM_ROM_DATA);
-+
-+	wrppmc_early_printk("prom_init: GT64120 SDRAM Bank 0: 0x%x - 0x%08lx\n",
-+			WRPPMC_SDRAM_SCS0_BASE, (WRPPMC_SDRAM_SCS0_BASE + WRPPMC_SDRAM_SCS0_SIZE));
-+}
-diff -Naur linux-2.6.17.orig/arch/mips/gt64120/wrppmc/time.c linux-2.6.17/arch/mips/gt64120/wrppmc/time.c
---- linux-2.6.17.orig/arch/mips/gt64120/wrppmc/time.c	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/arch/mips/gt64120/wrppmc/time.c	2006-06-19 18:16:13.000000000 -0700
-@@ -0,0 +1,57 @@
-+/*
-+ * time.c: MIPS CPU Count/Compare timer hookup
-+ *
-+ * Author: Mark.Zhan, <rongkai.zhan@windriver.com>
-+ *
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License.  See the file "COPYING" in the main directory of this archive
-+ * for more details.
-+ *
-+ * Copyright (C) 1996, 1997, 2004 by Ralf Baechle (ralf@linux-mips.org)
-+ * Copyright (C) 2006, Wind River System Inc.
-+ */
-+#include <linux/config.h>
-+#include <linux/init.h>
-+#include <linux/string.h>
-+#include <linux/kernel.h>
-+#include <linux/param.h>	/* for HZ */
-+#include <linux/irq.h>
-+#include <linux/timex.h>
-+#include <linux/interrupt.h>
-+
-+#include <asm/reboot.h>
-+#include <asm/time.h>
-+#include <asm/io.h>
-+#include <asm/bootinfo.h>
-+#include <asm/gt64120.h>
-+
-+#define WRPPMC_CPU_CLK_FREQ 40000000 /* 40MHZ */
-+
-+void __init wrppmc_timer_setup(struct irqaction *irq)
-+{
-+	/* Install ISR for timer interrupt */
-+	setup_irq(WRPPMC_MIPS_TIMER_IRQ, irq);
-+
-+	/* to generate the first timer interrupt */
-+	write_c0_compare(mips_hpt_frequency/HZ);
-+	write_c0_count(0);
-+}
-+
-+/*
-+ * Estimate CPU frequency.  Sets mips_hpt_frequency as a side-effect
-+ *
-+ * NOTE: We disable all GT64120 timers, and use MIPS processor internal
-+ * timer as the source of kernel clock tick.
-+ */
-+void __init wrppmc_time_init(void)
-+{
-+	/* Disable GT64120 timers */
-+	GT_WRITE(GT_TC_CONTROL_OFS, 0x00);
-+	GT_WRITE(GT_TC0_OFS, 0x00);
-+	GT_WRITE(GT_TC1_OFS, 0x00);
-+	GT_WRITE(GT_TC2_OFS, 0x00);
-+	GT_WRITE(GT_TC3_OFS, 0x00);
-+
-+	/* Use MIPS compare/count internal timer */
-+	mips_hpt_frequency = WRPPMC_CPU_CLK_FREQ;
-+}
-diff -Naur linux-2.6.17.orig/arch/mips/ite-boards/generic/it8172_setup.c linux-2.6.17/arch/mips/ite-boards/generic/it8172_setup.c
---- linux-2.6.17.orig/arch/mips/ite-boards/generic/it8172_setup.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/ite-boards/generic/it8172_setup.c	2006-06-19 18:16:13.000000000 -0700
-@@ -72,11 +72,29 @@
-     struct resource flash;
-     struct resource boot;
- } it8172_resources = {
--    { "RAM",           0,          0,          IORESOURCE_MEM }, /* to be initted */
--    { "PCI Mem",       0x10000000, 0x13FFFFFF, IORESOURCE_MEM },
--    { "PCI I/O",       0x14000000, 0x17FFFFFF                 },
--    { "Flash",         0x08000000, 0x0CFFFFFF                 },
--    { "Boot ROM",      0x1FC00000, 0x1FFFFFFF                 }
-+	{
-+		.start	= 0,				/* to be initted */
-+		.end	= 0,
-+		.name	= "RAM",
-+		.flags	= IORESOURCE_MEM
-+	}, {
-+		.start	= 0x10000000,
-+		.end	= 0x13FFFFFF,
-+		.name	= "PCI Mem",
-+		.flags	= IORESOURCE_MEM
-+	}, {
-+		.start	= 0x14000000,
-+		.end	= 0x17FFFFFF
-+		.name	= "PCI I/O",
-+	}, {
-+		.start	= 0x08000000,
-+		.end	= 0x0CFFFFFF
-+		.name	= "Flash",
-+	}, {
-+		.start	= 0x1FC00000,
-+		.end	= 0x1FFFFFFF
-+		.name	= "Boot ROM",
-+	}
- };
- #else
- struct {
-@@ -89,14 +107,44 @@
-     struct resource flash;
-     struct resource boot;
- } it8172_resources = {
--    { "RAM",           0,          0,          IORESOURCE_MEM }, /* to be initted */
--    { "PCI Mem0",      0x0C000000, 0x0FFFFFFF, IORESOURCE_MEM },
--    { "PCI Mem1",      0x10000000, 0x13FFFFFF, IORESOURCE_MEM },
--    { "PCI I/O",       0x14000000, 0x17FFFFFF                 },
--    { "PCI Mem2",      0x1A000000, 0x1BFFFFFF, IORESOURCE_MEM },
--    { "PCI Mem3",      0x1C000000, 0x1FBFFFFF, IORESOURCE_MEM },
--    { "Flash",         0x08000000, 0x0CFFFFFF                 },
--    { "Boot ROM",      0x1FC00000, 0x1FFFFFFF                 }
-+	{
-+		.start	= 0,				/* to be initted */
-+		.end	= 0,
-+		.name	= "RAM",
-+		.flags	= IORESOURCE_MEM
-+	}, {
-+		.start	= 0x0C000000,
-+		.end	= 0x0FFFFFFF,
-+		.name	= "PCI Mem0",
-+		.flags	= IORESOURCE_MEM
-+	 }, {
-+		.start	= 0x10000000,
-+		.end	= 0x13FFFFFF,
-+		.name	= "PCI Mem1",
-+		.flags	= IORESOURCE_MEM
-+	 }, {
-+		.start	= 0x14000000,
-+		.end	= 0x17FFFFFF
-+		.name	= "PCI I/O",
-+	}, {
-+		.start	= 0x1A000000,
-+		.end	= 0x1BFFFFFF,
-+		.name	= "PCI Mem2",
-+		.flags	= IORESOURCE_MEM
-+	}, {
-+		.start	= 0x1C000000,
-+		.end	= 0x1FBFFFFF,
-+		.name	= "PCI Mem3",
-+		.flags	= IORESOURCE_MEM
-+	}, {
-+		.start	= 0x08000000,
-+		.end	= 0x0CFFFFFF
-+		.name	= "Flash",
-+	}, {
-+		.start	= 0x1FC00000,
-+		.end	= 0x1FFFFFFF
-+		.name	= "Boot ROM",
-+	}
- };
- #endif
- 
-@@ -106,7 +154,7 @@
- 	it8172_resources.ram.end = memsize;
- }
- 
--void __init plat_setup(void)
-+void __init plat_mem_setup(void)
- {
- 	unsigned short dsr;
- 	char *argptr;
-diff -Naur linux-2.6.17.orig/arch/mips/jazz/setup.c linux-2.6.17/arch/mips/jazz/setup.c
---- linux-2.6.17.orig/arch/mips/jazz/setup.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/jazz/setup.c	2006-06-19 18:16:13.000000000 -0700
-@@ -52,7 +52,7 @@
- 	{ "dma2", 0xc0, 0xdf, IORESOURCE_BUSY },
- };
- 
--void __init plat_setup(void)
-+void __init plat_mem_setup(void)
- {
- 	int i;
- 
-diff -Naur linux-2.6.17.orig/arch/mips/jmr3927/rbhma3100/setup.c linux-2.6.17/arch/mips/jmr3927/rbhma3100/setup.c
---- linux-2.6.17.orig/arch/mips/jmr3927/rbhma3100/setup.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/jmr3927/rbhma3100/setup.c	2006-06-19 18:16:13.000000000 -0700
-@@ -82,17 +82,54 @@
-     struct resource sio0;
-     struct resource sio1;
- } jmr3927_resources = {
--    { "RAM0",           0,         0x01FFFFFF,  IORESOURCE_MEM },
--    { "RAM1",          0x02000000, 0x03FFFFFF,  IORESOURCE_MEM },
--    { "PCIMEM",        0x08000000, 0x07FFFFFF,  IORESOURCE_MEM },
--    { "IOB",           0x10000000, 0x13FFFFFF                  },
--    { "IOC",           0x14000000, 0x14FFFFFF                  },
--    { "PCIIO",         0x15000000, 0x15FFFFFF                  },
--    { "JMY1394",       0x1D000000, 0x1D3FFFFF                  },
--    { "ROM1",          0x1E000000, 0x1E3FFFFF                  },
--    { "ROM0",          0x1FC00000, 0x1FFFFFFF                  },
--    { "SIO0",          0xFFFEF300, 0xFFFEF3FF                  },
--    { "SIO1",          0xFFFEF400, 0xFFFEF4FF                  },
-+	{
-+		.start	= 0,
-+		.end	= 0x01FFFFFF,
-+		.name	= "RAM0",
-+		.flags = IORESOURCE_MEM
-+	}, {
-+		.start	= 0x02000000,
-+		.end	= 0x03FFFFFF,
-+		.name	= "RAM1",
-+		.flags = IORESOURCE_MEM
-+	}, {
-+		.start	= 0x08000000,
-+		.end	= 0x07FFFFFF,
-+		.name	= "PCIMEM",
-+		.flags = IORESOURCE_MEM
-+	}, {
-+		.start	= 0x10000000,
-+		.end	= 0x13FFFFFF,
-+		.name	= "IOB"
-+	}, {
-+		.start	= 0x14000000,
-+		.end	= 0x14FFFFFF,
-+		.name	= "IOC"
-+	}, {
-+		.start	= 0x15000000,
-+		.end	= 0x15FFFFFF,
-+		.name	= "PCIIO"
-+	}, {
-+		.start	= 0x1D000000,
-+		.end	= 0x1D3FFFFF,
-+		.name	= "JMY1394"
-+	}, {
-+		.start	= 0x1E000000,
-+		.end	= 0x1E3FFFFF,
-+		.name	= "ROM1"
-+	}, {
-+		.start	= 0x1FC00000,
-+		.end	= 0x1FFFFFFF,
-+		.name	= "ROM0"
-+	}, {
-+		.start	= 0xFFFEF300,
-+		.end	= 0xFFFEF3FF,
-+		.name	= "SIO0"
-+	}, {
-+		.start	= 0xFFFEF400,
-+		.end	= 0xFFFEF4FF,
-+		.name	= "SIO1"
-+	},
- };
- 
- /* don't enable - see errata */
-@@ -201,7 +238,7 @@
- extern struct resource pci_io_resource;
- extern struct resource pci_mem_resource;
- 
--void __init plat_setup(void)
-+void __init plat_mem_setup(void)
- {
- 	char *argptr;
- 
-diff -Naur linux-2.6.17.orig/arch/mips/Kconfig linux-2.6.17/arch/mips/Kconfig
---- linux-2.6.17.orig/arch/mips/Kconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/Kconfig	2006-06-19 18:16:13.000000000 -0700
-@@ -119,6 +119,32 @@
- 	select SYS_HAS_CPU_MIPS32_R1
- 	select SYS_SUPPORTS_LITTLE_ENDIAN
- 
-+config BASLER_EXCITE
-+	bool "Basler eXcite smart camera support"
-+	select DMA_COHERENT
-+	select HW_HAS_PCI
-+	select IRQ_CPU
-+	select IRQ_CPU_RM7K
-+	select IRQ_CPU_RM9K
-+	select SERIAL_RM9000
-+	select SYS_HAS_CPU_RM9000
-+	select SYS_SUPPORTS_32BIT_KERNEL
-+	select SYS_SUPPORTS_64BIT_KERNEL
-+	select SYS_SUPPORTS_BIG_ENDIAN
-+	help
-+	  The eXcite is a smart camera platform manufactured by
-+	  Basler Vision Technologies AG
-+
-+config BASLER_EXCITE_PROTOTYPE
-+	bool "Support for pre-release units"
-+	depends on BASLER_EXCITE
-+	default n
-+	help
-+	  Pre-series (prototype) units are different from later ones in
-+	  some ways. Select this option if you have one of these. Please
-+	  note that a kernel built with this option selected will not be
-+	  able to run on normal units.
-+
- config MIPS_COBALT
- 	bool "Cobalt Server"
- 	select DMA_NONCOHERENT
-@@ -278,6 +304,7 @@
- 	select SYS_SUPPORTS_64BIT_KERNEL
- 	select SYS_SUPPORTS_BIG_ENDIAN
- 	select SYS_SUPPORTS_LITTLE_ENDIAN
-+	select SYS_SUPPORTS_MULTITHREADING if EXPERIMENTAL
- 	help
- 	  This enables support for the MIPS Technologies Atlas evaluation
- 	  board.
-@@ -306,6 +333,7 @@
- 	select SYS_SUPPORTS_64BIT_KERNEL
- 	select SYS_SUPPORTS_BIG_ENDIAN
- 	select SYS_SUPPORTS_LITTLE_ENDIAN
-+	select SYS_SUPPORTS_MULTITHREADING
- 	help
- 	  This enables support for the MIPS Technologies Malta evaluation
- 	  board.
-@@ -327,6 +355,27 @@
- 	  This enables support for the MIPS Technologies SEAD evaluation
- 	  board.
- 
-+config WR_PPMC
-+	bool "Support for Wind River PPMC board"
-+	select IRQ_CPU
-+	select BOOT_ELF32
-+	select DMA_NONCOHERENT
-+	select HW_HAS_PCI
-+	select MIPS_GT64120
-+	select SWAP_IO_SPACE
-+	select SYS_HAS_CPU_MIPS32_R1
-+	select SYS_HAS_CPU_MIPS32_R2
-+	select SYS_HAS_CPU_MIPS64_R1
-+	select SYS_HAS_CPU_NEVADA
-+	select SYS_HAS_CPU_RM7000
-+	select SYS_SUPPORTS_32BIT_KERNEL
-+	select SYS_SUPPORTS_64BIT_KERNEL
-+	select SYS_SUPPORTS_BIG_ENDIAN
-+	select SYS_SUPPORTS_LITTLE_ENDIAN
-+	help
-+	  This enables support for the Wind River MIPS32 4KC PPMC evaluation
-+	  board, which is based on GT64120 bridge chip.
-+
- config MIPS_SIM
- 	bool 'MIPS simulator (MIPSsim)'
- 	select DMA_NONCOHERENT
-@@ -438,53 +487,16 @@
- 
- config PNX8550_V2PCI
- 	bool "Philips PNX8550 based Viper2-PCI board"
-+	depends on BROKEN
- 	select PNX8550
- 	select SYS_SUPPORTS_LITTLE_ENDIAN
- 
- config PNX8550_JBS
- 	bool "Philips PNX8550 based JBS board"
-+	depends on BROKEN
- 	select PNX8550
- 	select SYS_SUPPORTS_LITTLE_ENDIAN
- 
--config DDB5074
--	bool "NEC DDB Vrc-5074 (EXPERIMENTAL)"
--	depends on EXPERIMENTAL
--	select DDB5XXX_COMMON
--	select DMA_NONCOHERENT
--	select HAVE_STD_PC_SERIAL_PORT
--	select HW_HAS_PCI
--	select IRQ_CPU
--	select I8259
--	select ISA
--	select SYS_HAS_CPU_R5000
--	select SYS_SUPPORTS_32BIT_KERNEL
--	select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
--	select SYS_SUPPORTS_LITTLE_ENDIAN
--	help
--	  This enables support for the VR5000-based NEC DDB Vrc-5074
--	  evaluation board.
--
--config DDB5476
--	bool "NEC DDB Vrc-5476"
--	select DDB5XXX_COMMON
--	select DMA_NONCOHERENT
--	select HAVE_STD_PC_SERIAL_PORT
--	select HW_HAS_PCI
--	select IRQ_CPU
--	select I8259
--	select ISA
--	select SYS_HAS_CPU_R5432
--	select SYS_SUPPORTS_32BIT_KERNEL
--	select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
--	select SYS_SUPPORTS_LITTLE_ENDIAN
--	help
--	  This enables support for the R5432-based NEC DDB Vrc-5476
--	  evaluation board.
--
--	  Features : kernel debugging, serial terminal, NFS root fs, on-board
--	  ether port USB, AC97, PCI, PCI VGA card & framebuffer console,
--	  IDE controller, PS2 keyboard, PS2 mouse, etc.
--
- config DDB5477
- 	bool "NEC DDB Vrc-5477"
- 	select DDB5XXX_COMMON
-@@ -506,8 +518,6 @@
- config MACH_VR41XX
- 	bool "NEC VR41XX-based machines"
- 	select SYS_HAS_CPU_VR41XX
--	select SYS_SUPPORTS_32BIT_KERNEL
--	select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
- 
- config PMC_YOSEMITE
- 	bool "PMC-Sierra Yosemite eval board"
-@@ -522,6 +532,7 @@
- 	select SYS_SUPPORTS_64BIT_KERNEL
- 	select SYS_SUPPORTS_BIG_ENDIAN
- 	select SYS_SUPPORTS_HIGHMEM
-+	select SYS_SUPPORTS_SMP
- 	help
- 	  Yosemite is an evaluation board for the RM9000x2 processor
- 	  manufactured by PMC-Sierra.
-@@ -546,6 +557,20 @@
- 	  simulate actual MIPS hardware platforms.  More information on Qemu
- 	  can be found at http://www.linux-mips.org/wiki/Qemu.
- 
-+config MARKEINS
-+	bool "Support for NEC EMMA2RH Mark-eins"
-+	select DMA_NONCOHERENT
-+	select HW_HAS_PCI
-+	select IRQ_CPU
-+	select SWAP_IO_SPACE
-+	select SYS_SUPPORTS_32BIT_KERNEL
-+	select SYS_SUPPORTS_BIG_ENDIAN
-+	select SYS_SUPPORTS_LITTLE_ENDIAN
-+	select SYS_HAS_CPU_R5000
-+	help
-+	  This enables support for the R5432-based NEC Mark-eins
-+	  boards with R5500 CPU.
-+
- config SGI_IP22
- 	bool "SGI IP22 (Indy/Indigo2)"
- 	select ARC
-@@ -555,6 +580,7 @@
- 	select HW_HAS_EISA
- 	select IP22_CPU_SCACHE
- 	select IRQ_CPU
-+	select NO_ISA if ISA
- 	select SWAP_IO_SPACE
- 	select SYS_HAS_CPU_R4X00
- 	select SYS_HAS_CPU_R5000
-@@ -577,6 +603,8 @@
- 	select SYS_HAS_CPU_R10000
- 	select SYS_SUPPORTS_64BIT_KERNEL
- 	select SYS_SUPPORTS_BIG_ENDIAN
-+	select SYS_SUPPORTS_NUMA
-+	select SYS_SUPPORTS_SMP
- 	help
- 	  This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
- 	  workstations.  To compile a Linux kernel that runs on these, say Y
-@@ -707,8 +735,8 @@
- 
- config SNI_RM200_PCI
- 	bool "SNI RM200 PCI"
--	select ARC
--	select ARC32
-+	select ARC if CPU_LITTLE_ENDIAN
-+	select ARC32 if CPU_LITTLE_ENDIAN
- 	select ARCH_MAY_HAVE_PC_FDC
- 	select BOOT_ELF32
- 	select DMA_NONCOHERENT
-@@ -719,10 +747,13 @@
- 	select I8253
- 	select I8259
- 	select ISA
-+	select SWAP_IO_SPACE if CPU_BIG_ENDIAN
- 	select SYS_HAS_CPU_R4X00
-+	select SYS_HAS_CPU_R5000
-+	select R5000_CPU_SCACHE
- 	select SYS_SUPPORTS_32BIT_KERNEL
- 	select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
--	select SYS_SUPPORTS_BIG_ENDIAN if EXPERIMENTAL
-+	select SYS_SUPPORTS_BIG_ENDIAN
- 	select SYS_SUPPORTS_HIGHMEM
- 	select SYS_SUPPORTS_LITTLE_ENDIAN
- 	help
-@@ -979,6 +1010,11 @@
- config SWAP_IO_SPACE
- 	bool
- 
-+config EMMA2RH
-+	bool
-+	depends on MARKEINS
-+	default y
-+
- #
- # Unfortunately not all GT64120 systems run the chip at the same clock.
- # As the user for the clock rate and try to minimize the available options.
-@@ -1035,6 +1071,9 @@
- config HAVE_STD_PC_SERIAL_PORT
- 	bool
- 
-+config VR4181
-+	bool
-+
- config ARC_CONSOLE
- 	bool "ARC console support"
- 	depends on SGI_IP22 || SNI_RM200_PCI
-@@ -1155,7 +1194,7 @@
- 	select CPU_SUPPORTS_32BIT_KERNEL
- 	select CPU_SUPPORTS_64BIT_KERNEL
- 	help
--	  The options selects support for the NEC VR4100 series of processors.
-+	  The options selects support for the NEC VR41xx series of processors.
- 	  Only choose this option if you have one of these processors as a
- 	  kernel built with this option will not run on any other type of
- 	  processor or vice versa.
-@@ -1455,32 +1494,57 @@
- config CPU_HAS_PREFETCH
- 	bool
- 
--config MIPS_MT
--	bool "Enable MIPS MT"
--
- choice
- 	prompt "MIPS MT options"
--	depends on MIPS_MT
-+
-+config MIPS_MT_DISABLED
-+	bool "Disable multithreading support."
-+	help
-+	  Use this option if your workload can't take advantage of
-+	  MIPS hardware multithreading support.  On systems that don't have
-+	  the option of an MT-enabled processor this option will be the only
-+	  option in this menu.
- 
- config MIPS_MT_SMTC
- 	bool "SMTC: Use all TCs on all VPEs for SMP"
-+	depends on CPU_MIPS32_R2
-+	#depends on CPU_MIPS64_R2		# once there is hardware ...
-+	depends on SYS_SUPPORTS_MULTITHREADING
- 	select CPU_MIPSR2_IRQ_VI
- 	select CPU_MIPSR2_SRS
-+	select MIPS_MT
- 	select SMP
-+	help
-+	  This is a kernel model which is known a SMTC or lately has been
-+	  marketesed into SMVP.
- 
- config MIPS_MT_SMP
- 	bool "Use 1 TC on each available VPE for SMP"
-+	depends on SYS_SUPPORTS_MULTITHREADING
-+	select CPU_MIPSR2_IRQ_VI
-+	select CPU_MIPSR2_SRS
-+	select MIPS_MT
- 	select SMP
-+	help
-+	  This is a kernel model which is also known a VSMP or lately
-+	  has been marketesed into SMVP.
- 
- config MIPS_VPE_LOADER
- 	bool "VPE loader support."
--	depends on MIPS_MT
-+	depends on SYS_SUPPORTS_MULTITHREADING
-+	select MIPS_MT
- 	help
- 	  Includes a loader for loading an elf relocatable object
- 	  onto another VPE and running it.
- 
- endchoice
- 
-+config MIPS_MT
-+	bool
-+
-+config SYS_SUPPORTS_MULTITHREADING
-+	bool
-+
- config MIPS_MT_FPAFF
- 	bool "Dynamic FPU affinity for FP-intensive threads"
- 	depends on MIPS_MT
-@@ -1537,32 +1601,23 @@
- config CPU_HAS_WB
- 	bool
- 
-+#
-+# Vectored interrupt mode is an R2 feature
-+#
- config CPU_MIPSR2_IRQ_VI
--	bool "Vectored interrupt mode"
--	depends on CPU_MIPSR2
--	help
--	   Vectored interrupt mode allowing faster dispatching of interrupts.
--	   The board support code needs to be written to take advantage of this
--	   mode.  Compatibility code is included to allow the kernel to run on
--	   a CPU that does not support vectored interrupts.  It's safe to
--	   say Y here.
-+	bool
- 
-+#
-+# Extended interrupt mode is an R2 feature
-+#
- config CPU_MIPSR2_IRQ_EI
--	bool "External interrupt controller mode"
--	depends on CPU_MIPSR2
--	help
--	   Extended interrupt mode takes advantage of an external interrupt
--	   controller to allow fast dispatching from many possible interrupt
--	   sources. Say N unless you know that external interrupt support is
--	   required.
-+	bool
- 
-+#
-+# Shadow registers are an R2 feature
-+#
- config CPU_MIPSR2_SRS
--	bool "Make shadow set registers available for interrupt handlers"
--	depends on CPU_MIPSR2_IRQ_VI || CPU_MIPSR2_IRQ_EI
--	help
--	   Allow the kernel to use shadow register sets for fast interrupts.
--	   Interrupt handlers must be specially written to use shadow sets.
--	   Say N unless you know that shadow register set upport is needed.
-+	bool
- 
- config CPU_HAS_SYNC
- 	bool
-@@ -1607,6 +1662,28 @@
- 	def_bool y
- 	depends on !NUMA
- 
-+config ARCH_DISCONTIGMEM_ENABLE
-+	bool
-+	default y if SGI_IP27
-+	help
-+	  Say Y to upport efficient handling of discontiguous physical memory,
-+	  for architectures which are either NUMA (Non-Uniform Memory Access)
-+	  or have huge holes in the physical address space for other reasons.
-+	  See <file:Documentation/vm/numa> for more.
-+
-+config NUMA
-+	bool "NUMA Support"
-+	depends on SYS_SUPPORTS_NUMA
-+	help
-+	  Say Y to compile the kernel to support NUMA (Non-Uniform Memory
-+	  Access).  This option improves performance on systems with more
-+	  than two nodes; on two node systems it is generally better to
-+	  leave it disabled; on single node systems disable this option
-+	  disabled.
-+
-+config SYS_SUPPORTS_NUMA
-+	bool
-+
- config NODES_SHIFT
- 	int
- 	default "6"
-@@ -1616,8 +1693,8 @@
- 
- config SMP
- 	bool "Multi-Processing support"
--	depends on CPU_RM9000 || ((SIBYTE_BCM1x80 || SIBYTE_BCM1x55 || SIBYTE_SB1250 || QEMU) && !SIBYTE_STANDALONE) || SGI_IP27 || MIPS_MT_SMP || MIPS_MT_SMTC
--	---help---
-+	depends on SYS_SUPPORTS_SMP
-+	help
- 	  This enables support for systems with more than one CPU. If you have
- 	  a system with only one CPU, like most personal computers, say N. If
- 	  you have a system with more than one CPU, say Y.
-@@ -1636,6 +1713,9 @@
- 
- 	  If you don't know what to do here, say N.
- 
-+config SYS_SUPPORTS_SMP
-+	bool
-+
- config NR_CPUS
- 	int "Maximum number of CPUs (2-64)"
- 	range 2 64
-@@ -1710,6 +1790,9 @@
- config ISA
- 	bool
- 
-+config NO_ISA
-+	bool
-+
- config EISA
- 	bool "EISA support"
- 	depends on HW_HAS_EISA
-@@ -1840,6 +1923,32 @@
- 	bool "Power Management support (EXPERIMENTAL)"
- 	depends on EXPERIMENTAL && SOC_AU1X00
- 
-+config APM
-+        tristate "Advanced Power Management Emulation"
-+	depends on PM
-+        ---help---
-+	  APM is a BIOS specification for saving power using several different
-+	  techniques. This is mostly useful for battery powered systems with
-+	  APM compliant BIOSes. If you say Y here, the system time will be
-+	  reset after a RESUME operation, the /proc/apm device will provide
-+	  battery status information, and user-space programs will receive
-+	  notification of APM "events" (e.g. battery status change).
-+
-+	  In order to use APM, you will need supporting software. For location
-+	  and more information, read <file:Documentation/pm.txt> and the
-+	  Battery Powered Linux mini-HOWTO, available from
-+	  <http://www.tldp.org/docs.html#howto>.
-+
-+	  This driver does not spin down disk drives (see the hdparm(8)
-+	  manpage ("man 8 hdparm") for that), and it doesn't turn off
-+	  VESA-compliant "green" monitors.
-+
-+	  Generally, if you don't have a battery in your machine, there isn't
-+	  much point in using this driver and you should say N. If you get
-+	  random kernel OOPSes or reboots that don't seem to be related to
-+	  anything, try disabling/enabling this option (or disabling/enabling
-+	  APM in your BIOS).
-+
- endmenu
- 
- source "net/Kconfig"
-diff -Naur linux-2.6.17.orig/arch/mips/kernel/apm.c linux-2.6.17/arch/mips/kernel/apm.c
---- linux-2.6.17.orig/arch/mips/kernel/apm.c	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/arch/mips/kernel/apm.c	2006-06-19 18:16:13.000000000 -0700
-@@ -0,0 +1,605 @@
-+/*
-+ * bios-less APM driver for MIPS Linux
-+ *  Jamey Hicks <jamey@crl.dec.com>
-+ *  adapted from the APM BIOS driver for Linux by Stephen Rothwell (sfr@linuxcare.com)
-+ *
-+ * APM 1.2 Reference:
-+ *   Intel Corporation, Microsoft Corporation. Advanced Power Management
-+ *   (APM) BIOS Interface Specification, Revision 1.2, February 1996.
-+ *
-+ * [This document is available from Microsoft at:
-+ *    http://www.microsoft.com/hwdev/busbios/amp_12.htm]
-+ */
-+#include <linux/config.h>
-+#include <linux/module.h>
-+#include <linux/poll.h>
-+#include <linux/timer.h>
-+#include <linux/slab.h>
-+#include <linux/proc_fs.h>
-+#include <linux/miscdevice.h>
-+#include <linux/apm_bios.h>
-+#include <linux/capability.h>
-+#include <linux/sched.h>
-+#include <linux/pm.h>
-+#include <linux/device.h>
-+#include <linux/kernel.h>
-+#include <linux/list.h>
-+#include <linux/init.h>
-+#include <linux/completion.h>
-+
-+#include <asm/apm.h> /* apm_power_info */
-+#include <asm/system.h>
-+
-+/*
-+ * The apm_bios device is one of the misc char devices.
-+ * This is its minor number.
-+ */
-+#define APM_MINOR_DEV	134
-+
-+/*
-+ * See Documentation/Config.help for the configuration options.
-+ *
-+ * Various options can be changed at boot time as follows:
-+ * (We allow underscores for compatibility with the modules code)
-+ *	apm=on/off			enable/disable APM
-+ */
-+
-+/*
-+ * Maximum number of events stored
-+ */
-+#define APM_MAX_EVENTS		16
-+
-+struct apm_queue {
-+	unsigned int		event_head;
-+	unsigned int		event_tail;
-+	apm_event_t		events[APM_MAX_EVENTS];
-+};
-+
-+/*
-+ * The per-file APM data
-+ */
-+struct apm_user {
-+	struct list_head	list;
-+
-+	unsigned int		suser: 1;
-+	unsigned int		writer: 1;
-+	unsigned int		reader: 1;
-+
-+	int			suspend_result;
-+	unsigned int		suspend_state;
-+#define SUSPEND_NONE	0		/* no suspend pending */
-+#define SUSPEND_PENDING	1		/* suspend pending read */
-+#define SUSPEND_READ	2		/* suspend read, pending ack */
-+#define SUSPEND_ACKED	3		/* suspend acked */
-+#define SUSPEND_DONE	4		/* suspend completed */
-+
-+	struct apm_queue	queue;
-+};
-+
-+/*
-+ * Local variables
-+ */
-+static int suspends_pending;
-+static int apm_disabled;
-+static int mips_apm_active;
-+
-+static DECLARE_WAIT_QUEUE_HEAD(apm_waitqueue);
-+static DECLARE_WAIT_QUEUE_HEAD(apm_suspend_waitqueue);
-+
-+/*
-+ * This is a list of everyone who has opened /dev/apm_bios
-+ */
-+static DECLARE_RWSEM(user_list_lock);
-+static LIST_HEAD(apm_user_list);
-+
-+/*
-+ * kapmd info.  kapmd provides us a process context to handle
-+ * "APM" events within - specifically necessary if we're going
-+ * to be suspending the system.
-+ */
-+static DECLARE_WAIT_QUEUE_HEAD(kapmd_wait);
-+static DECLARE_COMPLETION(kapmd_exit);
-+static DEFINE_SPINLOCK(kapmd_queue_lock);
-+static struct apm_queue kapmd_queue;
-+
-+
-+static const char driver_version[] = "1.13";	/* no spaces */
-+
-+
-+
-+/*
-+ * Compatibility cruft until the IPAQ people move over to the new
-+ * interface.
-+ */
-+static void __apm_get_power_status(struct apm_power_info *info)
-+{
-+}
-+
-+/*
-+ * This allows machines to provide their own "apm get power status" function.
-+ */
-+void (*apm_get_power_status)(struct apm_power_info *) = __apm_get_power_status;
-+EXPORT_SYMBOL(apm_get_power_status);
-+
-+
-+/*
-+ * APM event queue management.
-+ */
-+static inline int queue_empty(struct apm_queue *q)
-+{
-+	return q->event_head == q->event_tail;
-+}
-+
-+static inline apm_event_t queue_get_event(struct apm_queue *q)
-+{
-+	q->event_tail = (q->event_tail + 1) % APM_MAX_EVENTS;
-+	return q->events[q->event_tail];
-+}
-+
-+static void queue_add_event(struct apm_queue *q, apm_event_t event)
-+{
-+	q->event_head = (q->event_head + 1) % APM_MAX_EVENTS;
-+	if (q->event_head == q->event_tail) {
-+		static int notified;
-+
-+		if (notified++ == 0)
-+		    printk(KERN_ERR "apm: an event queue overflowed\n");
-+		q->event_tail = (q->event_tail + 1) % APM_MAX_EVENTS;
-+	}
-+	q->events[q->event_head] = event;
-+}
-+
-+static void queue_event_one_user(struct apm_user *as, apm_event_t event)
-+{
-+	if (as->suser && as->writer) {
-+		switch (event) {
-+		case APM_SYS_SUSPEND:
-+		case APM_USER_SUSPEND:
-+			/*
-+			 * If this user already has a suspend pending,
-+			 * don't queue another one.
-+			 */
-+			if (as->suspend_state != SUSPEND_NONE)
-+				return;
-+
-+			as->suspend_state = SUSPEND_PENDING;
-+			suspends_pending++;
-+			break;
-+		}
-+	}
-+	queue_add_event(&as->queue, event);
-+}
-+
-+static void queue_event(apm_event_t event, struct apm_user *sender)
-+{
-+	struct apm_user *as;
-+
-+	down_read(&user_list_lock);
-+	list_for_each_entry(as, &apm_user_list, list) {
-+		if (as != sender && as->reader)
-+			queue_event_one_user(as, event);
-+	}
-+	up_read(&user_list_lock);
-+	wake_up_interruptible(&apm_waitqueue);
-+}
-+
-+static void apm_suspend(void)
-+{
-+	struct apm_user *as;
-+	int err = pm_suspend(PM_SUSPEND_MEM);
-+
-+	/*
-+	 * Anyone on the APM queues will think we're still suspended.
-+	 * Send a message so everyone knows we're now awake again.
-+	 */
-+	queue_event(APM_NORMAL_RESUME, NULL);
-+
-+	/*
-+	 * Finally, wake up anyone who is sleeping on the suspend.
-+	 */
-+	down_read(&user_list_lock);
-+	list_for_each_entry(as, &apm_user_list, list) {
-+		as->suspend_result = err;
-+		as->suspend_state = SUSPEND_DONE;
-+	}
-+	up_read(&user_list_lock);
-+
-+	wake_up(&apm_suspend_waitqueue);
-+}
-+
-+static ssize_t apm_read(struct file *fp, char __user *buf, size_t count, loff_t *ppos)
-+{
-+	struct apm_user *as = fp->private_data;
-+	apm_event_t event;
-+	int i = count, ret = 0;
-+
-+	if (count < sizeof(apm_event_t))
-+		return -EINVAL;
-+
-+	if (queue_empty(&as->queue) && fp->f_flags & O_NONBLOCK)
-+		return -EAGAIN;
-+
-+	wait_event_interruptible(apm_waitqueue, !queue_empty(&as->queue));
-+
-+	while ((i >= sizeof(event)) && !queue_empty(&as->queue)) {
-+		event = queue_get_event(&as->queue);
-+
-+		ret = -EFAULT;
-+		if (copy_to_user(buf, &event, sizeof(event)))
-+			break;
-+
-+		if (event == APM_SYS_SUSPEND || event == APM_USER_SUSPEND)
-+			as->suspend_state = SUSPEND_READ;
-+
-+		buf += sizeof(event);
-+		i -= sizeof(event);
-+	}
-+
-+	if (i < count)
-+		ret = count - i;
-+
-+	return ret;
-+}
-+
-+static unsigned int apm_poll(struct file *fp, poll_table * wait)
-+{
-+	struct apm_user *as = fp->private_data;
-+
-+	poll_wait(fp, &apm_waitqueue, wait);
-+	return queue_empty(&as->queue) ? 0 : POLLIN | POLLRDNORM;
-+}
-+
-+/*
-+ * apm_ioctl - handle APM ioctl
-+ *
-+ * APM_IOC_SUSPEND
-+ *   This IOCTL is overloaded, and performs two functions.  It is used to:
-+ *     - initiate a suspend
-+ *     - acknowledge a suspend read from /dev/apm_bios.
-+ *   Only when everyone who has opened /dev/apm_bios with write permission
-+ *   has acknowledge does the actual suspend happen.
-+ */
-+static int
-+apm_ioctl(struct inode * inode, struct file *filp, u_int cmd, u_long arg)
-+{
-+	struct apm_user *as = filp->private_data;
-+	unsigned long flags;
-+	int err = -EINVAL;
-+
-+	if (!as->suser || !as->writer)
-+		return -EPERM;
-+
-+	switch (cmd) {
-+	case APM_IOC_SUSPEND:
-+		as->suspend_result = -EINTR;
-+
-+		if (as->suspend_state == SUSPEND_READ) {
-+			/*
-+			 * If we read a suspend command from /dev/apm_bios,
-+			 * then the corresponding APM_IOC_SUSPEND ioctl is
-+			 * interpreted as an acknowledge.
-+			 */
-+			as->suspend_state = SUSPEND_ACKED;
-+			suspends_pending--;
-+		} else {
-+			/*
-+			 * Otherwise it is a request to suspend the system.
-+			 * Queue an event for all readers, and expect an
-+			 * acknowledge from all writers who haven't already
-+			 * acknowledged.
-+			 */
-+			queue_event(APM_USER_SUSPEND, as);
-+		}
-+
-+		/*
-+		 * If there are no further acknowledges required, suspend
-+		 * the system.
-+		 */
-+		if (suspends_pending == 0)
-+			apm_suspend();
-+
-+		/*
-+		 * Wait for the suspend/resume to complete.  If there are
-+		 * pending acknowledges, we wait here for them.
-+		 *
-+		 * Note that we need to ensure that the PM subsystem does
-+		 * not kick us out of the wait when it suspends the threads.
-+		 */
-+		flags = current->flags;
-+		current->flags |= PF_NOFREEZE;
-+
-+		/*
-+		 * Note: do not allow a thread which is acking the suspend
-+		 * to escape until the resume is complete.
-+		 */
-+		if (as->suspend_state == SUSPEND_ACKED)
-+			wait_event(apm_suspend_waitqueue,
-+					 as->suspend_state == SUSPEND_DONE);
-+		else
-+			wait_event_interruptible(apm_suspend_waitqueue,
-+					 as->suspend_state == SUSPEND_DONE);
-+
-+		current->flags = flags;
-+		err = as->suspend_result;
-+		as->suspend_state = SUSPEND_NONE;
-+		break;
-+	}
-+
-+	return err;
-+}
-+
-+static int apm_release(struct inode * inode, struct file * filp)
-+{
-+	struct apm_user *as = filp->private_data;
-+	filp->private_data = NULL;
-+
-+	down_write(&user_list_lock);
-+	list_del(&as->list);
-+	up_write(&user_list_lock);
-+
-+	/*
-+	 * We are now unhooked from the chain.  As far as new
-+	 * events are concerned, we no longer exist.  However, we
-+	 * need to balance suspends_pending, which means the
-+	 * possibility of sleeping.
-+	 */
-+	if (as->suspend_state != SUSPEND_NONE) {
-+		suspends_pending -= 1;
-+		if (suspends_pending == 0)
-+			apm_suspend();
-+	}
-+
-+	kfree(as);
-+	return 0;
-+}
-+
-+static int apm_open(struct inode * inode, struct file * filp)
-+{
-+	struct apm_user *as;
-+
-+	as = (struct apm_user *)kzalloc(sizeof(*as), GFP_KERNEL);
-+	if (as) {
-+		/*
-+		 * XXX - this is a tiny bit broken, when we consider BSD
-+		 * process accounting. If the device is opened by root, we
-+		 * instantly flag that we used superuser privs. Who knows,
-+		 * we might close the device immediately without doing a
-+		 * privileged operation -- cevans
-+		 */
-+		as->suser = capable(CAP_SYS_ADMIN);
-+		as->writer = (filp->f_mode & FMODE_WRITE) == FMODE_WRITE;
-+		as->reader = (filp->f_mode & FMODE_READ) == FMODE_READ;
-+
-+		down_write(&user_list_lock);
-+		list_add(&as->list, &apm_user_list);
-+		up_write(&user_list_lock);
-+
-+		filp->private_data = as;
-+	}
-+
-+	return as ? 0 : -ENOMEM;
-+}
-+
-+static struct file_operations apm_bios_fops = {
-+	.owner		= THIS_MODULE,
-+	.read		= apm_read,
-+	.poll		= apm_poll,
-+	.ioctl		= apm_ioctl,
-+	.open		= apm_open,
-+	.release	= apm_release,
-+};
-+
-+static struct miscdevice apm_device = {
-+	.minor		= APM_MINOR_DEV,
-+	.name		= "apm_bios",
-+	.fops		= &apm_bios_fops
-+};
-+
-+
-+#ifdef CONFIG_PROC_FS
-+/*
-+ * Arguments, with symbols from linux/apm_bios.h.
-+ *
-+ *   0) Linux driver version (this will change if format changes)
-+ *   1) APM BIOS Version.  Usually 1.0, 1.1 or 1.2.
-+ *   2) APM flags from APM Installation Check (0x00):
-+ *	bit 0: APM_16_BIT_SUPPORT
-+ *	bit 1: APM_32_BIT_SUPPORT
-+ *	bit 2: APM_IDLE_SLOWS_CLOCK
-+ *	bit 3: APM_BIOS_DISABLED
-+ *	bit 4: APM_BIOS_DISENGAGED
-+ *   3) AC line status
-+ *	0x00: Off-line
-+ *	0x01: On-line
-+ *	0x02: On backup power (BIOS >= 1.1 only)
-+ *	0xff: Unknown
-+ *   4) Battery status
-+ *	0x00: High
-+ *	0x01: Low
-+ *	0x02: Critical
-+ *	0x03: Charging
-+ *	0x04: Selected battery not present (BIOS >= 1.2 only)
-+ *	0xff: Unknown
-+ *   5) Battery flag
-+ *	bit 0: High
-+ *	bit 1: Low
-+ *	bit 2: Critical
-+ *	bit 3: Charging
-+ *	bit 7: No system battery
-+ *	0xff: Unknown
-+ *   6) Remaining battery life (percentage of charge):
-+ *	0-100: valid
-+ *	-1: Unknown
-+ *   7) Remaining battery life (time units):
-+ *	Number of remaining minutes or seconds
-+ *	-1: Unknown
-+ *   8) min = minutes; sec = seconds
-+ */
-+static int apm_get_info(char *buf, char **start, off_t fpos, int length)
-+{
-+	struct apm_power_info info;
-+	char *units;
-+	int ret;
-+
-+	info.ac_line_status = 0xff;
-+	info.battery_status = 0xff;
-+	info.battery_flag   = 0xff;
-+	info.battery_life   = -1;
-+	info.time	    = -1;
-+	info.units	    = -1;
-+
-+	if (apm_get_power_status)
-+		apm_get_power_status(&info);
-+
-+	switch (info.units) {
-+	default:	units = "?";	break;
-+	case 0: 	units = "min";	break;
-+	case 1: 	units = "sec";	break;
-+	}
-+
-+	ret = sprintf(buf, "%s 1.2 0x%02x 0x%02x 0x%02x 0x%02x %d%% %d %s\n",
-+		     driver_version, APM_32_BIT_SUPPORT,
-+		     info.ac_line_status, info.battery_status,
-+		     info.battery_flag, info.battery_life,
-+		     info.time, units);
-+
-+ 	return ret;
-+}
-+#endif
-+
-+static int kapmd(void *arg)
-+{
-+	daemonize("kapmd");
-+	current->flags |= PF_NOFREEZE;
-+
-+	do {
-+		apm_event_t event;
-+
-+		wait_event_interruptible(kapmd_wait,
-+				!queue_empty(&kapmd_queue) || !mips_apm_active);
-+
-+		if (!mips_apm_active)
-+			break;
-+
-+		spin_lock_irq(&kapmd_queue_lock);
-+		event = 0;
-+		if (!queue_empty(&kapmd_queue))
-+			event = queue_get_event(&kapmd_queue);
-+		spin_unlock_irq(&kapmd_queue_lock);
-+
-+		switch (event) {
-+		case 0:
-+			break;
-+
-+		case APM_LOW_BATTERY:
-+		case APM_POWER_STATUS_CHANGE:
-+			queue_event(event, NULL);
-+			break;
-+
-+		case APM_USER_SUSPEND:
-+		case APM_SYS_SUSPEND:
-+			queue_event(event, NULL);
-+			if (suspends_pending == 0)
-+				apm_suspend();
-+			break;
-+
-+		case APM_CRITICAL_SUSPEND:
-+			apm_suspend();
-+			break;
-+		}
-+	} while (1);
-+
-+	complete_and_exit(&kapmd_exit, 0);
-+}
-+
-+static int __init apm_init(void)
-+{
-+	int ret;
-+
-+	if (apm_disabled) {
-+		printk(KERN_NOTICE "apm: disabled on user request.\n");
-+		return -ENODEV;
-+	}
-+
-+	mips_apm_active = 1;
-+
-+	ret = kernel_thread(kapmd, NULL, CLONE_KERNEL);
-+	if (ret < 0) {
-+		mips_apm_active = 0;
-+		return ret;
-+	}
-+
-+#ifdef CONFIG_PROC_FS
-+	create_proc_info_entry("apm", 0, NULL, apm_get_info);
-+#endif
-+
-+	ret = misc_register(&apm_device);
-+	if (ret != 0) {
-+		remove_proc_entry("apm", NULL);
-+
-+		mips_apm_active = 0;
-+		wake_up(&kapmd_wait);
-+		wait_for_completion(&kapmd_exit);
-+	}
-+
-+	return ret;
-+}
-+
-+static void __exit apm_exit(void)
-+{
-+	misc_deregister(&apm_device);
-+	remove_proc_entry("apm", NULL);
-+
-+	mips_apm_active = 0;
-+	wake_up(&kapmd_wait);
-+	wait_for_completion(&kapmd_exit);
-+}
-+
-+module_init(apm_init);
-+module_exit(apm_exit);
-+
-+MODULE_AUTHOR("Stephen Rothwell");
-+MODULE_DESCRIPTION("Advanced Power Management");
-+MODULE_LICENSE("GPL");
-+
-+#ifndef MODULE
-+static int __init apm_setup(char *str)
-+{
-+	while ((str != NULL) && (*str != '\0')) {
-+		if (strncmp(str, "off", 3) == 0)
-+			apm_disabled = 1;
-+		if (strncmp(str, "on", 2) == 0)
-+			apm_disabled = 0;
-+		str = strchr(str, ',');
-+		if (str != NULL)
-+			str += strspn(str, ", \t");
-+	}
-+	return 1;
-+}
-+
-+__setup("apm=", apm_setup);
-+#endif
-+
-+/**
-+ * apm_queue_event - queue an APM event for kapmd
-+ * @event: APM event
-+ *
-+ * Queue an APM event for kapmd to process and ultimately take the
-+ * appropriate action.  Only a subset of events are handled:
-+ *   %APM_LOW_BATTERY
-+ *   %APM_POWER_STATUS_CHANGE
-+ *   %APM_USER_SUSPEND
-+ *   %APM_SYS_SUSPEND
-+ *   %APM_CRITICAL_SUSPEND
-+ */
-+void apm_queue_event(apm_event_t event)
-+{
-+	unsigned long flags;
-+
-+	spin_lock_irqsave(&kapmd_queue_lock, flags);
-+	queue_add_event(&kapmd_queue, event);
-+	spin_unlock_irqrestore(&kapmd_queue_lock, flags);
-+
-+	wake_up_interruptible(&kapmd_wait);
-+}
-+EXPORT_SYMBOL(apm_queue_event);
-diff -Naur linux-2.6.17.orig/arch/mips/kernel/asm-offsets.c linux-2.6.17/arch/mips/kernel/asm-offsets.c
---- linux-2.6.17.orig/arch/mips/kernel/asm-offsets.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/kernel/asm-offsets.c	2006-06-19 18:16:13.000000000 -0700
-@@ -141,72 +141,72 @@
- void output_thread_fpu_defines(void)
- {
- 	offset("#define THREAD_FPR0    ",
--	       struct task_struct, thread.fpu.hard.fpr[0]);
-+	       struct task_struct, thread.fpu.fpr[0]);
- 	offset("#define THREAD_FPR1    ",
--	       struct task_struct, thread.fpu.hard.fpr[1]);
-+	       struct task_struct, thread.fpu.fpr[1]);
- 	offset("#define THREAD_FPR2    ",
--	       struct task_struct, thread.fpu.hard.fpr[2]);
-+	       struct task_struct, thread.fpu.fpr[2]);
- 	offset("#define THREAD_FPR3    ",
--	       struct task_struct, thread.fpu.hard.fpr[3]);
-+	       struct task_struct, thread.fpu.fpr[3]);
- 	offset("#define THREAD_FPR4    ",
--	       struct task_struct, thread.fpu.hard.fpr[4]);
-+	       struct task_struct, thread.fpu.fpr[4]);
- 	offset("#define THREAD_FPR5    ",
--	       struct task_struct, thread.fpu.hard.fpr[5]);
-+	       struct task_struct, thread.fpu.fpr[5]);
- 	offset("#define THREAD_FPR6    ",
--	       struct task_struct, thread.fpu.hard.fpr[6]);
-+	       struct task_struct, thread.fpu.fpr[6]);
- 	offset("#define THREAD_FPR7    ",
--	       struct task_struct, thread.fpu.hard.fpr[7]);
-+	       struct task_struct, thread.fpu.fpr[7]);
- 	offset("#define THREAD_FPR8    ",
--	       struct task_struct, thread.fpu.hard.fpr[8]);
-+	       struct task_struct, thread.fpu.fpr[8]);
- 	offset("#define THREAD_FPR9    ",
--	       struct task_struct, thread.fpu.hard.fpr[9]);
-+	       struct task_struct, thread.fpu.fpr[9]);
- 	offset("#define THREAD_FPR10   ",
--	       struct task_struct, thread.fpu.hard.fpr[10]);
-+	       struct task_struct, thread.fpu.fpr[10]);
- 	offset("#define THREAD_FPR11   ",
--	       struct task_struct, thread.fpu.hard.fpr[11]);
-+	       struct task_struct, thread.fpu.fpr[11]);
- 	offset("#define THREAD_FPR12   ",
--	       struct task_struct, thread.fpu.hard.fpr[12]);
-+	       struct task_struct, thread.fpu.fpr[12]);
- 	offset("#define THREAD_FPR13   ",
--	       struct task_struct, thread.fpu.hard.fpr[13]);
-+	       struct task_struct, thread.fpu.fpr[13]);
- 	offset("#define THREAD_FPR14   ",
--	       struct task_struct, thread.fpu.hard.fpr[14]);
-+	       struct task_struct, thread.fpu.fpr[14]);
- 	offset("#define THREAD_FPR15   ",
--	       struct task_struct, thread.fpu.hard.fpr[15]);
-+	       struct task_struct, thread.fpu.fpr[15]);
- 	offset("#define THREAD_FPR16   ",
--	       struct task_struct, thread.fpu.hard.fpr[16]);
-+	       struct task_struct, thread.fpu.fpr[16]);
- 	offset("#define THREAD_FPR17   ",
--	       struct task_struct, thread.fpu.hard.fpr[17]);
-+	       struct task_struct, thread.fpu.fpr[17]);
- 	offset("#define THREAD_FPR18   ",
--	       struct task_struct, thread.fpu.hard.fpr[18]);
-+	       struct task_struct, thread.fpu.fpr[18]);
- 	offset("#define THREAD_FPR19   ",
--	       struct task_struct, thread.fpu.hard.fpr[19]);
-+	       struct task_struct, thread.fpu.fpr[19]);
- 	offset("#define THREAD_FPR20   ",
--	       struct task_struct, thread.fpu.hard.fpr[20]);
-+	       struct task_struct, thread.fpu.fpr[20]);
- 	offset("#define THREAD_FPR21   ",
--	       struct task_struct, thread.fpu.hard.fpr[21]);
-+	       struct task_struct, thread.fpu.fpr[21]);
- 	offset("#define THREAD_FPR22   ",
--	       struct task_struct, thread.fpu.hard.fpr[22]);
-+	       struct task_struct, thread.fpu.fpr[22]);
- 	offset("#define THREAD_FPR23   ",
--	       struct task_struct, thread.fpu.hard.fpr[23]);
-+	       struct task_struct, thread.fpu.fpr[23]);
- 	offset("#define THREAD_FPR24   ",
--	       struct task_struct, thread.fpu.hard.fpr[24]);
-+	       struct task_struct, thread.fpu.fpr[24]);
- 	offset("#define THREAD_FPR25   ",
--	       struct task_struct, thread.fpu.hard.fpr[25]);
-+	       struct task_struct, thread.fpu.fpr[25]);
- 	offset("#define THREAD_FPR26   ",
--	       struct task_struct, thread.fpu.hard.fpr[26]);
-+	       struct task_struct, thread.fpu.fpr[26]);
- 	offset("#define THREAD_FPR27   ",
--	       struct task_struct, thread.fpu.hard.fpr[27]);
-+	       struct task_struct, thread.fpu.fpr[27]);
- 	offset("#define THREAD_FPR28   ",
--	       struct task_struct, thread.fpu.hard.fpr[28]);
-+	       struct task_struct, thread.fpu.fpr[28]);
- 	offset("#define THREAD_FPR29   ",
--	       struct task_struct, thread.fpu.hard.fpr[29]);
-+	       struct task_struct, thread.fpu.fpr[29]);
- 	offset("#define THREAD_FPR30   ",
--	       struct task_struct, thread.fpu.hard.fpr[30]);
-+	       struct task_struct, thread.fpu.fpr[30]);
- 	offset("#define THREAD_FPR31   ",
--	       struct task_struct, thread.fpu.hard.fpr[31]);
-+	       struct task_struct, thread.fpu.fpr[31]);
- 
- 	offset("#define THREAD_FCR31   ",
--	       struct task_struct, thread.fpu.hard.fcr31);
-+	       struct task_struct, thread.fpu.fcr31);
- 	linefeed;
- }
- 
-diff -Naur linux-2.6.17.orig/arch/mips/kernel/branch.c linux-2.6.17/arch/mips/kernel/branch.c
---- linux-2.6.17.orig/arch/mips/kernel/branch.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/kernel/branch.c	2006-06-19 18:16:13.000000000 -0700
-@@ -178,7 +178,7 @@
- 		if (is_fpu_owner())
- 			asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
- 		else
--			fcr31 = current->thread.fpu.hard.fcr31;
-+			fcr31 = current->thread.fpu.fcr31;
- 		preempt_enable();
- 
- 		bit = (insn.i_format.rt >> 2);
-diff -Naur linux-2.6.17.orig/arch/mips/kernel/cpu-probe.c linux-2.6.17/arch/mips/kernel/cpu-probe.c
---- linux-2.6.17.orig/arch/mips/kernel/cpu-probe.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/kernel/cpu-probe.c	2006-06-19 18:16:13.000000000 -0700
-@@ -111,7 +111,6 @@
- 	case CPU_R5000:
- 	case CPU_NEVADA:
- 	case CPU_RM7000:
--	case CPU_RM9000:
- 	case CPU_TX49XX:
- 	case CPU_4KC:
- 	case CPU_4KEC:
-@@ -137,6 +136,14 @@
- 		} else
- 			printk(" unavailable.\n");
- 		break;
-+	case CPU_RM9000:
-+		if ((c->processor_id & 0x00ff) >= 0x40) {
-+			cpu_wait = r4k_wait;
-+			printk(" available.\n");
-+		} else {
-+			printk(" unavailable.\n");
-+		}
-+		break;
- 	default:
- 		printk(" unavailable.\n");
- 		break;
-@@ -243,9 +250,15 @@
- 		break;
- 	case PRID_IMP_VR41XX:
- 		switch (c->processor_id & 0xf0) {
-+#ifndef CONFIG_VR4181
- 		case PRID_REV_VR4111:
- 			c->cputype = CPU_VR4111;
- 			break;
-+#else
-+		case PRID_REV_VR4181:
-+			c->cputype = CPU_VR4181;
-+			break;
-+#endif
- 		case PRID_REV_VR4121:
- 			c->cputype = CPU_VR4121;
- 			break;
-diff -Naur linux-2.6.17.orig/arch/mips/kernel/entry.S linux-2.6.17/arch/mips/kernel/entry.S
---- linux-2.6.17.orig/arch/mips/kernel/entry.S	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/kernel/entry.S	2006-06-19 18:16:13.000000000 -0700
-@@ -87,7 +87,7 @@
- 	ori	v1, v0, TCSTATUS_IXMT
- 	mtc0	v1, CP0_TCSTATUS
- 	andi	v0, TCSTATUS_IXMT
--	ehb
-+	_ehb
- 	mfc0	t0, CP0_TCCONTEXT
- 	DMT	9				# dmt t1
- 	jal	mips_ihb
-@@ -95,7 +95,7 @@
- 	andi	t3, t0, 0xff00
- 	or	t2, t2, t3
- 	mtc0	t2, CP0_STATUS
--	ehb
-+	_ehb
- 	andi	t1, t1, VPECONTROL_TE
- 	beqz	t1, 1f
- 	EMT
-@@ -105,7 +105,7 @@
- 	xori	v1, v1, TCSTATUS_IXMT
- 	or	v1, v0, v1
- 	mtc0	v1, CP0_TCSTATUS
--	ehb
-+	_ehb
- 	xor	t0, t0, t3
- 	mtc0	t0, CP0_TCCONTEXT
- #endif /* CONFIG_MIPS_MT_SMTC */
-diff -Naur linux-2.6.17.orig/arch/mips/kernel/gdb-low.S linux-2.6.17/arch/mips/kernel/gdb-low.S
---- linux-2.6.17.orig/arch/mips/kernel/gdb-low.S	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/kernel/gdb-low.S	2006-06-19 18:16:13.000000000 -0700
-@@ -291,7 +291,7 @@
- 		ori	t1, t2, TCSTATUS_IXMT
- 		mtc0	t1, CP0_TCSTATUS
- 		andi	t2, t2, TCSTATUS_IXMT
--		ehb
-+		_ehb
- 		DMT	9				# dmt	t1
- 		jal	mips_ihb
- 		nop
-@@ -310,7 +310,7 @@
- 		xori	t1, t1, TCSTATUS_IXMT
- 		or	t1, t1, t2
- 		mtc0	t1, CP0_TCSTATUS
--		ehb
-+		_ehb
- #endif /* CONFIG_MIPS_MT_SMTC */
- 		LONG_L	v0, GDB_FR_STATUS(sp)
- 		LONG_L	v1, GDB_FR_EPC(sp)
-diff -Naur linux-2.6.17.orig/arch/mips/kernel/genex.S linux-2.6.17/arch/mips/kernel/genex.S
---- linux-2.6.17.orig/arch/mips/kernel/genex.S	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/kernel/genex.S	2006-06-19 18:16:13.000000000 -0700
-@@ -214,7 +214,7 @@
- 	mtc0	t0, CP0_TCCONTEXT
- 	xor	t1, t1, t0
- 	mtc0	t1, CP0_STATUS
--	ehb
-+	_ehb
- #endif /* CONFIG_MIPS_MT_SMTC */
- 	CLI
- 	move	a0, sp
-diff -Naur linux-2.6.17.orig/arch/mips/kernel/head.S linux-2.6.17/arch/mips/kernel/head.S
---- linux-2.6.17.orig/arch/mips/kernel/head.S	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/kernel/head.S	2006-06-19 18:16:13.000000000 -0700
-@@ -96,7 +96,7 @@
- 	/* Clear TKSU, leave IXMT */
- 	xori	t0, 0x00001800
- 	mtc0	t0, CP0_TCSTATUS
--	ehb
-+	_ehb
- 	/* We need to leave the global IE bit set, but clear EXL...*/
- 	mfc0	t0, CP0_STATUS
- 	or	t0, ST0_CU0 | ST0_EXL | ST0_ERL | \set | \clr
-diff -Naur linux-2.6.17.orig/arch/mips/kernel/i8259.c linux-2.6.17/arch/mips/kernel/i8259.c
---- linux-2.6.17.orig/arch/mips/kernel/i8259.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/kernel/i8259.c	2006-06-19 18:16:13.000000000 -0700
-@@ -302,11 +302,11 @@
- };
- 
- static struct resource pic1_io_resource = {
--	"pic1", 0x20, 0x3f, IORESOURCE_BUSY
-+	.name = "pic1", .start = 0x20, .end = 0x3f, .flags = IORESOURCE_BUSY
- };
- 
- static struct resource pic2_io_resource = {
--	"pic2", 0xa0, 0xbf, IORESOURCE_BUSY
-+	.name = "pic2", .start = 0xa0, .end = 0xbf, .flags = IORESOURCE_BUSY
- };
- 
- /*
-diff -Naur linux-2.6.17.orig/arch/mips/kernel/irixsig.c linux-2.6.17/arch/mips/kernel/irixsig.c
---- linux-2.6.17.orig/arch/mips/kernel/irixsig.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/kernel/irixsig.c	2006-06-19 18:16:13.000000000 -0700
-@@ -260,7 +260,7 @@
- 
- 		for(i = 0; i < 32; i++)
- 			error |= __get_user(fregs[i], &context->fpregs[i]);
--		error |= __get_user(current->thread.fpu.hard.fcr31, &context->fpcsr);
-+		error |= __get_user(current->thread.fpu.fcr31, &context->fpcsr);
- 	}
- 
- 	/* XXX do sigstack crapola here... XXX */
-diff -Naur linux-2.6.17.orig/arch/mips/kernel/Makefile linux-2.6.17/arch/mips/kernel/Makefile
---- linux-2.6.17.orig/arch/mips/kernel/Makefile	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/kernel/Makefile	2006-06-19 18:16:13.000000000 -0700
-@@ -13,6 +13,8 @@
- 
- obj-$(CONFIG_MODULES)		+= mips_ksyms.o module.o
- 
-+obj-$(CONFIG_APM)		+= apm.o
-+
- obj-$(CONFIG_CPU_R3000)		+= r2300_fpu.o r2300_switch.o
- obj-$(CONFIG_CPU_TX39XX)	+= r2300_fpu.o r2300_switch.o
- obj-$(CONFIG_CPU_TX49XX)	+= r4k_fpu.o r4k_switch.o
-diff -Naur linux-2.6.17.orig/arch/mips/kernel/ptrace32.c linux-2.6.17/arch/mips/kernel/ptrace32.c
---- linux-2.6.17.orig/arch/mips/kernel/ptrace32.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/kernel/ptrace32.c	2006-06-19 18:16:13.000000000 -0700
-@@ -166,10 +166,7 @@
- 			tmp = regs->lo;
- 			break;
- 		case FPC_CSR:
--			if (cpu_has_fpu)
--				tmp = child->thread.fpu.hard.fcr31;
--			else
--				tmp = child->thread.fpu.soft.fcr31;
-+			tmp = child->thread.fpu.fcr31;
- 			break;
- 		case FPC_EIR: {	/* implementation / version register */
- 			unsigned int flags;
-@@ -288,9 +285,9 @@
- 
- 			if (!tsk_used_math(child)) {
- 				/* FP not yet used  */
--				memset(&child->thread.fpu.hard, ~0,
--				       sizeof(child->thread.fpu.hard));
--				child->thread.fpu.hard.fcr31 = 0;
-+				memset(&child->thread.fpu, ~0,
-+				       sizeof(child->thread.fpu));
-+				child->thread.fpu.fcr31 = 0;
- 			}
- 			/*
- 			 * The odd registers are actually the high order bits
-@@ -318,10 +315,7 @@
- 			regs->lo = data;
- 			break;
- 		case FPC_CSR:
--			if (cpu_has_fpu)
--				child->thread.fpu.hard.fcr31 = data;
--			else
--				child->thread.fpu.soft.fcr31 = data;
-+			child->thread.fpu.fcr31 = data;
- 			break;
- 		case DSP_BASE ... DSP_BASE + 5: {
- 			dspreg_t *dregs;
-diff -Naur linux-2.6.17.orig/arch/mips/kernel/ptrace.c linux-2.6.17/arch/mips/kernel/ptrace.c
---- linux-2.6.17.orig/arch/mips/kernel/ptrace.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/kernel/ptrace.c	2006-06-19 18:16:13.000000000 -0700
-@@ -21,12 +21,12 @@
- #include <linux/mm.h>
- #include <linux/errno.h>
- #include <linux/ptrace.h>
--#include <linux/audit.h>
- #include <linux/smp.h>
- #include <linux/smp_lock.h>
- #include <linux/user.h>
- #include <linux/security.h>
--#include <linux/signal.h>
-+#include <linux/audit.h>
-+#include <linux/seccomp.h>
- 
- #include <asm/byteorder.h>
- #include <asm/cpu.h>
-@@ -120,11 +120,11 @@
- 			__put_user ((__u64) -1, i + (__u64 __user *) data);
- 	}
- 
-+	__put_user (child->thread.fpu.fcr31, data + 64);
-+
- 	if (cpu_has_fpu) {
- 		unsigned int flags, tmp;
- 
--		__put_user (child->thread.fpu.hard.fcr31, data + 64);
--
- 		preempt_disable();
- 		if (cpu_has_mipsmt) {
- 			unsigned int vpflags = dvpe();
-@@ -142,7 +142,6 @@
- 		preempt_enable();
- 		__put_user (tmp, data + 65);
- 	} else {
--		__put_user (child->thread.fpu.soft.fcr31, data + 64);
- 		__put_user ((__u32) 0, data + 65);
- 	}
- 
-@@ -162,10 +161,7 @@
- 	for (i = 0; i < 32; i++)
- 		__get_user (fregs[i], i + (__u64 __user *) data);
- 
--	if (cpu_has_fpu)
--		__get_user (child->thread.fpu.hard.fcr31, data + 64);
--	else
--		__get_user (child->thread.fpu.soft.fcr31, data + 64);
-+	__get_user (child->thread.fpu.fcr31, data + 64);
- 
- 	/* FIR may not be written.  */
- 
-@@ -241,10 +237,7 @@
- 			tmp = regs->lo;
- 			break;
- 		case FPC_CSR:
--			if (cpu_has_fpu)
--				tmp = child->thread.fpu.hard.fcr31;
--			else
--				tmp = child->thread.fpu.soft.fcr31;
-+			tmp = child->thread.fpu.fcr31;
- 			break;
- 		case FPC_EIR: {	/* implementation / version register */
- 			unsigned int flags;
-@@ -336,9 +329,9 @@
- 
- 			if (!tsk_used_math(child)) {
- 				/* FP not yet used  */
--				memset(&child->thread.fpu.hard, ~0,
--				       sizeof(child->thread.fpu.hard));
--				child->thread.fpu.hard.fcr31 = 0;
-+				memset(&child->thread.fpu, ~0,
-+				       sizeof(child->thread.fpu));
-+				child->thread.fpu.fcr31 = 0;
- 			}
- #ifdef CONFIG_32BIT
- 			/*
-@@ -369,10 +362,7 @@
- 			regs->lo = data;
- 			break;
- 		case FPC_CSR:
--			if (cpu_has_fpu)
--				child->thread.fpu.hard.fcr31 = data;
--			else
--				child->thread.fpu.soft.fcr31 = data;
-+			child->thread.fpu.fcr31 = data;
- 			break;
- 		case DSP_BASE ... DSP_BASE + 5: {
- 			dspreg_t *dregs;
-@@ -482,12 +472,16 @@
-  */
- asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit)
- {
-+	/* do the secure computing check first */
-+	secure_computing(regs->orig_eax);
-+
- 	if (unlikely(current->audit_context) && entryexit)
- 		audit_syscall_exit(AUDITSC_RESULT(regs->regs[2]),
- 		                   regs->regs[2]);
- 
- 	if (!(current->ptrace & PT_PTRACED))
- 		goto out;
-+
- 	if (!test_thread_flag(TIF_SYSCALL_TRACE))
- 		goto out;
- 
-@@ -505,9 +499,14 @@
- 		send_sig(current->exit_code, current, 1);
- 		current->exit_code = 0;
- 	}
-- out:
-+
-+out:
-+	/* There is no ->orig_eax and that's quite intensional for now making
-+	   this work will require some work in various other place before it's
-+	   more than a placebo.  */
-+
- 	if (unlikely(current->audit_context) && !entryexit)
--		audit_syscall_entry(audit_arch(), regs->regs[2],
--				    regs->regs[4], regs->regs[5],
--				    regs->regs[6], regs->regs[7]);
-+		audit_syscall_entry(audit_arch(), regs->orig_eax,
-+		                    regs->regs[4], regs->regs[5],
-+		                    regs->regs[6], regs->regs[7]);
- }
-diff -Naur linux-2.6.17.orig/arch/mips/kernel/r4k_switch.S linux-2.6.17/arch/mips/kernel/r4k_switch.S
---- linux-2.6.17.orig/arch/mips/kernel/r4k_switch.S	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/kernel/r4k_switch.S	2006-06-19 18:16:13.000000000 -0700
-@@ -75,8 +75,8 @@
- 	and	t0, t0, t1
- 	LONG_S	t0, ST_OFF(t3)
- 
--	fpu_save_double a0 t1 t0 t2		# c0_status passed in t1
--						# clobbers t0 and t2
-+	fpu_save_double a0 t0 t1		# c0_status passed in t0
-+						# clobbers t1
- 1:
- 
- 	/*
-@@ -94,7 +94,7 @@
- 	ori	t1, t2, TCSTATUS_IXMT
- 	mtc0	t1, CP0_TCSTATUS
- 	andi	t2, t2, TCSTATUS_IXMT
--	ehb
-+	_ehb
- 	DMT	8				# dmt	t0
- 	move	t1,ra
- 	jal	mips_ihb
-@@ -109,7 +109,7 @@
- 	or	a2, t1
- 	mtc0	a2, CP0_STATUS
- #ifdef CONFIG_MIPS_MT_SMTC
--	ehb
-+	_ehb
- 	andi	t0, t0, VPECONTROL_TE
- 	beqz	t0, 1f
- 	emt
-@@ -118,7 +118,7 @@
- 	xori	t1, t1, TCSTATUS_IXMT
- 	or	t1, t1, t2
- 	mtc0	t1, CP0_TCSTATUS
--	ehb
-+	_ehb
- #endif /* CONFIG_MIPS_MT_SMTC */
- 	move	v0, a0
- 	jr	ra
-@@ -129,9 +129,9 @@
-  */
- LEAF(_save_fp)
- #ifdef CONFIG_64BIT
--	mfc0	t1, CP0_STATUS
-+	mfc0	t0, CP0_STATUS
- #endif
--	fpu_save_double a0 t1 t0 t2		# clobbers t1
-+	fpu_save_double a0 t0 t1		# clobbers t1
- 	jr	ra
- 	END(_save_fp)
- 
-@@ -139,7 +139,10 @@
-  * Restore a thread's fp context.
-  */
- LEAF(_restore_fp)
--	fpu_restore_double a0, t1		# clobbers t1
-+#ifdef CONFIG_64BIT
-+	mfc0	t0, CP0_STATUS
-+#endif
-+	fpu_restore_double a0 t0 t1		# clobbers t1
- 	jr	ra
- 	END(_restore_fp)
- 
-diff -Naur linux-2.6.17.orig/arch/mips/kernel/scall32-o32.S linux-2.6.17/arch/mips/kernel/scall32-o32.S
---- linux-2.6.17.orig/arch/mips/kernel/scall32-o32.S	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/kernel/scall32-o32.S	2006-06-19 18:16:13.000000000 -0700
-@@ -497,7 +497,7 @@
- 	sys	sys_sched_get_priority_min 1
- 	sys	sys_sched_rr_get_interval 2	/* 4165 */
- 	sys	sys_nanosleep,		2
--	sys	sys_mremap,		4
-+	sys	sys_mremap,		5
- 	sys	sys_accept		3
- 	sys	sys_bind		3
- 	sys	sys_connect		3	/* 4170 */
-@@ -647,6 +647,7 @@
- 	sys	sys_unshare		1
- 	sys	sys_splice		4
- 	sys	sys_sync_file_range	7	/* 4305 */
-+	sys	sys_tee			4
- 	.endm
- 
- 	/* We pre-compute the number of _instruction_ bytes needed to
-diff -Naur linux-2.6.17.orig/arch/mips/kernel/scall64-64.S linux-2.6.17/arch/mips/kernel/scall64-64.S
---- linux-2.6.17.orig/arch/mips/kernel/scall64-64.S	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/kernel/scall64-64.S	2006-06-19 18:16:13.000000000 -0700
-@@ -462,3 +462,4 @@
- 	PTR	sys_unshare
- 	PTR	sys_splice
- 	PTR	sys_sync_file_range
-+	PTR	sys_tee				/* 5265 */
-diff -Naur linux-2.6.17.orig/arch/mips/kernel/scall64-n32.S linux-2.6.17/arch/mips/kernel/scall64-n32.S
---- linux-2.6.17.orig/arch/mips/kernel/scall64-n32.S	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/kernel/scall64-n32.S	2006-06-19 18:16:13.000000000 -0700
-@@ -388,3 +388,4 @@
- 	PTR	sys_unshare
- 	PTR	sys_splice
- 	PTR	sys_sync_file_range
-+	PTR	sys_tee
-diff -Naur linux-2.6.17.orig/arch/mips/kernel/scall64-o32.S linux-2.6.17/arch/mips/kernel/scall64-o32.S
---- linux-2.6.17.orig/arch/mips/kernel/scall64-o32.S	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/kernel/scall64-o32.S	2006-06-19 18:16:13.000000000 -0700
-@@ -510,4 +510,5 @@
- 	PTR	sys_unshare
- 	PTR	sys_splice
- 	PTR	sys32_sync_file_range		/* 4305 */
-+	PTR	sys_tee
- 	.size	sys_call_table,.-sys_call_table
-diff -Naur linux-2.6.17.orig/arch/mips/kernel/setup.c linux-2.6.17/arch/mips/kernel/setup.c
---- linux-2.6.17.orig/arch/mips/kernel/setup.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/kernel/setup.c	2006-06-19 18:16:13.000000000 -0700
-@@ -442,6 +442,48 @@
- #endif /* CONFIG_BLK_DEV_INITRD  */
- }
- 
-+/*
-+ * arch_mem_init - initialize memory managment subsystem
-+ *
-+ *  o plat_mem_setup() detects the memory configuration and will record detected
-+ *    memory areas using add_memory_region.
-+ *  o parse_cmdline_early() parses the command line for mem= options which,
-+ *    iff detected, will override the results of the automatic detection.
-+ *
-+ * At this stage the memory configuration of the system is known to the
-+ * kernel but generic memory managment system is still entirely uninitialized.
-+ *
-+ *  o bootmem_init()
-+ *  o sparse_init()
-+ *  o paging_init()
-+ *
-+ * At this stage the bootmem allocator is ready to use.
-+ *
-+ * NOTE: historically plat_mem_setup did the entire platform initialization.
-+ *       This was rather impractical because it meant plat_mem_setup had to
-+ * get away without any kind of memory allocator.  To keep old code from
-+ * breaking plat_setup was just renamed to plat_setup and a second platform
-+ * initialization hook for anything else was introduced.
-+ */
-+
-+extern void plat_mem_setup(void);
-+
-+static void __init arch_mem_init(char **cmdline_p)
-+{
-+	/* call board setup routine */
-+	plat_mem_setup();
-+
-+	strlcpy(command_line, arcs_cmdline, sizeof(command_line));
-+	strlcpy(saved_command_line, command_line, COMMAND_LINE_SIZE);
-+
-+	*cmdline_p = command_line;
-+
-+	parse_cmdline_early();
-+	bootmem_init();
-+	sparse_init();
-+	paging_init();
-+}
-+
- static inline void resource_init(void)
- {
- 	int i;
-@@ -495,8 +537,6 @@
- #undef MAXMEM
- #undef MAXMEM_PFN
- 
--extern void plat_setup(void);
--
- void __init setup_arch(char **cmdline_p)
- {
- 	cpu_probe();
-@@ -511,18 +551,8 @@
- #endif
- #endif
- 
--	/* call board setup routine */
--	plat_setup();
--
--	strlcpy(command_line, arcs_cmdline, sizeof(command_line));
--	strlcpy(saved_command_line, command_line, COMMAND_LINE_SIZE);
-+	arch_mem_init(cmdline_p);
- 
--	*cmdline_p = command_line;
--
--	parse_cmdline_early();
--	bootmem_init();
--	sparse_init();
--	paging_init();
- 	resource_init();
- #ifdef CONFIG_SMP
- 	plat_smp_setup();
-diff -Naur linux-2.6.17.orig/arch/mips/kernel/smtc-asm.S linux-2.6.17/arch/mips/kernel/smtc-asm.S
---- linux-2.6.17.orig/arch/mips/kernel/smtc-asm.S	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/kernel/smtc-asm.S	2006-06-19 18:16:13.000000000 -0700
-@@ -52,12 +52,12 @@
- 	.set	noat
- 	/* Disable thread scheduling to make Status update atomic */
- 	DMT	27					# dmt	k1
--	ehb
-+	_ehb
- 	/* Set EXL */
- 	mfc0	k0,CP0_STATUS
- 	ori	k0,k0,ST0_EXL
- 	mtc0	k0,CP0_STATUS
--	ehb
-+	_ehb
- 	/* Thread scheduling now inhibited by EXL. Restore TE state. */
- 	andi	k1,k1,VPECONTROL_TE
- 	beqz	k1,1f
-@@ -82,7 +82,7 @@
- 	li	k1,ST0_CU0
- 	or	k1,k1,k0
- 	mtc0	k1,CP0_STATUS
--	ehb
-+	_ehb
- 	get_saved_sp
- 	/* Interrupting TC will have pre-set values in slots in the new frame */
- 2:	subu	k1,k1,PT_SIZE
-@@ -90,7 +90,7 @@
- 	lw	k0,PT_TCSTATUS(k1)
- 	/* Write it to TCStatus to restore CU/KSU/IXMT state */
- 	mtc0	k0,$2,1
--	ehb
-+	_ehb
- 	lw	k0,PT_EPC(k1)
- 	mtc0	k0,CP0_EPC
- 	/* Save all will redundantly recompute the SP, but use it for now */
-@@ -116,7 +116,7 @@
- 	mfc0	t0,CP0_TCSTATUS
- 	ori	t1,t0,TCSTATUS_IXMT
- 	mtc0	t1,CP0_TCSTATUS
--	ehb
-+	_ehb
- 	/* We know we're in kernel mode, so prepare stack frame */
- 	subu	t1,sp,PT_SIZE
- 	sw	ra,PT_EPC(t1)
-diff -Naur linux-2.6.17.orig/arch/mips/kernel/traps.c linux-2.6.17/arch/mips/kernel/traps.c
---- linux-2.6.17.orig/arch/mips/kernel/traps.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/kernel/traps.c	2006-06-19 18:16:13.000000000 -0700
-@@ -65,7 +65,7 @@
- extern asmlinkage void handle_reserved(void);
- 
- extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
--	struct mips_fpu_soft_struct *ctx);
-+	struct mips_fpu_struct *ctx);
- 
- void (*board_be_init)(void);
- int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
-@@ -600,8 +600,7 @@
- 		preempt_enable();
- 
- 		/* Run the emulator */
--		sig = fpu_emulator_cop1Handler (regs,
--			&current->thread.fpu.soft);
-+		sig = fpu_emulator_cop1Handler (regs, &current->thread.fpu);
- 
- 		preempt_disable();
- 
-@@ -610,7 +609,7 @@
- 		 * We can't allow the emulated instruction to leave any of
- 		 * the cause bit set in $fcr31.
- 		 */
--		current->thread.fpu.soft.fcr31 &= ~FPU_CSR_ALL_X;
-+		current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
- 
- 		/* Restore the hardware register state */
- 		restore_fp(current);
-@@ -755,7 +754,7 @@
- 
- 		if (!cpu_has_fpu) {
- 			int sig = fpu_emulator_cop1Handler(regs,
--						&current->thread.fpu.soft);
-+						&current->thread.fpu);
- 			if (sig)
- 				force_sig(sig, current);
- #ifdef CONFIG_MIPS_MT_FPAFF
-@@ -1051,7 +1050,7 @@
- 	return (void *)old_handler;
- }
- 
--#ifdef CONFIG_CPU_MIPSR2
-+#ifdef CONFIG_CPU_MIPSR2_SRS
- /*
-  * MIPSR2 shadow register set allocation
-  * FIXME: SMP...
-@@ -1070,11 +1069,9 @@
- 
- static void mips_srs_init(void)
- {
--#ifdef CONFIG_CPU_MIPSR2_SRS
- 	shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
- 	printk(KERN_INFO "%d MIPSR2 register sets available\n",
- 	       shadow_registers.sr_supported);
--#endif
- 	shadow_registers.sr_allocated = 1;	/* Set 0 used by kernel */
- }
- 
-@@ -1199,7 +1196,14 @@
- {
- 	return set_vi_srs_handler(n, addr, 0);
- }
--#endif
-+
-+#else
-+
-+static inline void mips_srs_init(void)
-+{
-+}
-+
-+#endif /* CONFIG_CPU_MIPSR2_SRS */
- 
- /*
-  * This is used by native signal handling
-@@ -1389,9 +1393,7 @@
- 	else
- 		ebase = CAC_BASE;
- 
--#ifdef CONFIG_CPU_MIPSR2
- 	mips_srs_init();
--#endif
- 
- 	per_cpu_trap_init();
- 
-diff -Naur linux-2.6.17.orig/arch/mips/lasat/setup.c linux-2.6.17/arch/mips/lasat/setup.c
---- linux-2.6.17.orig/arch/mips/lasat/setup.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/lasat/setup.c	2006-06-19 18:16:13.000000000 -0700
-@@ -155,7 +155,7 @@
- }
- #endif
- 
--void __init plat_setup(void)
-+void __init plat_mem_setup(void)
- {
- 	int i;
- 	lasat_misc  = &lasat_misc_info[mips_machtype];
-diff -Naur linux-2.6.17.orig/arch/mips/lib/ashldi3.c linux-2.6.17/arch/mips/lib/ashldi3.c
---- linux-2.6.17.orig/arch/mips/lib/ashldi3.c	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/arch/mips/lib/ashldi3.c	2006-06-19 18:16:13.000000000 -0700
-@@ -0,0 +1,29 @@
-+#include <linux/module.h>
-+
-+#include "libgcc.h"
-+
-+long long __ashldi3(long long u, word_type b)
-+{
-+	DWunion uu, w;
-+	word_type bm;
-+
-+	if (b == 0)
-+		return u;
-+
-+	uu.ll = u;
-+	bm = 32 - b;
-+
-+	if (bm <= 0) {
-+		w.s.low = 0;
-+		w.s.high = (unsigned int) uu.s.low << -bm;
-+	} else {
-+		const unsigned int carries = (unsigned int) uu.s.low >> bm;
-+
-+		w.s.low = (unsigned int) uu.s.low << b;
-+		w.s.high = ((unsigned int) uu.s.high << b) | carries;
-+	}
-+
-+	return w.ll;
-+}
-+
-+EXPORT_SYMBOL(__ashldi3);
-diff -Naur linux-2.6.17.orig/arch/mips/lib/ashrdi3.c linux-2.6.17/arch/mips/lib/ashrdi3.c
---- linux-2.6.17.orig/arch/mips/lib/ashrdi3.c	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/arch/mips/lib/ashrdi3.c	2006-06-19 18:16:13.000000000 -0700
-@@ -0,0 +1,31 @@
-+#include <linux/module.h>
-+
-+#include "libgcc.h"
-+
-+long long __ashrdi3(long long u, word_type b)
-+{
-+	DWunion uu, w;
-+	word_type bm;
-+
-+	if (b == 0)
-+		return u;
-+
-+	uu.ll = u;
-+	bm = 32 - b;
-+
-+	if (bm <= 0) {
-+		/* w.s.high = 1..1 or 0..0 */
-+		w.s.high =
-+		    uu.s.high >> 31;
-+		w.s.low = uu.s.high >> -bm;
-+	} else {
-+		const unsigned int carries = (unsigned int) uu.s.high << bm;
-+
-+		w.s.high = uu.s.high >> b;
-+		w.s.low = ((unsigned int) uu.s.low >> b) | carries;
-+	}
-+
-+	return w.ll;
-+}
-+
-+EXPORT_SYMBOL(__ashrdi3);
-diff -Naur linux-2.6.17.orig/arch/mips/lib/libgcc.h linux-2.6.17/arch/mips/lib/libgcc.h
---- linux-2.6.17.orig/arch/mips/lib/libgcc.h	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/arch/mips/lib/libgcc.h	2006-06-19 18:16:13.000000000 -0700
-@@ -0,0 +1,26 @@
-+#ifndef __ASM_LIBGCC_H
-+#define __ASM_LIBGCC_H
-+
-+#include <asm/byteorder.h>
-+
-+typedef int word_type __attribute__ ((mode (__word__)));
-+
-+#ifdef __BIG_ENDIAN
-+struct DWstruct {
-+	int high, low;
-+};
-+#elif defined(__LITTLE_ENDIAN)
-+struct DWstruct {
-+	int low, high;
-+};
-+#else
-+#error I feel sick.
-+#endif
-+
-+typedef union
-+{
-+	struct DWstruct s;
-+	long long ll;
-+} DWunion;
-+
-+#endif /* __ASM_LIBGCC_H */
-diff -Naur linux-2.6.17.orig/arch/mips/lib/lshrdi3.c linux-2.6.17/arch/mips/lib/lshrdi3.c
---- linux-2.6.17.orig/arch/mips/lib/lshrdi3.c	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/arch/mips/lib/lshrdi3.c	2006-06-19 18:16:13.000000000 -0700
-@@ -0,0 +1,29 @@
-+#include <linux/module.h>
-+
-+#include "libgcc.h"
-+
-+long long __lshrdi3(long long u, word_type b)
-+{
-+	DWunion uu, w;
-+	word_type bm;
-+
-+	if (b == 0)
-+		return u;
-+
-+	uu.ll = u;
-+	bm = 32 - b;
-+
-+	if (bm <= 0) {
-+		w.s.high = 0;
-+		w.s.low = (unsigned int) uu.s.high >> -bm;
-+	} else {
-+		const unsigned int carries = (unsigned int) uu.s.high << bm;
-+
-+		w.s.high = (unsigned int) uu.s.high >> b;
-+		w.s.low = ((unsigned int) uu.s.low >> b) | carries;
-+	}
-+
-+	return w.ll;
-+}
-+
-+EXPORT_SYMBOL(__lshrdi3);
-diff -Naur linux-2.6.17.orig/arch/mips/lib/Makefile linux-2.6.17/arch/mips/lib/Makefile
---- linux-2.6.17.orig/arch/mips/lib/Makefile	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/lib/Makefile	2006-06-19 18:16:40.000000000 -0700
-@@ -7,4 +7,7 @@
- 
- obj-y	+= iomap.o
- 
-+# libgcc-style stuff needed in the kernel
-+lib-y += ashldi3.o ashrdi3.o lshrdi3.o
-+
- EXTRA_AFLAGS := $(CFLAGS)
-diff -Naur linux-2.6.17.orig/arch/mips/lib-32/dump_tlb.c linux-2.6.17/arch/mips/lib-32/dump_tlb.c
---- linux-2.6.17.orig/arch/mips/lib-32/dump_tlb.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/lib-32/dump_tlb.c	2006-06-19 18:16:13.000000000 -0700
-@@ -41,8 +41,6 @@
- 		return "256Mb";
- #endif
- 	}
--
--	return "unknown";
- }
- 
- #define BARRIER()					\
-diff -Naur linux-2.6.17.orig/arch/mips/lib-64/dump_tlb.c linux-2.6.17/arch/mips/lib-64/dump_tlb.c
---- linux-2.6.17.orig/arch/mips/lib-64/dump_tlb.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/lib-64/dump_tlb.c	2006-06-19 18:16:13.000000000 -0700
-@@ -32,8 +32,6 @@
- 	case PM_256M:	return "256Mb";
- #endif
- 	}
--
--	return "unknown";
- }
- 
- #define BARRIER()					\
-diff -Naur linux-2.6.17.orig/arch/mips/Makefile linux-2.6.17/arch/mips/Makefile
---- linux-2.6.17.orig/arch/mips/Makefile	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/Makefile	2006-06-19 18:16:13.000000000 -0700
-@@ -83,6 +83,8 @@
- LDFLAGS_vmlinux			+= -G 0 -static -n -nostdlib
- MODFLAGS			+= -mlong-calls
- 
-+cflags-y += -ffreestanding
-+
- #
- # We explicitly add the endianness specifier if needed, this allows
- # to compile kernels with a toolchain for the other endianness. We
-@@ -285,6 +287,13 @@
- load-$(CONFIG_MIPS_EV96100)	+= 0xffffffff80100000
- 
- #
-+# Wind River PPMC Board (4KC + GT64120)
-+#
-+core-$(CONFIG_WR_PPMC)		+= arch/mips/gt64120/wrppmc/
-+cflags-$(CONFIG_WR_PPMC)		+= -Iinclude/asm-mips/mach-wrppmc
-+load-$(CONFIG_WR_PPMC)		+= 0xffffffff80100000
-+
-+#
- # Globespan IVR eval board with QED 5231 CPU
- #
- core-$(CONFIG_ITE_BOARD_GEN)	+= arch/mips/ite-boards/generic/
-@@ -365,6 +374,7 @@
- cflags-$(CONFIG_PMC_YOSEMITE)	+= -Iinclude/asm-mips/mach-yosemite
- load-$(CONFIG_PMC_YOSEMITE)	+= 0xffffffff80100000
- 
-+#
- # Qemu simulating MIPS32 4Kc
- #
- core-$(CONFIG_QEMU)		+= arch/mips/qemu/
-@@ -379,6 +389,13 @@
- load-$(CONFIG_MOMENCO_OCELOT_3) 	+= 0xffffffff80100000
- 
- #
-+# Basler eXcite
-+#
-+core-$(CONFIG_BASLER_EXCITE)	+= arch/mips/basler/excite/
-+cflags-$(CONFIG_BASLER_EXCITE)	+= -Iinclude/asm-mips/mach-excite
-+load-$(CONFIG_BASLER_EXCITE)	+= 0x80100000
-+
-+#
- # Momentum Jaguar ATX
- #
- core-$(CONFIG_MOMENCO_JAGUAR_ATX)	+= arch/mips/momentum/jaguar_atx/
-@@ -395,18 +412,6 @@
- core-$(CONFIG_DDB5XXX_COMMON)	+= arch/mips/ddb5xxx/common/
- 
- #
--# NEC DDB Vrc-5074
--#
--core-$(CONFIG_DDB5074)		+= arch/mips/ddb5xxx/ddb5074/
--load-$(CONFIG_DDB5074)		+= 0xffffffff80080000
--
--#
--# NEC DDB Vrc-5476
--#
--core-$(CONFIG_DDB5476)		+= arch/mips/ddb5xxx/ddb5476/
--load-$(CONFIG_DDB5476)		+= 0xffffffff80080000
--
--#
- # NEC DDB Vrc-5477
- #
- core-$(CONFIG_DDB5477)		+= arch/mips/ddb5xxx/ddb5477/
-@@ -468,6 +473,15 @@
- #cflags-$(CONFIG_PNX8550_JBS)	+= -Iinclude/asm-mips/mach-pnx8550
- load-$(CONFIG_PNX8550_JBS)	+= 0xffffffff80060000
- 
-+# NEC EMMA2RH boards
-+#
-+core-$(CONFIG_EMMA2RH)          += arch/mips/emma2rh/common/
-+cflags-$(CONFIG_EMMA2RH)        += -Iinclude/asm-mips/mach-emma2rh
-+
-+# NEC EMMA2RH Mark-eins
-+core-$(CONFIG_MARKEINS)         += arch/mips/emma2rh/markeins/
-+load-$(CONFIG_MARKEINS)         += 0xffffffff88100000
-+
- #
- # SGI IP22 (Indy/Indigo2)
- #
-diff -Naur linux-2.6.17.orig/arch/mips/math-emu/cp1emu.c linux-2.6.17/arch/mips/math-emu/cp1emu.c
---- linux-2.6.17.orig/arch/mips/math-emu/cp1emu.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/math-emu/cp1emu.c	2006-06-19 18:16:13.000000000 -0700
-@@ -60,15 +60,15 @@
- 
- /* Function which emulates a floating point instruction. */
- 
--static int fpu_emu(struct pt_regs *, struct mips_fpu_soft_struct *,
-+static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
- 	mips_instruction);
- 
- #if __mips >= 4 && __mips != 32
- static int fpux_emu(struct pt_regs *,
--	struct mips_fpu_soft_struct *, mips_instruction);
-+	struct mips_fpu_struct *, mips_instruction);
- #endif
- 
--/* Further private data for which no space exists in mips_fpu_soft_struct */
-+/* Further private data for which no space exists in mips_fpu_struct */
- 
- struct mips_fpu_emulator_stats fpuemustats;
- 
-@@ -203,7 +203,7 @@
-  * Two instructions if the instruction is in a branch delay slot.
-  */
- 
--static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
-+static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
- {
- 	mips_instruction ir;
- 	void * emulpc, *contpc;
-@@ -595,7 +595,7 @@
- DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
- DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
- 
--static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
-+static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
- 	mips_instruction ir)
- {
- 	unsigned rcsr = 0;	/* resulting csr */
-@@ -759,7 +759,7 @@
- /*
-  * Emulate a single COP1 arithmetic instruction.
-  */
--static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
-+static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
- 	mips_instruction ir)
- {
- 	int rfmt;		/* resulting format */
-@@ -1233,8 +1233,7 @@
- 	return 0;
- }
- 
--int fpu_emulator_cop1Handler(struct pt_regs *xcp,
--	struct mips_fpu_soft_struct *ctx)
-+int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
- {
- 	unsigned long oldepc, prevepc;
- 	mips_instruction insn;
-diff -Naur linux-2.6.17.orig/arch/mips/math-emu/ieee754.h linux-2.6.17/arch/mips/math-emu/ieee754.h
---- linux-2.6.17.orig/arch/mips/math-emu/ieee754.h	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/math-emu/ieee754.h	2006-06-19 18:16:13.000000000 -0700
-@@ -329,7 +329,7 @@
- 	unsigned pad0:7;
- #endif
- };
--#define ieee754_csr (*(struct _ieee754_csr *)(&current->thread.fpu.soft.fcr31))
-+#define ieee754_csr (*(struct _ieee754_csr *)(&current->thread.fpu.fcr31))
- 
- static inline unsigned ieee754_getrm(void)
- {
-diff -Naur linux-2.6.17.orig/arch/mips/math-emu/kernel_linkage.c linux-2.6.17/arch/mips/math-emu/kernel_linkage.c
---- linux-2.6.17.orig/arch/mips/math-emu/kernel_linkage.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/math-emu/kernel_linkage.c	2006-06-19 18:16:13.000000000 -0700
-@@ -39,9 +39,9 @@
- 		printk("Algorithmics/MIPS FPU Emulator v1.5\n");
- 	}
- 
--	current->thread.fpu.soft.fcr31 = 0;
-+	current->thread.fpu.fcr31 = 0;
- 	for (i = 0; i < 32; i++) {
--		current->thread.fpu.soft.fpr[i] = SIGNALLING_NAN;
-+		current->thread.fpu.fpr[i] = SIGNALLING_NAN;
- 	}
- }
- 
-@@ -59,10 +59,9 @@
- 
- 	for (i = 0; i < 32; i++) {
- 		err |=
--		    __put_user(current->thread.fpu.soft.fpr[i],
--			       &sc->sc_fpregs[i]);
-+		    __put_user(current->thread.fpu.fpr[i], &sc->sc_fpregs[i]);
- 	}
--	err |= __put_user(current->thread.fpu.soft.fcr31, &sc->sc_fpc_csr);
-+	err |= __put_user(current->thread.fpu.fcr31, &sc->sc_fpc_csr);
- 
- 	return err;
- }
-@@ -74,10 +73,9 @@
- 
- 	for (i = 0; i < 32; i++) {
- 		err |=
--		    __get_user(current->thread.fpu.soft.fpr[i],
--			       &sc->sc_fpregs[i]);
-+		    __get_user(current->thread.fpu.fpr[i], &sc->sc_fpregs[i]);
- 	}
--	err |= __get_user(current->thread.fpu.soft.fcr31, &sc->sc_fpc_csr);
-+	err |= __get_user(current->thread.fpu.fcr31, &sc->sc_fpc_csr);
- 
- 	return err;
- }
-@@ -94,10 +92,9 @@
- 
- 	for (i = 0; i < 32; i+=2) {
- 		err |=
--		    __put_user(current->thread.fpu.soft.fpr[i],
--			       &sc->sc_fpregs[i]);
-+		    __put_user(current->thread.fpu.fpr[i], &sc->sc_fpregs[i]);
- 	}
--	err |= __put_user(current->thread.fpu.soft.fcr31, &sc->sc_fpc_csr);
-+	err |= __put_user(current->thread.fpu.fcr31, &sc->sc_fpc_csr);
- 
- 	return err;
- }
-@@ -109,10 +106,9 @@
- 
- 	for (i = 0; i < 32; i+=2) {
- 		err |=
--		    __get_user(current->thread.fpu.soft.fpr[i],
--			       &sc->sc_fpregs[i]);
-+		    __get_user(current->thread.fpu.fpr[i], &sc->sc_fpregs[i]);
- 	}
--	err |= __get_user(current->thread.fpu.soft.fcr31, &sc->sc_fpc_csr);
-+	err |= __get_user(current->thread.fpu.fcr31, &sc->sc_fpc_csr);
- 
- 	return err;
- }
-diff -Naur linux-2.6.17.orig/arch/mips/mips-boards/atlas/atlas_setup.c linux-2.6.17/arch/mips/mips-boards/atlas/atlas_setup.c
---- linux-2.6.17.orig/arch/mips/mips-boards/atlas/atlas_setup.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/mips-boards/atlas/atlas_setup.c	2006-06-19 18:16:13.000000000 -0700
-@@ -50,7 +50,7 @@
- 	return "MIPS Atlas";
- }
- 
--void __init plat_setup(void)
-+void __init plat_mem_setup(void)
- {
- 	mips_pcibios_init();
- 
-diff -Naur linux-2.6.17.orig/arch/mips/mips-boards/generic/memory.c linux-2.6.17/arch/mips/mips-boards/generic/memory.c
---- linux-2.6.17.orig/arch/mips/mips-boards/generic/memory.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/mips-boards/generic/memory.c	2006-06-19 18:16:13.000000000 -0700
-@@ -76,6 +76,15 @@
- 			memsize = simple_strtol(memsize_str, NULL, 0);
- 		}
- 	}
-+
-+#ifdef CONFIG_CPU_BIG_ENDIAN
-+	/*
-+	 * SOC-it swaps, or perhaps doesn't swap, when DMA'ing the last
-+	 * word of physical memory
-+	 */
-+	memsize -= PAGE_SIZE;
-+#endif
-+
- 	memset(mdesc, 0, sizeof(mdesc));
- 
- 	mdesc[0].type = yamon_dontuse;
-diff -Naur linux-2.6.17.orig/arch/mips/mips-boards/malta/malta_int.c linux-2.6.17/arch/mips/mips-boards/malta/malta_int.c
---- linux-2.6.17.orig/arch/mips/mips-boards/malta/malta_int.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/mips-boards/malta/malta_int.c	2006-06-19 18:16:13.000000000 -0700
-@@ -208,23 +208,23 @@
- 	unsigned int a0 = 7;
- 	unsigned int t0;
- 
--	t0 = s0 & 0xf000;
-+	t0 = pending & 0xf000;
- 	t0 = t0 < 1;
- 	t0 = t0 << 2;
- 	a0 = a0 - t0;
--	s0 = s0 << t0;
-+	pending = pending << t0;
- 
--	t0 = s0 & 0xc000;
-+	t0 = pending & 0xc000;
- 	t0 = t0 < 1;
- 	t0 = t0 << 1;
- 	a0 = a0 - t0;
--	s0 = s0 << t0;
-+	pending = pending << t0;
- 
--	t0 = s0 & 0x8000;
-+	t0 = pending & 0x8000;
- 	t0 = t0 < 1;
- 	//t0 = t0 << 2;
- 	a0 = a0 - t0;
--	//s0 = s0 << t0;
-+	//pending = pending << t0;
- 
- 	return a0;
- #endif
-diff -Naur linux-2.6.17.orig/arch/mips/mips-boards/malta/malta_setup.c linux-2.6.17/arch/mips/mips-boards/malta/malta_setup.c
---- linux-2.6.17.orig/arch/mips/mips-boards/malta/malta_setup.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/mips-boards/malta/malta_setup.c	2006-06-19 18:16:13.000000000 -0700
-@@ -53,11 +53,11 @@
- #endif
- 
- struct resource standard_io_resources[] = {
--	{ "dma1", 0x00, 0x1f, IORESOURCE_BUSY },
--	{ "timer", 0x40, 0x5f, IORESOURCE_BUSY },
--	{ "keyboard", 0x60, 0x6f, IORESOURCE_BUSY },
--	{ "dma page reg", 0x80, 0x8f, IORESOURCE_BUSY },
--	{ "dma2", 0xc0, 0xdf, IORESOURCE_BUSY },
-+	{ .name = "dma1", .start = 0x00, .end = 0x1f, .flags = IORESOURCE_BUSY },
-+	{ .name = "timer", .start = 0x40, .end = 0x5f, .flags = IORESOURCE_BUSY },
-+	{ .name = "keyboard", .start = 0x60, .end = 0x6f, .flags = IORESOURCE_BUSY },
-+	{ .name = "dma page reg", .start = 0x80, .end = 0x8f, .flags = IORESOURCE_BUSY },
-+	{ .name = "dma2", .start = 0xc0, .end = 0xdf, .flags = IORESOURCE_BUSY },
- };
- 
- #ifdef CONFIG_MTD
-@@ -111,7 +111,7 @@
- }
- #endif
- 
--void __init plat_setup(void)
-+void __init plat_mem_setup(void)
- {
- 	unsigned int i;
- 
-diff -Naur linux-2.6.17.orig/arch/mips/mips-boards/malta/malta_smp.c linux-2.6.17/arch/mips/mips-boards/malta/malta_smp.c
---- linux-2.6.17.orig/arch/mips/mips-boards/malta/malta_smp.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/mips-boards/malta/malta_smp.c	2006-06-19 18:16:13.000000000 -0700
-@@ -34,25 +34,6 @@
- }
- 
- /*
-- * Detect available CPUs/VPEs/TCs and populate phys_cpu_present_map
-- */
--
--void __init prom_build_cpu_map(void)
--{
--	int nextslot;
--
--	/*
--	 * As of November, 2004, MIPSsim only simulates one core
--	 * at a time.  However, that core may be a MIPS MT core
--	 * with multiple virtual processors and thread contexts.
--	 */
--
--	if (read_c0_config3() & (1<<2)) {
--		nextslot = mipsmt_build_cpu_map(1);
--	}
--}
--
--/*
-  * Platform "CPU" startup hook
-  */
- 
-diff -Naur linux-2.6.17.orig/arch/mips/mips-boards/sead/sead_setup.c linux-2.6.17/arch/mips/mips-boards/sead/sead_setup.c
---- linux-2.6.17.orig/arch/mips/mips-boards/sead/sead_setup.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/mips-boards/sead/sead_setup.c	2006-06-19 18:16:13.000000000 -0700
-@@ -45,7 +45,7 @@
- 	return "MIPS SEAD";
- }
- 
--void __init plat_setup(void)
-+void __init plat_mem_setup(void)
- {
- 	ioport_resource.end = 0x7fffffff;
- 
-diff -Naur linux-2.6.17.orig/arch/mips/mips-boards/sim/sim_setup.c linux-2.6.17/arch/mips/mips-boards/sim/sim_setup.c
---- linux-2.6.17.orig/arch/mips/mips-boards/sim/sim_setup.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/mips-boards/sim/sim_setup.c	2006-06-19 18:16:13.000000000 -0700
-@@ -50,7 +50,7 @@
- 	return "MIPSsim";
- }
- 
--void __init plat_setup(void)
-+void __init plat_mem_setup(void)
- {
- 	set_io_port_base(0xbfd00000);
- 
-diff -Naur linux-2.6.17.orig/arch/mips/mips-boards/sim/sim_smp.c linux-2.6.17/arch/mips/mips-boards/sim/sim_smp.c
---- linux-2.6.17.orig/arch/mips/mips-boards/sim/sim_smp.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/mips-boards/sim/sim_smp.c	2006-06-19 18:16:13.000000000 -0700
-@@ -51,27 +51,6 @@
- }
- 
- /*
-- * Detect available CPUs/VPEs/TCs and populate phys_cpu_present_map
-- */
--
--void __init prom_build_cpu_map(void)
--{
--#ifdef CONFIG_MIPS_MT_SMTC
--	int nextslot;
--
--	/*
--	 * As of November, 2004, MIPSsim only simulates one core
--	 * at a time.  However, that core may be a MIPS MT core
--	 * with multiple virtual processors and thread contexts.
--	 */
--
--	if (read_c0_config3() & (1<<2)) {
--		nextslot = mipsmt_build_cpu_map(1);
--	}
--#endif /* CONFIG_MIPS_MT_SMTC */
--}
--
--/*
-  * Platform "CPU" startup hook
-  */
- 
-diff -Naur linux-2.6.17.orig/arch/mips/mm/tlb-r4k.c linux-2.6.17/arch/mips/mm/tlb-r4k.c
---- linux-2.6.17.orig/arch/mips/mm/tlb-r4k.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/mm/tlb-r4k.c	2006-06-19 18:16:13.000000000 -0700
-@@ -413,7 +413,6 @@
- 	return ret;
- }
- 
--extern void __init sanitize_tlb_entries(void);
- static void __init probe_tlb(unsigned long config)
- {
- 	struct cpuinfo_mips *c = &current_cpu_data;
-diff -Naur linux-2.6.17.orig/arch/mips/momentum/jaguar_atx/setup.c linux-2.6.17/arch/mips/momentum/jaguar_atx/setup.c
---- linux-2.6.17.orig/arch/mips/momentum/jaguar_atx/setup.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/momentum/jaguar_atx/setup.c	2006-06-19 18:16:13.000000000 -0700
-@@ -359,7 +359,7 @@
- 
- arch_initcall(ja_pci_init);
- 
--void __init plat_setup(void)
-+void __init plat_mem_setup(void)
- {
- 	unsigned int tmpword;
- 
-diff -Naur linux-2.6.17.orig/arch/mips/momentum/ocelot_3/setup.c linux-2.6.17/arch/mips/momentum/ocelot_3/setup.c
---- linux-2.6.17.orig/arch/mips/momentum/ocelot_3/setup.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/momentum/ocelot_3/setup.c	2006-06-19 18:16:13.000000000 -0700
-@@ -313,7 +313,7 @@
- 
- arch_initcall(ja_pci_init);
- 
--void __init plat_setup(void)
-+void __init plat_mem_setup(void)
- {
- 	unsigned int tmpword;
- 
-diff -Naur linux-2.6.17.orig/arch/mips/momentum/ocelot_c/setup.c linux-2.6.17/arch/mips/momentum/ocelot_c/setup.c
---- linux-2.6.17.orig/arch/mips/momentum/ocelot_c/setup.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/momentum/ocelot_c/setup.c	2006-06-19 18:16:13.000000000 -0700
-@@ -231,7 +231,7 @@
- 	rtc_mips_set_time = m48t37y_set_time;
- }
- 
--void __init plat_setup(void)
-+void __init plat_mem_setup(void)
- {
- 	unsigned int tmpword;
- 
-diff -Naur linux-2.6.17.orig/arch/mips/momentum/ocelot_g/setup.c linux-2.6.17/arch/mips/momentum/ocelot_g/setup.c
---- linux-2.6.17.orig/arch/mips/momentum/ocelot_g/setup.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/momentum/ocelot_g/setup.c	2006-06-19 18:16:13.000000000 -0700
-@@ -162,7 +162,7 @@
- 	printk("Done\n");
- }
- 
--void __init plat_setup(void)
-+void __init plat_mem_setup(void)
- {
- 	void (*l3func)(unsigned long) = (void *) KSEG1ADDR(setup_l3cache);
- 	unsigned int tmpword;
-diff -Naur linux-2.6.17.orig/arch/mips/pci/fixup-ddb5074.c linux-2.6.17/arch/mips/pci/fixup-ddb5074.c
---- linux-2.6.17.orig/arch/mips/pci/fixup-ddb5074.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/pci/fixup-ddb5074.c	1969-12-31 16:00:00.000000000 -0800
-@@ -1,21 +0,0 @@
--/*
-- * It's nice to have the LEDs on the GPIO pins available for debugging
-- */
--static void ddb5074_fixup(struct pci_dev *dev)
--{
--	extern struct pci_dev *pci_pmu;
--	u8 t8;
--
--	pci_pmu = dev;  /* for LEDs D2 and D3 */
--	/* Program the lines for LEDs D2 and D3 to output */
--	pci_read_config_byte(dev, 0x7d, &t8);
--	t8 |= 0xc0;
--	pci_write_config_byte(dev, 0x7d, t8);
--	/* Turn LEDs D2 and D3 off */
--	pci_read_config_byte(dev, 0x7e, &t8);
--	t8 |= 0xc0;
--	pci_write_config_byte(dev, 0x7e, t8);
--}
--
--DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101,
--	  ddb5074_fixup);
-diff -Naur linux-2.6.17.orig/arch/mips/pci/fixup-emma2rh.c linux-2.6.17/arch/mips/pci/fixup-emma2rh.c
---- linux-2.6.17.orig/arch/mips/pci/fixup-emma2rh.c	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/arch/mips/pci/fixup-emma2rh.c	2006-06-19 18:16:13.000000000 -0700
-@@ -0,0 +1,102 @@
-+/*
-+ *  arch/mips/pci/fixup-emma2rh.c
-+ *      This file defines the PCI configration.
-+ *
-+ *  Copyright (C) NEC Electronics Corporation 2004-2006
-+ *
-+ *  This file is based on the arch/mips/ddb5xxx/ddb5477/pci.c
-+ *
-+ *	Copyright 2001 MontaVista Software Inc.
-+ *
-+ *  This program is free software; you can redistribute it and/or modify
-+ *  it under the terms of the GNU General Public License as published by
-+ *  the Free Software Foundation; either version 2 of the License, or
-+ *  (at your option) any later version.
-+ *
-+ *  This program is distributed in the hope that it will be useful,
-+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ *  GNU General Public License for more details.
-+ *
-+ *  You should have received a copy of the GNU General Public License
-+ *  along with this program; if not, write to the Free Software
-+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-+ */
-+
-+#include <linux/config.h>
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/types.h>
-+#include <linux/pci.h>
-+
-+#include <asm/bootinfo.h>
-+#include <asm/debug.h>
-+
-+#include <asm/emma2rh/emma2rh.h>
-+
-+#define EMMA2RH_PCI_HOST_SLOT 0x09
-+#define EMMA2RH_USB_SLOT 0x03
-+#define PCI_DEVICE_ID_NEC_EMMA2RH      0x014b /* EMMA2RH PCI Host */
-+
-+/*
-+ * we fix up irqs based on the slot number.
-+ * The first entry is at AD:11.
-+ * Fortunately this works because, although we have two pci buses,
-+ * they all have different slot numbers (except for rockhopper slot 20
-+ * which is handled below).
-+ *
-+ */
-+
-+#define	MAX_SLOT_NUM 10
-+static unsigned char irq_map[][5] __initdata = {
-+	[3] = {0, MARKEINS_PCI_IRQ_INTB, MARKEINS_PCI_IRQ_INTC,
-+	       MARKEINS_PCI_IRQ_INTD, 0,},
-+	[4] = {0, MARKEINS_PCI_IRQ_INTA, 0, 0, 0,},
-+	[5] = {0, 0, 0, 0, 0,},
-+	[6] = {0, MARKEINS_PCI_IRQ_INTC, MARKEINS_PCI_IRQ_INTD,
-+	       MARKEINS_PCI_IRQ_INTA, MARKEINS_PCI_IRQ_INTB,},
-+};
-+
-+static void __devinit nec_usb_controller_fixup(struct pci_dev *dev)
-+{
-+	if (PCI_SLOT(dev->devfn) == EMMA2RH_USB_SLOT)
-+		/* on board USB controller configuration */
-+		pci_write_config_dword(dev, 0xe4, 1 << 5);
-+}
-+
-+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB,
-+			nec_usb_controller_fixup);
-+
-+/*
-+ * Prevent the PCI layer from seeing the resources allocated to this device
-+ * if it is the host bridge by marking it as such.  These resources are of
-+ * no consequence to the PCI layer (they are handled elsewhere).
-+ */
-+static void __devinit emma2rh_pci_host_fixup(struct pci_dev *dev)
-+{
-+	int i;
-+
-+	if (PCI_SLOT(dev->devfn) == EMMA2RH_PCI_HOST_SLOT) {
-+		dev->class &= 0xff;
-+		dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
-+		for (i = 0; i < PCI_NUM_RESOURCES; i++) {
-+			dev->resource[i].start = 0;
-+			dev->resource[i].end = 0;
-+			dev->resource[i].flags = 0;
-+		}
-+	}
-+}
-+
-+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_EMMA2RH,
-+			 emma2rh_pci_host_fixup);
-+
-+int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
-+{
-+	return irq_map[slot][pin];
-+}
-+
-+/* Do platform specific device initialization at pci_enable_device() time */
-+int pcibios_plat_dev_init(struct pci_dev *dev)
-+{
-+	return 0;
-+}
-diff -Naur linux-2.6.17.orig/arch/mips/pci/fixup-excite.c linux-2.6.17/arch/mips/pci/fixup-excite.c
---- linux-2.6.17.orig/arch/mips/pci/fixup-excite.c	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/arch/mips/pci/fixup-excite.c	2006-06-19 18:16:13.000000000 -0700
-@@ -0,0 +1,36 @@
-+/*
-+ *  Copyright (C) 2004 by Basler Vision Technologies AG
-+ *  Author: Thomas Koeller <thomas.koeller@baslerweb.com>
-+ *
-+ *  This program is free software; you can redistribute it and/or modify
-+ *  it under the terms of the GNU General Public License as published by
-+ *  the Free Software Foundation; either version 2 of the License, or
-+ *  (at your option) any later version.
-+ *
-+ *  This program is distributed in the hope that it will be useful,
-+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ *  GNU General Public License for more details.
-+ *
-+ *  You should have received a copy of the GNU General Public License
-+ *  along with this program; if not, write to the Free Software
-+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-+ */
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/pci.h>
-+#include <excite.h>
-+
-+int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
-+{
-+	if (pin == 0)
-+		return -1;
-+
-+	return USB_IRQ;		/* USB controller is the only PCI device */
-+}
-+
-+/* Do platform specific device initialization at pci_enable_device() time */
-+int pcibios_plat_dev_init(struct pci_dev *dev)
-+{
-+	return 0;
-+}
-diff -Naur linux-2.6.17.orig/arch/mips/pci/fixup-tb0219.c linux-2.6.17/arch/mips/pci/fixup-tb0219.c
---- linux-2.6.17.orig/arch/mips/pci/fixup-tb0219.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/pci/fixup-tb0219.c	2006-06-19 18:16:13.000000000 -0700
-@@ -2,7 +2,7 @@
-  *  fixup-tb0219.c, The TANBAC TB0219 specific PCI fixups.
-  *
-  *  Copyright (C) 2003  Megasolution Inc. <matsu@megasolution.jp>
-- *  Copyright (C) 2004  Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
-+ *  Copyright (C) 2004-2005  Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
-  *
-  *  This program is free software; you can redistribute it and/or modify
-  *  it under the terms of the GNU General Public License as published by
-diff -Naur linux-2.6.17.orig/arch/mips/pci/fixup-wrppmc.c linux-2.6.17/arch/mips/pci/fixup-wrppmc.c
---- linux-2.6.17.orig/arch/mips/pci/fixup-wrppmc.c	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/arch/mips/pci/fixup-wrppmc.c	2006-06-19 18:16:13.000000000 -0700
-@@ -0,0 +1,37 @@
-+/*
-+ * fixup-wrppmc.c: PPMC board specific PCI fixup
-+ *
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License.  See the file "COPYING" in the main directory of this archive
-+ * for more details.
-+ *
-+ * Copyright (C) 2006, Wind River Inc. Rongkai.zhan (rongkai.zhan@windriver.com)
-+ */
-+#include <linux/init.h>
-+#include <linux/pci.h>
-+#include <asm/gt64120.h>
-+
-+/* PCI interrupt pins */
-+#define PCI_INTA		1
-+#define PCI_INTB		2
-+#define PCI_INTC		3
-+#define PCI_INTD		4
-+
-+#define PCI_SLOT_MAXNR	32 /* Each PCI bus has 32 physical slots */
-+
-+static char pci_irq_tab[PCI_SLOT_MAXNR][5] __initdata = {
-+	/* 0    INTA   INTB   INTC   INTD */
-+	[0] = {0, 0, 0, 0, 0},		/* Slot 0: GT64120 PCI bridge */
-+	[6] = {0, WRPPMC_PCI_INTA_IRQ, 0, 0, 0},
-+};
-+
-+int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
-+{
-+	return pci_irq_tab[slot][pin];
-+}
-+
-+/* Do platform specific device initialization at pci_enable_device() time */
-+int pcibios_plat_dev_init(struct pci_dev *dev)
-+{
-+	return 0;
-+}
-diff -Naur linux-2.6.17.orig/arch/mips/pci/Makefile linux-2.6.17/arch/mips/pci/Makefile
---- linux-2.6.17.orig/arch/mips/pci/Makefile	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/pci/Makefile	2006-06-19 18:16:13.000000000 -0700
-@@ -18,12 +18,12 @@
- obj-$(CONFIG_MIPS_TX3927)	+= ops-tx3927.o
- obj-$(CONFIG_PCI_VR41XX)	+= ops-vr41xx.o pci-vr41xx.o
- obj-$(CONFIG_NEC_CMBVR4133)	+= fixup-vr4133.o
-+obj-$(CONFIG_MARKEINS)		+= ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o
- 
- #
- # These are still pretty much in the old state, watch, go blind.
- #
--obj-$(CONFIG_DDB5074)		+= fixup-ddb5074.o pci-ddb5074.o ops-ddb5074.o
--obj-$(CONFIG_DDB5476)		+= ops-ddb5476.o pci-ddb5476.o
-+obj-$(CONFIG_BASLER_EXCITE)	= ops-titan.o pci-excite.o fixup-excite.o
- obj-$(CONFIG_DDB5477)		+= fixup-ddb5477.o pci-ddb5477.o ops-ddb5477.o
- obj-$(CONFIG_LASAT)		+= pci-lasat.o
- obj-$(CONFIG_MIPS_ATLAS)	+= fixup-atlas.o
-@@ -43,7 +43,7 @@
- obj-$(CONFIG_MOMENCO_OCELOT_G)	+= fixup-ocelot-g.o pci-ocelot-g.o
- obj-$(CONFIG_PMC_YOSEMITE)	+= fixup-yosemite.o ops-titan.o ops-titan-ht.o \
- 				   pci-yosemite.o
--obj-$(CONFIG_SGI_IP27)		+= pci-ip27.o
-+obj-$(CONFIG_SGI_IP27)		+= ops-bridge.o pci-ip27.o
- obj-$(CONFIG_SGI_IP32)		+= fixup-ip32.o ops-mace.o pci-ip32.o
- obj-$(CONFIG_SIBYTE_SB1250)	+= fixup-sb1250.o pci-sb1250.o
- obj-$(CONFIG_SIBYTE_BCM112X)	+= fixup-sb1250.o pci-sb1250.o
-@@ -57,3 +57,4 @@
- obj-$(CONFIG_TOSHIBA_RBTX4938)	+= fixup-tx4938.o ops-tx4938.o
- obj-$(CONFIG_VICTOR_MPC30X)	+= fixup-mpc30x.o
- obj-$(CONFIG_ZAO_CAPCELLA)	+= fixup-capcella.o
-+obj-$(CONFIG_WR_PPMC)		+= fixup-wrppmc.o
-diff -Naur linux-2.6.17.orig/arch/mips/pci/ops-bridge.c linux-2.6.17/arch/mips/pci/ops-bridge.c
---- linux-2.6.17.orig/arch/mips/pci/ops-bridge.c	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/arch/mips/pci/ops-bridge.c	2006-06-19 18:16:13.000000000 -0700
-@@ -0,0 +1,306 @@
-+/*
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License.  See the file "COPYING" in the main directory of this archive
-+ * for more details.
-+ *
-+ * Copyright (C) 1999, 2000, 04, 06 Ralf Baechle (ralf@linux-mips.org)
-+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
-+ */
-+#include <linux/pci.h>
-+#include <asm/paccess.h>
-+#include <asm/pci/bridge.h>
-+#include <asm/sn/arch.h>
-+#include <asm/sn/intr.h>
-+#include <asm/sn/sn0/hub.h>
-+
-+/*
-+ * The Bridge ASIC supports both type 0 and type 1 access.  Type 1 is
-+ * not really documented, so right now I can't write code which uses it.
-+ * Therefore we use type 0 accesses for now even though they won't work
-+ * correcly for PCI-to-PCI bridges.
-+ *
-+ * The function is complicated by the ultimate brokeness of the IOC3 chip
-+ * which is used in SGI systems.  The IOC3 can only handle 32-bit PCI
-+ * accesses and does only decode parts of it's address space.
-+ */
-+
-+static int pci_conf0_read_config(struct pci_bus *bus, unsigned int devfn,
-+				 int where, int size, u32 * value)
-+{
-+	struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
-+	bridge_t *bridge = bc->base;
-+	int slot = PCI_SLOT(devfn);
-+	int fn = PCI_FUNC(devfn);
-+	volatile void *addr;
-+	u32 cf, shift, mask;
-+	int res;
-+
-+	addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID];
-+	if (get_dbe(cf, (u32 *) addr))
-+		return PCIBIOS_DEVICE_NOT_FOUND;
-+
-+	/*
-+	 * IOC3 is fucked fucked beyond believe ...  Don't even give the
-+	 * generic PCI code a chance to look at it for real ...
-+	 */
-+	if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
-+		goto oh_my_gawd;
-+
-+	addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)];
-+
-+	if (size == 1)
-+		res = get_dbe(*value, (u8 *) addr);
-+	else if (size == 2)
-+		res = get_dbe(*value, (u16 *) addr);
-+	else
-+		res = get_dbe(*value, (u32 *) addr);
-+
-+	return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
-+
-+oh_my_gawd:
-+
-+	/*
-+	 * IOC3 is fucked fucked beyond believe ...  Don't even give the
-+	 * generic PCI code a chance to look at the wrong register.
-+	 */
-+	if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) {
-+		*value = 0;
-+		return PCIBIOS_SUCCESSFUL;
-+	}
-+
-+	/*
-+	 * IOC3 is fucked fucked beyond believe ...  Don't try to access
-+	 * anything but 32-bit words ...
-+	 */
-+	addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
-+
-+	if (get_dbe(cf, (u32 *) addr))
-+		return PCIBIOS_DEVICE_NOT_FOUND;
-+
-+	shift = ((where & 3) << 3);
-+	mask = (0xffffffffU >> ((4 - size) << 3));
-+	*value = (cf >> shift) & mask;
-+
-+	return PCIBIOS_SUCCESSFUL;
-+}
-+
-+static int pci_conf1_read_config(struct pci_bus *bus, unsigned int devfn,
-+				 int where, int size, u32 * value)
-+{
-+	struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
-+	bridge_t *bridge = bc->base;
-+	int busno = bus->number;
-+	int slot = PCI_SLOT(devfn);
-+	int fn = PCI_FUNC(devfn);
-+	volatile void *addr;
-+	u32 cf, shift, mask;
-+	int res;
-+
-+	bridge->b_pci_cfg = (busno << 16) | (slot << 11);
-+	addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID];
-+	if (get_dbe(cf, (u32 *) addr))
-+		return PCIBIOS_DEVICE_NOT_FOUND;
-+
-+	/*
-+	 * IOC3 is fucked fucked beyond believe ...  Don't even give the
-+	 * generic PCI code a chance to look at it for real ...
-+	 */
-+	if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
-+		goto oh_my_gawd;
-+
-+	bridge->b_pci_cfg = (busno << 16) | (slot << 11);
-+	addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))];
-+
-+	if (size == 1)
-+		res = get_dbe(*value, (u8 *) addr);
-+	else if (size == 2)
-+		res = get_dbe(*value, (u16 *) addr);
-+	else
-+		res = get_dbe(*value, (u32 *) addr);
-+
-+	return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
-+
-+oh_my_gawd:
-+
-+	/*
-+	 * IOC3 is fucked fucked beyond believe ...  Don't even give the
-+	 * generic PCI code a chance to look at the wrong register.
-+	 */
-+	if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) {
-+		*value = 0;
-+		return PCIBIOS_SUCCESSFUL;
-+	}
-+
-+	/*
-+	 * IOC3 is fucked fucked beyond believe ...  Don't try to access
-+	 * anything but 32-bit words ...
-+	 */
-+	bridge->b_pci_cfg = (busno << 16) | (slot << 11);
-+	addr = &bridge->b_type1_cfg.c[(fn << 8) | where];
-+
-+	if (get_dbe(cf, (u32 *) addr))
-+		return PCIBIOS_DEVICE_NOT_FOUND;
-+
-+	shift = ((where & 3) << 3);
-+	mask = (0xffffffffU >> ((4 - size) << 3));
-+	*value = (cf >> shift) & mask;
-+
-+	return PCIBIOS_SUCCESSFUL;
-+}
-+
-+static int pci_read_config(struct pci_bus *bus, unsigned int devfn,
-+			   int where, int size, u32 * value)
-+{
-+	if (bus->number > 0)
-+		return pci_conf1_read_config(bus, devfn, where, size, value);
-+
-+	return pci_conf0_read_config(bus, devfn, where, size, value);
-+}
-+
-+static int pci_conf0_write_config(struct pci_bus *bus, unsigned int devfn,
-+				  int where, int size, u32 value)
-+{
-+	struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
-+	bridge_t *bridge = bc->base;
-+	int slot = PCI_SLOT(devfn);
-+	int fn = PCI_FUNC(devfn);
-+	volatile void *addr;
-+	u32 cf, shift, mask, smask;
-+	int res;
-+
-+	addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID];
-+	if (get_dbe(cf, (u32 *) addr))
-+		return PCIBIOS_DEVICE_NOT_FOUND;
-+
-+	/*
-+	 * IOC3 is fucked fucked beyond believe ...  Don't even give the
-+	 * generic PCI code a chance to look at it for real ...
-+	 */
-+	if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
-+		goto oh_my_gawd;
-+
-+	addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)];
-+
-+	if (size == 1) {
-+		res = put_dbe(value, (u8 *) addr);
-+	} else if (size == 2) {
-+		res = put_dbe(value, (u16 *) addr);
-+	} else {
-+		res = put_dbe(value, (u32 *) addr);
-+	}
-+
-+	if (res)
-+		return PCIBIOS_DEVICE_NOT_FOUND;
-+
-+	return PCIBIOS_SUCCESSFUL;
-+
-+oh_my_gawd:
-+
-+	/*
-+	 * IOC3 is fucked fucked beyond believe ...  Don't even give the
-+	 * generic PCI code a chance to touch the wrong register.
-+	 */
-+	if ((where >= 0x14 && where < 0x40) || (where >= 0x48))
-+		return PCIBIOS_SUCCESSFUL;
-+
-+	/*
-+	 * IOC3 is fucked fucked beyond believe ...  Don't try to access
-+	 * anything but 32-bit words ...
-+	 */
-+	addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
-+
-+	if (get_dbe(cf, (u32 *) addr))
-+		return PCIBIOS_DEVICE_NOT_FOUND;
-+
-+	shift = ((where & 3) << 3);
-+	mask = (0xffffffffU >> ((4 - size) << 3));
-+	smask = mask << shift;
-+
-+	cf = (cf & ~smask) | ((value & mask) << shift);
-+	if (put_dbe(cf, (u32 *) addr))
-+		return PCIBIOS_DEVICE_NOT_FOUND;
-+
-+	return PCIBIOS_SUCCESSFUL;
-+}
-+
-+static int pci_conf1_write_config(struct pci_bus *bus, unsigned int devfn,
-+				  int where, int size, u32 value)
-+{
-+	struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
-+	bridge_t *bridge = bc->base;
-+	int slot = PCI_SLOT(devfn);
-+	int fn = PCI_FUNC(devfn);
-+	int busno = bus->number;
-+	volatile void *addr;
-+	u32 cf, shift, mask, smask;
-+	int res;
-+
-+	bridge->b_pci_cfg = (busno << 16) | (slot << 11);
-+	addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID];
-+	if (get_dbe(cf, (u32 *) addr))
-+		return PCIBIOS_DEVICE_NOT_FOUND;
-+
-+	/*
-+	 * IOC3 is fucked fucked beyond believe ...  Don't even give the
-+	 * generic PCI code a chance to look at it for real ...
-+	 */
-+	if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
-+		goto oh_my_gawd;
-+
-+	addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))];
-+
-+	if (size == 1) {
-+		res = put_dbe(value, (u8 *) addr);
-+	} else if (size == 2) {
-+		res = put_dbe(value, (u16 *) addr);
-+	} else {
-+		res = put_dbe(value, (u32 *) addr);
-+	}
-+
-+	if (res)
-+		return PCIBIOS_DEVICE_NOT_FOUND;
-+
-+	return PCIBIOS_SUCCESSFUL;
-+
-+oh_my_gawd:
-+
-+	/*
-+	 * IOC3 is fucked fucked beyond believe ...  Don't even give the
-+	 * generic PCI code a chance to touch the wrong register.
-+	 */
-+	if ((where >= 0x14 && where < 0x40) || (where >= 0x48))
-+		return PCIBIOS_SUCCESSFUL;
-+
-+	/*
-+	 * IOC3 is fucked fucked beyond believe ...  Don't try to access
-+	 * anything but 32-bit words ...
-+	 */
-+	addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
-+
-+	if (get_dbe(cf, (u32 *) addr))
-+		return PCIBIOS_DEVICE_NOT_FOUND;
-+
-+	shift = ((where & 3) << 3);
-+	mask = (0xffffffffU >> ((4 - size) << 3));
-+	smask = mask << shift;
-+
-+	cf = (cf & ~smask) | ((value & mask) << shift);
-+	if (put_dbe(cf, (u32 *) addr))
-+		return PCIBIOS_DEVICE_NOT_FOUND;
-+
-+	return PCIBIOS_SUCCESSFUL;
-+}
-+
-+static int pci_write_config(struct pci_bus *bus, unsigned int devfn,
-+	int where, int size, u32 value)
-+{
-+	if (bus->number > 0)
-+		return pci_conf1_write_config(bus, devfn, where, size, value);
-+
-+	return pci_conf0_write_config(bus, devfn, where, size, value);
-+}
-+
-+struct pci_ops bridge_pci_ops = {
-+	.read	= pci_read_config,
-+	.write	= pci_write_config,
-+};
-diff -Naur linux-2.6.17.orig/arch/mips/pci/ops-ddb5074.c linux-2.6.17/arch/mips/pci/ops-ddb5074.c
---- linux-2.6.17.orig/arch/mips/pci/ops-ddb5074.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/pci/ops-ddb5074.c	1969-12-31 16:00:00.000000000 -0800
-@@ -1,271 +0,0 @@
--/*
-- * Copyright 2001 MontaVista Software Inc.
-- * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
-- *
-- * arch/mips/ddb5xxx/ddb5476/pci_ops.c
-- *     Define the pci_ops for DB5477.
-- *
-- * Much of the code is derived from the original DDB5074 port by
-- * Geert Uytterhoeven <geert@sonycom.com>
-- *
-- * This program is free software; you can redistribute  it and/or modify it
-- * under  the terms of  the GNU General  Public License as published by the
-- * Free Software Foundation;  either version 2 of the  License, or (at your
-- * option) any later version.
-- *
-- */
--#include <linux/pci.h>
--#include <linux/kernel.h>
--#include <linux/types.h>
--
--#include <asm/addrspace.h>
--#include <asm/debug.h>
--
--#include <asm/ddb5xxx/ddb5xxx.h>
--
--/*
-- * config_swap structure records what set of pdar/pmr are used
-- * to access pci config space.  It also provides a place hold the
-- * original values for future restoring.
-- */
--struct pci_config_swap {
--	u32 pdar;
--	u32 pmr;
--	u32 config_base;
--	u32 config_size;
--	u32 pdar_backup;
--	u32 pmr_backup;
--};
--
--/*
-- * On DDB5476, we have one set of swap registers
-- */
--struct pci_config_swap ext_pci_swap = {
--	DDB_PCIW0,
--	DDB_PCIINIT0,
--	DDB_PCI_CONFIG_BASE,
--	DDB_PCI_CONFIG_SIZE
--};
--
--static int pci_config_workaround = 1;
--
--/*
-- * access config space
-- */
--static inline u32 ddb_access_config_base(struct pci_config_swap *swap, u32 bus,	/* 0 means top level bus */
--					 u32 slot_num)
--{
--	u32 pci_addr = 0;
--	u32 pciinit_offset = 0;
--	u32 virt_addr = swap->config_base;
--	u32 option;
--
--	if (pci_config_workaround) {
--		if (slot_num == 5)
--			slot_num = 14;
--	} else {
--		if (slot_num == 5)
--			return DDB_BASE + DDB_PCI_BASE;
--	}
--
--	/* minimum pdar (window) size is 2MB */
--	db_assert(swap->config_size >= (2 << 20));
--
--	db_assert(slot_num < (1 << 5));
--	db_assert(bus < (1 << 8));
--
--	/* backup registers */
--	swap->pdar_backup = ddb_in32(swap->pdar);
--	swap->pmr_backup = ddb_in32(swap->pmr);
--
--	/* set the pdar (pci window) register */
--	ddb_set_pdar(swap->pdar, swap->config_base, swap->config_size, 32,	/* 32 bit wide */
--		     0,		/* not on local memory bus */
--		     0);	/* not visible from PCI bus (N/A) */
--
--	/*
--	 * calcuate the absolute pci config addr;
--	 * according to the spec, we start scanning from adr:11 (0x800)
--	 */
--	if (bus == 0) {
--		/* type 0 config */
--		pci_addr = 0x00040000 << slot_num;
--	} else {
--		/* type 1 config */
--		pci_addr = 0x00040000 << slot_num;
--		panic
--		    ("ddb_access_config_base: we don't support type 1 config Yet");
--	}
--
--	/*
--	 * if pci_addr is less than pci config window size,  we set
--	 * pciinit_offset to 0 and adjust the virt_address.
--	 * Otherwise we will try to adjust pciinit_offset.
--	 */
--	if (pci_addr < swap->config_size) {
--		virt_addr = KSEG1ADDR(swap->config_base + pci_addr);
--		pciinit_offset = 0;
--	} else {
--		db_assert((pci_addr & (swap->config_size - 1)) == 0);
--		virt_addr = KSEG1ADDR(swap->config_base);
--		pciinit_offset = pci_addr;
--	}
--
--	/* set the pmr register */
--	option = DDB_PCI_ACCESS_32;
--	if (bus != 0)
--		option |= DDB_PCI_CFGTYPE1;
--	ddb_set_pmr(swap->pmr, DDB_PCICMD_CFG, pciinit_offset, option);
--
--	return virt_addr;
--}
--
--static inline void ddb_close_config_base(struct pci_config_swap *swap)
--{
--	ddb_out32(swap->pdar, swap->pdar_backup);
--	ddb_out32(swap->pmr, swap->pmr_backup);
--}
--
--static int read_config_dword(struct pci_config_swap *swap,
--			     struct pci_dev *dev, u32 where, u32 * val)
--{
--	u32 bus, slot_num, func_num;
--	u32 base;
--
--	db_assert((where & 3) == 0);
--	db_assert(where < (1 << 8));
--
--	/* check if the bus is top-level */
--	if (dev->bus->parent != NULL) {
--		bus = dev->bus->number;
--		db_assert(bus != 0);
--	} else {
--		bus = 0;
--	}
--
--	slot_num = PCI_SLOT(dev->devfn);
--	func_num = PCI_FUNC(dev->devfn);
--	base = ddb_access_config_base(swap, bus, slot_num);
--	*val = *(volatile u32 *) (base + (func_num << 8) + where);
--	ddb_close_config_base(swap);
--	return PCIBIOS_SUCCESSFUL;
--}
--
--static int read_config_word(struct pci_config_swap *swap,
--			    struct pci_dev *dev, u32 where, u16 * val)
--{
--	int status;
--	u32 result;
--
--	db_assert((where & 1) == 0);
--
--	status = read_config_dword(swap, dev, where & ~3, &result);
--	if (where & 2)
--		result >>= 16;
--	*val = result & 0xffff;
--	return status;
--}
--
--static int read_config_byte(struct pci_config_swap *swap,
--			    struct pci_dev *dev, u32 where, u8 * val)
--{
--	int status;
--	u32 result;
--
--	status = read_config_dword(swap, dev, where & ~3, &result);
--	if (where & 1)
--		result >>= 8;
--	if (where & 2)
--		result >>= 16;
--	*val = result & 0xff;
--	return status;
--}
--
--static int write_config_dword(struct pci_config_swap *swap,
--			      struct pci_dev *dev, u32 where, u32 val)
--{
--	u32 bus, slot_num, func_num;
--	u32 base;
--
--	db_assert((where & 3) == 0);
--	db_assert(where < (1 << 8));
--
--	/* check if the bus is top-level */
--	if (dev->bus->parent != NULL) {
--		bus = dev->bus->number;
--		db_assert(bus != 0);
--	} else {
--		bus = 0;
--	}
--
--	slot_num = PCI_SLOT(dev->devfn);
--	func_num = PCI_FUNC(dev->devfn);
--	base = ddb_access_config_base(swap, bus, slot_num);
--	*(volatile u32 *) (base + (func_num << 8) + where) = val;
--	ddb_close_config_base(swap);
--	return PCIBIOS_SUCCESSFUL;
--}
--
--static int write_config_word(struct pci_config_swap *swap,
--			     struct pci_dev *dev, u32 where, u16 val)
--{
--	int status, shift = 0;
--	u32 result;
--
--	db_assert((where & 1) == 0);
--
--	status = read_config_dword(swap, dev, where & ~3, &result);
--	if (status != PCIBIOS_SUCCESSFUL)
--		return status;
--
--	if (where & 2)
--		shift += 16;
--	result &= ~(0xffff << shift);
--	result |= val << shift;
--	return write_config_dword(swap, dev, where & ~3, result);
--}
--
--static int write_config_byte(struct pci_config_swap *swap,
--			     struct pci_dev *dev, u32 where, u8 val)
--{
--	int status, shift = 0;
--	u32 result;
--
--	status = read_config_dword(swap, dev, where & ~3, &result);
--	if (status != PCIBIOS_SUCCESSFUL)
--		return status;
--
--	if (where & 2)
--		shift += 16;
--	if (where & 1)
--		shift += 8;
--	result &= ~(0xff << shift);
--	result |= val << shift;
--	return write_config_dword(swap, dev, where & ~3, result);
--}
--
--#define	MAKE_PCI_OPS(prefix, rw, unitname, unittype, pciswap) \
--static int prefix##_##rw##_config_##unitname(struct pci_dev *dev, int where, unittype val) \
--{ \
--     return rw##_config_##unitname(pciswap, \
--                                   dev, \
--                                   where, \
--                                   val); \
--}
--
--MAKE_PCI_OPS(extpci, read, byte, u8 *, &ext_pci_swap)
--    MAKE_PCI_OPS(extpci, read, word, u16 *, &ext_pci_swap)
--    MAKE_PCI_OPS(extpci, read, dword, u32 *, &ext_pci_swap)
--
--    MAKE_PCI_OPS(extpci, write, byte, u8, &ext_pci_swap)
--    MAKE_PCI_OPS(extpci, write, word, u16, &ext_pci_swap)
--    MAKE_PCI_OPS(extpci, write, dword, u32, &ext_pci_swap)
--
--struct pci_ops ddb5476_ext_pci_ops = {
--	extpci_read_config_byte,
--	extpci_read_config_word,
--	extpci_read_config_dword,
--	extpci_write_config_byte,
--	extpci_write_config_word,
--	extpci_write_config_dword
--};
-diff -Naur linux-2.6.17.orig/arch/mips/pci/ops-ddb5476.c linux-2.6.17/arch/mips/pci/ops-ddb5476.c
---- linux-2.6.17.orig/arch/mips/pci/ops-ddb5476.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/pci/ops-ddb5476.c	1969-12-31 16:00:00.000000000 -0800
-@@ -1,286 +0,0 @@
--/*
-- * Copyright 2001 MontaVista Software Inc.
-- * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
-- *
-- * arch/mips/ddb5xxx/ddb5476/pci_ops.c
-- *     Define the pci_ops for DB5477.
-- *
-- * Much of the code is derived from the original DDB5074 port by
-- * Geert Uytterhoeven <geert@sonycom.com>
-- *
-- * This program is free software; you can redistribute  it and/or modify it
-- * under  the terms of  the GNU General  Public License as published by the
-- * Free Software Foundation;  either version 2 of the  License, or (at your
-- * option) any later version.
-- *
-- */
--#include <linux/pci.h>
--#include <linux/kernel.h>
--#include <linux/types.h>
--
--#include <asm/addrspace.h>
--#include <asm/debug.h>
--
--#include <asm/ddb5xxx/ddb5xxx.h>
--
--/*
-- * config_swap structure records what set of pdar/pmr are used
-- * to access pci config space.  It also provides a place hold the
-- * original values for future restoring.
-- */
--struct pci_config_swap {
--	u32 pdar;
--	u32 pmr;
--	u32 config_base;
--	u32 config_size;
--	u32 pdar_backup;
--	u32 pmr_backup;
--};
--
--/*
-- * On DDB5476, we have one set of swap registers
-- */
--struct pci_config_swap ext_pci_swap = {
--	DDB_PCIW0,
--	DDB_PCIINIT0,
--	DDB_PCI_CONFIG_BASE,
--	DDB_PCI_CONFIG_SIZE
--};
--
--static int pci_config_workaround = 1;
--
--/*
-- * access config space
-- */
--static inline u32 ddb_access_config_base(struct pci_config_swap *swap, u32 bus,	/* 0 means top level bus */
--					 u32 slot_num)
--{
--	u32 pci_addr = 0;
--	u32 pciinit_offset = 0;
--	u32 virt_addr = swap->config_base;
--	u32 option;
--
--	if (pci_config_workaround) {
--		/* [jsun] work around Vrc5476 controller itself, returnning
--		 * slot 0 essentially makes vrc5476 invisible
--		 */
--		if (slot_num == 12)
--			slot_num = 0;
--
--#if 0
--		/* BUG : skip P2P bridge for now */
--		if (slot_num == 5)
--			slot_num = 0;
--#endif
--
--	} else {
--		/* now we have to be hornest, returning the true
--		 * PCI config headers for vrc5476
--		 */
--		if (slot_num == 12) {
--			swap->pdar_backup = ddb_in32(swap->pdar);
--			swap->pmr_backup = ddb_in32(swap->pmr);
--			return DDB_BASE + DDB_PCI_BASE;
--		}
--	}
--
--	/* minimum pdar (window) size is 2MB */
--	db_assert(swap->config_size >= (2 << 20));
--
--	db_assert(slot_num < (1 << 5));
--	db_assert(bus < (1 << 8));
--
--	/* backup registers */
--	swap->pdar_backup = ddb_in32(swap->pdar);
--	swap->pmr_backup = ddb_in32(swap->pmr);
--
--	/* set the pdar (pci window) register */
--	ddb_set_pdar(swap->pdar, swap->config_base, swap->config_size, 32,	/* 32 bit wide */
--		     0,		/* not on local memory bus */
--		     0);	/* not visible from PCI bus (N/A) */
--
--	/*
--	 * calcuate the absolute pci config addr;
--	 * according to the spec, we start scanning from adr:11 (0x800)
--	 */
--	if (bus == 0) {
--		/* type 0 config */
--		pci_addr = 0x800 << slot_num;
--	} else {
--		/* type 1 config */
--		pci_addr = (bus << 16) | (slot_num << 11);
--		/* panic("ddb_access_config_base: we don't support type 1 config Yet"); */
--	}
--
--	/*
--	 * if pci_addr is less than pci config window size,  we set
--	 * pciinit_offset to 0 and adjust the virt_address.
--	 * Otherwise we will try to adjust pciinit_offset.
--	 */
--	if (pci_addr < swap->config_size) {
--		virt_addr = KSEG1ADDR(swap->config_base + pci_addr);
--		pciinit_offset = 0;
--	} else {
--		db_assert((pci_addr & (swap->config_size - 1)) == 0);
--		virt_addr = KSEG1ADDR(swap->config_base);
--		pciinit_offset = pci_addr;
--	}
--
--	/* set the pmr register */
--	option = DDB_PCI_ACCESS_32;
--	if (bus != 0)
--		option |= DDB_PCI_CFGTYPE1;
--	ddb_set_pmr(swap->pmr, DDB_PCICMD_CFG, pciinit_offset, option);
--
--	return virt_addr;
--}
--
--static inline void ddb_close_config_base(struct pci_config_swap *swap)
--{
--	ddb_out32(swap->pdar, swap->pdar_backup);
--	ddb_out32(swap->pmr, swap->pmr_backup);
--}
--
--static int read_config_dword(struct pci_config_swap *swap,
--			     struct pci_dev *dev, u32 where, u32 * val)
--{
--	u32 bus, slot_num, func_num;
--	u32 base;
--
--	db_assert((where & 3) == 0);
--	db_assert(where < (1 << 8));
--
--	/* check if the bus is top-level */
--	if (dev->bus->parent != NULL) {
--		bus = dev->bus->number;
--		db_assert(bus != 0);
--	} else {
--		bus = 0;
--	}
--
--	slot_num = PCI_SLOT(dev->devfn);
--	func_num = PCI_FUNC(dev->devfn);
--	base = ddb_access_config_base(swap, bus, slot_num);
--	*val = *(volatile u32 *) (base + (func_num << 8) + where);
--	ddb_close_config_base(swap);
--	return PCIBIOS_SUCCESSFUL;
--}
--
--static int read_config_word(struct pci_config_swap *swap,
--			    struct pci_dev *dev, u32 where, u16 * val)
--{
--	int status;
--	u32 result;
--
--	db_assert((where & 1) == 0);
--
--	status = read_config_dword(swap, dev, where & ~3, &result);
--	if (where & 2)
--		result >>= 16;
--	*val = result & 0xffff;
--	return status;
--}
--
--static int read_config_byte(struct pci_config_swap *swap,
--			    struct pci_dev *dev, u32 where, u8 * val)
--{
--	int status;
--	u32 result;
--
--	status = read_config_dword(swap, dev, where & ~3, &result);
--	if (where & 1)
--		result >>= 8;
--	if (where & 2)
--		result >>= 16;
--	*val = result & 0xff;
--	return status;
--}
--
--static int write_config_dword(struct pci_config_swap *swap,
--			      struct pci_dev *dev, u32 where, u32 val)
--{
--	u32 bus, slot_num, func_num;
--	u32 base;
--
--	db_assert((where & 3) == 0);
--	db_assert(where < (1 << 8));
--
--	/* check if the bus is top-level */
--	if (dev->bus->parent != NULL) {
--		bus = dev->bus->number;
--		db_assert(bus != 0);
--	} else {
--		bus = 0;
--	}
--
--	slot_num = PCI_SLOT(dev->devfn);
--	func_num = PCI_FUNC(dev->devfn);
--	base = ddb_access_config_base(swap, bus, slot_num);
--	*(volatile u32 *) (base + (func_num << 8) + where) = val;
--	ddb_close_config_base(swap);
--	return PCIBIOS_SUCCESSFUL;
--}
--
--static int write_config_word(struct pci_config_swap *swap,
--			     struct pci_dev *dev, u32 where, u16 val)
--{
--	int status, shift = 0;
--	u32 result;
--
--	db_assert((where & 1) == 0);
--
--	status = read_config_dword(swap, dev, where & ~3, &result);
--	if (status != PCIBIOS_SUCCESSFUL)
--		return status;
--
--	if (where & 2)
--		shift += 16;
--	result &= ~(0xffff << shift);
--	result |= val << shift;
--	return write_config_dword(swap, dev, where & ~3, result);
--}
--
--static int write_config_byte(struct pci_config_swap *swap,
--			     struct pci_dev *dev, u32 where, u8 val)
--{
--	int status, shift = 0;
--	u32 result;
--
--	status = read_config_dword(swap, dev, where & ~3, &result);
--	if (status != PCIBIOS_SUCCESSFUL)
--		return status;
--
--	if (where & 2)
--		shift += 16;
--	if (where & 1)
--		shift += 8;
--	result &= ~(0xff << shift);
--	result |= val << shift;
--	return write_config_dword(swap, dev, where & ~3, result);
--}
--
--#define	MAKE_PCI_OPS(prefix, rw, unitname, unittype, pciswap) \
--static int prefix##_##rw##_config_##unitname(struct pci_dev *dev, int where, unittype val) \
--{ \
--     return rw##_config_##unitname(pciswap, \
--                                   dev, \
--                                   where, \
--                                   val); \
--}
--
--MAKE_PCI_OPS(extpci, read, byte, u8 *, &ext_pci_swap)
--    MAKE_PCI_OPS(extpci, read, word, u16 *, &ext_pci_swap)
--    MAKE_PCI_OPS(extpci, read, dword, u32 *, &ext_pci_swap)
--
--    MAKE_PCI_OPS(extpci, write, byte, u8, &ext_pci_swap)
--    MAKE_PCI_OPS(extpci, write, word, u16, &ext_pci_swap)
--    MAKE_PCI_OPS(extpci, write, dword, u32, &ext_pci_swap)
--
--struct pci_ops ddb5476_ext_pci_ops = {
--	extpci_read_config_byte,
--	extpci_read_config_word,
--	extpci_read_config_dword,
--	extpci_write_config_byte,
--	extpci_write_config_word,
--	extpci_write_config_dword
--};
-diff -Naur linux-2.6.17.orig/arch/mips/pci/ops-emma2rh.c linux-2.6.17/arch/mips/pci/ops-emma2rh.c
---- linux-2.6.17.orig/arch/mips/pci/ops-emma2rh.c	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/arch/mips/pci/ops-emma2rh.c	2006-06-19 18:16:13.000000000 -0700
-@@ -0,0 +1,186 @@
-+/*
-+ *  arch/mips/pci/ops-emma2rh.c
-+ *      This file defines the PCI operation for EMMA2RH.
-+ *
-+ *  Copyright (C) NEC Electronics Corporation 2004-2006
-+ *
-+ *  This file is based on the arch/mips/pci/ops-vr41xx.c
-+ *
-+ *	Copyright 2001 MontaVista Software Inc.
-+ *
-+ *  This program is free software; you can redistribute it and/or modify
-+ *  it under the terms of the GNU General Public License as published by
-+ *  the Free Software Foundation; either version 2 of the License, or
-+ *  (at your option) any later version.
-+ *
-+ *  This program is distributed in the hope that it will be useful,
-+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ *  GNU General Public License for more details.
-+ *
-+ *  You should have received a copy of the GNU General Public License
-+ *  along with this program; if not, write to the Free Software
-+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-+ */
-+
-+#include <linux/config.h>
-+#include <linux/pci.h>
-+#include <linux/kernel.h>
-+#include <linux/types.h>
-+
-+#include <asm/addrspace.h>
-+#include <asm/debug.h>
-+
-+#include <asm/emma2rh/emma2rh.h>
-+
-+#define RTABORT (0x1<<9)
-+#define RMABORT (0x1<<10)
-+#define EMMA2RH_PCI_SLOT_NUM 9	/* 0000:09.0 is final PCI device */
-+
-+/*
-+ * access config space
-+ */
-+
-+static int check_args(struct pci_bus *bus, u32 devfn, u32 * bus_num)
-+{
-+	/* check if the bus is top-level */
-+	if (bus->parent != NULL) {
-+		*bus_num = bus->number;
-+		db_assert(bus_num != 0);
-+	} else
-+		*bus_num = 0;
-+
-+	if (*bus_num == 0) {
-+		/* Type 0 */
-+		if (PCI_SLOT(devfn) >= 10)
-+			return PCIBIOS_DEVICE_NOT_FOUND;
-+	} else {
-+		/* Type 1 */
-+		if ((*bus_num >= 64) || (PCI_SLOT(devfn) >= 16))
-+			return PCIBIOS_DEVICE_NOT_FOUND;
-+	}
-+	return 0;
-+}
-+
-+static inline int set_pci_configuration_address(unsigned char bus_num,
-+						unsigned int devfn, int where)
-+{
-+	u32 config_win0;
-+
-+	emma2rh_out32(EMMA2RH_PCI_INT, ~RMABORT);
-+	if (bus_num == 0)
-+		/*
-+		 * Type 0 configuration
-+		 */
-+		config_win0 = (1 << (22 + PCI_SLOT(devfn))) | (5 << 9);
-+	else
-+		/*
-+		 * Type 1 configuration
-+		 */
-+		config_win0 = (bus_num << 26) | (PCI_SLOT(devfn) << 22) |
-+		    (1 << 15) | (5 << 9);
-+
-+	emma2rh_out32(EMMA2RH_PCI_IWIN0_CTR, config_win0);
-+
-+	return 0;
-+}
-+
-+static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where,
-+			   int size, uint32_t * val)
-+{
-+	u32 bus_num;
-+	u32 base = KSEG1ADDR(EMMA2RH_PCI_CONFIG_BASE);
-+	u32 backup_win0;
-+	u32 data;
-+
-+	*val = 0xffffffffU;
-+
-+	if (check_args(bus, devfn, &bus_num) == PCIBIOS_DEVICE_NOT_FOUND)
-+		return PCIBIOS_DEVICE_NOT_FOUND;
-+
-+	backup_win0 = emma2rh_in32(EMMA2RH_PCI_IWIN0_CTR);
-+
-+	if (set_pci_configuration_address(bus_num, devfn, where) < 0)
-+		return PCIBIOS_DEVICE_NOT_FOUND;
-+
-+	data =
-+	    *(volatile u32 *)(base + (PCI_FUNC(devfn) << 8) +
-+			      (where & 0xfffffffc));
-+
-+	switch (size) {
-+	case 1:
-+		*val = (data >> ((where & 3) << 3)) & 0xffU;
-+		break;
-+	case 2:
-+		*val = (data >> ((where & 2) << 3)) & 0xffffU;
-+		break;
-+	case 4:
-+		*val = data;
-+		break;
-+	default:
-+		emma2rh_out32(EMMA2RH_PCI_IWIN0_CTR, backup_win0);
-+		return PCIBIOS_FUNC_NOT_SUPPORTED;
-+	}
-+
-+	emma2rh_out32(EMMA2RH_PCI_IWIN0_CTR, backup_win0);
-+
-+	if (emma2rh_in32(EMMA2RH_PCI_INT) & RMABORT)
-+		return PCIBIOS_DEVICE_NOT_FOUND;
-+
-+	return PCIBIOS_SUCCESSFUL;
-+}
-+
-+static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where,
-+			    int size, u32 val)
-+{
-+	u32 bus_num;
-+	u32 base = KSEG1ADDR(EMMA2RH_PCI_CONFIG_BASE);
-+	u32 backup_win0;
-+	u32 data;
-+	int shift;
-+
-+	if (check_args(bus, devfn, &bus_num) == PCIBIOS_DEVICE_NOT_FOUND)
-+		return PCIBIOS_DEVICE_NOT_FOUND;
-+
-+	backup_win0 = emma2rh_in32(EMMA2RH_PCI_IWIN0_CTR);
-+
-+	if (set_pci_configuration_address(bus_num, devfn, where) < 0)
-+		return PCIBIOS_DEVICE_NOT_FOUND;
-+
-+	/* read modify write */
-+	data =
-+	    *(volatile u32 *)(base + (PCI_FUNC(devfn) << 8) +
-+			      (where & 0xfffffffc));
-+
-+	switch (size) {
-+	case 1:
-+		shift = (where & 3) << 3;
-+		data &= ~(0xffU << shift);
-+		data |= ((val & 0xffU) << shift);
-+		break;
-+	case 2:
-+		shift = (where & 2) << 3;
-+		data &= ~(0xffffU << shift);
-+		data |= ((val & 0xffffU) << shift);
-+		break;
-+	case 4:
-+		data = val;
-+		break;
-+	default:
-+		emma2rh_out32(EMMA2RH_PCI_IWIN0_CTR, backup_win0);
-+		return PCIBIOS_FUNC_NOT_SUPPORTED;
-+	}
-+	*(volatile u32 *)(base + (PCI_FUNC(devfn) << 8) +
-+			  (where & 0xfffffffc)) = data;
-+
-+	emma2rh_out32(EMMA2RH_PCI_IWIN0_CTR, backup_win0);
-+	if (emma2rh_in32(EMMA2RH_PCI_INT) & RMABORT)
-+		return PCIBIOS_DEVICE_NOT_FOUND;
-+
-+	return PCIBIOS_SUCCESSFUL;
-+}
-+
-+struct pci_ops emma2rh_pci_ops = {
-+	.read = pci_config_read,
-+	.write = pci_config_write,
-+};
-diff -Naur linux-2.6.17.orig/arch/mips/pci/ops-it8172.c linux-2.6.17/arch/mips/pci/ops-it8172.c
---- linux-2.6.17.orig/arch/mips/pci/ops-it8172.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/pci/ops-it8172.c	2006-06-19 18:16:13.000000000 -0700
-@@ -50,30 +50,28 @@
- static struct resource pci_mem_resource_1;
- 
- static struct resource pci_io_resource = {
--	"io pci IO space",
--	0x14018000,
--	0x17FFFFFF,
--	IORESOURCE_IO
-+	.start	= 0x14018000,
-+	.end	= 0x17FFFFFF,
-+	.name	= "io pci IO space",
-+	.flags	= IORESOURCE_IO
- };
- 
- static struct resource pci_mem_resource_0 = {
--	"ext pci memory space 0/1",
--	0x10101000,
--	0x13FFFFFF,
--	IORESOURCE_MEM,
--	&pci_mem_resource_0,
--	NULL,
--	&pci_mem_resource_1
-+	.start	= 0x10101000,
-+	.end	= 0x13FFFFFF,
-+	.name	= "ext pci memory space 0/1",
-+	.flags	= IORESOURCE_MEM,
-+	.parent	= &pci_mem_resource_0,
-+	.sibling = NULL,
-+	.child	= &pci_mem_resource_1
- };
- 
- static struct resource pci_mem_resource_1 = {
--	"ext pci memory space 2/3",
--	0x1A000000,
--	0x1FBFFFFF,
--	IORESOURCE_MEM,
--	&pci_mem_resource_0,
--	NULL,
--	NULL
-+	.start	= 0x1A000000,
-+	.end	= 0x1FBFFFFF,
-+	.name	= "ext pci memory space 2/3",
-+	.flags	= IORESOURCE_MEM,
-+	.parent	= &pci_mem_resource_0
- };
- 
- extern struct pci_ops it8172_pci_ops;
-diff -Naur linux-2.6.17.orig/arch/mips/pci/ops-sni.c linux-2.6.17/arch/mips/pci/ops-sni.c
---- linux-2.6.17.orig/arch/mips/pci/ops-sni.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/pci/ops-sni.c	2006-06-19 18:16:13.000000000 -0700
-@@ -47,13 +47,13 @@
- 
- 	switch (size) {
- 	case 1:
--		*val = *(volatile  u8 *) (PCIMT_CONFIG_DATA + (reg & 3));
-+		*val = inb(PCIMT_CONFIG_DATA + (reg & 3));
- 		break;
- 	case 2:
--		*val = *(volatile u16 *) (PCIMT_CONFIG_DATA + (reg & 2));
-+		*val = inw(PCIMT_CONFIG_DATA + (reg & 2));
- 		break;
- 	case 4:
--		*val = *(volatile u32 *) PCIMT_CONFIG_DATA;
-+		*val = inl(PCIMT_CONFIG_DATA);
- 		break;
- 	}
- 
-@@ -70,13 +70,13 @@
- 
- 	switch (size) {
- 	case 1:
--		*(volatile  u8 *) (PCIMT_CONFIG_DATA + (reg & 3)) = val;
-+		outb (val, PCIMT_CONFIG_DATA + (reg & 3));
- 		break;
- 	case 2:
--		*(volatile u16 *) (PCIMT_CONFIG_DATA + (reg & 2)) = val;
-+		outw (val, PCIMT_CONFIG_DATA + (reg & 2));
- 		break;
- 	case 4:
--		*(volatile u32 *) PCIMT_CONFIG_DATA = val;
-+		outl (val, PCIMT_CONFIG_DATA);
- 		break;
- 	}
- 
-diff -Naur linux-2.6.17.orig/arch/mips/pci/ops-titan.c linux-2.6.17/arch/mips/pci/ops-titan.c
---- linux-2.6.17.orig/arch/mips/pci/ops-titan.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/pci/ops-titan.c	2006-06-19 18:16:13.000000000 -0700
-@@ -26,8 +26,19 @@
- #include <linux/pci.h>
- #include <linux/kernel.h>
- 
--#include <asm/titan_dep.h>
-+#include <asm/pci.h>
-+#include <asm/io.h>
-+#include <asm/rm9k-ocd.h>
- 
-+/*
-+ * PCI specific defines
-+ */
-+#define	TITAN_PCI_0_CONFIG_ADDRESS	0x780
-+#define	TITAN_PCI_0_CONFIG_DATA		0x784
-+
-+/*
-+ * Titan PCI Config Read Byte
-+ */
- static int titan_read_config(struct pci_bus *bus, unsigned int devfn, int reg,
- 	int size, u32 * val)
- {
-@@ -43,8 +54,8 @@
- 
- 
- 	/* start the configuration cycle */
--	TITAN_WRITE(TITAN_PCI_0_CONFIG_ADDRESS, address);
--	tmp = TITAN_READ(TITAN_PCI_0_CONFIG_DATA) >> ((reg & 3) << 3);
-+	ocd_writel(address, TITAN_PCI_0_CONFIG_ADDRESS);
-+	tmp = ocd_readl(TITAN_PCI_0_CONFIG_DATA) >> ((reg & 3) << 3);
- 
- 	switch (size) {
- 	case 1:
-@@ -71,20 +82,20 @@
- 		(reg & 0xfc) | 0x80000000;
- 
- 	/* start the configuration cycle */
--	TITAN_WRITE(TITAN_PCI_0_CONFIG_ADDRESS, address);
-+	ocd_writel(address, TITAN_PCI_0_CONFIG_ADDRESS);
- 
- 	/* write the data */
- 	switch (size) {
- 	case 1:
--		TITAN_WRITE_8(TITAN_PCI_0_CONFIG_DATA + (~reg & 0x3), val);
-+		ocd_writeb(val, TITAN_PCI_0_CONFIG_DATA + (~reg & 0x3));
- 		break;
- 
- 	case 2:
--		TITAN_WRITE_16(TITAN_PCI_0_CONFIG_DATA + (~reg & 0x2), val);
-+		ocd_writew(val, TITAN_PCI_0_CONFIG_DATA + (~reg & 0x2));
- 		break;
- 
- 	case 4:
--		TITAN_WRITE(TITAN_PCI_0_CONFIG_DATA, val);
-+		ocd_writel(val, TITAN_PCI_0_CONFIG_DATA);
- 		break;
- 	}
- 
-diff -Naur linux-2.6.17.orig/arch/mips/pci/pci.c linux-2.6.17/arch/mips/pci/pci.c
---- linux-2.6.17.orig/arch/mips/pci/pci.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/pci/pci.c	2006-06-19 18:16:13.000000000 -0700
-@@ -76,11 +76,6 @@
- 	res->start = start;
- }
- 
--struct pci_controller * __init alloc_pci_controller(void)
--{
--	return alloc_bootmem(sizeof(struct pci_controller));
--}
--
- void __init register_pci_controller(struct pci_controller *hose)
- {
- 	*hose_tail = hose;
-diff -Naur linux-2.6.17.orig/arch/mips/pci/pci-ddb5074.c linux-2.6.17/arch/mips/pci/pci-ddb5074.c
---- linux-2.6.17.orig/arch/mips/pci/pci-ddb5074.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/pci/pci-ddb5074.c	1969-12-31 16:00:00.000000000 -0800
-@@ -1,79 +0,0 @@
--#include <linux/kernel.h>
--#include <linux/init.h>
--#include <linux/types.h>
--#include <linux/pci.h>
--
--#include <asm/debug.h>
--
--#include <asm/ddb5xxx/ddb5xxx.h>
--
--static struct resource extpci_io_resource = {
--	"pci IO space",
--	0x1000,			/* leave some room for ISA bus */
--	DDB_PCI_IO_SIZE - 1,
--	IORESOURCE_IO
--};
--
--static struct resource extpci_mem_resource = {
--	"pci memory space",
--	DDB_PCI_MEM_BASE + 0x00100000,	/* leave 1 MB for RTC */
--	DDB_PCI_MEM_BASE + DDB_PCI_MEM_SIZE - 1,
--	IORESOURCE_MEM
--};
--
--extern struct pci_ops ddb5476_ext_pci_ops;
--
--struct pci_controller ddb5476_controller = {
--	.pci_ops	= &ddb5476_ext_pci_ops,
--	.io_resource	= &extpci_io_resource,
--	.mem_resource	= &extpci_mem_resource,
--};
--
--#define     PCI_EXT_INTA        8
--#define     PCI_EXT_INTB        9
--#define     PCI_EXT_INTC        10
--#define     PCI_EXT_INTD        11
--#define     PCI_EXT_INTE        12
--
--#define     MAX_SLOT_NUM        14
--
--static unsigned char irq_map[MAX_SLOT_NUM] = {
--  [ 0] = nile4_to_irq(PCI_EXT_INTE),
--  [ 1] = nile4_to_irq(PCI_EXT_INTA),
--  [ 2] = nile4_to_irq(PCI_EXT_INTA),
--  [ 3] = nile4_to_irq(PCI_EXT_INTB),
--  [ 4] = nile4_to_irq(PCI_EXT_INTC),
--  [ 5] = nile4_to_irq(NILE4_INT_UART),
--  [10] = nile4_to_irq(PCI_EXT_INTE),
--  [13] = nile4_to_irq(PCI_EXT_INTE),
--};
--
--int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
--{
--	return irq_map[slot];
--}
--
--/* Do platform specific device initialization at pci_enable_device() time */
--int pcibios_plat_dev_init(struct pci_dev *dev)
--{
--	return 0;
--}
--
--void __init ddb_pci_reset_bus(void)
--{
--	u32 temp;
--
--	/*
--	 * I am not sure about the "official" procedure, the following
--	 * steps work as far as I know:
--	 * We first set PCI cold reset bit (bit 31) in PCICTRL-H.
--	 * Then we clear the PCI warm reset bit (bit 30) to 0 in PCICTRL-H.
--	 * The same is true for both PCI channels.
--	 */
--	temp = ddb_in32(DDB_PCICTRL + 4);
--	temp |= 0x80000000;
--	ddb_out32(DDB_PCICTRL + 4, temp);
--	temp &= ~0xc0000000;
--	ddb_out32(DDB_PCICTRL + 4, temp);
--
--}
-diff -Naur linux-2.6.17.orig/arch/mips/pci/pci-ddb5476.c linux-2.6.17/arch/mips/pci/pci-ddb5476.c
---- linux-2.6.17.orig/arch/mips/pci/pci-ddb5476.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/pci/pci-ddb5476.c	1969-12-31 16:00:00.000000000 -0800
-@@ -1,93 +0,0 @@
--#include <linux/kernel.h>
--#include <linux/init.h>
--#include <linux/types.h>
--#include <linux/pci.h>
--
--#include <asm/debug.h>
--
--#include <asm/ddb5xxx/ddb5xxx.h>
--
--static struct resource extpci_io_resource = {
--	"pci IO space",
--	0x1000,			/* leave some room for ISA bus */
--	DDB_PCI_IO_SIZE - 1,
--	IORESOURCE_IO
--};
--
--static struct resource extpci_mem_resource = {
--	"pci memory space",
--	DDB_PCI_MEM_BASE + 0x00100000,	/* leave 1 MB for RTC */
--	DDB_PCI_MEM_BASE + DDB_PCI_MEM_SIZE - 1,
--	IORESOURCE_MEM
--};
--
--extern struct pci_ops ddb5476_ext_pci_ops;
--
--struct pci_controller ddb5476_controller = {
--	.pci_ops	= &ddb5476_ext_pci_ops,
--	.io_resource	= &extpci_io_resource,
--	.mem_resource	= &extpci_mem_resource
--};
--
--
--/*
-- * we fix up irqs based on the slot number.
-- * The first entry is at AD:11.
-- *
-- * This does not work for devices on sub-buses yet.
-- */
--
--/*
-- * temporary
-- */
--
--#define		PCI_EXT_INTA		8
--#define		PCI_EXT_INTB		9
--#define		PCI_EXT_INTC		10
--#define		PCI_EXT_INTD		11
--#define		PCI_EXT_INTE		12
--
--/*
-- * based on ddb5477 manual page 11
-- */
--#define		MAX_SLOT_NUM		21
--static unsigned char irq_map[MAX_SLOT_NUM] = {
-- [ 2] = 9,				/* AD:13	USB		*/
-- [ 3] = 10,				/* AD:14	PMU		*/
-- [ 5] = 0,				/* AD:16 	P2P bridge	*/
-- [ 6] = nile4_to_irq(PCI_EXT_INTB),	/* AD:17			*/
-- [ 7] =	nile4_to_irq(PCI_EXT_INTC),	/* AD:18			*/
-- [ 8] = nile4_to_irq(PCI_EXT_INTD),	/* AD:19			*/
-- [ 9] = nile4_to_irq(PCI_EXT_INTA),	/* AD:20			*/
-- [13] = 14,				/* AD:24 HD controller, M5229	*/
--};
--
--int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
--{
--	return irq_map[slot];
--}
--
--/* Do platform specific device initialization at pci_enable_device() time */
--int pcibios_plat_dev_init(struct pci_dev *dev)
--{
--	return 0;
--}
--
--void __init ddb_pci_reset_bus(void)
--{
--	u32 temp;
--
--	/*
--	 * I am not sure about the "official" procedure, the following
--	 * steps work as far as I know:
--	 * We first set PCI cold reset bit (bit 31) in PCICTRL-H.
--	 * Then we clear the PCI warm reset bit (bit 30) to 0 in PCICTRL-H.
--	 * The same is true for both PCI channels.
--	 */
--	temp = ddb_in32(DDB_PCICTRL + 4);
--	temp |= 0x80000000;
--	ddb_out32(DDB_PCICTRL + 4, temp);
--	temp &= ~0xc0000000;
--	ddb_out32(DDB_PCICTRL + 4, temp);
--
--}
-diff -Naur linux-2.6.17.orig/arch/mips/pci/pci-ddb5477.c linux-2.6.17/arch/mips/pci/pci-ddb5477.c
---- linux-2.6.17.orig/arch/mips/pci/pci-ddb5477.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/pci/pci-ddb5477.c	2006-06-19 18:16:13.000000000 -0700
-@@ -22,31 +22,31 @@
- #include <asm/ddb5xxx/ddb5xxx.h>
- 
- static struct resource extpci_io_resource = {
--	"ext pci IO space",
--	DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE + 0x4000,
--	DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI0_IO_SIZE - 1,
--	IORESOURCE_IO
-+	.start	= DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE + 0x4000,
-+	.end	= DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI0_IO_SIZE - 1,
-+	.name	= "ext pci IO space",
-+	.flags	= IORESOURCE_IO
- };
- 
- static struct resource extpci_mem_resource = {
--	"ext pci memory space",
--	DDB_PCI0_MEM_BASE + 0x100000,
--	DDB_PCI0_MEM_BASE + DDB_PCI0_MEM_SIZE - 1,
--	IORESOURCE_MEM
-+	.start	= DDB_PCI0_MEM_BASE + 0x100000,
-+	.end	= DDB_PCI0_MEM_BASE + DDB_PCI0_MEM_SIZE - 1,
-+	.name	= "ext pci memory space",
-+	.flags	= IORESOURCE_MEM
- };
- 
- static struct resource iopci_io_resource = {
--	"io pci IO space",
--	DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE,
--	DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI1_IO_SIZE - 1,
--	IORESOURCE_IO
-+	.start	= DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE,
-+	.end	= DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI1_IO_SIZE - 1,
-+	.name	= "io pci IO space",
-+	.flags	= IORESOURCE_IO
- };
- 
- static struct resource iopci_mem_resource = {
--	"ext pci memory space",
--	DDB_PCI1_MEM_BASE,
--	DDB_PCI1_MEM_BASE + DDB_PCI1_MEM_SIZE - 1,
--	IORESOURCE_MEM
-+	.start	= DDB_PCI1_MEM_BASE,
-+	.end	= DDB_PCI1_MEM_BASE + DDB_PCI1_MEM_SIZE - 1,
-+	.name	= "ext pci memory space",
-+	.flags	= IORESOURCE_MEM
- };
- 
- extern struct pci_ops ddb5477_ext_pci_ops;
-diff -Naur linux-2.6.17.orig/arch/mips/pci/pci-emma2rh.c linux-2.6.17/arch/mips/pci/pci-emma2rh.c
---- linux-2.6.17.orig/arch/mips/pci/pci-emma2rh.c	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/arch/mips/pci/pci-emma2rh.c	2006-06-19 18:16:13.000000000 -0700
-@@ -0,0 +1,90 @@
-+/*
-+ *  arch/mips/pci/pci-emma2rh.c
-+ *      This file defines the PCI configration.
-+ *
-+ *  Copyright (C) NEC Electronics Corporation 2004-2006
-+ *
-+ *  This file is based on the arch/mips/ddb5xxx/ddb5477/pci.c
-+ *
-+ *	Copyright 2001 MontaVista Software Inc.
-+ *
-+ *  This program is free software; you can redistribute it and/or modify
-+ *  it under the terms of the GNU General Public License as published by
-+ *  the Free Software Foundation; either version 2 of the License, or
-+ *  (at your option) any later version.
-+ *
-+ *  This program is distributed in the hope that it will be useful,
-+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ *  GNU General Public License for more details.
-+ *
-+ *  You should have received a copy of the GNU General Public License
-+ *  along with this program; if not, write to the Free Software
-+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-+ */
-+
-+#include <linux/config.h>
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/types.h>
-+#include <linux/pci.h>
-+
-+#include <asm/bootinfo.h>
-+#include <asm/debug.h>
-+
-+#include <asm/emma2rh/emma2rh.h>
-+
-+static struct resource pci_io_resource = {
-+	.name = "pci IO space",
-+	.start = EMMA2RH_PCI_IO_BASE,
-+	.end = EMMA2RH_PCI_IO_BASE + EMMA2RH_PCI_IO_SIZE - 1,
-+	.flags = IORESOURCE_IO,
-+};
-+
-+static struct resource pci_mem_resource = {
-+	.name = "pci memory space",
-+	.start = EMMA2RH_PCI_MEM_BASE,
-+	.end = EMMA2RH_PCI_MEM_BASE + EMMA2RH_PCI_MEM_SIZE - 1,
-+	.flags = IORESOURCE_MEM,
-+};
-+
-+extern struct pci_ops emma2rh_pci_ops;
-+
-+static struct pci_controller emma2rh_pci_controller = {
-+	.pci_ops = &emma2rh_pci_ops,
-+	.mem_resource = &pci_mem_resource,
-+	.io_resource = &pci_io_resource,
-+	.mem_offset = -0x04000000,
-+	.io_offset = 0,
-+};
-+
-+static void __init emma2rh_pci_init(void)
-+{
-+	/* setup PCI interface */
-+	emma2rh_out32(EMMA2RH_PCI_ARBIT_CTR, 0x70f);
-+
-+	emma2rh_out32(EMMA2RH_PCI_IWIN0_CTR, 0x80000a18);
-+	emma2rh_out32(EMMA2RH_PCI_CONFIG_BASE + PCI_COMMAND,
-+		      PCI_STATUS_DEVSEL_MEDIUM | PCI_STATUS_CAP_LIST |
-+		      PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
-+	emma2rh_out32(EMMA2RH_PCI_CONFIG_BASE + PCI_BASE_ADDRESS_0, 0x10000000);
-+	emma2rh_out32(EMMA2RH_PCI_CONFIG_BASE + PCI_BASE_ADDRESS_1, 0x00000000);
-+
-+	emma2rh_out32(EMMA2RH_PCI_IWIN0_CTR, 0x12000000 | 0x218);
-+	emma2rh_out32(EMMA2RH_PCI_IWIN1_CTR, 0x18000000 | 0x600);
-+	emma2rh_out32(EMMA2RH_PCI_INIT_ESWP, 0x00000200);
-+
-+	emma2rh_out32(EMMA2RH_PCI_TWIN_CTR, 0x00009200);
-+	emma2rh_out32(EMMA2RH_PCI_TWIN_BADR, 0x00000000);
-+	emma2rh_out32(EMMA2RH_PCI_TWIN0_DADR, 0x00000000);
-+	emma2rh_out32(EMMA2RH_PCI_TWIN1_DADR, 0x00000000);
-+}
-+
-+static int __init emma2rh_pci_setup(void)
-+{
-+	emma2rh_pci_init();
-+	register_pci_controller(&emma2rh_pci_controller);
-+	return 0;
-+}
-+
-+arch_initcall(emma2rh_pci_setup);
-diff -Naur linux-2.6.17.orig/arch/mips/pci/pci-excite.c linux-2.6.17/arch/mips/pci/pci-excite.c
---- linux-2.6.17.orig/arch/mips/pci/pci-excite.c	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/arch/mips/pci/pci-excite.c	2006-06-19 18:16:13.000000000 -0700
-@@ -0,0 +1,149 @@
-+/*
-+ *  Copyright (C) 2004 by Basler Vision Technologies AG
-+ *  Author: Thomas Koeller <thomas.koeller@baslerweb.com>
-+ *  Based on the PMC-Sierra Yosemite board support by Ralf Baechle.
-+ *
-+ *  This program is free software; you can redistribute it and/or modify
-+ *  it under the terms of the GNU General Public License as published by
-+ *  the Free Software Foundation; either version 2 of the License, or
-+ *  (at your option) any later version.
-+ *
-+ *  This program is distributed in the hope that it will be useful,
-+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ *  GNU General Public License for more details.
-+ *
-+ *  You should have received a copy of the GNU General Public License
-+ *  along with this program; if not, write to the Free Software
-+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-+ */
-+#include <linux/init.h>
-+#include <linux/kernel.h>
-+#include <linux/types.h>
-+#include <linux/pci.h>
-+#include <linux/bitops.h>
-+#include <asm/rm9k-ocd.h>
-+#include <excite.h>
-+
-+
-+extern struct pci_ops titan_pci_ops;
-+
-+
-+static struct resource
-+	mem_resource = 	{
-+		.name	= "PCI memory",
-+		.start	= EXCITE_PHYS_PCI_MEM,
-+		.end	= EXCITE_PHYS_PCI_MEM + EXCITE_SIZE_PCI_MEM - 1,
-+		.flags	= IORESOURCE_MEM
-+	},
-+	io_resource = {
-+		.name	= "PCI I/O",
-+		.start	= EXCITE_PHYS_PCI_IO,
-+		.end	= EXCITE_PHYS_PCI_IO + EXCITE_SIZE_PCI_IO - 1,
-+		.flags	= IORESOURCE_IO
-+	};
-+
-+
-+static struct pci_controller bx_controller = {
-+	.pci_ops	= &titan_pci_ops,
-+	.mem_resource	= &mem_resource,
-+	.mem_offset	= 0x00000000UL,
-+	.io_resource	= &io_resource,
-+	.io_offset	= 0x00000000UL
-+};
-+
-+
-+static char
-+	iopage_failed[] __initdata   = "Cannot allocate PCI I/O page",
-+	modebits_no_pci[] __initdata = "PCI is not configured in mode bits";
-+
-+#define RM9000x2_OCD_HTSC	0x0604
-+#define RM9000x2_OCD_HTBHL	0x060c
-+#define RM9000x2_OCD_PCIHRST	0x078c
-+
-+#define RM9K_OCD_MODEBIT1	0x00d4 /* (MODEBIT1) Mode Bit 1 */
-+#define RM9K_OCD_CPHDCR		0x00f4 /* CPU-PCI/HT Data Control. */
-+
-+#define PCISC_FB2B 		0x00000200
-+#define PCISC_MWICG		0x00000010
-+#define PCISC_EMC		0x00000004
-+#define PCISC_ERMA		0x00000002
-+
-+
-+
-+static int __init basler_excite_pci_setup(void)
-+{
-+	const unsigned int fullbars = memsize / (256 << 20);
-+	unsigned int i;
-+
-+	/* Check modebits to see if PCI is really enabled. */
-+	if (!((ocd_readl(RM9K_OCD_MODEBIT1) >> (47-32)) & 0x1))
-+		panic(modebits_no_pci);
-+
-+	if (NULL == request_mem_region(EXCITE_PHYS_PCI_IO, EXCITE_SIZE_PCI_IO,
-+				       "Memory-mapped PCI I/O page"))
-+		panic(iopage_failed);
-+
-+	/* Enable PCI 0 as master for config cycles */
-+	ocd_writel(PCISC_EMC | PCISC_ERMA, RM9000x2_OCD_HTSC);
-+
-+
-+	/* Set up latency timer */
-+	ocd_writel(0x8008, RM9000x2_OCD_HTBHL);
-+
-+	/*  Setup host IO and Memory space */
-+	ocd_writel((EXCITE_PHYS_PCI_IO >> 4) | 1, LKB7);
-+	ocd_writel(((EXCITE_SIZE_PCI_IO >> 4) & 0x7fffff00) - 0x100, LKM7);
-+	ocd_writel((EXCITE_PHYS_PCI_MEM >> 4) | 1, LKB8);
-+	ocd_writel(((EXCITE_SIZE_PCI_MEM >> 4) & 0x7fffff00) - 0x100, LKM8);
-+
-+	/* Set up PCI BARs to map all installed memory */
-+	for (i = 0; i < 6; i++) {
-+		const unsigned int bar = 0x610 + i * 4;
-+
-+	     	if (i < fullbars) {
-+			ocd_writel(0x10000000 * i, bar);
-+			ocd_writel(0x01000000 * i, bar + 0x140);
-+			ocd_writel(0x0ffff029, bar + 0x100);
-+			continue;
-+		}
-+
-+	     	if (i == fullbars) {
-+			int o;
-+			u32 mask;
-+
-+			const unsigned long rem = memsize - i * 0x10000000;
-+			if (!rem) {
-+				ocd_writel(0x00000000, bar + 0x100);
-+				continue;
-+			}
-+
-+			o = ffs(rem) - 1;
-+			if (rem & ~(0x1 << o))
-+				o++;
-+			mask = ((0x1 << o) & 0x0ffff000) - 0x1000;
-+			ocd_writel(0x10000000 * i, bar);
-+			ocd_writel(0x01000000 * i, bar + 0x140);
-+			ocd_writel(0x00000029 | mask, bar + 0x100);
-+			continue;
-+		}
-+
-+		ocd_writel(0x00000000, bar + 0x100);
-+	}
-+
-+	/* Finally, enable the PCI interupt */
-+#if USB_IRQ > 7
-+	set_c0_intcontrol(1 << USB_IRQ);
-+#else
-+	set_c0_status(1 << (USB_IRQ + 8));
-+#endif
-+
-+	ioport_resource.start = EXCITE_PHYS_PCI_IO;
-+	ioport_resource.end = EXCITE_PHYS_PCI_IO + EXCITE_SIZE_PCI_IO - 1;
-+	set_io_port_base((unsigned long) ioremap_nocache(EXCITE_PHYS_PCI_IO, EXCITE_SIZE_PCI_IO));
-+	register_pci_controller(&bx_controller);
-+	return 0;
-+}
-+
-+
-+arch_initcall(basler_excite_pci_setup);
-diff -Naur linux-2.6.17.orig/arch/mips/pci/pci-ip27.c linux-2.6.17/arch/mips/pci/pci-ip27.c
---- linux-2.6.17.orig/arch/mips/pci/pci-ip27.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/pci/pci-ip27.c	2006-06-19 18:16:13.000000000 -0700
-@@ -40,297 +40,7 @@
- struct bridge_controller *irq_to_bridge[MAX_PCI_BUSSES * MAX_DEVICES_PER_PCIBUS];
- int irq_to_slot[MAX_PCI_BUSSES * MAX_DEVICES_PER_PCIBUS];
- 
--/*
-- * The Bridge ASIC supports both type 0 and type 1 access.  Type 1 is
-- * not really documented, so right now I can't write code which uses it.
-- * Therefore we use type 0 accesses for now even though they won't work
-- * correcly for PCI-to-PCI bridges.
-- *
-- * The function is complicated by the ultimate brokeness of the IOC3 chip
-- * which is used in SGI systems.  The IOC3 can only handle 32-bit PCI
-- * accesses and does only decode parts of it's address space.
-- */
--
--static int pci_conf0_read_config(struct pci_bus *bus, unsigned int devfn,
--				 int where, int size, u32 * value)
--{
--	struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
--	bridge_t *bridge = bc->base;
--	int slot = PCI_SLOT(devfn);
--	int fn = PCI_FUNC(devfn);
--	volatile void *addr;
--	u32 cf, shift, mask;
--	int res;
--
--	addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID];
--	if (get_dbe(cf, (u32 *) addr))
--		return PCIBIOS_DEVICE_NOT_FOUND;
--
--	/*
--	 * IOC3 is fucked fucked beyond believe ...  Don't even give the
--	 * generic PCI code a chance to look at it for real ...
--	 */
--	if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
--		goto oh_my_gawd;
--
--	addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)];
--
--	if (size == 1)
--		res = get_dbe(*value, (u8 *) addr);
--	else if (size == 2)
--		res = get_dbe(*value, (u16 *) addr);
--	else
--		res = get_dbe(*value, (u32 *) addr);
--
--	return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
--
--oh_my_gawd:
--
--	/*
--	 * IOC3 is fucked fucked beyond believe ...  Don't even give the
--	 * generic PCI code a chance to look at the wrong register.
--	 */
--	if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) {
--		*value = 0;
--		return PCIBIOS_SUCCESSFUL;
--	}
--
--	/*
--	 * IOC3 is fucked fucked beyond believe ...  Don't try to access
--	 * anything but 32-bit words ...
--	 */
--	addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
--
--	if (get_dbe(cf, (u32 *) addr))
--		return PCIBIOS_DEVICE_NOT_FOUND;
--
--	shift = ((where & 3) << 3);
--	mask = (0xffffffffU >> ((4 - size) << 3));
--	*value = (cf >> shift) & mask;
--
--	return PCIBIOS_SUCCESSFUL;
--}
--
--static int pci_conf1_read_config(struct pci_bus *bus, unsigned int devfn,
--				 int where, int size, u32 * value)
--{
--	struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
--	bridge_t *bridge = bc->base;
--	int busno = bus->number;
--	int slot = PCI_SLOT(devfn);
--	int fn = PCI_FUNC(devfn);
--	volatile void *addr;
--	u32 cf, shift, mask;
--	int res;
--
--	bridge->b_pci_cfg = (busno << 16) | (slot << 11);
--	addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID];
--	if (get_dbe(cf, (u32 *) addr))
--		return PCIBIOS_DEVICE_NOT_FOUND;
--
--	/*
--	 * IOC3 is fucked fucked beyond believe ...  Don't even give the
--	 * generic PCI code a chance to look at it for real ...
--	 */
--	if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
--		goto oh_my_gawd;
--
--	bridge->b_pci_cfg = (busno << 16) | (slot << 11);
--	addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))];
--
--	if (size == 1)
--		res = get_dbe(*value, (u8 *) addr);
--	else if (size == 2)
--		res = get_dbe(*value, (u16 *) addr);
--	else
--		res = get_dbe(*value, (u32 *) addr);
--
--	return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
--
--oh_my_gawd:
--
--	/*
--	 * IOC3 is fucked fucked beyond believe ...  Don't even give the
--	 * generic PCI code a chance to look at the wrong register.
--	 */
--	if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) {
--		*value = 0;
--		return PCIBIOS_SUCCESSFUL;
--	}
--
--	/*
--	 * IOC3 is fucked fucked beyond believe ...  Don't try to access
--	 * anything but 32-bit words ...
--	 */
--	bridge->b_pci_cfg = (busno << 16) | (slot << 11);
--	addr = &bridge->b_type1_cfg.c[(fn << 8) | where];
--
--	if (get_dbe(cf, (u32 *) addr))
--		return PCIBIOS_DEVICE_NOT_FOUND;
--
--	shift = ((where & 3) << 3);
--	mask = (0xffffffffU >> ((4 - size) << 3));
--	*value = (cf >> shift) & mask;
--
--	return PCIBIOS_SUCCESSFUL;
--}
--
--static int pci_read_config(struct pci_bus *bus, unsigned int devfn,
--			   int where, int size, u32 * value)
--{
--	if (bus->number > 0)
--		return pci_conf1_read_config(bus, devfn, where, size, value);
--
--	return pci_conf0_read_config(bus, devfn, where, size, value);
--}
--
--static int pci_conf0_write_config(struct pci_bus *bus, unsigned int devfn,
--				  int where, int size, u32 value)
--{
--	struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
--	bridge_t *bridge = bc->base;
--	int slot = PCI_SLOT(devfn);
--	int fn = PCI_FUNC(devfn);
--	volatile void *addr;
--	u32 cf, shift, mask, smask;
--	int res;
--
--	addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID];
--	if (get_dbe(cf, (u32 *) addr))
--		return PCIBIOS_DEVICE_NOT_FOUND;
--
--	/*
--	 * IOC3 is fucked fucked beyond believe ...  Don't even give the
--	 * generic PCI code a chance to look at it for real ...
--	 */
--	if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
--		goto oh_my_gawd;
--
--	addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)];
--
--	if (size == 1) {
--		res = put_dbe(value, (u8 *) addr);
--	} else if (size == 2) {
--		res = put_dbe(value, (u16 *) addr);
--	} else {
--		res = put_dbe(value, (u32 *) addr);
--	}
--
--	if (res)
--		return PCIBIOS_DEVICE_NOT_FOUND;
--
--	return PCIBIOS_SUCCESSFUL;
--
--oh_my_gawd:
--
--	/*
--	 * IOC3 is fucked fucked beyond believe ...  Don't even give the
--	 * generic PCI code a chance to touch the wrong register.
--	 */
--	if ((where >= 0x14 && where < 0x40) || (where >= 0x48))
--		return PCIBIOS_SUCCESSFUL;
--
--	/*
--	 * IOC3 is fucked fucked beyond believe ...  Don't try to access
--	 * anything but 32-bit words ...
--	 */
--	addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
--
--	if (get_dbe(cf, (u32 *) addr))
--		return PCIBIOS_DEVICE_NOT_FOUND;
--
--	shift = ((where & 3) << 3);
--	mask = (0xffffffffU >> ((4 - size) << 3));
--	smask = mask << shift;
--
--	cf = (cf & ~smask) | ((value & mask) << shift);
--	if (put_dbe(cf, (u32 *) addr))
--		return PCIBIOS_DEVICE_NOT_FOUND;
--
--	return PCIBIOS_SUCCESSFUL;
--}
--
--static int pci_conf1_write_config(struct pci_bus *bus, unsigned int devfn,
--				  int where, int size, u32 value)
--{
--	struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
--	bridge_t *bridge = bc->base;
--	int slot = PCI_SLOT(devfn);
--	int fn = PCI_FUNC(devfn);
--	int busno = bus->number;
--	volatile void *addr;
--	u32 cf, shift, mask, smask;
--	int res;
--
--	bridge->b_pci_cfg = (busno << 16) | (slot << 11);
--	addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID];
--	if (get_dbe(cf, (u32 *) addr))
--		return PCIBIOS_DEVICE_NOT_FOUND;
--
--	/*
--	 * IOC3 is fucked fucked beyond believe ...  Don't even give the
--	 * generic PCI code a chance to look at it for real ...
--	 */
--	if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
--		goto oh_my_gawd;
--
--	addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))];
--
--	if (size == 1) {
--		res = put_dbe(value, (u8 *) addr);
--	} else if (size == 2) {
--		res = put_dbe(value, (u16 *) addr);
--	} else {
--		res = put_dbe(value, (u32 *) addr);
--	}
--
--	if (res)
--		return PCIBIOS_DEVICE_NOT_FOUND;
--
--	return PCIBIOS_SUCCESSFUL;
--
--oh_my_gawd:
--
--	/*
--	 * IOC3 is fucked fucked beyond believe ...  Don't even give the
--	 * generic PCI code a chance to touch the wrong register.
--	 */
--	if ((where >= 0x14 && where < 0x40) || (where >= 0x48))
--		return PCIBIOS_SUCCESSFUL;
--
--	/*
--	 * IOC3 is fucked fucked beyond believe ...  Don't try to access
--	 * anything but 32-bit words ...
--	 */
--	addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
--
--	if (get_dbe(cf, (u32 *) addr))
--		return PCIBIOS_DEVICE_NOT_FOUND;
--
--	shift = ((where & 3) << 3);
--	mask = (0xffffffffU >> ((4 - size) << 3));
--	smask = mask << shift;
--
--	cf = (cf & ~smask) | ((value & mask) << shift);
--	if (put_dbe(cf, (u32 *) addr))
--		return PCIBIOS_DEVICE_NOT_FOUND;
--
--	return PCIBIOS_SUCCESSFUL;
--}
--
--static int pci_write_config(struct pci_bus *bus, unsigned int devfn,
--	int where, int size, u32 value)
--{
--	if (bus->number > 0)
--		return pci_conf1_write_config(bus, devfn, where, size, value);
--
--	return pci_conf0_write_config(bus, devfn, where, size, value);
--}
--
--static struct pci_ops bridge_pci_ops = {
--	.read = pci_read_config,
--	.write = pci_write_config,
--};
-+extern struct pci_ops bridge_pci_ops;
- 
- int __init bridge_probe(nasid_t nasid, int widget_id, int masterwid)
- {
-@@ -370,8 +80,7 @@
- 	bc->widget_id = widget_id;
- 	bc->nasid = nasid;
- 
--	bc->baddr = (u64)masterwid << 60;
--	bc->baddr |= (1UL << 56);	/* Barrier set */
-+	bc->baddr = (u64)masterwid << 60 | PCI64_ATTR_BAR;
- 
- 	/*
- 	 * point to this bridge
-diff -Naur linux-2.6.17.orig/arch/mips/pci/pci-jmr3927.c linux-2.6.17/arch/mips/pci/pci-jmr3927.c
---- linux-2.6.17.orig/arch/mips/pci/pci-jmr3927.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/pci/pci-jmr3927.c	2006-06-19 18:16:13.000000000 -0700
-@@ -35,17 +35,17 @@
- #include <asm/debug.h>
- 
- struct resource pci_io_resource = {
--	"IO MEM",
--	0x1000,			/* reserve regacy I/O space */
--	0x1000 + JMR3927_PCIIO_SIZE - 1,
--	IORESOURCE_IO
-+	.name	= "IO MEM",
-+	.start	= 0x1000,			/* reserve regacy I/O space */
-+	.end	= 0x1000 + JMR3927_PCIIO_SIZE - 1,
-+	.flags	= IORESOURCE_IO
- };
- 
- struct resource pci_mem_resource = {
--	"PCI MEM",
--	JMR3927_PCIMEM,
--	JMR3927_PCIMEM + JMR3927_PCIMEM_SIZE - 1,
--	IORESOURCE_MEM
-+	.name	= "PCI MEM",
-+	.start	= JMR3927_PCIMEM,
-+	.end	= JMR3927_PCIMEM + JMR3927_PCIMEM_SIZE - 1,
-+	.flags	= IORESOURCE_MEM
- };
- 
- extern struct pci_ops jmr3927_pci_ops;
-diff -Naur linux-2.6.17.orig/arch/mips/pci/pci-ocelot.c linux-2.6.17/arch/mips/pci/pci-ocelot.c
---- linux-2.6.17.orig/arch/mips/pci/pci-ocelot.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/pci/pci-ocelot.c	2006-06-19 18:16:13.000000000 -0700
-@@ -71,13 +71,13 @@
- }
- 
- static struct resource ocelot_mem_resource = {
--	iomem_resource.start = GT_PCI_MEM_BASE;
--	iomem_resource.end = GT_PCI_MEM_BASE + GT_PCI_MEM_BASE - 1;
-+	start	= GT_PCI_MEM_BASE;
-+	end	= GT_PCI_MEM_BASE + GT_PCI_MEM_BASE - 1;
- };
- 
- static struct resource ocelot_io_resource = {
--	ioport_resource.start = GT_PCI_IO_BASE;
--	ioport_resource.end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1;
-+	start	= GT_PCI_IO_BASE;
-+	end	= GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1;
- };
- 
- static struct pci_controller ocelot_pci_controller = {
-diff -Naur linux-2.6.17.orig/arch/mips/pci/pci-yosemite.c linux-2.6.17/arch/mips/pci/pci-yosemite.c
---- linux-2.6.17.orig/arch/mips/pci/pci-yosemite.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/pci/pci-yosemite.c	2006-06-19 18:16:13.000000000 -0700
-@@ -14,7 +14,10 @@
- extern struct pci_ops titan_pci_ops;
- 
- static struct resource py_mem_resource = {
--	"Titan PCI MEM", 0xe0000000UL, 0xe3ffffffUL, IORESOURCE_MEM
-+	.start	= 0xe0000000UL,
-+	.end	= 0xe3ffffffUL,
-+	.name	= "Titan PCI MEM",
-+	.flags	= IORESOURCE_MEM
- };
- 
- /*
-@@ -26,7 +29,10 @@
- #define TITAN_IO_BASE	0xe8000000UL
- 
- static struct resource py_io_resource = {
--	"Titan IO MEM", 0x00001000UL, TITAN_IO_SIZE - 1, IORESOURCE_IO,
-+	.start	= 0x00001000UL,
-+	.end	= TITAN_IO_SIZE - 1,
-+	.name	= "Titan IO MEM",
-+	.flags	= IORESOURCE_IO,
- };
- 
- static struct pci_controller py_controller = {
-diff -Naur linux-2.6.17.orig/arch/mips/philips/pnx8550/common/pci.c linux-2.6.17/arch/mips/philips/pnx8550/common/pci.c
---- linux-2.6.17.orig/arch/mips/philips/pnx8550/common/pci.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/philips/pnx8550/common/pci.c	2006-06-19 18:16:13.000000000 -0700
-@@ -27,17 +27,17 @@
- #include <nand.h>
- 
- static struct resource pci_io_resource = {
--	"pci IO space",
--	(u32)(PNX8550_PCIIO + 0x1000),	/* reserve regacy I/O space */
--	(u32)(PNX8550_PCIIO + PNX8550_PCIIO_SIZE),
--	IORESOURCE_IO
-+	.start	= PNX8550_PCIIO + 0x1000,	/* reserve regacy I/O space */
-+	.end	= PNX8550_PCIIO + PNX8550_PCIIO_SIZE,
-+	.name	= "pci IO space",
-+	.flags	= IORESOURCE_IO
- };
- 
- static struct resource pci_mem_resource = {
--	"pci memory space",
--	(u32)(PNX8550_PCIMEM),
--	(u32)(PNX8550_PCIMEM + PNX8550_PCIMEM_SIZE - 1),
--	IORESOURCE_MEM
-+	.start	= PNX8550_PCIMEM,
-+	.end	= PNX8550_PCIMEM + PNX8550_PCIMEM_SIZE - 1,
-+	.name	= "pci memory space",
-+	.flags	= IORESOURCE_MEM
- };
- 
- extern struct pci_ops pnx8550_pci_ops;
-diff -Naur linux-2.6.17.orig/arch/mips/philips/pnx8550/common/setup.c linux-2.6.17/arch/mips/philips/pnx8550/common/setup.c
---- linux-2.6.17.orig/arch/mips/philips/pnx8550/common/setup.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/philips/pnx8550/common/setup.c	2006-06-19 18:16:13.000000000 -0700
-@@ -58,10 +58,27 @@
- extern char *prom_getcmdline(void);
- 
- struct resource standard_io_resources[] = {
--	{"dma1", 0x00, 0x1f, IORESOURCE_BUSY},
--	{"timer", 0x40, 0x5f, IORESOURCE_BUSY},
--	{"dma page reg", 0x80, 0x8f, IORESOURCE_BUSY},
--	{"dma2", 0xc0, 0xdf, IORESOURCE_BUSY},
-+	{
-+		.start	= .0x00,
-+		.end	= 0x1f,
-+		.name	= "dma1",
-+		.flags	= IORESOURCE_BUSY
-+	}, {
-+		.start	= 0x40,
-+		.end	= 0x5f,
-+		.name	= "timer",
-+		.flags	= IORESOURCE_BUSY
-+	}, {
-+		.start	= 0x80,
-+		.end	= 0x8f,
-+		.name	= "dma page reg",
-+		.flags	= IORESOURCE_BUSY
-+	}, {
-+		.start	= 0xc0,
-+		.end	= 0xdf,
-+		.name	= "dma2",
-+		.flags	= IORESOURCE_BUSY
-+	},
- };
- 
- #define STANDARD_IO_RESOURCES (sizeof(standard_io_resources)/sizeof(struct resource))
-@@ -82,7 +99,7 @@
- 
- int pnx8550_console_port = -1;
- 
--void __init plat_setup(void)
-+void __init plat_mem_setup(void)
- {
- 	int i;
- 	char* argptr;
-diff -Naur linux-2.6.17.orig/arch/mips/pmc-sierra/yosemite/setup.c linux-2.6.17/arch/mips/pmc-sierra/yosemite/setup.c
---- linux-2.6.17.orig/arch/mips/pmc-sierra/yosemite/setup.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/pmc-sierra/yosemite/setup.c	2006-06-19 18:16:13.000000000 -0700
-@@ -218,7 +218,7 @@
- 	py_rtc_setup();
- }
- 
--void __init plat_setup(void)
-+void __init plat_mem_setup(void)
- {
- 	board_time_init = yosemite_time_init;
- 	late_time_init = py_late_time_init;
-diff -Naur linux-2.6.17.orig/arch/mips/qemu/Makefile linux-2.6.17/arch/mips/qemu/Makefile
---- linux-2.6.17.orig/arch/mips/qemu/Makefile	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/qemu/Makefile	2006-06-19 18:16:13.000000000 -0700
-@@ -2,6 +2,7 @@
- # Makefile for Qemu specific kernel interface routines under Linux.
- #
- 
--obj-y		= q-firmware.o q-irq.o q-mem.o q-setup.o
-+obj-y		= q-firmware.o q-irq.o q-mem.o q-setup.o q-reset.o
- 
-+obj-$(CONFIG_VT) += q-vga.o
- obj-$(CONFIG_SMP) += q-smp.o
-diff -Naur linux-2.6.17.orig/arch/mips/qemu/q-reset.c linux-2.6.17/arch/mips/qemu/q-reset.c
---- linux-2.6.17.orig/arch/mips/qemu/q-reset.c	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/arch/mips/qemu/q-reset.c	2006-06-19 18:16:13.000000000 -0700
-@@ -0,0 +1,34 @@
-+#include <linux/config.h>
-+
-+#include <asm/io.h>
-+#include <asm/reboot.h>
-+#include <asm/cacheflush.h>
-+#include <asm/qemu.h>
-+
-+static void qemu_machine_restart(char *command)
-+{
-+	volatile unsigned int *reg = (unsigned int *)QEMU_RESTART_REG;
-+
-+	set_c0_status(ST0_BEV | ST0_ERL);
-+	change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
-+	flush_cache_all();
-+	write_c0_wired(0);
-+	*reg = 42;
-+	while (1)
-+		cpu_wait();
-+}
-+
-+static void qemu_machine_halt(void)
-+{
-+	volatile unsigned int *reg = (unsigned int *)QEMU_HALT_REG;
-+
-+	*reg = 42;
-+	while (1)
-+		cpu_wait();
-+}
-+
-+void qemu_reboot_setup(void)
-+{
-+	_machine_restart = qemu_machine_restart;
-+	_machine_halt = qemu_machine_halt;
-+}
-diff -Naur linux-2.6.17.orig/arch/mips/qemu/q-setup.c linux-2.6.17/arch/mips/qemu/q-setup.c
---- linux-2.6.17.orig/arch/mips/qemu/q-setup.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/qemu/q-setup.c	2006-06-19 18:16:13.000000000 -0700
-@@ -2,6 +2,9 @@
- #include <asm/io.h>
- #include <asm/time.h>
- 
-+extern void qvga_init(void);
-+extern void qemu_reboot_setup(void);
-+
- #define QEMU_PORT_BASE 0xb4000000
- 
- const char *get_system_type(void)
-@@ -18,8 +21,13 @@
- 	setup_irq(0, irq);
- }
- 
--void __init plat_setup(void)
-+void __init plat_mem_setup(void)
- {
- 	set_io_port_base(QEMU_PORT_BASE);
-+#ifdef CONFIG_VT
-+	qvga_init();
-+#endif
- 	board_timer_setup = qemu_timer_setup;
-+
-+	qemu_reboot_setup();
- }
-diff -Naur linux-2.6.17.orig/arch/mips/qemu/q-vga.c linux-2.6.17/arch/mips/qemu/q-vga.c
---- linux-2.6.17.orig/arch/mips/qemu/q-vga.c	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/arch/mips/qemu/q-vga.c	2006-06-19 18:16:13.000000000 -0700
-@@ -0,0 +1,188 @@
-+/*
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License.  See the file "COPYING" in the main directory of this archive
-+ * for more details.
-+ *
-+ * Copyright (C) 2005 by Ralf Baechle (ralf@linux-mips.org)
-+ *
-+ * This will eventually go into the qemu firmware.
-+ */
-+#include <linux/init.h>
-+#include <linux/tty.h>
-+#include <asm/io.h>
-+#include <video/vga.h>
-+
-+/*
-+ * This will eventually be done by the firmware; right now Linux assumes to
-+ * run on the uninitialized hardware.
-+ */
-+#undef LOAD_VGA_FONT
-+
-+static unsigned char sr[8] __initdata = {	/* Sequencer */
-+	0x03, 0x00, 0x03, 0x04, 0x02, 0x00, 0x00, 0x00
-+};
-+
-+static unsigned char gr[16] __initdata= {	/* Graphics Controller */
-+	0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0e, 0x00,
-+	0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
-+};
-+
-+static unsigned char ar[21] __initdata= {	/* Attribute Controller */
-+	0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
-+	0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
-+	0x0c, 0x01, 0x07, 0x13, 0x00
-+};
-+
-+static unsigned char cr[32] __initdata= {	/* CRT Controller */
-+	0x91, 0x4f, 0x4f, 0x95, 0x57, 0x4f, 0xc0, 0x1f,
-+	0x00, 0x4f, 0x0d, 0x0e, 0x02, 0x30, 0x09, 0xb0,
-+	0x90, 0x83, 0x8f, 0x28, 0x1f, 0x8f, 0xc1, 0xa3,
-+	0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
-+};
-+
-+static struct rgb {
-+	unsigned char r;
-+	unsigned char g;
-+	unsigned char b;
-+} palette[16] __initdata= {
-+	[ 0] = {0x00, 0x00, 0x00},
-+	[ 1] = {0x00, 0x00, 0x2a},
-+	[ 2] = {0x00, 0x2a, 0x00},
-+	[ 3] = {0x00, 0x2a, 0x2a},
-+	[ 4] = {0x2a, 0x00, 0x00},
-+	[ 5] = {0x2a, 0x00, 0x2a},
-+	[ 6] = {0x2a, 0x15, 0x00},
-+	[ 7] = {0x2a, 0x2a, 0x2a},
-+	[ 8] = {0x15, 0x15, 0x15},
-+	[ 9] = {0x15, 0x15, 0x3f},
-+	[10] = {0x15, 0x3f, 0x15},
-+	[11] = {0x15, 0x3f, 0x3f},
-+	[12] = {0x3f, 0x15, 0x15},
-+	[13] = {0x3f, 0x15, 0x3f},
-+	[14] = {0x3f, 0x3f, 0x15},
-+	[15] = {0x3f, 0x3f, 0x3f}
-+
-+};
-+
-+void __init qvga_init_ibm(void)
-+{
-+	int i;
-+
-+	for (i = 0; i < 8; i++) {	/* Sequencer registers */
-+		outb(i, 0x3c4);
-+		outb(sr[i], 0x3c5);
-+	}
-+
-+	for (i = 0; i < 16; i++) {	/* Graphics Controller registers */
-+		outb(i, 0x3ce);
-+		outb(gr[i], 0x3cf);
-+	}
-+
-+	for (i = 0; i < 21; i++) {	/* Attribute Controller registers */
-+		outb(i, 0x3c0);
-+		outb(ar[i], 0x3c1);
-+	}
-+	outb(0x20, 0x3c0);		/* enable bit in *index* register */
-+
-+	for (i = 0; i < 32; i++) {	/* CRT Controller registers */
-+		outb(i, 0x3d4);
-+		outb(cr[i], 0x3d5);
-+	}
-+
-+	for (i = 0; i < 16; i++) {	/* palette */
-+		outb(i, 0x3c8);
-+		outb(palette[i].r, 0x3c9);
-+		outb(palette[i].g, 0x3c9);
-+		outb(palette[i].b, 0x3c9);
-+	}
-+
-+#if 1
-+	 for (i = 0; i < 0x20000; i += 2)
-+		*(volatile unsigned short *) (0xb00a0000 + i) = 0xaaaa;
-+#endif
-+}
-+
-+#ifdef LOAD_VGA_FONT
-+#include "/home/ralf/src/qemu/qemu-mips/vgafont.h"
-+
-+static void __init
-+qvga_load_font(unsigned char *def, unsigned int c)
-+{
-+	volatile void *w = (volatile void *) 0xb00a0000;
-+
-+	vga_wseq(NULL, 0, 1);
-+	vga_wseq(NULL, 2, 4);
-+	vga_wseq(NULL, 4, 7);
-+	vga_wseq(NULL, 0, 3);
-+	vga_wgfx(NULL, 4, 2);
-+	vga_wgfx(NULL, 5, 0);
-+	vga_wgfx(NULL, 6, 0);
-+
-+	memcpy(w, def, c);
-+
-+	vga_wseq(NULL, 0, 1);
-+	vga_wseq(NULL, 2, 3);
-+	vga_wseq(NULL, 4, 3);
-+	vga_wseq(NULL, 0, 3);
-+	vga_wgfx(NULL, 4, 0);
-+	vga_wgfx(NULL, 5, 0x10);
-+	vga_wgfx(NULL, 6, 0xe);
-+}
-+#endif
-+
-+void __init qvga_init(void)
-+{
-+	struct screen_info *si = &screen_info;
-+	unsigned int h;
-+	int i;
-+
-+#if LOAD_VGA_FONT
-+	qvga_load_font(vgafont16, 4096);
-+#endif
-+
-+	vga_wgfx(NULL, 5, 0x10);	/* Set odd/even mode */
-+	vga_wgfx(NULL, 6, 0x0c);	/* map to offset 0xb8000, text mode */
-+	vga_wseq(NULL, 2, 3);		/* Planes 0 & 1 */
-+	vga_wseq(NULL, 3, 4);		/* Font offset */
-+	outb(1, VGA_MIS_W);		/* set msr to MSR_COLOR_EMULATION */
-+	vga_wcrt(NULL, 1, 79);		/* 80 columns */
-+	vga_wcrt(NULL, 9, 15);		/* 16 pixels per character */
-+	vga_wcrt(NULL, 0x0c, 0);	/* start address high 8 bit */
-+	vga_wcrt(NULL, 0x0d, 0);	/* start address low 8 bit */
-+	vga_wcrt(NULL, 0x13, 0x28);	/* line offset */
-+	vga_wcrt(NULL, 0x07, 0x1f);	/* line compare bit 8 */
-+	vga_wcrt(NULL, 0x09, 0x4f);	/* line compare bit 9 */
-+	vga_wcrt(NULL, 0x18, 0xff);	/* line compare low 8 bit */
-+
-+	h = (25 * 16);
-+	vga_wcrt(NULL, 0x12, h);
-+
-+	outb(7, 0x3d4);
-+	outb((inb(0x3d5) & ~0x42) | ((h >> 7) & 2) | ((h >> 3) & 0x40), 0x3d5);
-+
-+	for (i = 0; i < 21; i++)	/* Attribute Controller */
-+		vga_wattr(NULL, i, ar[i]);
-+	outb(0x20, 0x3c0);		/* Set bit 5 in Attribute Controller */
-+					/* index ...  VGA is so stupid I want */
-+					/* to cry all day ... */
-+	outb(0, VGA_PEL_IW);
-+	for (i = 0; i < 16; i++) {	/* palette */
-+		outb(palette[i].r, VGA_PEL_D);
-+		outb(palette[i].g, VGA_PEL_D);
-+		outb(palette[i].b, VGA_PEL_D);
-+	}
-+
-+	si->orig_x		= 0; 			/* Cursor x position */
-+	si->orig_y		= 0;			/* Cursor y position */
-+	si->orig_video_cols	= 80;			/* Columns */
-+	si->orig_video_lines	= 25;			/* Lines */
-+	si->orig_video_isVGA	= VIDEO_TYPE_VGAC;	/* Card type */
-+	si->orig_video_points	= 16;
-+
-+#if 0
-+	for (i = 0; i < 80; i += 2)
-+		//*(volatile unsigned short *) (0xb00b8000 + i) = 0x0100 | 'A';
-+		scr_writew(0x0100 | 'A', (volatile unsigned short *) (0xb00b8000 + i));
-+	while (1);
-+#endif
-+}
-diff -Naur linux-2.6.17.orig/arch/mips/sgi-ip22/ip22-setup.c linux-2.6.17/arch/mips/sgi-ip22/ip22-setup.c
---- linux-2.6.17.orig/arch/mips/sgi-ip22/ip22-setup.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/sgi-ip22/ip22-setup.c	2006-06-19 18:16:13.000000000 -0700
-@@ -53,7 +53,7 @@
- extern void ip22_be_init(void) __init;
- extern void ip22_time_init(void) __init;
- 
--void __init plat_setup(void)
-+void __init plat_mem_setup(void)
- {
- 	char *ctype;
- 	char *cserial;
-diff -Naur linux-2.6.17.orig/arch/mips/sgi-ip27/ip27-init.c linux-2.6.17/arch/mips/sgi-ip27/ip27-init.c
---- linux-2.6.17.orig/arch/mips/sgi-ip27/ip27-init.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/sgi-ip27/ip27-init.c	2006-06-19 18:16:13.000000000 -0700
-@@ -196,7 +196,7 @@
- extern void ip27_time_init(void);
- extern void ip27_reboot_setup(void);
- 
--void __init plat_setup(void)
-+void __init plat_mem_setup(void)
- {
- 	hubreg_t p, e, n_mode;
- 	nasid_t nid;
-@@ -228,7 +228,7 @@
- 	 */
- 	n_mode = LOCAL_HUB_L(NI_STATUS_REV_ID) & NSRI_MORENODES_MASK;
- 	printk("Machine is in %c mode.\n", n_mode ? 'N' : 'M');
--#ifdef CONFIG_SGI_SN0_N_MODE
-+#ifdef CONFIG_SGI_SN_N_MODE
- 	if (!n_mode)
- 		panic("Kernel compiled for M mode.");
- #else
-diff -Naur linux-2.6.17.orig/arch/mips/sgi-ip27/ip27-irq.c linux-2.6.17/arch/mips/sgi-ip27/ip27-irq.c
---- linux-2.6.17.orig/arch/mips/sgi-ip27/ip27-irq.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/sgi-ip27/ip27-irq.c	2006-06-19 18:16:13.000000000 -0700
-@@ -360,7 +360,7 @@
- 
- static unsigned long irq_map[NR_IRQS / BITS_PER_LONG];
- 
--static int allocate_irqno(void)
-+int allocate_irqno(void)
- {
- 	int irq;
- 
-diff -Naur linux-2.6.17.orig/arch/mips/sgi-ip27/ip27-timer.c linux-2.6.17/arch/mips/sgi-ip27/ip27-timer.c
---- linux-2.6.17.orig/arch/mips/sgi-ip27/ip27-timer.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/sgi-ip27/ip27-timer.c	2006-06-19 18:16:13.000000000 -0700
-@@ -89,11 +89,13 @@
- }
- #endif
- 
-+static unsigned int rt_timer_irq;
-+
- void ip27_rt_timer_interrupt(struct pt_regs *regs)
- {
- 	int cpu = smp_processor_id();
- 	int cpuA = cputoslice(cpu) == 0;
--	int irq = 9;				/* XXX Assign number */
-+	unsigned int irq = rt_timer_irq;
- 
- 	irq_enter();
- 	write_seqlock(&xtime_lock);
-@@ -179,13 +181,68 @@
-         return mktime(year, month, date, hour, min, sec);
- }
- 
-+static void startup_rt_irq(unsigned int irq)
-+{
-+}
-+
-+static void shutdown_rt_irq(unsigned int irq)
-+{
-+}
-+
-+static void enable_rt_irq(unsigned int irq)
-+{
-+}
-+
-+static void disable_rt_irq(unsigned int irq)
-+{
-+}
-+
-+static void mask_and_ack_rt(unsigned int irq)
-+{
-+}
-+
-+static void end_rt_irq(unsigned int irq)
-+{
-+}
-+
-+static struct hw_interrupt_type rt_irq_type = {
-+	.typename	= "SN HUB RT timer",
-+	.startup	= startup_rt_irq,
-+	.shutdown	= shutdown_rt_irq,
-+	.enable		= enable_rt_irq,
-+	.disable	= disable_rt_irq,
-+	.ack		= mask_and_ack_rt,
-+	.end		= end_rt_irq,
-+};
-+
-+static struct irqaction rt_irqaction = {
-+	.handler	= ip27_rt_timer_interrupt,
-+	.flags		= SA_INTERRUPT,
-+	.mask		= CPU_MASK_NONE,
-+	.name		= "timer"
-+};
-+
-+extern int allocate_irqno(void);
-+
- static void ip27_timer_setup(struct irqaction *irq)
- {
-+	int irqno  = allocate_irqno();
-+
-+	if (irqno < 0)
-+		panic("Can't allocate interrupt number for timer interrupt");
-+
-+	irq_desc[irqno].status = IRQ_DISABLED;
-+	irq_desc[irqno].action = NULL;
-+	irq_desc[irqno].depth = 1;
-+	irq_desc[irqno].handler = &rt_irq_type;
-+
- 	/* over-write the handler, we use our own way */
- 	irq->handler = no_action;
- 
- 	/* setup irqaction */
--//	setup_irq(IP27_TIMER_IRQ, irq);		/* XXX Can't do this yet.  */
-+	irq_desc[irqno].status |= IRQ_PER_CPU;
-+
-+	rt_timer_irq = irqno;
- }
- 
- void __init ip27_time_init(void)
-diff -Naur linux-2.6.17.orig/arch/mips/sgi-ip27/Kconfig linux-2.6.17/arch/mips/sgi-ip27/Kconfig
---- linux-2.6.17.orig/arch/mips/sgi-ip27/Kconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/sgi-ip27/Kconfig	2006-06-19 18:16:13.000000000 -0700
-@@ -4,43 +4,42 @@
- #	  This options adds support for userspace processes upto 16TB size.
- #	  Normally the limit is just .5TB.
- 
--config SGI_SN0_N_MODE
--	bool "IP27 N-Mode"
-+choice
-+	prompt "Node addressing mode"
- 	depends on SGI_IP27
-+	default SGI_SN_M_MODE
-+
-+config SGI_SN_M_MODE
-+	bool "IP27 M-Mode"
- 	help
--	  The nodes of Origin 200, Origin 2000 and Onyx 2 systems can be
--	  configured in either N-Modes which allows for more nodes or M-Mode
--	  which allows for more memory.  Your system is most probably
--	  running in M-Mode, so you should say N here.
--
--config ARCH_DISCONTIGMEM_ENABLE
--	bool
--	default y if SGI_IP27
--	help
--	  Say Y to upport efficient handling of discontiguous physical memory,
--	  for architectures which are either NUMA (Non-Uniform Memory Access)
--	  or have huge holes in the physical address space for other reasons.
--	  See <file:Documentation/vm/numa> for more.
-+	  The nodes of Origin, Onyx, Fuel and Tezro systems can be configured
-+	  in either N-Modes which allows for more nodes or M-Mode which allows
-+	  for more memory.  Your hardware is almost certainly running in
-+	  M-Mode, so choose M-mode here.
- 
--config NUMA
--	bool "NUMA Support"
--	depends on SGI_IP27
-+config SGI_SN_N_MODE
-+	bool "IP27 N-Mode"
-+	depends on EXPERIMENTAL
- 	help
--	  Say Y to compile the kernel to support NUMA (Non-Uniform Memory
--	  Access).  This option is for configuring high-end multiprocessor
--	  server machines.  If in doubt, say N.
-+	  The nodes of Origin, Onyx, Fuel and Tezro systems can be configured
-+	  in either N-Modes which allows for more nodes or M-Mode which allows
-+	  for more memory.  Your hardware is almost certainly running in
-+	  M-Mode, so choose M-mode here.
-+
-+endchoice
- 
- config MAPPED_KERNEL
- 	bool "Mapped kernel support"
- 	depends on SGI_IP27
- 	help
- 	  Change the way a Linux kernel is loaded into memory on a MIPS64
--	  machine.  This is required in order to support text replication and
-+	  machine.  This is required in order to support text replication on
- 	  NUMA.  If you need to understand it, read the source code.
- 
- config REPLICATE_KTEXT
- 	bool "Kernel text replication support"
- 	depends on SGI_IP27
-+	select MAPPED_KERNEL
- 	help
- 	  Say Y here to enable replicating the kernel text across multiple
- 	  nodes in a NUMA cluster.  This trades memory for speed.
-diff -Naur linux-2.6.17.orig/arch/mips/sgi-ip32/ip32-setup.c linux-2.6.17/arch/mips/sgi-ip32/ip32-setup.c
---- linux-2.6.17.orig/arch/mips/sgi-ip32/ip32-setup.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/sgi-ip32/ip32-setup.c	2006-06-19 18:16:13.000000000 -0700
-@@ -87,7 +87,7 @@
- 	setup_irq(IP32_R4K_TIMER_IRQ, irq);
- }
- 
--void __init plat_setup(void)
-+void __init plat_mem_setup(void)
- {
- 	board_be_init = ip32_be_init;
- 
-diff -Naur linux-2.6.17.orig/arch/mips/sibyte/bcm1480/time.c linux-2.6.17/arch/mips/sibyte/bcm1480/time.c
---- linux-2.6.17.orig/arch/mips/sibyte/bcm1480/time.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/sibyte/bcm1480/time.c	2006-06-19 18:16:13.000000000 -0700
-@@ -110,17 +110,18 @@
- 	__raw_writeq(M_SCD_TIMER_ENABLE|M_SCD_TIMER_MODE_CONTINUOUS,
- 	      IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
- 
--	/*
--	 * CPU 0 handles the global timer interrupt job
--	 */
- 	if (cpu == 0) {
-+		/*
-+		 * CPU 0 handles the global timer interrupt job
-+		 */
- 		ll_timer_interrupt(irq, regs);
- 	}
--
--	/*
--	 * every CPU should do profiling and process accouting
--	 */
--	ll_local_timer_interrupt(irq, regs);
-+	else {
-+		/*
-+		 * other CPUs should just do profiling and process accounting
-+		 */
-+		ll_local_timer_interrupt(irq, regs);
-+	}
- }
- 
- /*
-diff -Naur linux-2.6.17.orig/arch/mips/sibyte/Kconfig linux-2.6.17/arch/mips/sibyte/Kconfig
---- linux-2.6.17.orig/arch/mips/sibyte/Kconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/sibyte/Kconfig	2006-06-19 18:16:13.000000000 -0700
-@@ -3,6 +3,7 @@
- 	select HW_HAS_PCI
- 	select SIBYTE_HAS_LDT
- 	select SIBYTE_SB1xxx_SOC
-+	select SYS_SUPPORTS_SMP
- 
- config SIBYTE_BCM1120
- 	bool
-@@ -30,11 +31,13 @@
- 	bool
- 	select HW_HAS_PCI
- 	select SIBYTE_SB1xxx_SOC
-+	select SYS_SUPPORTS_SMP
- 
- config SIBYTE_BCM1x55
- 	bool
- 	select HW_HAS_PCI
- 	select SIBYTE_SB1xxx_SOC
-+	select SYS_SUPPORTS_SMP
- 
- config SIBYTE_SB1xxx_SOC
- 	bool
-diff -Naur linux-2.6.17.orig/arch/mips/sibyte/sb1250/irq.c linux-2.6.17/arch/mips/sibyte/sb1250/irq.c
---- linux-2.6.17.orig/arch/mips/sibyte/sb1250/irq.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/sibyte/sb1250/irq.c	2006-06-19 18:16:13.000000000 -0700
-@@ -435,13 +435,17 @@
- 	return lz;
- }
- 
-+extern void sb1250_timer_interrupt(struct pt_regs *regs);
-+extern void sb1250_mailbox_interrupt(struct pt_regs *regs);
-+extern void sb1250_kgdb_interrupt(struct pt_regs *regs);
-+
- asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
- {
- 	unsigned int pending;
- 
- #ifdef CONFIG_SIBYTE_SB1250_PROF
- 	/* Set compare to count to silence count/compare timer interrupts */
--	write_c0_count(read_c0_count());
-+	write_c0_compare(read_c0_count());
- #endif
- 
- 	/*
-@@ -482,7 +486,7 @@
- 		 * Default...we've hit an IP[2] interrupt, which means we've
- 		 * got to check the 1250 interrupt registers to figure out what
- 		 * to do.  Need to detect which CPU we're on, now that
--		 ~ smp_affinity is supported.
-+		 * smp_affinity is supported.
- 		 */
- 		mask = __raw_readq(IOADDR(A_IMR_REGISTER(smp_processor_id(),
- 		                              R_IMR_INTERRUPT_STATUS_BASE)));
-diff -Naur linux-2.6.17.orig/arch/mips/sibyte/swarm/setup.c linux-2.6.17/arch/mips/sibyte/swarm/setup.c
---- linux-2.6.17.orig/arch/mips/sibyte/swarm/setup.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/sibyte/swarm/setup.c	2006-06-19 18:16:13.000000000 -0700
-@@ -72,8 +72,10 @@
- 
- void __init swarm_time_init(void)
- {
-+#if defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
- 	/* Setup HPT */
- 	sb1250_hpt_setup();
-+#endif
- }
- 
- void __init swarm_timer_setup(struct irqaction *irq)
-@@ -103,7 +105,7 @@
- 	return (is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL);
- }
- 
--void __init plat_setup(void)
-+void __init plat_mem_setup(void)
- {
- #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
- 	bcm1480_setup();
-diff -Naur linux-2.6.17.orig/arch/mips/sni/Makefile linux-2.6.17/arch/mips/sni/Makefile
---- linux-2.6.17.orig/arch/mips/sni/Makefile	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/sni/Makefile	2006-06-19 18:16:13.000000000 -0700
-@@ -3,5 +3,6 @@
- #
- 
- obj-y	 	+= irq.o pcimt_scache.o reset.o setup.o
-+obj-$(CONFIG_CPU_BIG_ENDIAN) += sniprom.o
- 
- EXTRA_AFLAGS := $(CFLAGS)
-diff -Naur linux-2.6.17.orig/arch/mips/sni/setup.c linux-2.6.17/arch/mips/sni/setup.c
---- linux-2.6.17.orig/arch/mips/sni/setup.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/sni/setup.c	2006-06-19 18:16:13.000000000 -0700
-@@ -21,8 +21,11 @@
- #include <linux/fb.h>
- #include <linux/tty.h>
- 
-+#ifdef CONFIG_ARC
- #include <asm/arc/types.h>
- #include <asm/sgialib.h>
-+#endif
-+
- #include <asm/bcache.h>
- #include <asm/bootinfo.h>
- #include <asm/io.h>
-@@ -72,8 +75,7 @@
- 
- static void __init sni_display_setup(void)
- {
--#ifdef CONFIG_VT
--#if defined(CONFIG_VGA_CONSOLE)
-+#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE) && defined(CONFIG_ARC)
- 	struct screen_info *si = &screen_info;
- 	DISPLAY_STATUS *di;
- 
-@@ -88,24 +90,54 @@
- 		si->orig_video_points	= 16;
- 	}
- #endif
--#endif
- }
- 
- static struct resource sni_io_resource = {
--	"PCIMT IO MEM", 0x00001000UL, 0x03bfffffUL, IORESOURCE_IO,
-+	.start	= 0x00001000UL,
-+	.end	= 0x03bfffffUL,
-+	.name	= "PCIMT IO MEM",
-+	.flags	= IORESOURCE_IO,
- };
- 
- static struct resource pcimt_io_resources[] = {
--	{ "dma1", 0x00, 0x1f, IORESOURCE_BUSY },
--	{ "timer", 0x40, 0x5f, IORESOURCE_BUSY },
--	{ "keyboard", 0x60, 0x6f, IORESOURCE_BUSY },
--	{ "dma page reg", 0x80, 0x8f, IORESOURCE_BUSY },
--	{ "dma2", 0xc0, 0xdf, IORESOURCE_BUSY },
--	{ "PCI config data", 0xcfc, 0xcff, IORESOURCE_BUSY }
-+	{
-+		.start	= 0x00,
-+		.end	= 0x1f,
-+		.name	= "dma1",
-+		.flags	= IORESOURCE_BUSY
-+	}, {
-+		.start	=  0x40,
-+		.end	= 0x5f,
-+		.name	= "timer",
-+		.flags	= IORESOURCE_BUSY
-+	}, {
-+		.start	=  0x60,
-+		.end	= 0x6f,
-+		.name	= "keyboard",
-+		.flags	= IORESOURCE_BUSY
-+	}, {
-+		.start	=  0x80,
-+		.end	= 0x8f,
-+		.name	= "dma page reg",
-+		.flags	= IORESOURCE_BUSY
-+	}, {
-+		.start	=  0xc0,
-+		.end	= 0xdf,
-+		.name	= "dma2",
-+		.flags	= IORESOURCE_BUSY
-+	}, {
-+		.start	=  0xcfc,
-+		.end	= 0xcff,
-+		.name	= "PCI config data",
-+		.flags	= IORESOURCE_BUSY
-+	}
- };
- 
- static struct resource sni_mem_resource = {
--	"PCIMT PCI MEM", 0x10000000UL, 0xffffffffUL, IORESOURCE_MEM
-+	.start	= 0x10000000UL,
-+	.end	= 0xffffffffUL,
-+	.name	= "PCIMT PCI MEM",
-+	.flags	= IORESOURCE_MEM
- };
- 
- /*
-@@ -122,19 +154,72 @@
-  * 0xa0000000 - 0xffffffff (1.5GB) PCI/EISA Bus Memory
-  */
- static struct resource pcimt_mem_resources[] = {
--	{ "Video RAM area", 0x100a0000, 0x100bffff, IORESOURCE_BUSY },
--	{ "ISA Reserved", 0x100c0000, 0x100fffff, IORESOURCE_BUSY },
--	{ "PCI IO", 0x14000000, 0x17bfffff, IORESOURCE_BUSY },
--	{ "Cache Replacement Area", 0x17c00000, 0x17ffffff, IORESOURCE_BUSY},
--	{ "PCI INT Acknowledge", 0x1a000000, 0x1a000003, IORESOURCE_BUSY },
--	{ "Boot PROM", 0x1fc00000, 0x1fc7ffff, IORESOURCE_BUSY},
--	{ "Diag PROM", 0x1fc80000, 0x1fcfffff, IORESOURCE_BUSY},
--	{ "X-Bus", 0x1fd00000, 0x1fdfffff, IORESOURCE_BUSY},
--	{ "BIOS map", 0x1fe00000, 0x1fefffff, IORESOURCE_BUSY},
--	{ "NVRAM / EEPROM", 0x1ff00000, 0x1ff7ffff, IORESOURCE_BUSY},
--	{ "ASIC PCI", 0x1fff0000, 0x1fffefff, IORESOURCE_BUSY},
--	{ "MP Agent", 0x1ffff000, 0x1fffffff, IORESOURCE_BUSY},
--	{ "Main Memory", 0x20000000, 0x9fffffff, IORESOURCE_BUSY}
-+	{
-+		.start	= 0x100a0000,
-+		.end	= 0x100bffff,
-+		.name	= "Video RAM area",
-+		.flags	= IORESOURCE_BUSY
-+	}, {
-+		.start	= 0x100c0000,
-+		.end	= 0x100fffff,
-+		.name	= "ISA Reserved",
-+		.flags	= IORESOURCE_BUSY
-+	}, {
-+		.start	= 0x14000000,
-+		.end	= 0x17bfffff,
-+		.name	= "PCI IO",
-+		.flags	= IORESOURCE_BUSY
-+	}, {
-+		.start	= 0x17c00000,
-+		.end	= 0x17ffffff,
-+		.name	= "Cache Replacement Area",
-+		.flags	= IORESOURCE_BUSY
-+	}, {
-+		.start	= 0x1a000000,
-+		.end	= 0x1a000003,
-+		.name	= "PCI INT Acknowledge",
-+		.flags	= IORESOURCE_BUSY
-+	}, {
-+		.start	= 0x1fc00000,
-+		.end	= 0x1fc7ffff,
-+		.name	= "Boot PROM",
-+		.flags	= IORESOURCE_BUSY
-+	}, {
-+		.start	= 0x1fc80000,
-+		.end	= 0x1fcfffff,
-+		.name	= "Diag PROM",
-+		.flags	= IORESOURCE_BUSY
-+	}, {
-+		.start	= 0x1fd00000,
-+		.end	= 0x1fdfffff,
-+		.name	= "X-Bus",
-+		.flags	= IORESOURCE_BUSY
-+	}, {
-+		.start	= 0x1fe00000,
-+		.end	= 0x1fefffff,
-+		.name	= "BIOS map",
-+		.flags	= IORESOURCE_BUSY
-+	}, {
-+		.start	= 0x1ff00000,
-+		.end	= 0x1ff7ffff,
-+		.name	= "NVRAM / EEPROM",
-+		.flags	= IORESOURCE_BUSY
-+	}, {
-+		.start	= 0x1fff0000,
-+		.end	= 0x1fffefff,
-+		.name	= "ASIC PCI",
-+		.flags	= IORESOURCE_BUSY
-+	}, {
-+		.start	= 0x1ffff000,
-+		.end	= 0x1fffffff,
-+		.name	= "MP Agent",
-+		.flags	= IORESOURCE_BUSY
-+	}, {
-+		.start	= 0x20000000,
-+		.end	= 0x9fffffff,
-+		.name	= "Main Memory",
-+		.flags	= IORESOURCE_BUSY
-+	}
- };
- 
- static void __init sni_resource_init(void)
-@@ -168,7 +253,7 @@
- 	rtc_mips_set_time = mc146818_set_rtc_mmss;
- }
- 
--void __init plat_setup(void)
-+void __init plat_mem_setup(void)
- {
- 	sni_pcimt_detect();
- 	sni_pcimt_sc_init();
-diff -Naur linux-2.6.17.orig/arch/mips/sni/sniprom.c linux-2.6.17/arch/mips/sni/sniprom.c
---- linux-2.6.17.orig/arch/mips/sni/sniprom.c	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/arch/mips/sni/sniprom.c	2006-06-19 18:16:13.000000000 -0700
-@@ -0,0 +1,158 @@
-+/*
-+ * Big Endian PROM code for SNI RM machines
-+ *
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License.  See the file "COPYING" in the main directory of this archive
-+ * for more details.
-+ *
-+ * Copyright (C) 2005-2006 Florian Lohoff (flo@rfc822.org)
-+ * Copyright (C) 2005-2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/string.h>
-+
-+#include <asm/addrspace.h>
-+#include <asm/sni.h>
-+#include <asm/mipsprom.h>
-+#include <asm/bootinfo.h>
-+
-+/* special SNI prom calls */
-+/*
-+ * This does not exist in all proms - SINIX compares
-+ * the prom env variable "version" against "2.0008"
-+ * or greater. If lesser it tries to probe interesting
-+ * registers
-+ */
-+#define PROM_GET_MEMCONF	58
-+
-+#define PROM_VEC		(u64 *)CKSEG1ADDR(0x1fc00000)
-+#define PROM_ENTRY(x)		(PROM_VEC + (x))
-+
-+
-+#undef DEBUG
-+#ifdef DEBUG
-+#define DBG_PRINTF(x...)     prom_printf(x)
-+#else
-+#define DBG_PRINTF(x...)
-+#endif
-+
-+static int *(*__prom_putchar)(int)        = (int *(*)(int))PROM_ENTRY(PROM_PUTCHAR);
-+static char *(*__prom_getenv)(char *)     = (char *(*)(char *))PROM_ENTRY(PROM_GETENV);
-+static void (*__prom_get_memconf)(void *) = (void (*)(void *))PROM_ENTRY(PROM_GET_MEMCONF);
-+
-+char *prom_getenv (char *s)
-+{
-+	return __prom_getenv(s);
-+}
-+
-+void prom_printf(char *fmt, ...)
-+{
-+	va_list args;
-+	char ppbuf[1024];
-+	char *bptr;
-+
-+	va_start(args, fmt);
-+	vsprintf(ppbuf, fmt, args);
-+
-+	bptr = ppbuf;
-+
-+	while (*bptr != 0) {
-+		if (*bptr == '\n')
-+			__prom_putchar('\r');
-+
-+		__prom_putchar(*bptr++);
-+	}
-+	va_end(args);
-+}
-+
-+unsigned long prom_free_prom_memory(void)
-+{
-+	return 0;
-+}
-+
-+/*
-+ * /proc/cpuinfo system type
-+ *
-+ */
-+static const char *systype = "Unknown";
-+const char *get_system_type(void)
-+{
-+	return systype;
-+}
-+
-+#define SNI_IDPROM_BASE                0xbff00000
-+#define SNI_IDPROM_MEMSIZE             (SNI_IDPROM_BASE+0x28)  /* Memsize in 16MB quantities */
-+#define SNI_IDPROM_BRDTYPE             (SNI_IDPROM_BASE+0x29)  /* Board Type */
-+#define SNI_IDPROM_CPUTYPE             (SNI_IDPROM_BASE+0x30)  /* CPU Type */
-+
-+#define SNI_IDPROM_SIZE	0x1000
-+
-+#ifdef DEBUG
-+static void sni_idprom_dump(void)
-+{
-+	int	i;
-+
-+	prom_printf("SNI IDProm dump (first 128byte):\n");
-+	for(i=0;i<128;i++) {
-+		if (i%16 == 0)
-+			prom_printf("%04x ", i);
-+
-+		prom_printf("%02x ", *(unsigned char *) (SNI_IDPROM_BASE+i));
-+
-+		if (i%16 == 15)
-+			prom_printf("\n");
-+	}
-+}
-+#endif
-+
-+static void sni_mem_init(void )
-+{
-+	int i, memsize;
-+	struct membank {
-+	        u32		size;
-+	        u32		base;
-+	        u32		size2;
-+	        u32		pad1;
-+	        u32		pad2;
-+	} memconf[8];
-+
-+	/* MemSIZE from prom in 16MByte chunks */
-+	memsize=*((unsigned char *) SNI_IDPROM_MEMSIZE) * 16;
-+
-+	DBG_PRINTF("IDProm memsize: %lu MByte\n", memsize);
-+
-+	/* get memory bank layout from prom */
-+	__prom_get_memconf(&memconf);
-+
-+	DBG_PRINTF("prom_get_mem_conf memory configuration:\n");
-+	for(i=0;i<8 && memconf[i].size;i++) {
-+		prom_printf("Bank%d: %08x @ %08x\n", i,
-+			memconf[i].size, memconf[i].base);
-+		add_memory_region(memconf[i].base, memconf[i].size, BOOT_MEM_RAM);
-+	}
-+}
-+
-+void __init prom_init(void)
-+{
-+	int argc = fw_arg0;
-+	char **argv = (void *)fw_arg1;
-+	unsigned int sni_brd_type = *(unsigned char *) SNI_IDPROM_BRDTYPE;
-+	int i;
-+
-+	DBG_PRINTF("Found SNI brdtype %02x\n", sni_brd_type);
-+
-+#ifdef DEBUG
-+	sni_idprom_dump();
-+#endif
-+	sni_mem_init();
-+
-+	/* copy prom cmdline parameters to kernel cmdline */
-+	for (i = 1; i < argc; i++) {
-+		strcat(arcs_cmdline, argv[i]);
-+		if (i < (argc - 1))
-+			strcat(arcs_cmdline, " ");
-+	}
-+}
-+
-diff -Naur linux-2.6.17.orig/arch/mips/tx4927/common/tx4927_setup.c linux-2.6.17/arch/mips/tx4927/common/tx4927_setup.c
---- linux-2.6.17.orig/arch/mips/tx4927/common/tx4927_setup.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/tx4927/common/tx4927_setup.c	2006-06-19 18:16:13.000000000 -0700
-@@ -64,7 +64,7 @@
- }
- 
- 
--void __init plat_setup(void)
-+void __init plat_mem_setup(void)
- {
- 	board_time_init = tx4927_time_init;
- 	board_timer_setup = tx4927_timer_setup;
-diff -Naur linux-2.6.17.orig/arch/mips/tx4938/common/setup.c linux-2.6.17/arch/mips/tx4938/common/setup.c
---- linux-2.6.17.orig/arch/mips/tx4938/common/setup.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/tx4938/common/setup.c	2006-06-19 18:16:13.000000000 -0700
-@@ -61,7 +61,7 @@
- }
- 
- void __init
--plat_setup(void)
-+plat_mem_setup(void)
- {
- 	board_time_init = tx4938_time_init;
- 	board_timer_setup = tx4938_timer_setup;
-diff -Naur linux-2.6.17.orig/arch/mips/tx4938/toshiba_rbtx4938/setup.c linux-2.6.17/arch/mips/tx4938/toshiba_rbtx4938/setup.c
---- linux-2.6.17.orig/arch/mips/tx4938/toshiba_rbtx4938/setup.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/tx4938/toshiba_rbtx4938/setup.c	2006-06-19 18:16:13.000000000 -0700
-@@ -664,7 +664,10 @@
- 
- static char pcode_str[8];
- static struct resource tx4938_reg_resource = {
--	pcode_str, TX4938_REG_BASE, TX4938_REG_BASE+TX4938_REG_SIZE, IORESOURCE_MEM
-+	.start	= TX4938_REG_BASE,
-+	.end	= TX4938_REG_BASE + TX4938_REG_SIZE,
-+	.name	= pcode_str,
-+	.flags	= IORESOURCE_MEM
- };
- 
- void __init tx4938_board_setup(void)
-diff -Naur linux-2.6.17.orig/arch/mips/vr41xx/common/init.c linux-2.6.17/arch/mips/vr41xx/common/init.c
---- linux-2.6.17.orig/arch/mips/vr41xx/common/init.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/vr41xx/common/init.c	2006-06-19 18:16:13.000000000 -0700
-@@ -58,7 +58,7 @@
- 	board_timer_setup = setup_timer_irq;
- }
- 
--void __init plat_setup(void)
-+void __init plat_mem_setup(void)
- {
- 	vr41xx_calculate_clock_frequency();
- 
-diff -Naur linux-2.6.17.orig/arch/mips/vr41xx/Kconfig linux-2.6.17/arch/mips/vr41xx/Kconfig
---- linux-2.6.17.orig/arch/mips/vr41xx/Kconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/arch/mips/vr41xx/Kconfig	2006-06-19 18:16:13.000000000 -0700
-@@ -4,7 +4,6 @@
- 	select DMA_NONCOHERENT
- 	select IRQ_CPU
- 	select ISA
--	select SYS_HAS_CPU_VR41XX
- 	select SYS_SUPPORTS_32BIT_KERNEL
- 	select SYS_SUPPORTS_LITTLE_ENDIAN
- 
-@@ -14,18 +13,15 @@
- 	select DMA_NONCOHERENT
- 	select IRQ_CPU
- 	select ISA
--	select SYS_HAS_CPU_VR41XX
- 	select SYS_SUPPORTS_32BIT_KERNEL
- 	select SYS_SUPPORTS_LITTLE_ENDIAN
- 
- config NEC_CMBVR4133
- 	bool "Support for NEC CMB-VR4133"
- 	depends on MACH_VR41XX
--	select CPU_VR41XX
- 	select DMA_NONCOHERENT
- 	select IRQ_CPU
- 	select HW_HAS_PCI
--	select SYS_HAS_CPU_VR41XX
- 	select SYS_SUPPORTS_32BIT_KERNEL
- 	select SYS_SUPPORTS_LITTLE_ENDIAN
- 
-@@ -41,7 +37,6 @@
- 	select DMA_NONCOHERENT
- 	select HW_HAS_PCI
- 	select IRQ_CPU
--	select SYS_HAS_CPU_VR41XX
- 	select SYS_SUPPORTS_32BIT_KERNEL
- 	select SYS_SUPPORTS_LITTLE_ENDIAN
- 	help
-@@ -74,7 +69,6 @@
- 	select DMA_NONCOHERENT
- 	select HW_HAS_PCI
- 	select IRQ_CPU
--	select SYS_HAS_CPU_VR41XX
- 	select SYS_SUPPORTS_32BIT_KERNEL
- 	select SYS_SUPPORTS_LITTLE_ENDIAN
- 
-@@ -84,7 +78,6 @@
- 	select DMA_NONCOHERENT
- 	select HW_HAS_PCI
- 	select IRQ_CPU
--	select SYS_HAS_CPU_VR41XX
- 	select SYS_SUPPORTS_32BIT_KERNEL
- 	select SYS_SUPPORTS_LITTLE_ENDIAN
- 
-diff -Naur linux-2.6.17.orig/Documentation/feature-removal-schedule.txt linux-2.6.17/Documentation/feature-removal-schedule.txt
---- linux-2.6.17.orig/Documentation/feature-removal-schedule.txt	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/Documentation/feature-removal-schedule.txt	2006-06-19 18:16:13.000000000 -0700
-@@ -147,16 +147,6 @@
- 
- ---------------------------
- 
--What:	au1x00_uart driver
--When:	January 2006
--Why:	The 8250 serial driver now has the ability to deal with the differences
--	between the standard 8250 family of UARTs and their slightly strange
--	brother on Alchemy SOCs.  The loss of features is not considered an
--	issue.
--Who:	Ralf Baechle <ralf@linux-mips.org>
--
-----------------------------
--
- What:   eepro100 network driver
- When:   January 2007
- Why:    replaced by the e100 driver
-@@ -212,15 +202,6 @@
- 
- ---------------------------
- 
--What:	Support for NEC DDB5074 and DDB5476 evaluation boards.
--When:	June 2006
--Why:	Board specific code doesn't build anymore since ~2.6.0 and no
--	users have complained indicating there is no more need for these
--	boards.  This should really be considered a last call.
--Who:	Ralf Baechle <ralf@linux-mips.org>
--
-----------------------------
--
- What:	USB driver API moves to EXPORT_SYMBOL_GPL
- When:	Febuary 2008
- Files:	include/linux/usb.h, drivers/usb/core/driver.c
-diff -Naur linux-2.6.17.orig/drivers/char/au1000_gpio.c linux-2.6.17/drivers/char/au1000_gpio.c
---- linux-2.6.17.orig/drivers/char/au1000_gpio.c	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/drivers/char/au1000_gpio.c	2006-06-19 18:16:13.000000000 -0700
-@@ -0,0 +1,266 @@
-+/*
-+ * FILE NAME au1000_gpio.c
-+ *
-+ * BRIEF MODULE DESCRIPTION
-+ *  Driver for Alchemy Au1000 GPIO.
-+ *
-+ *  Author: MontaVista Software, Inc.  <source@mvista.com>
-+ *          Steve Longerbeam <stevel@mvista.com>
-+ *
-+ * Copyright 2001 MontaVista Software Inc.
-+ *
-+ *  This program is free software; you can redistribute  it and/or modify it
-+ *  under  the terms of  the GNU General  Public License as published by the
-+ *  Free Software Foundation;  either version 2 of the  License, or (at your
-+ *  option) any later version.
-+ *
-+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
-+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
-+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
-+ *  NO  EVENT  SHALL   THE AUTHOR  BE	LIABLE FOR ANY   DIRECT, INDIRECT,
-+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
-+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
-+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ *  You should have received a copy of the  GNU General Public License along
-+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
-+ *  675 Mass Ave, Cambridge, MA 02139, USA.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/config.h>
-+#include <linux/types.h>
-+#include <linux/kernel.h>
-+#include <linux/miscdevice.h>
-+#include <linux/init.h>
-+#include <asm/uaccess.h>
-+#include <asm/io.h>
-+#include <asm/au1000.h>
-+#include <asm/au1000_gpio.h>
-+
-+#define VERSION "0.01"
-+
-+static const struct {
-+	u32 active_hi;
-+	u32 avail_mask;
-+} pinfunc_to_avail[15] = {
-+	{1,  0x7<<16},   // 0  = SSI0     / GPIO[18:16]
-+	{-1, 0},         // 1  = AC97     / SSI1
-+	{1,  1<<19},     // 2  = IRDA     / GPIO19
-+	{1,  1<<20},     // 3  = UART0    / GPIO20
-+	{1,  0x1f<<24},  // 4  = NIC2     / GPIO[28:24]
-+	{1,  0x7<<29},   // 5  = I2S      / GPIO[31:29]
-+	{0,  1<<8},      // 6  = I2SDI    / GPIO8
-+	{0,  0x3f<<9},   // 7  = UART3    / GPIO[14:9]
-+	{0,  1<<15},     // 8  = IRFIRSEL / GPIO15
-+	{0,  1<<2},      // 9  = EXTCLK0 or OSC / GPIO2
-+	{0,  1<<3},      // 10 = EXTCLK1  / GPIO3
-+	{0,  1<<6},      // 11 = SMROMCKE / GPIO6
-+	{1,  1<<21},     // 12 = UART1    / GPIO21
-+	{1,  1<<22},     // 13 = UART2    / GPIO22
-+	{1,  1<<23}      // 14 = UART3    / GPIO23
-+};
-+
-+	
-+u32 get_au1000_avail_gpio_mask(void)
-+{
-+	int i;
-+	u32 pinfunc = inl(SYS_PINFUNC);
-+	u32 avail_mask = 0; // start with no gpio available
-+
-+	// first, check for GPIO's reprogrammed as peripheral pins
-+	for (i=0; i<15; i++) {
-+		if (pinfunc_to_avail[i].active_hi < 0)
-+			continue;
-+		if (!(pinfunc_to_avail[i].active_hi ^
-+		      ((pinfunc & (1<<i)) ? 1:0)))
-+			avail_mask |= pinfunc_to_avail[i].avail_mask;
-+	}
-+
-+	// check for GPIO's used as interrupt sources
-+	avail_mask &= ~(inl(IC1_MASKRD) &
-+			(inl(IC1_CFG0RD) | inl(IC1_CFG1RD)));
-+
-+#ifdef CONFIG_USB_OHCI
-+	avail_mask &= ~((1<<4) | (1<<11));
-+#ifndef CONFIG_AU1X00_USB_DEVICE
-+	avail_mask &= ~((1<<5) | (1<<13));
-+#endif
-+#endif
-+	
-+	return avail_mask;
-+}
-+
-+
-+/*
-+ * Tristate the requested GPIO pins specified in data.
-+ * Only available GPIOs will be tristated.
-+ */
-+int au1000gpio_tristate(u32 data)
-+{
-+	data &= get_au1000_avail_gpio_mask();
-+
-+	if (data)
-+		outl(data, SYS_TRIOUTCLR);
-+
-+	return 0;
-+}
-+
-+
-+/*
-+ * Return the pin state. Pins configured as outputs will return
-+ * the output state, and pins configured as inputs (tri-stated)
-+ * will return input pin state.
-+ */
-+int au1000gpio_in(u32 *data)
-+{
-+	*data = inl(SYS_PINSTATERD);
-+	return 0;
-+}
-+
-+
-+/*
-+ * Set/clear GPIO pins. Only available GPIOs will be affected.
-+ */
-+int au1000gpio_set(u32 data)
-+{
-+	data &= get_au1000_avail_gpio_mask();
-+
-+	if (data)
-+		outl(data, SYS_OUTPUTSET);
-+	return 0;
-+}
-+
-+int au1000gpio_clear(u32 data)
-+{
-+	data &= get_au1000_avail_gpio_mask();
-+
-+	if (data)
-+		outl(data, SYS_OUTPUTCLR);
-+	return 0;
-+}
-+
-+/*
-+ * Output data to GPIO pins. Only available GPIOs will be affected.
-+ */
-+int au1000gpio_out(u32 data)
-+{
-+	au1000gpio_set(data);
-+	au1000gpio_clear(~data);
-+	return 0;
-+}
-+
-+
-+EXPORT_SYMBOL(get_au1000_avail_gpio_mask);
-+EXPORT_SYMBOL(au1000gpio_tristate);
-+EXPORT_SYMBOL(au1000gpio_in);
-+EXPORT_SYMBOL(au1000gpio_set);
-+EXPORT_SYMBOL(au1000gpio_clear);
-+EXPORT_SYMBOL(au1000gpio_out);
-+
-+
-+static int au1000gpio_open(struct inode *inode, struct file *file)
-+{
-+	return 0;
-+}
-+
-+
-+static int au1000gpio_release(struct inode *inode, struct file *file)
-+{
-+	return 0;
-+}
-+
-+
-+static int au1000gpio_ioctl(struct inode *inode, struct file *file,
-+			    unsigned int cmd, unsigned long arg)
-+{
-+	int status;
-+	u32 val;
-+	
-+	switch(cmd) {
-+	case AU1000GPIO_IN:
-+		
-+		status = au1000gpio_in(&val);
-+		if (status != 0)
-+			return status;
-+
-+		return put_user(val, (u32 *)arg);
-+
-+	case AU1000GPIO_OUT:
-+
-+		if (get_user(val, (u32 *)arg)) 
-+			return -EFAULT;
-+
-+		return au1000gpio_out(val);
-+
-+	case AU1000GPIO_SET:
-+
-+		if (get_user(val, (u32 *)arg)) 
-+			return -EFAULT;
-+
-+		return au1000gpio_set(val);
-+		
-+	case AU1000GPIO_CLEAR:
-+
-+		if (get_user(val, (u32 *)arg)) 
-+			return -EFAULT;
-+
-+		return au1000gpio_clear(val);
-+
-+	case AU1000GPIO_TRISTATE:
-+
-+		if (get_user(val, (u32 *)arg)) 
-+			return -EFAULT;
-+
-+		return au1000gpio_tristate(val);
-+
-+	case AU1000GPIO_AVAIL_MASK:
-+		
-+		return put_user(get_au1000_avail_gpio_mask(),
-+				(u32 *)arg);
-+		
-+	default:
-+		return -ENOIOCTLCMD;
-+
-+	}
-+
-+	return 0;
-+}
-+
-+
-+static struct file_operations au1000gpio_fops =
-+{
-+	.owner		= THIS_MODULE,
-+	.ioctl		= au1000gpio_ioctl,
-+	.open		= au1000gpio_open,
-+	.release	= au1000gpio_release,
-+};
-+
-+
-+static struct miscdevice au1000gpio_miscdev =
-+{
-+	MISC_DYNAMIC_MINOR,
-+	"au1000_gpio",
-+	&au1000gpio_fops
-+};
-+
-+
-+int __init au1000gpio_init(void)
-+{
-+	misc_register(&au1000gpio_miscdev);
-+	printk("Au1000 gpio driver, version %s\n", VERSION);
-+	return 0;
-+}	
-+
-+
-+void __exit au1000gpio_exit(void)
-+{
-+	misc_deregister(&au1000gpio_miscdev);
-+}
-+
-+
-+module_init(au1000gpio_init);
-+module_exit(au1000gpio_exit);
-diff -Naur linux-2.6.17.orig/drivers/char/au1000_ts.c linux-2.6.17/drivers/char/au1000_ts.c
---- linux-2.6.17.orig/drivers/char/au1000_ts.c	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/drivers/char/au1000_ts.c	2006-06-19 18:16:13.000000000 -0700
-@@ -0,0 +1,677 @@
-+/*
-+ *      au1000_ts.c  --  Touch screen driver for the Alchemy Au1000's
-+ *                       SSI Port 0 talking to the ADS7846 touch screen
-+ *                       controller.
-+ *
-+ * Copyright 2001 MontaVista Software Inc.
-+ * Author: MontaVista Software, Inc.
-+ *         	stevel@mvista.com or source@mvista.com
-+ *
-+ *  This program is free software; you can redistribute  it and/or modify it
-+ *  under  the terms of  the GNU General  Public License as published by the
-+ *  Free Software Foundation;  either version 2 of the  License, or (at your
-+ *  option) any later version.
-+ *
-+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
-+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
-+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
-+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
-+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
-+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
-+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ *  You should have received a copy of the  GNU General Public License along
-+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
-+ *  675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ * Notes:
-+ *
-+ *  Revision history
-+ *    06.27.2001  Initial version
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/version.h>
-+
-+#include <linux/init.h>
-+#include <linux/fs.h>
-+#include <linux/delay.h>
-+#include <linux/poll.h>
-+#include <linux/string.h>
-+#include <linux/ioport.h>       /* request_region */
-+#include <linux/interrupt.h>    /* mark_bh */
-+#include <asm/uaccess.h>        /* get_user,copy_to_user */
-+#include <asm/io.h>
-+#include <asm/au1000.h>
-+
-+#define TS_NAME "au1000-ts"
-+#define TS_MAJOR 11
-+
-+#define PFX TS_NAME
-+#define AU1000_TS_DEBUG 1
-+
-+#ifdef AU1000_TS_DEBUG
-+#define dbg(format, arg...) printk(KERN_DEBUG PFX ": " format "\n" , ## arg)
-+#else
-+#define dbg(format, arg...) do {} while (0)
-+#endif
-+#define err(format, arg...) printk(KERN_ERR PFX ": " format "\n" , ## arg)
-+#define info(format, arg...) printk(KERN_INFO PFX ": " format "\n" , ## arg)
-+#define warn(format, arg...) printk(KERN_WARNING PFX ": " format "\n" , ## arg)
-+
-+
-+// SSI Status register bit defines
-+#define SSISTAT_BF    (1<<4)
-+#define SSISTAT_OF    (1<<3)
-+#define SSISTAT_UF    (1<<2)
-+#define SSISTAT_DONE  (1<<1)
-+#define SSISTAT_BUSY  (1<<0)
-+
-+// SSI Interrupt Pending and Enable register bit defines
-+#define SSIINT_OI     (1<<3)
-+#define SSIINT_UI     (1<<2)
-+#define SSIINT_DI     (1<<1)
-+
-+// SSI Address/Data register bit defines
-+#define SSIADAT_D         (1<<24)
-+#define SSIADAT_ADDR_BIT  16
-+#define SSIADAT_ADDR_MASK (0xff<<SSIADAT_ADDR_BIT)
-+#define SSIADAT_DATA_BIT  0
-+#define SSIADAT_DATA_MASK (0xfff<<SSIADAT_DATA_BIT)
-+
-+// SSI Enable register bit defines
-+#define SSIEN_CD (1<<1)
-+#define SSIEN_E  (1<<0)
-+
-+// SSI Config register bit defines
-+#define SSICFG_AO (1<<24)
-+#define SSICFG_DO (1<<23)
-+#define SSICFG_ALEN_BIT 20
-+#define SSICFG_ALEN_MASK (0x7<<SSICFG_ALEN_BIT)
-+#define SSICFG_DLEN_BIT 16
-+#define SSICFG_DLEN_MASK (0xf<<SSICFG_DLEN_BIT)
-+#define SSICFG_DD (1<<11)
-+#define SSICFG_AD (1<<10)
-+#define SSICFG_BM_BIT 8
-+#define SSICFG_BM_MASK (0x3<<SSICFG_BM_BIT)
-+#define SSICFG_CE (1<<7)
-+#define SSICFG_DP (1<<6)
-+#define SSICFG_DL (1<<5)
-+#define SSICFG_EP (1<<4)
-+
-+// Bus Turnaround Selection
-+#define SCLK_HOLD_HIGH 0
-+#define SCLK_HOLD_LOW  1
-+#define SCLK_CYCLE     2
-+
-+/*
-+ * Default config for SSI0:
-+ *
-+ *   - transmit MSBit first
-+ *   - expect MSBit first on data receive
-+ *   - address length 7 bits
-+ *   - expect data length 12 bits
-+ *   - do not disable Direction bit
-+ *   - do not disable Address bits
-+ *   - SCLK held low during bus turnaround
-+ *   - Address and Data bits clocked out on falling edge of SCLK
-+ *   - Direction bit high is a read, low is a write
-+ *   - Direction bit precedes Address bits
-+ *   - Active low enable signal
-+ */
-+
-+#define DEFAULT_SSI_CONFIG \
-+    (SSICFG_AO | SSICFG_DO | (6<<SSICFG_ALEN_BIT) | (11<<SSICFG_DLEN_BIT) |\
-+    (SCLK_HOLD_LOW<<SSICFG_BM_BIT) | SSICFG_DP | SSICFG_EP)
-+
-+
-+// ADS7846 Control Byte bit defines
-+#define ADS7846_ADDR_BIT  4
-+#define ADS7846_ADDR_MASK (0x7<<ADS7846_ADDR_BIT)
-+#define   ADS7846_MEASURE_X  (0x5<<ADS7846_ADDR_BIT)
-+#define   ADS7846_MEASURE_Y  (0x1<<ADS7846_ADDR_BIT)
-+#define   ADS7846_MEASURE_Z1 (0x3<<ADS7846_ADDR_BIT)
-+#define   ADS7846_MEASURE_Z2 (0x4<<ADS7846_ADDR_BIT)
-+#define ADS7846_8BITS     (1<<3)
-+#define ADS7846_12BITS    0
-+#define ADS7846_SER       (1<<2)
-+#define ADS7846_DFR       0
-+#define ADS7846_PWR_BIT   0
-+#define   ADS7846_PD      0
-+#define   ADS7846_ADC_ON  (0x1<<ADS7846_PWR_BIT)
-+#define   ADS7846_REF_ON  (0x2<<ADS7846_PWR_BIT)
-+#define   ADS7846_REF_ADC_ON (0x3<<ADS7846_PWR_BIT)
-+
-+#define MEASURE_12BIT_X \
-+    (ADS7846_MEASURE_X | ADS7846_12BITS | ADS7846_DFR | ADS7846_PD)
-+#define MEASURE_12BIT_Y \
-+    (ADS7846_MEASURE_Y | ADS7846_12BITS | ADS7846_DFR | ADS7846_PD)
-+#define MEASURE_12BIT_Z1 \
-+    (ADS7846_MEASURE_Z1 | ADS7846_12BITS | ADS7846_DFR | ADS7846_PD)
-+#define MEASURE_12BIT_Z2 \
-+    (ADS7846_MEASURE_Z2 | ADS7846_12BITS | ADS7846_DFR | ADS7846_PD)
-+
-+typedef enum {
-+	IDLE = 0,
-+	ACQ_X,
-+	ACQ_Y,
-+	ACQ_Z1,
-+	ACQ_Z2
-+} acq_state_t;
-+
-+/* +++++++++++++ Lifted from include/linux/h3600_ts.h ++++++++++++++*/
-+typedef struct {
-+	unsigned short pressure;  // touch pressure
-+	unsigned short x;         // calibrated X
-+	unsigned short y;         // calibrated Y
-+	unsigned short millisecs; // timestamp of this event
-+} TS_EVENT;
-+
-+typedef struct {
-+	int xscale;
-+	int xtrans;
-+	int yscale;
-+	int ytrans;
-+	int xyswap;
-+} TS_CAL;
-+
-+/* Use 'f' as magic number */
-+#define IOC_MAGIC  'f'
-+
-+#define TS_GET_RATE             _IO(IOC_MAGIC, 8)
-+#define TS_SET_RATE             _IO(IOC_MAGIC, 9)
-+#define TS_GET_CAL              _IOR(IOC_MAGIC, 10, TS_CAL)
-+#define TS_SET_CAL              _IOW(IOC_MAGIC, 11, TS_CAL)
-+
-+/* +++++++++++++ Done lifted from include/linux/h3600_ts.h +++++++++*/
-+
-+
-+#define EVENT_BUFSIZE 128
-+
-+/*
-+ * Which pressure equation to use from ADS7846 datasheet.
-+ * The first equation requires knowing only the X plate
-+ * resistance, but needs 4 measurements (X, Y, Z1, Z2).
-+ * The second equation requires knowing both X and Y plate
-+ * resistance, but only needs 3 measurements (X, Y, Z1).
-+ * The second equation is preferred because of the shorter
-+ * acquisition time required.
-+ */
-+enum {
-+	PRESSURE_EQN_1 = 0,
-+	PRESSURE_EQN_2
-+};
-+
-+
-+/*
-+ * The touch screen's X and Y plate resistances, used by
-+ * pressure equations.
-+ */
-+#define DEFAULT_X_PLATE_OHMS 580
-+#define DEFAULT_Y_PLATE_OHMS 580
-+
-+/*
-+ * Pen up/down pressure resistance thresholds.
-+ *
-+ * FIXME: these are bogus and will have to be found empirically.
-+ *
-+ * These are hysteresis points. If pen state is up and pressure
-+ * is greater than pen-down threshold, pen transitions to down.
-+ * If pen state is down and pressure is less than pen-up threshold,
-+ * pen transitions to up. If pressure is in-between, pen status
-+ * doesn't change.
-+ *
-+ * This wouldn't be needed if PENIRQ* from the ADS7846 were
-+ * routed to an interrupt line on the Au1000. This would issue
-+ * an interrupt when the panel is touched.
-+ */
-+#define DEFAULT_PENDOWN_THRESH_OHMS 100
-+#define DEFAULT_PENUP_THRESH_OHMS    80
-+
-+typedef struct {
-+	int baudrate;
-+	u32 clkdiv;
-+	acq_state_t acq_state;            // State of acquisition state machine
-+	int x_raw, y_raw, z1_raw, z2_raw; // The current raw acquisition values
-+	TS_CAL cal;                       // Calibration values
-+	// The X and Y plate resistance, needed to calculate pressure
-+	int x_plate_ohms, y_plate_ohms;
-+	// pressure resistance at which pen is considered down/up
-+	int pendown_thresh_ohms;
-+	int penup_thresh_ohms;
-+	int pressure_eqn;                 // eqn to use for pressure calc
-+	int pendown;                      // 1 = pen is down, 0 = pen is up
-+	TS_EVENT event_buf[EVENT_BUFSIZE];// The event queue
-+	int nextIn, nextOut;
-+	int event_count;
-+	struct fasync_struct *fasync;     // asynch notification
-+	struct timer_list acq_timer;      // Timer for triggering acquisitions
-+	wait_queue_head_t wait;           // read wait queue
-+	spinlock_t lock;
-+	struct tq_struct chug_tq;
-+} au1000_ts_t;
-+
-+static au1000_ts_t au1000_ts;
-+
-+
-+static inline u32
-+calc_clkdiv(int baud)
-+{
-+	u32 sys_busclk =
-+		(get_au1000_speed() / (int)(inl(PM_POWERUP_CONTROL)&0x03) + 2);
-+	return (sys_busclk / (2 * baud)) - 1;
-+}
-+
-+static inline int
-+calc_baudrate(u32 clkdiv)
-+{
-+	u32 sys_busclk =
-+		(get_au1000_speed() / (int)(inl(PM_POWERUP_CONTROL)&0x03) + 2);
-+	return sys_busclk / (2 * (clkdiv + 1));
-+}
-+
-+
-+/*
-+ * This is a bottom-half handler that is scheduled after
-+ * raw X,Y,Z1,Z2 coordinates have been acquired, and does
-+ * the following:
-+ *
-+ *   - computes touch screen pressure resistance
-+ *   - if pressure is above a threshold considered to be pen-down:
-+ *         - compute calibrated X and Y coordinates
-+ *         - queue a new TS_EVENT
-+ *         - signal asynchronously and wake up any read
-+ */
-+static void
-+chug_raw_data(void* private)
-+{
-+	au1000_ts_t* ts = (au1000_ts_t*)private;
-+	TS_EVENT event;
-+	int Rt, Xcal, Ycal;
-+	unsigned long flags;
-+
-+	// timestamp this new event.
-+	event.millisecs = jiffies;
-+
-+	// Calculate touch pressure resistance
-+	if (ts->pressure_eqn == PRESSURE_EQN_2) {
-+		Rt = (ts->x_plate_ohms * ts->x_raw *
-+		      (4096 - ts->z1_raw)) / ts->z1_raw;
-+		Rt -= (ts->y_plate_ohms * ts->y_raw);
-+		Rt = (Rt + 2048) >> 12; // round up to nearest ohm
-+	} else {
-+		Rt = (ts->x_plate_ohms * ts->x_raw *
-+		      (ts->z2_raw - ts->z1_raw)) / ts->z1_raw;
-+		Rt = (Rt + 2048) >> 12; // round up to nearest ohm
-+	}
-+
-+	// hysteresis
-+	if (!ts->pendown && Rt > ts->pendown_thresh_ohms)
-+		ts->pendown = 1;
-+	else if (ts->pendown && Rt < ts->penup_thresh_ohms)
-+		ts->pendown = 0;
-+
-+	if (ts->pendown) {
-+		// Pen is down
-+		// Calculate calibrated X,Y
-+		Xcal = ((ts->cal.xscale * ts->x_raw) >> 8) + ts->cal.xtrans;
-+		Ycal = ((ts->cal.yscale * ts->y_raw) >> 8) + ts->cal.ytrans;
-+
-+		event.x = (unsigned short)Xcal;
-+		event.y = (unsigned short)Ycal;
-+		event.pressure = (unsigned short)Rt;
-+
-+		// add this event to the event queue
-+		spin_lock_irqsave(&ts->lock, flags);
-+		ts->event_buf[ts->nextIn++] = event;
-+		if (ts->nextIn == EVENT_BUFSIZE)
-+			ts->nextIn = 0;
-+		if (ts->event_count < EVENT_BUFSIZE) {
-+			ts->event_count++;
-+		} else {
-+			// throw out the oldest event
-+			if (++ts->nextOut == EVENT_BUFSIZE)
-+				ts->nextOut = 0;
-+		}
-+		spin_unlock_irqrestore(&ts->lock, flags);
-+
-+		// async notify
-+		if (ts->fasync)
-+			kill_fasync(&ts->fasync, SIGIO, POLL_IN);
-+		// wake up any read call
-+		if (waitqueue_active(&ts->wait))
-+			wake_up_interruptible(&ts->wait);
-+	}
-+}
-+
-+
-+/*
-+ * Raw X,Y,pressure acquisition timer function. This triggers
-+ * the start of a new acquisition. Its duration between calls
-+ * is the touch screen polling rate.
-+ */
-+static void
-+au1000_acq_timer(unsigned long data)
-+{
-+	au1000_ts_t* ts = (au1000_ts_t*)data;
-+	unsigned long flags;
-+
-+	spin_lock_irqsave(&ts->lock, flags);
-+
-+	// start acquisition with X coordinate
-+	ts->acq_state = ACQ_X;
-+	// start me up
-+	outl(SSIADAT_D | (MEASURE_12BIT_X << SSIADAT_ADDR_BIT), SSI0_ADATA);
-+
-+	// schedule next acquire
-+	ts->acq_timer.expires = jiffies + HZ / 100;
-+	add_timer(&ts->acq_timer);
-+
-+	spin_unlock_irqrestore(&ts->lock, flags);
-+}
-+
-+static void
-+ssi0_interrupt(int irq, void *dev_id, struct pt_regs *regs)
-+{
-+	au1000_ts_t *ts = (au1000_ts_t*)dev_id;
-+	u32 stat, int_stat, data;
-+
-+	spin_lock(&ts->lock);
-+
-+	stat = inl(SSI0_STATUS);
-+	// clear sticky status bits
-+	outl(stat & (SSISTAT_OF|SSISTAT_UF|SSISTAT_DONE), SSI0_STATUS);
-+
-+	int_stat = inl(SSI0_INT);
-+	// clear sticky intr status bits
-+	outl(int_stat & (SSIINT_OI|SSIINT_UI|SSIINT_DI), SSI0_INT);
-+
-+	if ((int_stat & (SSIINT_OI|SSIINT_UI|SSIINT_DI)) != SSIINT_DI) {
-+		if (int_stat & SSIINT_OI)
-+			err("overflow");
-+		if (int_stat & SSIINT_UI)
-+			err("underflow");
-+		spin_unlock(&ts->lock);
-+		return;
-+	}
-+
-+	data = inl(SSI0_ADATA) & SSIADAT_DATA_MASK;
-+
-+	switch (ts->acq_state) {
-+	case IDLE:
-+		break;
-+	case ACQ_X:
-+		ts->x_raw = data;
-+		ts->acq_state = ACQ_Y;
-+		// trigger Y acq
-+		outl(SSIADAT_D | (MEASURE_12BIT_Y << SSIADAT_ADDR_BIT),
-+		     SSI0_ADATA);
-+		break;
-+	case ACQ_Y:
-+		ts->y_raw = data;
-+		ts->acq_state = ACQ_Z1;
-+		// trigger Z1 acq
-+		outl(SSIADAT_D | (MEASURE_12BIT_Z1 << SSIADAT_ADDR_BIT),
-+		     SSI0_ADATA);
-+		break;
-+	case ACQ_Z1:
-+		ts->z1_raw = data;
-+		if (ts->pressure_eqn == PRESSURE_EQN_2) {
-+			// don't acq Z2, using 2nd eqn for touch pressure
-+			ts->acq_state = IDLE;
-+			// got the raw stuff, now mark BH
-+			queue_task(&ts->chug_tq, &tq_immediate);
-+			mark_bh(IMMEDIATE_BH);
-+		} else {
-+			ts->acq_state = ACQ_Z2;
-+			// trigger Z2 acq
-+			outl(SSIADAT_D | (MEASURE_12BIT_Z2<<SSIADAT_ADDR_BIT),
-+			     SSI0_ADATA);
-+		}
-+		break;
-+	case ACQ_Z2:
-+		ts->z2_raw = data;
-+		ts->acq_state = IDLE;
-+		// got the raw stuff, now mark BH
-+		queue_task(&ts->chug_tq, &tq_immediate);
-+		mark_bh(IMMEDIATE_BH);
-+		break;
-+	}
-+
-+	spin_unlock(&ts->lock);
-+}
-+
-+
-+/* +++++++++++++ File operations ++++++++++++++*/
-+
-+static int
-+au1000_fasync(int fd, struct file *filp, int mode)
-+{
-+	au1000_ts_t* ts = (au1000_ts_t*)filp->private_data;
-+	return fasync_helper(fd, filp, mode, &ts->fasync);
-+}
-+
-+static int
-+au1000_ioctl(struct inode * inode, struct file *filp,
-+	     unsigned int cmd, unsigned long arg)
-+{
-+	au1000_ts_t* ts = (au1000_ts_t*)filp->private_data;
-+
-+	switch(cmd) {
-+	case TS_GET_RATE:       /* TODO: what is this? */
-+		break;
-+	case TS_SET_RATE:       /* TODO: what is this? */
-+		break;
-+	case TS_GET_CAL:
-+		copy_to_user((char *)arg, (char *)&ts->cal, sizeof(TS_CAL));
-+		break;
-+	case TS_SET_CAL:
-+		copy_from_user((char *)&ts->cal, (char *)arg, sizeof(TS_CAL));
-+		break;
-+	default:
-+		err("unknown cmd %04x", cmd);
-+		return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+
-+static unsigned int
-+au1000_poll(struct file * filp, poll_table * wait)
-+{
-+	au1000_ts_t* ts = (au1000_ts_t*)filp->private_data;
-+	poll_wait(filp, &ts->wait, wait);
-+	if (ts->event_count)
-+		return POLLIN | POLLRDNORM;
-+	return 0;
-+}
-+
-+static ssize_t
-+au1000_read(struct file * filp, char * buf, size_t count, loff_t * l)
-+{
-+	au1000_ts_t* ts = (au1000_ts_t*)filp->private_data;
-+	unsigned long flags;
-+	TS_EVENT event;
-+	int i;
-+
-+	if (ts->event_count == 0) {
-+		if (filp->f_flags & O_NONBLOCK)
-+			return -EAGAIN;
-+		interruptible_sleep_on(&ts->wait);
-+		if (signal_pending(current))
-+			return -ERESTARTSYS;
-+	}
-+
-+	for (i = count;
-+	     i >= sizeof(TS_EVENT);
-+	     i -= sizeof(TS_EVENT), buf += sizeof(TS_EVENT)) {
-+		if (ts->event_count == 0)
-+			break;
-+		spin_lock_irqsave(&ts->lock, flags);
-+		event = ts->event_buf[ts->nextOut++];
-+		if (ts->nextOut == EVENT_BUFSIZE)
-+			ts->nextOut = 0;
-+		if (ts->event_count)
-+			ts->event_count--;
-+		spin_unlock_irqrestore(&ts->lock, flags);
-+		copy_to_user(buf, &event, sizeof(TS_EVENT));
-+	}
-+
-+	return count - i;
-+}
-+
-+
-+static int
-+au1000_open(struct inode * inode, struct file * filp)
-+{
-+	au1000_ts_t* ts;
-+	unsigned long flags;
-+
-+	filp->private_data = ts = &au1000_ts;
-+
-+	spin_lock_irqsave(&ts->lock, flags);
-+
-+	// setup SSI0 config
-+	outl(DEFAULT_SSI_CONFIG, SSI0_CONFIG);
-+
-+	// clear out SSI0 status bits
-+	outl(SSISTAT_OF|SSISTAT_UF|SSISTAT_DONE, SSI0_STATUS);
-+	// clear out SSI0 interrupt pending bits
-+	outl(SSIINT_OI|SSIINT_UI|SSIINT_DI, SSI0_INT);
-+
-+	// enable SSI0 interrupts
-+	outl(SSIINT_OI|SSIINT_UI|SSIINT_DI, SSI0_INT_ENABLE);
-+
-+	/*
-+	 * init bh handler that chugs the raw data (calibrates and
-+	 * calculates touch pressure).
-+	 */
-+	ts->chug_tq.routine = chug_raw_data;
-+	ts->chug_tq.data = ts;
-+	ts->pendown = 0; // pen up
-+	
-+	// flush event queue
-+	ts->nextIn = ts->nextOut = ts->event_count = 0;
-+	
-+	// Start acquisition timer function
-+	init_timer(&ts->acq_timer);
-+	ts->acq_timer.function = au1000_acq_timer;
-+	ts->acq_timer.data = (unsigned long)ts;
-+	ts->acq_timer.expires = jiffies + HZ / 100;
-+	add_timer(&ts->acq_timer);
-+
-+	spin_unlock_irqrestore(&ts->lock, flags);
-+
-+	return 0;
-+}
-+
-+static int
-+au1000_release(struct inode * inode, struct file * filp)
-+{
-+	au1000_ts_t* ts = (au1000_ts_t*)filp->private_data;
-+	unsigned long flags;
-+	
-+	au1000_fasync(-1, filp, 0);
-+	del_timer_sync(&ts->acq_timer);
-+
-+	spin_lock_irqsave(&ts->lock, flags);
-+	// disable SSI0 interrupts
-+	outl(0, SSI0_INT_ENABLE);
-+	spin_unlock_irqrestore(&ts->lock, flags);
-+
-+	return 0;
-+}
-+
-+
-+static struct file_operations ts_fops = {
-+	.read           = au1000_read,
-+	.poll           = au1000_poll,
-+	.ioctl		= au1000_ioctl,
-+	.fasync         = au1000_fasync,
-+	.open		= au1000_open,
-+	.release	= au1000_release,
-+};
-+
-+/* +++++++++++++ End File operations ++++++++++++++*/
-+
-+
-+int __init
-+au1000ts_init_module(void)
-+{
-+	au1000_ts_t* ts = &au1000_ts;
-+	int ret;
-+
-+	/* register our character device */
-+	if ((ret = register_chrdev(TS_MAJOR, TS_NAME, &ts_fops)) < 0) {
-+		err("can't get major number");
-+		return ret;
-+	}
-+	info("registered");
-+
-+	memset(ts, 0, sizeof(au1000_ts_t));
-+	init_waitqueue_head(&ts->wait);
-+	spin_lock_init(&ts->lock);
-+
-+	if (!request_region(virt_to_phys((void*)SSI0_STATUS), 0x100, TS_NAME)) {
-+		err("SSI0 ports in use");
-+		return -ENXIO;
-+	}
-+
-+	if ((ret = request_irq(AU1000_SSI0_INT, ssi0_interrupt,
-+			       SA_SHIRQ | SA_INTERRUPT, TS_NAME, ts))) {
-+		err("could not get IRQ");
-+		return ret;
-+	}
-+
-+	// initial calibration values
-+	ts->cal.xscale = -93;
-+	ts->cal.xtrans = 346;
-+	ts->cal.yscale = -64;
-+	ts->cal.ytrans = 251;
-+
-+	// init pen up/down hysteresis points
-+	ts->pendown_thresh_ohms = DEFAULT_PENDOWN_THRESH_OHMS;
-+	ts->penup_thresh_ohms = DEFAULT_PENUP_THRESH_OHMS;
-+	ts->pressure_eqn = PRESSURE_EQN_2;
-+	// init X and Y plate resistances
-+	ts->x_plate_ohms = DEFAULT_X_PLATE_OHMS;
-+	ts->y_plate_ohms = DEFAULT_Y_PLATE_OHMS;
-+
-+	// set GPIO to SSI0 function
-+	outl(inl(PIN_FUNCTION) & ~1, PIN_FUNCTION);
-+	
-+	// enable SSI0 clock and bring SSI0 out of reset
-+	outl(0, SSI0_CONTROL);
-+	udelay(1000);
-+	outl(SSIEN_E, SSI0_CONTROL);
-+	udelay(100);
-+	
-+	// FIXME: is this a working baudrate?
-+	ts->clkdiv = 0;
-+	ts->baudrate = calc_baudrate(ts->clkdiv);
-+	outl(ts->clkdiv, SSI0_CLKDIV);
-+
-+	info("baudrate = %d Hz", ts->baudrate);
-+	
-+	return 0;
-+}
-+
-+void
-+au1000ts_cleanup_module(void)
-+{
-+	// disable clocks and hold in reset
-+	outl(SSIEN_CD, SSI0_CONTROL);
-+	free_irq(AU1000_SSI0_INT, &au1000_ts);
-+	release_region(virt_to_phys((void*)SSI0_STATUS), 0x100);
-+	unregister_chrdev(TS_MAJOR, TS_NAME);
-+}
-+
-+/* Module information */
-+MODULE_AUTHOR("Steve Longerbeam, stevel@mvista.com, www.mvista.com");
-+MODULE_DESCRIPTION("Au1000/ADS7846 Touch Screen Driver");
-+
-+module_init(au1000ts_init_module);
-+module_exit(au1000ts_cleanup_module);
-diff -Naur linux-2.6.17.orig/drivers/char/au1000_usbraw.c linux-2.6.17/drivers/char/au1000_usbraw.c
---- linux-2.6.17.orig/drivers/char/au1000_usbraw.c	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/drivers/char/au1000_usbraw.c	2006-06-19 18:16:13.000000000 -0700
-@@ -0,0 +1,573 @@
-+/*
-+ * BRIEF MODULE DESCRIPTION
-+ *	Au1x00 USB Device-Side Raw Block Driver (function layer)
-+ *
-+ * Copyright 2001-2002 MontaVista Software Inc.
-+ * Author: MontaVista Software, Inc.
-+ *		stevel@mvista.com or source@mvista.com
-+ *
-+ *  This program is free software; you can redistribute	 it and/or modify it
-+ *  under  the terms of	 the GNU General  Public License as published by the
-+ *  Free Software Foundation;  either version 2 of the	License, or (at your
-+ *  option) any later version.
-+ *
-+ *  THIS  SOFTWARE  IS PROVIDED	  ``AS	IS'' AND   ANY	EXPRESS OR IMPLIED
-+ *  WARRANTIES,	  INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
-+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
-+ *  NO	EVENT  SHALL   THE AUTHOR  BE	 LIABLE FOR ANY	  DIRECT, INDIRECT,
-+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ *  NOT LIMITED	  TO, PROCUREMENT OF  SUBSTITUTE GOODS	OR SERVICES; LOSS OF
-+ *  USE, DATA,	OR PROFITS; OR	BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ *  ANY THEORY OF LIABILITY, WHETHER IN	 CONTRACT, STRICT LIABILITY, OR TORT
-+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ *  You should have received a copy of the  GNU General Public License along
-+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
-+ *  675 Mass Ave, Cambridge, MA 02139, USA.
-+ */
-+
-+#include <linux/config.h>
-+#include <linux/kernel.h>
-+#include <linux/ioport.h>
-+#include <linux/sched.h>
-+#include <linux/signal.h>
-+#include <linux/errno.h>
-+#include <linux/poll.h>
-+#include <linux/init.h>
-+#include <linux/slab.h>
-+#include <linux/fcntl.h>
-+#include <linux/module.h>
-+#include <linux/spinlock.h>
-+#include <linux/list.h>
-+#include <linux/smp_lock.h>
-+#undef DEBUG
-+#include <linux/usb.h>
-+
-+#include <asm/io.h>
-+#include <asm/uaccess.h>
-+#include <asm/irq.h>
-+#include <asm/au1000.h>
-+#include <asm/au1000_usbdev.h>
-+
-+#define USBRAW_MAJOR 190 // FIXME: need a legal major
-+#define USBRAW_NAME "usbraw"
-+
-+#define MAX_NUM_PORTS 2
-+
-+#define IN_MAX_PACKET_SIZE  64
-+#define OUT_MAX_PACKET_SIZE 64
-+
-+// FIXME: when Au1x00 endpoints 3 and 5 are fixed, make NUM_PORTS=2
-+#define NUM_PORTS 1
-+#define NUM_EP 2*NUM_PORTS
-+
-+#define CONFIG_DESC_LEN \
-+ USB_DT_CONFIG_SIZE + USB_DT_INTERFACE_SIZE + NUM_EP*USB_DT_ENDPOINT_SIZE
-+
-+/* must be power of two */
-+#define READ_BUF_SIZE (1<<12)
-+
-+struct usb_raw_port {
-+	unsigned char number;
-+	spinlock_t port_lock;
-+
-+	struct usb_endpoint_descriptor* out_desc;
-+	struct usb_endpoint_descriptor* in_desc;
-+
-+	int out_ep_addr; /* endpoint address of OUT endpoint */
-+	int in_ep_addr;  /* endpoint address of IN endpoint */
-+	
-+	__u8 read_buf[READ_BUF_SIZE]; // FIXME: allocate with get_free_pages
-+	int read_nextin, read_nextout;
-+	int read_count;
-+
-+	wait_queue_head_t wait;
-+	struct fasync_struct *fasync;     // asynch notification
-+
-+	int active;	/* someone has this device open */
-+	int open_count;	/* number of times this port has been opened */
-+};
-+
-+static struct usb_serial {
-+	struct usb_device_descriptor* dev_desc;
-+	struct usb_config_descriptor* config_desc;
-+	struct usb_interface_descriptor* if_desc;
-+	struct usb_string_descriptor * str_desc[6];
-+	void* str_desc_buf;
-+
-+	usbdev_state_t dev_state;
-+
-+	struct usb_raw_port port[NUM_PORTS];
-+} usbraw;
-+
-+static struct usb_device_descriptor dev_desc = {
-+	bLength:USB_DT_DEVICE_SIZE,
-+	bDescriptorType:USB_DT_DEVICE,
-+	bcdUSB:USBDEV_REV,		//usb rev
-+	bDeviceClass:USB_CLASS_PER_INTERFACE,	//class    (none)
-+	bDeviceSubClass:0x00,	//subclass (none)
-+	bDeviceProtocol:0x00,	//protocol (none)
-+	bMaxPacketSize0:USBDEV_EP0_MAX_PACKET_SIZE, //max packet size for ep0
-+	idVendor:0x6d04,	//vendor  id
-+	idProduct:0x0bc0,	//product id
-+	bcdDevice:0x0001,	//BCD rev 0.1
-+	iManufacturer:0x01,	//manufactuer string index
-+	iProduct:0x02,		//product string index
-+	iSerialNumber:0x03,	//serial# string index
-+	bNumConfigurations:0x01	//num configurations
-+};
-+
-+static struct usb_endpoint_descriptor ep_desc[] = {
-+	{
-+		// Bulk IN for Port 0
-+		bLength:USB_DT_ENDPOINT_SIZE,
-+		bDescriptorType:USB_DT_ENDPOINT,
-+		bEndpointAddress:USB_DIR_IN,
-+		bmAttributes:USB_ENDPOINT_XFER_BULK,
-+		wMaxPacketSize:IN_MAX_PACKET_SIZE,
-+		bInterval:0x00	// ignored for bulk
-+	},
-+	{
-+		// Bulk OUT for Port 0
-+		bLength:USB_DT_ENDPOINT_SIZE,
-+		bDescriptorType:USB_DT_ENDPOINT,
-+		bEndpointAddress:USB_DIR_OUT,
-+		bmAttributes:USB_ENDPOINT_XFER_BULK,
-+		wMaxPacketSize:OUT_MAX_PACKET_SIZE,
-+		bInterval:0x00	// ignored for bulk
-+	},
-+	{
-+		// Bulk IN for Port 1
-+		bLength:USB_DT_ENDPOINT_SIZE,
-+		bDescriptorType:USB_DT_ENDPOINT,
-+		bEndpointAddress:USB_DIR_IN,
-+		bmAttributes:USB_ENDPOINT_XFER_BULK,
-+		wMaxPacketSize:IN_MAX_PACKET_SIZE,
-+		bInterval:0x00	// ignored for bulk
-+	},
-+	{
-+		// Bulk OUT for Port 1
-+		bLength:USB_DT_ENDPOINT_SIZE,
-+		bDescriptorType:USB_DT_ENDPOINT,
-+		bEndpointAddress:USB_DIR_OUT,
-+		bmAttributes:USB_ENDPOINT_XFER_BULK,
-+		wMaxPacketSize:OUT_MAX_PACKET_SIZE,
-+		bInterval:0x00	// ignored for bulk
-+	}
-+};
-+
-+static struct usb_interface_descriptor if_desc = {
-+	bLength:USB_DT_INTERFACE_SIZE,
-+	bDescriptorType:USB_DT_INTERFACE,
-+	bInterfaceNumber:0x00,
-+	bAlternateSetting:0x00,
-+	bNumEndpoints:NUM_EP,
-+	bInterfaceClass:0xff,
-+	bInterfaceSubClass:0xab,
-+	bInterfaceProtocol:0x00,
-+	iInterface:0x05
-+};
-+
-+static struct usb_config_descriptor config_desc = {
-+	bLength:USB_DT_CONFIG_SIZE,
-+	bDescriptorType:USB_DT_CONFIG,
-+	wTotalLength:CONFIG_DESC_LEN,
-+	bNumInterfaces:0x01,
-+	bConfigurationValue:0x01,
-+	iConfiguration:0x04,	// configuration string
-+	bmAttributes:0xc0,	// self-powered
-+	MaxPower:20		// 40 mA
-+};
-+
-+// String[0] is a list of Language IDs supported by this device
-+static struct usb_string_descriptor string_desc0 = {
-+	bLength:4,
-+	bDescriptorType:USB_DT_STRING,
-+	wData:{0x0409} // English, US
-+};
-+
-+// These strings will be converted to Unicode in string_desc[]
-+static char *strings[5] = {
-+	"Alchemy Semiconductor",  // iManufacturer
-+	"USB Raw Block Device",   // iProduct
-+	"0.1",                    // iSerialNumber
-+	"USB Raw Config",         // iConfiguration
-+	"USB Raw Interface"       // iInterface
-+};
-+
-+
-+static void
-+receive_callback(struct usb_raw_port *port)
-+{
-+	int i, pkt_size;
-+	usbdev_pkt_t* pkt;
-+	
-+	if ((pkt_size = usbdev_receive_packet(port->out_ep_addr,
-+					      &pkt)) <= 0) {
-+		dbg(__FUNCTION__ ": usbdev_receive_packet returns %d",
-+		    pkt_size);
-+		return;
-+	}
-+
-+	dbg(__FUNCTION__ ": ep%d, size=%d", port->out_ep_addr, pkt_size);
-+
-+	spin_lock(&port->port_lock);
-+	for (i=0; i < pkt_size; i++) {
-+		port->read_buf[port->read_nextin++] = pkt->payload[i];
-+		port->read_nextin &= (READ_BUF_SIZE - 1);
-+		if (++port->read_count == READ_BUF_SIZE)
-+			break;
-+	}
-+	spin_unlock(&port->port_lock);
-+
-+	/* free the packet */
-+	kfree(pkt);
-+	
-+	// async notify
-+	if (port->fasync)
-+		kill_fasync(&port->fasync, SIGIO, POLL_IN);
-+	// wake up any read call
-+	if (waitqueue_active(&port->wait))
-+		wake_up_interruptible(&port->wait);
-+}
-+
-+static void
-+transmit_callback(struct usb_raw_port *port, usbdev_pkt_t* pkt)
-+{
-+	dbg(__FUNCTION__ ": ep%d", port->in_ep_addr);
-+	/* just free the returned packet */
-+	kfree(pkt);
-+}
-+
-+
-+static void
-+usbraw_callback(usbdev_cb_type_t cb_type, unsigned long arg, void* data)
-+{
-+	usbdev_pkt_t* pkt;
-+	int i;
-+	
-+	switch (cb_type) {
-+	case CB_NEW_STATE:
-+		usbraw.dev_state = (usbdev_state_t)arg;
-+		break;
-+	case CB_PKT_COMPLETE:
-+		pkt = (usbdev_pkt_t*)arg;
-+		for (i=0; i<NUM_PORTS; i++) {
-+			struct usb_raw_port *port = &usbraw.port[i];
-+			if (pkt->ep_addr == port->in_ep_addr) {
-+				transmit_callback(port, pkt);
-+				break;
-+			} else if (pkt->ep_addr == port->out_ep_addr) {
-+				receive_callback(port);
-+				break;
-+			}
-+		}
-+		break;
-+	}
-+}
-+
-+/*****************************************************************************
-+ * Here begins the driver interface functions
-+ *****************************************************************************/
-+
-+static unsigned int usbraw_poll(struct file * filp, poll_table * wait)
-+{
-+	struct usb_raw_port *port = (struct usb_raw_port *)filp->private_data;
-+	unsigned long flags;
-+	int count;
-+	
-+	poll_wait(filp, &port->wait, wait);
-+
-+	spin_lock_irqsave(&port->port_lock, flags);
-+	count = port->read_count;
-+	spin_unlock_irqrestore(&port->port_lock, flags);
-+
-+	if (count > 0) {
-+		dbg(__FUNCTION__ ": count=%d", count);
-+		return POLLIN | POLLRDNORM;
-+	}
-+	
-+	return 0;
-+}
-+
-+static int usbraw_fasync(int fd, struct file *filp, int mode)
-+{
-+	struct usb_raw_port *port = (struct usb_raw_port *)filp->private_data;
-+	return fasync_helper(fd, filp, mode, &port->fasync);
-+}
-+
-+static int usbraw_open(struct inode * inode, struct file *filp)
-+{
-+	int portNumber;
-+	struct usb_raw_port *port;
-+	unsigned long flags;
-+
-+	/*
-+	 * the device-layer must be in the configured state before the
-+	 * function layer can operate.
-+	 */
-+	if (usbraw.dev_state != CONFIGURED)
-+		return -ENODEV;
-+	
-+	/* set up our port structure making the tty driver remember
-+	   our port object, and us it */
-+	portNumber = MINOR(inode->i_rdev);
-+	port = &usbraw.port[portNumber];
-+	filp->private_data = port;
-+
-+	dbg(__FUNCTION__ ": port %d", port->number);
-+
-+	spin_lock_irqsave(&port->port_lock, flags);
-+
-+	++port->open_count;
-+
-+	if (!port->active) {
-+		port->active = 1;
-+	}
-+
-+	/* flush read buffer */
-+	port->read_nextin = port->read_nextout = port->read_count = 0;
-+
-+	spin_unlock_irqrestore(&port->port_lock, flags);
-+
-+	return 0;
-+}
-+
-+static int usbraw_release(struct inode * inode, struct file * filp)
-+{
-+	struct usb_raw_port *port = (struct usb_raw_port *)filp->private_data;
-+	unsigned long flags;
-+
-+	dbg(__FUNCTION__ ": port %d", port->number);
-+
-+	if (!port->active) {
-+		err(__FUNCTION__ ": port not opened");
-+		return -ENODEV;
-+	}
-+
-+	usbraw_fasync(-1, filp, 0);
-+
-+	spin_lock_irqsave(&port->port_lock, flags);
-+
-+	--port->open_count;
-+
-+	if (port->open_count <= 0) {
-+		port->active = 0;
-+		port->open_count = 0;
-+	}
-+
-+	spin_unlock_irqrestore(&port->port_lock, flags);
-+
-+	return 0;
-+}
-+
-+
-+static ssize_t usbraw_read(struct file * filp, char * buf,
-+			   size_t count, loff_t * l)
-+{
-+	struct usb_raw_port *port = (struct usb_raw_port *)filp->private_data;
-+	unsigned long flags;
-+	int i, cnt;
-+
-+	/*
-+	 * the device-layer must be in the configured state before the
-+	 * function layer can operate.
-+	 */
-+	if (usbraw.dev_state != CONFIGURED)
-+		return -ENODEV;
-+
-+	do { 
-+		spin_lock_irqsave(&port->port_lock, flags);
-+		cnt = port->read_count;
-+		spin_unlock_irqrestore(&port->port_lock, flags);
-+		if (cnt == 0) {
-+			if (filp->f_flags & O_NONBLOCK)
-+				return -EAGAIN;
-+			interruptible_sleep_on(&port->wait);
-+			if (signal_pending(current))
-+				return -ERESTARTSYS;
-+		}
-+	} while (cnt == 0);
-+
-+	count = (count > cnt) ? cnt : count;
-+
-+	for (i=0; i<count; i++) {
-+		put_user(port->read_buf[port->read_nextout++], &buf[i]);
-+		port->read_nextout &= (READ_BUF_SIZE - 1);
-+		spin_lock_irqsave(&port->port_lock, flags);
-+		port->read_count--;
-+		spin_unlock_irqrestore(&port->port_lock, flags);
-+		if (port->read_count == 0)
-+			break;
-+	}
-+
-+	return i+1;
-+}
-+
-+static ssize_t usbraw_write(struct file * filp, const char * buf,
-+			    size_t count, loff_t *ppos)
-+{
-+	struct usb_raw_port *port = (struct usb_raw_port *)filp->private_data;
-+	usbdev_pkt_t* pkt;
-+	int ret, max_pkt_sz;
-+	
-+	/*
-+	 * the device-layer must be in the configured state before the
-+	 * function layer can operate.
-+	 */
-+	if (usbraw.dev_state != CONFIGURED)
-+		return -ENODEV;
-+
-+	if (!port->active) {
-+		err(__FUNCTION__ ": port not opened");
-+		return -EINVAL;
-+	}
-+
-+	if (count == 0) {
-+		dbg(__FUNCTION__ ": write request of 0 bytes");
-+		return (0);
-+	}
-+
-+	max_pkt_sz = port->in_desc->wMaxPacketSize;
-+	count = (count > max_pkt_sz) ? max_pkt_sz : count;
-+
-+	if ((ret = usbdev_alloc_packet(port->in_ep_addr, count, &pkt)) < 0)
-+		return ret;
-+
-+	copy_from_user(pkt->payload, buf, count);
-+	
-+	return usbdev_send_packet(port->in_ep_addr, pkt);
-+}
-+
-+static int usbraw_ioctl(struct inode *inode, struct file *filp,
-+			unsigned int cmd, unsigned long arg)
-+{
-+	struct usb_raw_port *port = (struct usb_raw_port *)filp->private_data;
-+
-+	if (!port->active) {
-+		err(__FUNCTION__ ": port not open");
-+		return -ENODEV;
-+	}
-+	// FIXME: need any IOCTLs?
-+
-+	return -ENOIOCTLCMD;
-+}
-+
-+
-+static struct file_operations usbraw_fops = {
-+        .owner          = THIS_MODULE,
-+        .write          = usbraw_write,
-+	.read           = usbraw_read,
-+	.poll           = usbraw_poll,
-+	.ioctl		= usbraw_ioctl,
-+	.fasync         = usbraw_fasync,
-+	.open		= usbraw_open,
-+	.release	= usbraw_release,
-+};
-+
-+void usbfn_raw_exit(void)
-+{
-+	/* kill the device layer */
-+	usbdev_exit();
-+
-+	unregister_chrdev(USBRAW_MAJOR, USBRAW_NAME);
-+
-+	if (usbraw.str_desc_buf)
-+		kfree(usbraw.str_desc_buf);
-+}
-+
-+
-+int usbfn_raw_init(void)
-+{
-+	int ret = 0, i, str_desc_len;
-+
-+	/* register our character device */
-+	if ((ret = register_chrdev(USBRAW_MAJOR, USBRAW_NAME,
-+				   &usbraw_fops)) < 0) {
-+		err("can't get major number");
-+		return ret;
-+	}
-+	info("registered");
-+
-+	/*
-+	 * initialize pointers to descriptors
-+	 */
-+	usbraw.dev_desc = &dev_desc;
-+	usbraw.config_desc = &config_desc;
-+	usbraw.if_desc = &if_desc;
-+
-+	/*
-+	 * initialize the string descriptors
-+	 */
-+
-+	/* alloc buffer big enough for all string descriptors */
-+	str_desc_len = string_desc0.bLength;
-+	for (i = 0; i < 5; i++)
-+		str_desc_len += 2 + 2 * strlen(strings[i]);
-+	usbraw.str_desc_buf = (void *) kmalloc(str_desc_len, GFP_KERNEL);
-+	if (!usbraw.str_desc_buf) {
-+		err(__FUNCTION__ ": failed to alloc string descriptors");
-+		ret = -ENOMEM;
-+		goto out;
-+	}
-+
-+	usbraw.str_desc[0] =
-+		(struct usb_string_descriptor *)usbraw.str_desc_buf;
-+	memcpy(usbraw.str_desc[0], &string_desc0, string_desc0.bLength);
-+	usbraw.str_desc[1] = (struct usb_string_descriptor *)
-+		(usbraw.str_desc_buf + string_desc0.bLength);
-+	for (i = 1; i < 6; i++) {
-+		struct usb_string_descriptor *desc = usbraw.str_desc[i];
-+		char *str = strings[i - 1];
-+		int j, str_len = strlen(str);
-+
-+		desc->bLength = 2 + 2 * str_len;
-+		desc->bDescriptorType = USB_DT_STRING;
-+		for (j = 0; j < str_len; j++) {
-+			desc->wData[j] = (u16) str[j];
-+		}
-+		if (i < 5)
-+			usbraw.str_desc[i + 1] =
-+				(struct usb_string_descriptor *)
-+				((u8 *) desc + desc->bLength);
-+	}
-+
-+	/*
-+	 * start the device layer. The device layer assigns us
-+	 * our endpoint addresses
-+	 */
-+	if ((ret = usbdev_init(&dev_desc, &config_desc, &if_desc, ep_desc,
-+			       usbraw.str_desc, usbraw_callback, NULL))) {
-+		err(__FUNCTION__ ": device-layer init failed");
-+		goto out;
-+	}
-+	
-+	/* initialize the devfs nodes for this device and let the user
-+	   know what ports we are bound to */
-+	for (i = 0; i < NUM_PORTS; ++i) {
-+		struct usb_raw_port *port = &usbraw.port[i];
-+
-+		port->number = i;
-+		port->in_desc = &ep_desc[NUM_PORTS*i];
-+		port->out_desc = &ep_desc[NUM_PORTS*i + 1];
-+		port->in_ep_addr = port->in_desc->bEndpointAddress & 0x0f;
-+		port->out_ep_addr = port->out_desc->bEndpointAddress & 0x0f;
-+		init_waitqueue_head(&port->wait);
-+		spin_lock_init(&port->port_lock);
-+	}
-+
-+ out:
-+	if (ret)
-+		usbfn_raw_exit();
-+	return ret;
-+}
-+
-+
-+/* Module information */
-+MODULE_AUTHOR("Steve Longerbeam, stevel@mvista.com, www.mvista.com");
-+MODULE_DESCRIPTION("Au1x00 USB Device-Side Raw Block Driver");
-+MODULE_LICENSE("GPL");
-+
-+module_init(usbfn_raw_init);
-+module_exit(usbfn_raw_exit);
-diff -Naur linux-2.6.17.orig/drivers/char/au1000_usbtty.c linux-2.6.17/drivers/char/au1000_usbtty.c
---- linux-2.6.17.orig/drivers/char/au1000_usbtty.c	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/drivers/char/au1000_usbtty.c	2006-06-19 18:16:13.000000000 -0700
-@@ -0,0 +1,761 @@
-+/*
-+ * BRIEF MODULE DESCRIPTION
-+ *	Au1x00 USB Device-Side Serial TTY Driver (function layer)
-+ *
-+ * Copyright 2001-2002 MontaVista Software Inc.
-+ * Author: MontaVista Software, Inc.
-+ *		stevel@mvista.com or source@mvista.com
-+ *
-+ *  Derived from drivers/usb/serial/usbserial.c:
-+ *
-+ *  Copyright (C) 1999 - 2001 Greg Kroah-Hartman (greg@kroah.com)
-+ *  Copyright (c) 2000 Peter Berger (pberger@brimson.com)
-+ *  Copyright (c) 2000 Al Borchers (borchers@steinerpoint.com)
-+ *
-+ *  This program is free software; you can redistribute	 it and/or modify it
-+ *  under  the terms of	 the GNU General  Public License as published by the
-+ *  Free Software Foundation;  either version 2 of the	License, or (at your
-+ *  option) any later version.
-+ *
-+ *  THIS  SOFTWARE  IS PROVIDED	  ``AS	IS'' AND   ANY	EXPRESS OR IMPLIED
-+ *  WARRANTIES,	  INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
-+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
-+ *  NO	EVENT  SHALL   THE AUTHOR  BE	 LIABLE FOR ANY	  DIRECT, INDIRECT,
-+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ *  NOT LIMITED	  TO, PROCUREMENT OF  SUBSTITUTE GOODS	OR SERVICES; LOSS OF
-+ *  USE, DATA,	OR PROFITS; OR	BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ *  ANY THEORY OF LIABILITY, WHETHER IN	 CONTRACT, STRICT LIABILITY, OR TORT
-+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ *  You should have received a copy of the  GNU General Public License along
-+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
-+ *  675 Mass Ave, Cambridge, MA 02139, USA.
-+ */
-+
-+#include <linux/config.h>
-+#include <linux/kernel.h>
-+#include <linux/ioport.h>
-+#include <linux/sched.h>
-+#include <linux/signal.h>
-+#include <linux/errno.h>
-+#include <linux/poll.h>
-+#include <linux/init.h>
-+#include <linux/slab.h>
-+#include <linux/fcntl.h>
-+#include <linux/tty.h>
-+#include <linux/tty_driver.h>
-+#include <linux/tty_flip.h>
-+#include <linux/module.h>
-+#include <linux/spinlock.h>
-+#include <linux/list.h>
-+#include <linux/smp_lock.h>
-+#undef DEBUG
-+#include <linux/usb.h>
-+
-+#include <asm/io.h>
-+#include <asm/uaccess.h>
-+#include <asm/irq.h>
-+#include <asm/au1000.h>
-+#include <asm/au1000_usbdev.h>
-+
-+
-+/* local function prototypes */
-+static int serial_open(struct tty_struct *tty, struct file *filp);
-+static void serial_close(struct tty_struct *tty, struct file *filp);
-+static int serial_write(struct tty_struct *tty, int from_user,
-+			const unsigned char *buf, int count);
-+static int serial_write_room(struct tty_struct *tty);
-+static int serial_chars_in_buffer(struct tty_struct *tty);
-+static void serial_throttle(struct tty_struct *tty);
-+static void serial_unthrottle(struct tty_struct *tty);
-+static int serial_ioctl(struct tty_struct *tty, struct file *file,
-+			unsigned int cmd, unsigned long arg);
-+static void serial_set_termios (struct tty_struct *tty, struct termios * old);
-+
-+#define SERIAL_TTY_MAJOR 189 // FIXME: need a legal major
-+
-+#define MAX_NUM_PORTS 2
-+
-+#define IN_MAX_PACKET_SIZE  32
-+#define OUT_MAX_PACKET_SIZE 32
-+
-+// FIXME: when Au1x00 endpoints 3 and 5 are fixed, make NUM_PORTS=2
-+#define NUM_PORTS 2
-+#define NUM_EP 2*NUM_PORTS
-+
-+#define CONFIG_DESC_LEN \
-+ USB_DT_CONFIG_SIZE + USB_DT_INTERFACE_SIZE + NUM_EP*USB_DT_ENDPOINT_SIZE
-+
-+struct usb_serial_port {
-+	struct tty_struct *tty;	   /* the coresponding tty for this port */
-+	unsigned char number;
-+	spinlock_t port_lock;
-+
-+	struct usb_endpoint_descriptor* out_desc;
-+	struct usb_endpoint_descriptor* in_desc;
-+
-+	int out_ep_addr; /* endpoint address of OUT endpoint */
-+	int in_ep_addr;  /* endpoint address of IN endpoint */
-+	
-+	/* task queue for line discipline waking up on send packet complete */
-+	struct tq_struct send_complete_tq;
-+	/* task queue for line discipline wakeup on receive packet complete */
-+	struct tq_struct receive_complete_tq;
-+
-+	int active;	/* someone has this device open */
-+	int writing;    /* a packet write is in progress */
-+	int open_count;	/* number of times this port has been opened */
-+
-+};
-+
-+static struct usb_serial {
-+	usbdev_state_t dev_state; // current state of device layer
-+	struct usb_device_descriptor* dev_desc;
-+	struct usb_config_descriptor* config_desc;
-+	struct usb_interface_descriptor* if_desc;
-+	struct usb_string_descriptor * str_desc[6];
-+	void* str_desc_buf;
-+
-+	struct usb_serial_port port[NUM_PORTS];
-+} usbtty;
-+
-+static int                 serial_refcount;
-+static struct tty_driver   serial_tty_driver;
-+static struct tty_struct * serial_tty[NUM_PORTS];
-+static struct termios *    serial_termios[NUM_PORTS];
-+static struct termios *    serial_termios_locked[NUM_PORTS];
-+
-+static struct usb_device_descriptor dev_desc = {
-+	bLength:USB_DT_DEVICE_SIZE,
-+	bDescriptorType:USB_DT_DEVICE,
-+	bcdUSB:USBDEV_REV,		//usb rev
-+	bDeviceClass:USB_CLASS_PER_INTERFACE,	//class    (none)
-+	bDeviceSubClass:0x00,	//subclass (none)
-+	bDeviceProtocol:0x00,	//protocol (none)
-+	bMaxPacketSize0:USBDEV_EP0_MAX_PACKET_SIZE, //max packet size for ep0
-+	idVendor:0x6d04,	//vendor  id
-+	idProduct:0x0bc0,	//product id
-+	bcdDevice:0x0001,	//BCD rev 0.1
-+	iManufacturer:0x01,	//manufactuer string index
-+	iProduct:0x02,		//product string index
-+	iSerialNumber:0x03,	//serial# string index
-+	bNumConfigurations:0x01	//num configurations
-+};
-+
-+static struct usb_endpoint_descriptor ep_desc[] = {
-+	{
-+		// Bulk IN for Port 0
-+		bLength:USB_DT_ENDPOINT_SIZE,
-+		bDescriptorType:USB_DT_ENDPOINT,
-+		bEndpointAddress:USB_DIR_IN,
-+		bmAttributes:USB_ENDPOINT_XFER_BULK,
-+		wMaxPacketSize:IN_MAX_PACKET_SIZE,
-+		bInterval:0x00	// ignored for bulk
-+	},
-+	{
-+		// Bulk OUT for Port 0
-+		bLength:USB_DT_ENDPOINT_SIZE,
-+		bDescriptorType:USB_DT_ENDPOINT,
-+		bEndpointAddress:USB_DIR_OUT,
-+		bmAttributes:USB_ENDPOINT_XFER_BULK,
-+		wMaxPacketSize:OUT_MAX_PACKET_SIZE,
-+		bInterval:0x00	// ignored for bulk
-+	},
-+	{
-+		// Bulk IN for Port 1
-+		bLength:USB_DT_ENDPOINT_SIZE,
-+		bDescriptorType:USB_DT_ENDPOINT,
-+		bEndpointAddress:USB_DIR_IN,
-+		bmAttributes:USB_ENDPOINT_XFER_BULK,
-+		wMaxPacketSize:IN_MAX_PACKET_SIZE,
-+		bInterval:0x00	// ignored for bulk
-+	},
-+	{
-+		// Bulk OUT for Port 1
-+		bLength:USB_DT_ENDPOINT_SIZE,
-+		bDescriptorType:USB_DT_ENDPOINT,
-+		bEndpointAddress:USB_DIR_OUT,
-+		bmAttributes:USB_ENDPOINT_XFER_BULK,
-+		wMaxPacketSize:OUT_MAX_PACKET_SIZE,
-+		bInterval:0x00	// ignored for bulk
-+	}
-+};
-+
-+static struct usb_interface_descriptor if_desc = {
-+	bLength:USB_DT_INTERFACE_SIZE,
-+	bDescriptorType:USB_DT_INTERFACE,
-+	bInterfaceNumber:0x00,
-+	bAlternateSetting:0x00,
-+	bNumEndpoints:NUM_EP,
-+	bInterfaceClass:0xff,
-+	bInterfaceSubClass:0xab,
-+	bInterfaceProtocol:0x00,
-+	iInterface:0x05
-+};
-+
-+static struct usb_config_descriptor config_desc = {
-+	bLength:USB_DT_CONFIG_SIZE,
-+	bDescriptorType:USB_DT_CONFIG,
-+	wTotalLength:CONFIG_DESC_LEN,
-+	bNumInterfaces:0x01,
-+	bConfigurationValue:0x01,
-+	iConfiguration:0x04,	// configuration string
-+	bmAttributes:0xc0,	// self-powered
-+	MaxPower:20		// 40 mA
-+};
-+
-+// String[0] is a list of Language IDs supported by this device
-+static struct usb_string_descriptor string_desc0 = {
-+	bLength:4,
-+	bDescriptorType:USB_DT_STRING,
-+	wData:{0x0409} // English, US
-+};
-+
-+// These strings will be converted to Unicode in string_desc[]
-+static char *strings[5] = {
-+	"Alchemy Semiconductor",  // iManufacturer
-+	"WutzAMattaU",            // iProduct
-+	"1.0.doh!",               // iSerialNumber
-+	"Au1000 TTY Config",      // iConfiguration
-+	"Au1000 TTY Interface"    // iInterface
-+};
-+
-+static inline int
-+port_paranoia_check(struct usb_serial_port *port, const char *function)
-+{
-+	if (!port) {
-+		err("%s: port is NULL", function);
-+		return -1;
-+	}
-+	if (!port->tty) {
-+		err("%s: port->tty is NULL", function);
-+		return -1;
-+	}
-+
-+	return 0;
-+}
-+
-+
-+static void
-+port_rx_callback(struct usb_serial_port *port)
-+{
-+	dbg(__FUNCTION__ ": ep%d", port->out_ep_addr);
-+	// mark a bh to push this data up to the tty
-+	queue_task(&port->receive_complete_tq, &tq_immediate);
-+	mark_bh(IMMEDIATE_BH);
-+}
-+
-+static void
-+port_tx_callback(struct usb_serial_port *port, usbdev_pkt_t* pkt)
-+{
-+	dbg(__FUNCTION__ ": ep%d", port->in_ep_addr);
-+	// mark a bh to wakeup any tty write system call on the port.
-+	queue_task(&port->send_complete_tq, &tq_immediate);
-+	mark_bh(IMMEDIATE_BH);
-+
-+	/* free the returned packet */
-+	kfree(pkt);
-+}
-+
-+static void
-+usbtty_callback(usbdev_cb_type_t cb_type, unsigned long arg, void* data)
-+{
-+	usbdev_pkt_t* pkt;
-+	int i;
-+	
-+	switch (cb_type) {
-+	case CB_NEW_STATE:
-+		dbg(__FUNCTION__ ": new dev_state=%d", (int)arg);
-+		usbtty.dev_state = (usbdev_state_t)arg;
-+		break;
-+	case CB_PKT_COMPLETE:
-+		pkt = (usbdev_pkt_t*)arg;
-+		for (i=0; i<NUM_PORTS; i++) {
-+			struct usb_serial_port *port = &usbtty.port[i];
-+			if (pkt->ep_addr == port->in_ep_addr) {
-+				port_tx_callback(port, pkt);
-+				break;
-+			} else if (pkt->ep_addr == port->out_ep_addr) {
-+				port_rx_callback(port);
-+				break;
-+			}
-+		}
-+		break;
-+	}
-+}
-+
-+
-+/*****************************************************************************
-+ * Here begins the tty driver interface functions
-+ *****************************************************************************/
-+
-+static int serial_open(struct tty_struct *tty, struct file *filp)
-+{
-+	int portNumber;
-+	struct usb_serial_port *port;
-+	unsigned long flags;
-+
-+	/* initialize the pointer incase something fails */
-+	tty->driver_data = NULL;
-+
-+	/* set up our port structure making the tty driver remember
-+	   our port object, and us it */
-+	portNumber = MINOR(tty->device);
-+	port = &usbtty.port[portNumber];
-+	tty->driver_data = port;
-+	port->tty = tty;
-+
-+	if (usbtty.dev_state != CONFIGURED ||
-+	    port_paranoia_check(port, __FUNCTION__)) {
-+		/*
-+		 * the device-layer must be in the configured state before
-+		 * the function layer can operate.
-+		 */
-+		return -ENODEV;
-+	}
-+	
-+	dbg(__FUNCTION__ ": port %d", port->number);
-+
-+	spin_lock_irqsave(&port->port_lock, flags);
-+
-+	++port->open_count;
-+
-+	if (!port->active) {
-+		port->active = 1;
-+
-+		/*
-+		 * force low_latency on so that our tty_push actually forces
-+		 * the data through, otherwise it is scheduled, and with high
-+		 * data rates (like with OHCI) data can get lost.
-+		 */
-+		port->tty->low_latency = 1;
-+
-+	}
-+
-+	spin_unlock_irqrestore(&port->port_lock, flags);
-+
-+	return 0;
-+}
-+
-+
-+static void serial_close(struct tty_struct *tty, struct file *filp)
-+{
-+	struct usb_serial_port *port =
-+		(struct usb_serial_port *) tty->driver_data;
-+	unsigned long flags;
-+
-+	dbg(__FUNCTION__ ": port %d", port->number);
-+
-+	if (!port->active) {
-+		err(__FUNCTION__ ": port not opened");
-+		return;
-+	}
-+
-+	spin_lock_irqsave(&port->port_lock, flags);
-+
-+	--port->open_count;
-+
-+	if (port->open_count <= 0) {
-+		port->active = 0;
-+		port->open_count = 0;
-+	}
-+
-+	spin_unlock_irqrestore(&port->port_lock, flags);
-+	MOD_DEC_USE_COUNT;
-+}
-+
-+
-+static int serial_write(struct tty_struct *tty, int from_user,
-+			const unsigned char *buf, int count)
-+{
-+	struct usb_serial_port *port =
-+		(struct usb_serial_port *) tty->driver_data;
-+	usbdev_pkt_t* pkt;
-+	int max_pkt_sz, ret;
-+	unsigned long flags;
-+	
-+	/*
-+	 * the device-layer must be in the configured state before the
-+	 * function layer can operate.
-+	 */
-+	if (usbtty.dev_state != CONFIGURED)
-+		return -ENODEV;
-+
-+	if (!port->active) {
-+		err(__FUNCTION__ ": port not open");
-+		return -EINVAL;
-+	}
-+
-+	if (count == 0) {
-+		dbg(__FUNCTION__ ": request of 0 bytes");
-+		return (0);
-+	}
-+
-+#if 0
-+	if (port->writing) {
-+		dbg(__FUNCTION__ ": already writing");
-+		return 0;
-+	}
-+#endif
-+	
-+	max_pkt_sz = port->in_desc->wMaxPacketSize;
-+	count = (count > max_pkt_sz) ? max_pkt_sz : count;
-+
-+	if ((ret = usbdev_alloc_packet(port->in_ep_addr, count, &pkt)))
-+		return ret;
-+
-+	if (from_user)
-+		copy_from_user(pkt->payload, buf, count);
-+	else
-+		memcpy(pkt->payload, buf, count);
-+	
-+	ret = usbdev_send_packet(port->in_ep_addr, pkt);
-+
-+	spin_lock_irqsave(&port->port_lock, flags);
-+	port->writing = 1;
-+	spin_unlock_irqrestore(&port->port_lock, flags);
-+
-+	return ret;
-+}
-+
-+
-+static int serial_write_room(struct tty_struct *tty)
-+{
-+	struct usb_serial_port *port =
-+		(struct usb_serial_port *) tty->driver_data;
-+	int room = 0;
-+	
-+	/*
-+	 * the device-layer must be in the configured state before the
-+	 * function layer can operate.
-+	 */
-+	if (usbtty.dev_state != CONFIGURED)
-+		return -ENODEV;
-+
-+	if (!port->active) {
-+		err(__FUNCTION__ ": port not open");
-+		return -EINVAL;
-+	}
-+
-+	//room = port->writing ? 0 : port->in_desc->wMaxPacketSize;
-+	room = port->in_desc->wMaxPacketSize;
-+	
-+	dbg(__FUNCTION__ ": %d", room);
-+	return room;
-+}
-+
-+
-+static int serial_chars_in_buffer(struct tty_struct *tty)
-+{
-+	struct usb_serial_port *port =
-+		(struct usb_serial_port *) tty->driver_data;
-+	int chars = 0;
-+	
-+	/*
-+	 * the device-layer must be in the configured state before the
-+	 * function layer can operate.
-+	 */
-+	if (usbtty.dev_state != CONFIGURED)
-+		return -ENODEV;
-+
-+	if (!port->active) {
-+		err(__FUNCTION__ ": port not open");
-+		return -EINVAL;
-+	}
-+
-+	//chars = port->writing ? usbdev_get_byte_count(port->in_ep_addr) : 0;
-+	chars = usbdev_get_byte_count(port->in_ep_addr);
-+
-+	dbg(__FUNCTION__ ": %d", chars);
-+	return chars;
-+}
-+
-+
-+static void serial_throttle(struct tty_struct *tty)
-+{
-+	struct usb_serial_port *port =
-+		(struct usb_serial_port *) tty->driver_data;
-+
-+	if (!port->active || usbtty.dev_state != CONFIGURED) {
-+		err(__FUNCTION__ ": port not open");
-+		return;
-+	}
-+
-+	// FIXME: anything to do?
-+	dbg(__FUNCTION__);
-+}
-+
-+
-+static void serial_unthrottle(struct tty_struct *tty)
-+{
-+	struct usb_serial_port *port =
-+		(struct usb_serial_port *) tty->driver_data;
-+
-+	if (!port->active || usbtty.dev_state != CONFIGURED) {
-+		err(__FUNCTION__ ": port not open");
-+		return;
-+	}
-+
-+	// FIXME: anything to do?
-+	dbg(__FUNCTION__);
-+}
-+
-+
-+static int serial_ioctl(struct tty_struct *tty, struct file *file,
-+			unsigned int cmd, unsigned long arg)
-+{
-+	struct usb_serial_port *port =
-+		(struct usb_serial_port *) tty->driver_data;
-+
-+	if (!port->active) {
-+		err(__FUNCTION__ ": port not open");
-+		return -ENODEV;
-+	}
-+	// FIXME: need any IOCTLs?
-+	dbg(__FUNCTION__);
-+
-+	return -ENOIOCTLCMD;
-+}
-+
-+
-+static void serial_set_termios(struct tty_struct *tty, struct termios *old)
-+{
-+	struct usb_serial_port *port =
-+		(struct usb_serial_port *) tty->driver_data;
-+
-+	if (!port->active || usbtty.dev_state != CONFIGURED)  {
-+		err(__FUNCTION__ ": port not open");
-+		return;
-+	}
-+
-+	dbg(__FUNCTION__);
-+	// FIXME: anything to do?
-+}
-+
-+
-+static void serial_break(struct tty_struct *tty, int break_state)
-+{
-+	struct usb_serial_port *port =
-+		(struct usb_serial_port *) tty->driver_data;
-+
-+	if (!port->active || usbtty.dev_state != CONFIGURED)  {
-+		err(__FUNCTION__ ": port not open");
-+		return;
-+	}
-+
-+	dbg(__FUNCTION__);
-+	// FIXME: anything to do?
-+}
-+
-+
-+static void port_send_complete(void *private)
-+{
-+	struct usb_serial_port *port = (struct usb_serial_port *) private;
-+	struct tty_struct *tty;
-+	unsigned long flags;
-+
-+	dbg(__FUNCTION__ ": port %d, ep%d", port->number, port->in_ep_addr);
-+
-+	tty = port->tty;
-+	if ((tty->flags & (1 << TTY_DO_WRITE_WAKEUP)) &&
-+	    tty->ldisc.write_wakeup) {
-+		dbg(__FUNCTION__ ": write wakeup call.");
-+		(tty->ldisc.write_wakeup) (tty);
-+	}
-+
-+	wake_up_interruptible(&tty->write_wait);
-+
-+	spin_lock_irqsave(&port->port_lock, flags);
-+	port->writing = usbdev_get_byte_count(port->in_ep_addr) <= 0 ? 0 : 1;
-+	spin_unlock_irqrestore(&port->port_lock, flags);
-+}
-+
-+
-+static void port_receive_complete(void *private)
-+{
-+	struct usb_serial_port *port = (struct usb_serial_port *) private;
-+	struct tty_struct *tty = port->tty;
-+	usbdev_pkt_t* pkt = NULL;
-+	int i, count;
-+
-+	/* while there is a packet available */
-+	while ((count = usbdev_receive_packet(port->out_ep_addr,
-+					      &pkt)) != -ENODATA) {
-+		if (count < 0) {
-+			if (pkt)
-+				kfree(pkt);
-+			break; /* exit if error other than ENODATA */
-+		}
-+		
-+		dbg(__FUNCTION__ ": port %d, ep%d, size=%d",
-+		    port->number, port->out_ep_addr, count);
-+
-+		for (i = 0; i < count; i++) {
-+			/* if we insert more than TTY_FLIPBUF_SIZE characters,
-+			   we drop them. */
-+			if (tty->flip.count >= TTY_FLIPBUF_SIZE) {
-+				tty_flip_buffer_push(tty);
-+			}
-+			/* this doesn't actually push the data through
-+			   unless tty->low_latency is set */
-+			tty_insert_flip_char(tty, pkt->payload[i], 0);
-+		}
-+		tty_flip_buffer_push(tty);
-+
-+		kfree(pkt); /* make sure we free the packet */
-+	}
-+
-+}
-+
-+
-+static struct tty_driver serial_tty_driver = {
-+	.magic= TTY_DRIVER_MAGIC,
-+	.driver_name= "usbfn-tty",
-+	.name= "usb/ttsdev/%d",
-+	.major= SERIAL_TTY_MAJOR,
-+	.minor_start= 0,
-+	.num= NUM_PORTS,
-+	.type= TTY_DRIVER_TYPE_SERIAL,
-+	.subtype= SERIAL_TYPE_NORMAL,
-+	.flags= TTY_DRIVER_REAL_RAW | TTY_DRIVER_NO_DEVFS,
-+	.refcount= &serial_refcount,
-+	.table= serial_tty,
-+	.termios= serial_termios,
-+	.termios_locked= serial_termios_locked,
-+
-+	.open= serial_open,
-+	.close= serial_close,
-+	.write= serial_write,
-+	.write_room= serial_write_room,
-+	.ioctl= serial_ioctl,
-+	.set_termios= serial_set_termios,
-+	.throttle= serial_throttle,
-+	.unthrottle= serial_unthrottle,
-+	.break_ctl= serial_break,
-+	.chars_in_buffer= serial_chars_in_buffer,
-+};
-+
-+
-+void usbfn_tty_exit(void)
-+{
-+	int i;
-+	
-+	/* kill the device layer */
-+	usbdev_exit();
-+
-+	for (i=0; i < NUM_PORTS; i++) {
-+		tty_unregister_devfs(&serial_tty_driver, i);
-+		info("usb serial converter now disconnected from ttyUSBdev%d",
-+		     i);
-+	}
-+
-+	tty_unregister_driver(&serial_tty_driver);
-+
-+	if (usbtty.str_desc_buf)
-+		kfree(usbtty.str_desc_buf);
-+}
-+
-+
-+int usbfn_tty_init(void)
-+{
-+	int ret = 0, i, str_desc_len;
-+
-+	/* register the tty driver */
-+	serial_tty_driver.init_termios = tty_std_termios;
-+	serial_tty_driver.init_termios.c_cflag =
-+		B9600 | CS8 | CREAD | HUPCL | CLOCAL;
-+	
-+	if (tty_register_driver(&serial_tty_driver)) {
-+		err(__FUNCTION__ ": failed to register tty driver");
-+		ret = -ENXIO;
-+		goto out;
-+	}
-+
-+	/*
-+	 * initialize pointers to descriptors
-+	 */
-+	usbtty.dev_desc = &dev_desc;
-+	usbtty.config_desc = &config_desc;
-+	usbtty.if_desc = &if_desc;
-+
-+	/*
-+	 * initialize the string descriptors
-+	 */
-+
-+	/* alloc buffer big enough for all string descriptors */
-+	str_desc_len = string_desc0.bLength;
-+	for (i = 0; i < 5; i++)
-+		str_desc_len += 2 + 2 * strlen(strings[i]);
-+	usbtty.str_desc_buf = (void *) kmalloc(str_desc_len, GFP_KERNEL);
-+	if (!usbtty.str_desc_buf) {
-+		err(__FUNCTION__ ": failed to alloc string descriptors");
-+		ret = -ENOMEM;
-+		goto out;
-+	}
-+
-+	usbtty.str_desc[0] =
-+		(struct usb_string_descriptor *)usbtty.str_desc_buf;
-+	memcpy(usbtty.str_desc[0], &string_desc0, string_desc0.bLength);
-+	usbtty.str_desc[1] = (struct usb_string_descriptor *)
-+		(usbtty.str_desc_buf + string_desc0.bLength);
-+	for (i = 1; i < 6; i++) {
-+		struct usb_string_descriptor *desc = usbtty.str_desc[i];
-+		char *str = strings[i - 1];
-+		int j, str_len = strlen(str);
-+
-+		desc->bLength = 2 + 2 * str_len;
-+		desc->bDescriptorType = USB_DT_STRING;
-+		for (j = 0; j < str_len; j++) {
-+			desc->wData[j] = (u16) str[j];
-+		}
-+		if (i < 5)
-+			usbtty.str_desc[i + 1] =
-+				(struct usb_string_descriptor *)
-+				((u8 *) desc + desc->bLength);
-+	}
-+
-+	/*
-+	 * start the device layer. The device layer assigns us
-+	 * our endpoint addresses
-+	 */
-+	if ((ret = usbdev_init(&dev_desc, &config_desc, &if_desc, ep_desc,
-+			       usbtty.str_desc, usbtty_callback, NULL))) {
-+		err(__FUNCTION__ ": device-layer init failed");
-+		goto out;
-+	}
-+	
-+	/* initialize the devfs nodes for this device and let the user
-+	   know what ports we are bound to */
-+	for (i = 0; i < NUM_PORTS; ++i) {
-+		struct usb_serial_port *port;
-+		tty_register_devfs(&serial_tty_driver, 0, i);
-+		info("usbdev serial attached to ttyUSBdev%d "
-+		     "(or devfs usb/ttsdev/%d)", i, i);
-+		port = &usbtty.port[i];
-+		port->number = i;
-+		port->in_desc = &ep_desc[NUM_PORTS*i];
-+		port->out_desc = &ep_desc[NUM_PORTS*i + 1];
-+		port->in_ep_addr = port->in_desc->bEndpointAddress & 0x0f;
-+		port->out_ep_addr = port->out_desc->bEndpointAddress & 0x0f;
-+		port->send_complete_tq.routine = port_send_complete;
-+		port->send_complete_tq.data = port;
-+		port->receive_complete_tq.routine = port_receive_complete;
-+		port->receive_complete_tq.data = port;
-+		spin_lock_init(&port->port_lock);
-+	}
-+
-+ out:
-+	if (ret)
-+		usbfn_tty_exit();
-+	return ret;
-+}
-+
-+
-+/* Module information */
-+MODULE_AUTHOR("Steve Longerbeam, stevel@mvista.com, www.mvista.com");
-+MODULE_DESCRIPTION("Au1x00 USB Device-Side Serial TTY Driver");
-+MODULE_LICENSE("GPL");
-+
-+module_init(usbfn_tty_init);
-+module_exit(usbfn_tty_exit);
-diff -Naur linux-2.6.17.orig/drivers/char/decserial.c linux-2.6.17/drivers/char/decserial.c
---- linux-2.6.17.orig/drivers/char/decserial.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/drivers/char/decserial.c	2006-06-19 18:16:13.000000000 -0700
-@@ -14,87 +14,85 @@
-  *      device. Added support for PROM console in drivers/char/tty_io.c
-  *      instead. Although it may work to enable more than one 
-  *      console device I strongly recommend to use only one.
-+ *
-+ *	Copyright (C) 2004  Maciej W. Rozycki
-  */
- 
- #include <linux/config.h>
-+#include <linux/errno.h>
- #include <linux/init.h>
--#include <asm/dec/machtype.h>
--
--#ifdef CONFIG_ZS
--extern int zs_init(void);
--#endif
- 
--#ifdef CONFIG_DZ
--extern int dz_init(void);
--#endif
-+#include <asm/dec/machtype.h>
-+#include <asm/dec/serial.h>
- 
--#ifdef CONFIG_SERIAL_CONSOLE
-+extern int register_zs_hook(unsigned int channel,
-+			    struct dec_serial_hook *hook);
-+extern int unregister_zs_hook(unsigned int channel);
- 
-+int register_dec_serial_hook(unsigned int channel,
-+			     struct dec_serial_hook *hook)
-+{
- #ifdef CONFIG_ZS
--extern void zs_serial_console_init(void);
--#endif
--
--#ifdef CONFIG_DZ
--extern void dz_serial_console_init(void);
-+	if (IOASIC)
-+		return register_zs_hook(channel, hook);
- #endif
-+	return 0;
-+}
- 
-+int unregister_dec_serial_hook(unsigned int channel)
-+{
-+#ifdef CONFIG_ZS
-+	if (IOASIC)
-+		return unregister_zs_hook(channel);
- #endif
-+	return 0;
-+}
- 
--/* rs_init - starts up the serial interface -
--   handle normal case of starting up the serial interface */
- 
--#ifdef CONFIG_SERIAL
-+extern int zs_init(void);
-+extern int dz_init(void);
- 
-+/*
-+ * rs_init - starts up the serial interface -
-+ * handle normal case of starting up the serial interface
-+ */
- int __init rs_init(void)
- {
--
--#if defined(CONFIG_ZS) && defined(CONFIG_DZ)
--    if (IOASIC)
--	return zs_init();
--    else
--	return dz_init();
--#else
--
- #ifdef CONFIG_ZS
--    return zs_init();
-+	if (IOASIC)
-+		return zs_init();
- #endif
--
- #ifdef CONFIG_DZ
--    return dz_init();
--#endif
--
-+	if (!IOASIC)
-+		return dz_init();
- #endif
-+	return -ENXIO;
- }
- 
- __initcall(rs_init);
- 
--#endif
- 
--#ifdef CONFIG_SERIAL_CONSOLE
-+#ifdef CONFIG_SERIAL_DEC_CONSOLE
-+
-+extern void zs_serial_console_init(void);
-+extern void dz_serial_console_init(void);
- 
--/* serial_console_init handles the special case of starting
-- *   up the console on the serial port
-+/*
-+ * dec_serial_console_init handles the special case of starting
-+ * up the console on the serial port
-  */
--static int __init decserial_console_init(void)
-+static int __init dec_serial_console_init(void)
- {
--#if defined(CONFIG_ZS) && defined(CONFIG_DZ)
--    if (IOASIC)
--	zs_serial_console_init();
--    else
--	dz_serial_console_init();
--#else
--
- #ifdef CONFIG_ZS
--    zs_serial_console_init();
-+	if (IOASIC)
-+		zs_serial_console_init();
- #endif
--
- #ifdef CONFIG_DZ
--    dz_serial_console_init();
--#endif
--
-+	if (!IOASIC)
-+		dz_serial_console_init();
- #endif
-     return 0;
- }
--console_initcall(decserial_console_init);
-+console_initcall(dec_serial_console_init);
- 
- #endif
-diff -Naur linux-2.6.17.orig/drivers/char/ibm_workpad_keymap.map linux-2.6.17/drivers/char/ibm_workpad_keymap.map
---- linux-2.6.17.orig/drivers/char/ibm_workpad_keymap.map	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/drivers/char/ibm_workpad_keymap.map	2006-06-19 18:16:13.000000000 -0700
-@@ -0,0 +1,343 @@
-+# Keymap for IBM Workpad z50
-+# US Mapping
-+#
-+# by Michael Klar <wyldfier@iname.com>
-+#
-+# This is a great big mess on account of how the Caps Lock key is handled as
-+# LeftShift-RightShift.  Right shift key had to be broken out, so don't use
-+# use this map file as a basis for other keyboards that don't do the same
-+# thing with Caps Lock.
-+#
-+# This file is subject to the terms and conditions of the GNU General Public
-+# License.  See the file "COPYING" in the main directory of this archive
-+# for more details.
-+
-+keymaps 0-2,4-5,8,12,32-33,36-37
-+strings as usual
-+
-+keycode 0 = F1 F11 Console_13
-+	shiftr keycode 0 = F11
-+	shift shiftr keycode 0 = F11
-+	control keycode 0 = F1
-+	alt keycode 0 = Console_1
-+	control alt keycode 0 = Console_1
-+keycode 1 = F3 F13 Console_15
-+	shiftr keycode 1 = F13
-+	shift shiftr keycode 1 = F13
-+	control keycode 1 = F3
-+	alt keycode 1 = Console_3
-+	control alt keycode 1 = Console_3
-+keycode 2 = F5 F15 Console_17
-+	shiftr keycode 2 = F15
-+	shift shiftr keycode 2 = F15
-+	control keycode 2 = F5
-+	alt keycode 2 = Console_5
-+	control alt keycode 2 = Console_5
-+keycode 3 = F7 F17 Console_19
-+	shiftr keycode 3 = F17
-+	shift shiftr keycode 3 = F17
-+	control keycode 3 = F7
-+	alt keycode 3 = Console_7
-+	control alt keycode 3 = Console_7
-+keycode 4 = F9 F19 Console_21
-+	shiftr keycode 4 = F19
-+	shift shiftr keycode 4 = F19
-+	control keycode 4 = F9
-+	alt keycode 4 = Console_9
-+	control alt keycode 4 = Console_9
-+#keycode 5 is contrast down
-+#keycode 6 is contrast up
-+keycode 7 = F11 F11 Console_23
-+	shiftr keycode 7 = F11
-+	shift shiftr keycode 7 = F11
-+	control keycode 7 = F11
-+	alt keycode 7 = Console_11
-+	control alt keycode 7 = Console_11
-+keycode 8 = F2 F12 Console_14
-+	shiftr keycode 8 = F12
-+	shift shiftr keycode 8 = F12
-+	control keycode 8 = F2
-+	alt keycode 8 = Console_2
-+	control alt keycode 8 = Console_2
-+keycode 9 = F4 F14 Console_16
-+	shiftr keycode 9 = F14
-+	shift shiftr keycode 9 = F14
-+	control keycode 9 = F4
-+	alt keycode 9 = Console_4
-+	control alt keycode 9 = Console_4
-+keycode 10 = F6 F16 Console_18
-+	shiftr keycode 10 = F16
-+	shift shiftr keycode 10 = F16
-+	control keycode 10 = F6
-+	alt keycode 10 = Console_6
-+	control alt keycode 10 = Console_6
-+keycode 11 = F8 F18 Console_20
-+	shiftr keycode 11 = F18
-+	shift shiftr keycode 11 = F18
-+	control keycode 11 = F8
-+	alt keycode 11 = Console_8
-+	control alt keycode 11 = Console_8
-+keycode 12 = F10 F20 Console_22
-+	shiftr keycode 12 = F20
-+	shift shiftr keycode 12 = F20
-+	control keycode 12 = F10
-+	alt keycode 12 = Console_10
-+	control alt keycode 12 = Console_10
-+#keycode 13 is brightness down
-+#keycode 14 is brightness up
-+keycode 15 = F12 F12 Console_24
-+	shiftr keycode 15 = F12
-+	shift shiftr keycode 15 = F12
-+	control keycode 15 = F12
-+	alt keycode 15 = Console_12
-+	control alt keycode 15 = Console_12
-+keycode 16 = apostrophe quotedbl
-+	shiftr keycode 16 = quotedbl
-+	shift shiftr keycode 16 = quotedbl
-+	control keycode 16 = Control_g
-+	alt keycode 16 = Meta_apostrophe
-+keycode 17 = bracketleft braceleft
-+	shiftr keycode 17 = braceleft
-+	shift shiftr keycode 17 = braceleft
-+	control keycode 17 = Escape
-+	alt keycode 17 = Meta_bracketleft
-+keycode 18 = minus underscore backslash       
-+	shiftr keycode 18 = underscore
-+	shift shiftr keycode 18 = underscore
-+	control keycode 18 = Control_underscore
-+	shift control keycode 18 = Control_underscore
-+	shiftr control keycode 18 = Control_underscore
-+	shift shiftr control keycode 18 = Control_underscore
-+	alt keycode 18 = Meta_minus
-+keycode 19 = zero parenright braceright
-+	shiftr keycode 19 = parenright
-+	shift shiftr keycode 19 = parenright
-+	alt keycode 19 = Meta_zero
-+keycode 20 = p
-+	shiftr keycode 20 = +P
-+	shift shiftr keycode 20 = +p
-+keycode 21 = semicolon colon
-+	shiftr keycode 21 = colon
-+	shift shiftr keycode 21 = colon
-+	alt keycode 21 = Meta_semicolon
-+keycode 22 = Up Scroll_Backward
-+	shiftr keycode 22 = Scroll_Backward
-+	shift shiftr keycode 22 = Scroll_Backward
-+	alt keycode 22 = Prior
-+keycode 23 = slash question
-+	shiftr keycode 23 = question
-+	shift shiftr keycode 23 = question
-+	control keycode 23 = Delete
-+	alt keycode 23 = Meta_slash
-+
-+keycode 27 = nine parenleft bracketright
-+	shiftr keycode 27 = parenleft
-+	shift shiftr keycode 27 = parenleft
-+	alt keycode 27 = Meta_nine
-+keycode 28 = o
-+	shiftr keycode 28 = +O
-+	shift shiftr keycode 28 = +o
-+keycode 29 = l
-+	shiftr keycode 29 = +L
-+	shift shiftr keycode 29 = +l
-+keycode 30 = period greater
-+	shiftr keycode 30 = greater
-+	shift shiftr keycode 30 = greater
-+	control keycode 30 = Compose
-+	alt keycode 30 = Meta_period
-+
-+keycode 32 = Left Decr_Console
-+	shiftr keycode 32 = Decr_Console
-+	shift shiftr keycode 32 = Decr_Console
-+	alt keycode 32 = Home
-+keycode 33 = bracketright braceright asciitilde      
-+	shiftr keycode 33 = braceright
-+	shift shiftr keycode 33 = braceright
-+	control keycode 33 = Control_bracketright
-+	alt keycode 33 = Meta_bracketright
-+keycode 34 = equal plus
-+	shiftr keycode 34 = plus
-+	shift shiftr keycode 34 = plus
-+	alt keycode 34 = Meta_equal
-+keycode 35 = eight asterisk bracketleft
-+	shiftr keycode 35 = asterisk
-+	shift shiftr keycode 35 = asterisk
-+	control keycode 35 = Delete
-+	alt keycode 35 = Meta_eight
-+keycode 36 = i
-+	shiftr keycode 36 = +I
-+	shift shiftr keycode 36 = +i
-+keycode 37 = k
-+	shiftr keycode 37 = +K
-+	shift shiftr keycode 37 = +k
-+keycode 38 = comma less
-+	shiftr keycode 38 = less
-+	shift shiftr keycode 38 = less
-+	alt keycode 38 = Meta_comma
-+
-+keycode 40 = h
-+	shiftr keycode 40 = +H
-+	shift shiftr keycode 40 = +h
-+keycode 41 = y
-+	shiftr keycode 41 = +Y
-+	shift shiftr keycode 41 = +y
-+keycode 42 = six asciicircum
-+	shiftr keycode 42 = asciicircum
-+	shift shiftr keycode 42 = asciicircum
-+	control keycode 42 = Control_asciicircum
-+	alt keycode 42 = Meta_six
-+keycode 43 = seven ampersand braceleft
-+	shiftr keycode 43 = ampersand
-+	shift shiftr keycode 43 = ampersand
-+	control keycode 43 = Control_underscore
-+	alt keycode 43 = Meta_seven
-+keycode 44 = u
-+	shiftr keycode 44 = +U
-+	shift shiftr keycode 44 = +u
-+keycode 45 = j
-+	shiftr keycode 45 = +J
-+	shift shiftr keycode 45 = +j
-+keycode 46 = m
-+	shiftr keycode 46 = +M
-+	shift shiftr keycode 46 = +m
-+keycode 47 = n
-+	shiftr keycode 47 = +N
-+	shift shiftr keycode 47 = +n
-+
-+# This is the "Backspace" key:
-+keycode 49 = Delete Delete
-+	shiftr keycode 49 = Delete
-+	shift shiftr keycode 49 = Delete
-+	control keycode 49 = BackSpace
-+	alt keycode 49 = Meta_Delete
-+keycode 50 = Num_Lock
-+	shift keycode 50 = Bare_Num_Lock
-+	shiftr keycode 50 = Bare_Num_Lock
-+	shift shiftr keycode 50 = Bare_Num_Lock
-+# This is the "Delete" key:
-+keycode 51 = Remove
-+	control alt keycode 51 = Boot
-+
-+keycode 53 = backslash bar
-+	shiftr keycode 53 = bar
-+	shift shiftr keycode 53 = bar
-+	control keycode 53 = Control_backslash
-+	alt keycode 53 = Meta_backslash
-+keycode 54 = Return
-+	alt keycode 54 = Meta_Control_m
-+keycode 55 = space space           
-+	shiftr keycode 55 = space
-+	shift shiftr keycode 55 = space
-+	control keycode 55 = nul
-+	alt keycode 55 = Meta_space
-+keycode 56 = g
-+	shiftr keycode 56 = +G
-+	shift shiftr keycode 56 = +g
-+keycode 57 = t
-+	shiftr keycode 57 = +T
-+	shift shiftr keycode 57 = +t
-+keycode 58 = five percent
-+	shiftr keycode 58 = percent
-+	shift shiftr keycode 58 = percent
-+	control keycode 58 = Control_bracketright
-+	alt keycode 58 = Meta_five
-+keycode 59 = four dollar dollar
-+	shiftr keycode 59 = dollar
-+	shift shiftr keycode 59 = dollar
-+	control keycode 59 = Control_backslash
-+	alt keycode 59 = Meta_four
-+keycode 60 = r
-+	shiftr keycode 60 = +R
-+	shift shiftr keycode 60 = +r
-+keycode 61 = f
-+	shiftr keycode 61 = +F
-+	shift shiftr keycode 61 = +f
-+	altgr keycode 61 = Hex_F
-+keycode 62 = v
-+	shiftr keycode 62 = +V
-+	shift shiftr keycode 62 = +v
-+keycode 63 = b
-+	shiftr keycode 63 = +B
-+	shift shiftr keycode 63 = +b
-+	altgr keycode 63 = Hex_B
-+
-+keycode 67 = three numbersign
-+	shiftr keycode 67 = numbersign
-+	shift shiftr keycode 67 = numbersign
-+	control keycode 67 = Escape
-+	alt keycode 67 = Meta_three
-+keycode 68 = e
-+	shiftr keycode 68 = +E
-+	shift shiftr keycode 68 = +e
-+	altgr keycode 68 = Hex_E
-+keycode 69 = d
-+	shiftr keycode 69 = +D
-+	shift shiftr keycode 69 = +d
-+	altgr keycode 69 = Hex_D
-+keycode 70 = c
-+	shiftr keycode 70 = +C
-+	shift shiftr keycode 70 = +c
-+	altgr keycode 70 = Hex_C
-+keycode 71 = Right Incr_Console
-+	shiftr keycode 71 = Incr_Console
-+	shift shiftr keycode 71 = Incr_Console
-+	alt keycode 71 = End
-+
-+keycode 75 = two at at
-+	shiftr keycode 75 = at
-+	shift shiftr keycode 75 = at
-+	control keycode 75 = nul
-+	shift control keycode 75 = nul
-+	shiftr control keycode 75 = nul
-+	shift shiftr control keycode 75 = nul
-+	alt keycode 75 = Meta_two
-+keycode 76 = w
-+	shiftr keycode 76 = +W
-+	shift shiftr keycode 76 = +w
-+keycode 77 = s
-+	shiftr keycode 77 = +S
-+	shift shiftr keycode 77 = +s
-+keycode 78 = x
-+	shiftr keycode 78 = +X
-+	shift shiftr keycode 78 = +x
-+keycode 79 = Down Scroll_Forward
-+	shiftr keycode 79 = Scroll_Forward
-+	shift shiftr keycode 79 = Scroll_Forward
-+	alt keycode 79 = Next
-+keycode 80 = Escape Escape
-+	shiftr keycode 80 = Escape
-+	shift shiftr keycode 80 = Escape
-+	alt keycode 80 = Meta_Escape
-+keycode 81 = Tab Tab             
-+	shiftr keycode 81 = Tab
-+	shift shiftr keycode 81 = Tab
-+	alt keycode 81 = Meta_Tab
-+keycode 82 = grave asciitilde
-+	shiftr keycode 82 = asciitilde
-+	shift shiftr keycode 82 = asciitilde
-+	control keycode 82 = nul
-+	alt keycode 82 = Meta_grave
-+keycode 83 = one exclam
-+	shiftr keycode 83 = exclam
-+	shift shiftr keycode 83 = exclam
-+	alt keycode 83 = Meta_one
-+keycode 84 = q
-+	shiftr keycode 84 = +Q
-+	shift shiftr keycode 84 = +q
-+keycode 85 = a
-+	shiftr keycode 85 = +A
-+	shift shiftr keycode 85 = +a
-+	altgr keycode 85 = Hex_A
-+keycode 86 = z
-+	shiftr keycode 86 = +Z
-+	shift shiftr keycode 86 = +z
-+
-+# This is the windows key:
-+keycode 88 = Decr_Console
-+keycode 89 = Shift
-+keycode 90 = Control
-+keycode 91 = Control
-+keycode 92 = Alt
-+keycode 93 = AltGr
-+keycode 94 = ShiftR
-+	shift keycode 94 = Caps_Lock
-diff -Naur linux-2.6.17.orig/drivers/char/Kconfig linux-2.6.17/drivers/char/Kconfig
---- linux-2.6.17.orig/drivers/char/Kconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/drivers/char/Kconfig	2006-06-19 18:16:13.000000000 -0700
-@@ -340,23 +340,68 @@
- 	  To compile this driver as a module, choose M here: the
- 	  module will be called istallion.
- 
--config AU1000_UART
--	bool "Enable Au1000 UART Support"
--	depends on SERIAL_NONSTANDARD && MIPS
--	help
--	  If you have an Alchemy AU1000 processor (MIPS based) and you want
--	  to use serial ports, say Y.  Otherwise, say N.
--
--config AU1000_SERIAL_CONSOLE
--	bool "Enable Au1000 serial console"
--	depends on AU1000_UART
-+config AU1X00_GPIO
-+	tristate "Alchemy Au1000 GPIO device support"
-+	depends on MIPS && SOC_AU1X00
-+
-+config TS_AU1X00_ADS7846
-+	tristate "Au1000/ADS7846 touchscreen support"
-+	depends on MIPS && SOC_AU1X00
-+
-+config AU1X00_USB_TTY
-+	tristate "Au1000 USB TTY Device support"
-+	depends on MIPS && MIPS_AU1000 && AU1000_USB_DEVICE=y && AU1000_USB_DEVICE
-+
-+config AU1X00_USB_RAW
-+	tristate "Au1000 USB Raw Device support"
-+	depends on MIPS && MIPS_AU1000 && AU1000_USB_DEVICE=y && AU1000_USB_TTY!=y && AU1X00_USB_DEVICE
-+
-+config SIBYTE_SB1250_DUART
-+	bool "Support for BCM1xxx onchip DUART"
-+	depends on MIPS && SIBYTE_SB1xxx_SOC=y
-+
-+config SIBYTE_SB1250_DUART_CONSOLE
-+	bool "Console on BCM1xxx DUART"
-+	depends on SIBYTE_SB1250_DUART
-+
-+config SERIAL_DEC
-+	bool "DECstation serial support"
-+	depends on MACH_DECSTATION
-+	default y
- 	help
--	  If you have an Alchemy AU1000 processor (MIPS based) and you want
--	  to use a console on a serial port, say Y.  Otherwise, say N.
-+	  This selects whether you want to be asked about drivers for
-+	  DECstation serial ports.
-+
-+	  Note that the answer to this question won't directly affect the
-+	  kernel: saying N will just cause the configurator to skip all
-+	  the questions about DECstation serial ports.
-+
-+	  If unsure, say Y.
-+
-+config SERIAL_DEC_CONSOLE
-+	bool "Support for console on a DECstation serial port"
-+	depends on SERIAL_DEC
-+	default y
-+	help
-+	  If you say Y here, it will be possible to use a serial port as the
-+	  system console (the system console is the device which receives all
-+	  kernel messages and warnings and which allows logins in single user
-+	  mode).  Note that the firmware uses ttyS0 as the serial console on
-+	  the Maxine and ttyS2 on the others.
-+
-+	  If unsure, say Y.
-+
-+config ZS
-+	bool "Z85C30 Serial Support"
-+	depends on SERIAL_DEC
-+	default y
-+	help
-+	  Documentation on the Zilog 85C350 serial communications controller
-+	  is downloadable at <http://www.zilog.com/pdfs/serial/z85c30.pdf>.
- 
- config QTRONIX_KEYBOARD
- 	bool "Enable Qtronix 990P Keyboard Support"
--	depends on IT8712
-+	depends on MIPS && (MIPS_ITE8172 || MIPS_IVR)
- 	help
- 	  Images of Qtronix keyboards are at
- 	  <http://www.qtronix.com/keyboard.html>.
-@@ -368,7 +413,7 @@
- 
- config IT8172_SCR0
- 	bool "Enable Smart Card Reader 0 Support "
--	depends on IT8712
-+	depends on MIPS && (MIPS_ITE8172 || MIPS_IVR)
- 	help
- 	  Say Y here to support smart-card reader 0 (SCR0) on the Integrated
- 	  Technology Express, Inc. ITE8172 SBC.  Vendor page at
-@@ -377,13 +422,17 @@
- 
- config IT8172_SCR1
- 	bool "Enable Smart Card Reader 1 Support "
--	depends on IT8712
-+	depends on MIPS && (MIPS_ITE8172 || MIPS_IVR)
- 	help
- 	  Say Y here to support smart-card reader 1 (SCR1) on the Integrated
- 	  Technology Express, Inc. ITE8172 SBC.  Vendor page at
- 	  <http://www.ite.com.tw/ia/brief_it8172bsp.htm>; picture of the
- 	  board at <http://www.mvista.com/partners/semiconductor/ite.html>.
- 
-+config ITE_GPIO
-+	tristate "ITE GPIO"
-+	depends on MIPS && MIPS_ITE8172
-+
- config A2232
- 	tristate "Commodore A2232 serial support (EXPERIMENTAL)"
- 	depends on EXPERIMENTAL && ZORRO && BROKEN_ON_SMP
-diff -Naur linux-2.6.17.orig/drivers/char/Makefile linux-2.6.17/drivers/char/Makefile
---- linux-2.6.17.orig/drivers/char/Makefile	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/drivers/char/Makefile	2006-06-19 18:16:13.000000000 -0700
-@@ -31,6 +31,7 @@
- obj-$(CONFIG_A2232)		+= ser_a2232.o generic_serial.o
- obj-$(CONFIG_ATARI_DSP56K)	+= dsp56k.o
- obj-$(CONFIG_MOXA_SMARTIO)	+= mxser.o
-+obj-$(CONFIG_SIBYTE_SB1250_DUART) += sb1250_duart.o
- obj-$(CONFIG_COMPUTONE)		+= ip2/
- obj-$(CONFIG_RISCOM8)		+= riscom8.o
- obj-$(CONFIG_ISI)		+= isicom.o
-@@ -51,6 +52,7 @@
- obj-$(CONFIG_VIOTAPE)		+= viotape.o
- obj-$(CONFIG_HVCS)		+= hvcs.o
- obj-$(CONFIG_SGI_MBCS)		+= mbcs.o
-+obj-$(CONFIG_SERIAL_DEC)	+= decserial.o
- 
- obj-$(CONFIG_PRINTER)		+= lp.o
- obj-$(CONFIG_TIPAR)		+= tipar.o
-@@ -78,6 +80,10 @@
- obj-$(CONFIG_HW_RANDOM)		+= hw_random.o
- obj-$(CONFIG_FTAPE)		+= ftape/
- obj-$(CONFIG_COBALT_LCD)	+= lcd.o
-+obj-$(CONFIG_ITE_GPIO)		+= ite_gpio.o
-+obj-$(CONFIG_AU1000_GPIO)	+= au1000_gpio.o
-+obj-$(CONFIG_AU1000_USB_TTY)	+= au1000_usbtty.o
-+obj-$(CONFIG_AU1000_USB_RAW)	+= au1000_usbraw.o
- obj-$(CONFIG_PPDEV)		+= ppdev.o
- obj-$(CONFIG_NWBUTTON)		+= nwbutton.o
- obj-$(CONFIG_NWFLASH)		+= nwflash.o
-diff -Naur linux-2.6.17.orig/drivers/char/qtronix.c linux-2.6.17/drivers/char/qtronix.c
---- linux-2.6.17.orig/drivers/char/qtronix.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/drivers/char/qtronix.c	2006-06-19 18:16:13.000000000 -0700
-@@ -535,8 +535,7 @@
- 		i--;
- 	}
- 	if (count-i) {
--		struct inode *inode = file->f_dentry->d_inode;
--		inode->i_atime = current_fs_time(inode->i_sb);
-+		file->f_dentry->d_inode->i_atime = get_seconds();
- 		return count-i;
- 	}
- 	if (signal_pending(current))
-diff -Naur linux-2.6.17.orig/drivers/char/rtc.c linux-2.6.17/drivers/char/rtc.c
---- linux-2.6.17.orig/drivers/char/rtc.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/drivers/char/rtc.c	2006-06-19 18:16:13.000000000 -0700
-@@ -35,23 +35,22 @@
-  *	1.09a	Pete Zaitcev: Sun SPARC
-  *	1.09b	Jeff Garzik: Modularize, init cleanup
-  *	1.09c	Jeff Garzik: SMP cleanup
-- *	1.10    Paul Barton-Davis: add support for async I/O
-+ *	1.10	Paul Barton-Davis: add support for async I/O
-  *	1.10a	Andrea Arcangeli: Alpha updates
-  *	1.10b	Andrew Morton: SMP lock fix
-  *	1.10c	Cesar Barros: SMP locking fixes and cleanup
-  *	1.10d	Paul Gortmaker: delete paranoia check in rtc_exit
-  *	1.10e	Maciej W. Rozycki: Handle DECstation's year weirdness.
-- *      1.11    Takashi Iwai: Kernel access functions
-+ *	1.11	Takashi Iwai: Kernel access functions
-  *			      rtc_register/rtc_unregister/rtc_control
-  *      1.11a   Daniele Bellucci: Audit create_proc_read_entry in rtc_init
-- *	1.12	Venkatesh Pallipadi: Hooks for emulating rtc on HPET base-timer
-+ *	1.12    Venkatesh Pallipadi: Hooks for emulating rtc on HPET base-timer
-  *		CONFIG_HPET_EMULATE_RTC
-+ *	1.12a	Maciej W. Rozycki: Handle memory-mapped chips properly.
-  *	1.12ac	Alan Cox: Allow read access to the day of week register
-  */
- 
--#define RTC_VERSION		"1.12ac"
--
--#define RTC_IO_EXTENT	0x8
-+#define RTC_VERSION		"1.12a"
- 
- /*
-  *	Note that *all* calls to CMOS_READ and CMOS_WRITE are done with
-@@ -338,7 +337,15 @@
- 	if (rtc_has_irq == 0)
- 		return -EIO;
- 
--	if (count < sizeof(unsigned))
-+	/*
-+	 * Historically this function used to assume that sizeof(unsigned long)
-+	 * is the same in userspace and kernelspace.  This lead to problems
-+	 * for configurations with multiple ABIs such a the MIPS o32 and 64
-+	 * ABIs supported on the same kernel.  So now we support read of both
-+	 * 4 and 8 bytes and assume that's the sizeof(unsigned long) in the
-+	 * userspace ABI.
-+	 */
-+	if (count != sizeof(unsigned int) && count !=  sizeof(unsigned long))
- 		return -EINVAL;
- 
- 	add_wait_queue(&rtc_wait, &wait);
-@@ -369,10 +376,12 @@
- 		schedule();
- 	} while (1);
- 
--	if (count < sizeof(unsigned long))
--		retval = put_user(data, (unsigned int __user *)buf) ?: sizeof(int); 
-+	if (count == sizeof(unsigned int))
-+		retval = put_user(data, (unsigned int __user *)buf) ?: sizeof(int);
- 	else
- 		retval = put_user(data, (unsigned long __user *)buf) ?: sizeof(long);
-+	if (!retval)
-+		retval = count;
-  out:
- 	current->state = TASK_RUNNING;
- 	remove_wait_queue(&rtc_wait, &wait);
-@@ -924,6 +933,9 @@
- 	struct sparc_isa_device *isa_dev;
- #endif
- #endif
-+#ifndef __sparc__
-+	void *r;
-+#endif
- 
- #ifdef __sparc__
- 	for_each_ebus(ebus) {
-@@ -969,8 +981,13 @@
- 	}
- no_irq:
- #else
--	if (!request_region(RTC_PORT(0), RTC_IO_EXTENT, "rtc")) {
--		printk(KERN_ERR "rtc: I/O port %d is not free.\n", RTC_PORT (0));
-+	if (RTC_IOMAPPED)
-+		r = request_region(RTC_PORT(0), RTC_IO_EXTENT, "rtc");
-+	else
-+		r = request_mem_region(RTC_PORT(0), RTC_IO_EXTENT, "rtc");
-+	if (!r) {
-+		printk(KERN_ERR "rtc: I/O resource %lx is not free.\n",
-+		       (long)(RTC_PORT(0)));
- 		return -EIO;
- 	}
- 
-@@ -984,7 +1001,10 @@
- 	if(request_irq(RTC_IRQ, rtc_int_handler_ptr, SA_INTERRUPT, "rtc", NULL)) {
- 		/* Yeah right, seeing as irq 8 doesn't even hit the bus. */
- 		printk(KERN_ERR "rtc: IRQ %d is not free.\n", RTC_IRQ);
--		release_region(RTC_PORT(0), RTC_IO_EXTENT);
-+		if (RTC_IOMAPPED)
-+			release_region(RTC_PORT(0), RTC_IO_EXTENT);
-+		else
-+			release_mem_region(RTC_PORT(0), RTC_IO_EXTENT);
- 		return -EIO;
- 	}
- 	hpet_rtc_timer_init();
-@@ -1084,7 +1104,10 @@
- 	if (rtc_has_irq)
- 		free_irq (rtc_irq, &rtc_port);
- #else
--	release_region (RTC_PORT (0), RTC_IO_EXTENT);
-+	if (RTC_IOMAPPED)
-+		release_region(RTC_PORT(0), RTC_IO_EXTENT);
-+	else
-+		release_mem_region(RTC_PORT(0), RTC_IO_EXTENT);
- #ifdef RTC_IRQ
- 	if (rtc_has_irq)
- 		free_irq (RTC_IRQ, NULL);
-diff -Naur linux-2.6.17.orig/drivers/char/sb1250_duart.c linux-2.6.17/drivers/char/sb1250_duart.c
---- linux-2.6.17.orig/drivers/char/sb1250_duart.c	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/drivers/char/sb1250_duart.c	2006-06-19 18:16:13.000000000 -0700
-@@ -0,0 +1,911 @@
-+/*
-+ * Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * as published by the Free Software Foundation; either version 2
-+ * of the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ * 
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
-+ */
-+
-+/* 
-+ * Driver support for the on-chip sb1250 dual-channel serial port,
-+ * running in asynchronous mode.  Also, support for doing a serial console
-+ * on one of those ports 
-+ */
-+#include <linux/config.h>
-+#include <linux/types.h>
-+#include <linux/kernel.h>
-+#include <linux/serial.h>
-+#include <linux/interrupt.h>
-+#include <linux/module.h>
-+#include <linux/console.h>
-+#include <linux/kdev_t.h>
-+#include <linux/major.h>
-+#include <linux/termios.h>
-+#include <linux/spinlock.h>
-+#include <linux/irq.h>
-+#include <linux/errno.h>
-+#include <linux/tty.h>
-+#include <linux/sched.h>
-+#include <linux/tty_flip.h>
-+#include <linux/timer.h>
-+#include <linux/init.h>
-+#include <linux/mm.h>
-+#include <asm/delay.h>
-+#include <asm/io.h>
-+#include <asm/uaccess.h>
-+#include <asm/sibyte/swarm.h>
-+#include <asm/sibyte/sb1250.h>
-+#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
-+#include <asm/sibyte/bcm1480_regs.h>
-+#include <asm/sibyte/bcm1480_int.h>
-+#elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
-+#include <asm/sibyte/sb1250_regs.h>
-+#include <asm/sibyte/sb1250_int.h>
-+#else
-+#error invalid SiByte UART configuation
-+#endif
-+#include <asm/sibyte/sb1250_uart.h>
-+#include <asm/war.h>
-+
-+#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
-+#define UNIT_CHANREG(n,reg)	A_BCM1480_DUART_CHANREG((n),(reg))
-+#define UNIT_IMRREG(n)		A_BCM1480_DUART_IMRREG(n)
-+#define UNIT_INT(n)		(K_BCM1480_INT_UART_0 + (n))
-+#elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
-+#define UNIT_CHANREG(n,reg)	A_DUART_CHANREG((n),(reg))
-+#define UNIT_IMRREG(n)		A_DUART_IMRREG(n)
-+#define UNIT_INT(n)		(K_INT_UART_0 + (n))
-+#else
-+#error invalid SiByte UART configuation
-+#endif
-+
-+/* Toggle spewing of debugging output */
-+#undef DEBUG
-+
-+#define DEFAULT_CFLAGS          (CS8 | B115200)
-+
-+#define TX_INTEN          1
-+#define DUART_INITIALIZED 2
-+
-+#define DUART_MAX_LINE 4
-+char sb1250_duart_present[DUART_MAX_LINE];
-+EXPORT_SYMBOL(sb1250_duart_present);
-+
-+/*
-+ * Still not sure what the termios structures set up here are for, 
-+ *  but we have to supply pointers to them to register the tty driver
-+ */
-+static struct tty_driver *sb1250_duart_driver; //, sb1250_duart_callout_driver;
-+
-+/*
-+ * This lock protects both the open flags for all the uart states as 
-+ * well as the reference count for the module
-+ */
-+static DEFINE_SPINLOCK(open_lock);
-+
-+typedef struct { 
-+	unsigned char       outp_buf[SERIAL_XMIT_SIZE];
-+	unsigned int        outp_head;
-+	unsigned int        outp_tail;
-+	unsigned int        outp_count;
-+	spinlock_t          outp_lock;
-+	unsigned int        open;
-+	unsigned int        line;
-+	unsigned int        last_cflags;
-+	unsigned long       flags;
-+	struct tty_struct   *tty;
-+	/* CSR addresses */
-+	volatile u32	    *status;
-+	volatile u32	    *imr;
-+	volatile u32	    *tx_hold;
-+	volatile u32	    *rx_hold;
-+	volatile u32	    *mode_1;
-+	volatile u32	    *mode_2;
-+	volatile u32	    *clk_sel;
-+	volatile u32	    *cmd;
-+} uart_state_t;
-+
-+static uart_state_t uart_states[DUART_MAX_LINE];
-+
-+/*
-+ * Inline functions local to this module 
-+ */
-+
-+/*
-+ * In bug 1956, we get glitches that can mess up uart registers.  This
-+ * "write-mode-1 after any register access" is the accepted
-+ * workaround.
-+ */
-+#if SIBYTE_1956_WAR
-+static unsigned int last_mode1[DUART_MAX_LINE];
-+#endif
-+
-+static inline u32 READ_SERCSR(volatile u32 *addr, int line)
-+{
-+	u32 val = csr_in32(addr);
-+#if SIBYTE_1956_WAR
-+	csr_out32(last_mode1[line], uart_states[line].mode_1);
-+#endif
-+	return val;
-+}
-+
-+static inline void WRITE_SERCSR(u32 val, volatile u32 *addr, int line)
-+{
-+	csr_out32(val, addr);
-+#if SIBYTE_1956_WAR
-+	csr_out32(last_mode1[line], uart_states[line].mode_1);
-+#endif
-+}
-+
-+static void init_duart_port(uart_state_t *port, int line)
-+{
-+	if (!(port->flags & DUART_INITIALIZED)) {
-+		port->line = line;
-+		port->status = IOADDR(UNIT_CHANREG(line, R_DUART_STATUS));
-+		port->imr = IOADDR(UNIT_IMRREG(line));
-+		port->tx_hold = IOADDR(UNIT_CHANREG(line, R_DUART_TX_HOLD));
-+		port->rx_hold = IOADDR(UNIT_CHANREG(line, R_DUART_RX_HOLD));
-+		port->mode_1 = IOADDR(UNIT_CHANREG(line, R_DUART_MODE_REG_1));
-+		port->mode_2 = IOADDR(UNIT_CHANREG(line, R_DUART_MODE_REG_2));
-+		port->clk_sel = IOADDR(UNIT_CHANREG(line, R_DUART_CLK_SEL));
-+		port->cmd = IOADDR(UNIT_CHANREG(line, R_DUART_CMD));
-+		port->flags |= DUART_INITIALIZED;
-+	}
-+}
-+
-+/*
-+ * Mask out the passed interrupt lines at the duart level.  This should be
-+ * called while holding the associated outp_lock.
-+ */
-+static inline void duart_mask_ints(unsigned int line, unsigned int mask)
-+{
-+	uart_state_t *port = uart_states + line;
-+	u64 tmp = READ_SERCSR(port->imr, line);
-+	WRITE_SERCSR(tmp & ~mask, port->imr, line);
-+}
-+
-+	
-+/* Unmask the passed interrupt lines at the duart level */
-+static inline void duart_unmask_ints(unsigned int line, unsigned int mask)
-+{
-+	uart_state_t *port = uart_states + line;
-+	u64 tmp = READ_SERCSR(port->imr, line);
-+	WRITE_SERCSR(tmp | mask, port->imr, line);
-+}
-+
-+static inline void transmit_char_pio(uart_state_t *us)
-+{
-+	struct tty_struct *tty = us->tty;
-+	int blocked = 0;
-+
-+	if (spin_trylock(&us->outp_lock)) {
-+		for (;;) {
-+			if (!(READ_SERCSR(us->status, us->line) & M_DUART_TX_RDY))
-+				break;
-+			if (us->outp_count <= 0 || tty->stopped || tty->hw_stopped) {
-+				break;
-+			} else {
-+				WRITE_SERCSR(us->outp_buf[us->outp_head],
-+					     us->tx_hold, us->line);
-+				us->outp_head = (us->outp_head + 1) & (SERIAL_XMIT_SIZE-1);
-+				if (--us->outp_count <= 0)
-+					break;
-+			}
-+			udelay(10);
-+		}
-+		spin_unlock(&us->outp_lock);
-+	} else {
-+		blocked = 1;
-+	}
-+
-+	if (!us->outp_count || tty->stopped ||
-+	    tty->hw_stopped || blocked) {
-+		us->flags &= ~TX_INTEN;
-+		duart_mask_ints(us->line, M_DUART_IMR_TX);
-+	}
-+
-+      	if (us->open &&
-+	    (us->outp_count < (SERIAL_XMIT_SIZE/2))) {
-+		/*
-+		 * We told the discipline at one point that we had no
-+		 * space, so it went to sleep.  Wake it up when we hit
-+		 * half empty
-+		 */
-+		if ((tty->flags & (1 << TTY_DO_WRITE_WAKEUP)) &&
-+		    tty->ldisc.write_wakeup)
-+			tty->ldisc.write_wakeup(tty);
-+		wake_up_interruptible(&tty->write_wait);
-+	}
-+}
-+
-+/* 
-+ * Generic interrupt handler for both channels.  dev_id is a pointer
-+ * to the proper uart_states structure, so from that we can derive 
-+ * which port interrupted 
-+ */
-+
-+static irqreturn_t duart_int(int irq, void *dev_id, struct pt_regs *regs)
-+{
-+	uart_state_t *us = (uart_state_t *)dev_id;
-+	struct tty_struct *tty = us->tty;
-+	unsigned int status = READ_SERCSR(us->status, us->line);
-+
-+	pr_debug("DUART INT\n");
-+
-+	if (status & M_DUART_RX_RDY) {
-+		int counter = 2048;
-+		unsigned int ch;
-+
-+		if (status & M_DUART_OVRUN_ERR)
-+			tty_insert_flip_char(tty, 0, TTY_OVERRUN);
-+		if (status & M_DUART_PARITY_ERR) {
-+			printk("Parity error!\n");
-+		} else if (status & M_DUART_FRM_ERR) {
-+			printk("Frame error!\n");
-+		}
-+
-+		while (counter > 0) {
-+			if (!(READ_SERCSR(us->status, us->line) & M_DUART_RX_RDY))
-+				break;
-+			ch = READ_SERCSR(us->rx_hold, us->line);
-+			tty_insert_flip_char(tty, ch, 0);
-+			udelay(1);
-+			counter--;
-+		}
-+		tty_flip_buffer_push(tty);
-+	}
-+
-+	if (status & M_DUART_TX_RDY) {
-+		transmit_char_pio(us);
-+	}
-+
-+	return IRQ_HANDLED;
-+}
-+
-+/*
-+ *  Actual driver functions
-+ */
-+
-+/* Return the number of characters we can accomodate in a write at this instant */
-+static int duart_write_room(struct tty_struct *tty)
-+{
-+	uart_state_t *us = (uart_state_t *) tty->driver_data;
-+	int retval;
-+
-+	retval = SERIAL_XMIT_SIZE - us->outp_count;
-+
-+	pr_debug("duart_write_room called, returning %i\n", retval);
-+
-+	return retval;
-+}
-+
-+/* memcpy the data from src to destination, but take extra care if the
-+   data is coming from user space */
-+static inline int copy_buf(char *dest, const char *src, int size, int from_user) 
-+{
-+	if (from_user) {
-+		(void) copy_from_user(dest, src, size); 
-+	} else {
-+		memcpy(dest, src, size);
-+	}
-+	return size;
-+}
-+
-+/*
-+ * Buffer up to count characters from buf to be written.  If we don't have
-+ * other characters buffered, enable the tx interrupt to start sending
-+ */
-+static int duart_write(struct tty_struct *tty, const unsigned char *buf,
-+		       int count)
-+{
-+	uart_state_t *us;
-+	int c, t, total = 0;
-+	unsigned long flags;
-+
-+	if (!tty) return 0;
-+
-+	us = tty->driver_data;
-+	if (!us) return 0;
-+
-+	pr_debug("duart_write called for %i chars by %i (%s)\n", count, current->pid, current->comm);
-+
-+	spin_lock_irqsave(&us->outp_lock, flags);
-+
-+	for (;;) {
-+		c = count;
-+
-+		t = SERIAL_XMIT_SIZE - us->outp_tail;
-+		if (t < c) c = t;
-+
-+		t = SERIAL_XMIT_SIZE - 1 - us->outp_count;
-+		if (t < c) c = t;
-+
-+		if (c <= 0) break;
-+
-+		memcpy(us->outp_buf + us->outp_tail, buf, c);
-+
-+		us->outp_count += c;
-+		us->outp_tail = (us->outp_tail + c) & (SERIAL_XMIT_SIZE - 1);
-+		buf += c;
-+		count -= c;
-+		total += c;
-+	}
-+
-+	spin_unlock_irqrestore(&us->outp_lock, flags);
-+
-+	if (us->outp_count && !tty->stopped && 
-+	    !tty->hw_stopped && !(us->flags & TX_INTEN)) {
-+		us->flags |= TX_INTEN;
-+		duart_unmask_ints(us->line, M_DUART_IMR_TX);
-+	}
-+
-+	return total;
-+}
-+
-+
-+/* Buffer one character to be written.  If there's not room for it, just drop
-+   it on the floor.  This is used for echo, among other things */
-+static void duart_put_char(struct tty_struct *tty, u_char ch)
-+{
-+	uart_state_t *us = (uart_state_t *) tty->driver_data;
-+	unsigned long flags;
-+
-+	pr_debug("duart_put_char called.  Char is %x (%c)\n", (int)ch, ch);
-+
-+	spin_lock_irqsave(&us->outp_lock, flags);
-+
-+	if (us->outp_count == SERIAL_XMIT_SIZE) {
-+		spin_unlock_irqrestore(&us->outp_lock, flags);
-+		return;
-+	}
-+
-+	us->outp_buf[us->outp_tail] = ch;
-+	us->outp_tail = (us->outp_tail + 1) &(SERIAL_XMIT_SIZE-1);
-+	us->outp_count++;
-+
-+	spin_unlock_irqrestore(&us->outp_lock, flags);
-+}
-+
-+static void duart_flush_chars(struct tty_struct * tty)
-+{
-+	uart_state_t *port;
-+
-+	if (!tty) return;
-+
-+	port = tty->driver_data;
-+
-+	if (!port) return;
-+
-+	if (port->outp_count <= 0 || tty->stopped || tty->hw_stopped) {
-+		return;
-+	}
-+
-+	port->flags |= TX_INTEN;
-+	duart_unmask_ints(port->line, M_DUART_IMR_TX);
-+}
-+
-+/* Return the number of characters in the output buffer that have yet to be 
-+   written */
-+static int duart_chars_in_buffer(struct tty_struct *tty)
-+{
-+	uart_state_t *us = (uart_state_t *) tty->driver_data;
-+	int retval;
-+
-+	retval = us->outp_count;
-+
-+	pr_debug("duart_chars_in_buffer returning %i\n", retval);
-+
-+	return retval;
-+}
-+
-+/* Kill everything we haven't yet shoved into the FIFO.  Turn off the
-+   transmit interrupt since we've nothing more to transmit */
-+static void duart_flush_buffer(struct tty_struct *tty)
-+{
-+	uart_state_t *us = (uart_state_t *) tty->driver_data;
-+	unsigned long flags;
-+
-+	pr_debug("duart_flush_buffer called\n");
-+	spin_lock_irqsave(&us->outp_lock, flags);
-+	us->outp_head = us->outp_tail = us->outp_count = 0;
-+	spin_unlock_irqrestore(&us->outp_lock, flags);
-+
-+	wake_up_interruptible(&us->tty->write_wait);
-+	if ((tty->flags & (1 << TTY_DO_WRITE_WAKEUP)) &&
-+	    tty->ldisc.write_wakeup)
-+		tty->ldisc.write_wakeup(tty);
-+}
-+
-+
-+/* See sb1250 user manual for details on these registers */
-+static inline void duart_set_cflag(unsigned int line, unsigned int cflag)
-+{
-+	unsigned int mode_reg1 = 0, mode_reg2 = 0;
-+	unsigned int clk_divisor;
-+	uart_state_t *port = uart_states + line;
-+
-+	switch (cflag & CSIZE) {
-+	case CS7:
-+		mode_reg1 |= V_DUART_BITS_PER_CHAR_7;
-+		
-+	default:
-+		/* We don't handle CS5 or CS6...is there a way we're supposed to flag this? 
-+		   right now we just force them to CS8 */
-+		mode_reg1 |= 0x0;
-+		break;
-+	}
-+	if (cflag & CSTOPB) {
-+	        mode_reg2 |= M_DUART_STOP_BIT_LEN_2;
-+	}
-+	if (!(cflag & PARENB)) {
-+	        mode_reg1 |= V_DUART_PARITY_MODE_NONE;
-+	}
-+	if (cflag & PARODD) {
-+		mode_reg1 |= M_DUART_PARITY_TYPE_ODD;
-+	}
-+	
-+	/* Formula for this is (5000000/baud)-1, but we saturate
-+	   at 12 bits, which means we can't actually do anything less
-+	   that 1200 baud */
-+	switch (cflag & CBAUD) {
-+	case B200:	
-+	case B300:	
-+	case B1200:	clk_divisor = 4095;		break;
-+	case B1800:	clk_divisor = 2776;		break;
-+	case B2400:	clk_divisor = 2082;		break;
-+	case B4800:	clk_divisor = 1040;		break;
-+	default:
-+	case B9600:	clk_divisor = 519;		break;
-+	case B19200:	clk_divisor = 259;		break;
-+	case B38400:	clk_divisor = 129;		break;
-+	case B57600:	clk_divisor = 85;		break;
-+	case B115200:	clk_divisor = 42;		break;
-+	}
-+	WRITE_SERCSR(mode_reg1, port->mode_1, port->line);
-+	WRITE_SERCSR(mode_reg2, port->mode_2, port->line);
-+	WRITE_SERCSR(clk_divisor, port->clk_sel, port->line);
-+	port->last_cflags = cflag;
-+}
-+
-+
-+/* Handle notification of a termios change.  */
-+static void duart_set_termios(struct tty_struct *tty, struct termios *old)
-+{
-+	uart_state_t *us = (uart_state_t *) tty->driver_data;
-+
-+	pr_debug("duart_set_termios called by %i (%s)\n", current->pid, current->comm);
-+	if (old && tty->termios->c_cflag == old->c_cflag)
-+		return;
-+	duart_set_cflag(us->line, tty->termios->c_cflag);
-+}
-+
-+static int get_serial_info(uart_state_t *us, struct serial_struct * retinfo) {
-+
-+	struct serial_struct tmp;
-+
-+	memset(&tmp, 0, sizeof(tmp));
-+
-+	tmp.type=PORT_SB1250;
-+	tmp.line=us->line;
-+	tmp.port=UNIT_CHANREG(tmp.line,0);
-+	tmp.irq=UNIT_INT(tmp.line);
-+	tmp.xmit_fifo_size=16; /* fixed by hw */
-+	tmp.baud_base=5000000;
-+	tmp.io_type=SERIAL_IO_MEM;
-+
-+	if (copy_to_user(retinfo,&tmp,sizeof(*retinfo)))
-+		return -EFAULT;
-+
-+	return 0;
-+}
-+
-+static int duart_ioctl(struct tty_struct *tty, struct file * file,
-+		       unsigned int cmd, unsigned long arg)
-+{
-+	uart_state_t *us = (uart_state_t *) tty->driver_data;
-+
-+/*	if (serial_paranoia_check(info, tty->device, "rs_ioctl"))
-+	return -ENODEV;*/
-+	switch (cmd) {
-+	case TIOCMGET:
-+		printk("Ignoring TIOCMGET\n");
-+		break;
-+	case TIOCMBIS:
-+		printk("Ignoring TIOCMBIS\n");
-+		break;
-+	case TIOCMBIC:
-+		printk("Ignoring TIOCMBIC\n");
-+		break;
-+	case TIOCMSET:
-+		printk("Ignoring TIOCMSET\n");
-+		break;
-+	case TIOCGSERIAL:
-+		return get_serial_info(us,(struct serial_struct *) arg);
-+	case TIOCSSERIAL:
-+		printk("Ignoring TIOCSSERIAL\n");
-+		break;
-+	case TIOCSERCONFIG:
-+		printk("Ignoring TIOCSERCONFIG\n");
-+		break;
-+	case TIOCSERGETLSR: /* Get line status register */
-+		printk("Ignoring TIOCSERGETLSR\n");
-+		break;
-+	case TIOCSERGSTRUCT:
-+		printk("Ignoring TIOCSERGSTRUCT\n");
-+		break;
-+	case TIOCMIWAIT:
-+		printk("Ignoring TIOCMIWAIT\n");
-+		break;
-+	case TIOCGICOUNT:
-+		printk("Ignoring TIOCGICOUNT\n");
-+		break;
-+	case TIOCSERGWILD:
-+		printk("Ignoring TIOCSERGWILD\n");
-+		break;
-+	case TIOCSERSWILD:
-+		printk("Ignoring TIOCSERSWILD\n");
-+		break;
-+	default:
-+		break;
-+	}
-+//	printk("Ignoring IOCTL %x from pid %i (%s)\n", cmd, current->pid, current->comm);
-+	return -ENOIOCTLCMD;
-+}
-+
-+/* XXXKW locking? */
-+static void duart_start(struct tty_struct *tty)
-+{
-+	uart_state_t *us = (uart_state_t *) tty->driver_data;
-+
-+	pr_debug("duart_start called\n");
-+
-+	if (us->outp_count && !(us->flags & TX_INTEN)) {
-+		us->flags |= TX_INTEN;
-+		duart_unmask_ints(us->line, M_DUART_IMR_TX);
-+	}
-+}
-+
-+/* XXXKW locking? */
-+static void duart_stop(struct tty_struct *tty)
-+{
-+	uart_state_t *us = (uart_state_t *) tty->driver_data;
-+
-+	pr_debug("duart_stop called\n");
-+
-+	if (us->outp_count && (us->flags & TX_INTEN)) {
-+		us->flags &= ~TX_INTEN;
-+		duart_mask_ints(us->line, M_DUART_IMR_TX);
-+	}
-+}
-+
-+/* Not sure on the semantics of this; are we supposed to wait until the stuff
-+   already in the hardware FIFO drains, or are we supposed to wait until 
-+   we've drained the output buffer, too?  I'm assuming the former, 'cause thats
-+   what the other drivers seem to assume 
-+*/
-+
-+static void duart_wait_until_sent(struct tty_struct *tty, int timeout)
-+{
-+	uart_state_t *us = (uart_state_t *) tty->driver_data;
-+	unsigned long orig_jiffies;
-+
-+	orig_jiffies = jiffies;
-+	pr_debug("duart_wait_until_sent(%d)+\n", timeout);
-+	while (!(READ_SERCSR(us->status, us->line) & M_DUART_TX_EMT)) {
-+		set_current_state(TASK_INTERRUPTIBLE);
-+	 	schedule_timeout(1);
-+		if (signal_pending(current))
-+			break;
-+		if (timeout && time_after(jiffies, orig_jiffies + timeout))
-+			break;
-+	}
-+	pr_debug("duart_wait_until_sent()-\n");
-+}
-+
-+/*
-+ * duart_hangup() --- called by tty_hangup() when a hangup is signaled.
-+ */
-+static void duart_hangup(struct tty_struct *tty)
-+{
-+	uart_state_t *us = (uart_state_t *) tty->driver_data;
-+
-+	duart_flush_buffer(tty);
-+	us->open = 0;
-+	us->tty = 0;
-+}
-+
-+/*
-+ * Open a tty line.  Note that this can be called multiple times, so ->open can
-+ * be >1.  Only set up the tty struct if this is a "new" open, e.g. ->open was
-+ * zero
-+ */
-+static int duart_open(struct tty_struct *tty, struct file *filp)
-+{
-+	uart_state_t *us;
-+	unsigned int line = tty->index;
-+	unsigned long flags;
-+
-+	if ((line >= tty->driver->num) || !sb1250_duart_present[line])
-+		return -ENODEV;
-+
-+	pr_debug("duart_open called by %i (%s), tty is %p, rw is %p, ww is %p\n",
-+	       current->pid, current->comm, tty, tty->read_wait,
-+	       tty->write_wait);
-+
-+	us = uart_states + line;
-+	tty->driver_data = us;
-+
-+	spin_lock_irqsave(&open_lock, flags);
-+	if (!us->open) {
-+		us->tty = tty;
-+		us->tty->termios->c_cflag = us->last_cflags;
-+	}
-+	us->open++;
-+	us->flags &= ~TX_INTEN;
-+	duart_unmask_ints(line, M_DUART_IMR_RX);
-+	spin_unlock_irqrestore(&open_lock, flags);
-+
-+	return 0;
-+}
-+
-+
-+/*
-+ * Close a reference count out.  If reference count hits zero, null the
-+ * tty, kill the interrupts.  The tty_io driver is responsible for making
-+ * sure we've cleared out our internal buffers before calling close()
-+ */
-+static void duart_close(struct tty_struct *tty, struct file *filp)
-+{
-+	uart_state_t *us = (uart_state_t *) tty->driver_data;
-+	unsigned long flags;
-+
-+	pr_debug("duart_close called by %i (%s)\n", current->pid, current->comm);
-+
-+	if (!us || !us->open)
-+		return;
-+
-+	spin_lock_irqsave(&open_lock, flags);
-+	if (tty_hung_up_p(filp)) {
-+		spin_unlock_irqrestore(&open_lock, flags);
-+		return;
-+	}
-+
-+	if (--us->open < 0) {
-+		us->open = 0;
-+		printk(KERN_ERR "duart: bad open count: %d\n", us->open);
-+	}
-+	if (us->open) {
-+		spin_unlock_irqrestore(&open_lock, flags);
-+		return;
-+	}
-+
-+	spin_unlock_irqrestore(&open_lock, flags);
-+
-+	tty->closing = 1;
-+
-+	/* Stop accepting input */
-+	duart_mask_ints(us->line, M_DUART_IMR_RX);
-+	/* Wait for FIFO to drain */
-+	while (!(READ_SERCSR(us->status, us->line) & M_DUART_TX_EMT))
-+		;
-+
-+	if (tty->driver->flush_buffer)
-+		tty->driver->flush_buffer(tty);
-+	if (tty->ldisc.flush_buffer)
-+		tty->ldisc.flush_buffer(tty);
-+	tty->closing = 0;
-+}
-+
-+
-+static struct tty_operations duart_ops = {
-+        .open   = duart_open,
-+        .close = duart_close,
-+        .write = duart_write,
-+        .put_char = duart_put_char,
-+        .flush_chars = duart_flush_chars,
-+        .write_room = duart_write_room,
-+        .chars_in_buffer = duart_chars_in_buffer,
-+        .flush_buffer = duart_flush_buffer,
-+        .ioctl = duart_ioctl,
-+//        .throttle = duart_throttle,
-+//        .unthrottle = duart_unthrottle,
-+        .set_termios = duart_set_termios,
-+        .stop = duart_stop,
-+        .start = duart_start,
-+        .hangup = duart_hangup,
-+	.wait_until_sent = duart_wait_until_sent,
-+};
-+
-+/* Initialize the sb1250_duart_present array based on SOC type.  */
-+static void __init sb1250_duart_init_present_lines(void)
-+{
-+	int i, max_lines;
-+
-+	/* Set the number of available units based on the SOC type.  */
-+	switch (soc_type) {
-+	case K_SYS_SOC_TYPE_BCM1x55:
-+	case K_SYS_SOC_TYPE_BCM1x80:
-+		max_lines = 4;
-+		break;
-+	default:
-+		/* Assume at least two serial ports at the normal address.  */
-+		max_lines = 2;
-+		break;
-+	}
-+	if (max_lines > DUART_MAX_LINE)
-+		max_lines = DUART_MAX_LINE;
-+
-+	for (i = 0; i < max_lines; i++)
-+		sb1250_duart_present[i] = 1;
-+}
-+
-+/* Set up the driver and register it, register the UART interrupts.  This
-+   is called from tty_init, or as a part of the module init */
-+static int __init sb1250_duart_init(void) 
-+{
-+	int i;
-+
-+	sb1250_duart_init_present_lines();
-+
-+	sb1250_duart_driver = alloc_tty_driver(DUART_MAX_LINE);
-+	if (!sb1250_duart_driver)
-+		return -ENOMEM;
-+
-+	sb1250_duart_driver->owner = THIS_MODULE;
-+	sb1250_duart_driver->name = "duart";
-+	sb1250_duart_driver->devfs_name = "duart/";
-+	sb1250_duart_driver->major = TTY_MAJOR;
-+	sb1250_duart_driver->minor_start = SB1250_DUART_MINOR_BASE;
-+	sb1250_duart_driver->type            = TTY_DRIVER_TYPE_SERIAL;
-+	sb1250_duart_driver->subtype         = SERIAL_TYPE_NORMAL;
-+	sb1250_duart_driver->init_termios    = tty_std_termios;
-+	sb1250_duart_driver->flags           = TTY_DRIVER_REAL_RAW;
-+	tty_set_operations(sb1250_duart_driver, &duart_ops);
-+
-+	for (i=0; i<DUART_MAX_LINE; i++) {
-+		uart_state_t *port = uart_states + i;
-+
-+		if (!sb1250_duart_present[i])
-+			continue;
-+
-+		init_duart_port(port, i);
-+		spin_lock_init(&port->outp_lock);
-+		duart_mask_ints(i, M_DUART_IMR_ALL);
-+		if (request_irq(UNIT_INT(i), duart_int, 0, "uart", port)) {
-+			panic("Couldn't get uart0 interrupt line");
-+		}
-+		__raw_writeq(M_DUART_RX_EN|M_DUART_TX_EN,
-+			     IOADDR(UNIT_CHANREG(i, R_DUART_CMD)));
-+		duart_set_cflag(i, DEFAULT_CFLAGS);
-+	}
-+
-+	/* Interrupts are now active, our ISR can be called. */
-+
-+	if (tty_register_driver(sb1250_duart_driver)) {
-+		printk(KERN_ERR "Couldn't register sb1250 duart serial driver\n");
-+		put_tty_driver(sb1250_duart_driver);
-+		return 1;
-+	}
-+	return 0;
-+}
-+
-+/* Unload the driver.  Unregister stuff, get ready to go away */
-+static void __exit sb1250_duart_fini(void)
-+{
-+	unsigned long flags;
-+	int i;
-+
-+	local_irq_save(flags);
-+	tty_unregister_driver(sb1250_duart_driver);
-+	put_tty_driver(sb1250_duart_driver);
-+
-+	for (i=0; i<DUART_MAX_LINE; i++) {
-+		if (!sb1250_duart_present[i])
-+			continue;
-+		free_irq(UNIT_INT(i), &uart_states[i]);
-+		disable_irq(UNIT_INT(i));
-+	}
-+	local_irq_restore(flags);
-+}
-+
-+module_init(sb1250_duart_init);
-+module_exit(sb1250_duart_fini);
-+MODULE_DESCRIPTION("SB1250 Duart serial driver");
-+MODULE_AUTHOR("Broadcom Corp.");
-+
-+#ifdef CONFIG_SIBYTE_SB1250_DUART_CONSOLE
-+
-+/*
-+ * Serial console stuff.  Very basic, polling driver for doing serial
-+ * console output.  The console_sem is held by the caller, so we
-+ * shouldn't be interrupted for more console activity.
-+ * XXXKW What about getting interrupted by uart driver activity?
-+ */
-+
-+void serial_outc(unsigned char c, int line)
-+{
-+	uart_state_t *port = uart_states + line;
-+	while (!(READ_SERCSR(port->status, line) & M_DUART_TX_RDY)) ;
-+	WRITE_SERCSR(c, port->tx_hold, line);
-+	while (!(READ_SERCSR(port->status, port->line) & M_DUART_TX_EMT)) ;
-+}
-+
-+static void ser_console_write(struct console *cons, const char *s,
-+	unsigned int count)
-+{
-+	int line = cons->index;
-+	uart_state_t *port = uart_states + line;
-+	u32 imr;
-+
-+	imr = READ_SERCSR(port->imr, line);
-+	WRITE_SERCSR(0, port->imr, line);
-+	while (count--) {
-+		if (*s == '\n')
-+			serial_outc('\r', line);
-+		serial_outc(*s++, line);
-+    	}
-+	WRITE_SERCSR(imr, port->imr, line);
-+}
-+
-+static struct tty_driver *ser_console_device(struct console *c, int *index)
-+{
-+	*index = c->index;
-+	return sb1250_duart_driver;
-+}
-+
-+static int ser_console_setup(struct console *cons, char *str)
-+{
-+	int i;
-+
-+	sb1250_duart_init_present_lines();
-+
-+	for (i=0; i<DUART_MAX_LINE; i++) {
-+		uart_state_t *port = uart_states + i;
-+
-+		if (!sb1250_duart_present[i])
-+			continue;
-+
-+		init_duart_port(port, i);
-+#if SIBYTE_1956_WAR
-+		last_mode1[i] = V_DUART_PARITY_MODE_NONE|V_DUART_BITS_PER_CHAR_8;
-+#endif
-+		WRITE_SERCSR(V_DUART_PARITY_MODE_NONE|V_DUART_BITS_PER_CHAR_8,
-+			     port->mode_1, i);
-+		WRITE_SERCSR(M_DUART_STOP_BIT_LEN_1,
-+			     port->mode_2, i);
-+		WRITE_SERCSR(V_DUART_BAUD_RATE(115200),
-+			     port->clk_sel, i);
-+		WRITE_SERCSR(M_DUART_RX_EN|M_DUART_TX_EN,
-+			     port->cmd, i);
-+	}
-+	return 0;
-+}
-+
-+static struct console sb1250_ser_cons = {
-+	.name		= "duart",
-+	.write		= ser_console_write,
-+	.device		= ser_console_device,
-+	.setup		= ser_console_setup,
-+	.flags		= CON_PRINTBUFFER,
-+	.index		= -1,
-+};
-+
-+static int __init sb1250_serial_console_init(void)
-+{
-+	register_console(&sb1250_ser_cons);
-+	return 0;
-+}
-+
-+console_initcall(sb1250_serial_console_init);
-+
-+#endif /* CONFIG_SIBYTE_SB1250_DUART_CONSOLE */
-diff -Naur linux-2.6.17.orig/drivers/ide/mips/Makefile linux-2.6.17/drivers/ide/mips/Makefile
---- linux-2.6.17.orig/drivers/ide/mips/Makefile	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/drivers/ide/mips/Makefile	2006-06-19 18:16:13.000000000 -0700
-@@ -1,4 +1,4 @@
- obj-$(CONFIG_BLK_DEV_IDE_SWARM)		+= swarm.o
- obj-$(CONFIG_BLK_DEV_IDE_AU1XXX)	+= au1xxx-ide.o
- 
--EXTRA_CFLAGS    := -Idrivers/ide
-+CFLAGS_au1xxx-ide.o := -Idrivers/ide
-diff -Naur linux-2.6.17.orig/drivers/mtd/devices/docprobe.c linux-2.6.17/drivers/mtd/devices/docprobe.c
---- linux-2.6.17.orig/drivers/mtd/devices/docprobe.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/drivers/mtd/devices/docprobe.c	2006-06-19 18:16:13.000000000 -0700
-@@ -84,10 +84,10 @@
- 	0xe4000000,
- #elif defined(CONFIG_MOMENCO_OCELOT)
- 	0x2f000000,
--        0xff000000,
-+	0xff000000,
- #elif defined(CONFIG_MOMENCO_OCELOT_G) || defined (CONFIG_MOMENCO_OCELOT_C)
--        0xff000000,
--##else
-+	0xff000000,
-+#else
- #warning Unknown architecture for DiskOnChip. No default probe locations defined
- #endif
- 	0xffffffff };
-diff -Naur linux-2.6.17.orig/drivers/mtd/devices/Kconfig linux-2.6.17/drivers/mtd/devices/Kconfig
---- linux-2.6.17.orig/drivers/mtd/devices/Kconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/drivers/mtd/devices/Kconfig	2006-06-19 18:16:13.000000000 -0700
-@@ -47,6 +47,11 @@
- 	  accelerator.  Say Y here if you have a DECstation 5000/2x0 or a
- 	  DECsystem 5900 equipped with such a module.
- 
-+	  If you want to compile this driver as a module ( = code which can be
-+	  inserted in and removed from the running kernel whenever you want),
-+	  say M here and read <file:Documentation/modules.txt>.  The module will
-+	  be called ms02-nv.o.
-+
- config MTD_DATAFLASH
- 	tristate "Support for AT45xxx DataFlash"
- 	depends on MTD && SPI_MASTER && EXPERIMENTAL
-diff -Naur linux-2.6.17.orig/drivers/mtd/maps/Kconfig linux-2.6.17/drivers/mtd/maps/Kconfig
---- linux-2.6.17.orig/drivers/mtd/maps/Kconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/drivers/mtd/maps/Kconfig	2006-06-19 18:16:13.000000000 -0700
-@@ -200,8 +200,8 @@
- 	  Support for the flash chip on Tsunami TIG bus.
- 
- config MTD_LASAT
--	tristate "Flash chips on LASAT board"
--	depends on LASAT
-+	tristate "LASAT flash device"
-+	depends on LASAT && MTD_CFI
- 	help
- 	  Support for the flash chips on the Lasat 100 and 200 boards.
- 
-@@ -299,6 +299,18 @@
- 	  Mapping for the Flaga digital module. If you don't have one, ignore
- 	  this setting.
- 
-+config MTD_XXS1500
-+	tristate "MyCable XXS1500 Flash device"
-+	depends on MIPS && MIPS_XXS1500
-+	help
-+	  Flash memory access on MyCable XXS1500 Board
-+
-+config MTD_MTX1
-+	tristate "4-G Systems MTX-1 Flash device"
-+	depends on MIPS && MIPS_MTX1
-+	help
-+	  Flash memory access on 4-G Systems MTX-1 Board
-+
- config MTD_BEECH
- 	tristate "CFI Flash device mapped on IBM 405LP Beech"
- 	depends on MTD_CFI && BEECH
-diff -Naur linux-2.6.17.orig/drivers/mtd/maps/lasat.c linux-2.6.17/drivers/mtd/maps/lasat.c
---- linux-2.6.17.orig/drivers/mtd/maps/lasat.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/drivers/mtd/maps/lasat.c	2006-06-19 18:16:13.000000000 -0700
-@@ -7,7 +7,7 @@
-  * modify it under the terms of the GNU General Public License version
-  * 2 as published by the Free Software Foundation.
-  *
-- * $Id: lasat.c,v 1.9 2004/11/04 13:24:15 gleixner Exp $
-+ * $Id: lasat.c,v 1.7 2004/07/12 21:59:44 dwmw2 Exp $
-  *
-  */
- 
-@@ -50,7 +50,7 @@
- 	ENABLE_VPP((&lasat_map));
- 
- 	lasat_map.phys = lasat_flash_partition_start(LASAT_MTD_BOOTLOADER);
--	lasat_map.virt = ioremap_nocache(
-+	lasat_map.virt = (unsigned long)ioremap_nocache(
- 		        lasat_map.phys, lasat_board_info.li_flash_size);
- 	lasat_map.size = lasat_board_info.li_flash_size;
- 
-diff -Naur linux-2.6.17.orig/drivers/net/big_sur_ge.c linux-2.6.17/drivers/net/big_sur_ge.c
---- linux-2.6.17.orig/drivers/net/big_sur_ge.c	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/drivers/net/big_sur_ge.c	2006-06-19 18:16:13.000000000 -0700
-@@ -0,0 +1,2005 @@
-+/*
-+ * drivers/net/big_sur_ge.c - Driver for PMC-Sierra Big Sur ethernet ports
-+ *
-+ * Copyright (C) 2003 PMC-Sierra Inc.
-+ * Author : Manish Lachwani (lachwani@pmc-sierra.com)
-+ * Copyright (C) 2003 Ralf Baechle (ralf@linux-mips.org)
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * as published by the Free Software Foundation; either version 2
-+ * of the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
-+ *
-+ */
-+
-+/*************************************************************************
-+ * Description :
-+ *
-+ * The driver has three modes of operation: FIFO non-DMA, Simple DMA
-+ * and SG DMA. There is also a Polled mode and an Interrupt mode of
-+ * operation. SG DMA should do zerocopy and check offload. Probably,
-+ * zerocopy on the Rx might also work. Simple DMA is the non-zerocpy
-+ * case on the Tx and the Rx.
-+ *
-+ * We turn on Simple DMA and interrupt mode. Although, support has been
-+ * added for the SG mode also but not for the polled mode. This is a
-+ * Fast Ethernet driver although there will be support for Gigabit soon.
-+ *
-+ * The driver is divided into two parts: Hardware dependent and a
-+ * Hardware independent. There is currently no support for checksum offload
-+ * zerocopy and Rx NAPI. There is support for Interrupt Mitigation.
-+ ****************************************************************************/
-+
-+/*************************************************************
-+ * Hardware Indepenent Part of the driver
-+ *************************************************************/
-+
-+#include <linux/module.h>
-+#include <linux/init.h>
-+#include <linux/netdevice.h>
-+#include <linux/etherdevice.h>
-+#include <linux/skbuff.h>
-+#include <linux/mii.h>
-+#include <asm/io.h>
-+#include <asm/irq.h>
-+
-+#include "big_sur_ge.h"
-+
-+#define TX_TIMEOUT (60*HZ)	/* Transmission timeout is 60 seconds. */
-+
-+static struct net_device *dev_list = NULL;
-+static DEFINE_SPINLOCK(dev_lock);
-+
-+typedef enum DUPLEX { UNKNOWN, HALF_DUPLEX, FULL_DUPLEX } DUPLEX;
-+
-+/* Big Sur Ethernet MAC structure */
-+struct big_sur_ge_enet {
-+	struct net_device_stats stats;	/* Statistics for this device */
-+	struct net_device *next_dev;	/* The next device in dev_list */
-+	struct timer_list phy_timer;	/* PHY monitoring timer */
-+	u32 index;		/* Which interface is this */
-+	u32 save_base_address;	/* Saved physical base address */
-+	struct sk_buff *saved_skb;	/* skb being transmitted */
-+	spinlock_t lock;	/* For atomic access to saved_skb */
-+	u8 mii_addr;		/* The MII address of the PHY */
-+	big_sur_ge emac;	/* GE driver structure */
-+};
-+
-+/* Manish : For testing purposes only */
-+static unsigned char big_sur_mac_addr_base[6] = "00:11:22:33:44:55";
-+
-+/*********************************************************************
-+ * Function Prototypes (whole bunch of them)
-+ *********************************************************************/
-+unsigned long big_sur_ge_dma_control(xdma_channel *);
-+void big_sur_ge_dma_reset(xdma_channel *);
-+static void handle_fifo_intr(big_sur_ge *);
-+void big_sur_ge_check_fifo_recv_error(big_sur_ge *);
-+void big_sur_ge_check_fifo_send_error(big_sur_ge *);
-+static int big_sur_ge_config_fifo(big_sur_ge *);
-+big_sur_ge_config *big_sur_ge_lookup_config(unsigned int);
-+static int big_sur_ge_config_dma(big_sur_ge *);
-+void big_sur_ge_enet_reset(big_sur_ge *);
-+void big_sur_ge_check_mac_error(big_sur_ge *, unsigned long);
-+
-+/*********************************************************************
-+ * DMA Channel Initialization
-+ **********************************************************************/
-+static int big_sur_ge_dma_init(xdma_channel * dma, unsigned long base_address)
-+{
-+	dma->reg_base_address = base_address;
-+	dma->get_ptr = NULL;
-+	dma->put_ptr = NULL;
-+	dma->commit_ptr = NULL;
-+	dma->last_ptr = NULL;
-+	dma->total_desc_count = (unsigned long) NULL;
-+	dma->active_desc_count = (unsigned long) NULL;
-+	dma->ready = 1;		/* DMA channel is ready */
-+
-+	big_sur_ge_dma_reset(dma);
-+
-+	return 0;
-+}
-+
-+/*********************************************************************
-+ * Is the DMA channel ready yet ?
-+ **********************************************************************/
-+static int big_sur_ge_dma_ready(xdma_channel * dma)
-+{
-+	return dma->ready == 1;
-+}
-+
-+/*********************************************************************
-+ * Perform the self test on the DMA channel
-+ **********************************************************************/
-+#define BIG_SUR_GE_CONTROL_REG_RESET_MASK	0x98000000
-+
-+static int big_sur_ge_dma_self_test(xdma_channel * dma)
-+{
-+	unsigned long reg_data;
-+
-+	big_sur_ge_dma_reset(dma);
-+
-+	reg_data = big_sur_ge_dma_control(dma);
-+	if (reg_data != BIG_SUR_GE_CONTROL_REG_RESET_MASK) {
-+		printk(KERN_ERR "DMA Channel Self Test Failed \n");
-+		return -1;
-+	}
-+
-+	return 0;
-+}
-+
-+/*********************************************************************
-+ * Reset the DMA channel
-+ **********************************************************************/
-+static void big_sur_ge_dma_reset(xdma_channel * dma)
-+{
-+	BIG_SUR_GE_WRITE(dma->reg_base_address + BIG_SUR_GE_RST_REG_OFFSET,
-+			 BIG_SUR_GE_RESET_MASK);
-+}
-+
-+/*********************************************************************
-+ * Get control of the DMA channel
-+ **********************************************************************/
-+static unsigned long big_sur_ge_dma_control(xdma_channel * dma)
-+{
-+	return BIG_SUR_GE_READ(dma->reg_base_address +
-+			       BIG_SUR_GE_DMAC_REG_OFFSET);
-+}
-+
-+/*********************************************************************
-+ * Set control of the DMA channel
-+ **********************************************************************/
-+static void big_sur_ge_set_dma_control(xdma_channel * dma, unsigned long control)
-+{
-+	BIG_SUR_GE_WRITE(dma->reg_base_address +
-+			 BIG_SUR_GE_DMAC_REG_OFFSET, control);
-+}
-+
-+/*********************************************************************
-+ * Get the status of the DMA channel
-+ *********************************************************************/
-+static unsigned long big_sur_ge_dma_status(xdma_channel * dma)
-+{
-+	return BIG_SUR_GE_READ(dma->reg_base_address +
-+			       BIG_SUR_GE_DMAS_REG_OFFSET);
-+}
-+
-+/*********************************************************************
-+ * Set the interrupt status of the DMA channel
-+ *********************************************************************/
-+static void big_sur_ge_set_intr_status(xdma_channel * dma, unsigned long status)
-+{
-+	BIG_SUR_GE_WRITE(dma->reg_base_address + BIG_SUR_GE_IS_REG_OFFSET,
-+			 status);
-+}
-+
-+/*********************************************************************
-+ * Get the interrupt status of the DMA channel
-+ *********************************************************************/
-+static unsigned long big_sur_ge_get_intr_status(xdma_channel * dma)
-+{
-+	return BIG_SUR_GE_READ(dma->reg_base_address +
-+			       BIG_SUR_GE_IS_REG_OFFSET);
-+}
-+
-+/*********************************************************************
-+ * Set the Interrupt Enable
-+ *********************************************************************/
-+static void big_sur_ge_set_intr_enable(xdma_channel * dma, unsigned long enable)
-+{
-+	BIG_SUR_GE_WRITE(dma->reg_base_address + BIG_SUR_GE_IE_REG_OFFSET,
-+			 enable);
-+}
-+
-+/*********************************************************************
-+ * Get the Interrupt Enable field to make a check
-+ *********************************************************************/
-+static unsigned long big_sur_ge_get_intr_enable(xdma_channel * dma)
-+{
-+	return BIG_SUR_GE_READ(dma->reg_base_address +
-+			       BIG_SUR_GE_IE_REG_OFFSET);
-+}
-+
-+/*********************************************************************
-+ * Transfer the data over the DMA channel
-+ *********************************************************************/
-+static void big_sur_ge_dma_transfer(xdma_channel * dma, unsigned long *source,
-+			     unsigned long *dest, unsigned long length)
-+{
-+	BIG_SUR_GE_WRITE(dma->reg_base_address + BIG_SUR_GE_SA_REG_OFFSET,
-+			 (unsigned long) source);
-+
-+	BIG_SUR_GE_WRITE(dma->reg_base_address + BIG_SUR_GE_DA_REG_OFFSET,
-+			 (unsigned long) dest);
-+
-+	BIG_SUR_GE_WRITE(dma->reg_base_address + BIG_SUR_GE_LEN_REG_OFFSET,
-+			 length);
-+}
-+
-+/*********************************************************************
-+ * Get the DMA descriptor
-+ *********************************************************************/
-+static int big_sur_ge_get_descriptor(xdma_channel * dma,
-+			      xbuf_descriptor ** buffer_desc)
-+{
-+	unsigned long reg_data;
-+
-+	reg_data = xbuf_descriptor_GetControl(dma->get_ptr);
-+	xbuf_descriptor_SetControl(dma->get_ptr, reg_data |
-+				   BIG_SUR_GE_DMACR_SG_DISABLE_MASK);
-+
-+	*buffer_desc = dma->get_ptr;
-+
-+	dma->get_ptr = xbuf_descriptor_GetNextPtr(dma->get_ptr);
-+	dma->active_desc_count--;
-+
-+	return 0;
-+}
-+
-+/*********************************************************************
-+ * Get the packet count
-+ *********************************************************************/
-+static int big_sur_ge_get_packet_count(xdma_channel * dma)
-+{
-+	return (BIG_SUR_GE_READ
-+		(dma->reg_base_address + BIG_SUR_GE_UPC_REG_OFFSET));
-+}
-+
-+/*********************************************************************
-+ * Descrement the packet count
-+ *********************************************************************/
-+static void big_sur_ge_decr_packet_count(xdma_channel * dma)
-+{
-+	unsigned long reg_data;
-+
-+	reg_data =
-+	    BIG_SUR_GE_READ(dma->base_address + BIG_SUR_GE_UPC_REG_OFFSET);
-+	if (reg_data > 0)
-+		BIG_SUR_GE_WRITE(dma->base_address +
-+				 BIG_SUR_GE_UPC_REG_OFFSET, 1);
-+}
-+
-+/****************************************************************************
-+ * Start of the code that deals with the Packet Fifo
-+ *****************************************************************************/
-+
-+/****************************************************************************
-+ * Init the packet fifo
-+ ****************************************************************************/
-+static int packet_fifo_init(packet_fifo * fifo, u32 reg, u32 data)
-+{
-+	fifo->reg_base_addr = reg;
-+	fifo->data_base_address = data;
-+	fifo->ready_status = 1;
-+
-+	BIG_SUR_GE_FIFO_RESET(fifo);
-+
-+	return 0;
-+}
-+
-+/****************************************************************************
-+ * Packet fifo self test
-+ ****************************************************************************/
-+static int packet_fifo_self_test(packet_fifo * fifo, unsigned long type)
-+{
-+	unsigned long reg_data;
-+
-+	BIG_SUR_GE_FIFO_RESET(fifo);
-+	reg_data =
-+	    BIG_SUR_GE_READ(fifo->reg_base_addr +
-+			    BIG_SUR_GE_COUNT_STATUS_REG_OFFSET);
-+
-+	if (type == BIG_SUR_GE_READ_FIFO_TYPE) {
-+		if (reg_data != BIG_SUR_GE_EMPTY_FULL_MASK) {
-+			printk(KERN_ERR "Read FIFO not empty \n");
-+			return -1;
-+		}
-+	} else if (!(reg_data & BIG_SUR_GE_EMPTY_FULL_MASK)) {
-+		printk(KERN_ERR "Write FIFO is full \n");
-+		return -1;
-+	}
-+
-+	return 0;
-+}
-+
-+/****************************************************************************
-+ * Packet FIFO read
-+ ****************************************************************************/
-+static int packet_fifo_read(packet_fifo * fifo, u8 * buffer, unsigned int len)
-+{
-+	unsigned long fifo_count, word_count, extra_byte;
-+	unsigned long *buffer_data = (unsigned long *) buffer;
-+
-+	fifo_count =
-+	    BIG_SUR_GE_READ(fifo->reg_base_addr +
-+			    BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT);
-+	fifo_count &= BIG_SUR_GE_COUNT_MASK;
-+
-+	if ((fifo_count * BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT) < len)
-+		return -1;
-+
-+	word_count = len / BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT;
-+	extra_byte = len % BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT;
-+
-+	for (fifo_count = 0; fifo_count < word_count; fifo_count++)
-+		buffer_data[fifo_count] =
-+		    BIG_SUR_GE_READ(fifo->reg_base_addr);
-+
-+	if (extra_byte > 0) {
-+		unsigned long last_word;
-+		int *extra_buffer_data =
-+		    (int *) (buffer_data + word_count);
-+
-+		last_word = BIG_SUR_GE_READ(fifo->data_base_address);
-+		if (extra_byte == 1)
-+			extra_buffer_data[0] = (int) (last_word << 24);
-+		else if (extra_byte == 2) {
-+			extra_buffer_data[0] = (int) (last_word << 24);
-+			extra_buffer_data[1] = (int) (last_word << 16);
-+		} else if (extra_byte == 3) {
-+			extra_buffer_data[0] = (int) (last_word << 24);
-+			extra_buffer_data[1] = (int) (last_word << 16);
-+			extra_buffer_data[2] = (int) (last_word << 8);
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+/*****************************************************************************
-+ * Write the data into the packet fifo
-+ *****************************************************************************/
-+static int packet_fifo_write(packet_fifo * fifo, int *buffer, int len)
-+{
-+	unsigned long fifo_count, word_count, extra_byte;
-+	unsigned long *buffer_data = (unsigned long *) buffer;
-+
-+	fifo_count =
-+	    BIG_SUR_GE_READ(fifo->reg_base_addr +
-+			    BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT);
-+	fifo_count &= BIG_SUR_GE_COUNT_MASK;
-+
-+	word_count = len / BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT;
-+	extra_byte = len % BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT;
-+
-+	/* You should see what the ppc driver does here. It just slobbers */
-+	if (extra_byte > 0)
-+		if (fifo_count > (word_count + 1)) {
-+			printk(KERN_ERR
-+			       "No room in the packet send fifo \n");
-+			return -1;
-+		}
-+
-+	for (fifo_count = 0; fifo_count < word_count; fifo_count++)
-+		BIG_SUR_GE_WRITE(fifo->data_base_address,
-+				 buffer_data[fifo_count]);
-+
-+
-+	if (extra_byte > 0) {
-+		unsigned long last_word = 0;
-+		int *extra_buffer_data =
-+		    (int *) (buffer_data + word_count);
-+
-+		if (extra_byte == 1)
-+			last_word = extra_buffer_data[0] << 24;
-+		else if (extra_byte == 2)
-+			last_word = (extra_buffer_data[0] << 24 |
-+				     extra_buffer_data[1] << 16);
-+
-+		else if (extra_byte == 3)
-+			last_word = (extra_buffer_data[0] << 24 |
-+				     extra_buffer_data[1] << 16 |
-+				     extra_buffer_data[2] << 8);
-+
-+
-+		BIG_SUR_GE_WRITE(fifo->data_base_address, last_word);
-+	}
-+
-+	return 0;
-+}
-+
-+
-+/*****************************************************************************
-+ * Interrupt handlers: We handle any errors associated with the FIFO.
-+ * FIFO is for simple dma case and we do want to handle the simple DMA
-+ * case. We dont handle the Scatter Gather DMA for now since it is not working.
-+ ******************************************************************************/
-+
-+/*********************************************************************************
-+ * FIFO send for Simple DMA with Interrupts
-+ **********************************************************************************/
-+static int big_sur_ge_enet_fifo_send(big_sur_ge * emac, u8 * buffer,
-+			      unsigned long byte_cnt)
-+{
-+	unsigned long int_status, reg_data;
-+
-+	/* Silly checks here that we really dont need */
-+	if (!emac->started)
-+		return -1;
-+
-+	if (emac->polled)
-+		return -1;
-+
-+	if (emac->dma_sg)
-+		return -1;
-+
-+	int_status =
-+	    BIG_SUR_GE_READ(emac->base_address + XIIF_V123B_IISR_OFFSET);
-+	if (int_status & BIG_SUR_GE_EIR_XMIT_LFIFO_FULL_MASK) {
-+		printk(KERN_ERR "Tx FIFO error: Queue is Full \n");
-+		return -1;
-+	}
-+
-+	/*
-+	 * Write the data to the FIFO in the hardware
-+	 */
-+	if ((BIG_SUR_GE_GET_COUNT(&emac->send_fifo) *
-+	     sizeof(unsigned long)) < byte_cnt) {
-+		printk(KERN_ERR "Send FIFO on chip is full \n");
-+		return -1;
-+	}
-+
-+	if (big_sur_ge_dma_status(&emac->send_channel) &
-+	    BIG_SUR_GE_DMASR_BUSY_MASK) {
-+		printk(KERN_ERR "Send channel FIFO engine busy \n");
-+		return -1;
-+	}
-+
-+	big_sur_ge_set_dma_control(&emac->send_channel,
-+				   BIG_SUR_GE_DMACR_SOURCE_INCR_MASK |
-+				   BIG_SUR_GE_DMACR_DEST_LOCAL_MASK |
-+				   BIG_SUR_GE_DMACR_SG_DISABLE_MASK);
-+
-+	big_sur_ge_dma_transfer(&emac->send_channel,
-+				(unsigned long *) buffer,
-+				(unsigned long *) (emac->base_address +
-+						   BIG_SUR_GE_PFIFO_TXDATA_OFFSET),
-+				byte_cnt);
-+
-+	reg_data = big_sur_ge_dma_status(&emac->send_channel);
-+	while (reg_data & BIG_SUR_GE_DMASR_BUSY_MASK) {
-+		reg_data = big_sur_ge_dma_status(&emac->recv_channel);
-+		if (!(reg_data & BIG_SUR_GE_DMASR_BUSY_MASK))
-+			break;
-+	}
-+
-+	if ((reg_data & BIG_SUR_GE_DMASR_BUS_ERROR_MASK) ||
-+	    (reg_data & BIG_SUR_GE_DMASR_BUS_TIMEOUT_MASK)) {
-+		printk(KERN_ERR "Send side DMA error \n");
-+		return -1;
-+	}
-+
-+	BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_TPLR_OFFSET,
-+			 byte_cnt);
-+
-+	return 0;
-+}
-+
-+/*************************************************************************
-+ * FIFO receive for Simple DMA case
-+ *************************************************************************/
-+static int big_sur_ge_enet_fifo_recv(big_sur_ge * emac, u8 * buffer,
-+			      unsigned long *byte_cnt)
-+{
-+	unsigned long int_status, reg_data;
-+
-+	/* Silly checks here that we really dont need */
-+	if (!emac->started)
-+		return -1;
-+
-+	if (emac->polled)
-+		return -1;
-+
-+	if (emac->dma_sg)
-+		return -1;
-+
-+	if (*byte_cnt < BIG_SUR_GE_MAX_FRAME_SIZE)
-+		return -1;
-+
-+	int_status =
-+	    BIG_SUR_GE_READ(emac->base_address + XIIF_V123B_IISR_OFFSET);
-+	if (int_status & BIG_SUR_GE_EIR_RECV_LFIFO_EMPTY_MASK) {
-+		BIG_SUR_GE_WRITE(emac->base_address +
-+				 XIIF_V123B_IISR_OFFSET,
-+				 BIG_SUR_GE_EIR_RECV_LFIFO_EMPTY_MASK);
-+		return -1;
-+	}
-+
-+	if (big_sur_ge_dma_status(&emac->recv_channel) &
-+	    BIG_SUR_GE_DMASR_BUSY_MASK) {
-+		printk(KERN_ERR "Rx side DMA Engine busy \n");
-+		return -1;
-+	}
-+
-+	if (BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_RPLR_OFFSET) ==
-+	    0) {
-+		printk(KERN_ERR "MAC has the FIFO packet length 0 \n");
-+		return -1;
-+	}
-+
-+	/* For the simple DMA case only */
-+	big_sur_ge_set_dma_control(&emac->recv_channel,
-+				   BIG_SUR_GE_DMACR_DEST_INCR_MASK |
-+				   BIG_SUR_GE_DMACR_SOURCE_LOCAL_MASK |
-+				   BIG_SUR_GE_DMACR_SG_DISABLE_MASK);
-+
-+	if (packet_fifo_read(&emac->recv_fifo, buffer,
-+			     BIG_SUR_GE_READ(emac->base_address +
-+					     BIG_SUR_GE_RPLR_OFFSET)) ==
-+	    -1) {
-+		printk(KERN_ERR "Not enough space in the FIFO \n");
-+		return -1;
-+	}
-+
-+	big_sur_ge_dma_transfer(&emac->recv_channel,
-+				(unsigned long *) (emac->base_address +
-+						   BIG_SUR_GE_PFIFO_RXDATA_OFFSET),
-+				(unsigned long *)
-+				buffer,
-+				BIG_SUR_GE_READ(emac->base_address +
-+						BIG_SUR_GE_RPLR_OFFSET));
-+
-+	reg_data = big_sur_ge_dma_status(&emac->recv_channel);
-+	while (reg_data & BIG_SUR_GE_DMASR_BUSY_MASK) {
-+		reg_data = big_sur_ge_dma_status(&emac->recv_channel);
-+		if (!(reg_data & BIG_SUR_GE_DMASR_BUSY_MASK))
-+			break;
-+	}
-+
-+	if ((reg_data & BIG_SUR_GE_DMASR_BUS_ERROR_MASK) ||
-+	    (reg_data & BIG_SUR_GE_DMASR_BUS_TIMEOUT_MASK)) {
-+		printk(KERN_ERR "DMA Bus Error \n");
-+		return -1;
-+	}
-+
-+	*byte_cnt =
-+	    BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_RPLR_OFFSET);
-+
-+	return 0;
-+}
-+
-+static irqreturn_t big_sur_ge_int_handler(int irq, void *dev_id,
-+				   struct pt_regs *regs)
-+{
-+	struct net_device *netdev = dev_id;
-+	struct big_sur_ge_enet *lp = netdev->priv;
-+	big_sur_ge *emac = (big_sur_ge *)emac_ptr;
-+	void *emac_ptr = &lp->emac;
-+	unsigned long int_status;
-+
-+	int_status =
-+	    BIG_SUR_GE_READ(emac->base_address + XIIF_V123B_DIPR_OFFSET);
-+	if (int_status & BIG_SUR_GE_IPIF_EMAC_MASK)
-+		handle_fifo_intr(emac);
-+
-+	if (int_status & BIG_SUR_GE_IPIF_RECV_FIFO_MASK)
-+		big_sur_ge_check_fifo_recv_error(emac);
-+
-+	if (int_status & BIG_SUR_GE_IPIF_SEND_FIFO_MASK)
-+		big_sur_ge_check_fifo_send_error(emac);
-+
-+	if (int_status & XIIF_V123B_ERROR_MASK)
-+		BIG_SUR_GE_WRITE(emac->base_address +
-+				 XIIF_V123B_DISR_OFFSET,
-+				 XIIF_V123B_ERROR_MASK);
-+
-+	return IRQ_HANDLED;
-+}
-+
-+/****************************************************************************
-+ * Set the FIFO send handler
-+ ***************************************************************************/
-+static void big_sur_ge_set_fifo_send_handler(big_sur_ge * emac, void *call_back,
-+				      big_sur_fifo_handler function)
-+{
-+	emac->big_sur_ge_fifo_send_handler = function;
-+	emac->fifo_send_ref = call_back;
-+}
-+
-+/****************************************************************************
-+ * Set the FIFO recv handler
-+ ***************************************************************************/
-+static void big_sur_ge_set_fifo_recv_handler(big_sur_ge * emac, void *call_back,
-+				      big_sur_fifo_handler function)
-+{
-+	emac->big_sur_ge_fifo_recv_handler = function;
-+	emac->fifo_recv_ref = call_back;
-+}
-+
-+/****************************************************************************
-+ * Main Fifo intr handler
-+ ***************************************************************************/
-+static void handle_fifo_intr(big_sur_ge * emac)
-+{
-+	unsigned long int_status;
-+
-+	/* Ack the interrupts asap */
-+	int_status =
-+	    BIG_SUR_GE_READ(emac->base_address + XIIF_V123B_IISR_OFFSET);
-+	BIG_SUR_GE_WRITE(emac->base_address + XIIF_V123B_IISR_OFFSET,
-+			 int_status);
-+
-+	/* Process the Rx side */
-+	if (int_status & BIG_SUR_GE_EIR_RECV_DONE_MASK) {
-+		emac->big_sur_ge_fifo_recv_handler(&emac->fifo_recv_ref);
-+		BIG_SUR_GE_WRITE(emac->base_address +
-+				 XIIF_V123B_IISR_OFFSET,
-+				 BIG_SUR_GE_EIR_RECV_DONE_MASK);
-+	}
-+
-+	if (int_status & BIG_SUR_GE_EIR_XMIT_DONE_MASK) {
-+		/* We dont collect stats and hence we dont need to get status */
-+
-+		emac->big_sur_ge_fifo_send_handler(emac->fifo_recv_ref);
-+		BIG_SUR_GE_WRITE(emac->base_address +
-+				 XIIF_V123B_IISR_OFFSET,
-+				 BIG_SUR_GE_EIR_XMIT_DONE_MASK);
-+	}
-+
-+	big_sur_ge_check_mac_error(emac, int_status);
-+}
-+
-+/******************************************************************
-+ * Handle the Receive side DMA interrupts. The PPC driver has
-+ * callbacks all over the place. This has been eliminated here by
-+ * using the following approach:
-+ *
-+ * The ISR is set to the main interrrupt handler. This will handle
-+ * all the interrupts including the ones for DMA. In this main isr,
-+ * we determine if we need to call recv or send side intr functions.
-+ * Pretty complex but thats the way it is now.
-+ *******************************************************************/
-+static void big_sur_ge_handle_recv_intr(big_sur_ge * emac)
-+{
-+	unsigned long int_status;
-+
-+	int_status = big_sur_ge_get_intr_status(&emac->recv_channel);
-+	if (int_status & (BIG_SUR_GE_IXR_PKT_THRESHOLD_MASK |
-+			  BIG_SUR_GE_IXR_PKT_WAIT_BOUND_MASK)) {
-+		u32 num_packets;
-+		u32 num_processed;
-+		u32 num_buffers;
-+		u32 num_bytes;
-+		xbuf_descriptor *first_desc_ptr = NULL;
-+		xbuf_descriptor *buffer_desc;
-+		int is_last = 0;
-+
-+		/* The number of packets we need to process on the Rx */
-+		num_packets =
-+		    big_sur_ge_get_packet_count(&emac->recv_channel);
-+
-+		for (num_processed = 0; num_processed < num_packets;
-+		     num_processed++) {
-+			while (!is_last) {
-+				if (big_sur_ge_get_descriptor
-+				    (&emac->recv_channel,
-+				     &buffer_desc) == -1)
-+					break;
-+
-+				if (first_desc_ptr == NULL)
-+					first_desc_ptr = buffer_desc;
-+
-+				num_bytes +=
-+				    xbuf_descriptor_GetLength(buffer_desc);
-+
-+				if (xbuf_descriptor_IsLastStatus
-+				    (buffer_desc)) {
-+					is_last = 1;
-+				}
-+
-+				num_buffers++;
-+			}
-+
-+			/* Number of buffers is always 1 since we dont do SG */
-+
-+			/*
-+			 * Only for SG DMA which is currently not supported. In the
-+			 * future, as we have SG channel working, we will code this
-+			 * receive side routine. For now, do nothing. This is never
-+			 * called from FIFO mode - Manish
-+			 */
-+			big_sur_ge_decr_packet_count(&emac->recv_channel);
-+		}
-+	}
-+
-+	/* Ack the interrupts */
-+	big_sur_ge_set_intr_status(&emac->recv_channel, int_status);
-+
-+	if (int_status & BIG_SUR_GE_IXR_DMA_ERROR_MASK) {
-+		/* We need a reset here */
-+	}
-+
-+	big_sur_ge_set_intr_status(&emac->recv_channel, int_status);
-+}
-+
-+/****************************************************************
-+ * Handle the send side DMA interrupt
-+ ****************************************************************/
-+static void big_sur_ge_handle_send_intr(big_sur_ge * emac)
-+{
-+	unsigned long int_status;
-+
-+	int_status = big_sur_ge_get_intr_status(&emac->send_channel);
-+
-+	if (int_status & (BIG_SUR_GE_IXR_PKT_THRESHOLD_MASK |
-+			  BIG_SUR_GE_IXR_PKT_WAIT_BOUND_MASK)) {
-+		unsigned long num_frames = 0;
-+		unsigned long num_processed = 0;
-+		unsigned long num_buffers = 0;
-+		unsigned long num_bytes = 0;
-+		unsigned long is_last = 0;
-+		xbuf_descriptor *first_desc_ptr = NULL;
-+		xbuf_descriptor *buffer_desc;
-+
-+		num_frames =
-+		    big_sur_ge_get_packet_count(&emac->send_channel);
-+
-+		for (num_processed = 0; num_processed < num_frames;
-+		     num_processed++) {
-+			while (!is_last) {
-+				if (big_sur_ge_get_descriptor
-+				    (&emac->send_channel, &buffer_desc)
-+				    == -1) {
-+					break;
-+				}
-+
-+				if (first_desc_ptr == NULL)
-+					first_desc_ptr = buffer_desc;
-+
-+				num_bytes +=
-+				    xbuf_descriptor_GetLength(buffer_desc);
-+				if (xbuf_descriptor_IsLastControl
-+				    (buffer_desc))
-+					is_last = 1;
-+
-+				num_buffers++;
-+			}
-+
-+			/*
-+			 * Only for SG DMA which is currently not supported. In the
-+			 * future, as we have SG channel working, we will code this
-+			 * receive side routine. For now, do nothing. This is never
-+			 * called from FIFO mode - Manish
-+			 */
-+			big_sur_ge_decr_packet_count(&emac->send_channel);
-+		}
-+	}
-+
-+	/* Ack the interrupts and reset DMA channel if necessary */
-+	big_sur_ge_set_intr_status(&emac->send_channel, int_status);
-+	if (int_status & BIG_SUR_GE_IXR_DMA_ERROR_MASK) {
-+		/* Manish : need reset */
-+	}
-+
-+	big_sur_ge_set_intr_status(&emac->send_channel, int_status);
-+}
-+
-+/*****************************************************************
-+ * For now, the MAC address errors dont trigger a update of the
-+ * stats. There is no stats framework in place. Hence, we just
-+ * check for the errors below and do a reset if needed.
-+ *****************************************************************/
-+static void big_sur_ge_check_mac_error(big_sur_ge * emac,
-+				unsigned long int_status)
-+{
-+	if (int_status & (BIG_SUR_GE_EIR_RECV_DFIFO_OVER_MASK |
-+			  BIG_SUR_GE_EIR_RECV_LFIFO_OVER_MASK |
-+			  BIG_SUR_GE_EIR_RECV_LFIFO_UNDER_MASK |
-+			  BIG_SUR_GE_EIR_RECV_ERROR_MASK |
-+			  BIG_SUR_GE_EIR_RECV_MISSED_FRAME_MASK |
-+			  BIG_SUR_GE_EIR_RECV_COLLISION_MASK |
-+			  BIG_SUR_GE_EIR_RECV_FCS_ERROR_MASK |
-+			  BIG_SUR_GE_EIR_RECV_LEN_ERROR_MASK |
-+			  BIG_SUR_GE_EIR_RECV_SHORT_ERROR_MASK |
-+			  BIG_SUR_GE_EIR_RECV_LONG_ERROR_MASK |
-+			  BIG_SUR_GE_EIR_RECV_ALIGN_ERROR_MASK |
-+			  BIG_SUR_GE_EIR_XMIT_SFIFO_OVER_MASK |
-+			  BIG_SUR_GE_EIR_XMIT_LFIFO_OVER_MASK |
-+			  BIG_SUR_GE_EIR_XMIT_SFIFO_UNDER_MASK |
-+			  BIG_SUR_GE_EIR_XMIT_LFIFO_UNDER_MASK)) {
-+
-+		BIG_SUR_GE_WRITE(emac->base_address +
-+				 XIIF_V123B_IIER_OFFSET, 0);
-+		/*
-+		 * Manish Reset the MAC here
-+		 */
-+	}
-+}
-+
-+/*****************************************************************
-+ * Check for FIFO Recv errors
-+ *****************************************************************/
-+static void big_sur_ge_check_fifo_recv_error(big_sur_ge * emac)
-+{
-+	if (BIG_SUR_GE_IS_DEADLOCKED(&emac->recv_fifo)) {
-+		unsigned long intr_enable;
-+
-+		intr_enable =
-+		    BIG_SUR_GE_READ(emac->base_address +
-+				    XIIF_V123B_DIER_OFFSET);
-+		BIG_SUR_GE_WRITE(emac->base_address +
-+				 XIIF_V123B_DIER_OFFSET,
-+				 intr_enable &
-+				 ~(BIG_SUR_GE_IPIF_RECV_FIFO_MASK));
-+
-+	}
-+}
-+
-+/*****************************************************************
-+ * Check for FIFO Send errors
-+ *****************************************************************/
-+static void big_sur_ge_check_fifo_send_error(big_sur_ge * emac)
-+{
-+	if (BIG_SUR_GE_IS_DEADLOCKED(&emac->send_fifo)) {
-+		unsigned long intr_enable;
-+
-+		intr_enable =
-+		    BIG_SUR_GE_READ(emac->base_address +
-+				    XIIF_V123B_DIER_OFFSET);
-+		BIG_SUR_GE_WRITE(emac->base_address +
-+				 XIIF_V123B_DIER_OFFSET,
-+				 intr_enable &
-+				 ~(BIG_SUR_GE_IPIF_SEND_FIFO_MASK));
-+	}
-+}
-+
-+/*****************************************************************
-+ * GE unit init
-+ ****************************************************************/
-+static int big_sur_ge_enet_init(big_sur_ge * emac, unsigned int device_id)
-+{
-+	unsigned long reg_data;
-+	big_sur_ge_config *config;
-+	int err;
-+
-+	/* Assume that the device has been stopped */
-+
-+	config = big_sur_ge_lookup_config(device_id);
-+	if (config == NULL)
-+		return -1;
-+
-+	emac->ready = 0;
-+	emac->started = 0;
-+	emac->dma_sg = 0;	/* This MAC has no support for Scatter Gather DMA */
-+	emac->has_mii = config->has_mii;
-+	emac->has_mcast_hash_table = 0;
-+	emac->dma_config = config->dma_config;
-+
-+	/*
-+	 * Initialize the FIFO send and recv handlers to the stub handlers.
-+	 * We only deal with the FIFO mode of operation since SG is not supported.
-+	 * Also, there is no error handler. We try to handle as much of error as
-+	 * possible and then return. No error codes also.
-+	 */
-+
-+	emac->base_address = config->base_address;
-+
-+	if (big_sur_ge_config_dma(emac) == -1)
-+		return -1;
-+
-+	err = big_sur_ge_config_fifo(emac);
-+	if (err == -1)
-+		return err;
-+
-+	/* Now, we know that the FIFO initialized successfully. So, set the ready flag */
-+	emac->ready = 1;
-+
-+	/* Do we need a PHY reset here also. It did cause problems on some boards */
-+	big_sur_ge_enet_reset(emac);
-+
-+	/* PHY reset code. Remove if causes a problem on the board */
-+	reg_data =
-+	    BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_ECR_OFFSET);
-+	reg_data &= ~(BIG_SUR_GE_ECR_PHY_ENABLE_MASK);
-+	BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_ECR_OFFSET,
-+			 reg_data);
-+	reg_data |= BIG_SUR_GE_ECR_PHY_ENABLE_MASK;
-+	BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_ECR_OFFSET,
-+			 reg_data);
-+
-+	return 0;
-+}
-+
-+/*******************************************************************
-+ * Start the GE unit for Tx, Rx and Interrupts
-+ *******************************************************************/
-+static int big_sur_ge_start(big_sur_ge * emac)
-+{
-+	unsigned long reg_data;
-+
-+	/*
-+	 * Basic mode of operation is polled and interrupt mode. We disable the polled
-+	 * mode for good. We may use the polled mode for Rx NAPI but that does not
-+	 * require all the interrupts to be disabled
-+	 */
-+
-+	emac->polled = 0;
-+
-+	/*
-+	 * DMA: Three modes of operation - simple, FIFO, SG. SG is surely not working
-+	 * and so is kept off using the dma_sg flag. Simple and FIFO work. But, we may
-+	 * not use FIFO at all. So, we enable the interrupts below
-+	 */
-+
-+	BIG_SUR_GE_WRITE(emac->base_address + XIIF_V123B_DIER_OFFSET,
-+			 BIG_SUR_GE_IPIF_FIFO_DFT_MASK |
-+			 XIIF_V123B_ERROR_MASK);
-+
-+	BIG_SUR_GE_WRITE(emac->base_address + XIIF_V123B_IIER_OFFSET,
-+			 BIG_SUR_GE_EIR_DFT_FIFO_MASK);
-+
-+	/* Toggle the started flag */
-+	emac->started = 1;
-+
-+	/* Start the Tx and Rx units respectively */
-+	reg_data =
-+	    BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_ECR_OFFSET);
-+	reg_data &=
-+	    ~(BIG_SUR_GE_ECR_XMIT_RESET_MASK |
-+	      BIG_SUR_GE_ECR_RECV_RESET_MASK);
-+	reg_data |=
-+	    (BIG_SUR_GE_ECR_XMIT_ENABLE_MASK |
-+	     BIG_SUR_GE_ECR_RECV_ENABLE_MASK);
-+
-+	BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_ECR_OFFSET,
-+			 reg_data);
-+
-+	return 0;
-+}
-+
-+/**************************************************************************
-+ * Stop the GE unit
-+ **************************************************************************/
-+static int big_sur_ge_stop(big_sur_ge * emac)
-+{
-+	unsigned long reg_data;
-+
-+	/* We assume that the device is not already stopped */
-+	if (!emac->started)
-+		return 0;
-+
-+	/* Disable the Tx and Rx unit respectively */
-+	reg_data =
-+	    BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_ECR_OFFSET);
-+	reg_data &=
-+	    ~(BIG_SUR_GE_ECR_XMIT_ENABLE_MASK |
-+	      BIG_SUR_GE_ECR_RECV_ENABLE_MASK);
-+	BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_ECR_OFFSET,
-+			 reg_data);
-+
-+	/* Disable the interrupts */
-+	BIG_SUR_GE_WRITE(emac->base_address + XIIF_V123B_DGIER_OFFSET, 0);
-+
-+	/* Toggle the started flag */
-+	emac->started = 0;
-+
-+	return 0;
-+}
-+
-+/************************************************************************
-+ * Reset the GE MAC unit
-+ *************************************************************************/
-+static void big_sur_ge_enet_reset(big_sur_ge * emac)
-+{
-+	unsigned long reg_data;
-+
-+	(void) big_sur_ge_stop(emac);
-+
-+	BIG_SUR_GE_WRITE(emac->base_address + XIIF_V123B_RESETR_OFFSET,
-+			 XIIF_V123B_RESET_MASK);
-+
-+	/*
-+	 * For now, configure the receiver to not strip off FCS and padding since
-+	 * this is not currently supported. In the future, just take the default
-+	 * and provide the option for the user to change this behavior.
-+	 */
-+	reg_data =
-+	    BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_ECR_OFFSET);
-+	reg_data &=
-+	    ~(BIG_SUR_GE_ECR_RECV_PAD_ENABLE_MASK |
-+	      BIG_SUR_GE_ECR_RECV_FCS_ENABLE_MASK);
-+	reg_data &= ~(BIG_SUR_GE_ECR_RECV_STRIP_ENABLE_MASK);
-+	BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_ECR_OFFSET,
-+			 reg_data);
-+}
-+
-+/*************************************************************************
-+ * Set the MAC address of the GE mac unit
-+ *************************************************************************/
-+static int big_sur_ge_set_mac_address(big_sur_ge * emac, unsigned char *addr)
-+{
-+	unsigned long mac_addr = 0;
-+
-+	/* Device is started and so mac address must be set */
-+	if (emac->started == 1)
-+		return 0;
-+
-+	mac_addr = ((addr[0] << 8) | addr[1]);
-+	BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_SAH_OFFSET,
-+			 mac_addr);
-+
-+	mac_addr |= ((addr[2] << 24) | (addr[3] << 16) |
-+		     (addr[4] << 8) | addr[5]);
-+
-+	BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_SAL_OFFSET,
-+			 mac_addr);
-+
-+	return 0;
-+}
-+
-+/****************************************************************************
-+ * Get the MAC address of the GE MAC unit
-+ ***************************************************************************/
-+static void big_sur_ge_get_mac_unit(big_sur_ge * emac, unsigned int *addr)
-+{
-+	unsigned long mac_addr_hi, mac_addr_lo;
-+
-+	mac_addr_hi =
-+	    BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_SAH_OFFSET);
-+	mac_addr_lo =
-+	    BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_SAL_OFFSET);
-+
-+	addr[0] = (mac_addr_hi >> 8);
-+	addr[1] = mac_addr_hi;
-+
-+	addr[2] = (mac_addr_lo >> 24);
-+	addr[3] = (mac_addr_lo >> 16);
-+	addr[4] = (mac_addr_lo >> 8);
-+	addr[5] = mac_addr_lo;
-+}
-+
-+/*********************************************************************************
-+ * Configure the GE MAC for DMA capabilities. Not for Scatter Gather, only Simple
-+ *********************************************************************************/
-+static int big_sur_ge_config_dma(big_sur_ge * emac)
-+{
-+	if (big_sur_ge_dma_init(&emac->recv_channel, emac->base_address +
-+				BIG_SUR_GE_DMA_RECV_OFFSET) == -1) {
-+		printk(KERN_ERR "Could not initialize the DMA unit  \n");
-+		return -1;
-+	}
-+
-+	if (big_sur_ge_dma_init(&emac->send_channel, emac->base_address +
-+				BIG_SUR_GE_DMA_SEND_OFFSET) == -1) {
-+		printk(KERN_ERR "Could not initialize the DMA unit  \n");
-+		return -1;
-+	}
-+
-+	return 0;
-+}
-+
-+/******************************************************************************
-+ * Configure the FIFO for simple DMA
-+ ******************************************************************************/
-+static int big_sur_ge_config_fifo(big_sur_ge * emac)
-+{
-+	int err = 0;
-+
-+	err = packet_fifo_init(&emac->recv_fifo, emac->base_address +
-+			       BIG_SUR_GE_PFIFO_RXREG_OFFSET,
-+			       emac->base_address +
-+			       BIG_SUR_GE_PFIFO_RXDATA_OFFSET);
-+
-+	if (err == -1) {
-+		printk(KERN_ERR
-+		       "Could not initialize Rx packet FIFO for Simple DMA \n");
-+		return err;
-+	}
-+
-+	err = packet_fifo_init(&emac->send_fifo, emac->base_address +
-+			       BIG_SUR_GE_PFIFO_TXREG_OFFSET,
-+			       emac->base_address +
-+			       BIG_SUR_GE_PFIFO_TXDATA_OFFSET);
-+
-+	if (err == -1) {
-+		printk(KERN_ERR
-+		       "Could not initialize Tx packet FIFO for Simple DMA \n");
-+	}
-+
-+	return err;
-+}
-+
-+#define BIG_SUR_GE_NUM_INSTANCES	2
-+
-+
-+/**********************************************************************************
-+ * Look up the config of the MAC
-+ **********************************************************************************/
-+static big_sur_ge_config *big_sur_ge_lookup_config(unsigned int device_id)
-+{
-+	big_sur_ge_config *config = NULL;
-+	int i = 0;
-+
-+	for (i = 0; i < BIG_SUR_GE_NUM_INSTANCES; i++) {
-+		/* Manish : Init the config here */
-+		break;
-+	}
-+
-+	return config;
-+}
-+
-+typedef struct {
-+	unsigned long option;
-+	unsigned long mask;
-+} option_map;
-+
-+static option_map option_table[] = {
-+	{BIG_SUR_GE_UNICAST_OPTION, BIG_SUR_GE_ECR_UNICAST_ENABLE_MASK},
-+	{BIG_SUR_GE_BROADCAST_OPTION, BIG_SUR_GE_ECR_BROAD_ENABLE_MASK},
-+	{BIG_SUR_GE_PROMISC_OPTION, BIG_SUR_GE_ECR_PROMISC_ENABLE_MASK},
-+	{BIG_SUR_GE_FDUPLEX_OPTION, BIG_SUR_GE_ECR_FULL_DUPLEX_MASK},
-+	{BIG_SUR_GE_LOOPBACK_OPTION, BIG_SUR_GE_ECR_LOOPBACK_MASK},
-+	{BIG_SUR_GE_MULTICAST_OPTION, BIG_SUR_GE_ECR_MULTI_ENABLE_MASK},
-+	{BIG_SUR_GE_FLOW_CONTROL_OPTION, BIG_SUR_GE_ECR_PAUSE_FRAME_MASK},
-+	{BIG_SUR_GE_INSERT_PAD_OPTION,
-+	 BIG_SUR_GE_ECR_XMIT_PAD_ENABLE_MASK},
-+	{BIG_SUR_GE_INSERT_FCS_OPTION,
-+	 BIG_SUR_GE_ECR_XMIT_FCS_ENABLE_MASK},
-+	{BIG_SUR_GE_INSERT_ADDR_OPTION,
-+	 BIG_SUR_GE_ECR_XMIT_ADDR_INSERT_MASK},
-+	{BIG_SUR_GE_OVWRT_ADDR_OPTION,
-+	 BIG_SUR_GE_ECR_XMIT_ADDR_OVWRT_MASK},
-+	{BIG_SUR_GE_STRIP_PAD_OPTION, BIG_SUR_GE_ECR_RECV_PAD_ENABLE_MASK},
-+	{BIG_SUR_GE_STRIP_FCS_OPTION, BIG_SUR_GE_ECR_RECV_FCS_ENABLE_MASK},
-+	{BIG_SUR_GE_STRIP_PAD_FCS_OPTION,
-+	 BIG_SUR_GE_ECR_RECV_STRIP_ENABLE_MASK}
-+};
-+
-+#define BIG_SUR_GE_NUM_OPTIONS		(sizeof(option_table) / sizeof(option_map))
-+
-+/**********************************************************************
-+ * Set the options for the GE
-+ **********************************************************************/
-+static int big_sur_ge_set_options(big_sur_ge * emac, unsigned long option_flag)
-+{
-+	unsigned long reg_data;
-+	unsigned int index;
-+
-+	/* Assume that the device is stopped before calling this function */
-+
-+	reg_data =
-+	    BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_ECR_OFFSET);
-+	for (index = 0; index < BIG_SUR_GE_NUM_OPTIONS; index++) {
-+		if (option_flag & option_table[index].option)
-+			reg_data |= option_table[index].mask;
-+		else
-+			reg_data &= ~(option_table[index].mask);
-+
-+	}
-+
-+	BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_ECR_OFFSET,
-+			 reg_data);
-+
-+	/* No polled option */
-+	emac->polled = 0;
-+
-+	return 0;
-+}
-+
-+/*******************************************************
-+ * Get the options from the GE
-+ *******************************************************/
-+static unsigned long big_sur_ge_get_options(big_sur_ge * emac)
-+{
-+	unsigned long option_flag = 0, reg_data;
-+	unsigned int index;
-+
-+	reg_data =
-+	    BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_ECR_OFFSET);
-+
-+	for (index = 0; index < BIG_SUR_GE_NUM_OPTIONS; index++) {
-+		if (option_flag & option_table[index].option)
-+			reg_data |= option_table[index].mask;
-+	}
-+
-+	/* No polled mode */
-+
-+	return option_flag;
-+}
-+
-+/********************************************************
-+ * Set the Inter frame gap
-+ ********************************************************/
-+static int big_sur_ge_set_frame_gap(big_sur_ge * emac, int part1, int part2)
-+{
-+	unsigned long config;
-+
-+	/* Assume that the device is stopped before calling this */
-+
-+	config = ((part1 << BIG_SUR_GE_IFGP_PART1_SHIFT) |
-+		  (part2 << BIG_SUR_GE_IFGP_PART2_SHIFT));
-+
-+	BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_IFGP_OFFSET,
-+			 config);
-+
-+	return 0;
-+}
-+
-+/********************************************************
-+ * Get the Inter frame gap
-+ ********************************************************/
-+static void big_sur_ge_get_frame_gap(big_sur_ge * emac, int *part1, int *part2)
-+{
-+	unsigned long config;
-+
-+	config =
-+	    BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_IFGP_OFFSET);
-+	*part1 =
-+	    ((config & BIG_SUR_GE_IFGP_PART1_SHIFT) >>
-+	     BIG_SUR_GE_IFGP_PART1_SHIFT);
-+	*part2 =
-+	    ((config & BIG_SUR_GE_IFGP_PART2_SHIFT) >>
-+	     BIG_SUR_GE_IFGP_PART2_SHIFT);
-+}
-+
-+/*******************************************************************
-+ * PHY specific functions for the MAC
-+ *******************************************************************/
-+#define BIG_SUR_GE_MAX_PHY_ADDR		32
-+#define BIG_SUR_GE_MAX_PHY_REG		32
-+
-+/*******************************************************************
-+ * Read the PHY reg
-+ *******************************************************************/
-+static int big_sur_ge_phy_read(big_sur_ge * emac, unsigned long addr,
-+			unsigned long reg_num, unsigned int *data)
-+{
-+	unsigned long mii_control, mii_data;
-+
-+	if (!emac->has_mii)
-+		return -1;
-+
-+	mii_control =
-+	    BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_MGTCR_OFFSET);
-+	if (mii_control & BIG_SUR_GE_MGTCR_START_MASK) {
-+		printk(KERN_ERR "PHY busy \n");
-+		return -1;
-+	}
-+
-+	mii_control = (addr << BIG_SUR_GE_MGTCR_PHY_ADDR_SHIFT);
-+	mii_control |= (reg_num << BIG_SUR_GE_MGTCR_REG_ADDR_SHIFT);
-+	mii_control |=
-+	    (BIG_SUR_GE_MGTCR_RW_NOT_MASK | BIG_SUR_GE_MGTCR_START_MASK |
-+	     BIG_SUR_GE_MGTCR_MII_ENABLE_MASK);
-+
-+	BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_MGTCR_OFFSET,
-+			 mii_control);
-+
-+	while (mii_control & BIG_SUR_GE_MGTCR_START_MASK)
-+		if (!(mii_control & BIG_SUR_GE_MGTCR_START_MASK))
-+			break;
-+
-+	mii_data =
-+	    BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_MGTDR_OFFSET);
-+	*data = (unsigned int) mii_data;
-+
-+	return 0;
-+}
-+
-+/**********************************************************************
-+ * Write to the PHY register
-+ **********************************************************************/
-+static int big_sur_ge_phy_write(big_sur_ge * emac, unsigned long addr,
-+			 unsigned long reg_num, unsigned int data)
-+{
-+	unsigned long mii_control;
-+
-+	if (!emac->has_mii)
-+		return -1;
-+
-+	mii_control =
-+	    BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_MGTCR_OFFSET);
-+	if (mii_control & BIG_SUR_GE_MGTCR_START_MASK) {
-+		printk(KERN_ERR "PHY busy \n");
-+		return -1;
-+	}
-+
-+	BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_MGTDR_OFFSET,
-+			 (unsigned long) data);
-+
-+	mii_control = (addr << BIG_SUR_GE_MGTCR_PHY_ADDR_SHIFT);
-+	mii_control |= (reg_num << BIG_SUR_GE_MGTCR_REG_ADDR_SHIFT);
-+	mii_control |=
-+	    (BIG_SUR_GE_MGTCR_START_MASK |
-+	     BIG_SUR_GE_MGTCR_MII_ENABLE_MASK);
-+
-+	BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_MGTCR_OFFSET,
-+			 mii_control);
-+
-+	while (mii_control & BIG_SUR_GE_MGTCR_START_MASK)
-+		if (!(mii_control & BIG_SUR_GE_MGTCR_START_MASK))
-+			break;
-+
-+	return 0;
-+}
-+
-+
-+
-+
-+
-+
-+/********************************************************************
-+ * The hardware dependent part of the driver begins here
-+ ********************************************************************/
-+
-+
-+/*******************************************************************
-+ * Reset the GE system
-+ *******************************************************************/
-+static void big_sur_ge_reset(struct net_device *netdev, DUPLEX duplex)
-+{
-+	struct big_sur_ge_enet *lp = netdev->priv;
-+	struct sk_buff *skb;
-+	unsigned long options;
-+	int ifcfg1, ifcfg2;
-+
-+	/* Stop the queue */
-+	netif_stop_queue(netdev);
-+
-+	big_sur_ge_get_frame_gap(&lp->emac, &ifcfg1, &ifcfg2);
-+	options = big_sur_ge_get_options(&lp->emac);
-+	switch (duplex) {
-+	case HALF_DUPLEX:
-+		options &= ~(BIG_SUR_GE_FDUPLEX_OPTION);
-+		break;
-+
-+	case FULL_DUPLEX:
-+		options |= BIG_SUR_GE_FDUPLEX_OPTION;
-+		break;
-+
-+	case UNKNOWN:
-+		break;
-+	}
-+
-+	/* There is no support for SG DMA in a 100 Mpbs NIC */
-+
-+	big_sur_ge_enet_reset(&lp->emac);
-+
-+	/* Set the necessary options for the MAC unit */
-+	big_sur_ge_set_mac_address(&lp->emac, netdev->dev_addr);
-+	big_sur_ge_set_frame_gap(&lp->emac, ifcfg1, ifcfg2);
-+	big_sur_ge_set_options(&lp->emac, options);
-+
-+	(void) big_sur_ge_start(&lp->emac);
-+
-+	spin_lock_irq(&lp->lock);
-+	skb = lp->saved_skb;
-+	lp->saved_skb = NULL;
-+	spin_unlock_irq(&lp->lock);
-+
-+	if (skb)
-+		dev_kfree_skb(skb);
-+
-+	/* Wake the queue */
-+	netif_wake_queue(netdev);
-+}
-+
-+/********************************************************************
-+ * Get the PHY status
-+ *******************************************************************/
-+static int big_sur_ge_get_phy_status(struct net_device *netdev,
-+				     DUPLEX * duplex, int *linkup)
-+{
-+	struct big_sur_ge_enet *lp = netdev->priv;
-+	unsigned int reg_data;
-+	int err = 0;
-+
-+	err =
-+	    big_sur_ge_phy_read(&lp->emac, lp->mii_addr, MII_BMCR,
-+				&reg_data);
-+	if (err == -1) {
-+		printk(KERN_ERR "%s: Could not read PHY control register",
-+		       netdev->name);
-+		return err;
-+	}
-+
-+	if (!(reg_data & BMCR_ANENABLE)) {
-+		if (reg_data & BMCR_FULLDPLX)
-+			*duplex = FULL_DUPLEX;
-+		else
-+			*duplex = HALF_DUPLEX;
-+	} else {
-+		unsigned int advertise, partner, neg;
-+
-+		err =
-+		    big_sur_ge_phy_read(&lp->emac, lp->mii_addr,
-+					MII_ADVERTISE, &advertise);
-+		if (err == -1) {
-+			printk(KERN_ERR
-+			       "%s: Could not read PHY control register",
-+			       netdev->name);
-+			return err;
-+		}
-+
-+		err =
-+		    big_sur_ge_phy_read(&lp->emac, lp->mii_addr, MII_LPA,
-+					&partner);
-+		if (err == -1) {
-+			printk(KERN_ERR
-+			       "%s: Could not read PHY control register",
-+			       netdev->name);
-+			return err;
-+		}
-+
-+		neg = advertise & partner & ADVERTISE_ALL;
-+		if (neg & ADVERTISE_100FULL)
-+			*duplex = FULL_DUPLEX;
-+		else if (neg & ADVERTISE_100HALF)
-+			*duplex = HALF_DUPLEX;
-+		else if (neg & ADVERTISE_10FULL)
-+			*duplex = FULL_DUPLEX;
-+		else
-+			*duplex = HALF_DUPLEX;
-+
-+		err =
-+		    big_sur_ge_phy_read(&lp->emac, lp->mii_addr, MII_BMSR,
-+					&reg_data);
-+		if (err == -1) {
-+			printk(KERN_ERR
-+			       "%s: Could not read PHY control register",
-+			       netdev->name);
-+			return err;
-+		}
-+
-+		*linkup = (reg_data & BMSR_LSTATUS) != 0;
-+
-+	}
-+	return 0;
-+}
-+
-+/************************************************************
-+ * Poll the MII for duplex and link status
-+ ***********************************************************/
-+static void big_sur_ge_poll_mii(unsigned long data)
-+{
-+	struct net_device *netdev = (struct net_device *) data;
-+	struct big_sur_ge_enet *lp = netdev->priv;
-+	unsigned long options;
-+	DUPLEX mac_duplex, phy_duplex;
-+	int phy_carrier, netif_carrier;
-+
-+	if (big_sur_ge_get_phy_status(netdev, &phy_duplex, &phy_carrier) ==
-+	    -1) {
-+		printk(KERN_ERR "%s: Terminating link monitoring.\n",
-+		       netdev->name);
-+		return;
-+	}
-+
-+	options = big_sur_ge_get_options(&lp->emac);
-+	if (options & BIG_SUR_GE_FDUPLEX_OPTION)
-+		mac_duplex = FULL_DUPLEX;
-+	else
-+		mac_duplex = HALF_DUPLEX;
-+
-+	if (mac_duplex != phy_duplex) {
-+		disable_irq(netdev->irq);
-+		big_sur_ge_reset(netdev, phy_duplex);
-+		enable_irq(netdev->irq);
-+	}
-+
-+	netif_carrier = netif_carrier_ok(netdev) != 0;
-+
-+	if (phy_carrier != netif_carrier) {
-+		if (phy_carrier) {
-+			printk(KERN_INFO "%s: Link carrier restored.\n",
-+			       netdev->name);
-+			netif_carrier_on(netdev);
-+		} else {
-+			printk(KERN_INFO "%s: Link carrier lost.\n",
-+			       netdev->name);
-+			netif_carrier_off(netdev);
-+		}
-+	}
-+
-+	/* Set up the timer so we'll get called again in 2 seconds. */
-+	lp->phy_timer.expires = jiffies + 2 * HZ;
-+	add_timer(&lp->phy_timer);
-+}
-+
-+/**************************************************************
-+ * Open the network interface
-+ *************************************************************/
-+static int big_sur_ge_open(struct net_device *netdev)
-+{
-+	struct big_sur_ge_enet *lp = netdev->priv;
-+	unsigned long options;
-+	DUPLEX phy_duplex, mac_duplex;
-+	int phy_carrier, retval;
-+
-+	(void) big_sur_ge_stop(&lp->emac);
-+
-+	if (big_sur_ge_set_mac_address(&lp->emac, netdev->dev_addr) == -1) {
-+		printk(KERN_ERR "%s: Could not set MAC address.\n",
-+		       netdev->name);
-+		return -EIO;
-+	}
-+
-+	options = big_sur_ge_get_options(&lp->emac);
-+
-+	retval =
-+	    request_irq(netdev->irq, &big_sur_ge_int_handler, 0,
-+			netdev->name, netdev);
-+	if (retval) {
-+		printk(KERN_ERR
-+		       "%s: Could not allocate interrupt %d.\n",
-+		       netdev->name, netdev->irq);
-+
-+		return retval;
-+	}
-+
-+	if (!
-+	    (big_sur_ge_get_phy_status(netdev, &phy_duplex, &phy_carrier)))
-+	{
-+		if (options & BIG_SUR_GE_FDUPLEX_OPTION)
-+			mac_duplex = FULL_DUPLEX;
-+		else
-+			mac_duplex = HALF_DUPLEX;
-+
-+		if (mac_duplex != phy_duplex) {
-+			switch (phy_duplex) {
-+			case HALF_DUPLEX:
-+				options &= ~(BIG_SUR_GE_FDUPLEX_OPTION);
-+				break;
-+			case FULL_DUPLEX:
-+				options |= BIG_SUR_GE_FDUPLEX_OPTION;
-+				break;
-+			case UNKNOWN:
-+				break;
-+			}
-+
-+			big_sur_ge_set_options(&lp->emac, options);
-+		}
-+	}
-+
-+	if (big_sur_ge_start(&lp->emac) == -1) {
-+		printk(KERN_ERR "%s: Could not start device.\n",
-+		       netdev->name);
-+		free_irq(netdev->irq, netdev);
-+		return -EBUSY;
-+	}
-+
-+	netif_start_queue(netdev);
-+
-+	lp->phy_timer.expires = jiffies + 2 * HZ;
-+	lp->phy_timer.data = (unsigned long) netdev;
-+	lp->phy_timer.function = &big_sur_ge_poll_mii;
-+	add_timer(&lp->phy_timer);
-+
-+	return 0;
-+}
-+
-+/*********************************************************************
-+ * Close the network device interface
-+ *********************************************************************/
-+static int big_sur_ge_close(struct net_device *netdev)
-+{
-+	struct big_sur_ge_enet *lp = netdev->priv;
-+
-+	del_timer_sync(&lp->phy_timer);
-+	netif_stop_queue(netdev);
-+
-+	free_irq(netdev->irq, netdev);
-+
-+	if (big_sur_ge_stop(&lp->emac) == -1) {
-+		printk(KERN_ERR "%s: Could not stop device.\n",
-+		       netdev->name);
-+		return -EBUSY;
-+	}
-+
-+	return 0;
-+}
-+
-+/*********************************************************************
-+ * Get the network device stats. For now, do nothing
-+ *********************************************************************/
-+static struct net_device_stats *big_sur_ge_get_stats(struct net_device
-+						     *netdev)
-+{
-+	/* Do nothing */
-+	return (struct net_device_stats *) 0;
-+}
-+
-+/********************************************************************
-+ * FIFO send for a packet that needs to be transmitted
-+ ********************************************************************/
-+static int big_sur_ge_fifo_send(struct sk_buff *orig_skb,
-+				struct net_device *netdev)
-+{
-+	struct big_sur_ge_enet *lp = netdev->priv;
-+	struct sk_buff *new_skb;
-+	unsigned int len, align;
-+
-+	netif_stop_queue(netdev);
-+	len = orig_skb->len;
-+
-+	if (!(new_skb = dev_alloc_skb(len + 4))) {
-+		dev_kfree_skb(orig_skb);
-+		printk(KERN_ERR
-+		       "%s: Could not allocate transmit buffer.\n",
-+		       netdev->name);
-+		netif_wake_queue(netdev);
-+		return -EBUSY;
-+	}
-+
-+	align = 4 - ((unsigned long) new_skb->data & 3);
-+	if (align != 4)
-+		skb_reserve(new_skb, align);
-+
-+	skb_put(new_skb, len);
-+	memcpy(new_skb->data, orig_skb->data, len);
-+
-+	dev_kfree_skb(orig_skb);
-+
-+	lp->saved_skb = new_skb;
-+	if (big_sur_ge_enet_fifo_send(&lp->emac, (u8 *) new_skb->data, len)
-+	    == -1) {
-+		spin_lock_irq(&lp->lock);
-+		new_skb = lp->saved_skb;
-+		lp->saved_skb = NULL;
-+		spin_unlock_irq(&lp->lock);
-+
-+		dev_kfree_skb(new_skb);
-+		printk(KERN_ERR "%s: Could not transmit buffer.\n",
-+		       netdev->name);
-+		netif_wake_queue(netdev);
-+		return -EIO;
-+	}
-+	return 0;
-+}
-+
-+/**********************************************************************
-+ * Call the fifo send handler
-+ **********************************************************************/
-+static void big_sur_ge_fifo_send_handler(void *callback)
-+{
-+	struct net_device *netdev = (struct net_device *) callback;
-+	struct big_sur_ge_enet *lp = netdev->priv;
-+	struct sk_buff *skb;
-+
-+	spin_lock_irq(&lp->lock);
-+	skb = lp->saved_skb;
-+	lp->saved_skb = NULL;
-+	spin_unlock_irq(&lp->lock);
-+
-+	if (skb)
-+		dev_kfree_skb(skb);
-+
-+	netif_wake_queue(netdev);
-+}
-+
-+/**********************************************************************
-+ * Handle the timeout of the ethernet device
-+ **********************************************************************/
-+static void big_sur_ge_tx_timeout(struct net_device *netdev)
-+{
-+	printk
-+	    ("%s: Exceeded transmit timeout of %lu ms.	Resetting mac.\n",
-+	     netdev->name, TX_TIMEOUT * 1000UL / HZ);
-+
-+	disable_irq(netdev->irq);
-+	big_sur_ge_reset(netdev, UNKNOWN);
-+	enable_irq(netdev->irq);
-+}
-+
-+/*********************************************************************
-+ * When in FIFO mode, the callback function for packets received
-+ *********************************************************************/
-+static void big_sur_ge_fifo_recv_handler(void *callback)
-+{
-+	struct net_device *netdev = (struct net_device *) callback;
-+	struct big_sur_ge_enet *lp = netdev->priv;
-+	struct sk_buff *skb;
-+	unsigned long len = BIG_SUR_GE_MAX_FRAME_SIZE;
-+	unsigned int align;
-+
-+	if (!(skb = dev_alloc_skb(len + 4))) {
-+		printk(KERN_ERR "%s: Could not allocate receive buffer.\n",
-+		       netdev->name);
-+		return;
-+	}
-+
-+	align = 4 - ((unsigned long) skb->data & 3);
-+	if (align != 4)
-+		skb_reserve(skb, align);
-+
-+	if (big_sur_ge_enet_fifo_recv(&lp->emac, (u8 *) skb->data, &len) ==
-+	    -1) {
-+		dev_kfree_skb(skb);
-+
-+		printk(KERN_ERR "%s: Could not receive buffer \n",
-+		       netdev->name);
-+		netdev->tx_timeout = NULL;
-+		big_sur_ge_reset(netdev, UNKNOWN);
-+		netdev->tx_timeout = big_sur_ge_tx_timeout;
-+	}
-+
-+	skb_put(skb, len);	/* Tell the skb how much data we got. */
-+	skb->dev = netdev;	/* Fill out required meta-data. */
-+	skb->protocol = eth_type_trans(skb, netdev);
-+
-+	netif_rx(skb);		/* Send the packet upstream. */
-+}
-+
-+/*********************************************************************
-+ * Set the Multicast Hash list
-+ *********************************************************************/
-+static void big_sur_ge_set_multicast_hash_list(struct net_device *netdev)
-+{
-+	struct big_sur_ge_enet *lp = netdev->priv;
-+	unsigned long options;
-+
-+	disable_irq(netdev->irq);
-+	local_bh_disable();
-+
-+	(void) big_sur_ge_stop(&lp->emac);
-+	options = big_sur_ge_get_options(&lp->emac);
-+	options &=
-+	    ~(BIG_SUR_GE_PROMISC_OPTION | BIG_SUR_GE_MULTICAST_OPTION);
-+
-+	/* Do nothing for now */
-+
-+	(void) big_sur_ge_start(&lp->emac);
-+	local_bh_enable();
-+	enable_irq(netdev->irq);
-+}
-+
-+/***********************************************************************
-+ * IOCTL support
-+ ***********************************************************************/
-+static int big_sur_ge_ioctl(struct net_device *netdev, struct ifreq *rq,
-+			    int cmd)
-+{
-+	struct big_sur_ge_enet *lp = netdev->priv;
-+	struct mii_ioctl_data *data =
-+	    (struct mii_ioctl_data *) &rq->ifr_data;
-+
-+	switch (cmd) {
-+	case SIOCGMIIPHY:	/* Get address of MII PHY in use. */
-+	case SIOCDEVPRIVATE:	/* for binary compat, remove in 2.5 */
-+		data->phy_id = lp->mii_addr;
-+
-+	case SIOCGMIIREG:	/* Read MII PHY register. */
-+	case SIOCDEVPRIVATE + 1:	/* for binary compat, remove in 2.5 */
-+		if (data->phy_id > 31 || data->reg_num > 31)
-+			return -ENXIO;
-+
-+		del_timer_sync(&lp->phy_timer);
-+
-+		if (big_sur_ge_phy_read(&lp->emac, data->phy_id,
-+					data->reg_num,
-+					&data->val_out) == -1) {
-+			printk(KERN_ERR "%s: Could not read from PHY",
-+			       netdev->name);
-+			return -EBUSY;
-+		}
-+
-+		lp->phy_timer.expires = jiffies + 2 * HZ;
-+		add_timer(&lp->phy_timer);
-+
-+		return 0;
-+
-+	case SIOCSMIIREG:	/* Write MII PHY register. */
-+	case SIOCDEVPRIVATE + 2:	/* for binary compat, remove in 2.5 */
-+		if (data->phy_id > 31 || data->reg_num > 31)
-+			return -ENXIO;
-+
-+		del_timer_sync(&lp->phy_timer);
-+
-+		if (big_sur_ge_phy_write
-+		    (&lp->emac, data->phy_id, data->reg_num,
-+		     data->val_in) == -1) {
-+			printk(KERN_ERR "%s: Could not write to PHY",
-+			       netdev->name);
-+			return -EBUSY;
-+		}
-+
-+		lp->phy_timer.expires = jiffies + 2 * HZ;
-+		add_timer(&lp->phy_timer);
-+
-+		return 0;
-+
-+	default:
-+		return -EOPNOTSUPP;
-+	}
-+}
-+
-+/*****************************************************************
-+ * Get the config from the config table
-+ *****************************************************************/
-+static big_sur_ge_config *big_sur_ge_get_config(int index)
-+{
-+	/* Manish */
-+	return (big_sur_ge_config *) 0;
-+}
-+
-+/*****************************************************************
-+ * Release the network device structure
-+ *****************************************************************/
-+static void big_sur_ge_remove_head(void)
-+{
-+	struct net_device *netdev;
-+	struct big_sur_ge_enet *lp;
-+	big_sur_ge_config *config;
-+
-+	spin_lock(&dev_lock);
-+	netdev = dev_list;
-+	lp = netdev->priv;
-+
-+	spin_unlock(&dev_lock);
-+
-+	config = big_sur_ge_get_config(lp->index);
-+	iounmap((void *) config->base_address);
-+	config->base_address = lp->save_base_address;
-+
-+	if (lp->saved_skb)
-+		dev_kfree_skb(lp->saved_skb);
-+	kfree(lp);
-+
-+	unregister_netdev(netdev);
-+	kfree(netdev);
-+}
-+
-+/*****************************************************************
-+ * Initial Function to probe the network interface
-+ *****************************************************************/
-+static int __init big_sur_ge_probe(int index)
-+{
-+	static const unsigned long remap_size =
-+	    BIG_SUR_GE_EMAC_0_HIGHADDR - BIG_SUR_GE_EMAC_0_BASEADDR + 1;
-+	struct net_device *netdev;
-+	struct big_sur_ge_enet *lp;
-+	big_sur_ge_config *config;
-+	unsigned int irq;
-+	unsigned long maddr;
-+	goto err;
-+
-+	switch (index) {
-+	case 0:
-+		irq = (31 - BIG_SUR_GE_INTC_0_EMAC_0_VEC_ID);
-+		break;
-+	case 1:
-+		irq = (31 - BIG_SUR_GE_INTC_1_EMAC_1_VEC_ID);
-+		break;
-+	case 2:
-+		irq = (31 - BIG_SUR_GE_INTC_2_EMAC_2_VEC_ID);
-+		break;
-+	default:
-+		err = -ENODEV;
-+		goto out;
-+	}
-+
-+	config = big_sur_ge_get_config(index);
-+	if (!config) {
-+		err = -ENODEV;
-+		goto out;
-+	}
-+
-+	netdev = alloc_etherdev(sizeof(big_sur_ge_config));
-+
-+	if (!netdev) {
-+		err = -ENOMEM;
-+		goto out;
-+	}
-+
-+	SET_MODULE_OWNER(netdev);
-+
-+	netdev->irq = irq;
-+
-+	lp = (struct big_sur_ge_enet *) netdev->priv;
-+	memset(lp, 0, sizeof(struct big_sur_ge_enet));
-+	spin_lock_init(&lp->lock);
-+	spin_lock(&dev_lock);
-+	lp->next_dev = dev_list;
-+	dev_list = netdev;
-+	spin_unlock(&dev_lock);
-+
-+	lp->save_base_address = config->base_address;
-+	config->base_address =
-+	    (unsigned long) ioremap(lp->save_base_address, remap_size);
-+	if (!config->base_address) {
-+		err = -ENOMEM;
-+		goto out_unlock;
-+	}
-+
-+	if (big_sur_ge_enet_init(&lp->emac, config->device_id) == -1) {
-+		printk(KERN_ERR "%s: Could not initialize device.\n",
-+		       netdev->name);
-+		err = -ENODEV;
-+		goto out_unmap;
-+	}
-+
-+	/* Manish: dev_addr value */
-+	memcpy(netdev->dev_addr, big_sur_mac_addr_base, 6);
-+	if (big_sur_ge_set_mac_address(&lp->emac, netdev->dev_addr) == -1) {
-+		printk(KERN_ERR "%s: Could not set MAC address.\n",
-+		       netdev->name);
-+		err = -EIO;
-+		goto out_unmap;
-+	}
-+
-+	/*
-+	 * There is no Scatter Gather support but there is a Simple DMA support
-+	 */
-+	big_sur_ge_set_fifo_recv_handler(&lp->emac, netdev,
-+					 big_sur_ge_fifo_recv_handler);
-+	big_sur_ge_set_fifo_send_handler(&lp->emac, netdev,
-+					 big_sur_ge_fifo_send_handler);
-+	netdev->hard_start_xmit = big_sur_ge_fifo_send;
-+
-+	lp->mii_addr = 0xFF;
-+
-+	for (maddr = 0; maddr < 31; maddr++) {
-+		unsigned int reg_data;
-+
-+		if (big_sur_ge_phy_read
-+		    (&lp->emac, maddr, MII_BMCR, &reg_data) == 0) {
-+			lp->mii_addr = maddr;
-+			break;
-+		}
-+	}
-+
-+	if (lp->mii_addr == 0xFF) {
-+		lp->mii_addr = 0;
-+		printk(KERN_WARNING
-+		       "%s: No PHY detected.  Assuming a PHY at address %d.\n",
-+		       netdev->name, lp->mii_addr);
-+	}
-+
-+	netdev->open = big_sur_ge_open;
-+	netdev->stop = big_sur_ge_close;
-+	netdev->get_stats = big_sur_ge_get_stats;	/* Does nothing */
-+	netdev->do_ioctl = big_sur_ge_ioctl;
-+	netdev->tx_timeout = big_sur_ge_tx_timeout;
-+	netdev->watchdog_timeo = TX_TIMEOUT;
-+
-+	err = register_netdev(netdev))
-+	if (!err)
-+		goto out_unmap;
-+
-+	printk(KERN_INFO "%s: PMC-Sierra Big Sur Ethernet Device %d  at 0x%08X "
-+	       "mapped to 0x%08X, irq=%d\n", netdev->name, index,
-+	       lp->save_base_address, config->base_address, netdev->irq);
-+
-+	return ret;
-+
-+out_unmap:
-+	iounmap(config->base_address);
-+
-+out_unlock:
-+	big_sur_ge_remove_head();
-+
-+out:
-+	return ret;
-+}
-+
-+static int __init big_sur_ge_init(void)
-+{
-+	int index = 0;
-+
-+	while (big_sur_ge_probe(index++) == 0);
-+
-+	return (index > 1) ? 0 : -ENODEV;
-+}
-+
-+static void __exit big_sur_ge_cleanup(void)
-+{
-+	while (dev_list)
-+		big_sur_ge_remove_head();
-+}
-+
-+module_init(big_sur_ge_init);
-+module_exit(big_sur_ge_cleanup);
-+
-+MODULE_AUTHOR("Manish Lachwani <lachwani@pmc-sierra.com>");
-+MODULE_DESCRIPTION("PMC-Sierra Big Sur Ethernet MAC Driver");
-+MODULE_LICENSE("GPL");
-diff -Naur linux-2.6.17.orig/drivers/net/big_sur_ge.h linux-2.6.17/drivers/net/big_sur_ge.h
---- linux-2.6.17.orig/drivers/net/big_sur_ge.h	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/drivers/net/big_sur_ge.h	2006-06-19 18:16:13.000000000 -0700
-@@ -0,0 +1,713 @@
-+/*
-+ * drivers/net/big_sur_ge.h - Driver for PMC-Sierra Big Sur
-+ * ethernet ports
-+ *
-+ * Copyright (C) 2003 PMC-Sierra Inc.
-+ * Author : Manish Lachwani (lachwani@pmc-sierra.com)
-+ * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * as published by the Free Software Foundation; either version 2
-+ * of the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
-+ *
-+ */
-+
-+#ifndef	__BIG_SUR_GE_H__
-+#define	__BIG_SUR_GE_H__
-+
-+#include <linux/version.h>
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/spinlock.h>
-+#include <linux/types.h>
-+
-+#define	BIG_SUR_DEVICE_NAME	"big sur"
-+#define	BIG_SUR_DEVICE_DESC	"Big Sur Ethernet 10/100 MAC"
-+
-+#define BIG_SUR_GE_BASE			0xbb000000
-+
-+#define	BIG_SUR_GE_WRITE(ofs,data)	*(volatile u32 *)(BIG_SUR_GE_BASE+(ofs)) = data
-+
-+#define	BIG_SUR_GE_READ(ofs)		*(volatile u32 *)(BIG_SUR_GE_BASE+(ofs))
-+
-+/* Manish : Need to fix these defines later */
-+#define	BIG_SUR_GE_EMAC_0_HIGHADDR
-+#define	BIG_SUR_GE_EMAC_0_BASEADDR
-+#define	BIG_SUR_GE_INTC_0_EMAC_0_VEC_ID		1
-+#define	BIG_SUR_GE_INTC_1_EMAC_1_VEC_ID		2
-+#define	BIG_SUR_GE_INTC_2_EMAC_2_VEC_ID		3
-+#define	BIG_SUR_GE_EMAC_0_ERR_COUNT_EXIST
-+#define	BIG_SUR_GE_EMAC_0_DMA_PRESENT
-+#define	BIG_SUR_GE_EMAC_0_MII_EXIST
-+#define	BIG_SUR_GE_OPB_ETHERNET_0_BASEADDR
-+#define	BIG_SUR_GE_EMAC_0_DEVICE_ID
-+#define	BIG_SUR_GE_OPB_ETHERNET_0_ERR_COUNT_EXIST
-+#define	BIG_SUR_GE_OPB_ETHERNET_0_DMA_PRESENT
-+#define	BIG_SUR_GE_OPB_ETHERNET_0_MII_EXIST
-+#define	BIG_SUR_GE_OPB_ETHERNET_0_DEVICE_ID
-+
-+#define	BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT	4UL
-+/* IPIF specific defines */
-+#define XIIF_V123B_DISR_OFFSET     0UL  /* device interrupt status register */
-+#define XIIF_V123B_DIPR_OFFSET     4UL  /* device interrupt pending register */
-+#define XIIF_V123B_DIER_OFFSET     8UL  /* device interrupt enable register */
-+#define XIIF_V123B_DIIR_OFFSET     24UL /* device interrupt ID register */
-+#define XIIF_V123B_DGIER_OFFSET    28UL /* device global interrupt enable reg */
-+#define XIIF_V123B_IISR_OFFSET     32UL /* IP interrupt status register */
-+#define XIIF_V123B_IIER_OFFSET     40UL /* IP interrupt enable register */
-+#define XIIF_V123B_RESETR_OFFSET   64UL /* reset register */
-+#define XIIF_V123B_RESET_MASK             0xAUL
-+#define	XIIF_V123B_ERROR_MASK		0x1UL
-+
-+/* defines */
-+#define BIG_SUR_GE_UNICAST_OPTION        	0x00000001
-+#define BIG_SUR_GE_BROADCAST_OPTION      	0x00000002
-+#define BIG_SUR_GE_PROMISC_OPTION        	0x00000004
-+#define BIG_SUR_GE_FDUPLEX_OPTION        	0x00000008
-+#define BIG_SUR_GE_POLLED_OPTION         	0x00000010
-+#define BIG_SUR_GE_LOOPBACK_OPTION       	0x00000020
-+#define BIG_SUR_GE_FLOW_CONTROL_OPTION   	0x00000080
-+#define BIG_SUR_GE_INSERT_PAD_OPTION     	0x00000100
-+#define BIG_SUR_GE_INSERT_FCS_OPTION     	0x00000200
-+#define BIG_SUR_GE_INSERT_ADDR_OPTION    	0x00000400
-+#define BIG_SUR_GE_OVWRT_ADDR_OPTION     	0x00000800
-+#define BIG_SUR_GE_STRIP_PAD_FCS_OPTION  	0x00002000
-+
-+/* Not Supported */
-+#define BIG_SUR_GE_MULTICAST_OPTION      	0x00000040
-+#define BIG_SUR_GE_FLOW_CONTROL_OPTION   	0x00000080
-+#define BIG_SUR_GE_INSERT_PAD_OPTION     	0x00000100
-+#define BIG_SUR_GE_INSERT_FCS_OPTION     	0x00000200
-+#define BIG_SUR_GE_INSERT_ADDR_OPTION    	0x00000400
-+#define BIG_SUR_GE_OVWRT_ADDR_OPTION     	0x00000800
-+#define BIG_SUR_GE_STRIP_PAD_OPTION      	0x00001000
-+#define BIG_SUR_GE_STRIP_FCS_OPTION     	0x00002000
-+
-+
-+/* Defaults for Interrupt Coalescing in the SG DMA Engine */
-+#define BIG_SUR_GE_SGDMA_DFT_THRESHOLD     1   /* Default pkt threshold */
-+#define BIG_SUR_GE_SGDMA_MAX_THRESHOLD     255 /* Maximum pkt theshold */
-+#define BIG_SUR_GE_SGDMA_DFT_WAITBOUND     5   /* Default pkt wait bound (msec) */
-+#define BIG_SUR_GE_SGDMA_MAX_WAITBOUND     1023        /* Maximum pkt wait bound (msec) */
-+
-+/* Direction */
-+#define BIG_SUR_GE_SEND    1
-+#define BIG_SUR_GE_RECV    2
-+
-+/* SG DMA */
-+#define BIG_SUR_GE_SGDMA_NODELAY     0 /* start SG DMA immediately */
-+#define BIG_SUR_GE_SGDMA_DELAY       1 /* do not start SG DMA */
-+
-+#define BIG_SUR_GE_CFG_NO_IPIF             0   /* Not supported by the driver */
-+#define BIG_SUR_GE_CFG_NO_DMA              1   /* No DMA */
-+#define BIG_SUR_GE_CFG_SIMPLE_DMA          2   /* Simple DMA */
-+#define BIG_SUR_GE_CFG_DMA_SG              3   /* DMA scatter gather */
-+
-+#define BIG_SUR_GE_MAC_ADDR_SIZE   6   /* six-byte MAC address */
-+#define BIG_SUR_GE_MTU             1500        /* max size of Ethernet frame */
-+#define BIG_SUR_GE_HDR_SIZE        14  /* size of Ethernet header */
-+#define BIG_SUR_GE_HDR_VLAN_SIZE   18  /* size of Ethernet header with VLAN */
-+#define BIG_SUR_GE_TRL_SIZE        4   /* size of Ethernet trailer (FCS) */
-+#define BIG_SUR_GE_MAX_FRAME_SIZE  \
-+		(BIG_SUR_GE_MTU + BIG_SUR_GE_HDR_SIZE + BIG_SUR_GE_TRL_SIZE)
-+
-+#define BIG_SUR_GE_MAX_VLAN_FRAME_SIZE  \
-+		(BIG_SUR_GE_MTU + BIG_SUR_GE_HDR_VLAN_SIZE + BIG_SUR_GE_TRL_SIZE)
-+
-+/* Send and Receive buffers */
-+#define BIG_SUR_GE_MIN_RECV_BUFS   32  /* minimum # of recv buffers */
-+#define BIG_SUR_GE_DFT_RECV_BUFS   64  /* default # of recv buffers */
-+
-+#define BIG_SUR_GE_MIN_SEND_BUFS   16  /* minimum # of send buffers */
-+#define BIG_SUR_GE_DFT_SEND_BUFS   32  /* default # of send buffers */
-+
-+#define BIG_SUR_GE_MIN_BUFFERS     (BIG_SUR_GE_MIN_RECV_BUFS + BIG_SUR_GE_MIN_SEND_BUFS)
-+#define BIG_SUR_GE_DFT_BUFFERS     (BIG_SUR_GE_DFT_RECV_BUFS + BIG_SUR_GE_DFT_SEND_BUFS)
-+
-+/* Send and Receive Descriptors */
-+#define BIG_SUR_GE_MIN_RECV_DESC   16  /* minimum # of recv descriptors */
-+#define BIG_SUR_GE_DFT_RECV_DESC   32  /* default # of recv descriptors */
-+
-+#define BIG_SUR_GE_MIN_SEND_DESC   8   /* minimum # of send descriptors */
-+#define BIG_SUR_GE_DFT_SEND_DESC   16  /* default # of send descriptors */
-+
-+/* FIFO Specific Defines */
-+#define BIG_SUR_GE_READ_FIFO_TYPE      0       /* a read FIFO */
-+#define BIG_SUR_GE_WRITE_FIFO_TYPE     1       /* a write FIFO */
-+#define BIG_SUR_GE_RESET_REG_OFFSET            0UL
-+#define BIG_SUR_GE_MODULE_INFO_REG_OFFSET      0UL
-+#define BIG_SUR_GE_COUNT_STATUS_REG_OFFSET     4UL
-+#define BIG_SUR_GE_RESET_FIFO_MASK             0x0000000A
-+#define BIG_SUR_GE_COUNT_MASK                  0x0000FFFF
-+#define BIG_SUR_GE_DEADLOCK_MASK               0x20000000
-+#define BIG_SUR_GE_ALMOST_EMPTY_FULL_MASK      0x40000000
-+#define BIG_SUR_GE_EMPTY_FULL_MASK             0x80000000
-+
-+#define BIG_SUR_GE_FIFO_RESET(fifo)	\
-+	BIG_SUR_GE_WRITE((fifo)->reg_base_addr + BIG_SUR_GE_RESET_REG_OFFSET, BIG_SUR_GE_RESET_FIFO_MASK)
-+
-+#define	BIG_SUR_GE_GET_COUNT(fifo)	\
-+	(BIG_SUR_GE_READ((fifo)->reg_base_addr + BIG_SUR_GE_COUNT_STATUS_REG_OFFSET) & 	\
-+							BIG_SUR_GE_COUNT_MASK)
-+
-+#define	BIG_SUR_GE_IS_ALMOST_EMPTY(fifo)	\
-+		(BIG_SUR_GE_READ(fifo->reg_base_addr + BIG_SUR_GE_COUNT_STATUS_REG_OFFSET) &	\
-+							BIG_SUR_GE_ALMOST_EMPTY_FULL_MASK)
-+
-+#define	BIG_SUR_GE_IS_ALMOST_FULL(fifo)  \
-+		(BIG_SUR_GE_READ(fifo->reg_base_addr + BIG_SUR_GE_COUNT_STATUS_REG_OFFSET) &   \
-+							BIG_SUR_GE_ALMOST_EMPTY_FULL_MASK)
-+
-+#define BIG_SUR_GE_IS_EMPTY(fifo)  \
-+		(BIG_SUR_GE_READ(fifo->reg_base_addr + BIG_SUR_GE_COUNT_STATUS_REG_OFFSET) &   \
-+							BIG_SUR_GE_EMPTY_FULL_MASK)
-+
-+#define BIG_SUR_GE_IS_FULL(fifo)  \
-+	(BIG_SUR_GE_READ(fifo->reg_base_addr + BIG_SUR_GE_COUNT_STATUS_REG_OFFSET) &   \
-+							BIG_SUR_GE_EMPTY_FULL_MASK)
-+
-+#define	BIG_SUR_GE_IS_DEADLOCKED(fifo)	\
-+	(BIG_SUR_GE_READ((fifo)->reg_base_addr + BIG_SUR_GE_COUNT_STATUS_REG_OFFSET) &   \
-+							BIG_SUR_GE_DEADLOCK_MASK)
-+
-+/* Device Config */
-+typedef struct _big_sur_ge_config {
-+	u16		device_id;
-+	u32		base_address;
-+	u32		has_counters;
-+	u32		has_sg_dma;
-+	u8		dma_config;
-+	u32		has_mii;
-+} big_sur_ge_config;
-+
-+#define BIG_SUR_GE_SIZE_IN_WORDS           10
-+typedef unsigned long xbuf_descriptor[BIG_SUR_GE_SIZE_IN_WORDS];
-+
-+/* Callback Functions */
-+typedef void (*big_sur_sg_handler) (void *callback, xbuf_descriptor *desc, u32 num_desc);
-+typedef	void (*big_sur_fifo_handler) (void *callback);
-+typedef void (*big_sur_irq_handler) (void *instance);
-+
-+typedef struct _xdma_channel_tag {
-+	u32			reg_base_address;
-+        u32                     base_address;
-+        u32                     ready;
-+        xbuf_descriptor         *put_ptr;
-+        xbuf_descriptor         *get_ptr;
-+        xbuf_descriptor         *commit_ptr;
-+        xbuf_descriptor         *last_ptr;
-+
-+        u32                     total_desc_count;
-+        u32                     active_desc_count;
-+} xdma_channel;
-+
-+typedef struct _packet_fifo {
-+        u32             reg_base_addr;
-+        u32             ready_status;
-+        u32             data_base_address;
-+} packet_fifo;
-+
-+
-+/* Big Sur GE driver structure */
-+typedef struct _big_sur_ge {
-+	u32		base_address;
-+	u32		started;
-+	u32		ready;
-+	u32		polled;
-+	u32		dma_sg;
-+
-+	u8		dma_config;
-+	u32		has_mii;
-+	u32		has_mcast_hash_table;
-+
-+	/* For the FIFO and simple DMA case only */
-+	packet_fifo	recv_fifo;
-+	packet_fifo	send_fifo;
-+
-+	big_sur_fifo_handler	big_sur_ge_fifo_recv_handler;
-+	big_sur_fifo_handler	big_sur_ge_fifo_send_handler;
-+
-+	void	*fifo_send_ref;
-+	void	*fifo_recv_ref;	
-+
-+	/* For SG DMA only */
-+	xdma_channel	recv_channel;
-+	xdma_channel	send_channel;
-+} big_sur_ge;
-+
-+/* Offset of the MAC registers from the IPIF base address */
-+#define BIG_SUR_GE_REG_OFFSET     0x1100UL
-+
-+/*
-+ * Register offsets for the Ethernet MAC. Each register is 32 bits.
-+ */
-+#define BIG_SUR_GE_EMIR_OFFSET   (BIG_SUR_GE_REG_OFFSET + 0x0)        /* EMAC Module ID */
-+#define BIG_SUR_GE_ECR_OFFSET    (BIG_SUR_GE_REG_OFFSET + 0x4)        /* MAC Control */
-+#define BIG_SUR_GE_IFGP_OFFSET   (BIG_SUR_GE_REG_OFFSET + 0x8)        /* Interframe Gap */
-+#define BIG_SUR_GE_SAH_OFFSET    (BIG_SUR_GE_REG_OFFSET + 0xC)        /* Station addr, high */
-+#define BIG_SUR_GE_SAL_OFFSET    (BIG_SUR_GE_REG_OFFSET + 0x10)       /* Station addr, low */
-+#define BIG_SUR_GE_MGTCR_OFFSET  (BIG_SUR_GE_REG_OFFSET + 0x14)       /* MII mgmt control */
-+#define BIG_SUR_GE_MGTDR_OFFSET  (BIG_SUR_GE_REG_OFFSET + 0x18)       /* MII mgmt data */
-+#define BIG_SUR_GE_RPLR_OFFSET   (BIG_SUR_GE_REG_OFFSET + 0x1C)       /* Rx packet length */
-+#define BIG_SUR_GE_TPLR_OFFSET   (BIG_SUR_GE_REG_OFFSET + 0x20)       /* Tx packet length */
-+#define BIG_SUR_GE_TSR_OFFSET    (BIG_SUR_GE_REG_OFFSET + 0x24)       /* Tx status */
-+#define BIG_SUR_GE_RMFC_OFFSET   (BIG_SUR_GE_REG_OFFSET + 0x28)       /* Rx missed frames */
-+#define BIG_SUR_GE_RCC_OFFSET    (BIG_SUR_GE_REG_OFFSET + 0x2C)       /* Rx collisions */
-+#define BIG_SUR_GE_RFCSEC_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x30)       /* Rx FCS errors */
-+#define BIG_SUR_GE_RAEC_OFFSET   (BIG_SUR_GE_REG_OFFSET + 0x34)       /* Rx alignment errors */
-+#define BIG_SUR_GE_TEDC_OFFSET   (BIG_SUR_GE_REG_OFFSET + 0x38)       /* Transmit excess
-+                                                         * deferral cnt */
-+/*
-+ * Register offsets for the IPIF components
-+ */
-+#define BIG_SUR_GE_ISR_OFFSET           0x20UL /* Interrupt status */
-+
-+#define BIG_SUR_GE_DMA_OFFSET           0x2300UL
-+#define BIG_SUR_GE_DMA_SEND_OFFSET      (BIG_SUR_GE_DMA_OFFSET + 0x0) /* DMA send channel */
-+#define BIG_SUR_GE_DMA_RECV_OFFSET      (BIG_SUR_GE_DMA_OFFSET + 0x40)        /* DMA recv channel */
-+
-+#define BIG_SUR_GE_PFIFO_OFFSET         0x2000UL
-+#define BIG_SUR_GE_PFIFO_TXREG_OFFSET   (BIG_SUR_GE_PFIFO_OFFSET + 0x0)       /* Tx registers */
-+#define BIG_SUR_GE_PFIFO_RXREG_OFFSET   (BIG_SUR_GE_PFIFO_OFFSET + 0x10)      /* Rx registers */
-+#define BIG_SUR_GE_PFIFO_TXDATA_OFFSET  (BIG_SUR_GE_PFIFO_OFFSET + 0x100)     /* Tx keyhole */
-+#define BIG_SUR_GE_PFIFO_RXDATA_OFFSET  (BIG_SUR_GE_PFIFO_OFFSET + 0x200)     /* Rx keyhole */
-+
-+/*
-+ * EMAC Module Identification Register (EMIR)
-+ */
-+#define BIG_SUR_GE_EMIR_VERSION_MASK    0xFFFF0000UL   /* Device version */
-+#define BIG_SUR_GE_EMIR_TYPE_MASK       0x0000FF00UL   /* Device type */
-+
-+/*
-+ * EMAC Control Register (ECR)
-+ */
-+#define BIG_SUR_GE_ECR_FULL_DUPLEX_MASK         0x80000000   /* Full duplex mode */
-+#define BIG_SUR_GE_ECR_XMIT_RESET_MASK          0x40000000   /* Reset transmitter */
-+#define BIG_SUR_GE_ECR_XMIT_ENABLE_MASK         0x20000000   /* Enable transmitter */
-+#define BIG_SUR_GE_ECR_RECV_RESET_MASK          0x10000000   /* Reset receiver */
-+#define BIG_SUR_GE_ECR_RECV_ENABLE_MASK         0x08000000   /* Enable receiver */
-+#define BIG_SUR_GE_ECR_PHY_ENABLE_MASK          0x04000000   /* Enable PHY */
-+#define BIG_SUR_GE_ECR_XMIT_PAD_ENABLE_MASK     0x02000000   /* Enable xmit pad insert */
-+#define BIG_SUR_GE_ECR_XMIT_FCS_ENABLE_MASK     0x01000000   /* Enable xmit FCS insert */
-+#define BIG_SUR_GE_ECR_XMIT_ADDR_INSERT_MASK    0x00800000   /* Enable xmit source addr insertion */
-+#define BIG_SUR_GE_ECR_XMIT_ERROR_INSERT_MASK   0x00400000   /* Insert xmit error */
-+#define BIG_SUR_GE_ECR_XMIT_ADDR_OVWRT_MASK     0x00200000   /* Enable xmit source addr overwrite */
-+#define BIG_SUR_GE_ECR_LOOPBACK_MASK            0x00100000   /* Enable internal loopback */
-+#define BIG_SUR_GE_ECR_RECV_PAD_ENABLE_MASK     0x00080000   /* Enable recv pad strip */
-+#define BIG_SUR_GE_ECR_RECV_FCS_ENABLE_MASK     0x00040000   /* Enable recv FCS strip */
-+#define BIG_SUR_GE_ECR_RECV_STRIP_ENABLE_MASK   0x00080000   /* Enable recv pad/fcs strip */
-+#define BIG_SUR_GE_ECR_UNICAST_ENABLE_MASK      0x00020000   /* Enable unicast addr */
-+#define BIG_SUR_GE_ECR_MULTI_ENABLE_MASK        0x00010000   /* Enable multicast addr */
-+#define BIG_SUR_GE_ECR_BROAD_ENABLE_MASK        0x00008000   /* Enable broadcast addr */
-+#define BIG_SUR_GE_ECR_PROMISC_ENABLE_MASK      0x00004000   /* Enable promiscuous mode */
-+#define BIG_SUR_GE_ECR_RECV_ALL_MASK            0x00002000   /* Receive all frames */
-+#define BIG_SUR_GE_ECR_RESERVED2_MASK           0x00001000   /* Reserved */
-+#define BIG_SUR_GE_ECR_MULTI_HASH_ENABLE_MASK   0x00000800   /* Enable multicast hash */
-+#define BIG_SUR_GE_ECR_PAUSE_FRAME_MASK         0x00000400   /* Interpret pause frames */
-+#define BIG_SUR_GE_ECR_CLEAR_HASH_MASK          0x00000200   /* Clear hash table */
-+#define BIG_SUR_GE_ECR_ADD_HASH_ADDR_MASK       0x00000100  /* Add hash table address */
-+
-+/*
-+ * Interframe Gap Register (IFGR)
-+ */
-+#define BIG_SUR_GE_IFGP_PART1_MASK         0xF8000000        /* Interframe Gap Part1 */
-+#define BIG_SUR_GE_IFGP_PART1_SHIFT        27
-+#define BIG_SUR_GE_IFGP_PART2_MASK         0x07C00000        /* Interframe Gap Part2 */
-+#define BIG_SUR_GE_IFGP_PART2_SHIFT        22
-+
-+/*
-+ * Station Address High Register (SAH)
-+ */
-+#define BIG_SUR_GE_SAH_ADDR_MASK           0x0000FFFF        /* Station address high bytes */
-+
-+/*
-+ * Station Address Low Register (SAL)
-+ */
-+#define BIG_SUR_GE_SAL_ADDR_MASK           0xFFFFFFFF        /* Station address low bytes */
-+
-+/*
-+ * MII Management Control Register (MGTCR)
-+ */
-+#define BIG_SUR_GE_MGTCR_START_MASK        0x80000000        /* Start/Busy */
-+#define BIG_SUR_GE_MGTCR_RW_NOT_MASK       0x40000000        /* Read/Write Not (direction) */
-+#define BIG_SUR_GE_MGTCR_PHY_ADDR_MASK     0x3E000000        /* PHY address */
-+#define BIG_SUR_GE_MGTCR_PHY_ADDR_SHIFT    25  /* PHY address shift */
-+#define BIG_SUR_GE_MGTCR_REG_ADDR_MASK     0x01F00000        /* Register address */
-+#define BIG_SUR_GE_MGTCR_REG_ADDR_SHIFT    20  /* Register addr shift */
-+#define BIG_SUR_GE_MGTCR_MII_ENABLE_MASK   0x00080000        /* Enable MII from EMAC */
-+#define BIG_SUR_GE_MGTCR_RD_ERROR_MASK     0x00040000        /* MII mgmt read error */
-+
-+/*
-+ * MII Management Data Register (MGTDR)
-+ */
-+#define BIG_SUR_GE_MGTDR_DATA_MASK         0x0000FFFF        /* MII data */
-+
-+/*
-+ * Receive Packet Length Register (RPLR)
-+ */
-+#define BIG_SUR_GE_RPLR_LENGTH_MASK        0x0000FFFF        /* Receive packet length */
-+
-+/*
-+ * Transmit Packet Length Register (TPLR)
-+ */
-+#define BIG_SUR_GE_TPLR_LENGTH_MASK        0x0000FFFF       /* Transmit packet length */
-+
-+/*
-+ * Transmit Status Register (TSR)
-+ */
-+#define BIG_SUR_GE_TSR_EXCESS_DEFERRAL_MASK 0x80000000       /* Transmit excess deferral */
-+#define BIG_SUR_GE_TSR_FIFO_UNDERRUN_MASK   0x40000000       /* Packet FIFO underrun */
-+#define BIG_SUR_GE_TSR_ATTEMPTS_MASK        0x3E000000      /* Transmission attempts */
-+#define BIG_SUR_GE_TSR_LATE_COLLISION_MASK  0x01000000      /* Transmit late collision */
-+
-+/*
-+ * Receive Missed Frame Count (RMFC)
-+ */
-+#define BIG_SUR_GE_RMFC_DATA_MASK          0x0000FFFF
-+
-+/*
-+ * Receive Collision Count (RCC)
-+ */
-+#define BIG_SUR_GE_RCC_DATA_MASK           0x0000FFFF
-+/*
-+ * Receive FCS Error Count (RFCSEC)
-+ */
-+#define BIG_SUR_GE_RFCSEC_DATA_MASK        0x0000FFFF
-+
-+/*
-+ * Receive Alignment Error Count (RALN)
-+ */
-+#define BIG_SUR_GE_RAEC_DATA_MASK          0x0000FFFF
-+
-+/*
-+ * Transmit Excess Deferral Count (TEDC)
-+ */
-+#define BIG_SUR_GE_TEDC_DATA_MASK          0x0000FFFF
-+
-+/*
-+ * EMAC Interrupt Registers (Status and Enable) masks. These registers are
-+ * part of the IPIF IP Interrupt registers
-+ */
-+#define BIG_SUR_GE_EIR_XMIT_DONE_MASK         0x00000001     /* Xmit complete */
-+#define BIG_SUR_GE_EIR_RECV_DONE_MASK         0x00000002     /* Recv complete */
-+#define BIG_SUR_GE_EIR_XMIT_ERROR_MASK        0x00000004     /* Xmit error */
-+#define BIG_SUR_GE_EIR_RECV_ERROR_MASK        0x00000008     /* Recv error */
-+#define BIG_SUR_GE_EIR_XMIT_SFIFO_EMPTY_MASK  0x00000010     /* Xmit status fifo empty */
-+#define BIG_SUR_GE_EIR_RECV_LFIFO_EMPTY_MASK  0x00000020     /* Recv length fifo empty */
-+#define BIG_SUR_GE_EIR_XMIT_LFIFO_FULL_MASK   0x00000040     /* Xmit length fifo full */
-+#define BIG_SUR_GE_EIR_RECV_LFIFO_OVER_MASK   0x00000080     /* Recv length fifo overrun */
-+#define BIG_SUR_GE_EIR_RECV_LFIFO_UNDER_MASK  0x00000100     /* Recv length fifo underrun */
-+#define BIG_SUR_GE_EIR_XMIT_SFIFO_OVER_MASK   0x00000200     /* Xmit status fifo overrun */
-+#define BIG_SUR_GE_EIR_XMIT_SFIFO_UNDER_MASK  0x00000400     /* Transmit status fifo underrun */
-+#define BIG_SUR_GE_EIR_XMIT_LFIFO_OVER_MASK   0x00000800     /* Transmit length fifo overrun */
-+#define BIG_SUR_GE_EIR_XMIT_LFIFO_UNDER_MASK  0x00001000     /* Transmit length fifo underrun */
-+#define BIG_SUR_GE_EIR_XMIT_PAUSE_MASK        0x00002000     /* Transmit pause pkt received */
-+#define BIG_SUR_GE_EIR_RECV_DFIFO_OVER_MASK   0x00004000     /* Receive data fifo overrun */
-+#define BIG_SUR_GE_EIR_RECV_MISSED_FRAME_MASK 0x00008000     /* Receive missed frame error */
-+#define BIG_SUR_GE_EIR_RECV_COLLISION_MASK    0x00010000     /* Receive collision error */
-+#define BIG_SUR_GE_EIR_RECV_FCS_ERROR_MASK    0x00020000     /* Receive FCS error */
-+#define BIG_SUR_GE_EIR_RECV_LEN_ERROR_MASK    0x00040000     /* Receive length field error */
-+#define BIG_SUR_GE_EIR_RECV_SHORT_ERROR_MASK  0x00080000     /* Receive short frame error */
-+#define BIG_SUR_GE_EIR_RECV_LONG_ERROR_MASK   0x00100000     /* Receive long frame error */
-+#define BIG_SUR_GE_EIR_RECV_ALIGN_ERROR_MASK  0x00200000     /* Receive alignment error */
-+
-+#define	BIG_SUR_GE_READ_REG(base_addr, reg_offset)	\
-+		BIG_SUR_GE_READ(base_addr + reg_offset)
-+
-+#define	BIG_SUR_GE_WRITE_REG(base_addr, reg_offset, data)	\
-+		 BIG_SUR_GE_WRITE(base_addr + reg_offset, data)
-+
-+#define BIG_SUR_GE_CONTROL_REG(base_addr, mask)		\
-+		BIG_SUR_GE_WRITE(base_addr + BIG_SUR_GE_ECR_OFFSET, mask)
-+
-+/* Set the MAC Address */
-+#define	big_sur_ge_set_mac(base_addr, address)					\
-+{										\
-+	u32	mac_addr;							\
-+										\
-+	mac_addr = ((address[0] << 8) | (address[1]);				\
-+	BIG_SUR_GE_WRITE(base_address + BIG_SUR_GE_SAH_OFFSET, mac_address);		\
-+										\
-+	mac_addr = ((address[2] << 24) | (address[3] << 16) |			\
-+			(address[4] << 8) | address[5]);			\
-+										\
-+	BIG_SUR_GE_WRITE(base_address + BIG_SUR_GE_SAL_OFFSET, mac_address);		\
-+										\
-+}										
-+
-+/* Enable the MAC unit */
-+#define	big_sur_ge_mac_enable(base_address)					\
-+{										\
-+	u32	control;							\
-+	control = BIG_SUR_GE_READ(base_address + BIG_SUR_GE_ECR_OFFSET);		\
-+	control &= ~(BIG_SUR_GE_ECR_XMIT_RESET_MASK | BIG_SUR_GE_ECR_RECV_RESET_MASK);	\
-+	control |= (BIG_SUR_GE_ECR_XMIT_ENABLE_MASK | BIG_SUR_GE_ECR_RECV_ENABLE_MASK);	\
-+	BIG_SUR_GE_WRITE(base_address + BIG_SUR_GE_ECR_OFFSET, control);		\
-+}
-+
-+/* Disable the MAC unit */
-+#define	big_sur_ge_mac_disable(base_address)					\
-+{										\
-+	u32	control;							\
-+	control = BIG_SUR_GE_READ(base_address + BIG_SUR_GE_ECR_OFFSET);		\
-+	control &= ~(BIG_SUR_GE_ECR_XMIT_ENABLE_MASK | BIG_SUR_GE_ECR_RECV_ENABLE_MASK);	\
-+	BIG_SUR_GE_WRITE(base_address + BIG_SUR_GE_ECR_OFFSET, control);		\
-+}
-+
-+/* Check if the Tx is done */
-+#define	big_sur_ge_tx_done(base_address)						\
-+	(BIG_SUR_GE_READ(base_address + BIG_SUR_GE_ISR_OFFSET) & BIG_SUR_GE_EIR_XMIT_DONE_MASK)
-+
-+
-+/* Check if Rx FIFO is empty */
-+#define	big_sur_ge_rx_empty(base_address)						\
-+	(!(BIG_SUR_GE_READ(base_address + BIG_SUR_GE_ISR_OFFSET) & BIG_SUR_GE_EIR_RECV_DONE_MASK))
-+
-+/* Reset the MAC PHY */
-+#define	big_sur_ge_reset_phy(base_address)						\
-+{											\
-+	u32	control;								\
-+	control = BIG_SUR_GE_READ(base_address + BIG_SUR_GE_ECR_OFFSET);			\
-+	control &= ~(BIG_SUR_GE_ECR_PHY_ENABLE_MASK);						\
-+	BIG_SUR_GE_WRITE(base_address + BIG_SUR_GE_ECR_OFFSET, control);			\
-+	control |= BIG_SUR_GE_ECR_PHY_ENABLE_MASK;						\
-+	BIG_SUR_GE_WRITE(base_address + BIG_SUR_GE_ECR_OFFSET, control);			\
-+}
-+
-+/* DMA SG defines */
-+#define BIG_SUR_GE_CONTROL_LAST_BD_MASK        0x02000000
-+#define BIG_SUR_GE_STATUS_LAST_BD_MASK         0x10000000
-+#define BIG_SUR_GE_RST_REG_OFFSET      0       /* reset register */
-+#define BIG_SUR_GE_MI_REG_OFFSET       0       /* module information register */
-+#define BIG_SUR_GE_DMAC_REG_OFFSET     4       /* DMA control register */
-+#define BIG_SUR_GE_SA_REG_OFFSET       8       /* source address register */
-+#define BIG_SUR_GE_DA_REG_OFFSET       12      /* destination address register */
-+#define BIG_SUR_GE_LEN_REG_OFFSET      16      /* length register */
-+#define BIG_SUR_GE_DMAS_REG_OFFSET     20      /* DMA status register */
-+#define BIG_SUR_GE_BDA_REG_OFFSET      24      /* buffer descriptor address register */
-+#define BIG_SUR_GE_SWCR_REG_OFFSET 28  /* software control register */
-+#define BIG_SUR_GE_UPC_REG_OFFSET      32      /* unserviced packet count register */
-+#define BIG_SUR_GE_PCT_REG_OFFSET      36      /* packet count threshold register */
-+#define BIG_SUR_GE_PWB_REG_OFFSET      40      /* packet wait bound register */
-+#define BIG_SUR_GE_IS_REG_OFFSET       44      /* interrupt status register */
-+#define BIG_SUR_GE_IE_REG_OFFSET       48      /* interrupt enable register */
-+
-+#define BIG_SUR_GE_RESET_MASK                          0x0000000A
-+
-+/* Buffer Descriptor Control */
-+
-+#define BIG_SUR_GE_DEVICE_STATUS_OFFSET    0
-+#define BIG_SUR_GE_CONTROL_OFFSET          1
-+#define BIG_SUR_GE_SOURCE_OFFSET           2
-+#define BIG_SUR_GE_DESTINATION_OFFSET      3
-+#define BIG_SUR_GE_LENGTH_OFFSET           4
-+#define BIG_SUR_GE_STATUS_OFFSET           5
-+#define BIG_SUR_GE_NEXT_PTR_OFFSET         6
-+#define BIG_SUR_GE_ID_OFFSET               7
-+#define BIG_SUR_GE_FLAGS_OFFSET            8
-+#define BIG_SUR_GE_RQSTED_LENGTH_OFFSET    9
-+
-+#define BIG_SUR_GE_FLAGS_LOCKED_MASK       1
-+
-+#define	xbuf_descriptor_init(base)				\
-+{								\
-+	(*((u32 *)base + BIG_SUR_GE_CONTROL_OFFSET) = 0);		\
-+	(*((u32 *)base + BIG_SUR_GE_SOURCE_OFFSET) = 0);        \
-+    	(*((u32 *)base + BIG_SUR_GE_DESTINATION_OFFSET) = 0);   \
-+    	(*((u32 *)base + BIG_SUR_GE_LENGTH_OFFSET) = 0);        \
-+    	(*((u32 *)base + BIG_SUR_GE_STATUS_OFFSET) = 0);        \
-+    	(*((u32 *)base + BIG_SUR_GE_DEVICE_STATUS_OFFSET) = 0); \
-+    	(*((u32 *)base + BIG_SUR_GE_NEXT_PTR_OFFSET) = 0);      \
-+    	(*((u32 *)base + BIG_SUR_GE_ID_OFFSET) = 0);            \
-+    	(*((u32 *)base + BIG_SUR_GE_FLAGS_OFFSET) = 0);         \
-+    	(*((u32 *)base + BIG_SUR_GE_RQSTED_LENGTH_OFFSET) = 0); \
-+}
-+
-+#define xbuf_descriptor_GetControl(base)   \
-+    (u32)(*((u32 *)base + BIG_SUR_GE_CONTROL_OFFSET))
-+
-+#define xbuf_descriptor_SetControl(base, Control)  \
-+    (*((u32 *)base + BIG_SUR_GE_CONTROL_OFFSET) = (u32)Control)
-+
-+#define xbuf_descriptor_IsLastControl(base) \
-+    (u32)(*((u32 *)base + BIG_SUR_GE_CONTROL_OFFSET) & \
-+               BIG_SUR_GE_CONTROL_LAST_BD_MASK)
-+
-+#define xbuf_descriptor_SetLast(base) \
-+    (*((u32 *)base + BIG_SUR_GE_CONTROL_OFFSET) |= BIG_SUR_GECONTROL_LAST_BD_MASK)
-+
-+#define xbuf_descriptor_GetSrcAddress(base) \
-+    ((u32 *)(*((u32 *)base + BIG_SUR_GE_SOURCE_OFFSET)))
-+
-+#define xbuf_descriptor_SetSrcAddress(base, Source) \
-+    (*((u32 *)base + BIG_SUR_GE_SOURCE_OFFSET) = (u32)Source)
-+
-+#define xbuf_descriptor_GetDestAddress(base) \
-+    ((u32 *)(*((u32 *)base + BIG_SUR_GE_DESTINATION_OFFSET)))
-+
-+#define xbuf_descriptor_SetDestAddress(base, Destination) \
-+    (*((u32 *)base + BIG_SUR_GE_DESTINATION_OFFSET) = (u32)Destination)
-+
-+#define xbuf_descriptor_GetLength(base)                           \
-+    (u32)(*((u32 *)base + BIG_SUR_GE_RQSTED_LENGTH_OFFSET) -    \
-+              *((u32 *)base + BIG_SUR_GE_LENGTH_OFFSET))
-+
-+#define xbuf_descriptor_SetLength(base, Length)                       \
-+{                                                                           \
-+    (*((u32 *)base + BIG_SUR_GE_LENGTH_OFFSET) = (u32)(Length));    \
-+    (*((u32 *)base + BIG_SUR_GE_RQSTED_LENGTH_OFFSET) = (u32)(Length));\
-+}
-+
-+#define xbuf_descriptor_GetStatus(base)    \
-+    (u32)(*((u32 *)base + BIG_SUR_GE_STATUS_OFFSET))
-+
-+#define xbuf_descriptor_SetStatus(base, Status)    \
-+    (*((u32 *)base + BIG_SUR_GE_STATUS_OFFSET) = (u32)Status)
-+
-+#define xbuf_descriptor_IsLastStatus(base) \
-+    (u32)(*((u32 *)base + BIG_SUR_GE_STATUS_OFFSET) & \
-+               BIG_SUR_GE_STATUS_LAST_BD_MASK)
-+
-+#define xbuf_descriptor_GetDeviceStatus(base) \
-+    ((u32)(*((u32 *)base + BIG_SUR_GE_DEVICE_STATUS_OFFSET)))
-+
-+#define xbuf_descriptor_SetDeviceStatus(base, Status) \
-+    (*((u32 *)base + BIG_SUR_GE_DEVICE_STATUS_OFFSET) = (u32)Status)
-+
-+#define xbuf_descriptor_GetNextPtr(base) \
-+    (xbuf_descriptor *)(*((u32 *)base + BIG_SUR_GE_NEXT_PTR_OFFSET))
-+
-+#define xbuf_descriptor_SetNextPtr(base, NextPtr) \
-+    (*((u32 *)base + BIG_SUR_GE_NEXT_PTR_OFFSET) = (u32)NextPtr)
-+
-+#define xbuf_descriptor_GetId(base) \
-+    (u32)(*((u32 *)base + BIG_SUR_GE_ID_OFFSET))
-+
-+#define xbuf_descriptor_SetId(base, Id) \
-+    (*((u32 *)base + BIG_SUR_GE_ID_OFFSET) = (u32)Id)
-+
-+#define xbuf_descriptor_GetFlags(base) \
-+    (u32)(*((u32 *)base + BIG_SUR_GE_FLAGS_OFFSET))
-+
-+#define xbuf_descriptor_SetFlags(base, Flags) \
-+    (*((u32 *)base + BIG_SUR_GE_FLAGS_OFFSET) = (u32)Flags)
-+
-+#define xbuf_descriptor_Lock(base) \
-+    (*((u32 *)base + BIG_SUR_GE_FLAGS_OFFSET) |= BIG_SUR_GE_FLAGS_LOCKED_MASK)
-+
-+#define xbuf_descriptor_Unlock(base) \
-+    (*((u32 *)base + BIG_SUR_GE_FLAGS_OFFSET) &= ~BIG_SUR_GE_FLAGS_LOCKED_MASK)
-+
-+#define xbuf_descriptor_IsLocked(base) \
-+	(*((u32 *)base + BIG_SUR_GE_FLAGS_OFFSET) & BIG_SUR_GE_FLAGS_LOCKED_MASK)
-+
-+#define BIG_SUR_GE_DMACR_SOURCE_INCR_MASK      0x80000000UL    /* increment source address */
-+#define BIG_SUR_GE_DMACR_DEST_INCR_MASK        0x40000000UL    /* increment dest address */
-+#define BIG_SUR_GE_DMACR_SOURCE_LOCAL_MASK 0x20000000UL        /* local source address */
-+#define BIG_SUR_GE_DMACR_DEST_LOCAL_MASK       0x10000000UL    /* local dest address */
-+#define BIG_SUR_GE_DMACR_SG_DISABLE_MASK       0x08000000UL    /* scatter gather disable */
-+#define BIG_SUR_GE_DMACR_GEN_BD_INTR_MASK      0x04000000UL    /* descriptor interrupt */
-+#define BIG_SUR_GE_DMACR_LAST_BD_MASK          BIG_SUR_GE_CONTROL_LAST_BD_MASK        /* last buffer */
-+#define BIG_SUR_GE_DMASR_BUSY_MASK                     0x80000000UL    /* channel is busy */
-+#define BIG_SUR_GE_DMASR_BUS_ERROR_MASK        0x40000000UL    /* bus error occurred */
-+#define BIG_SUR_GE_DMASR_BUS_TIMEOUT_MASK      0x20000000UL    /* bus timeout occurred */
-+#define BIG_SUR_GE_DMASR_LAST_BD_MASK          BIG_SUR_GE_STATUS_LAST_BD_MASK /* last buffer */
-+#define BIG_SUR_GE_DMASR_SG_BUSY_MASK          0x08000000UL    /* scatter gather is busy */
-+#define BIG_SUR_GE_IXR_DMA_DONE_MASK           0x1UL   /* dma operation done */
-+#define BIG_SUR_GE_IXR_DMA_ERROR_MASK      0x2UL       /* dma operation error */
-+#define BIG_SUR_GE_IXR_PKT_DONE_MASK       0x4UL       /* packet done */
-+#define BIG_SUR_GE_IXR_PKT_THRESHOLD_MASK      0x8UL   /* packet count threshold */
-+#define BIG_SUR_GE_IXR_PKT_WAIT_BOUND_MASK 0x10UL      /* packet wait bound reached */
-+#define BIG_SUR_GE_IXR_SG_DISABLE_ACK_MASK 0x20UL      /* scatter gather disable
-+                                                   acknowledge occurred */
-+#define BIG_SUR_GEIXR_SG_END_MASK                     0x40UL  /* last buffer descriptor
-+                                                           disabled scatter gather */
-+#define BIG_SUR_GEIXR_BD_MASK                         0x80UL  /* buffer descriptor done */
-+
-+/* BD control */
-+#define BIG_SUR_GE_DFT_SEND_BD_MASK    (BIG_SUR_GEDMACR_SOURCE_INCR_MASK | \
-+                                 BIG_SUR_GEDMACR_DEST_LOCAL_MASK)
-+#define BIG_SUR_GE_DFT_RECV_BD_MASK    (BIG_SUR_GEDMACR_DEST_INCR_MASK |  \
-+                                 BIG_SUR_GEDMACR_SOURCE_LOCAL_MASK)
-+
-+/* Interrupts */
-+#define BIG_SUR_GE_IPIF_EMAC_MASK      0x00000004UL    /* MAC interrupt */
-+#define BIG_SUR_GE_IPIF_SEND_DMA_MASK  0x00000008UL    /* Send DMA interrupt */
-+#define BIG_SUR_GE_IPIF_RECV_DMA_MASK  0x00000010UL    /* Receive DMA interrupt */
-+#define BIG_SUR_GE_IPIF_RECV_FIFO_MASK 0x00000020UL    /* Receive FIFO interrupt */
-+#define BIG_SUR_GE_IPIF_SEND_FIFO_MASK 0x00000040UL    /* Send FIFO interrupt */
-+
-+#define BIG_SUR_GE_IPIF_DMA_DFT_MASK   (BIG_SUR_GE_IPIF_SEND_DMA_MASK |   \
-+                                 BIG_SUR_GE_IPIF_RECV_DMA_MASK |   \
-+                                 BIG_SUR_GE_IPIF_EMAC_MASK |       \
-+                                 BIG_SUR_GE_IPIF_SEND_FIFO_MASK |  \
-+                                 BIG_SUR_GE_IPIF_RECV_FIFO_MASK)
-+
-+#define BIG_SUR_GE_IPIF_FIFO_DFT_MASK  (BIG_SUR_GE_IPIF_EMAC_MASK |       \
-+                                 BIG_SUR_GE_IPIF_SEND_FIFO_MASK |  \
-+                                 BIG_SUR_GE_IPIF_RECV_FIFO_MASK)
-+
-+#define BIG_SUR_GE_IPIF_DMA_DEV_INTR_COUNT   7 /* Number of interrupt sources */
-+#define BIG_SUR_GE_IPIF_FIFO_DEV_INTR_COUNT  5 /* Number of interrupt sources */
-+#define BIG_SUR_GE_IPIF_DEVICE_INTR_COUNT  7   /* Number of interrupt sources */
-+#define BIG_SUR_GE_IPIF_IP_INTR_COUNT      22  /* Number of MAC interrupts */
-+
-+/* a mask for all transmit interrupts, used in polled mode */
-+#define BIG_SUR_GE_EIR_XMIT_ALL_MASK   (BIG_SUR_GE_EIR_XMIT_DONE_MASK |           \
-+                                 BIG_SUR_GE_EIR_XMIT_ERROR_MASK |          \
-+                                 BIG_SUR_GE_EIR_XMIT_SFIFO_EMPTY_MASK |    \
-+                                 BIG_SUR_GE_EIR_XMIT_LFIFO_FULL_MASK)
-+
-+/* a mask for all receive interrupts, used in polled mode */
-+#define BIG_SUR_GE_EIR_RECV_ALL_MASK   (BIG_SUR_GE_EIR_RECV_DONE_MASK |           \
-+                                 BIG_SUR_GE_EIR_RECV_ERROR_MASK |          \
-+                                 BIG_SUR_GE_EIR_RECV_LFIFO_EMPTY_MASK |    \
-+                                 BIG_SUR_GE_EIR_RECV_LFIFO_OVER_MASK |     \
-+                                 BIG_SUR_GE_EIR_RECV_LFIFO_UNDER_MASK |    \
-+                                 BIG_SUR_GE_EIR_RECV_DFIFO_OVER_MASK |     \
-+                                 BIG_SUR_GE_EIR_RECV_MISSED_FRAME_MASK |   \
-+                                 BIG_SUR_GE_EIR_RECV_COLLISION_MASK |      \
-+                                 BIG_SUR_GE_EIR_RECV_FCS_ERROR_MASK |      \
-+                                 BIG_SUR_GE_EIR_RECV_LEN_ERROR_MASK |      \
-+                                 BIG_SUR_GE_EIR_RECV_SHORT_ERROR_MASK |    \
-+                                 BIG_SUR_GE_EIR_RECV_LONG_ERROR_MASK |     \
-+                                 BIG_SUR_GE_EIR_RECV_ALIGN_ERROR_MASK)
-+
-+/* a default interrupt mask for scatter-gather DMA operation */
-+#define BIG_SUR_GE_EIR_DFT_SG_MASK    (BIG_SUR_GE_EIR_RECV_ERROR_MASK |           \
-+                                BIG_SUR_GE_EIR_RECV_LFIFO_OVER_MASK |      \
-+                                BIG_SUR_GE_EIR_RECV_LFIFO_UNDER_MASK |     \
-+                                BIG_SUR_GE_EIR_XMIT_SFIFO_OVER_MASK |      \
-+                                BIG_SUR_GE_EIR_XMIT_SFIFO_UNDER_MASK |     \
-+                                BIG_SUR_GE_EIR_XMIT_LFIFO_OVER_MASK |      \
-+                                BIG_SUR_GE_EIR_XMIT_LFIFO_UNDER_MASK |     \
-+                                BIG_SUR_GE_EIR_RECV_DFIFO_OVER_MASK |      \
-+                                BIG_SUR_GE_EIR_RECV_MISSED_FRAME_MASK |    \
-+                                BIG_SUR_GE_EIR_RECV_COLLISION_MASK |       \
-+                                BIG_SUR_GE_EIR_RECV_FCS_ERROR_MASK |       \
-+                                BIG_SUR_GE_EIR_RECV_LEN_ERROR_MASK |       \
-+                                BIG_SUR_GE_EIR_RECV_SHORT_ERROR_MASK |     \
-+                                BIG_SUR_GE_EIR_RECV_LONG_ERROR_MASK |      \
-+                                BIG_SUR_GE_EIR_RECV_ALIGN_ERROR_MASK)
-+
-+/* a default interrupt mask for non-DMA operation (direct FIFOs) */
-+#define BIG_SUR_GE_EIR_DFT_FIFO_MASK  (BIG_SUR_GE_EIR_XMIT_DONE_MASK |            \
-+                                BIG_SUR_GE_EIR_RECV_DONE_MASK |            \
-+                                BIG_SUR_GE_EIR_DFT_SG_MASK)
-+
-+#define BIG_SUR_GE_DMA_SG_INTR_MASK    (BIG_SUR_GEIXR_DMA_ERROR_MASK  |      \
-+                                 BIG_SUR_GEIXR_PKT_THRESHOLD_MASK |   \
-+                                 BIG_SUR_GEIXR_PKT_WAIT_BOUND_MASK |  \
-+                                 BIG_SUR_GEIXR_SG_END_MASK)
-+
-+#endif
-diff -Naur linux-2.6.17.orig/drivers/net/declance.c linux-2.6.17/drivers/net/declance.c
---- linux-2.6.17.orig/drivers/net/declance.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/drivers/net/declance.c	2006-06-19 18:16:13.000000000 -0700
-@@ -704,8 +704,8 @@
- 	return IRQ_HANDLED;
- }
- 
--static irqreturn_t
--lance_interrupt(const int irq, void *dev_id, struct pt_regs *regs)
-+static irqreturn_t lance_interrupt(const int irq, void *dev_id,
-+				   struct pt_regs *regs)
- {
- 	struct net_device *dev = (struct net_device *) dev_id;
- 	struct lance_private *lp = netdev_priv(dev);
-@@ -1255,7 +1255,7 @@
- 	return 0;
- 
- err_out_free_dev:
--	kfree(dev);
-+	free_netdev(dev);
- 
- err_out:
- 	return ret;
-@@ -1301,6 +1301,7 @@
- 	while (root_lance_dev) {
- 		struct net_device *dev = root_lance_dev;
- 		struct lance_private *lp = netdev_priv(dev);
-+
- 		unregister_netdev(dev);
- #ifdef CONFIG_TC
- 		if (lp->slot >= 0)
-diff -Naur linux-2.6.17.orig/drivers/net/gt64240eth.c linux-2.6.17/drivers/net/gt64240eth.c
---- linux-2.6.17.orig/drivers/net/gt64240eth.c	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/drivers/net/gt64240eth.c	2006-06-19 18:16:13.000000000 -0700
-@@ -0,0 +1,1672 @@
-+/*
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License.  See the file "COPYING" in the main directory of this archive
-+ * for more details.
-+ *
-+ * Copyright (C) 2001 Patton Electronics Company
-+ * Copyright (C) 2002 Momentum Computer
-+ *
-+ * Copyright 2000 MontaVista Software Inc.
-+ * Author: MontaVista Software, Inc.
-+ *         	stevel@mvista.com or support@mvista.com
-+ *
-+ *  This program is free software; you can distribute it and/or modify it
-+ *  under the terms of the GNU General Public License (Version 2) as
-+ *  published by the Free Software Foundation.
-+ *
-+ *  This program is distributed in the hope it will be useful, but WITHOUT
-+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
-+ *  for more details.
-+ *
-+ *  You should have received a copy of the GNU General Public License along
-+ *  with this program; if not, write to the Free Software Foundation, Inc.,
-+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
-+ *
-+ * Ethernet driver for the MIPS GT96100 Advanced Communication Controller.
-+ * 
-+ * Modified for the Gallileo/Marvell GT-64240 Communication Controller.
-+ *
-+ * Support for Rx NAPI, Rx checksum offload, IOCTL and ETHTOOL added
-+ * Manish Lachwani (lachwani@pmc-sierra.com) - 09/16/2003
-+ *
-+ * Modified for later version of Linux 2.4 kernel
-+ * Manish Lachwani (lachwani@pmc-sierra.com) - 04/29/2004
-+ */
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/sched.h>
-+#include <linux/string.h>
-+#include <linux/timer.h>
-+#include <linux/errno.h>
-+#include <linux/in.h>
-+#include <linux/ioport.h>
-+#include <linux/slab.h>
-+#include <linux/interrupt.h>
-+#include <linux/pci.h>
-+#include <linux/init.h>
-+#include <linux/netdevice.h>
-+#include <linux/etherdevice.h>
-+#include <linux/ethtool.h>
-+#include <linux/skbuff.h>
-+#include <linux/delay.h>
-+#include <linux/ctype.h>
-+#include <linux/mii.h>
-+
-+#include <asm/irq.h>
-+#include <asm/bitops.h>
-+#include <asm/io.h>
-+#include <asm/uaccess.h>
-+
-+#define DESC_DATA_BE 1
-+
-+#include "gt64240eth.h"
-+
-+// enable this port (set hash size to 1/2K)
-+//- #define PORT_CONFIG pcrHS
-+#define PORT_CONFIG (pcrHS | pcrHD)
-+//- #define PORT_CONFIG pcrHS |pcrPM |pcrPBF|pcrHDM
-+//- GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG, pcrEN | pcrHS);
-+//- GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG, pcrEN | pcrHS | pcrPM);
-+//- GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG, pcrEN | pcrHS | pcrPM | 1<<pcrLPBKBit);
-+
-+// clear all the MIB ctr regs
-+#define EXT_CONFIG_CLEAR (pcxrFCTL | pcxrFCTLen | pcxrFLP | pcxrDPLXen | pcxrPRIOrxOverride | pcxrRMIIen)
-+
-+/*
-+ * _debug level:
-+ * <= 2	none.
-+ *  > 2	some warnings such as queue full, .....
-+ *  > 3	lots of change-of-state messages.
-+ *  > 4	EXTENSIVE data/descriptor dumps.
-+ */
-+
-+#ifdef GT64240_DEBUG
-+static int gt64240_debug = GT64240_DEBUG;
-+#else
-+static int gt64240_debug = 0;
-+#endif
-+
-+static int debug = -1;
-+
-+#define GT64240_MSG_ENABLE	(NETIF_MSG_DRV          | \
-+				NETIF_MSG_PROBE        | \
-+				NETIF_MSG_LINK)
-+
-+
-+/********************************************************/
-+
-+// prototypes
-+static void gt64240_delay(int msec);
-+static int gt64240_add_hash_entry(struct net_device *dev,
-+				  unsigned char *addr);
-+static void read_mib_counters(struct gt64240_private *gp);
-+static void dump_MII(struct net_device *dev);
-+static void dump_tx_desc(struct net_device *dev, int i);
-+static void dump_rx_desc(struct net_device *dev, int i);
-+static void dump_hw_addr(unsigned char *addr_str);
-+static void update_stats(struct gt64240_private *gp);
-+static void abort(struct net_device *dev, u32 abort_bits);
-+static void hard_stop(struct net_device *dev);
-+static void enable_ether_irq(struct net_device *dev);
-+static void disable_ether_irq(struct net_device *dev);
-+static int __init gt64240_probe1(unsigned long ioaddr, int irq, int port_num);
-+static void reset_tx(struct net_device *dev);
-+static void reset_rx(struct net_device *dev);
-+static int gt64240_init(struct net_device *dev);
-+static int gt64240_open(struct net_device *dev);
-+static int gt64240_close(struct net_device *dev);
-+static int gt64240_tx(struct sk_buff *skb, struct net_device *dev);
-+#ifdef GT64240_NAPI
-+static int gt64240_poll(struct net_device *dev, int *budget);
-+static int gt64240_rx(struct net_device *dev, u32 status, int budget);
-+#else
-+static int gt64240_rx(struct net_device *dev, u32 status);
-+#endif
-+static void gt64240_tx_timeout(struct net_device *dev);
-+static void gt64240_set_rx_mode(struct net_device *dev);
-+static struct net_device_stats *gt64240_get_stats(struct net_device *dev);
-+
-+extern char *__init prom_getcmdline(void);
-+extern int prom_get_mac_addrs(unsigned char
-+			      station_addr[NUM_INTERFACES][6]);
-+
-+static char version[] __devinitdata =
-+	"gt64240eth.o: version 0.1, <www.patton.com>\n";
-+
-+// PHY device addresses
-+static u32 gt64240_phy_addr[NUM_INTERFACES] __devinitdata = { 0x8, 0x1, 0xa };
-+
-+// Need real Ethernet addresses -- in parse_mac_addr_options(),
-+// these will be replaced by prom_get_mac_addrs() and/or prom_getcmdline().
-+static unsigned char gt64240_station_addr[NUM_INTERFACES][6] = {
-+	{0x00, 0x01, 0x02, 0x03, 0x04, 0x05},
-+	{0x01, 0x02, 0x03, 0x04, 0x05, 0x06},
-+	{0x02, 0x03, 0x04, 0x05, 0x06, 0x07}
-+};
-+
-+static int max_interrupt_work = 32;
-+
-+/*
-+ * Base address and interupt of the GT64240 ethernet controllers
-+ */
-+static struct {
-+	unsigned int port;
-+	int irq;
-+} gt64240_iflist[NUM_INTERFACES] = {
-+	{
-+	GT64240_ETH0_BASE, 8}, {
-+	GT64240_ETH1_BASE, 8}, {
-+	GT64240_ETH2_BASE, 8}
-+};
-+
-+static void gt64240_delay(int ms)
-+{
-+	if (in_interrupt())
-+		return;
-+	else {
-+		current->state = TASK_INTERRUPTIBLE;
-+		schedule_timeout(ms * HZ / 1000);
-+	}
-+}
-+
-+unsigned char prom_mac_addr_base[6];
-+
-+int prom_get_mac_addrs(unsigned char station_addr[NUM_INTERFACES][6])
-+{
-+	memcpy(station_addr[0], prom_mac_addr_base, 6);
-+	memcpy(station_addr[1], prom_mac_addr_base, 6);
-+	memcpy(station_addr[2], prom_mac_addr_base, 6);
-+
-+	station_addr[1][5] += 1;
-+	station_addr[2][5] += 2;
-+
-+	return 0;
-+}
-+
-+void parse_mac_addr_options(void)
-+{
-+	prom_get_mac_addrs(gt64240_station_addr);
-+}
-+
-+static int read_MII(struct net_device *dev, int phy, int reg)
-+{
-+	int timedout = 20;
-+	u32 smir = smirOpCode | (phy << smirPhyAdBit) |
-+	    (reg << smirRegAdBit);
-+
-+	// wait for last operation to complete
-+	while ((GT64240_READ(GT64240_ETH_SMI_REG)) & smirBusy) {
-+		// snooze for 1 msec and check again
-+		gt64240_delay(1);
-+
-+		if (--timedout == 0) {
-+			printk("%s: read_MII busy timeout!!\n", dev->name);
-+			return -1;
-+		}
-+	}
-+
-+	GT64240_WRITE(GT64240_ETH_SMI_REG, smir);
-+
-+	timedout = 20;
-+	// wait for read to complete
-+	while (!
-+	       ((smir =
-+		 GT64240_READ(GT64240_ETH_SMI_REG)) & smirReadValid)) {
-+		// snooze for 1 msec and check again
-+		gt64240_delay(1);
-+
-+		if (--timedout == 0) {
-+			printk("%s: read_MII timeout!!\n", dev->name);
-+			return -1;
-+		}
-+	}
-+
-+	return (int) (smir & smirDataMask);
-+}
-+
-+static void gp_get_drvinfo (struct net_device *dev, 
-+				struct ethtool_drvinfo *info)
-+{
-+	strcpy(info->driver, "gt64260");
-+	strcpy(info->version, version);
-+}
-+
-+static int gp_get_settings(struct net_device *dev, 
-+				struct ethtool_cmd *cmd)
-+{
-+	struct gt64240_private *gp = netdev_priv(dev);
-+	int rc;
-+
-+	spin_lock_irq(&gp->lock);
-+	rc = mii_ethtool_gset(&gp->mii_if, cmd);
-+	spin_unlock_irq(&gp->lock);
-+	return rc;
-+}
-+
-+static int gp_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
-+{
-+	struct gt64240_private *gp = netdev_priv(dev);
-+	int rc;
-+
-+	spin_lock_irq(&gp->lock);
-+	rc = mii_ethtool_sset(&gp->mii_if, cmd);
-+	spin_unlock_irq(&gp->lock);
-+	return rc;
-+}
-+
-+static int gp_nway_reset(struct net_device *dev)
-+{
-+	struct gt64240_private *gp = netdev_priv(dev);
-+	return mii_nway_restart(&gp->mii_if);
-+}
-+
-+static u32 gp_get_link(struct net_device *dev)
-+{
-+	struct gt64240_private *gp = netdev_priv(dev);
-+	return mii_link_ok(&gp->mii_if);
-+}
-+
-+static u32 gp_get_msglevel(struct net_device *dev)
-+{
-+	struct gt64240_private *gp = netdev_priv(dev);
-+	return gp->msg_enable;
-+}
-+
-+static void gp_set_msglevel(struct net_device *dev, u32 value)
-+{
-+	struct gt64240_private *gp = netdev_priv(dev);
-+	gp->msg_enable = value;
-+}
-+
-+static struct ethtool_ops gp_ethtool_ops = {
-+	.get_drvinfo		= gp_get_drvinfo,
-+	.get_settings		= gp_get_settings,
-+	.set_settings		= gp_set_settings,
-+	.nway_reset		= gp_nway_reset,
-+	.get_link		= gp_get_link,
-+	.get_msglevel		= gp_get_msglevel,
-+	.set_msglevel		= gp_set_msglevel,
-+};
-+
-+static int gt64240_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
-+{
-+	struct gt64240_private *gp = netdev_priv(dev);
-+	struct mii_ioctl_data *data =
-+	    (struct mii_ioctl_data *) &rq->ifr_data;
-+	int retval;
-+
-+	if (!netif_running(dev))
-+		return -EINVAL;
-+
-+	spin_lock_irq(&gp->lock);
-+	retval = generic_mii_ioctl(&gp->mii_if, data, cmd, NULL);
-+	spin_unlock_irq(&gp->lock);
-+
-+	return retval;
-+}
-+
-+static void dump_tx_desc(struct net_device *dev, int i)
-+{
-+	struct gt64240_private *gp = netdev_priv(dev);
-+	gt64240_td_t *td = &gp->tx_ring[i];
-+
-+	printk("%s:tx[%d]: self=%p cmd=%08x, cnt=%4d. bufp=%08x, next=%08x\n",
-+	       dev->name, i, td, td->cmdstat, td->byte_cnt, td->buff_ptr,
-+	       td->next);
-+}
-+
-+static void dump_rx_desc(struct net_device *dev, int i)
-+{
-+	struct gt64240_private *gp = netdev_priv(dev);
-+	gt64240_rd_t *rd = &gp->rx_ring[i];
-+
-+	printk("%s:rx_dsc[%d]: self=%p cst=%08x,size=%4d. cnt=%4d. "
-+	       "bufp=%08x, next=%08x\n",
-+	       dev->name, i, rd, rd->cmdstat, rd->buff_sz, rd->byte_cnt,
-+	       rd->buff_ptr, rd->next);
-+}
-+
-+// These routines work, just disabled to avoid compile warnings
-+static void write_MII(struct net_device *dev, int phy, int reg, int data)
-+{
-+	u32 smir = (phy << smirPhyAdBit) | (reg << smirRegAdBit) | data;
-+	int timedout = 20;
-+
-+	// wait for last operation to complete
-+	while (GT64240_READ(GT64240_ETH_SMI_REG) & smirBusy) {
-+		// snooze for 1 msec and check again
-+		gt64240_delay(1);
-+
-+		if (--timedout == 0) {
-+			printk("%s: write_MII busy timeout!!\n",
-+			       dev->name);
-+			return;
-+		}
-+	}
-+
-+	GT64240_WRITE(GT64240_ETH_SMI_REG, smir);
-+}
-+
-+static void dump_MII(struct net_device *dev)
-+{
-+	struct gt64240_private *gp = netdev_priv(dev);
-+	int i, val;
-+
-+	for (i = 0; i < 7; i++) {
-+		if ((val = read_MII(dev, gp->phy_addr, i)) >= 0)
-+			printk("%s: MII Reg %d=%x\n", dev->name, i, val);
-+	}
-+	for (i = 16; i < 21; i++) {
-+		if ((val = read_MII(dev, gp->phy_addr, i)) >= 0)
-+			printk("%s: MII Reg %d=%x\n", dev->name, i, val);
-+	}
-+}
-+
-+
-+static void dump_hw_addr(unsigned char *addr_str)
-+{
-+	int i;
-+	for (i = 0; i < 6; i++) {
-+		printk("%2.2x", addr_str[i]);
-+		printk(i < 5 ? ":" : "\n");
-+	}
-+}
-+
-+static int gt64240_add_hash_entry(struct net_device *dev,
-+				  unsigned char *addr)
-+{
-+	static unsigned char swapped[256];
-+	struct gt64240_private *gp;
-+	u32 value1, value0, *entry;
-+	unsigned char hash_ea[6];
-+	static int flag = 0;
-+	u16 hashResult;
-+	int i;
-+
-+	if (flag == 0) {	/* Create table to swap bits in a byte  */
-+		flag = 1;
-+		for (i = 0; i < 256; i++) {
-+			swapped[i] = (i & 0x01) << 7;
-+			swapped[i] |= (i & 0x02) << 5;
-+			swapped[i] |= (i & 0x04) << 3;
-+			swapped[i] |= (i & 0x08) << 1;
-+			swapped[i] |= (i & 0x10) >> 1;
-+			swapped[i] |= (i & 0x20) >> 3;
-+			swapped[i] |= (i & 0x40) >> 5;
-+			swapped[i] |= (i & 0x80) >> 7;
-+		}
-+	}
-+
-+	for (i = 0; i < 6; i++) {	/* swap bits from mac to create hash mac */
-+		hash_ea[i] = swapped[addr[i]];
-+	}
-+
-+	gp = netdev_priv(dev);
-+
-+	/* create hash entry address    */
-+	hashResult = (((hash_ea[5] >> 2) & 0x3F) << 9) & 0x7E00;
-+	hashResult |= ((hash_ea[4] & 0x7F) << 2) | (hash_ea[5] & 0x03);
-+	hashResult ^=
-+	    ((hash_ea[3] & 0xFF) << 1) | ((hash_ea[4] >> 7) & 0x01);
-+	hashResult ^= ((hash_ea[1] & 0x01) << 8) | (hash_ea[2] & 0xFF);
-+
-+	value0 = hteValid | hteRD;	/* Create hash table entry value */
-+	value0 |= (u32) addr[0] << 3;
-+	value0 |= (u32) addr[1] << 11;
-+	value0 |= (u32) addr[2] << 19;
-+	value0 |= ((u32) addr[3] & 0x1f) << 27;
-+
-+	value1 = ((u32) addr[3] >> 5) & 0x07;
-+	value1 |= (u32) addr[4] << 3;
-+	value1 |= (u32) addr[5] << 11;
-+
-+	/* Inset entry value into hash table */
-+	for (i = 0; i < HASH_HOP_NUMBER; i++) {
-+		entry = (u32 *) ((u32) gp->hash_table +
-+				 (((u32) hashResult & 0x07ff) << 3));
-+		if ((*entry & hteValid) && !(*entry & hteSkip)) {
-+			hashResult += 2;	/* oops, occupied, go to next entry */
-+		} else {
-+#ifdef __LITTLE_ENDIAN
-+			entry[1] = value1;
-+			entry[0] = value0;
-+#else
-+			entry[0] = value1;
-+			entry[1] = value0;
-+#endif
-+			break;
-+		}
-+	}
-+	if (i >= HASH_HOP_NUMBER) {
-+		printk("%s: gt64240_add_hash_entry expired!\n", dev->name);
-+		return (-1);
-+	}
-+	return (0);
-+}
-+
-+
-+static void read_mib_counters(struct gt64240_private *gp)
-+{
-+	u32 *mib_regs = (u32 *) & gp->mib;
-+	int i;
-+
-+	for (i = 0; i < sizeof(mib_counters_t) / sizeof(u32); i++)
-+		mib_regs[i] =
-+		    GT64240ETH_READ(gp,
-+				    GT64240_ETH_MIB_COUNT_BASE +
-+				    i * sizeof(u32));
-+}
-+
-+
-+static void update_stats(struct gt64240_private *gp)
-+{
-+	mib_counters_t *mib = &gp->mib;
-+	struct net_device_stats *stats = &gp->stats;
-+
-+	read_mib_counters(gp);
-+
-+	stats->rx_packets = mib->totalFramesReceived;
-+	stats->tx_packets = mib->framesSent;
-+	stats->rx_bytes = mib->totalByteReceived;
-+	stats->tx_bytes = mib->byteSent;
-+	stats->rx_errors = mib->totalFramesReceived - mib->framesReceived;
-+	//the tx error counters are incremented by the ISR
-+	//rx_dropped incremented by gt64240_rx
-+	//tx_dropped incremented by gt64240_tx
-+	stats->multicast = mib->multicastFramesReceived;
-+	// collisions incremented by gt64240_tx_complete
-+	stats->rx_length_errors = mib->oversizeFrames + mib->fragments;
-+	// The RxError condition means the Rx DMA encountered a
-+	// CPU owned descriptor, which, if things are working as
-+	// they should, means the Rx ring has overflowed.
-+	stats->rx_over_errors = mib->macRxError;
-+	stats->rx_crc_errors = mib->cRCError;
-+}
-+
-+static void abort(struct net_device *dev, u32 abort_bits)
-+{
-+	struct gt64240_private *gp = netdev_priv(dev);
-+	int timedout = 100;	// wait up to 100 msec for hard stop to complete
-+
-+	if (gt64240_debug > 3)
-+		printk("%s: abort\n", dev->name);
-+
-+	// Return if neither Rx or Tx abort bits are set
-+	if (!(abort_bits & (sdcmrAR | sdcmrAT)))
-+		return;
-+
-+	// make sure only the Rx/Tx abort bits are set
-+	abort_bits &= (sdcmrAR | sdcmrAT);
-+
-+	spin_lock(&gp->lock);
-+
-+	// abort any Rx/Tx DMA immediately
-+	GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_COMM, abort_bits);
-+
-+	if (gt64240_debug > 3)
-+		printk("%s: abort: SDMA cmd  = %x/%x\n",
-+		       dev->name, abort_bits, GT64240ETH_READ(gp,
-+							      GT64240_ETH_SDMA_COMM));
-+
-+	// wait for abort to complete
-+	while ((GT64240ETH_READ(gp, GT64240_ETH_SDMA_COMM)) & abort_bits) {
-+		// snooze for 20 msec and check again
-+		gt64240_delay(1);
-+
-+		if (--timedout == 0) {
-+			printk("%s: abort timeout!!\n", dev->name);
-+			break;
-+		}
-+	}
-+
-+	spin_unlock(&gp->lock);
-+}
-+
-+
-+static void hard_stop(struct net_device *dev)
-+{
-+	struct gt64240_private *gp = netdev_priv(dev);
-+
-+	if (gt64240_debug > 3)
-+		printk("%s: hard stop\n", dev->name);
-+
-+	disable_ether_irq(dev);
-+
-+	abort(dev, sdcmrAR | sdcmrAT);
-+
-+	// disable port
-+	GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG, 0);
-+	if (gt64240_debug > 3)
-+		printk("%s: gt64240_hard_stop: Port Config=%x\n",
-+		       dev->name, GT64240ETH_READ(gp,
-+						  GT64240_ETH_PORT_CONFIG));
-+
-+}
-+
-+static void gt64240_tx_complete(struct net_device *dev, u32 status)
-+{
-+	struct gt64240_private *gp = netdev_priv(dev);
-+	int nextOut, cdp;
-+	gt64240_td_t *td;
-+	u32 cmdstat;
-+
-+	cdp = (GT64240ETH_READ(gp, GT64240_ETH_CURR_TX_DESC_PTR0)
-+	       - gp->tx_ring_dma) / sizeof(gt64240_td_t);
-+
-+	if (gt64240_debug > 3) {	/*+prk17aug01 */
-+		nextOut = gp->tx_next_out;
-+		printk
-+		    ("%s: tx_complete: TX_PTR0=0x%08x, cdp=%d. nextOut=%d.\n",
-+		     dev->name, GT64240ETH_READ(gp,
-+						GT64240_ETH_CURR_TX_DESC_PTR0),
-+		     cdp, nextOut);
-+		td = &gp->tx_ring[nextOut];
-+	}
-+
-+/*** NEED to check and CLEAR these errors every time thru here: ***/
-+	if (gt64240_debug > 2) {
-+		if (GT64240_READ(COMM_UNIT_INTERRUPT_CAUSE))
-+			printk
-+			    ("%s: gt64240_tx_complete: CIU Cause=%08x, Mask=%08x, EAddr=%08x\n",
-+			     dev->name,
-+			     GT64240_READ(COMM_UNIT_INTERRUPT_CAUSE),
-+			     GT64240_READ(COMM_UNIT_INTERRUPT_MASK),
-+			     GT64240_READ(COMM_UNIT_ERROR_ADDRESS));
-+		GT64240_WRITE(COMM_UNIT_INTERRUPT_CAUSE, 0);
-+	}
-+	// Continue until we reach the current descriptor pointer
-+	for (nextOut = gp->tx_next_out; nextOut != cdp;
-+	     nextOut = (nextOut + 1) % TX_RING_SIZE) {
-+
-+		if (--gp->intr_work_done == 0)
-+			break;
-+
-+		td = &gp->tx_ring[nextOut];
-+		cmdstat = td->cmdstat;
-+
-+		if (cmdstat & (u32) txOwn) {
-+			// DMA is not finished writing descriptor???
-+			// Leave and come back later to pick-up where we left off.
-+			break;
-+		}
-+		// increment Tx error stats
-+		if (cmdstat & (u32) txErrorSummary) {
-+			if (gt64240_debug > 2)
-+				printk
-+				    ("%s: tx_complete: Tx error, cmdstat = %x\n",
-+				     dev->name, cmdstat);
-+			gp->stats.tx_errors++;
-+			if (cmdstat & (u32) txReTxLimit)
-+				gp->stats.tx_aborted_errors++;
-+			if (cmdstat & (u32) txUnderrun)
-+				gp->stats.tx_fifo_errors++;
-+			if (cmdstat & (u32) txLateCollision)
-+				gp->stats.tx_window_errors++;
-+		}
-+
-+		if (cmdstat & (u32) txCollision)
-+			gp->stats.collisions +=
-+			    (unsigned long) ((cmdstat & txReTxCntMask) >>
-+					     txReTxCntBit);
-+
-+		// Wake the queue if the ring was full
-+		if (gp->tx_full) {
-+			gp->tx_full = 0;
-+			if (gp->last_psr & psrLink) {
-+				netif_wake_queue(dev);
-+			}
-+		}
-+		// decrement tx ring buffer count
-+		if (gp->tx_count)
-+			gp->tx_count--;
-+
-+		// free the skb
-+		if (gp->tx_skbuff[nextOut]) {
-+			if (gt64240_debug > 3)
-+				printk
-+				    ("%s: tx_complete: good Tx, skb=%p\n",
-+				     dev->name, gp->tx_skbuff[nextOut]);
-+			dev_kfree_skb_irq(gp->tx_skbuff[nextOut]);
-+			gp->tx_skbuff[nextOut] = NULL;
-+		} else {
-+			printk("%s: tx_complete: no skb!\n", dev->name);
-+		}
-+	}
-+
-+	gp->tx_next_out = nextOut;
-+
-+	if ((status & icrTxEndLow) && gp->tx_count != 0) {
-+		// we must restart the DMA
-+		GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_COMM,
-+				 sdcmrERD | sdcmrTXDL);
-+	}
-+}
-+
-+static irqreturn_t gt64240_interrupt(int irq, void *dev_id,
-+	struct pt_regs *regs)
-+{
-+	struct net_device *dev = (struct net_device *) dev_id;
-+	struct gt64240_private *gp = netdev_priv(dev);
-+	u32 status;
-+
-+	if (dev == NULL) {
-+		printk("%s: isr: null dev ptr\n", dev->name);
-+		return IRQ_NONE;
-+	}
-+
-+	spin_lock(&gp->lock);
-+
-+	if (gt64240_debug > 3)
-+		printk("%s: isr: entry\n", dev->name);
-+
-+	gp->intr_work_done = max_interrupt_work;
-+
-+	while (gp->intr_work_done > 0) {
-+
-+		status = GT64240ETH_READ(gp, GT64240_ETH_INT_CAUSE);
-+#ifdef GT64240_NAPI
-+		/* dont ack Rx interrupts */
-+		if (!(status & icrRxBuffer))
-+			GT64240ETH_WRITE(gp, GT64240_ETH_INT_CAUSE, 0);
-+#else
-+		// ACK interrupts
-+		GT64240ETH_WRITE(gp, GT64240_ETH_INT_CAUSE, 0);
-+#endif
-+
-+		if (gt64240_debug > 3)
-+			printk("%s: isr: work=%d., icr=%x\n", dev->name,
-+			       gp->intr_work_done, status);
-+
-+		if ((status & icrEtherIntSum) == 0) {
-+			if (!(status &
-+			      (icrTxBufferLow | icrTxBufferHigh |
-+			       icrRxBuffer))) {
-+				/* exit from the while() loop */
-+				break;
-+			}
-+		}
-+
-+		if (status & icrMIIPhySTC) {
-+			u32 psr =
-+			    GT64240ETH_READ(gp, GT64240_ETH_PORT_STATUS);
-+			if (gp->last_psr != psr) {
-+				printk("%s: port status: 0x%08x\n",
-+				       dev->name, psr);
-+				printk
-+				    ("%s:    %s MBit/s, %s-duplex, flow-control %s, link is %s,\n",
-+				     dev->name,
-+				     psr & psrSpeed ? "100" : "10",
-+				     psr & psrDuplex ? "full" : "half",
-+				     psr & psrFctl ? "disabled" :
-+				     "enabled",
-+				     psr & psrLink ? "up" : "down");
-+				printk
-+				    ("%s:    TxLowQ is %s, TxHighQ is %s, Transmitter is %s\n",
-+				     dev->name,
-+				     psr & psrTxLow ? "running" :
-+				     "stopped",
-+				     psr & psrTxHigh ? "running" :
-+				     "stopped",
-+				     psr & psrTxInProg ? "on" : "off");
-+
-+				if ((psr & psrLink) && !gp->tx_full &&
-+				    netif_queue_stopped(dev)) {
-+					printk
-+					    ("%s: isr: Link up, waking queue.\n",
-+					     dev->name);
-+					netif_wake_queue(dev);
-+				} else if (!(psr & psrLink)
-+					   && !netif_queue_stopped(dev)) {
-+					printk
-+					    ("%s: isr: Link down, stopping queue.\n",
-+					     dev->name);
-+					netif_stop_queue(dev);
-+				}
-+
-+				gp->last_psr = psr;
-+			}
-+		}
-+
-+		if (status & (icrTxBufferLow | icrTxEndLow))
-+			gt64240_tx_complete(dev, status);
-+
-+		if (status & icrRxBuffer) {
-+#ifdef GT64240_NAPI
-+			if (netif_rx_schedule_prep(dev)) {
-+				disable_ether_irq(dev);
-+				__netif_rx_schedule(dev);
-+			}
-+#else
-+			gt64240_rx(dev, status);
-+#endif
-+		}
-+		// Now check TX errors (RX errors were handled in gt64240_rx)
-+		if (status & icrTxErrorLow) {
-+			printk("%s: isr: Tx resource error\n", dev->name);
-+		}
-+
-+		if (status & icrTxUdr) {
-+			printk("%s: isr: Tx underrun error\n", dev->name);
-+		}
-+	}
-+
-+	if (gp->intr_work_done == 0) {
-+		// ACK any remaining pending interrupts
-+		GT64240ETH_WRITE(gp, GT64240_ETH_INT_CAUSE, 0);
-+		if (gt64240_debug > 3)
-+			printk("%s: isr: hit max work\n", dev->name);
-+	}
-+
-+	if (gt64240_debug > 3)
-+		printk("%s: isr: exit, icr=%x\n",
-+		       dev->name, GT64240ETH_READ(gp,
-+						  GT64240_ETH_INT_CAUSE));
-+
-+	spin_unlock(&gp->lock);
-+
-+	return IRQ_HANDLED;
-+}
-+
-+static void enable_ether_irq(struct net_device *dev)
-+{
-+	struct gt64240_private *gp = netdev_priv(dev);
-+	u32 intMask;
-+
-+	intMask =
-+	    icrTxBufferLow | icrTxEndLow | icrTxErrorLow |
-+	    icrTxBufferHigh | icrTxEndHigh | icrTxErrorHigh | icrTxUdr |
-+	    icrRxBuffer | icrRxOVR | icrRxError | icrMIIPhySTC |
-+	    icrEtherIntSum;
-+
-+
-+//- GT64240ETH_WRITE(gp, GT64240_ETH_INT_CAUSE, 0); /* CLEAR existing ints */
-+	// unmask device interrupts:
-+	GT64240ETH_WRITE(gp, GT64240_ETH_INT_MASK, intMask);
-+
-+	// now route ethernet interrupts to GT PCI1 (eth0 and eth1 will be
-+	// sharing it).
-+	intMask = MV_READ(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH);
-+	intMask |= 1 << gp->port_num;
-+	MV_WRITE(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, intMask);
-+}
-+
-+static void disable_ether_irq(struct net_device *dev)
-+{
-+	struct gt64240_private *gp = netdev_priv(dev);
-+	u32 intMask;
-+
-+	intMask = MV_READ(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH);
-+	intMask &= ~(1 << gp->port_num);
-+	MV_WRITE(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, intMask);
-+
-+	// mask all device interrupts: 
-+	GT64240ETH_WRITE(gp, GT64240_ETH_INT_MASK, 0);
-+}
-+
-+/*
-+ * Probe for a GT64240 ethernet controller.
-+ */
-+static int __init gt64240_probe(void)
-+{
-+	int found = 0;
-+	int i;
-+
-+	parse_mac_addr_options();
-+
-+	for (i = 0; i < NUM_INTERFACES; i++) {
-+		unsigned long base_addr = gt64240_iflist[i].port;
-+
-+		if (check_region(base_addr, GT64240_ETH_IO_SIZE)) {
-+			printk("gt64240_probe: ioaddr 0x%lx taken?\n",
-+			       base_addr);
-+			continue;
-+		}
-+
-+		if (gt64240_probe1(base_addr, gt64240_iflist[i].irq, i) == 0) {
-+			/*
-+			 * Does not seem to be the "traditional" way folks do
-+			 * this, but I want to init both eth ports if at all
-+			 * possible!
-+			 *
-+			 * So, until I find out the "correct" way to do this:
-+			 */
-+			if (++found == NUM_INTERFACES)	/* That's all of them */
-+				return 0;
-+		}
-+	}
-+
-+	if (found)
-+		return 0;	/* as long as we found at least one! */
-+
-+	return -ENODEV;
-+}
-+
-+module_init(gt64240_probe);
-+
-+static int __init gt64240_probe1(unsigned long ioaddr, int irq, int port_num)
-+{
-+	struct net_device *dev = NULL;
-+	static unsigned version_printed = 0;
-+	struct gt64240_private *gp = NULL;
-+	int retval;
-+	u32 cpuConfig;
-+
-+	dev = alloc_etherdev(sizeof(struct gt64240_private));
-+	if (!dev)
-+		return -ENOMEM;
-+
-+	if (irq < 0) {
-+		printk
-+		    ("gt64240_probe1: irq unknown - probing not supported\n");
-+		return -ENODEV;
-+	}
-+#if 1				/* KLUDGE Alert: no check on return value: */
-+	if (!request_region(ioaddr, GT64240_ETH_IO_SIZE, "gt64240eth"))
-+		printk("*** request_region() failed!\n");
-+#endif
-+
-+	cpuConfig = GT64240_READ(CPU_CONFIGURATION);
-+	printk("gt64240_probe1: cpu in %s-endian mode\n",
-+	       (cpuConfig & (1 << 12)) ? "little" : "big");
-+
-+	printk("%s: GT64240 found at ioaddr 0x%lx, irq %d.\n",
-+	       dev->name, ioaddr, irq);
-+
-+	if (gt64240_debug && version_printed++ == 0)
-+		printk("%s: %s", dev->name, version);
-+
-+	/* private struct aligned and zeroed by init_etherdev */
-+	/* Fill in the 'dev' fields. */
-+	dev->base_addr = ioaddr;
-+	dev->irq = irq;
-+	memcpy(dev->dev_addr, gt64240_station_addr[port_num],
-+	       sizeof(dev->dev_addr));
-+
-+	printk("%s: HW Address ", dev->name);
-+	dump_hw_addr(dev->dev_addr);
-+
-+	gp = dev->priv;
-+
-+	gp->msg_enable = (debug < 0 ? GT64240_MSG_ENABLE : debug);
-+	gp->port_num = port_num;
-+	gp->io_size = GT64240_ETH_IO_SIZE;
-+	gp->port_offset = port_num * GT64240_ETH_IO_SIZE;
-+	gp->phy_addr = gt64240_phy_addr[port_num];
-+
-+	printk("%s: GT64240 ethernet port %d\n", dev->name, gp->port_num);
-+
-+#ifdef GT64240_NAPI
-+	printk("Rx NAPI supported \n");
-+#endif
-+
-+/* MII Initialization */
-+	gp->mii_if.dev = dev;
-+	gp->mii_if.phy_id = dev->base_addr;
-+	gp->mii_if.mdio_read = read_MII;
-+	gp->mii_if.mdio_write = write_MII;
-+	gp->mii_if.advertising = read_MII(dev, gp->phy_addr, MII_ADVERTISE);
-+
-+	// Allocate Rx and Tx descriptor rings
-+	if (gp->rx_ring == NULL) {
-+		// All descriptors in ring must be 16-byte aligned
-+		gp->rx_ring = dma_alloc_noncoherent(NULL,
-+					sizeof(gt64240_rd_t) * RX_RING_SIZE +
-+					sizeof(gt64240_td_t) * TX_RING_SIZE,
-+					&gp->rx_ring_dma, GFP_KERNEL);
-+		if (gp->rx_ring == NULL) {
-+			retval = -ENOMEM;
-+			goto free_region;
-+		}
-+
-+		gp->tx_ring = (gt64240_td_t *) (gp->rx_ring + RX_RING_SIZE);
-+		gp->tx_ring_dma =
-+			gp->rx_ring_dma + sizeof(gt64240_rd_t) * RX_RING_SIZE;
-+	}
-+	// Allocate the Rx Data Buffers
-+	if (gp->rx_buff == NULL) {
-+		gp->rx_buff = dma_alloc_coherent(NULL,
-+				PKT_BUF_SZ * RX_RING_SIZE, &gp->rx_buff_dma,
-+				GFP_KERNEL);
-+		if (gp->rx_buff == NULL) {
-+			dma_free_noncoherent(NULL,
-+				sizeof(gt64240_rd_t) * RX_RING_SIZE +
-+				sizeof(gt64240_td_t) * TX_RING_SIZE,
-+				gp->rx_ring, gp->rx_ring_dma);
-+			retval = -ENOMEM;
-+			goto free_region;
-+		}
-+	}
-+
-+	if (gt64240_debug > 3)
-+		printk("%s: gt64240_probe1, rx_ring=%p, tx_ring=%p\n",
-+		       dev->name, gp->rx_ring, gp->tx_ring);
-+
-+	// Allocate Rx Hash Table
-+	if (gp->hash_table == NULL) {
-+		gp->hash_table = dma_alloc_coherent(NULL,
-+				RX_HASH_TABLE_SIZE, &gp->hash_table_dma,
-+				GFP_KERNEL);
-+		if (gp->hash_table == NULL) {
-+			dma_free_noncoherent(NULL,
-+				sizeof(gt64240_rd_t) * RX_RING_SIZE +
-+				sizeof(gt64240_td_t) * TX_RING_SIZE,
-+				gp->rx_ring, gp->rx_ring_dma);
-+			dma_free_noncoherent(NULL, PKT_BUF_SZ * RX_RING_SIZE,
-+				gp->rx_buff, gp->rx_buff_dma);
-+			retval = -ENOMEM;
-+			goto free_region;
-+		}
-+	}
-+
-+	if (gt64240_debug > 3)
-+		printk("%s: gt64240_probe1, hash=%p\n",
-+		       dev->name, gp->hash_table);
-+
-+	spin_lock_init(&gp->lock);
-+
-+	dev->open = gt64240_open;
-+	dev->hard_start_xmit = gt64240_tx;
-+	dev->stop = gt64240_close;
-+	dev->get_stats = gt64240_get_stats;
-+	dev->do_ioctl = gt64240_ioctl;
-+	dev->set_multicast_list = gt64240_set_rx_mode;
-+	dev->tx_timeout = gt64240_tx_timeout;
-+	dev->watchdog_timeo = GT64240ETH_TX_TIMEOUT;
-+
-+#ifdef GT64240_NAPI
-+	dev->poll = gt64240_poll;
-+	dev->weight = 64;
-+#endif
-+	dev->ethtool_ops = &gp_ethtool_ops;
-+
-+	/* Fill in the fields of the device structure with ethernet values. */
-+	return 0;
-+
-+free_region:
-+	release_region(ioaddr, gp->io_size);
-+	unregister_netdev(dev);
-+	free_netdev(dev);
-+	printk("%s: gt64240_probe1 failed.  Returns %d\n",
-+	       dev->name, retval);
-+	return retval;
-+}
-+
-+
-+static void reset_tx(struct net_device *dev)
-+{
-+	struct gt64240_private *gp = netdev_priv(dev);
-+	int i;
-+
-+	abort(dev, sdcmrAT);
-+
-+	for (i = 0; i < TX_RING_SIZE; i++) {
-+		if (gp->tx_skbuff[i]) {
-+			if (in_interrupt())
-+				dev_kfree_skb_irq(gp->tx_skbuff[i]);
-+			else
-+				dev_kfree_skb(gp->tx_skbuff[i]);
-+			gp->tx_skbuff[i] = NULL;
-+		}
-+//-     gp->tx_ring[i].cmdstat = 0; // CPU owns
-+		gp->tx_ring[i].cmdstat =
-+		    (u32) (txGenCRC | txEI | txPad | txFirst | txLast);
-+		gp->tx_ring[i].byte_cnt = 0;
-+		gp->tx_ring[i].buff_ptr = 0;
-+		gp->tx_ring[i].next =
-+		    gp->tx_ring_dma + sizeof(gt64240_td_t) * (i + 1);
-+		if (gt64240_debug > 4)
-+			dump_tx_desc(dev, i);
-+	}
-+	/* Wrap the ring. */
-+	gp->tx_ring[i - 1].next = gp->tx_ring_dma;
-+	if (gt64240_debug > 4)
-+		dump_tx_desc(dev, i - 1);
-+
-+	// setup only the lowest priority TxCDP reg
-+	GT64240ETH_WRITE(gp, GT64240_ETH_CURR_TX_DESC_PTR0,
-+			 gp->tx_ring_dma);
-+//- GT64240ETH_WRITE(gp, GT64240_ETH_CURR_TX_DESC_PTR0, 0);     /* ROLLINS */
-+//- GT64240ETH_WRITE(gp, GT64240_ETH_CURR_TX_DESC_PTR0,virt_to_phys(&gp->tx_ring[0]));  /* ROLLINS */
-+
-+	GT64240ETH_WRITE(gp, GT64240_ETH_CURR_TX_DESC_PTR1, 0);
-+
-+	// init Tx indeces and pkt counter
-+	gp->tx_next_in = gp->tx_next_out = 0;
-+	gp->tx_count = 0;
-+}
-+
-+static void reset_rx(struct net_device *dev)
-+{
-+	struct gt64240_private *gp = netdev_priv(dev);
-+	int i;
-+
-+	abort(dev, sdcmrAR);
-+
-+	for (i = 0; i < RX_RING_SIZE; i++) {
-+		gp->rx_ring[i].next =
-+		    gp->rx_ring_dma + sizeof(gt64240_rd_t) * (i + 1);
-+		gp->rx_ring[i].buff_ptr = gp->rx_buff_dma + i * PKT_BUF_SZ;
-+		gp->rx_ring[i].buff_sz = PKT_BUF_SZ;
-+		gp->rx_ring[i].byte_cnt = 0;	/* just for debug printk's */
-+		// Give ownership to device, set first and last, enable interrupt
-+		gp->rx_ring[i].cmdstat =
-+		    (uint32_t) (rxFirst | rxLast | rxOwn | rxEI);
-+		if (gt64240_debug > 4)
-+			dump_rx_desc(dev, i);
-+	}
-+	/* Wrap the ring. */
-+	gp->rx_ring[i - 1].next = gp->rx_ring_dma;
-+	if (gt64240_debug > 4)
-+		dump_rx_desc(dev, i - 1);
-+
-+	// Setup only the lowest priority RxFDP and RxCDP regs
-+	for (i = 0; i < 4; i++) {
-+		if (i == 0) {
-+			GT64240ETH_WRITE(gp, GT64240_ETH_1ST_RX_DESC_PTR0,
-+					 gp->rx_ring_dma);
-+			GT64240ETH_WRITE(gp, GT64240_ETH_CURR_RX_DESC_PTR0,
-+					 gp->rx_ring_dma);
-+		} else {
-+			GT64240ETH_WRITE(gp,
-+					 GT64240_ETH_1ST_RX_DESC_PTR0 +
-+					 i * 4, 0);
-+			GT64240ETH_WRITE(gp,
-+					 GT64240_ETH_CURR_RX_DESC_PTR0 +
-+					 i * 4, 0);
-+		}
-+	}
-+
-+	// init Rx NextOut index
-+	gp->rx_next_out = 0;
-+}
-+
-+
-+static int gt64240_init(struct net_device *dev)
-+{
-+	struct gt64240_private *gp = netdev_priv(dev);
-+
-+	if (gt64240_debug > 3) {
-+		printk("%s: gt64240_init: dev=%p\n", dev->name, dev);
-+		printk("%s: gt64240_init: scs0_lo=%04x, scs0_hi=%04x\n",
-+		       dev->name, GT64240_READ(0x008),
-+		       GT64240_READ(0x010));
-+		printk("%s: gt64240_init: scs1_lo=%04x, scs1_hi=%04x\n",
-+		       dev->name, GT64240_READ(0x208),
-+		       GT64240_READ(0x210));
-+		printk("%s: gt64240_init: scs2_lo=%04x, scs2_hi=%04x\n",
-+		       dev->name, GT64240_READ(0x018),
-+		       GT64240_READ(0x020));
-+		printk("%s: gt64240_init: scs3_lo=%04x, scs3_hi=%04x\n",
-+		       dev->name, GT64240_READ(0x218),
-+		       GT64240_READ(0x220));
-+	}
-+	// Stop and disable Port
-+	hard_stop(dev);
-+
-+	GT64240_WRITE(COMM_UNIT_INTERRUPT_MASK, 0x07070777);	/*+prk21aug01 */
-+	if (gt64240_debug > 2)
-+		printk
-+		    ("%s: gt64240_init: CIU Cause=%08x, Mask=%08x, EAddr=%08x\n",
-+		     dev->name, GT64240_READ(COMM_UNIT_INTERRUPT_CAUSE),
-+		     GT64240_READ(COMM_UNIT_INTERRUPT_MASK),
-+		     GT64240_READ(COMM_UNIT_ERROR_ADDRESS));
-+
-+	// Set-up hash table
-+	memset(gp->hash_table, 0, RX_HASH_TABLE_SIZE);	// clear it
-+	gp->hash_mode = 0;
-+	// Add a single entry to hash table - our ethernet address
-+	gt64240_add_hash_entry(dev, dev->dev_addr);
-+	// Set-up DMA ptr to hash table
-+	GT64240ETH_WRITE(gp, GT64240_ETH_HASH_TBL_PTR, gp->hash_table_dma);
-+	if (gt64240_debug > 3)
-+		printk("%s: gt64240_init: Hash Tbl Ptr=%x\n", dev->name,
-+		       GT64240ETH_READ(gp, GT64240_ETH_HASH_TBL_PTR));
-+
-+	// Setup Tx
-+	reset_tx(dev);
-+
-+	if (gt64240_debug > 3)
-+		printk("%s: gt64240_init: Curr Tx Desc Ptr0=%x\n",
-+		       dev->name, GT64240ETH_READ(gp,
-+						  GT64240_ETH_CURR_TX_DESC_PTR0));
-+
-+	// Setup Rx
-+	reset_rx(dev);
-+
-+	if (gt64240_debug > 3)
-+		printk("%s: gt64240_init: 1st/Curr Rx Desc Ptr0=%x/%x\n",
-+		       dev->name, GT64240ETH_READ(gp,
-+						  GT64240_ETH_1ST_RX_DESC_PTR0),
-+		       GT64240ETH_READ(gp, GT64240_ETH_CURR_RX_DESC_PTR0));
-+
-+	if (gt64240_debug > 3)
-+		dump_MII(dev);
-+
-+	/* force a PHY reset -- self-clearing! */
-+	write_MII(dev, gp->phy_addr, 0, 0x8000);
-+
-+	if (gt64240_debug > 3)
-+		printk("%s: gt64240_init: PhyAD=%x\n", dev->name,
-+		       GT64240_READ(GT64240_ETH_PHY_ADDR_REG));
-+
-+	// setup DMA
-+	// We want the Rx/Tx DMA to write/read data to/from memory in
-+	// Big Endian mode. Also set DMA Burst Size to 8 64Bit words.
-+#ifdef DESC_DATA_BE
-+	GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_CONFIG,
-+			 (0xf << sdcrRCBit) | sdcrRIFB | (3 <<
-+							  sdcrBSZBit));
-+#else
-+	GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_CONFIG, sdcrBLMR | sdcrBLMT |
-+//-                  (0xf<<sdcrRCBit) | sdcrRIFB | (3<<sdcrBSZBit));
-+			 (0xf << sdcrRCBit) | sdcrRIFB | (2 <<
-+							  sdcrBSZBit));
-+#endif
-+
-+	if (gt64240_debug > 3)
-+		printk("%s: gt64240_init: SDMA Config=%x\n", dev->name,
-+		       GT64240ETH_READ(gp, GT64240_ETH_SDMA_CONFIG));
-+
-+#if 0
-+	// start Rx DMA
-+	GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_COMM, sdcmrERD);
-+#endif
-+
-+	if (gt64240_debug > 3)
-+		printk("%s: gt64240_init: SDMA Cmd =%x\n", dev->name,
-+		       GT64240ETH_READ(gp, GT64240_ETH_SDMA_COMM));
-+
-+#if 1
-+	GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG, PORT_CONFIG);
-+#endif
-+
-+	if (gt64240_debug > 3)
-+		printk("%s: gt64240_init: Port Config=%x\n", dev->name,
-+		       GT64240ETH_READ(gp, GT64240_ETH_PORT_CONFIG));
-+
-+	/*
-+	 * Disable all Type-of-Service queueing. All Rx packets will be
-+	 * treated normally and will be sent to the lowest priority
-+	 * queue.
-+	 *
-+	 * Disable flow-control for now. FIX! support flow control?
-+	 */
-+
-+#if 1
-+	// clear all the MIB ctr regs
-+	GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG_EXT,
-+			 EXT_CONFIG_CLEAR);
-+	read_mib_counters(gp);
-+	GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG_EXT,
-+			 EXT_CONFIG_CLEAR | pcxrMIBclrMode);
-+
-+#endif
-+	if (gt64240_debug > 3)
-+		printk("%s: gt64240_init: Port Config Ext=%x\n", dev->name,
-+		       GT64240ETH_READ(gp, GT64240_ETH_PORT_CONFIG_EXT));
-+
-+	if (gt64240_debug > 3)
-+		printk("%s: gt64240_init: Port Command=%x\n", dev->name,
-+		       GT64240ETH_READ(gp, GT64240_ETH_PORT_COMMAND));
-+	GT64240ETH_WRITE(gp, GT64240_ETH_PORT_COMMAND, 0x0);
-+
-+	netif_start_queue(dev);
-+
-+	/* enable the port */
-+	GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG,
-+			 (PORT_CONFIG | pcrEN));
-+	if (gt64240_debug > 3)
-+		printk("%s: gt64240_init: Port Config=%x\n", dev->name,
-+		       GT64240ETH_READ(gp, GT64240_ETH_PORT_CONFIG));
-+#if 1
-+	// start Rx DMA
-+	GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_COMM, sdcmrERD);
-+#endif
-+
-+
-+	// enable interrupts
-+	enable_ether_irq(dev);
-+
-+//---    gp->last_psr |= psrLink;   /* KLUDGE ALERT */
-+
-+	// we should now be receiving frames
-+	return 0;
-+}
-+
-+
-+static int gt64240_open(struct net_device *dev)
-+{
-+	int retval;
-+
-+	if (gt64240_debug > 3)
-+		printk("%s: gt64240_open: dev=%p\n", dev->name, dev);
-+
-+	if ((retval = request_irq(dev->irq, &gt64240_interrupt,
-+				  SA_SHIRQ, dev->name, dev))) {
-+		printk("%s: unable to get IRQ %d\n", dev->name, dev->irq);
-+
-+		return retval;
-+	}
-+	// Initialize and startup the GT-64240 ethernet port
-+	if ((retval = gt64240_init(dev))) {
-+		printk("%s: error in gt64240_open\n", dev->name);
-+		free_irq(dev->irq, dev);
-+
-+		return retval;
-+	}
-+
-+	if (gt64240_debug > 3)
-+		printk("%s: gt64240_open: Initialization done.\n",
-+		       dev->name);
-+
-+	return 0;
-+}
-+
-+static int gt64240_close(struct net_device *dev)
-+{
-+	if (gt64240_debug > 3)
-+		printk("%s: gt64240_close: dev=%p\n", dev->name, dev);
-+
-+	// stop the device
-+	if (netif_device_present(dev)) {
-+		netif_stop_queue(dev);
-+		hard_stop(dev);
-+	}
-+
-+	free_irq(dev->irq, dev);
-+
-+	return 0;
-+}
-+
-+#ifdef GT64240_NAPI
-+/*
-+ * Function will release Tx skbs which are now complete
-+ */
-+static void gt64240_tx_fill(struct net_device *dev, u32 status)
-+{
-+	struct gt64240_private *gp = netdev_priv(dev);
-+	int nextOut, cdp;
-+	gt64240_td_t *td;
-+	u32 cmdstat;
-+
-+	cdp = (GT64240ETH_READ(gp, GT64240_ETH_CURR_TX_DESC_PTR0)
-+	       - gp->tx_ring_dma) / sizeof(gt64240_td_t);
-+
-+	for (nextOut = gp->tx_next_out; nextOut != cdp;
-+	     nextOut = (nextOut + 1) % TX_RING_SIZE) {
-+		if (--gp->intr_work_done == 0)
-+			break;
-+
-+		td = &gp->tx_ring[nextOut];
-+		cmdstat = td->cmdstat;
-+
-+		if (cmdstat & (u32) txOwn)
-+			break;
-+
-+		if (gp->tx_full) {
-+			gp->tx_full = 0;
-+			if (gp->last_psr & psrLink) {
-+				netif_wake_queue(dev);
-+			}
-+		}
-+		// decrement tx ring buffer count
-+		if (gp->tx_count)
-+			gp->tx_count--;
-+
-+		// free the skb
-+		if (gp->tx_skbuff[nextOut]) {
-+			dev_kfree_skb_irq(gp->tx_skbuff[nextOut]);
-+			gp->tx_skbuff[nextOut] = NULL;
-+		}
-+	}
-+
-+	gp->tx_next_out = nextOut;
-+
-+	if ((status & icrTxEndLow) && gp->tx_count != 0)
-+		// we must restart the DMA
-+		GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_COMM,
-+				 sdcmrERD | sdcmrTXDL);
-+}
-+
-+/*
-+ * Main function for NAPI
-+ */
-+static int gt64240_poll(struct net_device *dev, int *budget)
-+{
-+	struct gt64240_private *gp = netdev_priv(dev);
-+	unsigned long flags;
-+	int done = 1, orig_budget, work_done;
-+	u32 status = GT64240ETH_READ(gp, GT64240_ETH_INT_CAUSE);
-+
-+	spin_lock_irqsave(&gp->lock, flags);
-+	gt64240_tx_fill(dev, status);
-+
-+	if (GT64240ETH_READ(gp, GT64240_ETH_CURR_RX_DESC_PTR0) !=
-+	    gp->rx_next_out) {
-+		orig_budget = *budget;
-+		if (orig_budget > dev->quota)
-+			orig_budget = dev->quota;
-+
-+		work_done = gt64240_rx(dev, status, orig_budget);
-+		*budget -= work_done;
-+		dev->quota -= work_done;
-+		if (work_done >= orig_budget)
-+			done = 0;
-+		if (done) {
-+			__netif_rx_complete(dev);
-+			enable_ether_irq(dev);
-+		}
-+	}
-+
-+	spin_unlock_irqrestore(&gp->lock, flags);
-+
-+	return (done ? 0 : 1);
-+}
-+#endif
-+
-+static int gt64240_tx(struct sk_buff *skb, struct net_device *dev)
-+{
-+	struct gt64240_private *gp = netdev_priv(dev);
-+	unsigned long flags;
-+	int nextIn;
-+
-+	spin_lock_irqsave(&gp->lock, flags);
-+
-+	nextIn = gp->tx_next_in;
-+
-+	if (gt64240_debug > 3) {
-+		printk("%s: gt64240_tx: nextIn=%d.\n", dev->name, nextIn);
-+	}
-+
-+	if (gp->tx_count >= TX_RING_SIZE) {
-+		printk("%s: Tx Ring full, pkt dropped.\n", dev->name);
-+		gp->stats.tx_dropped++;
-+		spin_unlock_irqrestore(&gp->lock, flags);
-+		return 1;
-+	}
-+
-+	if (!(gp->last_psr & psrLink)) {
-+		printk("%s: gt64240_tx: Link down, pkt dropped.\n",
-+		       dev->name);
-+		gp->stats.tx_dropped++;
-+		spin_unlock_irqrestore(&gp->lock, flags);
-+//---   dump_MII(dev);          /* KLUDGE ALERT !!! */
-+		return 1;
-+	}
-+
-+	if (gp->tx_ring[nextIn].cmdstat & txOwn) {
-+		printk
-+		    ("%s: gt64240_tx: device owns descriptor, pkt dropped.\n",
-+		     dev->name);
-+		gp->stats.tx_dropped++;
-+		// stop the queue, so Tx timeout can fix it
-+		netif_stop_queue(dev);
-+		spin_unlock_irqrestore(&gp->lock, flags);
-+		return 1;
-+	}
-+	// Prepare the Descriptor at tx_next_in
-+	gp->tx_skbuff[nextIn] = skb;
-+	gp->tx_ring[nextIn].byte_cnt = skb->len;
-+	gp->tx_ring[nextIn].buff_ptr = virt_to_phys(skb->data);
-+
-+	// make sure packet gets written back to memory
-+	dma_cache_wback_inv((unsigned long) (skb->data), skb->len);
-+	mb();
-+
-+	// Give ownership to device, set first and last desc, enable interrupt
-+	// Setting of ownership bit must be *last*!
-+	gp->tx_ring[nextIn].cmdstat =
-+	    txOwn | txGenCRC | txEI | txPad | txFirst | txLast;
-+
-+	if (gt64240_debug > 5) {
-+		dump_tx_desc(dev, nextIn);
-+	}
-+	// increment tx_next_in with wrap
-+	gp->tx_next_in = (nextIn + 1) % TX_RING_SIZE;
-+
-+//+prk20aug01:
-+	if (0) {		/* ROLLINS */
-+		GT64240ETH_WRITE(gp, GT64240_ETH_CURR_TX_DESC_PTR0,
-+				 virt_to_phys(&gp->tx_ring[nextIn]));
-+	}
-+
-+	if (gt64240_debug > 3) {	/*+prk17aug01 */
-+		printk
-+		    ("%s: gt64240_tx: TX_PTR0=0x%08x, EthPortStatus=0x%08x\n",
-+		     dev->name, GT64240ETH_READ(gp,
-+						GT64240_ETH_CURR_TX_DESC_PTR0),
-+		     GT64240ETH_READ(gp, GT64240_ETH_PORT_STATUS));
-+	}
-+	// If DMA is stopped, restart
-+	if (!((GT64240ETH_READ(gp, GT64240_ETH_PORT_STATUS)) & psrTxLow)) {
-+		GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_COMM,
-+				 sdcmrERD | sdcmrTXDL);
-+	}
-+
-+	if (gt64240_debug > 3) {	/*+prk17aug01 */
-+		printk
-+		    ("%s: gt64240_tx: TX_PTR0=0x%08x, EthPortStatus=0x%08x\n",
-+		     dev->name, GT64240ETH_READ(gp,
-+						GT64240_ETH_CURR_TX_DESC_PTR0),
-+		     GT64240ETH_READ(gp, GT64240_ETH_PORT_STATUS));
-+	}
-+	// increment count and stop queue if full
-+	if (++gp->tx_count >= TX_RING_SIZE) {
-+		gp->tx_full = 1;
-+		netif_stop_queue(dev);
-+	}
-+
-+	dev->trans_start = jiffies;
-+	spin_unlock_irqrestore(&gp->lock, flags);
-+
-+	return 0;
-+}
-+
-+
-+static int
-+#ifdef GT64240_NAPI
-+gt64240_rx(struct net_device *dev, u32 status, int budget)
-+#else
-+gt64240_rx(struct net_device *dev, u32 status)
-+#endif
-+{
-+	struct gt64240_private *gp = netdev_priv(dev);
-+	struct sk_buff *skb;
-+	int pkt_len, nextOut, cdp;
-+	gt64240_rd_t *rd;
-+	u32 cmdstat;
-+
-+	if (gt64240_debug > 3)
-+		printk("%s: gt64240_rx: dev=%p, status=%x\n",
-+		       dev->name, dev, status);
-+
-+	cdp = (GT64240ETH_READ(gp, GT64240_ETH_CURR_RX_DESC_PTR0)
-+	       - gp->rx_ring_dma) / sizeof(gt64240_rd_t);
-+
-+	// Continue until we reach the current descriptor pointer
-+	for (nextOut = gp->rx_next_out; nextOut != cdp;
-+	     nextOut = (nextOut + 1) % RX_RING_SIZE) {
-+
-+#ifdef GT64240_NAPI
-+		if (budget <= 0)
-+			break;
-+
-+		budget--;
-+#endif
-+
-+		if (--gp->intr_work_done == 0)
-+			break;
-+
-+		if (gt64240_debug > 4)
-+			dump_rx_desc(dev, nextOut);
-+
-+		rd = &gp->rx_ring[nextOut];
-+		cmdstat = rd->cmdstat;
-+
-+		if (gt64240_debug > 3)
-+			printk("%s: isr: Rx desc cmdstat=%x, nextOut=%d\n",
-+			       dev->name, cmdstat, nextOut);
-+
-+		if (cmdstat & (u32) rxOwn) {
-+			if (gt64240_debug > 2)
-+				printk
-+				    ("%s: gt64240_rx: device owns descriptor!\n",
-+				     dev->name);
-+			// DMA is not finished updating descriptor???
-+			// Leave and come back later to pick-up where we left off.
-+			break;
-+		}
-+		// must be first and last (ie only) buffer of packet
-+		if (!(cmdstat & (u32) rxFirst)
-+		    || !(cmdstat & (u32) rxLast)) {
-+			printk
-+			    ("%s: gt64240_rx: desc not first and last!\n",
-+			     dev->name);
-+			cmdstat |= (u32) rxOwn;
-+			rd->cmdstat = cmdstat;
-+			continue;
-+		}
-+		// Drop this received pkt if there were any errors
-+		if ((cmdstat & (u32) rxErrorSummary)
-+		    || (status & icrRxError)) {
-+			// update the detailed rx error counters that are not covered
-+			// by the MIB counters.
-+			if (cmdstat & (u32) rxOverrun)
-+				gp->stats.rx_fifo_errors++;
-+			cmdstat |= (u32) rxOwn;
-+			rd->cmdstat = cmdstat;
-+			continue;
-+		}
-+
-+		pkt_len = rd->byte_cnt;
-+
-+		/* Create new skb. */
-+//      skb = dev_alloc_skb(pkt_len+2);
-+		skb = dev_alloc_skb(1538);
-+		if (skb == NULL) {
-+			printk("%s: Memory squeeze, dropping packet.\n",
-+			       dev->name);
-+			gp->stats.rx_dropped++;
-+			cmdstat |= (u32) rxOwn;
-+			rd->cmdstat = cmdstat;
-+			continue;
-+		}
-+		skb->dev = dev;
-+		skb_reserve(skb, 2);	/* 16 byte IP header align */
-+		memcpy(skb_put(skb, pkt_len),
-+		       &gp->rx_buff[nextOut * PKT_BUF_SZ], pkt_len);
-+		skb->protocol = eth_type_trans(skb, dev);
-+
-+		/* NIC performed some checksum computation */
-+		skb->ip_summed = CHECKSUM_UNNECESSARY;
-+#ifdef GT64240_NAPI
-+		netif_receive_skb(skb);
-+#else
-+		netif_rx(skb);	/* pass the packet to upper layers */
-+#endif
-+
-+		// now we can release ownership of this desc back to device
-+		cmdstat |= (u32) rxOwn;
-+		rd->cmdstat = cmdstat;
-+
-+		dev->last_rx = jiffies;
-+	}
-+
-+	if (gt64240_debug > 3 && nextOut == gp->rx_next_out)
-+		printk("%s: gt64240_rx: RxCDP did not increment?\n",
-+		       dev->name);
-+
-+	gp->rx_next_out = nextOut;
-+	return 0;
-+}
-+
-+
-+static void gt64240_tx_timeout(struct net_device *dev)
-+{
-+	struct gt64240_private *gp = netdev_priv(dev);
-+	unsigned long flags;
-+
-+	spin_lock_irqsave(&gp->lock, flags);
-+
-+
-+	if (!(gp->last_psr & psrLink)) {
-+		spin_unlock_irqrestore(&gp->lock, flags);
-+	} else {
-+		printk("======------> gt64240_tx_timeout: %d jiffies \n",
-+		       GT64240ETH_TX_TIMEOUT);
-+
-+		disable_ether_irq(dev);
-+		spin_unlock_irqrestore(&gp->lock, flags);
-+		reset_tx(dev);
-+		enable_ether_irq(dev);
-+
-+		netif_wake_queue(dev);
-+	}
-+}
-+
-+
-+static void gt64240_set_rx_mode(struct net_device *dev)
-+{
-+	struct gt64240_private *gp = netdev_priv(dev);
-+	unsigned long flags;
-+	struct dev_mc_list *mcptr;
-+
-+	if (gt64240_debug > 3)
-+		printk("%s: gt64240_set_rx_mode: dev=%p, flags=%x\n",
-+		       dev->name, dev, dev->flags);
-+
-+	// stop the Receiver DMA
-+	abort(dev, sdcmrAR);
-+
-+	spin_lock_irqsave(&gp->lock, flags);
-+
-+	if (dev->flags & IFF_PROMISC)
-+		GT64240ETH_SETBIT(gp, GT64240_ETH_PORT_CONFIG, pcrPM);
-+	else
-+		GT64240ETH_CLRBIT(gp, GT64240_ETH_PORT_CONFIG, pcrPM);
-+/*
-+	GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG,
-+		(PORT_CONFIG | pcrPM | pcrEN));
-+*/
-+
-+	memset(gp->hash_table, 0, RX_HASH_TABLE_SIZE);	// clear hash table
-+	// Add our ethernet address
-+	gt64240_add_hash_entry(dev, dev->dev_addr);
-+	if (dev->mc_count) {
-+		for (mcptr = dev->mc_list; mcptr; mcptr = mcptr->next) {
-+			if (gt64240_debug > 2) {
-+				printk("%s: gt64240_set_rx_mode: addr=\n",
-+				       dev->name);
-+				dump_hw_addr(mcptr->dmi_addr);
-+			}
-+			gt64240_add_hash_entry(dev, mcptr->dmi_addr);
-+		}
-+	}
-+
-+	if (gt64240_debug > 3)
-+		printk("%s: gt64240_set_rx: Port Config=%x\n", dev->name,
-+		       GT64240ETH_READ(gp, GT64240_ETH_PORT_CONFIG));
-+
-+	// restart Rx DMA
-+	GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_COMM, sdcmrERD);
-+
-+	spin_unlock_irqrestore(&gp->lock, flags);
-+}
-+
-+static struct net_device_stats *gt64240_get_stats(struct net_device *dev)
-+{
-+	struct gt64240_private *gp = netdev_priv(dev);
-+	unsigned long flags;
-+
-+	if (gt64240_debug > 3)
-+		printk("%s: gt64240_get_stats: dev=%p\n", dev->name, dev);
-+
-+	if (netif_device_present(dev)) {
-+		spin_lock_irqsave(&gp->lock, flags);
-+		update_stats(gp);
-+		spin_unlock_irqrestore(&gp->lock, flags);
-+	}
-+
-+	return &gp->stats;
-+}
-diff -Naur linux-2.6.17.orig/drivers/net/gt64240eth.h linux-2.6.17/drivers/net/gt64240eth.h
---- linux-2.6.17.orig/drivers/net/gt64240eth.h	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/drivers/net/gt64240eth.h	2006-06-19 18:16:13.000000000 -0700
-@@ -9,6 +9,7 @@
-  * Copyright 2000 MontaVista Software Inc.
-  * Author: MontaVista Software, Inc.
-  *         	stevel@mvista.com or support@mvista.com
-+ * Copyright 2004, 05 Ralf Baechle (ralf@linux-mips.org)
-  *
-  *  This program is free software; you can distribute it and/or modify it
-  *  under the terms of the GNU General Public License (Version 2) as
-@@ -31,6 +32,7 @@
- #ifndef _GT64240ETH_H
- #define _GT64240ETH_H
- 
-+#include <linux/config.h>
- #include <asm/gt64240.h>
- 
- #define ETHERNET_PORTS_DIFFERENCE_OFFSETS	0x400
-@@ -108,10 +110,10 @@
- #define REV_GT64240A 0x10
- 
- #define GT64240ETH_READ(gp, offset)					\
--	GT_READ((gp)->port_offset + (offset))
-+	MV_READ((gp)->port_offset + (offset))
- 
- #define GT64240ETH_WRITE(gp, offset, data)				\
--	GT_WRITE((gp)->port_offset + (offset), (data))
-+	MV_WRITE((gp)->port_offset + (offset), (data))
- 
- #define GT64240ETH_SETBIT(gp, offset, bits)				\
- 	GT64240ETH_WRITE((gp), (offset),				\
-@@ -121,8 +123,8 @@
- 	GT64240ETH_WRITE((gp), (offset),				\
- 	                 GT64240ETH_READ((gp), (offset)) & ~(bits))
- 
--#define GT64240_READ(ofs)		GT_READ(ofs)
--#define GT64240_WRITE(ofs, data)	GT_WRITE((ofs), (data))
-+#define GT64240_READ(ofs)		MV_READ(ofs)
-+#define GT64240_WRITE(ofs, data)	MV_WRITE((ofs), (data))
- 
- /* Bit definitions of the SMI Reg */
- enum {
-diff -Naur linux-2.6.17.orig/drivers/net/ioc3-eth.c linux-2.6.17/drivers/net/ioc3-eth.c
---- linux-2.6.17.orig/drivers/net/ioc3-eth.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/drivers/net/ioc3-eth.c	2006-06-19 18:16:13.000000000 -0700
-@@ -5,7 +5,7 @@
-  *
-  * Driver for SGI's IOC3 based Ethernet cards as found in the PCI card.
-  *
-- * Copyright (C) 1999, 2000, 2001, 2003 Ralf Baechle
-+ * Copyright (C) 1999, 2000, 01, 03, 06 Ralf Baechle
-  * Copyright (C) 1995, 1999, 2000, 2001 by Silicon Graphics, Inc.
-  *
-  * References:
-@@ -63,12 +63,7 @@
- #include <asm/pgtable.h>
- #include <asm/uaccess.h>
- #include <asm/sn/types.h>
--#include <asm/sn/sn0/addrs.h>
--#include <asm/sn/sn0/hubni.h>
--#include <asm/sn/sn0/hubio.h>
--#include <asm/sn/klconfig.h>
- #include <asm/sn/ioc3.h>
--#include <asm/sn/sn0/ip27.h>
- #include <asm/pci/bridge.h>
- 
- /*
-@@ -96,6 +91,9 @@
- 	u32 emcr, ehar_h, ehar_l;
- 	spinlock_t ioc3_lock;
- 	struct mii_if_info mii;
-+	unsigned long flags;
-+#define IOC3_FLAG_RX_CHECKSUMS	1
-+
- 	struct pci_dev *pdev;
- 
- 	/* Members used by autonegotiation  */
-@@ -145,7 +143,7 @@
- static inline unsigned long ioc3_map(void *ptr, unsigned long vdev)
- {
- #ifdef CONFIG_SGI_IP27
--	vdev <<= 58;   /* Shift to PCI64_ATTR_VIRTUAL */
-+	vdev <<= 57;   /* Shift to PCI64_ATTR_VIRTUAL */
- 
- 	return vdev | (0xaUL << PCI64_ATTR_TARG_SHFT) | PCI64_ATTR_PREF |
- 	       ((unsigned long)ptr & TO_PHYS_MASK);
-@@ -523,8 +521,6 @@
- 	return &ip->stats;
- }
- 
--#ifdef CONFIG_SGI_IOC3_ETH_HW_RX_CSUM
--
- static void ioc3_tcpudp_checksum(struct sk_buff *skb, uint32_t hwsum, int len)
- {
- 	struct ethhdr *eh = eth_hdr(skb);
-@@ -592,7 +588,6 @@
- 	if (csum == 0xffff)
- 		skb->ip_summed = CHECKSUM_UNNECESSARY;
- }
--#endif /* CONFIG_SGI_IOC3_ETH_HW_RX_CSUM */
- 
- static inline void ioc3_rx(struct ioc3_private *ip)
- {
-@@ -627,9 +622,9 @@
- 				goto next;
- 			}
- 
--#ifdef CONFIG_SGI_IOC3_ETH_HW_RX_CSUM
--			ioc3_tcpudp_checksum(skb, w0 & ERXBUF_IPCKSUM_MASK,len);
--#endif
-+			if (likely(ip->flags & IOC3_FLAG_RX_CHECKSUMS))
-+				ioc3_tcpudp_checksum(skb,
-+					w0 & ERXBUF_IPCKSUM_MASK, len);
- 
- 			netif_rx(skb);
- 
-@@ -1290,9 +1285,7 @@
- 	dev->set_multicast_list	= ioc3_set_multicast_list;
- 	dev->set_mac_address	= ioc3_set_mac_address;
- 	dev->ethtool_ops	= &ioc3_ethtool_ops;
--#ifdef CONFIG_SGI_IOC3_ETH_HW_TX_CSUM
- 	dev->features		= NETIF_F_IP_CSUM;
--#endif
- 
- 	sw_physid1 = ioc3_mdio_read(dev, ip->mii.phy_id, MII_PHYSID1);
- 	sw_physid2 = ioc3_mdio_read(dev, ip->mii.phy_id, MII_PHYSID2);
-@@ -1379,7 +1372,6 @@
- 	uint32_t w0 = 0;
- 	int produce;
- 
--#ifdef CONFIG_SGI_IOC3_ETH_HW_TX_CSUM
- 	/*
- 	 * IOC3 has a fairly simple minded checksumming hardware which simply
- 	 * adds up the 1's complement checksum for the entire packet and
-@@ -1427,7 +1419,6 @@
- 
- 		w0 = ETXD_DOCHECKSUM | (csoff << ETXD_CHKOFF_SHIFT);
- 	}
--#endif /* CONFIG_SGI_IOC3_ETH_HW_TX_CSUM */
- 
- 	spin_lock_irq(&ip->ioc3_lock);
- 
-@@ -1581,12 +1572,37 @@
- 	return rc;
- }
- 
-+static u32 ioc3_get_rx_csum(struct net_device *dev)
-+{
-+	struct ioc3_private *ip = netdev_priv(dev);
-+
-+	return ip->flags & IOC3_FLAG_RX_CHECKSUMS;
-+}
-+
-+static int ioc3_set_rx_csum(struct net_device *dev, u32 data)
-+{
-+	struct ioc3_private *ip = netdev_priv(dev);
-+
-+	spin_lock_bh(&ip->ioc3_lock);
-+	if (data)
-+		ip->flags |= IOC3_FLAG_RX_CHECKSUMS;
-+	else
-+		ip->flags &= ~IOC3_FLAG_RX_CHECKSUMS;
-+	spin_unlock_bh(&ip->ioc3_lock);
-+
-+	return 0;
-+}
-+
- static struct ethtool_ops ioc3_ethtool_ops = {
- 	.get_drvinfo		= ioc3_get_drvinfo,
- 	.get_settings		= ioc3_get_settings,
- 	.set_settings		= ioc3_set_settings,
- 	.nway_reset		= ioc3_nway_reset,
- 	.get_link		= ioc3_get_link,
-+	.get_rx_csum		= ioc3_get_rx_csum,
-+	.set_rx_csum		= ioc3_set_rx_csum,
-+	.get_tx_csum		= ethtool_op_get_tx_csum,
-+	.set_tx_csum		= ethtool_op_set_tx_csum
- };
- 
- static int ioc3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
-diff -Naur linux-2.6.17.orig/drivers/net/Kconfig linux-2.6.17/drivers/net/Kconfig
---- linux-2.6.17.orig/drivers/net/Kconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/drivers/net/Kconfig	2006-06-19 18:16:13.000000000 -0700
-@@ -438,6 +438,14 @@
- 	  This is the driver for the onboard card of MIPS Magnum 4000,
- 	  Acer PICA, Olivetti M700-10 and a few other identical OEM systems.
- 
-+config GALILEO_64240_ETH
-+	tristate "Galileo GT64240 Ethernet support"
-+	depends on NET_ETHERNET && MOMENCO_OCELOT_G
-+	select MII
-+	help
-+	  This is the driver for the ethernet interfaces integrated into
-+	  the Galileo (now Marvell) GT64240 chipset.
-+
- config MIPS_GT96100ETH
- 	bool "MIPS GT96100 Ethernet support"
- 	depends on NET_ETHERNET && MIPS_GT96100
-@@ -452,10 +460,6 @@
- 	  If you have an Alchemy Semi AU1X00 based system
- 	  say Y.  Otherwise, say N.
- 
--config NET_SB1250_MAC
--	tristate "SB1250 Ethernet support"
--	depends on NET_ETHERNET && SIBYTE_SB1xxx_SOC
--
- config SGI_IOC3_ETH
- 	bool "SGI IOC3 Ethernet"
- 	depends on NET_ETHERNET && PCI && SGI_IP27
-@@ -466,25 +470,13 @@
- 	  the Ethernet-HOWTO, available from
- 	  <http://www.tldp.org/docs.html#howto>.
- 
--config SGI_IOC3_ETH_HW_RX_CSUM
--	bool "Receive hardware checksums"
--	depends on SGI_IOC3_ETH && INET
--	default y
--	help
--	  The SGI IOC3 network adapter supports TCP and UDP checksums in
--	  hardware to offload processing of these checksums from the CPU.  At
--	  the moment only acceleration of IPv4 is supported.  This option
--	  enables offloading for checksums on receive.  If unsure, say Y.
--
--config SGI_IOC3_ETH_HW_TX_CSUM
--	bool "Transmit hardware checksums"
--	depends on SGI_IOC3_ETH && INET
--	default y
-+config MIPS_SIM_NET
-+	tristate "MIPS simulator Network device (EXPERIMENTAL)"
-+	depends on NETDEVICES && MIPS_SIM && EXPERIMENTAL
- 	help
--	  The SGI IOC3 network adapter supports TCP and UDP checksums in
--	  hardware to offload processing of these checksums from the CPU.  At
--	  the moment only acceleration of IPv4 is supported.  This option
--	  enables offloading for checksums on transmit.  If unsure, say Y.
-+	  The MIPSNET device is a simple Ethernet network device which is
-+	  emulated by the MIPS Simulator.
-+	  If you are not using a MIPSsim or are unsure, say N.
- 
- config MIPS_SIM_NET
- 	tristate "MIPS simulator Network device (EXPERIMENTAL)"
-@@ -1993,6 +1985,10 @@
- 
- 	  If in doubt, say N.
- 
-+config NET_SB1250_MAC
-+	tristate "SB1250 Ethernet support"
-+	depends on SIBYTE_SB1xxx_SOC
-+
- config R8169_VLAN
- 	bool "VLAN support"
- 	depends on R8169 && VLAN_8021Q
-@@ -2195,8 +2191,8 @@
- 	select MII
- 	help
- 	  This driver supports the gigabit Ethernet on the Marvell MV643XX
--	  chipset which is used in the Momenco Ocelot C and Jaguar ATX and
--	  Pegasos II, amongst other PPC and MIPS boards.
-+	  chipset which is used in the Momenco Ocelot C Ocelot, Jaguar ATX
-+	  and Pegasos II, amongst other PPC and MIPS boards.
- 
- config MV643XX_ETH_0
- 	bool "MV-643XX Port 0"
-@@ -2219,6 +2215,20 @@
- 	  This enables support for Port 2 of the Marvell MV643XX Gigabit
- 	  Ethernet.
- 
-+config BIG_SUR_FE
-+	bool "PMC-Sierra TITAN Fast Ethernet Support"
-+	depends on NET_ETHERNET && PMC_BIG_SUR
-+	help
-+	  This enables support for the the integrated ethernet of
-+	  PMC-Sierra's Big Sur SoC.
-+
-+config TITAN_GE
-+	bool "PMC-Sierra TITAN Gigabit Ethernet Support"
-+	depends on PMC_YOSEMITE
-+	help
-+	  This enables support for the the integrated ethernet of
-+	  PMC-Sierra's Titan SoC.
-+
- endmenu
- 
- #
-diff -Naur linux-2.6.17.orig/drivers/net/Makefile linux-2.6.17/drivers/net/Makefile
---- linux-2.6.17.orig/drivers/net/Makefile	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/drivers/net/Makefile	2006-06-19 18:16:13.000000000 -0700
-@@ -111,6 +111,11 @@
- 
- obj-$(CONFIG_MV643XX_ETH) += mv643xx_eth.o
- 
-+obj-$(CONFIG_GALILEO_64240_ETH) += gt64240eth.o
-+obj-$(CONFIG_MV64340_ETH) += mv64340_eth.o
-+obj-$(CONFIG_BIG_SUR_FE) += big_sur_ge.o
-+obj-$(CONFIG_TITAN_GE) += titan_mdio.o titan_ge.o
-+
- obj-$(CONFIG_PPP) += ppp_generic.o slhc.o
- obj-$(CONFIG_PPP_ASYNC) += ppp_async.o
- obj-$(CONFIG_PPP_SYNC_TTY) += ppp_synctty.o
-diff -Naur linux-2.6.17.orig/drivers/net/sb1250-mac.c linux-2.6.17/drivers/net/sb1250-mac.c
---- linux-2.6.17.orig/drivers/net/sb1250-mac.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/drivers/net/sb1250-mac.c	2006-06-19 18:16:13.000000000 -0700
-@@ -156,6 +156,10 @@
- 
- #define NUMCACHEBLKS(x) (((x)+SMP_CACHE_BYTES-1)/SMP_CACHE_BYTES)
- 
-+#define SBMAC_READCSR(t)	__raw_readq((unsigned long)t)
-+#define SBMAC_WRITECSR(t,v)	__raw_writeq(v, (unsigned long)t)
-+
-+
- #define SBMAC_MAX_TXDESCR	32
- #define SBMAC_MAX_RXDESCR	32
- 
-@@ -2416,6 +2420,11 @@
- 			sc->sbm_dev->name);
- 	}
- 
-+	if (periph_rev >= 2) {
-+		printk(KERN_INFO "%s: enabling TCP rcv checksum\n",
-+			sc->sbm_dev->name);
-+	}
-+
- 	/*
- 	 * Display Ethernet address (this is called during the config
- 	 * process so we need to finish off the config message that
-diff -Naur linux-2.6.17.orig/drivers/net/titan_ge.c linux-2.6.17/drivers/net/titan_ge.c
---- linux-2.6.17.orig/drivers/net/titan_ge.c	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/drivers/net/titan_ge.c	2006-06-19 18:16:13.000000000 -0700
-@@ -0,0 +1,2071 @@
-+/*
-+ * drivers/net/titan_ge.c - Driver for Titan ethernet ports
-+ *
-+ * Copyright (C) 2003 PMC-Sierra Inc.
-+ * Author : Manish Lachwani (lachwani@pmc-sierra.com)
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * as published by the Free Software Foundation; either version 2
-+ * of the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
-+ */
-+
-+/*
-+ * The MAC unit of the Titan consists of the following:
-+ *
-+ * -> XDMA Engine to move data to from the memory to the MAC packet FIFO
-+ * -> FIFO is where the incoming and outgoing data is placed
-+ * -> TRTG is the unit that pulls the data from the FIFO for Tx and pushes
-+ *    the data into the FIFO for Rx
-+ * -> TMAC is the outgoing MAC interface and RMAC is the incoming.
-+ * -> AFX is the address filtering block
-+ * -> GMII block to communicate with the PHY
-+ *
-+ * Rx will look like the following:
-+ * GMII --> RMAC --> AFX --> TRTG --> Rx FIFO --> XDMA --> CPU memory
-+ *
-+ * Tx will look like the following:
-+ * CPU memory --> XDMA --> Tx FIFO --> TRTG --> TMAC --> GMII
-+ *
-+ * The Titan driver has support for the following performance features:
-+ * -> Rx side checksumming
-+ * -> Jumbo Frames
-+ * -> Interrupt Coalscing
-+ * -> Rx NAPI
-+ * -> SKB Recycling
-+ * -> Transmit/Receive descriptors in SRAM
-+ * -> Fast routing for IP forwarding
-+ */
-+
-+#include <linux/config.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/sched.h>
-+#include <linux/ioport.h>
-+#include <linux/interrupt.h>
-+#include <linux/slab.h>
-+#include <linux/string.h>
-+#include <linux/errno.h>
-+#include <linux/ip.h>
-+#include <linux/init.h>
-+#include <linux/in.h>
-+#include <linux/platform_device.h>
-+#include <linux/netdevice.h>
-+#include <linux/etherdevice.h>
-+#include <linux/skbuff.h>
-+#include <linux/mii.h>
-+#include <linux/delay.h>
-+#include <linux/skbuff.h>
-+#include <linux/prefetch.h>
-+
-+/* For MII specifc registers, titan_mdio.h should be included */
-+#include <net/ip.h>
-+
-+#include <asm/bitops.h>
-+#include <asm/io.h>
-+#include <asm/types.h>
-+#include <asm/pgtable.h>
-+#include <asm/system.h>
-+#include <asm/titan_dep.h>
-+
-+#include "titan_ge.h"
-+#include "titan_mdio.h"
-+
-+/* Static Function Declarations	 */
-+static int titan_ge_eth_open(struct net_device *);
-+static void titan_ge_eth_stop(struct net_device *);
-+static struct net_device_stats *titan_ge_get_stats(struct net_device *);
-+static int titan_ge_init_rx_desc_ring(titan_ge_port_info *, int, int,
-+				      unsigned long, unsigned long,
-+				      unsigned long);
-+static int titan_ge_init_tx_desc_ring(titan_ge_port_info *, int,
-+				      unsigned long, unsigned long);
-+
-+static int titan_ge_open(struct net_device *);
-+static int titan_ge_start_xmit(struct sk_buff *, struct net_device *);
-+static int titan_ge_stop(struct net_device *);
-+
-+static unsigned long titan_ge_tx_coal(unsigned long, int);
-+
-+static void titan_ge_port_reset(unsigned int);
-+static int titan_ge_free_tx_queue(titan_ge_port_info *);
-+static int titan_ge_rx_task(struct net_device *, titan_ge_port_info *);
-+static int titan_ge_port_start(struct net_device *, titan_ge_port_info *);
-+
-+static int titan_ge_return_tx_desc(titan_ge_port_info *, int);
-+
-+/*
-+ * Some configuration for the FIFO and the XDMA channel needs
-+ * to be done only once for all the ports. This flag controls
-+ * that
-+ */
-+static unsigned long config_done;
-+
-+/*
-+ * One time out of memory flag
-+ */
-+static unsigned int oom_flag;
-+
-+static int titan_ge_poll(struct net_device *netdev, int *budget);
-+
-+static int titan_ge_receive_queue(struct net_device *, unsigned int);
-+
-+static struct platform_device *titan_ge_device[3];
-+
-+/* MAC Address */
-+extern unsigned char titan_ge_mac_addr_base[6];
-+
-+unsigned long titan_ge_base;
-+static unsigned long titan_ge_sram;
-+
-+static char titan_string[] = "titan";
-+
-+/*
-+ * The Titan GE has two alignment requirements:
-+ * -> skb->data to be cacheline aligned (32 byte)
-+ * -> IP header alignment to 16 bytes
-+ *
-+ * The latter is not implemented. So, that results in an extra copy on
-+ * the Rx. This is a big performance hog. For the former case, the
-+ * dev_alloc_skb() has been replaced with titan_ge_alloc_skb(). The size
-+ * requested is calculated:
-+ *
-+ * Ethernet Frame Size : 1518
-+ * Ethernet Header     : 14
-+ * Future Titan change for IP header alignment : 2
-+ *
-+ * Hence, we allocate (1518 + 14 + 2+ 64) = 1580 bytes.  For IP header
-+ * alignment, we use skb_reserve().
-+ */
-+
-+#define ALIGNED_RX_SKB_ADDR(addr) \
-+	((((unsigned long)(addr) + (64UL - 1UL)) \
-+	& ~(64UL - 1UL)) - (unsigned long)(addr))
-+
-+#define titan_ge_alloc_skb(__length, __gfp_flags) \
-+({      struct sk_buff *__skb; \
-+	__skb = alloc_skb((__length) + 64, (__gfp_flags)); \
-+	if(__skb) { \
-+		int __offset = (int) ALIGNED_RX_SKB_ADDR(__skb->data); \
-+		if(__offset) \
-+			skb_reserve(__skb, __offset); \
-+	} \
-+	__skb; \
-+})
-+
-+/*
-+ * Configure the GMII block of the Titan based on what the PHY tells us
-+ */
-+static void titan_ge_gmii_config(int port_num)
-+{
-+	unsigned int reg_data = 0, phy_reg;
-+	int err;
-+
-+	err = titan_ge_mdio_read(port_num, TITAN_GE_MDIO_PHY_STATUS, &phy_reg);
-+
-+	if (err == TITAN_GE_MDIO_ERROR) {
-+		printk(KERN_ERR
-+		       "Could not read PHY control register 0x11 \n");
-+		printk(KERN_ERR
-+			"Setting speed to 1000 Mbps and Duplex to Full \n");
-+
-+		return;
-+	}
-+
-+	err = titan_ge_mdio_write(port_num, TITAN_GE_MDIO_PHY_IE, 0);
-+
-+	if (phy_reg & 0x8000) {
-+		if (phy_reg & 0x2000) {
-+			/* Full Duplex and 1000 Mbps */
-+			TITAN_GE_WRITE((TITAN_GE_GMII_CONFIG_MODE +
-+					(port_num << 12)), 0x201);
-+		}  else {
-+			/* Half Duplex and 1000 Mbps */
-+			TITAN_GE_WRITE((TITAN_GE_GMII_CONFIG_MODE +
-+					(port_num << 12)), 0x2201);
-+			}
-+	}
-+	if (phy_reg & 0x4000) {
-+		if (phy_reg & 0x2000) {
-+			/* Full Duplex and 100 Mbps */
-+			TITAN_GE_WRITE((TITAN_GE_GMII_CONFIG_MODE +
-+					(port_num << 12)), 0x100);
-+		} else {
-+			/* Half Duplex and 100 Mbps */
-+			TITAN_GE_WRITE((TITAN_GE_GMII_CONFIG_MODE +
-+					(port_num << 12)), 0x2100);
-+		}
-+	}
-+	reg_data = TITAN_GE_READ(TITAN_GE_GMII_CONFIG_GENERAL +
-+				(port_num << 12));
-+	reg_data |= 0x3;
-+	TITAN_GE_WRITE((TITAN_GE_GMII_CONFIG_GENERAL +
-+			(port_num << 12)), reg_data);
-+}
-+
-+/*
-+ * Enable the TMAC if it is not
-+ */
-+static void titan_ge_enable_tx(unsigned int port_num)
-+{
-+	unsigned long reg_data;
-+
-+	reg_data = TITAN_GE_READ(TITAN_GE_TMAC_CONFIG_1 + (port_num << 12));
-+	if (!(reg_data & 0x8000)) {
-+		printk("TMAC disabled for port %d!! \n", port_num);
-+
-+		reg_data |= 0x0001;	/* Enable TMAC */
-+		reg_data |= 0x4000;	/* CRC Check Enable */
-+		reg_data |= 0x2000;	/* Padding enable */
-+		reg_data |= 0x0800;	/* CRC Add enable */
-+		reg_data |= 0x0080;	/* PAUSE frame */
-+
-+		TITAN_GE_WRITE((TITAN_GE_TMAC_CONFIG_1 +
-+				(port_num << 12)), reg_data);
-+	}
-+}
-+
-+/*
-+ * Tx Timeout function
-+ */
-+static void titan_ge_tx_timeout(struct net_device *netdev)
-+{
-+	titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
-+
-+	printk(KERN_INFO "%s: TX timeout  ", netdev->name);
-+	printk(KERN_INFO "Resetting card \n");
-+
-+	/* Do the reset outside of interrupt context */
-+	schedule_work(&titan_ge_eth->tx_timeout_task);
-+}
-+
-+/*
-+ * Update the AFX tables for UC and MC for slice 0 only
-+ */
-+static void titan_ge_update_afx(titan_ge_port_info * titan_ge_eth)
-+{
-+	int port = titan_ge_eth->port_num;
-+	unsigned int i;
-+	volatile unsigned long reg_data = 0;
-+	u8 p_addr[6];
-+
-+	memcpy(p_addr, titan_ge_eth->port_mac_addr, 6);
-+
-+	/* Set the MAC address here for TMAC and RMAC */
-+	TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_HI + (port << 12)),
-+		       ((p_addr[5] << 8) | p_addr[4]));
-+	TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_MID + (port << 12)),
-+		       ((p_addr[3] << 8) | p_addr[2]));
-+	TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_LOW + (port << 12)),
-+		       ((p_addr[1] << 8) | p_addr[0]));
-+
-+	TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_HI + (port << 12)),
-+		       ((p_addr[5] << 8) | p_addr[4]));
-+	TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_MID + (port << 12)),
-+		       ((p_addr[3] << 8) | p_addr[2]));
-+	TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_LOW + (port << 12)),
-+		       ((p_addr[1] << 8) | p_addr[0]));
-+
-+	TITAN_GE_WRITE((0x112c | (port << 12)), 0x1);
-+	/* Configure the eight address filters */
-+	for (i = 0; i < 8; i++) {
-+		/* Select each of the eight filters */
-+		TITAN_GE_WRITE((TITAN_GE_AFX_ADDRS_FILTER_CTRL_2 +
-+				(port << 12)), i);
-+
-+		/* Configure the match */
-+		reg_data = 0x9;	/* Forward Enable Bit */
-+		TITAN_GE_WRITE((TITAN_GE_AFX_ADDRS_FILTER_CTRL_0 +
-+				(port << 12)), reg_data);
-+
-+		/* Finally, AFX Exact Match Address Registers */
-+		TITAN_GE_WRITE((TITAN_GE_AFX_EXACT_MATCH_LOW + (port << 12)),
-+			       ((p_addr[1] << 8) | p_addr[0]));
-+		TITAN_GE_WRITE((TITAN_GE_AFX_EXACT_MATCH_MID + (port << 12)),
-+			       ((p_addr[3] << 8) | p_addr[2]));
-+		TITAN_GE_WRITE((TITAN_GE_AFX_EXACT_MATCH_HIGH + (port << 12)),
-+			       ((p_addr[5] << 8) | p_addr[4]));
-+
-+		/* VLAN id set to 0 */
-+		TITAN_GE_WRITE((TITAN_GE_AFX_EXACT_MATCH_VID +
-+				(port << 12)), 0);
-+	}
-+}
-+
-+/*
-+ * Actual Routine to reset the adapter when the timeout occurred
-+ */
-+static void titan_ge_tx_timeout_task(struct net_device *netdev)
-+{
-+	titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
-+	int port = titan_ge_eth->port_num;
-+
-+	printk("Titan GE: Transmit timed out. Resetting ... \n");
-+
-+	/* Dump debug info */
-+	printk(KERN_ERR "TRTG cause : %x \n",
-+			TITAN_GE_READ(0x100c + (port << 12)));
-+
-+	/* Fix this for the other ports */
-+	printk(KERN_ERR "FIFO cause : %x \n", TITAN_GE_READ(0x482c));
-+	printk(KERN_ERR "IE cause : %x \n", TITAN_GE_READ(0x0040));
-+	printk(KERN_ERR "XDMA GDI ERROR : %x \n",
-+			TITAN_GE_READ(0x5008 + (port << 8)));
-+	printk(KERN_ERR "CHANNEL ERROR: %x \n",
-+			TITAN_GE_READ(TITAN_GE_CHANNEL0_INTERRUPT
-+						+ (port << 8)));
-+
-+	netif_device_detach(netdev);
-+	titan_ge_port_reset(titan_ge_eth->port_num);
-+	titan_ge_port_start(netdev, titan_ge_eth);
-+	netif_device_attach(netdev);
-+}
-+
-+/*
-+ * Change the MTU of the Ethernet Device
-+ */
-+static int titan_ge_change_mtu(struct net_device *netdev, int new_mtu)
-+{
-+	titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
-+	unsigned long flags;
-+
-+	if ((new_mtu > 9500) || (new_mtu < 64))
-+		return -EINVAL;
-+
-+	spin_lock_irqsave(&titan_ge_eth->lock, flags);
-+
-+	netdev->mtu = new_mtu;
-+
-+	/* Now we have to reopen the interface so that SKBs with the new
-+	 * size will be allocated */
-+
-+	if (netif_running(netdev)) {
-+		titan_ge_eth_stop(netdev);
-+
-+		if (titan_ge_eth_open(netdev) != TITAN_OK) {
-+			printk(KERN_ERR
-+			       "%s: Fatal error on opening device\n",
-+			       netdev->name);
-+			spin_unlock_irqrestore(&titan_ge_eth->lock, flags);
-+			return -1;
-+		}
-+	}
-+
-+	spin_unlock_irqrestore(&titan_ge_eth->lock, flags);
-+	return 0;
-+}
-+
-+/*
-+ * Titan Gbe Interrupt Handler. All the three ports send interrupt to one line
-+ * only. Once an interrupt is triggered, figure out the port and then check
-+ * the channel.
-+ */
-+static irqreturn_t titan_ge_int_handler(int irq, void *dev_id,
-+	struct pt_regs *regs)
-+{
-+	struct net_device *netdev = (struct net_device *) dev_id;
-+	titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
-+	unsigned int port_num = titan_ge_eth->port_num;
-+	unsigned int reg_data;
-+	unsigned int eth_int_cause_error = 0, is;
-+	unsigned long eth_int_cause1;
-+	int err = 0;
-+#ifdef CONFIG_SMP
-+	unsigned long eth_int_cause2;
-+#endif
-+
-+	/* Ack the CPU interrupt */
-+	switch (port_num) {
-+	case 0:
-+		is = OCD_READ(RM9000x2_OCD_INTP0STATUS1);
-+		OCD_WRITE(RM9000x2_OCD_INTP0CLEAR1, is);
-+
-+#ifdef CONFIG_SMP
-+		is = OCD_READ(RM9000x2_OCD_INTP1STATUS1);
-+		OCD_WRITE(RM9000x2_OCD_INTP1CLEAR1, is);
-+#endif
-+		break;
-+
-+	case 1:
-+		is = OCD_READ(RM9000x2_OCD_INTP0STATUS0);
-+		OCD_WRITE(RM9000x2_OCD_INTP0CLEAR0, is);
-+
-+#ifdef CONFIG_SMP
-+		is = OCD_READ(RM9000x2_OCD_INTP1STATUS0);
-+		OCD_WRITE(RM9000x2_OCD_INTP1CLEAR0, is);
-+#endif
-+		break;
-+
-+	case 2:
-+		is = OCD_READ(RM9000x2_OCD_INTP0STATUS4);
-+		OCD_WRITE(RM9000x2_OCD_INTP0CLEAR4, is);
-+
-+#ifdef CONFIG_SMP
-+		is = OCD_READ(RM9000x2_OCD_INTP1STATUS4);
-+		OCD_WRITE(RM9000x2_OCD_INTP1CLEAR4, is);
-+#endif
-+	}
-+
-+	eth_int_cause1 = TITAN_GE_READ(TITAN_GE_INTR_XDMA_CORE_A);
-+#ifdef CONFIG_SMP
-+	eth_int_cause2 = TITAN_GE_READ(TITAN_GE_INTR_XDMA_CORE_B);
-+#endif
-+
-+	/* Spurious interrupt */
-+#ifdef CONFIG_SMP
-+	if ( (eth_int_cause1 == 0) && (eth_int_cause2 == 0)) {
-+#else
-+	if (eth_int_cause1 == 0) {
-+#endif
-+		eth_int_cause_error = TITAN_GE_READ(TITAN_GE_CHANNEL0_INTERRUPT +
-+					(port_num << 8));
-+
-+		if (eth_int_cause_error == 0)
-+			return IRQ_NONE;
-+	}
-+
-+	/* Handle Tx first. No need to ack interrupts */
-+#ifdef CONFIG_SMP
-+	if ( (eth_int_cause1 & 0x20202) ||
-+		(eth_int_cause2 & 0x20202) )
-+#else
-+	if (eth_int_cause1 & 0x20202)
-+#endif
-+		titan_ge_free_tx_queue(titan_ge_eth);
-+
-+	/* Handle the Rx next */
-+#ifdef CONFIG_SMP
-+	if ( (eth_int_cause1 & 0x10101) ||
-+		(eth_int_cause2 & 0x10101)) {
-+#else
-+	if (eth_int_cause1 & 0x10101) {
-+#endif
-+		if (netif_rx_schedule_prep(netdev)) {
-+			unsigned int ack;
-+
-+			ack = TITAN_GE_READ(TITAN_GE_INTR_XDMA_IE);
-+			/* Disable Tx and Rx both */
-+			if (port_num == 0)
-+				ack &= ~(0x3);
-+			if (port_num == 1)
-+				ack &= ~(0x300);
-+
-+			if (port_num == 2)
-+				ack &= ~(0x30000);
-+
-+			/* Interrupts have been disabled */
-+			TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_IE, ack);
-+
-+			__netif_rx_schedule(netdev);
-+		}
-+	}
-+
-+	/* Handle error interrupts */
-+	if (eth_int_cause_error && (eth_int_cause_error != 0x2)) {
-+		printk(KERN_ERR
-+			"XDMA Channel Error : %x  on port %d\n",
-+			eth_int_cause_error, port_num);
-+
-+		printk(KERN_ERR
-+			"XDMA GDI Hardware error : %x  on port %d\n",
-+			TITAN_GE_READ(0x5008 + (port_num << 8)), port_num);
-+
-+		printk(KERN_ERR
-+			"XDMA currently has %d Rx descriptors \n",
-+			TITAN_GE_READ(0x5048 + (port_num << 8)));
-+
-+		printk(KERN_ERR
-+			"XDMA currently has prefetcted %d Rx descriptors \n",
-+			TITAN_GE_READ(0x505c + (port_num << 8)));
-+
-+		TITAN_GE_WRITE((TITAN_GE_CHANNEL0_INTERRUPT +
-+			       (port_num << 8)), eth_int_cause_error);
-+	}
-+
-+	/*
-+	 * PHY interrupt to inform abt the changes. Reading the
-+	 * PHY Status register will clear the interrupt
-+	 */
-+	if ((!(eth_int_cause1 & 0x30303)) &&
-+		(eth_int_cause_error == 0)) {
-+		err =
-+		    titan_ge_mdio_read(port_num,
-+			       TITAN_GE_MDIO_PHY_IS, &reg_data);
-+
-+		if (reg_data & 0x0400) {
-+			/* Link status change */
-+			titan_ge_mdio_read(port_num,
-+				   TITAN_GE_MDIO_PHY_STATUS, &reg_data);
-+			if (!(reg_data & 0x0400)) {
-+				/* Link is down */
-+				netif_carrier_off(netdev);
-+				netif_stop_queue(netdev);
-+			} else {
-+				/* Link is up */
-+				netif_carrier_on(netdev);
-+				netif_wake_queue(netdev);
-+
-+				/* Enable the queue */
-+				titan_ge_enable_tx(port_num);
-+			}
-+		}
-+	}
-+
-+	return IRQ_HANDLED;
-+}
-+
-+/*
-+ * Multicast and Promiscuous mode set. The
-+ * set_multi entry point is called whenever the
-+ * multicast address list or the network interface
-+ * flags are updated.
-+ */
-+static void titan_ge_set_multi(struct net_device *netdev)
-+{
-+	titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
-+	unsigned int port_num = titan_ge_eth->port_num;
-+	unsigned long reg_data;
-+
-+	reg_data = TITAN_GE_READ(TITAN_GE_AFX_ADDRS_FILTER_CTRL_1 +
-+				(port_num << 12));
-+
-+	if (netdev->flags & IFF_PROMISC) {
-+		reg_data |= 0x2;
-+	}
-+	else if (netdev->flags & IFF_ALLMULTI) {
-+		reg_data |= 0x01;
-+		reg_data |= 0x400; /* Use the 64-bit Multicast Hash bin */
-+	}
-+	else {
-+		reg_data = 0x2;
-+	}
-+
-+	TITAN_GE_WRITE((TITAN_GE_AFX_ADDRS_FILTER_CTRL_1 +
-+			(port_num << 12)), reg_data);
-+	if (reg_data & 0x01) {
-+		TITAN_GE_WRITE((TITAN_GE_AFX_MULTICAST_HASH_LOW +
-+				(port_num << 12)), 0xffff);
-+		TITAN_GE_WRITE((TITAN_GE_AFX_MULTICAST_HASH_MIDLOW +
-+				(port_num << 12)), 0xffff);
-+		TITAN_GE_WRITE((TITAN_GE_AFX_MULTICAST_HASH_MIDHI +
-+				(port_num << 12)), 0xffff);
-+		TITAN_GE_WRITE((TITAN_GE_AFX_MULTICAST_HASH_HI +
-+				(port_num << 12)), 0xffff);
-+	}
-+}
-+
-+/*
-+ * Open the network device
-+ */
-+static int titan_ge_open(struct net_device *netdev)
-+{
-+	titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
-+	unsigned int port_num = titan_ge_eth->port_num;
-+	unsigned int irq = TITAN_ETH_PORT_IRQ - port_num;
-+	int retval;
-+
-+	retval = request_irq(irq, titan_ge_int_handler,
-+		     SA_INTERRUPT | SA_SAMPLE_RANDOM , netdev->name, netdev);
-+
-+	if (retval != 0) {
-+		printk(KERN_ERR "Cannot assign IRQ number to TITAN GE \n");
-+		return -1;
-+	}
-+
-+	netdev->irq = irq;
-+	printk(KERN_INFO "Assigned IRQ %d to port %d\n", irq, port_num);
-+
-+	spin_lock_irq(&(titan_ge_eth->lock));
-+
-+	if (titan_ge_eth_open(netdev) != TITAN_OK) {
-+		spin_unlock_irq(&(titan_ge_eth->lock));
-+		printk("%s: Error opening interface \n", netdev->name);
-+		free_irq(netdev->irq, netdev);
-+		return -EBUSY;
-+	}
-+
-+	spin_unlock_irq(&(titan_ge_eth->lock));
-+
-+	return 0;
-+}
-+
-+/*
-+ * Allocate the SKBs for the Rx ring. Also used
-+ * for refilling the queue
-+ */
-+static int titan_ge_rx_task(struct net_device *netdev,
-+				titan_ge_port_info *titan_ge_port)
-+{
-+	struct device *device = &titan_ge_device[titan_ge_port->port_num]->dev;
-+	volatile titan_ge_rx_desc *rx_desc;
-+	struct sk_buff *skb;
-+	int rx_used_desc;
-+	int count = 0;
-+
-+	while (titan_ge_port->rx_ring_skbs < titan_ge_port->rx_ring_size) {
-+
-+	/* First try to get the skb from the recycler */
-+#ifdef TITAN_GE_JUMBO_FRAMES
-+		skb = titan_ge_alloc_skb(TITAN_GE_JUMBO_BUFSIZE, GFP_ATOMIC);
-+#else
-+		skb = titan_ge_alloc_skb(TITAN_GE_STD_BUFSIZE, GFP_ATOMIC);
-+#endif
-+		if (unlikely(!skb)) {
-+			/* OOM, set the flag */
-+			printk("OOM \n");
-+			oom_flag = 1;
-+			break;
-+		}
-+		count++;
-+		skb->dev = netdev;
-+
-+		titan_ge_port->rx_ring_skbs++;
-+
-+		rx_used_desc = titan_ge_port->rx_used_desc_q;
-+		rx_desc = &(titan_ge_port->rx_desc_area[rx_used_desc]);
-+
-+#ifdef TITAN_GE_JUMBO_FRAMES
-+		rx_desc->buffer_addr = dma_map_single(device, skb->data,
-+				TITAN_GE_JUMBO_BUFSIZE - 2, DMA_FROM_DEVICE);
-+#else
-+		rx_desc->buffer_addr = dma_map_single(device, skb->data,
-+				TITAN_GE_STD_BUFSIZE - 2, DMA_FROM_DEVICE);
-+#endif
-+
-+		titan_ge_port->rx_skb[rx_used_desc] = skb;
-+		rx_desc->cmd_sts = TITAN_GE_RX_BUFFER_OWNED;
-+
-+		titan_ge_port->rx_used_desc_q =
-+			(rx_used_desc + 1) % TITAN_GE_RX_QUEUE;
-+	}
-+
-+	return count;
-+}
-+
-+/*
-+ * Actual init of the Tital GE port. There is one register for
-+ * the channel configuration
-+ */
-+static void titan_port_init(struct net_device *netdev,
-+			    titan_ge_port_info * titan_ge_eth)
-+{
-+	unsigned long reg_data;
-+
-+	titan_ge_port_reset(titan_ge_eth->port_num);
-+
-+	/* First reset the TMAC */
-+	reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG);
-+	reg_data |= 0x80000000;
-+	TITAN_GE_WRITE(TITAN_GE_CHANNEL0_CONFIG, reg_data);
-+
-+	udelay(30);
-+
-+	reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG);
-+	reg_data &= ~(0xc0000000);
-+	TITAN_GE_WRITE(TITAN_GE_CHANNEL0_CONFIG, reg_data);
-+
-+	/* Now reset the RMAC */
-+	reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG);
-+	reg_data |= 0x00080000;
-+	TITAN_GE_WRITE(TITAN_GE_CHANNEL0_CONFIG, reg_data);
-+
-+	udelay(30);
-+
-+	reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG);
-+	reg_data &= ~(0x000c0000);
-+	TITAN_GE_WRITE(TITAN_GE_CHANNEL0_CONFIG, reg_data);
-+}
-+
-+/*
-+ * Start the port. All the hardware specific configuration
-+ * for the XDMA, Tx FIFO, Rx FIFO, TMAC, RMAC, TRTG and AFX
-+ * go here
-+ */
-+static int titan_ge_port_start(struct net_device *netdev,
-+				titan_ge_port_info * titan_port)
-+{
-+	volatile unsigned long reg_data, reg_data1;
-+	int port_num = titan_port->port_num;
-+	int count = 0;
-+	unsigned long reg_data_1;
-+
-+	if (config_done == 0) {
-+		reg_data = TITAN_GE_READ(0x0004);
-+		reg_data |= 0x100;
-+		TITAN_GE_WRITE(0x0004, reg_data);
-+
-+		reg_data &= ~(0x100);
-+		TITAN_GE_WRITE(0x0004, reg_data);
-+
-+		/* Turn on GMII/MII mode and turn off TBI mode */
-+		reg_data = TITAN_GE_READ(TITAN_GE_TSB_CTRL_1);
-+		reg_data |= 0x00000700;
-+		reg_data &= ~(0x00800000); /* Fencing */
-+
-+		TITAN_GE_WRITE(0x000c, 0x00001100);
-+
-+		TITAN_GE_WRITE(TITAN_GE_TSB_CTRL_1, reg_data);
-+
-+		/* Set the CPU Resource Limit register */
-+		TITAN_GE_WRITE(0x00f8, 0x8);
-+
-+		/* Be conservative when using the BIU buffers */
-+		TITAN_GE_WRITE(0x0068, 0x4);
-+	}
-+
-+	titan_port->tx_threshold = 0;
-+	titan_port->rx_threshold = 0;
-+
-+	/* We need to write the descriptors for Tx and Rx */
-+	TITAN_GE_WRITE((TITAN_GE_CHANNEL0_TX_DESC + (port_num << 8)),
-+		       (unsigned long) titan_port->tx_dma);
-+	TITAN_GE_WRITE((TITAN_GE_CHANNEL0_RX_DESC + (port_num << 8)),
-+		       (unsigned long) titan_port->rx_dma);
-+
-+	if (config_done == 0) {
-+		/* Step 1:  XDMA config	*/
-+		reg_data = TITAN_GE_READ(TITAN_GE_XDMA_CONFIG);
-+		reg_data &= ~(0x80000000);      /* clear reset */
-+		reg_data |= 0x1 << 29;	/* sparse tx descriptor spacing */
-+		reg_data |= 0x1 << 28;	/* sparse rx descriptor spacing */
-+		reg_data |= (0x1 << 23) | (0x1 << 24);  /* Descriptor Coherency */
-+		reg_data |= (0x1 << 21) | (0x1 << 22);  /* Data Coherency */
-+		TITAN_GE_WRITE(TITAN_GE_XDMA_CONFIG, reg_data);
-+	}
-+
-+	/* IR register for the XDMA */
-+	reg_data = TITAN_GE_READ(TITAN_GE_GDI_INTERRUPT_ENABLE + (port_num << 8));
-+	reg_data |= 0x80068000; /* No Rx_OOD */
-+	TITAN_GE_WRITE((TITAN_GE_GDI_INTERRUPT_ENABLE + (port_num << 8)), reg_data);
-+
-+	/* Start the Tx and Rx XDMA controller */
-+	reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG + (port_num << 8));
-+	reg_data &= 0x4fffffff;     /* Clear tx reset */
-+	reg_data &= 0xfff4ffff;     /* Clear rx reset */
-+
-+#ifdef TITAN_GE_JUMBO_FRAMES
-+	reg_data |= 0xa0 | 0x30030000;
-+#else
-+	reg_data |= 0x40 | 0x20030000;
-+#endif
-+
-+#ifndef CONFIG_SMP
-+	reg_data &= ~(0x10);
-+	reg_data |= 0x0f; /* All of the packet */
-+#endif
-+
-+	TITAN_GE_WRITE((TITAN_GE_CHANNEL0_CONFIG + (port_num << 8)), reg_data);
-+
-+	/* Rx desc count */
-+	count = titan_ge_rx_task(netdev, titan_port);
-+	TITAN_GE_WRITE((0x5048 + (port_num << 8)), count);
-+	count = TITAN_GE_READ(0x5048 + (port_num << 8));
-+
-+	udelay(30);
-+
-+	/*
-+	 * Step 2:  Configure the SDQPF, i.e. FIFO
-+	 */
-+	if (config_done == 0) {
-+		reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_RXFIFO_CTL);
-+		reg_data = 0x1;
-+		TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_CTL, reg_data);
-+		reg_data &= ~(0x1);
-+		TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_CTL, reg_data);
-+		reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_RXFIFO_CTL);
-+		TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_CTL, reg_data);
-+
-+		reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_TXFIFO_CTL);
-+		reg_data = 0x1;
-+		TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_CTL, reg_data);
-+		reg_data &= ~(0x1);
-+		TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_CTL, reg_data);
-+		reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_TXFIFO_CTL);
-+		TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_CTL, reg_data);
-+	}
-+	/*
-+	 * Enable RX FIFO 0, 4 and 8
-+	 */
-+	if (port_num == 0) {
-+		reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_RXFIFO_0);
-+
-+		reg_data |= 0x100000;
-+		reg_data |= (0xff << 10);
-+
-+		TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_0, reg_data);
-+		/*
-+		 * BAV2,BAV and DAV settings for the Rx FIFO
-+		 */
-+		reg_data1 = TITAN_GE_READ(0x4844);
-+		reg_data1 |= ( (0x10 << 20) | (0x10 << 10) | 0x1);
-+		TITAN_GE_WRITE(0x4844, reg_data1);
-+
-+		reg_data &= ~(0x00100000);
-+		reg_data |= 0x200000;
-+
-+		TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_0, reg_data);
-+
-+		reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_TXFIFO_0);
-+		reg_data |= 0x100000;
-+
-+		TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_0, reg_data);
-+
-+		reg_data |= (0xff << 10);
-+
-+		TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_0, reg_data);
-+
-+		/*
-+		 * BAV2, BAV and DAV settings for the Tx FIFO
-+		 */
-+		reg_data1 = TITAN_GE_READ(0x4944);
-+		reg_data1 = ( (0x1 << 20) | (0x1 << 10) | 0x10);
-+
-+		TITAN_GE_WRITE(0x4944, reg_data1);
-+
-+		reg_data &= ~(0x00100000);
-+		reg_data |= 0x200000;
-+
-+		TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_0, reg_data);
-+
-+	}
-+
-+	if (port_num == 1) {
-+		reg_data = TITAN_GE_READ(0x4870);
-+
-+		reg_data |= 0x100000;
-+		reg_data |= (0xff << 10) | (0xff + 1);
-+
-+		TITAN_GE_WRITE(0x4870, reg_data);
-+		/*
-+		 * BAV2,BAV and DAV settings for the Rx FIFO
-+		 */
-+		reg_data1 = TITAN_GE_READ(0x4874);
-+		reg_data1 |= ( (0x10 << 20) | (0x10 << 10) | 0x1);
-+		TITAN_GE_WRITE(0x4874, reg_data1);
-+
-+		reg_data &= ~(0x00100000);
-+		reg_data |= 0x200000;
-+
-+		TITAN_GE_WRITE(0x4870, reg_data);
-+
-+		reg_data = TITAN_GE_READ(0x494c);
-+		reg_data |= 0x100000;
-+
-+		TITAN_GE_WRITE(0x494c, reg_data);
-+		reg_data |= (0xff << 10) | (0xff + 1);
-+		TITAN_GE_WRITE(0x494c, reg_data);
-+
-+		/*
-+		 * BAV2, BAV and DAV settings for the Tx FIFO
-+		 */
-+		reg_data1 = TITAN_GE_READ(0x4950);
-+		reg_data1 = ( (0x1 << 20) | (0x1 << 10) | 0x10);
-+
-+		TITAN_GE_WRITE(0x4950, reg_data1);
-+
-+		reg_data &= ~(0x00100000);
-+		reg_data |= 0x200000;
-+
-+		TITAN_GE_WRITE(0x494c, reg_data);
-+	}
-+
-+	/*
-+	 * Titan 1.2 revision does support port #2
-+	 */
-+	if (port_num == 2) {
-+		/*
-+		 * Put the descriptors in the SRAM
-+		 */
-+		reg_data = TITAN_GE_READ(0x48a0);
-+
-+		reg_data |= 0x100000;
-+		reg_data |= (0xff << 10) | (2*(0xff + 1));
-+
-+		TITAN_GE_WRITE(0x48a0, reg_data);
-+		/*
-+		 * BAV2,BAV and DAV settings for the Rx FIFO
-+		 */
-+		reg_data1 = TITAN_GE_READ(0x48a4);
-+		reg_data1 |= ( (0x10 << 20) | (0x10 << 10) | 0x1);
-+		TITAN_GE_WRITE(0x48a4, reg_data1);
-+
-+		reg_data &= ~(0x00100000);
-+		reg_data |= 0x200000;
-+
-+		TITAN_GE_WRITE(0x48a0, reg_data);
-+		
-+		reg_data = TITAN_GE_READ(0x4958);
-+		reg_data |= 0x100000;
-+
-+		TITAN_GE_WRITE(0x4958, reg_data);
-+		reg_data |= (0xff << 10) | (2*(0xff + 1));
-+		TITAN_GE_WRITE(0x4958, reg_data);
-+
-+		/*
-+		 * BAV2, BAV and DAV settings for the Tx FIFO
-+		 */
-+		reg_data1 = TITAN_GE_READ(0x495c);
-+		reg_data1 = ( (0x1 << 20) | (0x1 << 10) | 0x10);
-+
-+		TITAN_GE_WRITE(0x495c, reg_data1);
-+
-+		reg_data &= ~(0x00100000);
-+		reg_data |= 0x200000;
-+
-+		TITAN_GE_WRITE(0x4958, reg_data);
-+	}
-+
-+	if (port_num == 2) {
-+		reg_data = TITAN_GE_READ(0x48a0);
-+
-+		reg_data |= 0x100000;
-+		reg_data |= (0xff << 10) | (2*(0xff + 1));
-+
-+		TITAN_GE_WRITE(0x48a0, reg_data);
-+		/*
-+		 * BAV2,BAV and DAV settings for the Rx FIFO
-+		 */
-+		reg_data1 = TITAN_GE_READ(0x48a4);
-+		reg_data1 |= ( (0x10 << 20) | (0x10 << 10) | 0x1);
-+		TITAN_GE_WRITE(0x48a4, reg_data1);
-+
-+		reg_data &= ~(0x00100000);
-+		reg_data |= 0x200000;
-+
-+		TITAN_GE_WRITE(0x48a0, reg_data);
-+
-+		reg_data = TITAN_GE_READ(0x4958);
-+		reg_data |= 0x100000;
-+
-+		TITAN_GE_WRITE(0x4958, reg_data);
-+		reg_data |= (0xff << 10) | (2*(0xff + 1));
-+		TITAN_GE_WRITE(0x4958, reg_data);
-+
-+		/*
-+		 * BAV2, BAV and DAV settings for the Tx FIFO
-+		 */
-+		reg_data1 = TITAN_GE_READ(0x495c);
-+		reg_data1 = ( (0x1 << 20) | (0x1 << 10) | 0x10);
-+
-+		TITAN_GE_WRITE(0x495c, reg_data1);
-+
-+		reg_data &= ~(0x00100000);
-+		reg_data |= 0x200000;
-+
-+		TITAN_GE_WRITE(0x4958, reg_data);
-+	}
-+
-+	/*
-+	 * Step 3:  TRTG block enable
-+	 */
-+	reg_data = TITAN_GE_READ(TITAN_GE_TRTG_CONFIG + (port_num << 12));
-+
-+	/*
-+	 * This is the 1.2 revision of the chip. It has fix for the
-+	 * IP header alignment. Now, the IP header begins at an
-+	 * aligned address and this wont need an extra copy in the
-+	 * driver. This performance drawback existed in the previous
-+	 * versions of the silicon
-+	 */
-+	reg_data_1 = TITAN_GE_READ(0x103c + (port_num << 12));
-+	reg_data_1 |= 0x40000000;
-+	TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1);
-+
-+	reg_data_1 |= 0x04000000;
-+	TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1);
-+
-+	mdelay(5);
-+
-+	reg_data_1 &= ~(0x04000000);
-+	TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1);
-+
-+	mdelay(5);
-+
-+	reg_data |= 0x0001;
-+	TITAN_GE_WRITE((TITAN_GE_TRTG_CONFIG + (port_num << 12)), reg_data);
-+
-+	/*
-+	 * Step 4:  Start the Tx activity
-+	 */
-+	TITAN_GE_WRITE((TITAN_GE_TMAC_CONFIG_2 + (port_num << 12)), 0xe197);
-+#ifdef TITAN_GE_JUMBO_FRAMES
-+	TITAN_GE_WRITE((0x1258 + (port_num << 12)), 0x4000);
-+#endif
-+	reg_data = TITAN_GE_READ(TITAN_GE_TMAC_CONFIG_1 + (port_num << 12));
-+	reg_data |= 0x0001;	/* Enable TMAC */
-+	reg_data |= 0x6c70;	/* PAUSE also set */
-+
-+	TITAN_GE_WRITE((TITAN_GE_TMAC_CONFIG_1 + (port_num << 12)), reg_data);
-+
-+	udelay(30);
-+
-+	/* Destination Address drop bit */
-+	reg_data = TITAN_GE_READ(TITAN_GE_RMAC_CONFIG_2 + (port_num << 12));
-+	reg_data |= 0x218;        /* DA_DROP bit and pause */
-+	TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_2 + (port_num << 12)), reg_data);
-+
-+	TITAN_GE_WRITE((0x1218 + (port_num << 12)), 0x3);
-+
-+#ifdef TITAN_GE_JUMBO_FRAMES
-+	TITAN_GE_WRITE((0x1208 + (port_num << 12)), 0x4000);
-+#endif
-+	/* Start the Rx activity */
-+	reg_data = TITAN_GE_READ(TITAN_GE_RMAC_CONFIG_1 + (port_num << 12));
-+	reg_data |= 0x0001;	/* RMAC Enable */
-+	reg_data |= 0x0010;	/* CRC Check enable */
-+	reg_data |= 0x0040;	/* Min Frame check enable */
-+	reg_data |= 0x4400;	/* Max Frame check enable */
-+
-+	TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_1 + (port_num << 12)), reg_data);
-+
-+	udelay(30);
-+
-+	/*
-+	 * Enable the Interrupts for Tx and Rx
-+	 */
-+	reg_data1 = TITAN_GE_READ(TITAN_GE_INTR_XDMA_IE);
-+
-+	if (port_num == 0) {
-+		reg_data1 |= 0x3;
-+#ifdef CONFIG_SMP
-+		TITAN_GE_WRITE(0x0038, 0x003);
-+#else
-+		TITAN_GE_WRITE(0x0038, 0x303);
-+#endif
-+	}
-+
-+	if (port_num == 1) {
-+		reg_data1 |= 0x300;
-+	}
-+
-+	if (port_num == 2)
-+		reg_data1 |= 0x30000;
-+
-+	TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_IE, reg_data1);
-+	TITAN_GE_WRITE(0x003c, 0x300);
-+
-+	if (config_done == 0) {
-+		TITAN_GE_WRITE(0x0024, 0x04000024);	/* IRQ vector */
-+		TITAN_GE_WRITE(0x0020, 0x000fb000);	/* INTMSG base */
-+	}
-+
-+	/* Priority */
-+	reg_data = TITAN_GE_READ(0x1038 + (port_num << 12));
-+	reg_data &= ~(0x00f00000);
-+	TITAN_GE_WRITE((0x1038 + (port_num << 12)), reg_data);
-+
-+	/* Step 5:  GMII config */
-+	titan_ge_gmii_config(port_num);
-+
-+	if (config_done == 0) {
-+		TITAN_GE_WRITE(0x1a80, 0);
-+		config_done = 1;
-+	}
-+
-+	return TITAN_OK;
-+}
-+
-+/*
-+ * Function to queue the packet for the Ethernet device
-+ */
-+static void titan_ge_tx_queue(titan_ge_port_info * titan_ge_eth,
-+				struct sk_buff * skb)
-+{
-+	struct device *device = &titan_ge_device[titan_ge_eth->port_num]->dev;
-+	unsigned int curr_desc = titan_ge_eth->tx_curr_desc_q;
-+	volatile titan_ge_tx_desc *tx_curr;
-+	int port_num = titan_ge_eth->port_num;
-+
-+	tx_curr = &(titan_ge_eth->tx_desc_area[curr_desc]);
-+	tx_curr->buffer_addr =
-+		dma_map_single(device, skb->data, skb_headlen(skb),
-+			       DMA_TO_DEVICE);
-+
-+	titan_ge_eth->tx_skb[curr_desc] = (struct sk_buff *) skb;
-+	tx_curr->buffer_len = skb_headlen(skb);
-+
-+	/* Last descriptor enables interrupt and changes ownership */
-+	tx_curr->cmd_sts = 0x1 | (1 << 15) | (1 << 5);
-+
-+	/* Kick the XDMA to start the transfer from memory to the FIFO */
-+	TITAN_GE_WRITE((0x5044 + (port_num << 8)), 0x1);
-+
-+	/* Current descriptor updated */
-+	titan_ge_eth->tx_curr_desc_q = (curr_desc + 1) % TITAN_GE_TX_QUEUE;
-+
-+	/* Prefetch the next descriptor */
-+	prefetch((const void *)
-+		 &titan_ge_eth->tx_desc_area[titan_ge_eth->tx_curr_desc_q]);
-+}
-+
-+/*
-+ * Actually does the open of the Ethernet device
-+ */
-+static int titan_ge_eth_open(struct net_device *netdev)
-+{
-+	titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
-+	unsigned int port_num = titan_ge_eth->port_num;
-+	struct device *device = &titan_ge_device[port_num]->dev;
-+	unsigned long reg_data;
-+	unsigned int phy_reg;
-+	int err = 0;
-+
-+	/* Stop the Rx activity */
-+	reg_data = TITAN_GE_READ(TITAN_GE_RMAC_CONFIG_1 + (port_num << 12));
-+	reg_data &= ~(0x00000001);
-+	TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_1 + (port_num << 12)), reg_data);
-+
-+	/* Clear the port interrupts */
-+	TITAN_GE_WRITE((TITAN_GE_CHANNEL0_INTERRUPT + (port_num << 8)), 0x0);
-+
-+	if (config_done == 0) {
-+		TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_CORE_A, 0);
-+		TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_CORE_B, 0);
-+	}
-+
-+	/* Set the MAC Address */
-+	memcpy(titan_ge_eth->port_mac_addr, netdev->dev_addr, 6);
-+
-+	if (config_done == 0)
-+		titan_port_init(netdev, titan_ge_eth);
-+
-+	titan_ge_update_afx(titan_ge_eth);
-+
-+	/* Allocate the Tx ring now */
-+	titan_ge_eth->tx_ring_skbs = 0;
-+	titan_ge_eth->tx_ring_size = TITAN_GE_TX_QUEUE;
-+
-+	/* Allocate space in the SRAM for the descriptors */
-+	titan_ge_eth->tx_desc_area = (titan_ge_tx_desc *)
-+		(titan_ge_sram + TITAN_TX_RING_BYTES * port_num);
-+	titan_ge_eth->tx_dma = TITAN_SRAM_BASE + TITAN_TX_RING_BYTES * port_num;
-+
-+	if (!titan_ge_eth->tx_desc_area) {
-+		printk(KERN_ERR
-+		       "%s: Cannot allocate Tx Ring (size %d bytes) for port %d\n",
-+		       netdev->name, TITAN_TX_RING_BYTES, port_num);
-+		return -ENOMEM;
-+	}
-+
-+	memset(titan_ge_eth->tx_desc_area, 0, titan_ge_eth->tx_desc_area_size);
-+
-+	/* Now initialize the Tx descriptor ring */
-+	titan_ge_init_tx_desc_ring(titan_ge_eth,
-+				   titan_ge_eth->tx_ring_size,
-+				   (unsigned long) titan_ge_eth->tx_desc_area,
-+				   (unsigned long) titan_ge_eth->tx_dma);
-+
-+	/* Allocate the Rx ring now */
-+	titan_ge_eth->rx_ring_size = TITAN_GE_RX_QUEUE;
-+	titan_ge_eth->rx_ring_skbs = 0;
-+
-+	titan_ge_eth->rx_desc_area =
-+		(titan_ge_rx_desc *)(titan_ge_sram + 0x1000 + TITAN_RX_RING_BYTES * port_num);
-+
-+	titan_ge_eth->rx_dma = TITAN_SRAM_BASE + 0x1000 + TITAN_RX_RING_BYTES * port_num;
-+
-+	if (!titan_ge_eth->rx_desc_area) {
-+		printk(KERN_ERR "%s: Cannot allocate Rx Ring (size %d bytes)\n",
-+		       netdev->name, TITAN_RX_RING_BYTES);
-+
-+		printk(KERN_ERR "%s: Freeing previously allocated TX queues...",
-+		       netdev->name);
-+
-+		dma_free_coherent(device, titan_ge_eth->tx_desc_area_size,
-+				    (void *) titan_ge_eth->tx_desc_area,
-+				    titan_ge_eth->tx_dma);
-+
-+		return -ENOMEM;
-+	}
-+
-+	memset(titan_ge_eth->rx_desc_area, 0, titan_ge_eth->rx_desc_area_size);
-+
-+	/* Now initialize the Rx ring */
-+#ifdef TITAN_GE_JUMBO_FRAMES
-+	if ((titan_ge_init_rx_desc_ring
-+	    (titan_ge_eth, titan_ge_eth->rx_ring_size, TITAN_GE_JUMBO_BUFSIZE,
-+	     (unsigned long) titan_ge_eth->rx_desc_area, 0,
-+	      (unsigned long) titan_ge_eth->rx_dma)) == 0)
-+#else
-+	if ((titan_ge_init_rx_desc_ring
-+	     (titan_ge_eth, titan_ge_eth->rx_ring_size, TITAN_GE_STD_BUFSIZE,
-+	      (unsigned long) titan_ge_eth->rx_desc_area, 0,
-+	      (unsigned long) titan_ge_eth->rx_dma)) == 0)
-+#endif
-+		panic("%s: Error initializing RX Ring\n", netdev->name);
-+
-+	/* Fill the Rx ring with the SKBs */
-+	titan_ge_port_start(netdev, titan_ge_eth);
-+
-+	/*
-+	 * Check if Interrupt Coalscing needs to be turned on. The
-+	 * values specified in the register is multiplied by
-+	 * (8 x 64 nanoseconds) to determine when an interrupt should
-+	 * be sent to the CPU.
-+	 */
-+
-+	if (TITAN_GE_TX_COAL) {
-+		titan_ge_eth->tx_int_coal =
-+		    titan_ge_tx_coal(TITAN_GE_TX_COAL, port_num);
-+	}
-+
-+	err = titan_ge_mdio_read(port_num, TITAN_GE_MDIO_PHY_STATUS, &phy_reg);
-+	if (err == TITAN_GE_MDIO_ERROR) {
-+		printk(KERN_ERR
-+		       "Could not read PHY control register 0x11 \n");
-+		return TITAN_ERROR;
-+	}
-+	if (!(phy_reg & 0x0400)) {
-+		netif_carrier_off(netdev);
-+		netif_stop_queue(netdev);
-+		return TITAN_ERROR;
-+	} else {
-+		netif_carrier_on(netdev);
-+		netif_start_queue(netdev);
-+	}
-+
-+	return TITAN_OK;
-+}
-+
-+/*
-+ * Queue the packet for Tx. Currently no support for zero copy,
-+ * checksum offload and Scatter Gather. The chip does support
-+ * Scatter Gather only. But, that wont help here since zero copy
-+ * requires support for Tx checksumming also.
-+ */
-+int titan_ge_start_xmit(struct sk_buff *skb, struct net_device *netdev)
-+{
-+	titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
-+	unsigned long flags;
-+	struct net_device_stats *stats;
-+//printk("titan_ge_start_xmit\n");
-+
-+	stats = &titan_ge_eth->stats;
-+	spin_lock_irqsave(&titan_ge_eth->lock, flags);
-+
-+	if ((TITAN_GE_TX_QUEUE - titan_ge_eth->tx_ring_skbs) <=
-+	    (skb_shinfo(skb)->nr_frags + 1)) {
-+		netif_stop_queue(netdev);
-+		spin_unlock_irqrestore(&titan_ge_eth->lock, flags);
-+		printk(KERN_ERR "Tx OOD \n");
-+		return 1;
-+	}
-+
-+	titan_ge_tx_queue(titan_ge_eth, skb);
-+	titan_ge_eth->tx_ring_skbs++;
-+
-+	if (TITAN_GE_TX_QUEUE <= (titan_ge_eth->tx_ring_skbs + 4)) {
-+		spin_unlock_irqrestore(&titan_ge_eth->lock, flags);
-+		titan_ge_free_tx_queue(titan_ge_eth);
-+		spin_lock_irqsave(&titan_ge_eth->lock, flags);
-+	}
-+
-+	stats->tx_bytes += skb->len;
-+	stats->tx_packets++;
-+
-+	spin_unlock_irqrestore(&titan_ge_eth->lock, flags);
-+
-+	netdev->trans_start = jiffies;
-+
-+	return 0;
-+}
-+
-+/*
-+ * Actually does the Rx. Rx side checksumming supported.
-+ */
-+static int titan_ge_rx(struct net_device *netdev, int port_num,
-+			titan_ge_port_info * titan_ge_port,
-+		       titan_ge_packet * packet)
-+{
-+	int rx_curr_desc, rx_used_desc;
-+	volatile titan_ge_rx_desc *rx_desc;
-+
-+	rx_curr_desc = titan_ge_port->rx_curr_desc_q;
-+	rx_used_desc = titan_ge_port->rx_used_desc_q;
-+
-+	if (((rx_curr_desc + 1) % TITAN_GE_RX_QUEUE) == rx_used_desc)
-+		return TITAN_ERROR;
-+
-+	rx_desc = &(titan_ge_port->rx_desc_area[rx_curr_desc]);
-+
-+	if (rx_desc->cmd_sts & TITAN_GE_RX_BUFFER_OWNED)
-+		return TITAN_ERROR;
-+
-+	packet->skb = titan_ge_port->rx_skb[rx_curr_desc];
-+	packet->len = (rx_desc->cmd_sts & 0x7fff);
-+
-+	/*
-+	 * At this point, we dont know if the checksumming
-+	 * actually helps relieve CPU. So, keep it for
-+	 * port 0 only
-+	 */
-+	packet->checksum = ntohs((rx_desc->buffer & 0xffff0000) >> 16);
-+	packet->cmd_sts = rx_desc->cmd_sts;
-+
-+	titan_ge_port->rx_curr_desc_q = (rx_curr_desc + 1) % TITAN_GE_RX_QUEUE;
-+
-+	/* Prefetch the next descriptor */
-+	prefetch((const void *)
-+	       &titan_ge_port->rx_desc_area[titan_ge_port->rx_curr_desc_q + 1]);
-+
-+	return TITAN_OK;
-+}
-+
-+/*
-+ * Free the Tx queue of the used SKBs
-+ */
-+static int titan_ge_free_tx_queue(titan_ge_port_info *titan_ge_eth)
-+{
-+	unsigned long flags;
-+
-+	/* Take the lock */
-+	spin_lock_irqsave(&(titan_ge_eth->lock), flags);
-+
-+	while (titan_ge_return_tx_desc(titan_ge_eth, titan_ge_eth->port_num) == 0)
-+		if (titan_ge_eth->tx_ring_skbs != 1)
-+			titan_ge_eth->tx_ring_skbs--;
-+
-+	spin_unlock_irqrestore(&titan_ge_eth->lock, flags);
-+
-+	return TITAN_OK;
-+}
-+
-+/*
-+ * Threshold beyond which we do the cleaning of
-+ * Tx queue and new allocation for the Rx
-+ * queue
-+ */
-+#define	TX_THRESHOLD	4
-+#define	RX_THRESHOLD	10
-+
-+/*
-+ * Receive the packets and send it to the kernel.
-+ */
-+static int titan_ge_receive_queue(struct net_device *netdev, unsigned int max)
-+{
-+	titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
-+	unsigned int port_num = titan_ge_eth->port_num;
-+	titan_ge_packet packet;
-+	struct net_device_stats *stats;
-+	struct sk_buff *skb;
-+	unsigned long received_packets = 0;
-+	unsigned int ack;
-+
-+	stats = &titan_ge_eth->stats;
-+
-+	while ((--max)
-+	       && (titan_ge_rx(netdev, port_num, titan_ge_eth, &packet) == TITAN_OK)) {
-+		skb = (struct sk_buff *) packet.skb;
-+
-+		titan_ge_eth->rx_ring_skbs--;
-+
-+		if (--titan_ge_eth->rx_work_limit < 0)
-+			break;
-+		received_packets++;
-+
-+		stats->rx_packets++;
-+		stats->rx_bytes += packet.len;
-+
-+		if ((packet.cmd_sts & TITAN_GE_RX_PERR) ||
-+			(packet.cmd_sts & TITAN_GE_RX_OVERFLOW_ERROR) ||
-+			(packet.cmd_sts & TITAN_GE_RX_TRUNC) ||
-+			(packet.cmd_sts & TITAN_GE_RX_CRC_ERROR)) {
-+				stats->rx_dropped++;
-+				dev_kfree_skb_any(skb);
-+
-+				continue;
-+		}
-+		/*
-+		 * Either support fast path or slow path. Decision
-+		 * making can really slow down the performance. The
-+		 * idea is to cut down the number of checks and improve
-+		 * the fastpath.
-+		 */
-+
-+		skb_put(skb, packet.len - 2);
-+
-+		/*
-+		 * Increment data pointer by two since thats where
-+		 * the MAC starts
-+		 */
-+		skb_reserve(skb, 2);
-+		skb->protocol = eth_type_trans(skb, netdev);
-+		netif_receive_skb(skb);
-+
-+		if (titan_ge_eth->rx_threshold > RX_THRESHOLD) {
-+			ack = titan_ge_rx_task(netdev, titan_ge_eth);
-+			TITAN_GE_WRITE((0x5048 + (port_num << 8)), ack);
-+			titan_ge_eth->rx_threshold = 0;
-+		} else
-+			titan_ge_eth->rx_threshold++;
-+
-+		if (titan_ge_eth->tx_threshold > TX_THRESHOLD) {
-+			titan_ge_eth->tx_threshold = 0;
-+			titan_ge_free_tx_queue(titan_ge_eth);
-+		}
-+		else
-+			titan_ge_eth->tx_threshold++;
-+
-+	}
-+	return received_packets;
-+}
-+
-+
-+/*
-+ * Enable the Rx side interrupts
-+ */
-+static void titan_ge_enable_int(unsigned int port_num,
-+			titan_ge_port_info *titan_ge_eth,
-+			struct net_device *netdev)
-+{
-+	unsigned long reg_data = TITAN_GE_READ(TITAN_GE_INTR_XDMA_IE);
-+
-+	if (port_num == 0)
-+		reg_data |= 0x3;
-+	if (port_num == 1)
-+		reg_data |= 0x300;
-+	if (port_num == 2)
-+		reg_data |= 0x30000;
-+
-+	/* Re-enable interrupts */
-+	TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_IE, reg_data);
-+}
-+
-+/*
-+ * Main function to handle the polling for Rx side NAPI.
-+ * Receive interrupts have been disabled at this point.
-+ * The poll schedules the transmit followed by receive.
-+ */
-+static int titan_ge_poll(struct net_device *netdev, int *budget)
-+{
-+	titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
-+	int port_num = titan_ge_eth->port_num;
-+	int work_done = 0;
-+	unsigned long flags, status;
-+
-+	titan_ge_eth->rx_work_limit = *budget;
-+	if (titan_ge_eth->rx_work_limit > netdev->quota)
-+		titan_ge_eth->rx_work_limit = netdev->quota;
-+
-+	do {
-+		/* Do the transmit cleaning work here */
-+		titan_ge_free_tx_queue(titan_ge_eth);
-+
-+		/* Ack the Rx interrupts */
-+		if (port_num == 0)
-+			TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_CORE_A, 0x3);
-+		if (port_num == 1)
-+			TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_CORE_A, 0x300);
-+		if (port_num == 2)
-+			TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_CORE_A, 0x30000);
-+
-+		work_done += titan_ge_receive_queue(netdev, 0);
-+
-+		/* Out of quota and there is work to be done */
-+		if (titan_ge_eth->rx_work_limit < 0)
-+			goto not_done;
-+
-+		/* Receive alloc_skb could lead to OOM */
-+		if (oom_flag == 1) {
-+			oom_flag = 0;
-+			goto oom;
-+		}
-+
-+		status = TITAN_GE_READ(TITAN_GE_INTR_XDMA_CORE_A);
-+	} while (status & 0x30300);
-+
-+	/* If we are here, then no more interrupts to process */
-+	goto done;
-+
-+not_done:
-+	*budget -= work_done;
-+	netdev->quota -= work_done;
-+	return 1;
-+
-+oom:
-+	printk(KERN_ERR "OOM \n");
-+	netif_rx_complete(netdev);
-+	return 0;
-+
-+done:
-+	/*
-+	 * No more packets on the poll list. Turn the interrupts
-+	 * back on and we should be able to catch the new
-+	 * packets in the interrupt handler
-+	 */
-+	if (!work_done)
-+		work_done = 1;
-+
-+	*budget -= work_done;
-+	netdev->quota -= work_done;
-+
-+	spin_lock_irqsave(&titan_ge_eth->lock, flags);
-+
-+	/* Remove us from the poll list */
-+	netif_rx_complete(netdev);
-+
-+	/* Re-enable interrupts */
-+	titan_ge_enable_int(port_num, titan_ge_eth, netdev);
-+
-+	spin_unlock_irqrestore(&titan_ge_eth->lock, flags);
-+
-+	return 0;
-+}
-+
-+/*
-+ * Close the network device
-+ */
-+int titan_ge_stop(struct net_device *netdev)
-+{
-+	titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
-+
-+	spin_lock_irq(&(titan_ge_eth->lock));
-+	titan_ge_eth_stop(netdev);
-+	free_irq(netdev->irq, netdev);
-+	spin_unlock_irq(&titan_ge_eth->lock);
-+
-+	return TITAN_OK;
-+}
-+
-+/*
-+ * Free the Tx ring
-+ */
-+static void titan_ge_free_tx_rings(struct net_device *netdev)
-+{
-+	titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
-+	unsigned int port_num = titan_ge_eth->port_num;
-+	unsigned int curr;
-+	unsigned long reg_data;
-+
-+	/* Stop the Tx DMA */
-+	reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG +
-+				(port_num << 8));
-+	reg_data |= 0xc0000000;
-+	TITAN_GE_WRITE((TITAN_GE_CHANNEL0_CONFIG +
-+			(port_num << 8)), reg_data);
-+
-+	/* Disable the TMAC */
-+	reg_data = TITAN_GE_READ(TITAN_GE_TMAC_CONFIG_1 +
-+				(port_num << 12));
-+	reg_data &= ~(0x00000001);
-+	TITAN_GE_WRITE((TITAN_GE_TMAC_CONFIG_1 +
-+			(port_num << 12)), reg_data);
-+
-+	for (curr = 0;
-+	     (titan_ge_eth->tx_ring_skbs) && (curr < TITAN_GE_TX_QUEUE);
-+	     curr++) {
-+		if (titan_ge_eth->tx_skb[curr]) {
-+			dev_kfree_skb(titan_ge_eth->tx_skb[curr]);
-+			titan_ge_eth->tx_ring_skbs--;
-+		}
-+	}
-+
-+	if (titan_ge_eth->tx_ring_skbs != 0)
-+		printk
-+		    ("%s: Error on Tx descriptor free - could not free %d"
-+		     " descriptors\n", netdev->name,
-+		     titan_ge_eth->tx_ring_skbs);
-+
-+#ifndef TITAN_RX_RING_IN_SRAM
-+	dma_free_coherent(&titan_ge_device[port_num]->dev,
-+			  titan_ge_eth->tx_desc_area_size,
-+			  (void *) titan_ge_eth->tx_desc_area,
-+			  titan_ge_eth->tx_dma);
-+#endif
-+}
-+
-+/*
-+ * Free the Rx ring
-+ */
-+static void titan_ge_free_rx_rings(struct net_device *netdev)
-+{
-+	titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
-+	unsigned int port_num = titan_ge_eth->port_num;
-+	unsigned int curr;
-+	unsigned long reg_data;
-+
-+	/* Stop the Rx DMA */
-+	reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG +
-+				(port_num << 8));
-+	reg_data |= 0x000c0000;
-+	TITAN_GE_WRITE((TITAN_GE_CHANNEL0_CONFIG +
-+			(port_num << 8)), reg_data);
-+
-+	/* Disable the RMAC */
-+	reg_data = TITAN_GE_READ(TITAN_GE_RMAC_CONFIG_1 +
-+				(port_num << 12));
-+	reg_data &= ~(0x00000001);
-+	TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_1 +
-+			(port_num << 12)), reg_data);
-+
-+	for (curr = 0;
-+	     titan_ge_eth->rx_ring_skbs && (curr < TITAN_GE_RX_QUEUE);
-+	     curr++) {
-+		if (titan_ge_eth->rx_skb[curr]) {
-+			dev_kfree_skb(titan_ge_eth->rx_skb[curr]);
-+			titan_ge_eth->rx_ring_skbs--;
-+		}
-+	}
-+
-+	if (titan_ge_eth->rx_ring_skbs != 0)
-+		printk(KERN_ERR
-+		       "%s: Error in freeing Rx Ring. %d skb's still"
-+		       " stuck in RX Ring - ignoring them\n", netdev->name,
-+		       titan_ge_eth->rx_ring_skbs);
-+
-+#ifndef TITAN_RX_RING_IN_SRAM
-+	dma_free_coherent(&titan_ge_device[port_num]->dev,
-+			  titan_ge_eth->rx_desc_area_size,
-+			  (void *) titan_ge_eth->rx_desc_area,
-+			  titan_ge_eth->rx_dma);
-+#endif
-+}
-+
-+/*
-+ * Actually does the stop of the Ethernet device
-+ */
-+static void titan_ge_eth_stop(struct net_device *netdev)
-+{
-+	titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
-+
-+	netif_stop_queue(netdev);
-+
-+	titan_ge_port_reset(titan_ge_eth->port_num);
-+
-+	titan_ge_free_tx_rings(netdev);
-+	titan_ge_free_rx_rings(netdev);
-+
-+	/* Disable the Tx and Rx Interrupts for all channels */
-+	TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_IE, 0x0);
-+}
-+
-+/*
-+ * Update the MAC address. Note that we have to write the
-+ * address in three station registers, 16 bits each. And this
-+ * has to be done for TMAC and RMAC
-+ */
-+static void titan_ge_update_mac_address(struct net_device *netdev)
-+{
-+	titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
-+	unsigned int port_num = titan_ge_eth->port_num;
-+	u8 p_addr[6];
-+
-+	memcpy(titan_ge_eth->port_mac_addr, netdev->dev_addr, 6);
-+	memcpy(p_addr, netdev->dev_addr, 6);
-+
-+	/* Update the Address Filtering Match tables */
-+	titan_ge_update_afx(titan_ge_eth);
-+
-+	printk("Station MAC : %d %d %d %d %d %d  \n",
-+		p_addr[5], p_addr[4], p_addr[3],
-+		p_addr[2], p_addr[1], p_addr[0]);
-+
-+	/* Set the MAC address here for TMAC and RMAC */
-+	TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_HI + (port_num << 12)),
-+		       ((p_addr[5] << 8) | p_addr[4]));
-+	TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_MID + (port_num << 12)),
-+		       ((p_addr[3] << 8) | p_addr[2]));
-+	TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_LOW + (port_num << 12)),
-+		       ((p_addr[1] << 8) | p_addr[0]));
-+
-+	TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_HI + (port_num << 12)),
-+		       ((p_addr[5] << 8) | p_addr[4]));
-+	TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_MID + (port_num << 12)),
-+		       ((p_addr[3] << 8) | p_addr[2]));
-+	TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_LOW + (port_num << 12)),
-+		       ((p_addr[1] << 8) | p_addr[0]));
-+}
-+
-+/*
-+ * Set the MAC address of the Ethernet device
-+ */
-+static int titan_ge_set_mac_address(struct net_device *dev, void *addr)
-+{
-+	titan_ge_port_info *tp = netdev_priv(dev);
-+	struct sockaddr *sa = addr;
-+
-+	memcpy(dev->dev_addr, sa->sa_data, dev->addr_len);
-+
-+	spin_lock_irq(&tp->lock);
-+	titan_ge_update_mac_address(dev);
-+	spin_unlock_irq(&tp->lock);
-+
-+	return 0;
-+}
-+
-+/*
-+ * Get the Ethernet device stats
-+ */
-+static struct net_device_stats *titan_ge_get_stats(struct net_device *netdev)
-+{
-+	titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
-+
-+	return &titan_ge_eth->stats;
-+}
-+
-+/*
-+ * Initialize the Rx descriptor ring for the Titan Ge
-+ */
-+static int titan_ge_init_rx_desc_ring(titan_ge_port_info * titan_eth_port,
-+				      int rx_desc_num,
-+				      int rx_buff_size,
-+				      unsigned long rx_desc_base_addr,
-+				      unsigned long rx_buff_base_addr,
-+				      unsigned long rx_dma)
-+{
-+	volatile titan_ge_rx_desc *rx_desc;
-+	unsigned long buffer_addr;
-+	int index;
-+	unsigned long titan_ge_rx_desc_bus = rx_dma;
-+
-+	buffer_addr = rx_buff_base_addr;
-+	rx_desc = (titan_ge_rx_desc *) rx_desc_base_addr;
-+
-+	/* Check alignment */
-+	if (rx_buff_base_addr & 0xF)
-+		return 0;
-+
-+	/* Check Rx buffer size */
-+	if ((rx_buff_size < 8) || (rx_buff_size > TITAN_GE_MAX_RX_BUFFER))
-+		return 0;
-+
-+	/* 64-bit alignment
-+	if ((rx_buff_base_addr + rx_buff_size) & 0x7)
-+		return 0; */
-+
-+	/* Initialize the Rx desc ring */
-+	for (index = 0; index < rx_desc_num; index++) {
-+		titan_ge_rx_desc_bus += sizeof(titan_ge_rx_desc);
-+		rx_desc[index].cmd_sts = 0;
-+		rx_desc[index].buffer_addr = buffer_addr;
-+		titan_eth_port->rx_skb[index] = NULL;
-+		buffer_addr += rx_buff_size;
-+	}
-+
-+	titan_eth_port->rx_curr_desc_q = 0;
-+	titan_eth_port->rx_used_desc_q = 0;
-+
-+	titan_eth_port->rx_desc_area = (titan_ge_rx_desc *) rx_desc_base_addr;
-+	titan_eth_port->rx_desc_area_size =
-+	    rx_desc_num * sizeof(titan_ge_rx_desc);
-+
-+	titan_eth_port->rx_dma = rx_dma;
-+
-+	return TITAN_OK;
-+}
-+
-+/*
-+ * Initialize the Tx descriptor ring. Descriptors in the SRAM
-+ */
-+static int titan_ge_init_tx_desc_ring(titan_ge_port_info * titan_ge_port,
-+				      int tx_desc_num,
-+				      unsigned long tx_desc_base_addr,
-+				      unsigned long tx_dma)
-+{
-+	titan_ge_tx_desc *tx_desc;
-+	int index;
-+	unsigned long titan_ge_tx_desc_bus = tx_dma;
-+
-+	if (tx_desc_base_addr & 0xF)
-+		return 0;
-+
-+	tx_desc = (titan_ge_tx_desc *) tx_desc_base_addr;
-+
-+	for (index = 0; index < tx_desc_num; index++) {
-+		titan_ge_port->tx_dma_array[index] =
-+		    (dma_addr_t) titan_ge_tx_desc_bus;
-+		titan_ge_tx_desc_bus += sizeof(titan_ge_tx_desc);
-+		tx_desc[index].cmd_sts = 0x0000;
-+		tx_desc[index].buffer_len = 0;
-+		tx_desc[index].buffer_addr = 0x00000000;
-+		titan_ge_port->tx_skb[index] = NULL;
-+	}
-+
-+	titan_ge_port->tx_curr_desc_q = 0;
-+	titan_ge_port->tx_used_desc_q = 0;
-+
-+	titan_ge_port->tx_desc_area = (titan_ge_tx_desc *) tx_desc_base_addr;
-+	titan_ge_port->tx_desc_area_size =
-+	    tx_desc_num * sizeof(titan_ge_tx_desc);
-+
-+	titan_ge_port->tx_dma = tx_dma;
-+	return TITAN_OK;
-+}
-+
-+/*
-+ * Initialize the device as an Ethernet device
-+ */
-+static int __init titan_ge_probe(struct device *device)
-+{
-+	titan_ge_port_info *titan_ge_eth;
-+	struct net_device *netdev;
-+	int port = to_platform_device(device)->id;
-+	int err;
-+
-+	netdev = alloc_etherdev(sizeof(titan_ge_port_info));
-+	if (!netdev) {
-+		err = -ENODEV;
-+		goto out;
-+	}
-+
-+	netdev->open = titan_ge_open;
-+	netdev->stop = titan_ge_stop;
-+	netdev->hard_start_xmit = titan_ge_start_xmit;
-+	netdev->get_stats = titan_ge_get_stats;
-+	netdev->set_multicast_list = titan_ge_set_multi;
-+	netdev->set_mac_address = titan_ge_set_mac_address;
-+
-+	/* Tx timeout */
-+	netdev->tx_timeout = titan_ge_tx_timeout;
-+	netdev->watchdog_timeo = 2 * HZ;
-+
-+	/* Set these to very high values */
-+	netdev->poll = titan_ge_poll;
-+	netdev->weight = 64;
-+
-+	netdev->tx_queue_len = TITAN_GE_TX_QUEUE;
-+	netif_carrier_off(netdev);
-+	netdev->base_addr = 0;
-+
-+	netdev->change_mtu = titan_ge_change_mtu;
-+
-+	titan_ge_eth = netdev_priv(netdev);
-+	/* Allocation of memory for the driver structures */
-+
-+	titan_ge_eth->port_num = port;
-+
-+	/* Configure the Tx timeout handler */
-+	INIT_WORK(&titan_ge_eth->tx_timeout_task,
-+		  (void (*)(void *)) titan_ge_tx_timeout_task, netdev);
-+
-+	spin_lock_init(&titan_ge_eth->lock);
-+
-+	/* set MAC addresses */
-+	memcpy(netdev->dev_addr, titan_ge_mac_addr_base, 6);
-+	netdev->dev_addr[5] += port;
-+
-+	err = register_netdev(netdev);
-+
-+	if (err)
-+		goto out_free_netdev;
-+
-+	printk(KERN_NOTICE
-+	       "%s: port %d with MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
-+	       netdev->name, port, netdev->dev_addr[0],
-+	       netdev->dev_addr[1], netdev->dev_addr[2],
-+	       netdev->dev_addr[3], netdev->dev_addr[4],
-+	       netdev->dev_addr[5]);
-+
-+	printk(KERN_NOTICE "Rx NAPI supported, Tx Coalescing ON \n");
-+
-+	return 0;
-+
-+out_free_netdev:
-+	kfree(netdev);
-+
-+out:
-+	return err;
-+}
-+
-+static void __devexit titan_device_remove(struct device *device)
-+{
-+}
-+
-+/*
-+ * Reset the Ethernet port
-+ */
-+static void titan_ge_port_reset(unsigned int port_num)
-+{
-+	unsigned int reg_data;
-+
-+	/* Stop the Tx port activity */
-+	reg_data = TITAN_GE_READ(TITAN_GE_TMAC_CONFIG_1 +
-+				(port_num << 12));
-+	reg_data &= ~(0x0001);
-+	TITAN_GE_WRITE((TITAN_GE_TMAC_CONFIG_1 +
-+			(port_num << 12)), reg_data);
-+
-+	/* Stop the Rx port activity */
-+	reg_data = TITAN_GE_READ(TITAN_GE_RMAC_CONFIG_1 +
-+				(port_num << 12));
-+	reg_data &= ~(0x0001);
-+	TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_1 +
-+			(port_num << 12)), reg_data);
-+
-+	return;
-+}
-+
-+/*
-+ * Return the Tx desc after use by the XDMA
-+ */
-+static int titan_ge_return_tx_desc(titan_ge_port_info * titan_ge_eth, int port)
-+{
-+	int tx_desc_used;
-+	struct sk_buff *skb;
-+
-+	tx_desc_used = titan_ge_eth->tx_used_desc_q;
-+
-+	/* return right away */
-+	if (tx_desc_used == titan_ge_eth->tx_curr_desc_q)
-+		return TITAN_ERROR;
-+
-+	/* Now the critical stuff */
-+	skb = titan_ge_eth->tx_skb[tx_desc_used];
-+
-+	dev_kfree_skb_any(skb);
-+
-+	titan_ge_eth->tx_skb[tx_desc_used] = NULL;
-+	titan_ge_eth->tx_used_desc_q =
-+	    (tx_desc_used + 1) % TITAN_GE_TX_QUEUE;
-+
-+	return 0;
-+}
-+
-+/*
-+ * Coalescing for the Tx path
-+ */
-+static unsigned long titan_ge_tx_coal(unsigned long delay, int port)
-+{
-+	unsigned long rx_delay;
-+
-+	rx_delay = TITAN_GE_READ(TITAN_GE_INT_COALESCING);
-+	delay = (delay << 16) | rx_delay;
-+
-+	TITAN_GE_WRITE(TITAN_GE_INT_COALESCING, delay);
-+	TITAN_GE_WRITE(0x5038, delay);
-+
-+	return delay;
-+}
-+
-+static struct device_driver titan_soc_driver = {
-+	.name   = titan_string,
-+	.bus    = &platform_bus_type,
-+	.probe  = titan_ge_probe,
-+	.remove = __devexit_p(titan_device_remove),
-+};
-+
-+static void titan_platform_release (struct device *device)
-+{
-+	struct platform_device *pldev;
-+
-+	/* free device */
-+	pldev = to_platform_device (device);
-+	kfree (pldev);
-+}
-+
-+/*
-+ * Register the Titan GE with the kernel
-+ */
-+static int __init titan_ge_init_module(void)
-+{
-+	struct platform_device *pldev;
-+	unsigned int version, device;
-+	int i;
-+
-+	printk(KERN_NOTICE
-+	       "PMC-Sierra TITAN 10/100/1000 Ethernet Driver \n");
-+
-+	titan_ge_base = (unsigned long) ioremap(TITAN_GE_BASE, TITAN_GE_SIZE);
-+	if (!titan_ge_base) {
-+		printk("Mapping Titan GE failed\n");
-+		goto out;
-+	}
-+
-+	device = TITAN_GE_READ(TITAN_GE_DEVICE_ID);
-+	version = (device & 0x000f0000) >> 16;
-+	device &= 0x0000ffff;
-+
-+	printk(KERN_NOTICE "Device Id : %x,  Version : %x \n", device, version);
-+
-+#ifdef TITAN_RX_RING_IN_SRAM
-+	titan_ge_sram = (unsigned long) ioremap(TITAN_SRAM_BASE,
-+						TITAN_SRAM_SIZE);
-+	if (!titan_ge_sram) {
-+		printk("Mapping Titan SRAM failed\n");
-+		goto out_unmap_ge;
-+	}
-+#endif
-+
-+	if (driver_register(&titan_soc_driver)) {
-+		printk(KERN_ERR "Driver registration failed\n");
-+		goto out_unmap_sram;
-+	}
-+
-+	for (i = 0; i < 3; i++) {
-+		titan_ge_device[i] = NULL;
-+
-+	        if (!(pldev = kmalloc (sizeof (*pldev), GFP_KERNEL)))
-+	                continue;
-+
-+                memset (pldev, 0, sizeof (*pldev));
-+                pldev->name		= titan_string;
-+                pldev->id		= i;
-+                pldev->dev.release	= titan_platform_release;
-+                titan_ge_device[i]	= pldev;
-+
-+                if (platform_device_register (pldev)) {
-+                        kfree (pldev);
-+                        titan_ge_device[i] = NULL;
-+                        continue;
-+                }
-+                                                                                
-+                if (!pldev->dev.driver) {
-+	                /*
-+			 * The driver was not bound to this device, there was
-+	                 * no hardware at this address. Unregister it, as the
-+	                 * release fuction will take care of freeing the
-+	                 * allocated structure
-+			 */
-+                        titan_ge_device[i] = NULL;
-+                        platform_device_unregister (pldev);
-+                }
-+        }
-+
-+	return 0;
-+
-+out_unmap_sram:
-+	iounmap((void *)titan_ge_sram);
-+
-+out_unmap_ge:
-+	iounmap((void *)titan_ge_base);
-+
-+out:
-+	return -ENOMEM;
-+}
-+
-+/*
-+ * Unregister the Titan GE from the kernel
-+ */
-+static void __exit titan_ge_cleanup_module(void)
-+{
-+	int i;
-+
-+	driver_unregister(&titan_soc_driver);
-+
-+	for (i = 0; i < 3; i++) {
-+		if (titan_ge_device[i]) {
-+			platform_device_unregister (titan_ge_device[i]);
-+			titan_ge_device[i] = NULL;
-+		}
-+	}
-+
-+	iounmap((void *)titan_ge_sram);
-+	iounmap((void *)titan_ge_base);
-+}
-+
-+MODULE_AUTHOR("Manish Lachwani <lachwani@pmc-sierra.com>");
-+MODULE_DESCRIPTION("Titan GE Ethernet driver");
-+MODULE_LICENSE("GPL");
-+
-+module_init(titan_ge_init_module);
-+module_exit(titan_ge_cleanup_module);
-diff -Naur linux-2.6.17.orig/drivers/net/titan_ge.h linux-2.6.17/drivers/net/titan_ge.h
---- linux-2.6.17.orig/drivers/net/titan_ge.h	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/drivers/net/titan_ge.h	2006-06-19 18:16:13.000000000 -0700
-@@ -0,0 +1,417 @@
-+#ifndef _TITAN_GE_H_
-+#define _TITAN_GE_H_
-+
-+#include <linux/config.h>
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/config.h>
-+#include <linux/spinlock.h>
-+#include <asm/byteorder.h>
-+
-+/*
-+ * These functions should be later moved to a more generic location since there
-+ * will be others accessing it also
-+ */
-+
-+/*
-+ * This is the way it works: LKB5 Base is at 0x0128. TITAN_BASE is defined in
-+ * include/asm/titan_dep.h. TITAN_GE_BASE is the value in the TITAN_GE_LKB5
-+ * register.
-+ */
-+
-+#define	TITAN_GE_BASE	0xfe000000UL
-+#define	TITAN_GE_SIZE	0x10000UL
-+
-+extern unsigned long titan_ge_base;
-+
-+#define	TITAN_GE_WRITE(offset, data) \
-+		*(volatile u32 *)(titan_ge_base + (offset)) = (data)
-+
-+#define TITAN_GE_READ(offset) *(volatile u32 *)(titan_ge_base + (offset))
-+
-+#ifndef msec_delay
-+#define msec_delay(x)   do { if(in_interrupt()) { \
-+				/* Don't mdelay in interrupt context! */ \
-+				BUG(); \
-+			} else { \
-+				set_current_state(TASK_UNINTERRUPTIBLE); \
-+				schedule_timeout((x * HZ)/1000); \
-+			} } while(0)
-+#endif
-+
-+#define TITAN_GE_PORT_0
-+
-+#define	TITAN_SRAM_BASE		((OCD_READ(RM9000x2_OCD_LKB13) & ~1) << 4)
-+#define	TITAN_SRAM_SIZE		0x2000UL
-+
-+/*
-+ * We may need these constants
-+ */
-+#define TITAN_BIT0    0x00000001
-+#define TITAN_BIT1    0x00000002
-+#define TITAN_BIT2    0x00000004
-+#define TITAN_BIT3    0x00000008
-+#define TITAN_BIT4    0x00000010
-+#define TITAN_BIT5    0x00000020
-+#define TITAN_BIT6    0x00000040
-+#define TITAN_BIT7    0x00000080
-+#define TITAN_BIT8    0x00000100
-+#define TITAN_BIT9    0x00000200
-+#define TITAN_BIT10   0x00000400
-+#define TITAN_BIT11   0x00000800
-+#define TITAN_BIT12   0x00001000
-+#define TITAN_BIT13   0x00002000
-+#define TITAN_BIT14   0x00004000
-+#define TITAN_BIT15   0x00008000
-+#define TITAN_BIT16   0x00010000
-+#define TITAN_BIT17   0x00020000
-+#define TITAN_BIT18   0x00040000
-+#define TITAN_BIT19   0x00080000
-+#define TITAN_BIT20   0x00100000
-+#define TITAN_BIT21   0x00200000
-+#define TITAN_BIT22   0x00400000
-+#define TITAN_BIT23   0x00800000
-+#define TITAN_BIT24   0x01000000
-+#define TITAN_BIT25   0x02000000
-+#define TITAN_BIT26   0x04000000
-+#define TITAN_BIT27   0x08000000
-+#define TITAN_BIT28   0x10000000
-+#define TITAN_BIT29   0x20000000
-+#define TITAN_BIT30   0x40000000
-+#define TITAN_BIT31   0x80000000
-+
-+/* Flow Control */
-+#define	TITAN_GE_FC_NONE	0x0
-+#define	TITAN_GE_FC_FULL	0x1
-+#define	TITAN_GE_FC_TX_PAUSE	0x2
-+#define	TITAN_GE_FC_RX_PAUSE	0x3
-+
-+/* Duplex Settings */
-+#define	TITAN_GE_FULL_DUPLEX	0x1
-+#define	TITAN_GE_HALF_DUPLEX	0x2
-+
-+/* Speed settings */
-+#define	TITAN_GE_SPEED_1000	0x1
-+#define	TITAN_GE_SPEED_100	0x2
-+#define	TITAN_GE_SPEED_10	0x3
-+
-+/* Debugging info only */
-+#undef TITAN_DEBUG
-+
-+/* Keep the rings in the Titan's SSRAM */
-+#define TITAN_RX_RING_IN_SRAM
-+
-+#ifdef CONFIG_64BIT
-+#define	TITAN_GE_IE_MASK	0xfffffffffb001b64
-+#define	TITAN_GE_IE_STATUS	0xfffffffffb001b60
-+#else
-+#define	TITAN_GE_IE_MASK	0xfb001b64
-+#define	TITAN_GE_IE_STATUS	0xfb001b60
-+#endif
-+
-+/* Support for Jumbo Frames */
-+#undef TITAN_GE_JUMBO_FRAMES
-+
-+/* Rx buffer size */
-+#ifdef TITAN_GE_JUMBO_FRAMES
-+#define	TITAN_GE_JUMBO_BUFSIZE	9080
-+#else
-+#define	TITAN_GE_STD_BUFSIZE	1580
-+#endif
-+
-+/*
-+ * Tx and Rx Interrupt Coalescing parameter. These values are
-+ * for 1 Ghz processor. Rx coalescing can be taken care of
-+ * by NAPI. NAPI is adaptive and hence useful. Tx coalescing
-+ * is not adaptive. Hence, these values need to be adjusted
-+ * based on load, CPU speed etc.
-+ */
-+#define	TITAN_GE_RX_COAL	150
-+#define	TITAN_GE_TX_COAL	300
-+
-+#if defined(__BIG_ENDIAN)
-+
-+/* Define the Rx descriptor */
-+typedef struct eth_rx_desc {
-+	u32     reserved;	/* Unused 		*/
-+	u32     buffer_addr;	/* CPU buffer address 	*/
-+	u32	cmd_sts;	/* Command and Status	*/
-+	u32	buffer;		/* XDMA buffer address	*/
-+} titan_ge_rx_desc;
-+
-+/* Define the Tx descriptor */
-+typedef struct eth_tx_desc {
-+	u16     cmd_sts;	/* Command, Status and Buffer count */
-+	u16	buffer_len;	/* Length of the buffer	*/
-+	u32     buffer_addr;	/* Physical address of the buffer */
-+} titan_ge_tx_desc;
-+
-+#elif defined(__LITTLE_ENDIAN)
-+
-+/* Define the Rx descriptor */
-+typedef struct eth_rx_desc {
-+	u32	buffer_addr;	/* CPU buffer address   */
-+	u32	reserved;	/* Unused               */
-+	u32	buffer;		/* XDMA buffer address  */
-+	u32	cmd_sts;	/* Command and Status   */
-+} titan_ge_rx_desc;
-+
-+/* Define the Tx descriptor */
-+typedef struct eth_tx_desc {
-+	u32     buffer_addr;	/* Physical address of the buffer */
-+	u16     buffer_len;     /* Length of the buffer */
-+	u16     cmd_sts;        /* Command, Status and Buffer count */
-+} titan_ge_tx_desc;
-+#endif
-+
-+/* Default Tx Queue Size */
-+#define	TITAN_GE_TX_QUEUE	128
-+#define TITAN_TX_RING_BYTES	(TITAN_GE_TX_QUEUE * sizeof(struct eth_tx_desc))
-+
-+/* Default Rx Queue Size */
-+#define	TITAN_GE_RX_QUEUE	64
-+#define TITAN_RX_RING_BYTES	(TITAN_GE_RX_QUEUE * sizeof(struct eth_rx_desc))
-+
-+/* Packet Structure */
-+typedef struct _pkt_info {
-+	unsigned int           len;
-+	unsigned int            cmd_sts;
-+	unsigned int            buffer;
-+	struct sk_buff          *skb;
-+	unsigned int		checksum;
-+} titan_ge_packet;
-+
-+
-+#define	PHYS_CNT	3
-+
-+/* Titan Port specific data structure */
-+typedef struct _eth_port_ctrl {
-+	unsigned int		port_num;
-+	u8			port_mac_addr[6];
-+
-+	/* Rx descriptor pointers */
-+	int 			rx_curr_desc_q, rx_used_desc_q;
-+
-+	/* Tx descriptor pointers */
-+	int 			tx_curr_desc_q, tx_used_desc_q;
-+
-+	/* Rx descriptor area */
-+	volatile titan_ge_rx_desc	*rx_desc_area;
-+	unsigned int			rx_desc_area_size;
-+	struct sk_buff*			rx_skb[TITAN_GE_RX_QUEUE];
-+
-+	/* Tx Descriptor area */
-+	volatile titan_ge_tx_desc	*tx_desc_area;
-+	unsigned int                    tx_desc_area_size;
-+	struct sk_buff*                 tx_skb[TITAN_GE_TX_QUEUE];
-+
-+	/* Timeout task */
-+	struct work_struct		tx_timeout_task;
-+
-+	/* DMA structures and handles */
-+	dma_addr_t			tx_dma;
-+	dma_addr_t			rx_dma;
-+	dma_addr_t			tx_dma_array[TITAN_GE_TX_QUEUE];
-+
-+	/* Device lock */
-+	spinlock_t			lock;
-+
-+	unsigned int			tx_ring_skbs;
-+	unsigned int			rx_ring_size;
-+	unsigned int			tx_ring_size;
-+	unsigned int			rx_ring_skbs;
-+
-+	struct net_device_stats		stats;
-+
-+	/* Tx and Rx coalescing */
-+	unsigned long			rx_int_coal;
-+	unsigned long			tx_int_coal;
-+
-+	/* Threshold for replenishing the Rx and Tx rings */
-+	unsigned int			tx_threshold;
-+	unsigned int			rx_threshold;
-+
-+	/* NAPI work limit */
-+	unsigned int			rx_work_limit;
-+} titan_ge_port_info;
-+
-+/* Titan specific constants */
-+#define	TITAN_ETH_PORT_IRQ		3
-+
-+/* Max Rx buffer */
-+#define	TITAN_GE_MAX_RX_BUFFER		65536
-+
-+/* Tx and Rx Error */
-+#define	TITAN_GE_ERROR
-+
-+/* Rx Descriptor Command and Status */
-+
-+#define	TITAN_GE_RX_CRC_ERROR		TITAN_BIT27	/* crc error */
-+#define	TITAN_GE_RX_OVERFLOW_ERROR	TITAN_BIT15	/* overflow */
-+#define TITAN_GE_RX_BUFFER_OWNED	TITAN_BIT21	/* buffer ownership */
-+#define	TITAN_GE_RX_STP			TITAN_BIT31	/* start of packet */
-+#define	TITAN_GE_RX_BAM			TITAN_BIT30	/* broadcast address match */
-+#define TITAN_GE_RX_PAM			TITAN_BIT28	/* physical address match */
-+#define TITAN_GE_RX_LAFM		TITAN_BIT29	/* logical address filter match */
-+#define TITAN_GE_RX_VLAN		TITAN_BIT26	/* virtual lans */
-+#define TITAN_GE_RX_PERR		TITAN_BIT19	/* packet error */
-+#define TITAN_GE_RX_TRUNC		TITAN_BIT20	/* packet size greater than 32 buffers */
-+
-+/* Tx Descriptor Command */
-+#define	TITAN_GE_TX_BUFFER_OWNED	TITAN_BIT5	/* buffer ownership */
-+#define	TITAN_GE_TX_ENABLE_INTERRUPT	TITAN_BIT15	/* Interrupt Enable */
-+
-+/* Return Status */
-+#define	TITAN_OK	0x1	/* Good Status */
-+#define	TITAN_ERROR	0x2	/* Error Status */
-+
-+/* MIB specific register offset */
-+#define TITAN_GE_MSTATX_STATS_BASE_LOW       0x0800  /* MSTATX COUNTL[15:0] */
-+#define TITAN_GE_MSTATX_STATS_BASE_MID       0x0804  /* MSTATX COUNTM[15:0] */
-+#define TITAN_GE_MSTATX_STATS_BASE_HI        0x0808  /* MSTATX COUNTH[7:0] */
-+#define TITAN_GE_MSTATX_CONTROL              0x0828  /* MSTATX Control */
-+#define TITAN_GE_MSTATX_VARIABLE_SELECT      0x082C  /* MSTATX Variable Select */
-+
-+/* MIB counter offsets, add to the TITAN_GE_MSTATX_STATS_BASE_XXX */
-+#define TITAN_GE_MSTATX_RXFRAMESOK                   0x0040
-+#define TITAN_GE_MSTATX_RXOCTETSOK                   0x0050
-+#define TITAN_GE_MSTATX_RXFRAMES                     0x0060
-+#define TITAN_GE_MSTATX_RXOCTETS                     0x0070
-+#define TITAN_GE_MSTATX_RXUNICASTFRAMESOK            0x0080
-+#define TITAN_GE_MSTATX_RXBROADCASTFRAMESOK          0x0090
-+#define TITAN_GE_MSTATX_RXMULTICASTFRAMESOK          0x00A0
-+#define TITAN_GE_MSTATX_RXTAGGEDFRAMESOK             0x00B0
-+#define TITAN_GE_MSTATX_RXMACPAUSECONTROLFRAMESOK    0x00C0
-+#define TITAN_GE_MSTATX_RXMACCONTROLFRAMESOK         0x00D0
-+#define TITAN_GE_MSTATX_RXFCSERROR                   0x00E0
-+#define TITAN_GE_MSTATX_RXALIGNMENTERROR             0x00F0
-+#define TITAN_GE_MSTATX_RXSYMBOLERROR                0x0100
-+#define TITAN_GE_MSTATX_RXLAYER1ERROR                0x0110
-+#define TITAN_GE_MSTATX_RXINRANGELENGTHERROR         0x0120
-+#define TITAN_GE_MSTATX_RXLONGLENGTHERROR            0x0130
-+#define TITAN_GE_MSTATX_RXLONGLENGTHCRCERROR         0x0140
-+#define TITAN_GE_MSTATX_RXSHORTLENGTHERROR           0x0150
-+#define TITAN_GE_MSTATX_RXSHORTLLENGTHCRCERROR       0x0160
-+#define TITAN_GE_MSTATX_RXFRAMES64OCTETS             0x0170
-+#define TITAN_GE_MSTATX_RXFRAMES65TO127OCTETS        0x0180
-+#define TITAN_GE_MSTATX_RXFRAMES128TO255OCTETS       0x0190
-+#define TITAN_GE_MSTATX_RXFRAMES256TO511OCTETS       0x01A0
-+#define TITAN_GE_MSTATX_RXFRAMES512TO1023OCTETS      0x01B0
-+#define TITAN_GE_MSTATX_RXFRAMES1024TO1518OCTETS     0x01C0
-+#define TITAN_GE_MSTATX_RXFRAMES1519TOMAXSIZE        0x01D0
-+#define TITAN_GE_MSTATX_RXSTATIONADDRESSFILTERED     0x01E0
-+#define TITAN_GE_MSTATX_RXVARIABLE                   0x01F0
-+#define TITAN_GE_MSTATX_GENERICADDRESSFILTERED       0x0200
-+#define TITAN_GE_MSTATX_UNICASTFILTERED              0x0210
-+#define TITAN_GE_MSTATX_MULTICASTFILTERED            0x0220
-+#define TITAN_GE_MSTATX_BROADCASTFILTERED            0x0230
-+#define TITAN_GE_MSTATX_HASHFILTERED                 0x0240
-+#define TITAN_GE_MSTATX_TXFRAMESOK                   0x0250
-+#define TITAN_GE_MSTATX_TXOCTETSOK                   0x0260
-+#define TITAN_GE_MSTATX_TXOCTETS                     0x0270
-+#define TITAN_GE_MSTATX_TXTAGGEDFRAMESOK             0x0280
-+#define TITAN_GE_MSTATX_TXMACPAUSECONTROLFRAMESOK    0x0290
-+#define TITAN_GE_MSTATX_TXFCSERROR                   0x02A0
-+#define TITAN_GE_MSTATX_TXSHORTLENGTHERROR           0x02B0
-+#define TITAN_GE_MSTATX_TXLONGLENGTHERROR            0x02C0
-+#define TITAN_GE_MSTATX_TXSYSTEMERROR                0x02D0
-+#define TITAN_GE_MSTATX_TXMACERROR                   0x02E0
-+#define TITAN_GE_MSTATX_TXCARRIERSENSEERROR          0x02F0
-+#define TITAN_GE_MSTATX_TXSQETESTERROR               0x0300
-+#define TITAN_GE_MSTATX_TXUNICASTFRAMESOK            0x0310
-+#define TITAN_GE_MSTATX_TXBROADCASTFRAMESOK          0x0320
-+#define TITAN_GE_MSTATX_TXMULTICASTFRAMESOK          0x0330
-+#define TITAN_GE_MSTATX_TXUNICASTFRAMESATTEMPTED     0x0340
-+#define TITAN_GE_MSTATX_TXBROADCASTFRAMESATTEMPTED   0x0350
-+#define TITAN_GE_MSTATX_TXMULTICASTFRAMESATTEMPTED   0x0360
-+#define TITAN_GE_MSTATX_TXFRAMES64OCTETS             0x0370
-+#define TITAN_GE_MSTATX_TXFRAMES65TO127OCTETS        0x0380
-+#define TITAN_GE_MSTATX_TXFRAMES128TO255OCTETS       0x0390
-+#define TITAN_GE_MSTATX_TXFRAMES256TO511OCTETS       0x03A0
-+#define TITAN_GE_MSTATX_TXFRAMES512TO1023OCTETS      0x03B0
-+#define TITAN_GE_MSTATX_TXFRAMES1024TO1518OCTETS     0x03C0
-+#define TITAN_GE_MSTATX_TXFRAMES1519TOMAXSIZE        0x03D0
-+#define TITAN_GE_MSTATX_TXVARIABLE                   0x03E0
-+#define TITAN_GE_MSTATX_RXSYSTEMERROR                0x03F0
-+#define TITAN_GE_MSTATX_SINGLECOLLISION              0x0400
-+#define TITAN_GE_MSTATX_MULTIPLECOLLISION            0x0410
-+#define TITAN_GE_MSTATX_DEFERREDXMISSIONS            0x0420
-+#define TITAN_GE_MSTATX_LATECOLLISIONS               0x0430
-+#define TITAN_GE_MSTATX_ABORTEDDUETOXSCOLLS          0x0440
-+
-+/* Interrupt specific defines */
-+#define TITAN_GE_DEVICE_ID         0x0000  /* Device ID */
-+#define TITAN_GE_RESET             0x0004  /* Reset reg */
-+#define TITAN_GE_TSB_CTRL_0        0x000C  /* TSB Control reg 0 */
-+#define TITAN_GE_TSB_CTRL_1        0x0010  /* TSB Control reg 1 */
-+#define TITAN_GE_INTR_GRP0_STATUS  0x0040  /* General Interrupt Group 0 Status */
-+#define TITAN_GE_INTR_XDMA_CORE_A  0x0048  /* XDMA Channel Interrupt Status, Core A*/
-+#define TITAN_GE_INTR_XDMA_CORE_B  0x004C  /* XDMA Channel Interrupt Status, Core B*/
-+#define	TITAN_GE_INTR_XDMA_IE	   0x0058  /* XDMA Channel Interrupt Enable */
-+#define TITAN_GE_SDQPF_ECC_INTR    0x480C  /* SDQPF ECC Interrupt Status */
-+#define TITAN_GE_SDQPF_RXFIFO_CTL  0x4828  /* SDQPF RxFifo Control and Interrupt Enb*/
-+#define TITAN_GE_SDQPF_RXFIFO_INTR 0x482C  /* SDQPF RxFifo Interrupt Status */
-+#define TITAN_GE_SDQPF_TXFIFO_CTL  0x4928  /* SDQPF TxFifo Control and Interrupt Enb*/
-+#define TITAN_GE_SDQPF_TXFIFO_INTR 0x492C  /* SDQPF TxFifo Interrupt Status */
-+#define	TITAN_GE_SDQPF_RXFIFO_0	   0x4840  /* SDQPF RxFIFO Enable */
-+#define	TITAN_GE_SDQPF_TXFIFO_0	   0x4940  /* SDQPF TxFIFO Enable */
-+#define TITAN_GE_XDMA_CONFIG       0x5000  /* XDMA Global Configuration */
-+#define TITAN_GE_XDMA_INTR_SUMMARY 0x5010  /* XDMA Interrupt Summary */
-+#define TITAN_GE_XDMA_BUFADDRPRE   0x5018  /* XDMA Buffer Address Prefix */
-+#define TITAN_GE_XDMA_DESCADDRPRE  0x501C  /* XDMA Descriptor Address Prefix */
-+#define TITAN_GE_XDMA_PORTWEIGHT   0x502C  /* XDMA Port Weight Configuration */
-+
-+/* Rx MAC defines */
-+#define TITAN_GE_RMAC_CONFIG_1               0x1200  /* RMAC Configuration 1 */
-+#define TITAN_GE_RMAC_CONFIG_2               0x1204  /* RMAC Configuration 2 */
-+#define TITAN_GE_RMAC_MAX_FRAME_LEN          0x1208  /* RMAC Max Frame Length */
-+#define TITAN_GE_RMAC_STATION_HI             0x120C  /* Rx Station Address High */
-+#define TITAN_GE_RMAC_STATION_MID            0x1210  /* Rx Station Address Middle */
-+#define TITAN_GE_RMAC_STATION_LOW            0x1214  /* Rx Station Address Low */
-+#define TITAN_GE_RMAC_LINK_CONFIG            0x1218  /* RMAC Link Configuration */
-+
-+/* Tx MAC defines */
-+#define TITAN_GE_TMAC_CONFIG_1               0x1240  /* TMAC Configuration 1 */
-+#define TITAN_GE_TMAC_CONFIG_2               0x1244  /* TMAC Configuration 2 */
-+#define TITAN_GE_TMAC_IPG                    0x1248  /* TMAC Inter-Packet Gap */
-+#define TITAN_GE_TMAC_STATION_HI             0x124C  /* Tx Station Address High */
-+#define TITAN_GE_TMAC_STATION_MID            0x1250  /* Tx Station Address Middle */
-+#define TITAN_GE_TMAC_STATION_LOW            0x1254  /* Tx Station Address Low */
-+#define TITAN_GE_TMAC_MAX_FRAME_LEN          0x1258  /* TMAC Max Frame Length */
-+#define TITAN_GE_TMAC_MIN_FRAME_LEN          0x125C  /* TMAC Min Frame Length */
-+#define TITAN_GE_TMAC_PAUSE_FRAME_TIME       0x1260  /* TMAC Pause Frame Time */
-+#define TITAN_GE_TMAC_PAUSE_FRAME_INTERVAL   0x1264  /* TMAC Pause Frame Interval */
-+
-+/* GMII register */
-+#define TITAN_GE_GMII_INTERRUPT_STATUS       0x1348  /* GMII Interrupt Status */
-+#define TITAN_GE_GMII_CONFIG_GENERAL         0x134C  /* GMII Configuration General */
-+#define TITAN_GE_GMII_CONFIG_MODE            0x1350  /* GMII Configuration Mode */
-+
-+/* Tx and Rx XDMA defines */
-+#define	TITAN_GE_INT_COALESCING		     0x5030 /* Interrupt Coalescing */
-+#define	TITAN_GE_CHANNEL0_CONFIG	     0x5040 /* Channel 0 XDMA config */
-+#define	TITAN_GE_CHANNEL0_INTERRUPT	     0x504c /* Channel 0 Interrupt Status */
-+#define	TITAN_GE_GDI_INTERRUPT_ENABLE        0x5050 /* IE for the GDI Errors */
-+#define	TITAN_GE_CHANNEL0_PACKET	     0x5060 /* Channel 0 Packet count */
-+#define	TITAN_GE_CHANNEL0_BYTE		     0x5064 /* Channel 0 Byte count */
-+#define	TITAN_GE_CHANNEL0_TX_DESC	     0x5054 /* Channel 0 Tx first desc */
-+#define	TITAN_GE_CHANNEL0_RX_DESC	     0x5058 /* Channel 0 Rx first desc */
-+
-+/* AFX (Address Filter Exact) register offsets for Slice 0 */
-+#define TITAN_GE_AFX_EXACT_MATCH_LOW         0x1100  /* AFX Exact Match Address Low*/
-+#define TITAN_GE_AFX_EXACT_MATCH_MID         0x1104  /* AFX Exact Match Address Mid*/
-+#define TITAN_GE_AFX_EXACT_MATCH_HIGH        0x1108  /* AFX Exact Match Address Hi */
-+#define TITAN_GE_AFX_EXACT_MATCH_VID         0x110C  /* AFX Exact Match VID */
-+#define TITAN_GE_AFX_MULTICAST_HASH_LOW      0x1110  /* AFX Multicast HASH Low */
-+#define TITAN_GE_AFX_MULTICAST_HASH_MIDLOW   0x1114  /* AFX Multicast HASH MidLow */
-+#define TITAN_GE_AFX_MULTICAST_HASH_MIDHI    0x1118  /* AFX Multicast HASH MidHi */
-+#define TITAN_GE_AFX_MULTICAST_HASH_HI       0x111C  /* AFX Multicast HASH Hi */
-+#define TITAN_GE_AFX_ADDRS_FILTER_CTRL_0     0x1120  /* AFX Address Filter Ctrl 0 */
-+#define TITAN_GE_AFX_ADDRS_FILTER_CTRL_1     0x1124  /* AFX Address Filter Ctrl 1 */
-+#define TITAN_GE_AFX_ADDRS_FILTER_CTRL_2     0x1128  /* AFX Address Filter Ctrl 2 */
-+
-+/* Traffic Groomer block */
-+#define        TITAN_GE_TRTG_CONFIG	     0x1000  /* TRTG Config */
-+
-+#endif 				/* _TITAN_GE_H_ */
-+
-diff -Naur linux-2.6.17.orig/drivers/net/titan_mdio.c linux-2.6.17/drivers/net/titan_mdio.c
---- linux-2.6.17.orig/drivers/net/titan_mdio.c	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/drivers/net/titan_mdio.c	2006-06-19 18:16:13.000000000 -0700
-@@ -0,0 +1,217 @@
-+/*
-+ * drivers/net/titan_mdio.c - Driver for Titan ethernet ports
-+ *
-+ * Copyright (C) 2003 PMC-Sierra Inc.
-+ * Author : Manish Lachwani (lachwani@pmc-sierra.com)
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * as published by the Free Software Foundation; either version 2
-+ * of the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
-+ *
-+ * Management Data IO (MDIO) driver for the Titan GMII. Interacts with the Marvel PHY
-+ * on the Titan. No support for the TBI as yet.
-+ *
-+ */
-+
-+#include	"titan_mdio.h"
-+
-+#define MDIO_DEBUG
-+
-+/*
-+ * Local constants
-+ */
-+#define MAX_CLKA            1023
-+#define MAX_PHY_DEV         31
-+#define MAX_PHY_REG         31
-+#define WRITEADDRS_OPCODE   0x0
-+#define	READ_OPCODE	    0x2
-+#define WRITE_OPCODE        0x1
-+#define MAX_MDIO_POLL       100
-+
-+/*
-+ * Titan MDIO and SCMB registers
-+ */
-+#define TITAN_GE_SCMB_CONTROL                0x01c0  /* SCMB Control */
-+#define TITAN_GE_SCMB_CLKA	             0x01c4  /* SCMB Clock A */
-+#define TITAN_GE_MDIO_COMMAND                0x01d0  /* MDIO Command */
-+#define TITAN_GE_MDIO_DEVICE_PORT_ADDRESS    0x01d4  /* MDIO Device and Port addrs */
-+#define TITAN_GE_MDIO_DATA                   0x01d8  /* MDIO Data */
-+#define TITAN_GE_MDIO_INTERRUPTS             0x01dC  /* MDIO Interrupts */
-+
-+/*
-+ * Function to poll the MDIO
-+ */
-+static int titan_ge_mdio_poll(void)
-+{
-+	int	i, val;
-+
-+	for (i = 0; i < MAX_MDIO_POLL; i++) {
-+		val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_COMMAND);
-+
-+		if (!(val & 0x8000))
-+			return TITAN_GE_MDIO_GOOD;
-+	}
-+
-+	return TITAN_GE_MDIO_ERROR;
-+}
-+
-+
-+/*
-+ * Initialize and configure the MDIO
-+ */
-+int titan_ge_mdio_setup(titan_ge_mdio_config *titan_mdio)
-+{
-+	unsigned long	val;
-+
-+	/* Reset the SCMB and program into MDIO mode*/
-+	TITAN_GE_MDIO_WRITE(TITAN_GE_SCMB_CONTROL, 0x9000);
-+	TITAN_GE_MDIO_WRITE(TITAN_GE_SCMB_CONTROL, 0x1000);
-+
-+	/* CLK A */
-+	val = TITAN_GE_MDIO_READ(TITAN_GE_SCMB_CLKA);
-+	val = ( (val & ~(0x03ff)) | (titan_mdio->clka & 0x03ff));
-+	TITAN_GE_MDIO_WRITE(TITAN_GE_SCMB_CLKA, val);
-+
-+	/* Preamble Suppresion */
-+	val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_COMMAND);
-+	val = ( (val & ~(0x0001)) | (titan_mdio->mdio_spre & 0x0001));
-+	TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_COMMAND, val);
-+
-+	/* MDIO mode */
-+	val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS);
-+	val = ( (val & ~(0x4000)) | (titan_mdio->mdio_mode & 0x4000));
-+	TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS, val);
-+
-+	return TITAN_GE_MDIO_GOOD;
-+}
-+
-+/*
-+ * Set the PHY address in indirect mode
-+ */
-+int titan_ge_mdio_inaddrs(int dev_addr, int reg_addr)
-+{
-+	volatile unsigned long	val;
-+
-+	/* Setup the PHY device */
-+	val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS);
-+	val = ( (val & ~(0x1f00)) | ( (dev_addr << 8) & 0x1f00));
-+	val = ( (val & ~(0x001f)) | ( reg_addr & 0x001f));
-+	TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS, val);
-+
-+	/* Write the new address */
-+	val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_COMMAND);
-+	val = ( (val & ~(0x0300)) | ( (WRITEADDRS_OPCODE << 8) & 0x0300));
-+	TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_COMMAND, val);
-+
-+	return TITAN_GE_MDIO_GOOD;
-+}
-+
-+/*
-+ * Read the MDIO register. This is what the individual parametes mean:
-+ *
-+ * dev_addr : PHY ID
-+ * reg_addr : register offset
-+ *
-+ * See the spec for the Titan MAC. We operate in the Direct Mode.
-+ */
-+
-+#define MAX_RETRIES	2
-+
-+int titan_ge_mdio_read(int dev_addr, int reg_addr, unsigned int *pdata)
-+{
-+	volatile unsigned long	val;
-+	int retries = 0;
-+
-+	/* Setup the PHY device */
-+
-+again:
-+	val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS);
-+	val = ( (val & ~(0x1f00)) | ( (dev_addr << 8) & 0x1f00));
-+	val = ( (val & ~(0x001f)) | ( reg_addr & 0x001f));
-+	val |= 0x4000;
-+	TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS, val);
-+
-+	udelay(30);
-+
-+	/* Issue the read command */
-+	val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_COMMAND);
-+	val = ( (val & ~(0x0300)) | ( (READ_OPCODE << 8) & 0x0300));
-+	TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_COMMAND, val);
-+
-+	udelay(30);
-+
-+	if (titan_ge_mdio_poll() != TITAN_GE_MDIO_GOOD)
-+		return TITAN_GE_MDIO_ERROR;
-+
-+	*pdata = (unsigned int)TITAN_GE_MDIO_READ(TITAN_GE_MDIO_DATA);
-+	val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_INTERRUPTS);
-+
-+	udelay(30);
-+
-+	if (val & 0x2) {
-+		if (retries == MAX_RETRIES)
-+			return TITAN_GE_MDIO_ERROR;
-+		else {
-+			retries++;
-+			goto again;
-+		}
-+	}
-+
-+	return TITAN_GE_MDIO_GOOD;
-+}
-+
-+/*
-+ * Write to the MDIO register
-+ *
-+ * dev_addr : PHY ID
-+ * reg_addr : register that needs to be written to
-+ *
-+ */
-+int titan_ge_mdio_write(int dev_addr, int reg_addr, unsigned int data)
-+{
-+	volatile unsigned long	val;
-+
-+	if (titan_ge_mdio_poll() != TITAN_GE_MDIO_GOOD)
-+		return TITAN_GE_MDIO_ERROR;
-+
-+	/* Setup the PHY device */
-+	val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS);
-+	val = ( (val & ~(0x1f00)) | ( (dev_addr << 8) & 0x1f00));
-+	val = ( (val & ~(0x001f)) | ( reg_addr & 0x001f));
-+	val |= 0x4000;
-+	TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS, val);
-+
-+	udelay(30);
-+
-+	/* Setup the data to write */
-+	TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_DATA, data);
-+
-+	udelay(30);
-+
-+	/* Issue the write command */
-+	val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_COMMAND);
-+	val = ( (val & ~(0x0300)) | ( (WRITE_OPCODE << 8) & 0x0300));
-+	TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_COMMAND, val);
-+
-+	udelay(30);
-+
-+	if (titan_ge_mdio_poll() != TITAN_GE_MDIO_GOOD)
-+		return TITAN_GE_MDIO_ERROR;
-+
-+	val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_INTERRUPTS);
-+	if (val & 0x2)
-+		return TITAN_GE_MDIO_ERROR;
-+
-+	return TITAN_GE_MDIO_GOOD;
-+}
-+
-diff -Naur linux-2.6.17.orig/drivers/net/titan_mdio.h linux-2.6.17/drivers/net/titan_mdio.h
---- linux-2.6.17.orig/drivers/net/titan_mdio.h	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/drivers/net/titan_mdio.h	2006-06-19 18:16:13.000000000 -0700
-@@ -0,0 +1,56 @@
-+/*
-+ * MDIO used to interact with the PHY when using GMII/MII
-+ */
-+#ifndef _TITAN_MDIO_H
-+#define _TITAN_MDIO_H
-+
-+#include <linux/netdevice.h>
-+#include <linux/workqueue.h>
-+#include <linux/delay.h>
-+#include "titan_ge.h"
-+
-+
-+#define	TITAN_GE_MDIO_ERROR	(-9000)
-+#define	TITAN_GE_MDIO_GOOD	0
-+
-+#define	TITAN_GE_MDIO_BASE		titan_ge_base
-+
-+#define	TITAN_GE_MDIO_READ(offset)	\
-+	*(volatile u32 *)(titan_ge_base + (offset))
-+
-+#define	TITAN_GE_MDIO_WRITE(offset, data)	\
-+	*(volatile u32 *)(titan_ge_base + (offset)) = (data)
-+
-+
-+/* GMII specific registers */
-+#define	TITAN_GE_MARVEL_PHY_ID		0x00
-+#define	TITAN_PHY_AUTONEG_ADV		0x04
-+#define	TITAN_PHY_LP_ABILITY		0x05
-+#define	TITAN_GE_MDIO_MII_CTRL		0x09
-+#define	TITAN_GE_MDIO_MII_EXTENDED	0x0f
-+#define	TITAN_GE_MDIO_PHY_CTRL		0x10
-+#define	TITAN_GE_MDIO_PHY_STATUS	0x11
-+#define	TITAN_GE_MDIO_PHY_IE		0x12
-+#define	TITAN_GE_MDIO_PHY_IS		0x13
-+#define	TITAN_GE_MDIO_PHY_LED		0x18
-+#define	TITAN_GE_MDIO_PHY_LED_OVER	0x19
-+#define	PHY_ANEG_TIME_WAIT		45	/* 45 seconds wait time */
-+
-+/*
-+ * MDIO Config Structure
-+ */
-+typedef struct {
-+	unsigned int		clka;
-+	int			mdio_spre;
-+	int			mdio_mode;
-+} titan_ge_mdio_config;
-+
-+/*
-+ * Function Prototypes
-+ */
-+int titan_ge_mdio_setup(titan_ge_mdio_config *);
-+int titan_ge_mdio_inaddrs(int, int);
-+int titan_ge_mdio_read(int, int, unsigned int *);
-+int titan_ge_mdio_write(int, int, unsigned int);
-+
-+#endif /* _TITAN_MDIO_H */
-diff -Naur linux-2.6.17.orig/drivers/net/tulip/tulip_core.c linux-2.6.17/drivers/net/tulip/tulip_core.c
---- linux-2.6.17.orig/drivers/net/tulip/tulip_core.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/drivers/net/tulip/tulip_core.c	2006-06-19 18:16:13.000000000 -0700
-@@ -1483,14 +1483,6 @@
- 			sa_offset = 2;		/* Grrr, damn Matrox boards. */
- 			multiport_cnt = 4;
- 		}
--#ifdef CONFIG_DDB5476
--		if ((pdev->bus->number == 0) && (PCI_SLOT(pdev->devfn) == 6)) {
--			/* DDB5476 MAC address in first EEPROM locations. */
--                       sa_offset = 0;
--                       /* No media table either */
--                       tp->flags &= ~HAS_MEDIA_TABLE;
--               }
--#endif
- #ifdef CONFIG_DDB5477
-                if ((pdev->bus->number == 0) && (PCI_SLOT(pdev->devfn) == 4)) {
-                        /* DDB5477 MAC address in first EEPROM locations. */
-diff -Naur linux-2.6.17.orig/drivers/scsi/dec_esp.c linux-2.6.17/drivers/scsi/dec_esp.c
---- linux-2.6.17.orig/drivers/scsi/dec_esp.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/drivers/scsi/dec_esp.c	2006-06-19 18:16:13.000000000 -0700
-@@ -55,7 +55,7 @@
- 
- static int  dma_bytes_sent(struct NCR_ESP *esp, int fifo_count);
- static void dma_drain(struct NCR_ESP *esp);
--static int  dma_can_transfer(struct NCR_ESP *esp, struct scsi_cmnd *sp);
-+static int  dma_can_transfer(struct NCR_ESP *esp, struct scsi_cmnd * sp);
- static void dma_dump_state(struct NCR_ESP *esp);
- static void dma_init_read(struct NCR_ESP *esp, u32 vaddress, int length);
- static void dma_init_write(struct NCR_ESP *esp, u32 vaddress, int length);
-@@ -230,7 +230,7 @@
- 			mem_start = get_tc_base_addr(slot);
- 
- 			/* Store base addr into esp struct */
--			esp->slot = CPHYSADDR(mem_start);
-+			esp->slot = mem_start;
- 
- 			esp->dregs = 0;
- 			esp->eregs = (void *)CKSEG1ADDR(mem_start +
-diff -Naur linux-2.6.17.orig/drivers/scsi/NCR53C9x.h linux-2.6.17/drivers/scsi/NCR53C9x.h
---- linux-2.6.17.orig/drivers/scsi/NCR53C9x.h	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/drivers/scsi/NCR53C9x.h	2006-06-19 18:16:13.000000000 -0700
-@@ -145,12 +145,7 @@
- 
- #ifndef MULTIPLE_PAD_SIZES
- 
--#ifdef CONFIG_CPU_HAS_WB
--#include <asm/wbflush.h>
--#define esp_write(__reg, __val) do{(__reg) = (__val); wbflush();} while(0)
--#else
--#define esp_write(__reg, __val) ((__reg) = (__val))
--#endif
-+#define esp_write(__reg, __val) do{(__reg) = (__val); iob();} while(0)
- #define esp_read(__reg) (__reg)
- 
- struct ESP_regs {
-diff -Naur linux-2.6.17.orig/drivers/scsi/sgiwd93.c linux-2.6.17/drivers/scsi/sgiwd93.c
---- linux-2.6.17.orig/drivers/scsi/sgiwd93.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/drivers/scsi/sgiwd93.c	2006-06-19 18:16:13.000000000 -0700
-@@ -14,6 +14,7 @@
- #include <linux/interrupt.h>
- #include <linux/types.h>
- #include <linux/mm.h>
-+#include <linux/module.h>
- #include <linux/blkdev.h>
- #include <linux/delay.h>
- #include <linux/dma-mapping.h>
-@@ -197,6 +198,7 @@
- 	udelay(50);
- 	hregs->ctrl = 0;
- }
-+EXPORT_SYMBOL_GPL(sgiwd93_reset);
- 
- static inline void init_hpc_chain(struct hpc_data *hd)
- {
-diff -Naur linux-2.6.17.orig/drivers/serial/ip22zilog.c linux-2.6.17/drivers/serial/ip22zilog.c
---- linux-2.6.17.orig/drivers/serial/ip22zilog.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/drivers/serial/ip22zilog.c	2006-06-19 18:16:13.000000000 -0700
-@@ -866,6 +866,7 @@
- 	up->cflag = termios->c_cflag;
- 
- 	ip22zilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port));
-+	uart_update_timeout(port, termios->c_cflag, baud);
- 
- 	spin_unlock_irqrestore(&up->port.lock, flags);
- }
-@@ -1027,6 +1028,8 @@
- 	}
- 
- 	con->cflag = cflag | CS8;			/* 8N1 */
-+
-+	uart_update_timeout(&ip22zilog_port_table[con->index].port, cflag, baud);
- }
- 
- static int __init ip22zilog_console_setup(struct console *con, char *options)
-diff -Naur linux-2.6.17.orig/drivers/serial/ip3106_uart.c linux-2.6.17/drivers/serial/ip3106_uart.c
---- linux-2.6.17.orig/drivers/serial/ip3106_uart.c	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/drivers/serial/ip3106_uart.c	2006-06-19 18:16:13.000000000 -0700
-@@ -0,0 +1,912 @@
-+/*
-+ * Initially based on linux-2.4.20_mvl31-pnx8xx0/drivers/char/serial_pnx8550.c
-+ *
-+ * Complete rewrite to drivers/serial/pnx8550_uart.c by
-+ * Embedded Alley Solutions, source@embeddedalley.com as part of the
-+ * PNX8550 2.6 port, and then drivers/serial/ip3106_uart.c to work
-+ * with other Philips SoCs.
-+ *
-+ * Existing copyrights from files used to write this driver:
-+ * Author: Per Hallsmark per.hallsmark@mvista.com
-+ *
-+ * and
-+ *
-+ * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
-+ * Copyright (C) 2000 Deep Blue Solutions Ltd.
-+ *
-+ */
-+
-+#include <linux/config.h>
-+
-+#if defined(CONFIG_SERIAL_IP3106_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
-+#define SUPPORT_SYSRQ
-+#endif
-+
-+#include <linux/module.h>
-+#include <linux/ioport.h>
-+#include <linux/init.h>
-+#include <linux/console.h>
-+#include <linux/sysrq.h>
-+#include <linux/device.h>
-+#include <linux/tty.h>
-+#include <linux/tty_flip.h>
-+#include <linux/serial_core.h>
-+#include <linux/serial.h>
-+#include <linux/serial_ip3106.h>
-+
-+#include <asm/io.h>
-+#include <asm/irq.h>
-+
-+#include <uart.h>
-+
-+/* We've been assigned a range on the "Low-density serial ports" major */
-+#define SERIAL_IP3106_MAJOR	204
-+#define MINOR_START		5
-+
-+#define NR_PORTS		2
-+
-+#define IP3106_ISR_PASS_LIMIT	256
-+
-+/*
-+ * Convert from ignore_status_mask or read_status_mask to FIFO
-+ * and interrupt status bits
-+ */
-+#define SM_TO_FIFO(x)	((x) >> 10)
-+#define SM_TO_ISTAT(x)	((x) & 0x000001ff)
-+#define FIFO_TO_SM(x)	((x) << 10)
-+#define ISTAT_TO_SM(x)	((x) & 0x000001ff)
-+
-+/*
-+ * This is the size of our serial port register set.
-+ */
-+#define UART_PORT_SIZE	0x1000
-+
-+/*
-+ * This determines how often we check the modem status signals
-+ * for any change.  They generally aren't connected to an IRQ
-+ * so we have to poll them.  We also check immediately before
-+ * filling the TX fifo incase CTS has been dropped.
-+ */
-+#define MCTRL_TIMEOUT	(250*HZ/1000)
-+
-+
-+extern struct ip3106_port ip3106_ports[];
-+
-+static inline int serial_in(struct ip3106_port *sport, int offset)
-+{
-+	return (__raw_readl(sport->port.membase + offset));
-+}
-+
-+static inline void serial_out(struct ip3106_port *sport, int offset, int value)
-+{
-+	__raw_writel(value, sport->port.membase + offset);
-+}
-+
-+/*
-+ * Handle any change of modem status signal since we were last called.
-+ */
-+static void ip3106_mctrl_check(struct ip3106_port *sport)
-+{
-+	unsigned int status, changed;
-+
-+	status = sport->port.ops->get_mctrl(&sport->port);
-+	changed = status ^ sport->old_status;
-+
-+	if (changed == 0)
-+		return;
-+
-+	sport->old_status = status;
-+
-+	if (changed & TIOCM_RI)
-+		sport->port.icount.rng++;
-+	if (changed & TIOCM_DSR)
-+		sport->port.icount.dsr++;
-+	if (changed & TIOCM_CAR)
-+		uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
-+	if (changed & TIOCM_CTS)
-+		uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
-+
-+	wake_up_interruptible(&sport->port.info->delta_msr_wait);
-+}
-+
-+/*
-+ * This is our per-port timeout handler, for checking the
-+ * modem status signals.
-+ */
-+static void ip3106_timeout(unsigned long data)
-+{
-+	struct ip3106_port *sport = (struct ip3106_port *)data;
-+	unsigned long flags;
-+
-+	if (sport->port.info) {
-+		spin_lock_irqsave(&sport->port.lock, flags);
-+		ip3106_mctrl_check(sport);
-+		spin_unlock_irqrestore(&sport->port.lock, flags);
-+
-+		mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
-+	}
-+}
-+
-+/*
-+ * interrupts disabled on entry
-+ */
-+static void ip3106_stop_tx(struct uart_port *port, unsigned int tty_stop)
-+{
-+	struct ip3106_port *sport = (struct ip3106_port *)port;
-+	u32 ien;
-+
-+	/* Disable TX intr */
-+	ien = serial_in(sport, IP3106_IEN);
-+	serial_out(sport, IP3106_IEN, ien & ~IP3106_UART_INT_ALLTX);
-+
-+	/* Clear all pending TX intr */
-+	serial_out(sport, IP3106_ICLR, IP3106_UART_INT_ALLTX);
-+}
-+
-+/*
-+ * interrupts may not be disabled on entry
-+ */
-+static void ip3106_start_tx(struct uart_port *port, unsigned int tty_start)
-+{
-+	struct ip3106_port *sport = (struct ip3106_port *)port;
-+	unsigned long flags;
-+	u32 ien;
-+
-+	spin_lock_irqsave(&sport->port.lock, flags);
-+
-+	/* Clear all pending TX intr */
-+	serial_out(sport, IP3106_ICLR, IP3106_UART_INT_ALLTX);
-+
-+	/* Enable TX intr */
-+	ien = serial_in(sport, IP3106_IEN);
-+	serial_out(sport, IP3106_IEN, ien | IP3106_UART_INT_ALLTX);
-+
-+	spin_unlock_irqrestore(&sport->port.lock, flags);
-+}
-+
-+/*
-+ * Interrupts enabled
-+ */
-+static void ip3106_stop_rx(struct uart_port *port)
-+{
-+	struct ip3106_port *sport = (struct ip3106_port *)port;
-+	u32 ien;
-+
-+	/* Disable RX intr */
-+	ien = serial_in(sport, IP3106_IEN);
-+	serial_out(sport, IP3106_IEN, ien & ~IP3106_UART_INT_ALLRX);
-+
-+	/* Clear all pending RX intr */
-+	serial_out(sport, IP3106_ICLR, IP3106_UART_INT_ALLRX);
-+}
-+
-+/*
-+ * Set the modem control timer to fire immediately.
-+ */
-+static void ip3106_enable_ms(struct uart_port *port)
-+{
-+	struct ip3106_port *sport = (struct ip3106_port *)port;
-+
-+	mod_timer(&sport->timer, jiffies);
-+}
-+
-+static void
-+ip3106_rx_chars(struct ip3106_port *sport, struct pt_regs *regs)
-+{
-+	struct tty_struct *tty = sport->port.info->tty;
-+	unsigned int status, ch, flg, ignored = 0;
-+
-+	status = FIFO_TO_SM(serial_in(sport, IP3106_FIFO)) |
-+		 ISTAT_TO_SM(serial_in(sport, IP3106_ISTAT));
-+	while (status & FIFO_TO_SM(IP3106_UART_FIFO_RXFIFO)) {
-+		ch = serial_in(sport, IP3106_FIFO);
-+
-+		if (tty->flip.count >= TTY_FLIPBUF_SIZE)
-+			goto ignore_char;
-+		sport->port.icount.rx++;
-+
-+		flg = TTY_NORMAL;
-+
-+		/*
-+		 * note that the error handling code is
-+		 * out of the main execution path
-+		 */
-+		if (status & FIFO_TO_SM(IP3106_UART_FIFO_RXFE |
-+					IP3106_UART_FIFO_RXPAR))
-+			goto handle_error;
-+
-+		if (uart_handle_sysrq_char(&sport->port, ch, regs))
-+			goto ignore_char;
-+
-+	error_return:
-+		tty_insert_flip_char(tty, ch, flg);
-+	ignore_char:
-+		serial_out(sport, IP3106_LCR, serial_in(sport, IP3106_LCR) |
-+				IP3106_UART_LCR_RX_NEXT);
-+		status = FIFO_TO_SM(serial_in(sport, IP3106_FIFO)) |
-+			 ISTAT_TO_SM(serial_in(sport, IP3106_ISTAT));
-+	}
-+ out:
-+	tty_flip_buffer_push(tty);
-+	return;
-+
-+ handle_error:
-+	if (status & FIFO_TO_SM(IP3106_UART_FIFO_RXPAR))
-+		sport->port.icount.parity++;
-+	else if (status & FIFO_TO_SM(IP3106_UART_FIFO_RXFE))
-+		sport->port.icount.frame++;
-+	if (status & ISTAT_TO_SM(IP3106_UART_INT_RXOVRN))
-+		sport->port.icount.overrun++;
-+
-+	if (status & sport->port.ignore_status_mask) {
-+		if (++ignored > 100)
-+			goto out;
-+		goto ignore_char;
-+	}
-+
-+//	status &= sport->port.read_status_mask;
-+
-+	if (status & FIFO_TO_SM(IP3106_UART_FIFO_RXPAR))
-+		flg = TTY_PARITY;
-+	else if (status & FIFO_TO_SM(IP3106_UART_FIFO_RXFE))
-+		flg = TTY_FRAME;
-+
-+	if (status & ISTAT_TO_SM(IP3106_UART_INT_RXOVRN)) {
-+		/*
-+		 * overrun does *not* affect the character
-+		 * we read from the FIFO
-+		 */
-+		tty_insert_flip_char(tty, ch, flg);
-+		ch = 0;
-+		flg = TTY_OVERRUN;
-+	}
-+#ifdef SUPPORT_SYSRQ
-+	sport->port.sysrq = 0;
-+#endif
-+	goto error_return;
-+}
-+
-+static void ip3106_tx_chars(struct ip3106_port *sport)
-+{
-+	struct circ_buf *xmit = &sport->port.info->xmit;
-+
-+	if (sport->port.x_char) {
-+		serial_out(sport, IP3106_FIFO, sport->port.x_char);
-+		sport->port.icount.tx++;
-+		sport->port.x_char = 0;
-+		return;
-+	}
-+
-+	/*
-+	 * Check the modem control lines before
-+	 * transmitting anything.
-+	 */
-+	ip3106_mctrl_check(sport);
-+
-+	if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
-+		ip3106_stop_tx(&sport->port, 0);
-+		return;
-+	}
-+
-+	/*
-+	 * TX while bytes available
-+	 */
-+	while (((serial_in(sport, IP3106_FIFO) &
-+					IP3106_UART_FIFO_TXFIFO) >> 16) < 16) {
-+		serial_out(sport, IP3106_FIFO, xmit->buf[xmit->tail]);
-+		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
-+		sport->port.icount.tx++;
-+		if (uart_circ_empty(xmit))
-+			break;
-+	}
-+
-+	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
-+		uart_write_wakeup(&sport->port);
-+
-+	if (uart_circ_empty(xmit))
-+		ip3106_stop_tx(&sport->port, 0);
-+}
-+
-+static irqreturn_t ip3106_int(int irq, void *dev_id, struct pt_regs *regs)
-+{
-+	struct ip3106_port *sport = dev_id;
-+	unsigned int status;
-+
-+	spin_lock(&sport->port.lock);
-+	/* Get the interrupts */
-+	status  = serial_in(sport, IP3106_ISTAT) & serial_in(sport, IP3106_IEN);
-+
-+	/* RX Receiver Holding Register Overrun */
-+	if (status & IP3106_UART_INT_RXOVRN) {
-+		sport->port.icount.overrun++;
-+		serial_out(sport, IP3106_ICLR, IP3106_UART_INT_RXOVRN);
-+	}
-+
-+	/* RX Frame Error */
-+	if (status & IP3106_UART_INT_FRERR) {
-+		sport->port.icount.frame++;
-+		serial_out(sport, IP3106_ICLR, IP3106_UART_INT_FRERR);
-+	}
-+
-+	/* Break signal received */
-+	if (status & IP3106_UART_INT_BREAK) {
-+		sport->port.icount.brk++;
-+		serial_out(sport, IP3106_ICLR, IP3106_UART_INT_BREAK);
-+	}
-+
-+	/* RX Parity Error */
-+	if (status & IP3106_UART_INT_PARITY) {
-+		sport->port.icount.parity++;
-+		serial_out(sport, IP3106_ICLR, IP3106_UART_INT_PARITY);
-+	}
-+
-+	/* Byte received */
-+	if (status & IP3106_UART_INT_RX) {
-+		ip3106_rx_chars(sport, regs);
-+		serial_out(sport, IP3106_ICLR, IP3106_UART_INT_RX);
-+	}
-+
-+	/* TX holding register empty - transmit a byte */
-+	if (status & IP3106_UART_INT_TX) {
-+		ip3106_tx_chars(sport);
-+		serial_out(sport, IP3106_ICLR, IP3106_UART_INT_TX);
-+	}
-+
-+	/* TX shift register and holding register empty  */
-+	if (status & IP3106_UART_INT_EMPTY) {
-+		serial_out(sport, IP3106_ICLR, IP3106_UART_INT_EMPTY);
-+	}
-+
-+	/* Receiver time out */
-+	if (status & IP3106_UART_INT_RCVTO) {
-+		serial_out(sport, IP3106_ICLR, IP3106_UART_INT_RCVTO);
-+	}
-+	spin_unlock(&sport->port.lock);
-+	return IRQ_HANDLED;
-+}
-+
-+/*
-+ * Return TIOCSER_TEMT when transmitter is not busy.
-+ */
-+static unsigned int ip3106_tx_empty(struct uart_port *port)
-+{
-+	struct ip3106_port *sport = (struct ip3106_port *)port;
-+
-+	return serial_in(sport, IP3106_FIFO) & IP3106_UART_FIFO_TXFIFO_STA ? 0 : TIOCSER_TEMT;
-+}
-+
-+static unsigned int ip3106_get_mctrl(struct uart_port *port)
-+{
-+	struct ip3106_port *sport = (struct ip3106_port *)port;
-+	unsigned int mctrl = TIOCM_DSR;
-+	unsigned int msr;
-+
-+	/* REVISIT */
-+
-+	msr = serial_in(sport, IP3106_MCR);
-+
-+	mctrl |= msr & IP3106_UART_MCR_CTS ? TIOCM_CTS : 0;
-+	mctrl |= msr & IP3106_UART_MCR_DCD ? TIOCM_CAR : 0;
-+
-+	return mctrl;
-+}
-+
-+static void ip3106_set_mctrl(struct uart_port *port, unsigned int mctrl)
-+{
-+#if	0	/* FIXME */
-+	struct ip3106_port *sport = (struct ip3106_port *)port;
-+	unsigned int msr;
-+#endif
-+}
-+
-+/*
-+ * Interrupts always disabled.
-+ */
-+static void ip3106_break_ctl(struct uart_port *port, int break_state)
-+{
-+	struct ip3106_port *sport = (struct ip3106_port *)port;
-+	unsigned long flags;
-+	unsigned int lcr;
-+
-+	spin_lock_irqsave(&sport->port.lock, flags);
-+	lcr = serial_in(sport, IP3106_LCR);
-+	if (break_state == -1)
-+		lcr |= IP3106_UART_LCR_TXBREAK;
-+	else
-+		lcr &= ~IP3106_UART_LCR_TXBREAK;
-+	serial_out(sport, IP3106_LCR, lcr);
-+	spin_unlock_irqrestore(&sport->port.lock, flags);
-+}
-+
-+static int ip3106_startup(struct uart_port *port)
-+{
-+	struct ip3106_port *sport = (struct ip3106_port *)port;
-+	int retval;
-+
-+	/*
-+	 * Allocate the IRQ
-+	 */
-+	retval = request_irq(sport->port.irq, ip3106_int, 0,
-+			     "ip3106-uart", sport);
-+	if (retval)
-+		return retval;
-+
-+	/*
-+	 * Finally, clear and enable interrupts
-+	 */
-+
-+	serial_out(sport, IP3106_ICLR, IP3106_UART_INT_ALLRX |
-+			     IP3106_UART_INT_ALLTX);
-+
-+	serial_out(sport, IP3106_IEN, serial_in(sport, IP3106_IEN) |
-+			    IP3106_UART_INT_ALLRX |
-+			    IP3106_UART_INT_ALLTX);
-+
-+	/*
-+	 * Enable modem status interrupts
-+	 */
-+	spin_lock_irq(&sport->port.lock);
-+	ip3106_enable_ms(&sport->port);
-+	spin_unlock_irq(&sport->port.lock);
-+
-+	return 0;
-+}
-+
-+static void ip3106_shutdown(struct uart_port *port)
-+{
-+	struct ip3106_port *sport = (struct ip3106_port *)port;
-+
-+	/*
-+	 * Stop our timer.
-+	 */
-+	del_timer_sync(&sport->timer);
-+
-+	/*
-+	 * Disable all interrupts, port and break condition.
-+	 */
-+	serial_out(sport, IP3106_IEN, 0);
-+
-+	/*
-+	 * Reset the Tx and Rx FIFOS
-+	 */
-+	serial_out(sport, IP3106_LCR, serial_in(sport, IP3106_LCR) |
-+			    IP3106_UART_LCR_TX_RST |
-+			    IP3106_UART_LCR_RX_RST);
-+
-+	/*
-+	 * Clear all interrupts
-+	 */
-+	serial_out(sport, IP3106_ICLR, IP3106_UART_INT_ALLRX |
-+			     IP3106_UART_INT_ALLTX);
-+
-+	/*
-+	 * Free the interrupt
-+	 */
-+	free_irq(sport->port.irq, sport);
-+}
-+
-+static void
-+ip3106_set_termios(struct uart_port *port, struct termios *termios,
-+		   struct termios *old)
-+{
-+	struct ip3106_port *sport = (struct ip3106_port *)port;
-+	unsigned long flags;
-+	unsigned int lcr_fcr, old_ien, baud, quot;
-+	unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
-+
-+	/*
-+	 * We only support CS7 and CS8.
-+	 */
-+	while ((termios->c_cflag & CSIZE) != CS7 &&
-+	       (termios->c_cflag & CSIZE) != CS8) {
-+		termios->c_cflag &= ~CSIZE;
-+		termios->c_cflag |= old_csize;
-+		old_csize = CS8;
-+	}
-+
-+	if ((termios->c_cflag & CSIZE) == CS8)
-+		lcr_fcr = IP3106_UART_LCR_8BIT;
-+	else
-+		lcr_fcr = 0;
-+
-+	if (termios->c_cflag & CSTOPB)
-+		lcr_fcr |= IP3106_UART_LCR_2STOPB;
-+	if (termios->c_cflag & PARENB) {
-+		lcr_fcr |= IP3106_UART_LCR_PAREN;
-+		if (!(termios->c_cflag & PARODD))
-+			lcr_fcr |= IP3106_UART_LCR_PAREVN;
-+	}
-+
-+	/*
-+	 * Ask the core to calculate the divisor for us.
-+	 */
-+	baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
-+	quot = uart_get_divisor(port, baud);
-+
-+	spin_lock_irqsave(&sport->port.lock, flags);
-+
-+#if	0	/* REVISIT */
-+	sport->port.read_status_mask &= UTSR0_TO_SM(UTSR0_TFS);
-+	sport->port.read_status_mask |= UTSR1_TO_SM(UTSR1_ROR);
-+	if (termios->c_iflag & INPCK)
-+		sport->port.read_status_mask |=
-+				UTSR1_TO_SM(UTSR1_FRE | UTSR1_PRE);
-+	if (termios->c_iflag & (BRKINT | PARMRK))
-+		sport->port.read_status_mask |=
-+				UTSR0_TO_SM(UTSR0_RBB | UTSR0_REB);
-+
-+	/*
-+	 * Characters to ignore
-+	 */
-+	sport->port.ignore_status_mask = 0;
-+	if (termios->c_iflag & IGNPAR)
-+		sport->port.ignore_status_mask |=
-+				UTSR1_TO_SM(UTSR1_FRE | UTSR1_PRE);
-+	if (termios->c_iflag & IGNBRK) {
-+		sport->port.ignore_status_mask |=
-+				UTSR0_TO_SM(UTSR0_RBB | UTSR0_REB);
-+		/*
-+		 * If we're ignoring parity and break indicators,
-+		 * ignore overruns too (for real raw support).
-+		 */
-+		if (termios->c_iflag & IGNPAR)
-+			sport->port.ignore_status_mask |=
-+				UTSR1_TO_SM(UTSR1_ROR);
-+	}
-+#endif
-+
-+	del_timer_sync(&sport->timer);
-+
-+	/*
-+	 * Update the per-port timeout.
-+	 */
-+	uart_update_timeout(port, termios->c_cflag, baud);
-+
-+	/*
-+	 * disable interrupts and drain transmitter
-+	 */
-+	old_ien = serial_in(sport, IP3106_IEN);
-+	serial_out(sport, IP3106_IEN, old_ien & ~(IP3106_UART_INT_ALLTX |
-+					IP3106_UART_INT_ALLRX));
-+
-+	while (serial_in(sport, IP3106_FIFO) & IP3106_UART_FIFO_TXFIFO_STA)
-+		barrier();
-+
-+	/* then, disable everything */
-+	serial_out(sport, IP3106_IEN, 0);
-+
-+	/* Reset the Rx and Tx FIFOs too */
-+	lcr_fcr |= IP3106_UART_LCR_TX_RST;
-+	lcr_fcr |= IP3106_UART_LCR_RX_RST;
-+
-+	/* set the parity, stop bits and data size */
-+	serial_out(sport, IP3106_LCR, lcr_fcr);
-+
-+	/* set the baud rate */
-+	quot -= 1;
-+	serial_out(sport, IP3106_BAUD, quot);
-+
-+	serial_out(sport, IP3106_ICLR, -1);
-+
-+	serial_out(sport, IP3106_IEN, old_ien);
-+
-+	if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
-+		ip3106_enable_ms(&sport->port);
-+
-+	spin_unlock_irqrestore(&sport->port.lock, flags);
-+}
-+
-+static const char *ip3106_type(struct uart_port *port)
-+{
-+	struct ip3106_port *sport = (struct ip3106_port *)port;
-+
-+	return sport->port.type == PORT_IP3106 ? "IP3106" : NULL;
-+}
-+
-+/*
-+ * Release the memory region(s) being used by 'port'.
-+ */
-+static void ip3106_release_port(struct uart_port *port)
-+{
-+	struct ip3106_port *sport = (struct ip3106_port *)port;
-+
-+	release_mem_region(sport->port.mapbase, UART_PORT_SIZE);
-+}
-+
-+/*
-+ * Request the memory region(s) being used by 'port'.
-+ */
-+static int ip3106_request_port(struct uart_port *port)
-+{
-+	struct ip3106_port *sport = (struct ip3106_port *)port;
-+
-+	return request_mem_region(sport->port.mapbase, UART_PORT_SIZE,
-+			"ip3106-uart") != NULL ? 0 : -EBUSY;
-+}
-+
-+/*
-+ * Configure/autoconfigure the port.
-+ */
-+static void ip3106_config_port(struct uart_port *port, int flags)
-+{
-+	struct ip3106_port *sport = (struct ip3106_port *)port;
-+
-+	if (flags & UART_CONFIG_TYPE &&
-+	    ip3106_request_port(&sport->port) == 0)
-+		sport->port.type = PORT_IP3106;
-+}
-+
-+/*
-+ * Verify the new serial_struct (for TIOCSSERIAL).
-+ * The only change we allow are to the flags and type, and
-+ * even then only between PORT_IP3106 and PORT_UNKNOWN
-+ */
-+static int
-+ip3106_verify_port(struct uart_port *port, struct serial_struct *ser)
-+{
-+	struct ip3106_port *sport = (struct ip3106_port *)port;
-+	int ret = 0;
-+
-+	if (ser->type != PORT_UNKNOWN && ser->type != PORT_IP3106)
-+		ret = -EINVAL;
-+	if (sport->port.irq != ser->irq)
-+		ret = -EINVAL;
-+	if (ser->io_type != SERIAL_IO_MEM)
-+		ret = -EINVAL;
-+	if (sport->port.uartclk / 16 != ser->baud_base)
-+		ret = -EINVAL;
-+	if ((void *)sport->port.mapbase != ser->iomem_base)
-+		ret = -EINVAL;
-+	if (sport->port.iobase != ser->port)
-+		ret = -EINVAL;
-+	if (ser->hub6 != 0)
-+		ret = -EINVAL;
-+	return ret;
-+}
-+
-+struct uart_ops ip3106_pops = {
-+	.tx_empty	= ip3106_tx_empty,
-+	.set_mctrl	= ip3106_set_mctrl,
-+	.get_mctrl	= ip3106_get_mctrl,
-+	.stop_tx	= ip3106_stop_tx,
-+	.start_tx	= ip3106_start_tx,
-+	.stop_rx	= ip3106_stop_rx,
-+	.enable_ms	= ip3106_enable_ms,
-+	.break_ctl	= ip3106_break_ctl,
-+	.startup	= ip3106_startup,
-+	.shutdown	= ip3106_shutdown,
-+	.set_termios	= ip3106_set_termios,
-+	.type		= ip3106_type,
-+	.release_port	= ip3106_release_port,
-+	.request_port	= ip3106_request_port,
-+	.config_port	= ip3106_config_port,
-+	.verify_port	= ip3106_verify_port,
-+};
-+
-+
-+/*
-+ * Setup the IP3106 serial ports.
-+ *
-+ * Note also that we support "console=ttySx" where "x" is either 0 or 1.
-+ */
-+static void __init ip3106_init_ports(void)
-+{
-+	static int first = 1;
-+	int i;
-+
-+	if (!first)
-+		return;
-+	first = 0;
-+
-+	for (i = 0; i < NR_PORTS; i++) {
-+		init_timer(&ip3106_ports[i].timer);
-+		ip3106_ports[i].timer.function = ip3106_timeout;
-+		ip3106_ports[i].timer.data     = (unsigned long)&ip3106_ports[i];
-+	}
-+}
-+
-+#ifdef CONFIG_SERIAL_IP3106_CONSOLE
-+
-+/*
-+ * Interrupts are disabled on entering
-+ */
-+static void
-+ip3106_console_write(struct console *co, const char *s, unsigned int count)
-+{
-+	struct ip3106_port *sport = &ip3106_ports[co->index];
-+	unsigned int old_ien, status, i;
-+
-+	/*
-+	 *	First, save IEN and then disable interrupts
-+	 */
-+	old_ien = serial_in(sport, IP3106_IEN);
-+	serial_out(sport, IP3106_IEN, old_ien & ~(IP3106_UART_INT_ALLTX |
-+					IP3106_UART_INT_ALLRX));
-+
-+	/*
-+	 *	Now, do each character
-+	 */
-+	for (i = 0; i < count; i++) {
-+		do {
-+			/* Wait for UART_TX register to empty */
-+			status = serial_in(sport, IP3106_FIFO);
-+		} while (status & IP3106_UART_FIFO_TXFIFO);
-+		serial_out(sport, IP3106_FIFO, s[i]);
-+		if (s[i] == '\n') {
-+			do {
-+				status = serial_in(sport, IP3106_FIFO);
-+			} while (status & IP3106_UART_FIFO_TXFIFO);
-+			serial_out(sport, IP3106_FIFO, '\r');
-+		}
-+	}
-+
-+	/*
-+	 *	Finally, wait for transmitter to become empty
-+	 *	and restore IEN
-+	 */
-+	do {
-+		/* Wait for UART_TX register to empty */
-+		status = serial_in(sport, IP3106_FIFO);
-+	} while (status & IP3106_UART_FIFO_TXFIFO);
-+
-+	/* Clear TX and EMPTY interrupt */
-+	serial_out(sport, IP3106_ICLR, IP3106_UART_INT_TX |
-+			     IP3106_UART_INT_EMPTY);
-+
-+	serial_out(sport, IP3106_IEN, old_ien);
-+}
-+
-+static int __init
-+ip3106_console_setup(struct console *co, char *options)
-+{
-+	struct ip3106_port *sport;
-+	int baud = 38400;
-+	int bits = 8;
-+	int parity = 'n';
-+	int flow = 'n';
-+
-+	/*
-+	 * Check whether an invalid uart number has been specified, and
-+	 * if so, search for the first available port that does have
-+	 * console support.
-+	 */
-+	if (co->index == -1 || co->index >= NR_PORTS)
-+		co->index = 0;
-+	sport = &ip3106_ports[co->index];
-+
-+	if (options)
-+		uart_parse_options(options, &baud, &parity, &bits, &flow);
-+
-+	return uart_set_options(&sport->port, co, baud, parity, bits, flow);
-+}
-+
-+extern struct uart_driver ip3106_reg;
-+static struct console ip3106_console = {
-+	.name		= "ttyS",
-+	.write		= ip3106_console_write,
-+	.device		= uart_console_device,
-+	.setup		= ip3106_console_setup,
-+	.flags		= CON_PRINTBUFFER,
-+	.index		= -1,
-+	.data		= &ip3106_reg,
-+};
-+
-+static int __init ip3106_rs_console_init(void)
-+{
-+	ip3106_init_ports();
-+	register_console(&ip3106_console);
-+	return 0;
-+}
-+console_initcall(ip3106_rs_console_init);
-+
-+#define IP3106_CONSOLE	&ip3106_console
-+#else
-+#define IP3106_CONSOLE	NULL
-+#endif
-+
-+static struct uart_driver ip3106_reg = {
-+	.owner			= THIS_MODULE,
-+	.driver_name		= "ttyS",
-+	.dev_name		= "ttyS",
-+	.devfs_name		= "tts/",
-+	.major			= SERIAL_IP3106_MAJOR,
-+	.minor			= MINOR_START,
-+	.nr			= NR_PORTS,
-+	.cons			= IP3106_CONSOLE,
-+};
-+
-+static int ip3106_serial_suspend(struct device *_dev, u32 state, u32 level)
-+{
-+	struct ip3106_port *sport = dev_get_drvdata(_dev);
-+
-+	if (sport && level == SUSPEND_DISABLE)
-+		uart_suspend_port(&ip3106_reg, &sport->port);
-+
-+	return 0;
-+}
-+
-+static int ip3106_serial_resume(struct device *_dev, u32 level)
-+{
-+	struct ip3106_port *sport = dev_get_drvdata(_dev);
-+
-+	if (sport && level == RESUME_ENABLE)
-+		uart_resume_port(&ip3106_reg, &sport->port);
-+
-+	return 0;
-+}
-+
-+static int ip3106_serial_probe(struct device *_dev)
-+{
-+	struct platform_device *dev = to_platform_device(_dev);
-+	struct resource *res = dev->resource;
-+	int i;
-+
-+	for (i = 0; i < dev->num_resources; i++, res++) {
-+		if (!(res->flags & IORESOURCE_MEM))
-+			continue;
-+
-+		for (i = 0; i < NR_PORTS; i++) {
-+			if (ip3106_ports[i].port.mapbase != res->start)
-+				continue;
-+
-+			ip3106_ports[i].port.dev = _dev;
-+			uart_add_one_port(&ip3106_reg, &ip3106_ports[i].port);
-+			dev_set_drvdata(_dev, &ip3106_ports[i]);
-+			break;
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int ip3106_serial_remove(struct device *_dev)
-+{
-+	struct ip3106_port *sport = dev_get_drvdata(_dev);
-+
-+	dev_set_drvdata(_dev, NULL);
-+
-+	if (sport)
-+		uart_remove_one_port(&ip3106_reg, &sport->port);
-+
-+	return 0;
-+}
-+
-+static struct device_driver ip3106_serial_driver = {
-+	.name		= "ip3106-uart",
-+	.bus		= &platform_bus_type,
-+	.probe		= ip3106_serial_probe,
-+	.remove		= ip3106_serial_remove,
-+	.suspend	= ip3106_serial_suspend,
-+	.resume		= ip3106_serial_resume,
-+};
-+
-+static int __init ip3106_serial_init(void)
-+{
-+	int ret;
-+
-+	printk(KERN_INFO "Serial: IP3106 driver $Revision: 1.2 $\n");
-+
-+	ip3106_init_ports();
-+
-+	ret = uart_register_driver(&ip3106_reg);
-+	if (ret == 0) {
-+		ret = driver_register(&ip3106_serial_driver);
-+		if (ret)
-+			uart_unregister_driver(&ip3106_reg);
-+	}
-+	return ret;
-+}
-+
-+static void __exit ip3106_serial_exit(void)
-+{
-+	driver_unregister(&ip3106_serial_driver);
-+	uart_unregister_driver(&ip3106_reg);
-+}
-+
-+module_init(ip3106_serial_init);
-+module_exit(ip3106_serial_exit);
-+
-+MODULE_AUTHOR("Embedded Alley Solutions, Inc.");
-+MODULE_DESCRIPTION("IP3106 generic serial port driver");
-+MODULE_LICENSE("GPL");
-+MODULE_ALIAS_CHARDEV_MAJOR(SERIAL_IP3106_MAJOR);
-diff -Naur linux-2.6.17.orig/drivers/serial/Kconfig linux-2.6.17/drivers/serial/Kconfig
---- linux-2.6.17.orig/drivers/serial/Kconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/drivers/serial/Kconfig	2006-06-19 18:16:13.000000000 -0700
-@@ -647,6 +647,25 @@
- 	depends on SERIAL_SH_SCI=y
- 	select SERIAL_CORE_CONSOLE
- 
-+config SERIAL_IP3106
-+	bool "Enable IP3106 UART Support (Philips PNX 8xx0 SoCs)"
-+	depends on MIPS && (SOC_PNX8550 || SOC_PNX8330)
-+	select SERIAL_CORE
-+	help
-+	  If you have a Philips SoC with an IP 3106 UART in it, such as
-+	  the PNX8550 or PNX8330 (MIPS based) and you want to use
-+	  serial ports, say Y.  Otherwise, say N.
-+
-+config SERIAL_IP3106_CONSOLE
-+	bool "Enable PNX8XX0 serial console"
-+	depends on SERIAL_IP3106
-+	select SERIAL_CORE_CONSOLE
-+	help
-+	  If you have a Philips SoC with an IP 3106 UART in it, such as
-+	  the PNX8550 or PNX8330 (MIPS based) and you want to use
-+	  a serial console, say Y.
-+	  Otherwise, say N.
-+
- config SERIAL_CORE
- 	tristate
- 
-diff -Naur linux-2.6.17.orig/drivers/serial/Makefile linux-2.6.17/drivers/serial/Makefile
---- linux-2.6.17.orig/drivers/serial/Makefile	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/drivers/serial/Makefile	2006-06-19 18:16:13.000000000 -0700
-@@ -39,6 +39,7 @@
- obj-$(CONFIG_V850E_UART) += v850e_uart.o
- obj-$(CONFIG_SERIAL_PMACZILOG) += pmac_zilog.o
- obj-$(CONFIG_SERIAL_LH7A40X) += serial_lh7a40x.o
-+obj-$(CONFIG_SERIAL_IP3106) += ip3106_uart.o
- obj-$(CONFIG_SERIAL_DZ) += dz.o
- obj-$(CONFIG_SERIAL_SH_SCI) += sh-sci.o
- obj-$(CONFIG_SERIAL_SGI_L1_CONSOLE) += sn_console.o
-diff -Naur linux-2.6.17.orig/drivers/usb/gadget/net2280.c linux-2.6.17/drivers/usb/gadget/net2280.c
---- linux-2.6.17.orig/drivers/usb/gadget/net2280.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/drivers/usb/gadget/net2280.c	2006-06-19 18:16:13.000000000 -0700
-@@ -468,7 +468,8 @@
- #elif	defined(CONFIG_PPC) && !defined(CONFIG_NOT_COHERENT_CACHE)
- #define USE_KMALLOC
- 
--#elif	defined(CONFIG_MIPS) && !defined(CONFIG_DMA_NONCOHERENT)
-+#elif	defined(CONFIG_MIPS) && \
-+	(defined(CONFIG_DMA_COHERENT) || defined(CONFIG_DMA_IP27))
- #define USE_KMALLOC
- 
- /* FIXME there are other cases, including an x86-64 one ...  */
-diff -Naur linux-2.6.17.orig/drivers/usb/host/ohci-hcd.c linux-2.6.17/drivers/usb/host/ohci-hcd.c
---- linux-2.6.17.orig/drivers/usb/host/ohci-hcd.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/drivers/usb/host/ohci-hcd.c	2006-06-19 18:16:13.000000000 -0700
-@@ -906,6 +906,10 @@
- #include "ohci-au1xxx.c"
- #endif
- 
-+#ifdef CONFIG_PNX8550
-+#include "ohci-pnx8550.c"
-+#endif
-+
- #ifdef CONFIG_USB_OHCI_HCD_PPC_SOC
- #include "ohci-ppc-soc.c"
- #endif
-diff -Naur linux-2.6.17.orig/drivers/usb/host/ohci-pnx8550.c linux-2.6.17/drivers/usb/host/ohci-pnx8550.c
---- linux-2.6.17.orig/drivers/usb/host/ohci-pnx8550.c	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/drivers/usb/host/ohci-pnx8550.c	2006-06-19 18:16:13.000000000 -0700
-@@ -0,0 +1,277 @@
-+/*
-+ * OHCI HCD (Host Controller Driver) for USB.
-+ *
-+ * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
-+ * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
-+ * (C) Copyright 2002 Hewlett-Packard Company
-+ * (C) Copyright 2005 Embedded Alley Solutions, Inc.
-+ *
-+ * Bus Glue for PNX8550
-+ *
-+ * Written by Christopher Hoover <ch@hpl.hp.com>
-+ * Based on fragments of previous driver by Russell King et al.
-+ *
-+ * Modified for LH7A404 from ohci-sa1111.c
-+ *  by Durgesh Pattamatta <pattamattad@sharpsec.com>
-+ *
-+ * Modified for pxa27x from ohci-lh7a404.c
-+ *  by Nick Bane <nick@cecomputing.co.uk> 26-8-2004
-+ *
-+ * Modified for PNX8550 from ohci-pxa27x.c
-+ *  by Embedded Alley Solutions, Inc. 
-+ *
-+ * This file is licenced under the GPL.
-+ */
-+
-+#include <linux/device.h>
-+#include <asm/mach-pnx8550/usb.h>
-+#include <asm/mach-pnx8550/int.h>
-+#include <asm/mach-pnx8550/pci.h>
-+
-+#ifndef CONFIG_PNX8550
-+#error "This file is PNX8550 bus glue.  CONFIG_PNX8550 must be defined."
-+#endif
-+
-+extern int usb_disabled(void);
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static void pnx8550_start_hc(struct platform_device *dev)
-+{
-+	/*
-+	 * Set register CLK48CTL to enable and 48MHz
-+	 */
-+	outl(0x00000003, PCI_BASE | 0x0004770c);
-+
-+	/*
-+	 * Set register CLK12CTL to enable and 48MHz
-+	 */
-+	outl(0x00000003, PCI_BASE | 0x00047710);
-+
-+	udelay(100);
-+}
-+
-+static void pnx8550_stop_hc(struct platform_device *dev)
-+{
-+	udelay(10);
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/* configure so an HC device and id are always provided */
-+/* always called with process context; sleeping is OK */
-+
-+
-+/**
-+ * usb_hcd_pnx8550_probe - initialize pnx8550-based HCDs
-+ * Context: !in_interrupt()
-+ *
-+ * Allocates basic resources for this USB host controller, and
-+ * then invokes the start() method for the HCD associated with it
-+ * through the hotplug entry's driver_data.
-+ *
-+ */
-+int usb_hcd_pnx8550_probe (const struct hc_driver *driver,
-+			  struct platform_device *dev)
-+{
-+	int retval;
-+	struct usb_hcd *hcd;
-+
-+	if (dev->resource[1].flags != IORESOURCE_IRQ) {
-+		pr_debug ("resource[1] is not IORESOURCE_IRQ");
-+		return -ENOMEM;
-+	}
-+
-+	hcd = usb_create_hcd (driver, &dev->dev, "pnx8550");
-+	if (!hcd)
-+		return -ENOMEM;
-+	hcd->rsrc_start = dev->resource[0].start;
-+	hcd->rsrc_len = dev->resource[0].end - dev->resource[0].start + 1;
-+
-+	if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) {
-+		pr_debug("request_mem_region failed");
-+		retval = -EBUSY;
-+		goto err1;
-+	}
-+
-+	hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
-+	if (!hcd->regs) {
-+		pr_debug("ioremap failed");
-+		retval = -ENOMEM;
-+		goto err2;
-+	}
-+
-+	pnx8550_start_hc(dev);
-+
-+	ohci_hcd_init(hcd_to_ohci(hcd));
-+
-+	retval = usb_add_hcd(hcd, dev->resource[1].start, SA_INTERRUPT);
-+	if (retval == 0)
-+		return retval;
-+
-+	pnx8550_stop_hc(dev);
-+	iounmap(hcd->regs);
-+ err2:
-+	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
-+ err1:
-+	usb_put_hcd(hcd);
-+	return retval;
-+}
-+
-+
-+/* may be called without controller electrically present */
-+/* may be called with controller, bus, and devices active */
-+
-+/**
-+ * usb_hcd_pnx8550_remove - shutdown processing for pnx8550-based HCDs
-+ * @dev: USB Host Controller being removed
-+ * Context: !in_interrupt()
-+ *
-+ * Reverses the effect of usb_hcd_pnx8550_probe(), first invoking
-+ * the HCD's stop() method.  It is always called from a thread
-+ * context, normally "rmmod", "apmd", or something similar.
-+ *
-+ */
-+void usb_hcd_pnx8550_remove (struct usb_hcd *hcd, struct platform_device *dev)
-+{
-+	usb_remove_hcd(hcd);
-+	pnx8550_stop_hc(dev);
-+	iounmap(hcd->regs);
-+	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
-+	usb_put_hcd(hcd);
-+}
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static int __devinit
-+ohci_pnx8550_start (struct usb_hcd *hcd)
-+{
-+	struct ohci_hcd	*ohci = hcd_to_ohci (hcd);
-+	int		ret;
-+
-+	ohci_dbg (ohci, "ohci_pnx8550_start, ohci:%p", ohci);
-+
-+	if ((ret = ohci_init(ohci)) < 0)
-+		return ret;
-+
-+	if ((ret = ohci_run (ohci)) < 0) {
-+		err ("can't start %s", hcd->self.bus_name);
-+		ohci_stop (hcd);
-+		return ret;
-+	}
-+
-+	return 0;
-+}
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static const struct hc_driver ohci_pnx8550_hc_driver = {
-+	.description =		hcd_name,
-+	.product_desc =		"PNX8550 OHCI",
-+	.hcd_priv_size =	sizeof(struct ohci_hcd),
-+
-+	/*
-+	 * generic hardware linkage
-+	 */
-+	.irq =			ohci_irq,
-+	.flags =		HCD_USB11 | HCD_MEMORY,
-+
-+	/*
-+	 * basic lifecycle operations
-+	 */
-+	.start =		ohci_pnx8550_start,
-+	.stop =			ohci_stop,
-+
-+	/*
-+	 * managing i/o requests and associated device resources
-+	 */
-+	.urb_enqueue =		ohci_urb_enqueue,
-+	.urb_dequeue =		ohci_urb_dequeue,
-+	.endpoint_disable =	ohci_endpoint_disable,
-+
-+	/*
-+	 * scheduling support
-+	 */
-+	.get_frame_number =	ohci_get_frame,
-+
-+	/*
-+	 * root hub support
-+	 */
-+	.hub_status_data =	ohci_hub_status_data,
-+	.hub_control =		ohci_hub_control,
-+#ifdef  CONFIG_USB_SUSPEND
-+	.hub_suspend =		ohci_hub_suspend,
-+	.hub_resume =		ohci_hub_resume,
-+#endif
-+};
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static int ohci_hcd_pnx8550_drv_probe(struct device *dev)
-+{
-+	struct platform_device *pdev = to_platform_device(dev);
-+	int ret;
-+
-+	pr_debug ("In ohci_hcd_pnx8550_drv_probe");
-+
-+	if (usb_disabled())
-+		return -ENODEV;
-+
-+	ret = usb_hcd_pnx8550_probe(&ohci_pnx8550_hc_driver, pdev);
-+	return ret;
-+}
-+
-+static int ohci_hcd_pnx8550_drv_remove(struct device *dev)
-+{
-+	struct platform_device *pdev = to_platform_device(dev);
-+	struct usb_hcd *hcd = dev_get_drvdata(dev);
-+
-+	usb_hcd_pnx8550_remove(hcd, pdev);
-+	return 0;
-+}
-+
-+static int ohci_hcd_pnx8550_drv_suspend(struct device *dev, u32 state, u32 level)
-+{
-+//	struct platform_device *pdev = to_platform_device(dev);
-+//	struct usb_hcd *hcd = dev_get_drvdata(dev);
-+	printk("%s: not implemented yet\n", __FUNCTION__);
-+
-+	return 0;
-+}
-+
-+static int ohci_hcd_pnx8550_drv_resume(struct device *dev, u32 state)
-+{
-+//	struct platform_device *pdev = to_platform_device(dev);
-+//	struct usb_hcd *hcd = dev_get_drvdata(dev);
-+	printk("%s: not implemented yet\n", __FUNCTION__);
-+
-+	return 0;
-+}
-+
-+
-+static struct device_driver ohci_hcd_pnx8550_driver = {
-+	.name		= "pnx8550-ohci",
-+	.bus		= &platform_bus_type,
-+	.probe		= ohci_hcd_pnx8550_drv_probe,
-+	.remove		= ohci_hcd_pnx8550_drv_remove,
-+	.suspend	= ohci_hcd_pnx8550_drv_suspend, 
-+	.resume		= ohci_hcd_pnx8550_drv_resume, 
-+};
-+
-+static int __init ohci_hcd_pnx8550_init (void)
-+{
-+	pr_debug (DRIVER_INFO " (pnx8550)");
-+	pr_debug ("block sizes: ed %d td %d\n",
-+		sizeof (struct ed), sizeof (struct td));
-+
-+	return driver_register(&ohci_hcd_pnx8550_driver);
-+}
-+
-+static void __exit ohci_hcd_pnx8550_cleanup (void)
-+{
-+	driver_unregister(&ohci_hcd_pnx8550_driver);
-+}
-+
-+module_init (ohci_hcd_pnx8550_init);
-+module_exit (ohci_hcd_pnx8550_cleanup);
-diff -Naur linux-2.6.17.orig/drivers/video/au1100fb.c linux-2.6.17/drivers/video/au1100fb.c
---- linux-2.6.17.orig/drivers/video/au1100fb.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/drivers/video/au1100fb.c	2006-06-19 18:16:13.000000000 -0700
-@@ -38,6 +38,7 @@
-  *  with this program; if not, write  to the Free Software Foundation, Inc.,
-  *  675 Mass Ave, Cambridge, MA 02139, USA.
-  */
-+
- #include <linux/config.h>
- #include <linux/module.h>
- #include <linux/kernel.h>
-diff -Naur linux-2.6.17.orig/drivers/video/Kconfig linux-2.6.17/drivers/video/Kconfig
---- linux-2.6.17.orig/drivers/video/Kconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/drivers/video/Kconfig	2006-06-19 18:16:13.000000000 -0700
-@@ -1142,6 +1142,17 @@
- 	  Please read the <file:Documentation/fb/README-sstfb.txt> for supported
- 	  options and other important info  support.
- 
-+config FB_SMIVGX
-+	tristate "Silicon Motion VoyagerGX support"
-+	depends on FB && PCI && (MIPS || EXPERIMENTAL)
-+	select FB_CFB_FILLRECT
-+	select FB_CFB_COPYAREA
-+	select FB_CFB_IMAGEBLIT
-+	---help---
-+	  This drivers supports SMI VoyagerGX 501 based PCI boards
-+	  The default settings drive both a CRT and LCD.  The CRT
-+	  can be turned off by passing in the no_crt option
-+
- config FB_CYBLA
- 	tristate "Cyberblade/i1 support"
- 	depends on FB && PCI && X86_32 && !64BIT
-@@ -1206,7 +1217,25 @@
- 
- config FB_AU1100
- 	bool "Au1100 LCD Driver"
--	depends on (FB = y) && EXPERIMENTAL && PCI && MIPS && MIPS_PB1100=y
-+	depends on FB && MIPS && SOC_AU1100
-+	select FB_CFB_FILLRECT
-+	select FB_CFB_COPYAREA
-+	select FB_CFB_IMAGEBLIT
-+	help
-+	  This is the framebuffer driver for the AMD Au1100 SOC.  It can drive
-+	  various panels and CRTs by passing in kernel cmd line option
-+	  au1100fb:panel=<name>.
-+
-+config FB_AU1200
-+	bool "Au1200 LCD Driver"
-+	depends on FB && MIPS && SOC_AU1200
-+	select FB_CFB_FILLRECT
-+	select FB_CFB_COPYAREA
-+	select FB_CFB_IMAGEBLIT
-+	help
-+	  This is the framebuffer driver for the AMD Au1200 SOC.  It can drive
-+	  various panels and CRTs by passing in kernel cmd line option
-+	  au1200fb:panel=<name>.
- 
- config FB_AU1200
- 	bool "Au1200 LCD Driver"
-@@ -1322,8 +1351,8 @@
-  	select FB_CFB_IMAGEBLIT
- 	help
- 	  Support for the PMAGB-B TURBOchannel framebuffer card used mainly
--	  in the MIPS-based DECstation series. The card is currently only
--	  supported in 1280x1024x8 mode.
-+	  in the MIPS-based DECstation series. The card is currently only 
-+	  supported in 1280x1024x8 mode.  
- 
- config FB_MAXINE
- 	bool "Maxine (Personal DECstation) onboard framebuffer support"
-diff -Naur linux-2.6.17.orig/drivers/video/Makefile linux-2.6.17/drivers/video/Makefile
---- linux-2.6.17.orig/drivers/video/Makefile	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/drivers/video/Makefile	2006-06-19 18:16:13.000000000 -0700
-@@ -93,6 +93,7 @@
- obj-$(CONFIG_FB_TX3912)		  += tx3912fb.o
- obj-$(CONFIG_FB_S1D13XXX)	  += s1d13xxxfb.o
- obj-$(CONFIG_FB_IMX)              += imxfb.o
-+obj-$(CONFIG_FB_SMIVGX)		  += smivgxfb.o
- obj-$(CONFIG_FB_S3C2410)	  += s3c2410fb.o
- 
- # Platform or fallback drivers go here
-diff -Naur linux-2.6.17.orig/drivers/video/smivgxfb.c linux-2.6.17/drivers/video/smivgxfb.c
---- linux-2.6.17.orig/drivers/video/smivgxfb.c	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/drivers/video/smivgxfb.c	2006-06-19 18:16:13.000000000 -0700
-@@ -0,0 +1,387 @@
-+/***************************************************************************
-+ *  Silicon Motion VoyagerGX framebuffer driver
-+ *
-+ * 	ported to 2.6 by Embedded Alley Solutions, Inc
-+ * 	Copyright (C) 2005 Embedded Alley Solutions, Inc
-+ *
-+ * 		based on
-+    copyright            : (C) 2001 by Szu-Tao Huang
-+    email                : johuang@siliconmotion.com
-+    Updated to SM501 by Eric.Devolder@amd.com and dan@embeddededge.com
-+    for the AMD Mirage Portable Tablet.  20 Oct 2003
-+ ***************************************************************************/
-+
-+/***************************************************************************
-+ *                                                                         *
-+ *   This program is free software; you can redistribute it and/or modify  *
-+ *   it under the terms of the GNU General Public License as published by  *
-+ *   the Free Software Foundation; either version 2 of the License, or     *
-+ *   (at your option) any later version.                                   *
-+ *                                                                         *
-+ ***************************************************************************/
-+
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/errno.h>
-+#include <linux/string.h>
-+#include <linux/mm.h>
-+#include <linux/tty.h>
-+#include <linux/slab.h>
-+#include <linux/delay.h>
-+#include <linux/fb.h>
-+#include <linux/pci.h>
-+#include <linux/init.h>
-+
-+#include <asm/io.h>
-+#include <asm/irq.h>
-+#include <asm/pgtable.h>
-+#include <asm/system.h>
-+#include <asm/uaccess.h>
-+
-+static char __iomem *SMIRegs;	// point to virtual Memory Map IO starting address
-+static char __iomem *SMILFB;	// point to virtual video memory starting address
-+
-+static struct fb_fix_screeninfo smifb_fix __devinitdata = {
-+	.id =		"smivgx",
-+	.type =		FB_TYPE_PACKED_PIXELS,
-+	.visual =	FB_VISUAL_TRUECOLOR,
-+	.ywrapstep = 	0,
-+	.line_length	= 1024 * 2, /* (bbp * xres)/8 */
-+	.accel =	FB_ACCEL_NONE,
-+};
-+
-+static struct fb_var_screeninfo smifb_var __devinitdata = {
-+	.xres           = 1024,
-+	.yres           = 768,
-+	.xres_virtual   = 1024,
-+	.yres_virtual   = 768,
-+	.bits_per_pixel = 16,
-+	.red            = { 11, 5, 0 },
-+	.green          = {  5, 6, 0 },
-+	.blue           = {  0, 5, 0 },
-+	.activate       = FB_ACTIVATE_NOW,
-+	.height         = -1,
-+	.width          = -1,
-+	.vmode          = FB_VMODE_NONINTERLACED,
-+};
-+
-+
-+static struct fb_info info;
-+
-+#define smi_mmiowb(dat,reg)	writeb(dat, (SMIRegs + reg))
-+#define smi_mmioww(dat,reg)	writew(dat, (SMIRegs + reg))
-+#define smi_mmiowl(dat,reg)	writel(dat, (SMIRegs + reg))
-+
-+#define smi_mmiorb(reg)	        readb(SMIRegs + reg)
-+#define smi_mmiorw(reg)	        readw(SMIRegs + reg)
-+#define smi_mmiorl(reg)	        readl(SMIRegs + reg)
-+
-+/* Address space offsets for various control/status registers.
-+*/
-+#define MISC_CTRL			0x000004
-+#define GPIO_LO_CTRL			0x000008
-+#define GPIO_HI_CTRL			0x00000c
-+#define DRAM_CTRL			0x000010
-+#define CURRENT_POWER_GATE		0x000038
-+#define CURRENT_POWER_CLOCK		0x00003C
-+#define POWER_MODE1_GATE                0x000048
-+#define POWER_MODE1_CLOCK               0x00004C
-+#define POWER_MODE_CTRL			0x000054
-+
-+#define GPIO_DATA_LO			0x010000
-+#define GPIO_DATA_HI			0x010004
-+#define GPIO_DATA_DIR_LO		0x010008
-+#define GPIO_DATA_DIR_HI		0x01000c
-+#define I2C_BYTE_COUNT			0x010040
-+#define I2C_CONTROL			0x010041
-+#define I2C_STATUS_RESET		0x010042
-+#define I2C_SLAVE_ADDRESS		0x010043
-+#define I2C_DATA			0x010044
-+
-+#define DE_COLOR_COMPARE		0x100020
-+#define DE_COLOR_COMPARE_MASK		0x100024
-+#define DE_MASKS			0x100028
-+#define DE_WRAP				0x10004C
-+
-+#define PANEL_DISPLAY_CTRL              0x080000
-+#define PANEL_PAN_CTRL                  0x080004
-+#define PANEL_COLOR_KEY                 0x080008
-+#define PANEL_FB_ADDRESS                0x08000C
-+#define PANEL_FB_WIDTH                  0x080010
-+#define PANEL_WINDOW_WIDTH              0x080014
-+#define PANEL_WINDOW_HEIGHT             0x080018
-+#define PANEL_PLANE_TL                  0x08001C
-+#define PANEL_PLANE_BR                  0x080020
-+#define PANEL_HORIZONTAL_TOTAL          0x080024
-+#define PANEL_HORIZONTAL_SYNC           0x080028
-+#define PANEL_VERTICAL_TOTAL            0x08002C
-+#define PANEL_VERTICAL_SYNC             0x080030
-+#define PANEL_CURRENT_LINE              0x080034
-+#define VIDEO_DISPLAY_CTRL		0x080040
-+#define VIDEO_DISPLAY_FB0		0x080044
-+#define VIDEO_DISPLAY_FBWIDTH		0x080048
-+#define VIDEO_DISPLAY_FB0LAST		0x08004C
-+#define VIDEO_DISPLAY_TL		0x080050
-+#define VIDEO_DISPLAY_BR		0x080054
-+#define VIDEO_SCALE			0x080058
-+#define VIDEO_INITIAL_SCALE		0x08005C
-+#define VIDEO_YUV_CONSTANTS		0x080060
-+#define VIDEO_DISPLAY_FB1		0x080064
-+#define VIDEO_DISPLAY_FB1LAST		0x080068
-+#define VIDEO_ALPHA_CTRL		0x080080
-+#define PANEL_HWC_ADDRESS		0x0800F0
-+#define CRT_DISPLAY_CTRL		0x080200
-+#define CRT_FB_ADDRESS			0x080204
-+#define CRT_FB_WIDTH			0x080208
-+#define CRT_HORIZONTAL_TOTAL		0x08020c
-+#define CRT_HORIZONTAL_SYNC		0x080210
-+#define CRT_VERTICAL_TOTAL		0x080214
-+#define CRT_VERTICAL_SYNC		0x080218
-+#define CRT_HWC_ADDRESS			0x080230
-+#define CRT_HWC_LOCATION		0x080234
-+
-+#define ZV_CAPTURE_CTRL			0x090000
-+#define ZV_CAPTURE_CLIP			0x090004
-+#define ZV_CAPTURE_SIZE			0x090008
-+#define ZV_CAPTURE_BUF0			0x09000c
-+#define ZV_CAPTURE_BUF1			0x090010
-+#define ZV_CAPTURE_OFFSET		0x090014
-+#define ZV_FIFO_CTRL			0x090018
-+
-+#define waitforvsync() udelay(400)
-+
-+static int initdone = 0;
-+static int crt_out = 1;
-+
-+
-+static int
-+smi_setcolreg(unsigned regno, unsigned red, unsigned green,
-+	unsigned blue, unsigned transp,
-+	struct fb_info *info)
-+{
-+	if (regno > 255)
-+		return 1;
-+
-+	((u32 *)(info->pseudo_palette))[regno] =
-+		    ((red & 0xf800) >> 0) |
-+		    ((green & 0xfc00) >> 5) |
-+		    ((blue & 0xf800) >> 11);
-+
-+	return 0;
-+}
-+
-+/* This function still needs lots of work to generically support
-+ * different output devices (CRT or LCD) and resolutions.
-+ * Currently hard-coded for 1024x768 LCD panel.
-+ */
-+static void smi_setmode(void)
-+{
-+	if (initdone)
-+		return;
-+
-+	initdone = 1;
-+
-+	/* Just blast in some control values based upon the chip
-+	 * documentation.  We use the internal memory, I don't know
-+	 * how to determine the amount available yet.
-+	 */
-+	smi_mmiowl(0x07F127C2, DRAM_CTRL);
-+	smi_mmiowl(0x02000020, PANEL_HWC_ADDRESS);
-+	smi_mmiowl(0x007FF800, PANEL_HWC_ADDRESS);
-+	smi_mmiowl(0x00021827, POWER_MODE1_GATE);
-+	smi_mmiowl(0x011A0A09, POWER_MODE1_CLOCK);
-+	smi_mmiowl(0x00000001, POWER_MODE_CTRL);
-+	smi_mmiowl(0x80000000, PANEL_FB_ADDRESS);
-+	smi_mmiowl(0x08000800, PANEL_FB_WIDTH);
-+	smi_mmiowl(0x04000000, PANEL_WINDOW_WIDTH);
-+	smi_mmiowl(0x03000000, PANEL_WINDOW_HEIGHT);
-+	smi_mmiowl(0x00000000, PANEL_PLANE_TL);
-+	smi_mmiowl(0x02FF03FF, PANEL_PLANE_BR);
-+	smi_mmiowl(0x05D003FF, PANEL_HORIZONTAL_TOTAL);
-+	smi_mmiowl(0x00C80424, PANEL_HORIZONTAL_SYNC);
-+	smi_mmiowl(0x032502FF, PANEL_VERTICAL_TOTAL);
-+	smi_mmiowl(0x00060302, PANEL_VERTICAL_SYNC);
-+	smi_mmiowl(0x00013905, PANEL_DISPLAY_CTRL);
-+	smi_mmiowl(0x01013105, PANEL_DISPLAY_CTRL);
-+	waitforvsync();
-+	smi_mmiowl(0x03013905, PANEL_DISPLAY_CTRL);
-+	waitforvsync();
-+	smi_mmiowl(0x07013905, PANEL_DISPLAY_CTRL);
-+	waitforvsync();
-+	smi_mmiowl(0x0F013905, PANEL_DISPLAY_CTRL);
-+	smi_mmiowl(0x0002187F, POWER_MODE1_GATE);
-+	smi_mmiowl(0x01011801, POWER_MODE1_CLOCK);
-+	smi_mmiowl(0x00000001, POWER_MODE_CTRL);
-+
-+	smi_mmiowl(0x80000000, PANEL_FB_ADDRESS);
-+	smi_mmiowl(0x00000000, PANEL_PAN_CTRL);
-+	smi_mmiowl(0x00000000, PANEL_COLOR_KEY);
-+
-+	if (crt_out) {
-+		/* Just sent the panel out to the CRT for now.
-+		*/
-+		smi_mmiowl(0x80000000, CRT_FB_ADDRESS);
-+		smi_mmiowl(0x08000800, CRT_FB_WIDTH);
-+		smi_mmiowl(0x05D003FF, CRT_HORIZONTAL_TOTAL);
-+		smi_mmiowl(0x00C80424, CRT_HORIZONTAL_SYNC);
-+		smi_mmiowl(0x032502FF, CRT_VERTICAL_TOTAL);
-+		smi_mmiowl(0x00060302, CRT_VERTICAL_SYNC);
-+		smi_mmiowl(0x007FF800, CRT_HWC_ADDRESS);
-+		smi_mmiowl(0x00010305, CRT_DISPLAY_CTRL);
-+		smi_mmiowl(0x00000001, MISC_CTRL);
-+	}
-+}
-+
-+/*
-+ * Unmap in the memory mapped IO registers
-+ *
-+ */
-+
-+static void __devinit smi_unmap_mmio(void)
-+{
-+	if (SMIRegs) {
-+		iounmap(SMIRegs);
-+		SMIRegs = NULL;
-+	}
-+}
-+
-+
-+/*
-+ * Unmap in the screen memory
-+ *
-+ */
-+static void __devinit smi_unmap_smem(void)
-+{
-+	if (SMILFB) {
-+		iounmap(SMILFB);
-+		SMILFB = NULL;
-+	}
-+}
-+
-+static void vgxfb_setup(char *options)
-+{
-+
-+	if (!options || !*options)
-+		return;
-+
-+	/* The only thing I'm looking for right now is to disable a
-+	 * CRT output that mirrors the panel display.
-+	 */
-+	if (strcmp(options, "no_crt") == 0)
-+		crt_out = 0;
-+
-+	return;
-+}
-+
-+static struct fb_ops smifb_ops = {
-+	.owner =		THIS_MODULE,
-+	.fb_setcolreg =		smi_setcolreg,
-+	.fb_fillrect =		cfb_fillrect,
-+	.fb_copyarea =		cfb_copyarea,
-+	.fb_imageblit =		cfb_imageblit,
-+};
-+
-+static int __devinit vgx_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
-+{
-+	int err;
-+
-+	/* Enable the chip.
-+	*/
-+	err = pci_enable_device(dev);
-+	if (err)
-+		return err;
-+
-+
-+	/* Set up MMIO space.
-+	*/
-+	smifb_fix.mmio_start = pci_resource_start(dev,1);
-+	smifb_fix.mmio_len = 0x00200000;
-+	SMIRegs = ioremap(smifb_fix.mmio_start, smifb_fix.mmio_len);
-+
-+	/* Set up framebuffer.  It's a 64M space, various amount of
-+	 * internal memory.  I don't know how to determine the real
-+	 * amount of memory (yet).
-+	 */
-+	smifb_fix.smem_start = pci_resource_start(dev,0);
-+	smifb_fix.smem_len = 0x00800000;
-+	SMILFB = ioremap(smifb_fix.smem_start, smifb_fix.smem_len);
-+
-+	memset_io(SMILFB, 0, smifb_fix.smem_len);
-+
-+	info.screen_base = SMILFB;
-+	info.fbops = &smifb_ops;
-+	info.fix = smifb_fix;
-+
-+	info.flags = FBINFO_FLAG_DEFAULT;
-+
-+	info.pseudo_palette = kmalloc(sizeof(u32) * 16, GFP_KERNEL);
-+	if (!info.pseudo_palette) {
-+		return -ENOMEM;
-+	}
-+	memset(info.pseudo_palette, 0, sizeof(u32) *16);
-+
-+	fb_alloc_cmap(&info.cmap,256,0);
-+
-+	smi_setmode();
-+
-+	info.var = smifb_var;
-+
-+	if (register_framebuffer(&info) < 0)
-+		goto failed;
-+
-+	return 0;
-+
-+failed:
-+	smi_unmap_smem();
-+	smi_unmap_mmio();
-+
-+	return err;
-+}
-+
-+static void __devexit vgx_pci_remove(struct pci_dev *dev)
-+{
-+	unregister_framebuffer(&info);
-+	smi_unmap_smem();
-+	smi_unmap_mmio();
-+}
-+
-+static struct pci_device_id vgx_devices[] = {
-+	{PCI_VENDOR_ID_SILICON_MOTION, PCI_DEVICE_ID_SM501_VOYAGER_GX_REV_AA,
-+	 PCI_ANY_ID, PCI_ANY_ID},
-+	{PCI_VENDOR_ID_SILICON_MOTION, PCI_DEVICE_ID_SM501_VOYAGER_GX_REV_B,
-+	 PCI_ANY_ID, PCI_ANY_ID},
-+	{0}
-+};
-+
-+MODULE_DEVICE_TABLE(pci, vgx_devices);
-+
-+static struct pci_driver vgxfb_pci_driver = {
-+	.name	= "vgxfb",
-+	.id_table= vgx_devices,
-+	.probe	= vgx_pci_probe,
-+	.remove	= __devexit_p(vgx_pci_remove),
-+};
-+
-+static int __init vgxfb_init(void)
-+{
-+	char *option = NULL;
-+
-+	if (fb_get_options("vgxfb", &option))
-+		return -ENODEV;
-+	vgxfb_setup(option);
-+
-+	printk("Silicon Motion Inc. VOYAGER Init complete.\n");
-+	return pci_module_init(&vgxfb_pci_driver);
-+}
-+
-+static void __exit vgxfb_exit(void)
-+{
-+	pci_unregister_driver(&vgxfb_pci_driver);
-+}
-+
-+module_init(vgxfb_init);
-+module_exit(vgxfb_exit);
-+
-+MODULE_AUTHOR("");
-+MODULE_DESCRIPTION("Framebuffer driver for SMI Voyager");
-+MODULE_LICENSE("GPL");
-diff -Naur linux-2.6.17.orig/include/asm-mips/addrspace.h linux-2.6.17/include/asm-mips/addrspace.h
---- linux-2.6.17.orig/include/asm-mips/addrspace.h	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/include/asm-mips/addrspace.h	2006-06-19 18:16:14.000000000 -0700
-@@ -133,57 +133,22 @@
-     || defined (CONFIG_CPU_NEVADA)					\
-     || defined (CONFIG_CPU_TX49XX)					\
-     || defined (CONFIG_CPU_MIPS64)
--#define KUSIZE		_LLCONST_(0x0000010000000000)	/* 2^^40 */
--#define KUSIZE_64	_LLCONST_(0x0000010000000000)	/* 2^^40 */
--#define K0SIZE		_LLCONST_(0x0000001000000000)	/* 2^^36 */
--#define K1SIZE		_LLCONST_(0x0000001000000000)	/* 2^^36 */
--#define K2SIZE		_LLCONST_(0x000000ff80000000)
--#define KSEGSIZE	_LLCONST_(0x000000ff80000000)	/* max syssegsz */
- #define TO_PHYS_MASK	_LLCONST_(0x0000000fffffffff)	/* 2^^36 - 1 */
- #endif
- 
- #if defined (CONFIG_CPU_R8000)
- /* We keep KUSIZE consistent with R4000 for now (2^^40) instead of (2^^48) */
--#define KUSIZE		_LLCONST_(0x0000010000000000)	/* 2^^40 */
--#define KUSIZE_64	_LLCONST_(0x0000010000000000)	/* 2^^40 */
--#define K0SIZE		_LLCONST_(0x0000010000000000)	/* 2^^40 */
--#define K1SIZE		_LLCONST_(0x0000010000000000)	/* 2^^40 */
--#define K2SIZE		_LLCONST_(0x0001000000000000)
--#define KSEGSIZE	_LLCONST_(0x0000010000000000)	/* max syssegsz */
- #define TO_PHYS_MASK	_LLCONST_(0x000000ffffffffff)	/* 2^^40 - 1 */
- #endif
- 
- #if defined (CONFIG_CPU_R10000)
--#define KUSIZE		_LLCONST_(0x0000010000000000)	/* 2^^40 */
--#define KUSIZE_64	_LLCONST_(0x0000010000000000)	/* 2^^40 */
--#define K0SIZE		_LLCONST_(0x0000010000000000)	/* 2^^40 */
--#define K1SIZE		_LLCONST_(0x0000010000000000)	/* 2^^40 */
--#define K2SIZE		_LLCONST_(0x00000fff80000000)
--#define KSEGSIZE	_LLCONST_(0x00000fff80000000)	/* max syssegsz */
- #define TO_PHYS_MASK	_LLCONST_(0x000000ffffffffff)	/* 2^^40 - 1 */
- #endif
- 
- #if defined(CONFIG_CPU_SB1) || defined(CONFIG_CPU_SB1A)
--#define KUSIZE		_LLCONST_(0x0000100000000000)	/* 2^^44 */
--#define KUSIZE_64	_LLCONST_(0x0000100000000000)	/* 2^^44 */
--#define K0SIZE		_LLCONST_(0x0000100000000000)	/* 2^^44 */
--#define K1SIZE		_LLCONST_(0x0000100000000000)	/* 2^^44 */
--#define K2SIZE		_LLCONST_(0x0000ffff80000000)
--#define KSEGSIZE	_LLCONST_(0x0000ffff80000000)	/* max syssegsz */
- #define TO_PHYS_MASK	_LLCONST_(0x00000fffffffffff)	/* 2^^44 - 1 */
- #endif
- 
--/*
-- * Further names for SGI source compatibility.  These are stolen from
-- * IRIX's <sys/mips_addrspace.h>.
-- */
--#define KUBASE		_LLCONST_(0)
--#define KUSIZE_32	_LLCONST_(0x0000000080000000)	/* KUSIZE
--							   for a 32 bit proc */
--#define K0BASE_EXL_WR	_LLCONST_(0xa800000000000000)	/* exclusive on write */
--#define K0BASE_NONCOH	_LLCONST_(0x9800000000000000)	/* noncoherent */
--#define K0BASE_EXL	_LLCONST_(0xa000000000000000)	/* exclusive */
--
- #ifndef CONFIG_CPU_R8000
- 
- /*
-diff -Naur linux-2.6.17.orig/include/asm-mips/apm.h linux-2.6.17/include/asm-mips/apm.h
---- linux-2.6.17.orig/include/asm-mips/apm.h	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/include/asm-mips/apm.h	2006-06-19 18:16:14.000000000 -0700
-@@ -0,0 +1,65 @@
-+/* -*- linux-c -*-
-+ *
-+ * (C) 2003 zecke@handhelds.org
-+ *
-+ * GPL version 2
-+ *
-+ * based on arch/arm/kernel/apm.c
-+ * factor out the information needed by architectures to provide
-+ * apm status
-+ *
-+ *
-+ */
-+#ifndef MIPS_ASM_SA1100_APM_H
-+#define MIPS_ASM_SA1100_APM_H
-+
-+#include <linux/config.h>
-+#include <linux/apm_bios.h>
-+
-+/*
-+ * This structure gets filled in by the machine specific 'get_power_status'
-+ * implementation.  Any fields which are not set default to a safe value.
-+ */
-+struct apm_power_info {
-+	unsigned char	ac_line_status;
-+#define APM_AC_OFFLINE			0
-+#define APM_AC_ONLINE			1
-+#define APM_AC_BACKUP			2
-+#define APM_AC_UNKNOWN			0xff
-+
-+	unsigned char	battery_status;
-+#define APM_BATTERY_STATUS_HIGH		0
-+#define APM_BATTERY_STATUS_LOW		1
-+#define APM_BATTERY_STATUS_CRITICAL	2
-+#define APM_BATTERY_STATUS_CHARGING	3
-+#define APM_BATTERY_STATUS_NOT_PRESENT	4
-+#define APM_BATTERY_STATUS_UNKNOWN	0xff
-+
-+	unsigned char	battery_flag;
-+#define APM_BATTERY_FLAG_HIGH		(1 << 0)
-+#define APM_BATTERY_FLAG_LOW		(1 << 1)
-+#define APM_BATTERY_FLAG_CRITICAL	(1 << 2)
-+#define APM_BATTERY_FLAG_CHARGING	(1 << 3)
-+#define APM_BATTERY_FLAG_NOT_PRESENT	(1 << 7)
-+#define APM_BATTERY_FLAG_UNKNOWN	0xff
-+
-+	int		battery_life;
-+	int		time;
-+	int		units;
-+#define APM_UNITS_MINS			0
-+#define APM_UNITS_SECS			1
-+#define APM_UNITS_UNKNOWN		-1
-+
-+};
-+
-+/*
-+ * This allows machines to provide their own "apm get power status" function.
-+ */
-+extern void (*apm_get_power_status)(struct apm_power_info *);
-+
-+/*
-+ * Queue an event (APM_SYS_SUSPEND or APM_CRITICAL_SUSPEND)
-+ */
-+void apm_queue_event(apm_event_t event);
-+
-+#endif
-diff -Naur linux-2.6.17.orig/include/asm-mips/asmmacro-32.h linux-2.6.17/include/asm-mips/asmmacro-32.h
---- linux-2.6.17.orig/include/asm-mips/asmmacro-32.h	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/include/asm-mips/asmmacro-32.h	2006-06-19 18:16:14.000000000 -0700
-@@ -12,7 +12,7 @@
- #include <asm/fpregdef.h>
- #include <asm/mipsregs.h>
- 
--	.macro	fpu_save_double thread status tmp1=t0 tmp2
-+	.macro	fpu_save_double thread status tmp1=t0
- 	cfc1	\tmp1,  fcr31
- 	sdc1	$f0,  THREAD_FPR0(\thread)
- 	sdc1	$f2,  THREAD_FPR2(\thread)
-@@ -70,7 +70,7 @@
- 	sw	\tmp, THREAD_FCR31(\thread)
- 	.endm
- 
--	.macro	fpu_restore_double thread tmp=t0
-+	.macro	fpu_restore_double thread status tmp=t0
- 	lw	\tmp, THREAD_FCR31(\thread)
- 	ldc1	$f0,  THREAD_FPR0(\thread)
- 	ldc1	$f2,  THREAD_FPR2(\thread)
-diff -Naur linux-2.6.17.orig/include/asm-mips/asmmacro-64.h linux-2.6.17/include/asm-mips/asmmacro-64.h
---- linux-2.6.17.orig/include/asm-mips/asmmacro-64.h	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/include/asm-mips/asmmacro-64.h	2006-06-19 18:16:14.000000000 -0700
-@@ -53,12 +53,12 @@
- 	sdc1	$f31, THREAD_FPR31(\thread)
- 	.endm
- 
--	.macro	fpu_save_double thread status tmp1 tmp2
--	sll	\tmp2, \tmp1, 5
--	bgez	\tmp2, 2f
-+	.macro	fpu_save_double thread status tmp
-+	sll	\tmp, \status, 5
-+	bgez	\tmp, 2f
- 	fpu_save_16odd \thread
- 2:
--	fpu_save_16even \thread \tmp1			# clobbers t1
-+	fpu_save_16even \thread \tmp
- 	.endm
- 
- 	.macro	fpu_restore_16even thread tmp=t0
-@@ -101,13 +101,12 @@
- 	ldc1	$f31, THREAD_FPR31(\thread)
- 	.endm
- 
--	.macro	fpu_restore_double thread tmp
--	mfc0	t0, CP0_STATUS
--	sll	t1, t0, 5
--	bgez	t1, 1f				# 16 register mode?
-+	.macro	fpu_restore_double thread status tmp
-+	sll	\tmp, \status, 5
-+	bgez	\tmp, 1f				# 16 register mode?
- 
--	fpu_restore_16odd a0
--1:	fpu_restore_16even a0, t0		# clobbers t0
-+	fpu_restore_16odd \thread
-+1:	fpu_restore_16even \thread \tmp
- 	.endm
- 
- 	.macro	cpu_save_nonscratch thread
-diff -Naur linux-2.6.17.orig/include/asm-mips/asmmacro.h linux-2.6.17/include/asm-mips/asmmacro.h
---- linux-2.6.17.orig/include/asm-mips/asmmacro.h	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/include/asm-mips/asmmacro.h	2006-06-19 18:16:14.000000000 -0700
-@@ -27,14 +27,14 @@
- 	ori	\reg, \reg, TCSTATUS_IXMT
- 	xori	\reg, \reg, TCSTATUS_IXMT
- 	mtc0	\reg, CP0_TCSTATUS
--	ehb
-+	_ehb
- 	.endm
- 
- 	.macro	local_irq_disable reg=t0
- 	mfc0	\reg, CP0_TCSTATUS
- 	ori	\reg, \reg, TCSTATUS_IXMT
- 	mtc0	\reg, CP0_TCSTATUS
--	ehb
-+	_ehb
- 	.endm
- #else
- 	.macro	local_irq_enable reg=t0
-diff -Naur linux-2.6.17.orig/include/asm-mips/bootinfo.h linux-2.6.17/include/asm-mips/bootinfo.h
---- linux-2.6.17.orig/include/asm-mips/bootinfo.h	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/include/asm-mips/bootinfo.h	2006-06-19 18:16:14.000000000 -0700
-@@ -217,6 +217,13 @@
-  */
- #define MACH_GROUP_TITAN       22	/* PMC-Sierra Titan		*/
- #define  MACH_TITAN_YOSEMITE	1	/* PMC-Sierra Yosemite		*/
-+#define  MACH_TITAN_EXCITE	2	/* Basler eXcite		*/
-+
-+/*
-+ * Valid machtype for group NEC EMMA2RH
-+ */
-+#define MACH_GROUP_NEC_EMMA2RH 25	/* NEC EMMA2RH (was 23)		*/
-+#define  MACH_NEC_MARKEINS	0	/* NEC EMMA2RH Mark-eins	*/
- 
- #define CL_SIZE			COMMAND_LINE_SIZE
- 
-@@ -258,4 +265,10 @@
-  * Registers a0, a1, a3 and a4 as passed to the kenrel entry by firmware
-  */
- extern unsigned long fw_arg0, fw_arg1, fw_arg2, fw_arg3;
-+
-+/*
-+ * Platform memory detection hook called by setup_arch
-+ */
-+extern void plat_mem_setup(void);
-+
- #endif /* _ASM_BOOTINFO_H */
-diff -Naur linux-2.6.17.orig/include/asm-mips/cpu-features.h linux-2.6.17/include/asm-mips/cpu-features.h
---- linux-2.6.17.orig/include/asm-mips/cpu-features.h	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/include/asm-mips/cpu-features.h	2006-06-19 18:16:14.000000000 -0700
-@@ -188,19 +188,15 @@
- # endif
- #endif
- 
--#ifdef CONFIG_CPU_MIPSR2
--# if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
--#  define cpu_has_vint		(cpu_data[0].options & MIPS_CPU_VINT)
--# else
--#  define cpu_has_vint			0
--# endif
--# if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
--#  define cpu_has_veic		(cpu_data[0].options & MIPS_CPU_VEIC)
--# else
--#  define cpu_has_veic			0
--# endif
--#else
-+#if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
-+# define cpu_has_vint		(cpu_data[0].options & MIPS_CPU_VINT)
-+#elif !defined(cpu_has_vint)
- # define cpu_has_vint			0
-+#endif
-+
-+#if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
-+# define cpu_has_veic		(cpu_data[0].options & MIPS_CPU_VEIC)
-+#elif !defined(cpu_has_veic)
- # define cpu_has_veic			0
- #endif
- 
-diff -Naur linux-2.6.17.orig/include/asm-mips/ddb5074.h linux-2.6.17/include/asm-mips/ddb5074.h
---- linux-2.6.17.orig/include/asm-mips/ddb5074.h	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/include/asm-mips/ddb5074.h	1969-12-31 16:00:00.000000000 -0800
-@@ -1,11 +0,0 @@
--/*
-- *  include/asm-mips/ddb5074.h -- NEC DDB Vrc-5074 definitions
-- *
-- *  Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
-- *                     Sony Software Development Center Europe (SDCE), Brussels
-- */
--
--extern void ddb5074_led_hex(int hex);
--extern void ddb5074_led_d2(int on);
--extern void ddb5074_led_d3(int on);
--
-diff -Naur linux-2.6.17.orig/include/asm-mips/ddb5xxx/ddb5074.h linux-2.6.17/include/asm-mips/ddb5xxx/ddb5074.h
---- linux-2.6.17.orig/include/asm-mips/ddb5xxx/ddb5074.h	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/include/asm-mips/ddb5xxx/ddb5074.h	1969-12-31 16:00:00.000000000 -0800
-@@ -1,38 +0,0 @@
--/*
-- *  include/asm-mips/ddb5074.h -- NEC DDB Vrc-5074 definitions
-- *
-- *  Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
-- *                     Sony Software Development Center Europe (SDCE), Brussels
-- */
--
--#ifndef _ASM_DDB5XXX_DDB5074_H
--#define _ASM_DDB5XXX_DDB5074_H
--
--#include <asm/nile4.h>
--
--#define DDB_SDRAM_SIZE      0x04000000      /* 64MB */
--
--#define DDB_PCI_IO_BASE     0x06000000
--#define DDB_PCI_IO_SIZE     0x02000000      /* 32 MB */
--
--#define DDB_PCI_MEM_BASE    0x08000000
--#define DDB_PCI_MEM_SIZE    0x08000000  /* 128 MB */
--
--#define DDB_PCI_CONFIG_BASE DDB_PCI_MEM_BASE
--#define DDB_PCI_CONFIG_SIZE DDB_PCI_MEM_SIZE
--
--#define NILE4_PCI_IO_BASE   0xa6000000
--#define NILE4_PCI_MEM_BASE  0xa8000000
--#define NILE4_PCI_CFG_BASE  NILE4_PCI_MEM_BASE
--#define DDB_PCI_IACK_BASE NILE4_PCI_IO_BASE
--
--#define NILE4_IRQ_BASE NUM_I8259_INTERRUPTS
--#define CPU_IRQ_BASE (NUM_NILE4_INTERRUPTS + NILE4_IRQ_BASE)
--#define CPU_NILE4_CASCADE 2
--
--extern void ddb5074_led_hex(int hex);
--extern void ddb5074_led_d2(int on);
--extern void ddb5074_led_d3(int on);
--
--extern void nile4_irq_setup(u32 base);
--#endif
-diff -Naur linux-2.6.17.orig/include/asm-mips/ddb5xxx/ddb5476.h linux-2.6.17/include/asm-mips/ddb5xxx/ddb5476.h
---- linux-2.6.17.orig/include/asm-mips/ddb5xxx/ddb5476.h	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/include/asm-mips/ddb5xxx/ddb5476.h	1969-12-31 16:00:00.000000000 -0800
-@@ -1,157 +0,0 @@
--/*
-- * header file specific for ddb5476
-- *
-- * Copyright (C) 2001 MontaVista Software Inc.
-- * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
-- *
-- * This program is free software; you can redistribute  it and/or modify it
-- * under  the terms of  the GNU General  Public License as published by the
-- * Free Software Foundation;  either version 2 of the  License, or (at your
-- * option) any later version.
-- *
-- */
--
--/*
-- *  Memory map (physical address)
-- *
-- *  Note most of the following address must be properly aligned by the
-- *  corresponding size.  For example, if PCI_IO_SIZE is 16MB, then
-- *  PCI_IO_BASE must be aligned along 16MB boundary.
-- */
--#define DDB_SDRAM_BASE		0x00000000
--#define DDB_SDRAM_SIZE		0x04000000      /* 64MB */
--
--#define	DDB_DCS3_BASE		0x04000000	/* flash 1 */
--#define	DDB_DCS3_SIZE		0x01000000	/* 16MB */
--
--#define	DDB_DCS2_BASE		0x05000000	/* flash 2 */
--#define	DDB_DCS2_SIZE		0x01000000	/* 16MB */
--
--#define DDB_PCI_IO_BASE		0x06000000
--#define DDB_PCI_IO_SIZE		0x02000000      /* 32 MB */
--
--#define	DDB_PCI_MEM_BASE	0x08000000
--#define	DDB_PCI_MEM_SIZE	0x08000000	/* 128 MB */
--
--#define	DDB_DCS5_BASE		0x13000000	/* DDB status regs */
--#define	DDB_DCS5_SIZE		0x00200000	/* 2MB, 8-bit */
--
--#define	DDB_DCS4_BASE		0x14000000	/* DDB control regs */
--#define	DDB_DCS4_SIZE		0x00200000	/* 2MB, 8-bit */
--
--#define DDB_INTCS_BASE		0x1fa00000      /* VRC5476 control regs */
--#define DDB_INTCS_SIZE		0x00200000      /* 2MB */
--
--#define DDB_BOOTCS_BASE         0x1fc00000      /* Boot ROM / EPROM /Flash */
--#define DDB_BOOTCS_SIZE         0x00200000      /* 2 MB - doc says 4MB */
--
--
--/* aliases */
--#define	DDB_PCI_CONFIG_BASE	DDB_PCI_MEM_BASE
--#define	DDB_PCI_CONFIG_SIZE	DDB_PCI_MEM_SIZE
--
--/* PCI intr ack share PCIW0 with PCI IO */
--#define	DDB_PCI_IACK_BASE	DDB_PCI_IO_BASE
--
--/*
-- * Interrupt mapping
-- *
-- * We have three interrupt controllers:
-- *
-- *   . CPU itself - 8 sources
-- *   . i8259 - 16 sources
-- *   . vrc5476 - 16 sources
-- *
-- *  They connected as follows:
-- *    all vrc5476 interrupts are routed to cpu IP2 (by software setting)
-- *    all i2869 are routed to INTC in vrc5476 (by hardware connection)
-- *
-- *  All VRC5476 PCI interrupts are level-triggered (no ack needed).
-- *  All PCI irq but INTC are active low.
-- */
--
--/*
-- * irq number block assignment
-- */
--
--#define	NUM_CPU_IRQ		8
--#define	NUM_I8259_IRQ		16
--#define	NUM_VRC5476_IRQ		16
--
--#define	DDB_IRQ_BASE		0
--
--#define	I8259_IRQ_BASE		DDB_IRQ_BASE
--#define	VRC5476_IRQ_BASE	(I8259_IRQ_BASE + NUM_I8259_IRQ)
--#define	CPU_IRQ_BASE		(VRC5476_IRQ_BASE + NUM_VRC5476_IRQ)
--
--/*
-- * vrc5476 irq defs, see page 52-64 of Vrc5074 system controller manual
-- */
--
--#define VRC5476_IRQ_CPCE	0	/* cpu parity error */
--#define VRC5476_IRQ_CNTD	1	/* cpu no target */
--#define VRC5476_IRQ_MCE		2	/* memory check error */
--#define VRC5476_IRQ_DMA		3	/* DMA */
--#define VRC5476_IRQ_UART	4	/* vrc5476 builtin UART, not used */
--#define VRC5476_IRQ_WDOG	5	/* watchdog timer */
--#define VRC5476_IRQ_GPT		6	/* general purpose timer */
--#define VRC5476_IRQ_LBRT	7	/* local bus read timeout */
--#define VRC5476_IRQ_INTA	8	/* PCI INT #A */
--#define VRC5476_IRQ_INTB	9	/* PCI INT #B */
--#define VRC5476_IRQ_INTC	10	/* PCI INT #C */
--#define VRC5476_IRQ_INTD	11	/* PCI INT #D */
--#define VRC5476_IRQ_INTE	12	/* PCI INT #E */
--#define VRC5476_IRQ_RESERVED_13	13	/* reserved  */
--#define VRC5476_IRQ_PCIS	14	/* PCI SERR #  */
--#define VRC5476_IRQ_PCI		15	/* PCI internal error */
--
--/*
-- * i2859 irq assignment
-- */
--#define I8259_IRQ_RESERVED_0	0
--#define I8259_IRQ_KEYBOARD	1	/* M1543 default */
--#define I8259_IRQ_CASCADE	2
--#define I8259_IRQ_UART_B	3	/* M1543 default, may conflict with RTC according to schematic diagram  */
--#define I8259_IRQ_UART_A	4	/* M1543 default */
--#define I8259_IRQ_PARALLEL	5	/* M1543 default */
--#define I8259_IRQ_RESERVED_6	6
--#define I8259_IRQ_RESERVED_7	7
--#define I8259_IRQ_RTC		8	/* who set this? */
--#define I8259_IRQ_USB		9	/* ddb_setup */
--#define I8259_IRQ_PMU		10	/* ddb_setup */
--#define I8259_IRQ_RESERVED_11	11
--#define I8259_IRQ_RESERVED_12	12	/* m1543_irq_setup */
--#define I8259_IRQ_RESERVED_13	13
--#define I8259_IRQ_HDC1		14	/* default and ddb_setup */
--#define I8259_IRQ_HDC2		15	/* default */
--
--
--/*
-- * misc
-- */
--#define	VRC5476_I8259_CASCADE	VRC5476_IRQ_INTC
--#define	CPU_VRC5476_CASCADE	2
--
--#define is_i8259_irq(irq)       ((irq) < NUM_I8259_IRQ)
--#define nile4_to_irq(n)         ((n)+NUM_I8259_IRQ)
--#define irq_to_nile4(n)         ((n)-NUM_I8259_IRQ)
--
--/*
-- * low-level irq functions
-- */
--#ifndef __ASSEMBLY__
--extern void nile4_map_irq(int nile4_irq, int cpu_irq);
--extern void nile4_map_irq_all(int cpu_irq);
--extern void nile4_enable_irq(int nile4_irq);
--extern void nile4_disable_irq(int nile4_irq);
--extern void nile4_disable_irq_all(void);
--extern u16 nile4_get_irq_stat(int cpu_irq);
--extern void nile4_enable_irq_output(int cpu_irq);
--extern void nile4_disable_irq_output(int cpu_irq);
--extern void nile4_set_pci_irq_polarity(int pci_irq, int high);
--extern void nile4_set_pci_irq_level_or_edge(int pci_irq, int level);
--extern void nile4_clear_irq(int nile4_irq);
--extern void nile4_clear_irq_mask(u32 mask);
--extern u8 nile4_i8259_iack(void);
--extern void nile4_dump_irq_status(void);        /* Debug */
--#endif /* !__ASSEMBLY__ */
-diff -Naur linux-2.6.17.orig/include/asm-mips/ddb5xxx/ddb5xxx.h linux-2.6.17/include/asm-mips/ddb5xxx/ddb5xxx.h
---- linux-2.6.17.orig/include/asm-mips/ddb5xxx/ddb5xxx.h	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/include/asm-mips/ddb5xxx/ddb5xxx.h	2006-06-19 18:16:14.000000000 -0700
-@@ -174,13 +174,8 @@
- 
- static inline void ddb_sync(void)
- {
--/* The DDB5074 doesn't seem to like these accesses. They kill the board on
-- * interrupt load
-- */
--#ifndef CONFIG_DDB5074
-     volatile u32 *p = (volatile u32 *)0xbfc00000;
-     (void)(*p);
--#endif
- }
- 
- static inline void ddb_out32(u32 offset, u32 val)
-@@ -260,11 +255,7 @@
- /*
-  * include the board dependent part
-  */
--#if defined(CONFIG_DDB5074)
--#include <asm/ddb5xxx/ddb5074.h>
--#elif defined(CONFIG_DDB5476)
--#include <asm/ddb5xxx/ddb5476.h>
--#elif defined(CONFIG_DDB5477)
-+#if defined(CONFIG_DDB5477)
- #include <asm/ddb5xxx/ddb5477.h>
- #else
- #error "Unknown DDB board!"
-diff -Naur linux-2.6.17.orig/include/asm-mips/emma2rh/emma2rh.h linux-2.6.17/include/asm-mips/emma2rh/emma2rh.h
---- linux-2.6.17.orig/include/asm-mips/emma2rh/emma2rh.h	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/include/asm-mips/emma2rh/emma2rh.h	2006-06-19 18:16:14.000000000 -0700
-@@ -0,0 +1,330 @@
-+/*
-+ *  include/asm-mips/emma2rh/emma2rh.h
-+ *      This file is EMMA2RH common header.
-+ *
-+ *  Copyright (C) NEC Electronics Corporation 2005-2006
-+ *
-+ *  This file based on include/asm-mips/ddb5xxx/ddb5xxx.h
-+ *          Copyright 2001 MontaVista Software Inc.
-+ *
-+ *  This program is free software; you can redistribute it and/or modify
-+ *  it under the terms of the GNU General Public License as published by
-+ *  the Free Software Foundation; either version 2 of the License, or
-+ *  (at your option) any later version.
-+ *
-+ *  This program is distributed in the hope that it will be useful,
-+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ *  GNU General Public License for more details.
-+ *
-+ *  You should have received a copy of the GNU General Public License
-+ *  along with this program; if not, write to the Free Software
-+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-+ */
-+#ifndef __ASM_EMMA2RH_EMMA2RH_H
-+#define __ASM_EMMA2RH_EMMA2RH_H
-+
-+/*
-+ * EMMA2RH registers
-+ */
-+#define REGBASE 0x10000000
-+
-+#define EMMA2RH_BHIF_STRAP_0	(0x000010+REGBASE)
-+#define EMMA2RH_BHIF_INT_ST_0	(0x000030+REGBASE)
-+#define EMMA2RH_BHIF_INT_ST_1	(0x000034+REGBASE)
-+#define EMMA2RH_BHIF_INT_ST_2	(0x000038+REGBASE)
-+#define EMMA2RH_BHIF_INT_EN_0	(0x000040+REGBASE)
-+#define EMMA2RH_BHIF_INT_EN_1	(0x000044+REGBASE)
-+#define EMMA2RH_BHIF_INT_EN_2	(0x000048+REGBASE)
-+#define EMMA2RH_BHIF_INT1_EN_0	(0x000050+REGBASE)
-+#define EMMA2RH_BHIF_INT1_EN_1	(0x000054+REGBASE)
-+#define EMMA2RH_BHIF_INT1_EN_2	(0x000058+REGBASE)
-+#define EMMA2RH_BHIF_SW_INT	(0x000070+REGBASE)
-+#define EMMA2RH_BHIF_SW_INT_EN	(0x000080+REGBASE)
-+#define EMMA2RH_BHIF_SW_INT_CLR	(0x000090+REGBASE)
-+#define EMMA2RH_BHIF_MAIN_CTRL	(0x0000b4+REGBASE)
-+#define EMMA2RH_BHIF_EXCEPT_VECT_BASE_ADDRESS	(0x0000c0+REGBASE)
-+#define EMMA2RH_GPIO_DIR	(0x110d20+REGBASE)
-+#define EMMA2RH_GPIO_INT_ST	(0x110d30+REGBASE)
-+#define EMMA2RH_GPIO_INT_MASK	(0x110d3c+REGBASE)
-+#define EMMA2RH_GPIO_INT_MODE	(0x110d48+REGBASE)
-+#define EMMA2RH_GPIO_INT_CND_A	(0x110d54+REGBASE)
-+#define EMMA2RH_GPIO_INT_CND_B	(0x110d60+REGBASE)
-+#define EMMA2RH_PBRD_INT_EN	(0x100010+REGBASE)
-+#define EMMA2RH_PBRD_CLKSEL	(0x100028+REGBASE)
-+#define EMMA2RH_PFUR0_BASE	(0x101000+REGBASE)
-+#define EMMA2RH_PFUR1_BASE	(0x102000+REGBASE)
-+#define EMMA2RH_PFUR2_BASE	(0x103000+REGBASE)
-+#define EMMA2RH_PIIC0_BASE	(0x107000+REGBASE)
-+#define EMMA2RH_PIIC1_BASE	(0x108000+REGBASE)
-+#define EMMA2RH_PIIC2_BASE	(0x109000+REGBASE)
-+#define EMMA2RH_PCI_CONTROL	(0x200000+REGBASE)
-+#define EMMA2RH_PCI_ARBIT_CTR	(0x200004+REGBASE)
-+#define EMMA2RH_PCI_IWIN0_CTR	(0x200010+REGBASE)
-+#define EMMA2RH_PCI_IWIN1_CTR	(0x200014+REGBASE)
-+#define EMMA2RH_PCI_INIT_ESWP	(0x200018+REGBASE)
-+#define EMMA2RH_PCI_INT		(0x200020+REGBASE)
-+#define EMMA2RH_PCI_INT_EN	(0x200024+REGBASE)
-+#define EMMA2RH_PCI_TWIN_CTR	(0x200030+REGBASE)
-+#define EMMA2RH_PCI_TWIN_BADR	(0x200034+REGBASE)
-+#define EMMA2RH_PCI_TWIN0_DADR	(0x200038+REGBASE)
-+#define EMMA2RH_PCI_TWIN1_DADR	(0x20003c+REGBASE)
-+
-+/*
-+ *  Memory map (physical address)
-+ *
-+ *  Note most of the following address must be properly aligned by the
-+ *  corresponding size.  For example, if PCI_IO_SIZE is 16MB, then
-+ *  PCI_IO_BASE must be aligned along 16MB boundary.
-+ */
-+
-+/* the actual ram size is detected at run-time */
-+#define EMMA2RH_RAM_BASE	0x00000000
-+#define EMMA2RH_RAM_SIZE	0x10000000	/* less than 256MB */
-+
-+#define EMMA2RH_IO_BASE		0x10000000
-+#define EMMA2RH_IO_SIZE		0x01000000	/* 16 MB */
-+
-+#define EMMA2RH_GENERALIO_BASE	0x11000000
-+#define EMMA2RH_GENERALIO_SIZE	0x01000000	/* 16 MB */
-+
-+#define EMMA2RH_PCI_IO_BASE	0x12000000
-+#define EMMA2RH_PCI_IO_SIZE	0x02000000	/* 32 MB */
-+
-+#define EMMA2RH_PCI_MEM_BASE	0x14000000
-+#define EMMA2RH_PCI_MEM_SIZE	0x08000000	/* 128 MB */
-+
-+#define EMMA2RH_ROM_BASE	0x1c000000
-+#define EMMA2RH_ROM_SIZE	0x04000000	/* 64 MB */
-+
-+#define EMMA2RH_PCI_CONFIG_BASE	EMMA2RH_PCI_IO_BASE
-+#define EMMA2RH_PCI_CONFIG_SIZE	EMMA2RH_PCI_IO_SIZE
-+
-+#define NUM_CPU_IRQ		8
-+#define NUM_EMMA2RH_IRQ		96
-+
-+#define CPU_EMMA2RH_CASCADE	2
-+#define EMMA2RH_IRQ_BASE	0
-+
-+/*
-+ * emma2rh irq defs
-+ */
-+
-+#define EMMA2RH_IRQ_INT0	(0 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT1	(1 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT2	(2 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT3	(3 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT4	(4 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT5	(5 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT6	(6 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT7	(7 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT8	(8 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT9	(9 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT10	(10 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT11	(11 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT12	(12 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT13	(13 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT14	(14 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT15	(15 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT16	(16 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT17	(17 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT18	(18 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT19	(19 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT20	(20 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT21	(21 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT22	(22 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT23	(23 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT24	(24 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT25	(25 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT26	(26 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT27	(27 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT28	(28 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT29	(29 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT30	(30 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT31	(31 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT32	(32 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT33	(33 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT34	(34 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT35	(35 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT36	(36 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT37	(37 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT38	(38 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT39	(39 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT40	(40 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT41	(41 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT42	(42 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT43	(43 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT44	(44 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT45	(45 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT46	(46 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT47	(47 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT48	(48 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT49	(49 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT50	(50 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT51	(51 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT52	(52 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT53	(53 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT54	(54 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT55	(55 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT56	(56 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT57	(57 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT58	(58 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT59	(59 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT60	(60 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT61	(61 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT62	(62 + EMMA2RH_IRQ_BASE)
-+#define EMMA2RH_IRQ_INT63	(63 + EMMA2RH_IRQ_BASE)
-+
-+#define EMMA2RH_IRQ_PFUR0	EMMA2RH_IRQ_INT49
-+#define EMMA2RH_IRQ_PFUR1	EMMA2RH_IRQ_INT50
-+#define EMMA2RH_IRQ_PFUR2	EMMA2RH_IRQ_INT51
-+#define EMMA2RH_IRQ_PIIC0	EMMA2RH_IRQ_INT56
-+#define EMMA2RH_IRQ_PIIC1	EMMA2RH_IRQ_INT57
-+#define EMMA2RH_IRQ_PIIC2	EMMA2RH_IRQ_INT58
-+
-+/*
-+ *  EMMA2RH Register Access
-+ */
-+
-+#define EMMA2RH_BASE (0xa0000000)
-+
-+static inline void emma2rh_sync(void)
-+{
-+	volatile u32 *p = (volatile u32 *)0xbfc00000;
-+	(void)(*p);
-+}
-+
-+static inline void emma2rh_out32(u32 offset, u32 val)
-+{
-+	*(volatile u32 *)(EMMA2RH_BASE | offset) = val;
-+	emma2rh_sync();
-+}
-+
-+static inline u32 emma2rh_in32(u32 offset)
-+{
-+	u32 val = *(volatile u32 *)(EMMA2RH_BASE | offset);
-+	emma2rh_sync();
-+	return val;
-+}
-+
-+static inline void emma2rh_out16(u32 offset, u16 val)
-+{
-+	*(volatile u16 *)(EMMA2RH_BASE | offset) = val;
-+	emma2rh_sync();
-+}
-+
-+static inline u16 emma2rh_in16(u32 offset)
-+{
-+	u16 val = *(volatile u16 *)(EMMA2RH_BASE | offset);
-+	emma2rh_sync();
-+	return val;
-+}
-+
-+static inline void emma2rh_out8(u32 offset, u8 val)
-+{
-+	*(volatile u8 *)(EMMA2RH_BASE | offset) = val;
-+	emma2rh_sync();
-+}
-+
-+static inline u8 emma2rh_in8(u32 offset)
-+{
-+	u8 val = *(volatile u8 *)(EMMA2RH_BASE | offset);
-+	emma2rh_sync();
-+	return val;
-+}
-+
-+/**
-+ * IIC registers map
-+ **/
-+
-+/*---------------------------------------------------------------------------*/
-+/* CNT - Control register (00H R/W)                                          */
-+/*---------------------------------------------------------------------------*/
-+#define SPT         0x00000001
-+#define STT         0x00000002
-+#define ACKE        0x00000004
-+#define WTIM        0x00000008
-+#define SPIE        0x00000010
-+#define WREL        0x00000020
-+#define LREL        0x00000040
-+#define IICE        0x00000080
-+#define CNT_RESERVED    0x000000ff	/* reserved bit 0 */
-+
-+#define I2C_EMMA_START      (IICE | STT)
-+#define I2C_EMMA_STOP       (IICE | SPT)
-+#define I2C_EMMA_REPSTART   I2C_EMMA_START
-+
-+/*---------------------------------------------------------------------------*/
-+/* STA - Status register (10H Read)                                          */
-+/*---------------------------------------------------------------------------*/
-+#define MSTS        0x00000080
-+#define ALD         0x00000040
-+#define EXC         0x00000020
-+#define COI         0x00000010
-+#define TRC         0x00000008
-+#define ACKD        0x00000004
-+#define STD         0x00000002
-+#define SPD         0x00000001
-+
-+/*---------------------------------------------------------------------------*/
-+/* CSEL - Clock select register (20H R/W)                                    */
-+/*---------------------------------------------------------------------------*/
-+#define FCL         0x00000080
-+#define ND50        0x00000040
-+#define CLD         0x00000020
-+#define DAD         0x00000010
-+#define SMC         0x00000008
-+#define DFC         0x00000004
-+#define CL          0x00000003
-+#define CSEL_RESERVED   0x000000ff	/* reserved bit 0 */
-+
-+#define FAST397     0x0000008b
-+#define FAST297     0x0000008a
-+#define FAST347     0x0000000b
-+#define FAST260     0x0000000a
-+#define FAST130     0x00000008
-+#define STANDARD108 0x00000083
-+#define STANDARD83  0x00000082
-+#define STANDARD95  0x00000003
-+#define STANDARD73  0x00000002
-+#define STANDARD36  0x00000001
-+#define STANDARD71  0x00000000
-+
-+/*---------------------------------------------------------------------------*/
-+/* SVA - Slave address register (30H R/W)                                    */
-+/*---------------------------------------------------------------------------*/
-+#define SVA         0x000000fe
-+
-+/*---------------------------------------------------------------------------*/
-+/* SHR - Shift register (40H R/W)                                            */
-+/*---------------------------------------------------------------------------*/
-+#define SR          0x000000ff
-+
-+/*---------------------------------------------------------------------------*/
-+/* INT - Interrupt register (50H R/W)                                        */
-+/* INTM - Interrupt mask register (60H R/W)                                  */
-+/*---------------------------------------------------------------------------*/
-+#define INTE0       0x00000001
-+
-+/***********************************************************************
-+ * I2C registers
-+ ***********************************************************************
-+ */
-+#define I2C_EMMA_CNT            0x00
-+#define I2C_EMMA_STA            0x10
-+#define I2C_EMMA_CSEL           0x20
-+#define I2C_EMMA_SVA            0x30
-+#define I2C_EMMA_SHR            0x40
-+#define I2C_EMMA_INT            0x50
-+#define I2C_EMMA_INTM           0x60
-+
-+/*
-+ * include the board dependent part
-+ */
-+#if defined(CONFIG_MARKEINS)
-+#include <asm/emma2rh/markeins.h>
-+#else
-+#error "Unknown EMMA2RH board!"
-+#endif
-+
-+#endif /* __ASM_EMMA2RH_EMMA2RH_H */
-diff -Naur linux-2.6.17.orig/include/asm-mips/emma2rh/markeins.h linux-2.6.17/include/asm-mips/emma2rh/markeins.h
---- linux-2.6.17.orig/include/asm-mips/emma2rh/markeins.h	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/include/asm-mips/emma2rh/markeins.h	2006-06-19 18:16:14.000000000 -0700
-@@ -0,0 +1,76 @@
-+/*
-+ *  include/asm-mips/emma2rh/markeins.h
-+ *      This file is EMMA2RH board depended header.
-+ *
-+ *  Copyright (C) NEC Electronics Corporation 2005-2006
-+ *
-+ *  This file based on include/asm-mips/ddb5xxx/ddb5xxx.h
-+ *          Copyright 2001 MontaVista Software Inc.
-+ *
-+ *  This program is free software; you can redistribute it and/or modify
-+ *  it under the terms of the GNU General Public License as published by
-+ *  the Free Software Foundation; either version 2 of the License, or
-+ *  (at your option) any later version.
-+ *
-+ *  This program is distributed in the hope that it will be useful,
-+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ *  GNU General Public License for more details.
-+ *
-+ *  You should have received a copy of the GNU General Public License
-+ *  along with this program; if not, write to the Free Software
-+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-+ */
-+
-+#ifndef MARKEINS_H
-+#define MARKEINS_H
-+
-+#define NUM_EMMA2RH_IRQ_SW	32
-+#define NUM_EMMA2RH_IRQ_GPIO	32
-+
-+#define EMMA2RH_SW_CASCADE	(EMMA2RH_IRQ_INT7 - EMMA2RH_IRQ_INT0)
-+#define EMMA2RH_GPIO_CASCADE	(EMMA2RH_IRQ_INT46 - EMMA2RH_IRQ_INT0)
-+
-+#define EMMA2RH_SW_IRQ_BASE	(EMMA2RH_IRQ_BASE + NUM_EMMA2RH_IRQ)
-+#define EMMA2RH_GPIO_IRQ_BASE	(EMMA2RH_SW_IRQ_BASE + NUM_EMMA2RH_IRQ_SW)
-+#define CPU_IRQ_BASE		(EMMA2RH_GPIO_IRQ_BASE + NUM_EMMA2RH_IRQ_GPIO)
-+
-+#define EMMA2RH_SW_IRQ_INT0	(0+EMMA2RH_SW_IRQ_BASE)
-+#define EMMA2RH_SW_IRQ_INT1	(1+EMMA2RH_SW_IRQ_BASE)
-+#define EMMA2RH_SW_IRQ_INT2	(2+EMMA2RH_SW_IRQ_BASE)
-+#define EMMA2RH_SW_IRQ_INT3	(3+EMMA2RH_SW_IRQ_BASE)
-+#define EMMA2RH_SW_IRQ_INT4	(4+EMMA2RH_SW_IRQ_BASE)
-+#define EMMA2RH_SW_IRQ_INT5	(5+EMMA2RH_SW_IRQ_BASE)
-+#define EMMA2RH_SW_IRQ_INT6	(6+EMMA2RH_SW_IRQ_BASE)
-+#define EMMA2RH_SW_IRQ_INT7	(7+EMMA2RH_SW_IRQ_BASE)
-+#define EMMA2RH_SW_IRQ_INT8	(8+EMMA2RH_SW_IRQ_BASE)
-+#define EMMA2RH_SW_IRQ_INT9	(9+EMMA2RH_SW_IRQ_BASE)
-+#define EMMA2RH_SW_IRQ_INT10	(10+EMMA2RH_SW_IRQ_BASE)
-+#define EMMA2RH_SW_IRQ_INT11	(11+EMMA2RH_SW_IRQ_BASE)
-+#define EMMA2RH_SW_IRQ_INT12	(12+EMMA2RH_SW_IRQ_BASE)
-+#define EMMA2RH_SW_IRQ_INT13	(13+EMMA2RH_SW_IRQ_BASE)
-+#define EMMA2RH_SW_IRQ_INT14	(14+EMMA2RH_SW_IRQ_BASE)
-+#define EMMA2RH_SW_IRQ_INT15	(15+EMMA2RH_SW_IRQ_BASE)
-+#define EMMA2RH_SW_IRQ_INT16	(16+EMMA2RH_SW_IRQ_BASE)
-+#define EMMA2RH_SW_IRQ_INT17	(17+EMMA2RH_SW_IRQ_BASE)
-+#define EMMA2RH_SW_IRQ_INT18	(18+EMMA2RH_SW_IRQ_BASE)
-+#define EMMA2RH_SW_IRQ_INT19	(19+EMMA2RH_SW_IRQ_BASE)
-+#define EMMA2RH_SW_IRQ_INT20	(20+EMMA2RH_SW_IRQ_BASE)
-+#define EMMA2RH_SW_IRQ_INT21	(21+EMMA2RH_SW_IRQ_BASE)
-+#define EMMA2RH_SW_IRQ_INT22	(22+EMMA2RH_SW_IRQ_BASE)
-+#define EMMA2RH_SW_IRQ_INT23	(23+EMMA2RH_SW_IRQ_BASE)
-+#define EMMA2RH_SW_IRQ_INT24	(24+EMMA2RH_SW_IRQ_BASE)
-+#define EMMA2RH_SW_IRQ_INT25	(25+EMMA2RH_SW_IRQ_BASE)
-+#define EMMA2RH_SW_IRQ_INT26	(26+EMMA2RH_SW_IRQ_BASE)
-+#define EMMA2RH_SW_IRQ_INT27	(27+EMMA2RH_SW_IRQ_BASE)
-+#define EMMA2RH_SW_IRQ_INT28	(28+EMMA2RH_SW_IRQ_BASE)
-+#define EMMA2RH_SW_IRQ_INT29	(29+EMMA2RH_SW_IRQ_BASE)
-+#define EMMA2RH_SW_IRQ_INT30	(30+EMMA2RH_SW_IRQ_BASE)
-+#define EMMA2RH_SW_IRQ_INT31	(31+EMMA2RH_SW_IRQ_BASE)
-+
-+#define MARKEINS_PCI_IRQ_INTA	EMMA2RH_GPIO_IRQ_BASE+15
-+#define MARKEINS_PCI_IRQ_INTB	EMMA2RH_GPIO_IRQ_BASE+16
-+#define MARKEINS_PCI_IRQ_INTC	EMMA2RH_GPIO_IRQ_BASE+17
-+#define MARKEINS_PCI_IRQ_INTD	EMMA2RH_GPIO_IRQ_BASE+18
-+
-+#endif /* CONFIG_MARKEINS */
-diff -Naur linux-2.6.17.orig/include/asm-mips/fpu_emulator.h linux-2.6.17/include/asm-mips/fpu_emulator.h
---- linux-2.6.17.orig/include/asm-mips/fpu_emulator.h	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/include/asm-mips/fpu_emulator.h	2006-06-19 18:16:14.000000000 -0700
-@@ -12,8 +12,8 @@
-  *  with this program; if not, write to the Free Software Foundation, Inc.,
-  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
-  *
-- * Further private data for which no space exists in mips_fpu_soft_struct.
-- * This should be subsumed into the mips_fpu_soft_struct structure as
-+ * Further private data for which no space exists in mips_fpu_struct.
-+ * This should be subsumed into the mips_fpu_struct structure as
-  * defined in processor.h as soon as the absurd wired absolute assembler
-  * offsets become dynamic at compile time.
-  *
-diff -Naur linux-2.6.17.orig/include/asm-mips/fpu.h linux-2.6.17/include/asm-mips/fpu.h
---- linux-2.6.17.orig/include/asm-mips/fpu.h	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/include/asm-mips/fpu.h	2006-06-19 18:16:14.000000000 -0700
-@@ -138,10 +138,9 @@
- 	if (cpu_has_fpu) {
- 		if ((tsk == current) && __is_fpu_owner())
- 			_save_fp(current);
--		return tsk->thread.fpu.hard.fpr;
- 	}
- 
--	return tsk->thread.fpu.soft.fpr;
-+	return tsk->thread.fpu.fpr;
- }
- 
- #endif /* _ASM_FPU_H */
-diff -Naur linux-2.6.17.orig/include/asm-mips/futex.h linux-2.6.17/include/asm-mips/futex.h
---- linux-2.6.17.orig/include/asm-mips/futex.h	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/include/asm-mips/futex.h	2006-06-19 18:16:14.000000000 -0700
-@@ -22,51 +22,53 @@
- 		"	.set	push				\n"	\
- 		"	.set	noat				\n"	\
- 		"	.set	mips3				\n"	\
--		"1:	ll	%1, (%3)	# __futex_atomic_op	\n" \
-+		"1:	ll	%1, %4	# __futex_atomic_op	\n"	\
- 		"	.set	mips0				\n"	\
- 		"	" insn	"				\n"	\
- 		"	.set	mips3				\n"	\
--		"2:	sc	$1, (%3)			\n"	\
-+		"2:	sc	$1, %2				\n"	\
- 		"	beqzl	$1, 1b				\n"	\
- 		__FUTEX_SMP_SYNC					\
- 		"3:						\n"	\
- 		"	.set	pop				\n"	\
- 		"	.set	mips0				\n"	\
- 		"	.section .fixup,\"ax\"			\n"	\
--		"4:	li	%0, %5				\n"	\
-+		"4:	li	%0, %6				\n"	\
- 		"	j	2b				\n"	\
- 		"	.previous				\n"	\
- 		"	.section __ex_table,\"a\"		\n"	\
- 		"	"__UA_ADDR "\t1b, 4b			\n"	\
- 		"	"__UA_ADDR "\t2b, 4b			\n"	\
- 		"	.previous				\n"	\
--		: "=r" (ret), "=r" (oldval)				\
--		: "0" (0), "r" (uaddr), "Jr" (oparg), "i" (-EFAULT));	\
-+		: "=r" (ret), "=&r" (oldval), "=R" (*uaddr)		\
-+		: "0" (0), "R" (*uaddr), "Jr" (oparg), "i" (-EFAULT)	\
-+		: "memory");						\
- 	} else if (cpu_has_llsc) {					\
- 		__asm__ __volatile__(					\
- 		"	.set	push				\n"	\
- 		"	.set	noat				\n"	\
- 		"	.set	mips3				\n"	\
--		"1:	ll	%1, (%3)	# __futex_atomic_op	\n" \
-+		"1:	ll	%1, %4	# __futex_atomic_op	\n"	\
- 		"	.set	mips0				\n"	\
- 		"	" insn	"				\n"	\
- 		"	.set	mips3				\n"	\
--		"2:	sc	$1, (%3)			\n"	\
-+		"2:	sc	$1, %2				\n"	\
- 		"	beqz	$1, 1b				\n"	\
- 		__FUTEX_SMP_SYNC					\
- 		"3:						\n"	\
- 		"	.set	pop				\n"	\
- 		"	.set	mips0				\n"	\
- 		"	.section .fixup,\"ax\"			\n"	\
--		"4:	li	%0, %5				\n"	\
-+		"4:	li	%0, %6				\n"	\
- 		"	j	2b				\n"	\
- 		"	.previous				\n"	\
- 		"	.section __ex_table,\"a\"		\n"	\
- 		"	"__UA_ADDR "\t1b, 4b			\n"	\
- 		"	"__UA_ADDR "\t2b, 4b			\n"	\
- 		"	.previous				\n"	\
--		: "=r" (ret), "=r" (oldval)				\
--		: "0" (0), "r" (uaddr), "Jr" (oparg), "i" (-EFAULT));	\
-+		: "=r" (ret), "=&r" (oldval), "=R" (*uaddr)		\
-+		: "0" (0), "R" (*uaddr), "Jr" (oparg), "i" (-EFAULT)	\
-+		: "memory");						\
- 	} else								\
- 		ret = -ENOSYS;						\
- }
-@@ -89,23 +91,23 @@
- 
- 	switch (op) {
- 	case FUTEX_OP_SET:
--		__futex_atomic_op("move	$1, %z4", ret, oldval, uaddr, oparg);
-+		__futex_atomic_op("move	$1, %z5", ret, oldval, uaddr, oparg);
- 		break;
- 
- 	case FUTEX_OP_ADD:
--		__futex_atomic_op("addu	$1, %1, %z4",
-+		__futex_atomic_op("addu	$1, %1, %z5",
- 		                  ret, oldval, uaddr, oparg);
- 		break;
- 	case FUTEX_OP_OR:
--		__futex_atomic_op("or	$1, %1, %z4",
-+		__futex_atomic_op("or	$1, %1, %z5",
- 		                  ret, oldval, uaddr, oparg);
- 		break;
- 	case FUTEX_OP_ANDN:
--		__futex_atomic_op("and	$1, %1, %z4",
-+		__futex_atomic_op("and	$1, %1, %z5",
- 		                  ret, oldval, uaddr, ~oparg);
- 		break;
- 	case FUTEX_OP_XOR:
--		__futex_atomic_op("xor	$1, %1, %z4",
-+		__futex_atomic_op("xor	$1, %1, %z5",
- 		                  ret, oldval, uaddr, oparg);
- 		break;
- 	default:
-diff -Naur linux-2.6.17.orig/include/asm-mips/io.h linux-2.6.17/include/asm-mips/io.h
---- linux-2.6.17.orig/include/asm-mips/io.h	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/include/asm-mips/io.h	2006-06-19 18:16:14.000000000 -0700
-@@ -519,34 +519,6 @@
- }
- 
- /*
-- * Memory Mapped I/O
-- */
--#define ioread8(addr)		readb(addr)
--#define ioread16(addr)		readw(addr)
--#define ioread32(addr)		readl(addr)
--
--#define iowrite8(b,addr)	writeb(b,addr)
--#define iowrite16(w,addr)	writew(w,addr)
--#define iowrite32(l,addr)	writel(l,addr)
--
--#define ioread8_rep(a,b,c)	readsb(a,b,c)
--#define ioread16_rep(a,b,c)	readsw(a,b,c)
--#define ioread32_rep(a,b,c)	readsl(a,b,c)
--
--#define iowrite8_rep(a,b,c)	writesb(a,b,c)
--#define iowrite16_rep(a,b,c)	writesw(a,b,c)
--#define iowrite32_rep(a,b,c)	writesl(a,b,c)
--
--/* Create a virtual mapping cookie for an IO port range */
--extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
--extern void ioport_unmap(void __iomem *);
--
--/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
--struct pci_dev;
--extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
--extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
--
--/*
-  * ISA space is 'always mapped' on currently supported MIPS systems, no need
-  * to explicitly ioremap() it. The fact that the ISA IO space is mapped
-  * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
-diff -Naur linux-2.6.17.orig/include/asm-mips/irq.h linux-2.6.17/include/asm-mips/irq.h
---- linux-2.6.17.orig/include/asm-mips/irq.h	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/include/asm-mips/irq.h	2006-06-19 18:16:14.000000000 -0700
-@@ -77,4 +77,8 @@
-                           unsigned long hwmask);
- #endif /* CONFIG_MIPS_MT_SMTC */
- 
-+#ifdef CONFIG_SMP
-+#define ARCH_HAS_IRQ_PER_CPU
-+#endif
-+
- #endif /* _ASM_IRQ_H */
-diff -Naur linux-2.6.17.orig/include/asm-mips/mach-au1x00/au1xxx_ide.h linux-2.6.17/include/asm-mips/mach-au1x00/au1xxx_ide.h
---- linux-2.6.17.orig/include/asm-mips/mach-au1x00/au1xxx_ide.h	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/include/asm-mips/mach-au1x00/au1xxx_ide.h	2006-06-19 18:16:14.000000000 -0700
-@@ -84,6 +84,7 @@
- } _auide_hwif;
- 
- #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
-+
- /* HD white list */
- static const struct drive_list_entry dma_white_list [] = {
- /*
-diff -Naur linux-2.6.17.orig/include/asm-mips/mach-ddb5074/mc146818rtc.h linux-2.6.17/include/asm-mips/mach-ddb5074/mc146818rtc.h
---- linux-2.6.17.orig/include/asm-mips/mach-ddb5074/mc146818rtc.h	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/include/asm-mips/mach-ddb5074/mc146818rtc.h	1969-12-31 16:00:00.000000000 -0800
-@@ -1,31 +0,0 @@
--/*
-- * This file is subject to the terms and conditions of the GNU General Public
-- * License.  See the file "COPYING" in the main directory of this archive
-- * for more details.
-- *
-- * Copyright (C) 1998, 2001, 03 by Ralf Baechle
-- *
-- * RTC routines for PC style attached Dallas chip.
-- */
--#ifndef __ASM_MACH_DDB5074_MC146818RTC_H
--#define __ASM_MACH_DDB5074_MC146818RTC_H
--
--#include <asm/ddb5xxx/ddb5074.h>
--#include <asm/ddb5xxx/ddb5xxx.h>
--
--#define RTC_PORT(x)	(0x70 + (x))
--#define RTC_IRQ		8
--
--static inline unsigned char CMOS_READ(unsigned long addr)
--{
--	return *(volatile unsigned char *)(KSEG1ADDR(DDB_PCI_MEM_BASE)+addr);
--}
--
--static inline void CMOS_WRITE(unsigned char data, unsigned long addr)
--{
--	*(volatile unsigned char *)(KSEG1ADDR(DDB_PCI_MEM_BASE)+addr) = data;
--}
--
--#define RTC_ALWAYS_BCD	1
--
--#endif /* __ASM_MACH_DDB5074_MC146818RTC_H */
-diff -Naur linux-2.6.17.orig/include/asm-mips/mach-emma2rh/irq.h linux-2.6.17/include/asm-mips/mach-emma2rh/irq.h
---- linux-2.6.17.orig/include/asm-mips/mach-emma2rh/irq.h	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/include/asm-mips/mach-emma2rh/irq.h	2006-06-19 18:16:14.000000000 -0700
-@@ -0,0 +1,13 @@
-+/*
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License.  See the file "COPYING" in the main directory of this archive
-+ * for more details.
-+ *
-+ * Copyright (C) 2003 by Ralf Baechle
-+ */
-+#ifndef __ASM_MACH_EMMA2RH_IRQ_H
-+#define __ASM_MACH_EMMA2RH_IRQ_H
-+
-+#define NR_IRQS	256
-+
-+#endif /* __ASM_MACH_EMMA2RH_IRQ_H */
-diff -Naur linux-2.6.17.orig/include/asm-mips/mach-excite/cpu-feature-overrides.h linux-2.6.17/include/asm-mips/mach-excite/cpu-feature-overrides.h
---- linux-2.6.17.orig/include/asm-mips/mach-excite/cpu-feature-overrides.h	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/include/asm-mips/mach-excite/cpu-feature-overrides.h	2006-06-19 18:16:14.000000000 -0700
-@@ -0,0 +1,40 @@
-+/*
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License.  See the file "COPYING" in the main directory of this archive
-+ * for more details.
-+ *
-+ * Copyright (C) 2004 Thomas Koeller <thomas.koeller@baslerweb.com>
-+ */
-+#ifndef __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H
-+#define __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H
-+
-+/*
-+ * Basler eXcite has an RM9122 processor.
-+ */
-+#define cpu_has_watch		1
-+#define cpu_has_mips16		0
-+#define cpu_has_divec		0
-+#define cpu_has_vce		0
-+#define cpu_has_cache_cdex_p	0
-+#define cpu_has_cache_cdex_s	0
-+#define cpu_has_prefetch	1
-+#define cpu_has_mcheck		0
-+#define cpu_has_ejtag		0
-+
-+#define cpu_has_llsc		1
-+#define cpu_has_vtag_icache	0
-+#define cpu_has_dc_aliases	0
-+#define cpu_has_ic_fills_f_dc	0
-+#define cpu_has_dsp		0
-+#define cpu_icache_snoops_remote_store	0
-+
-+#define cpu_has_nofpuex		0
-+#define cpu_has_64bits		1
-+
-+#define cpu_has_subset_pcaches	0
-+
-+#define cpu_dcache_line_size()	32
-+#define cpu_icache_line_size()	32
-+#define cpu_scache_line_size()	32
-+
-+#endif /* __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H */
-diff -Naur linux-2.6.17.orig/include/asm-mips/mach-excite/excite.h linux-2.6.17/include/asm-mips/mach-excite/excite.h
---- linux-2.6.17.orig/include/asm-mips/mach-excite/excite.h	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/include/asm-mips/mach-excite/excite.h	2006-06-19 18:16:14.000000000 -0700
-@@ -0,0 +1,155 @@
-+#ifndef __EXCITE_H__
-+#define __EXCITE_H__
-+
-+#include <linux/config.h>
-+#include <linux/init.h>
-+#include <asm/addrspace.h>
-+#include <asm/types.h>
-+
-+#define EXCITE_CPU_EXT_CLOCK 100000000
-+
-+#if !defined(__ASSEMBLER__)
-+void __init excite_kgdb_init(void);
-+void excite_procfs_init(void);
-+extern unsigned long memsize;
-+extern char modetty[];
-+extern u32 unit_id;
-+#endif
-+
-+/* Base name for XICAP devices */
-+#define XICAP_NAME	"xicap_gpi"
-+
-+/* OCD register offsets */
-+#define LKB0		0x0038
-+#define LKB5		0x0128
-+#define LKM5		0x012C
-+#define LKB7		0x0138
-+#define LKM7		0x013c
-+#define LKB8		0x0140
-+#define LKM8		0x0144
-+#define LKB9		0x0148
-+#define LKM9		0x014c
-+#define LKB10		0x0150
-+#define LKM10		0x0154
-+#define LKB11		0x0158
-+#define LKM11		0x015c
-+#define LKB12		0x0160
-+#define LKM12		0x0164
-+#define LKB13		0x0168
-+#define LKM13		0x016c
-+#define LDP0		0x0200
-+#define LDP1		0x0210
-+#define LDP2		0x0220
-+#define LDP3		0x0230
-+#define INTPIN0		0x0A40
-+#define INTPIN1		0x0A44
-+#define INTPIN2		0x0A48
-+#define INTPIN3		0x0A4C
-+#define INTPIN4		0x0A50
-+#define INTPIN5		0x0A54
-+#define INTPIN6		0x0A58
-+#define INTPIN7		0x0A5C
-+
-+
-+
-+
-+/* TITAN register offsets */
-+#define CPRR		0x0004
-+#define CPDSR		0x0008
-+#define CPTC0R		0x000c
-+#define CPTC1R		0x0010
-+#define CPCFG0		0x0020
-+#define CPCFG1		0x0024
-+#define CPDST0A		0x0028
-+#define CPDST0B		0x002c
-+#define CPDST1A		0x0030
-+#define CPDST1B		0x0034
-+#define CPXDSTA		0x0038
-+#define CPXDSTB		0x003c
-+#define CPXCISRA	0x0048
-+#define CPXCISRB	0x004c
-+#define CPGIG0ER	0x0050
-+#define CPGIG1ER	0x0054
-+#define CPGRWL		0x0068
-+#define CPURSLMT	0x00f8
-+#define UACFG		0x0200
-+#define UAINTS		0x0204
-+#define SDRXFCIE	0x4828
-+#define SDTXFCIE	0x4928
-+#define INTP0Status0	0x1B00
-+#define INTP0Mask0	0x1B04
-+#define INTP0Set0	0x1B08
-+#define INTP0Clear0	0x1B0C
-+#define GXCFG		0x5000
-+#define GXDMADRPFX	0x5018
-+#define GXDMA_DESCADR	0x501c
-+#define GXCH0TDESSTRT	0x5054
-+
-+/* IRQ definitions */
-+#define NMICONFIG		0xac0
-+#define TITAN_MSGINT	0xc4
-+#define TITAN_IRQ	((TITAN_MSGINT / 0x20) + 2)
-+#define FPGA0_MSGINT	0x5a
-+#define FPGA0_IRQ	((FPGA0_MSGINT / 0x20) + 2)
-+#define FPGA1_MSGINT	0x7b
-+#define FPGA1_IRQ	((FPGA1_MSGINT / 0x20) + 2)
-+#define PHY_MSGINT	0x9c
-+#define PHY_IRQ		((PHY_MSGINT   / 0x20) + 2)
-+
-+#if defined(CONFIG_BASLER_EXCITE_PROTOTYPE)
-+/* Pre-release units used interrupt pin #9 */
-+#define USB_IRQ		11
-+#else
-+/* Re-designed units use interrupt pin #1 */
-+#define USB_MSGINT	0x39
-+#define USB_IRQ		((USB_MSGINT / 0x20) + 2)
-+#endif
-+#define TIMER_IRQ	12
-+
-+
-+/* Device address ranges */
-+#define EXCITE_OFFS_OCD		0x1fffc000
-+#define	EXCITE_SIZE_OCD		(16 * 1024)
-+#define EXCITE_PHYS_OCD		CPHYSADDR(EXCITE_OFFS_OCD)
-+#define EXCITE_ADDR_OCD		CKSEG1ADDR(EXCITE_OFFS_OCD)
-+
-+#define EXCITE_OFFS_SCRAM 	0x1fffa000
-+#define	EXCITE_SIZE_SCRAM	(8 << 10)
-+#define EXCITE_PHYS_SCRAM 	CPHYSADDR(EXCITE_OFFS_SCRAM)
-+#define EXCITE_ADDR_SCRAM 	CKSEG1ADDR(EXCITE_OFFS_SCRAM)
-+
-+#define EXCITE_OFFS_PCI_IO	0x1fff8000
-+#define	EXCITE_SIZE_PCI_IO	(8 << 10)
-+#define EXCITE_PHYS_PCI_IO	CPHYSADDR(EXCITE_OFFS_PCI_IO)
-+#define EXCITE_ADDR_PCI_IO 	CKSEG1ADDR(EXCITE_OFFS_PCI_IO)
-+
-+#define EXCITE_OFFS_TITAN	0x1fff0000
-+#define EXCITE_SIZE_TITAN	(32 << 10)
-+#define EXCITE_PHYS_TITAN	CPHYSADDR(EXCITE_OFFS_TITAN)
-+#define EXCITE_ADDR_TITAN	CKSEG1ADDR(EXCITE_OFFS_TITAN)
-+
-+#define EXCITE_OFFS_PCI_MEM	0x1ffe0000
-+#define EXCITE_SIZE_PCI_MEM	(64 << 10)
-+#define EXCITE_PHYS_PCI_MEM	CPHYSADDR(EXCITE_OFFS_PCI_MEM)
-+#define EXCITE_ADDR_PCI_MEM	CKSEG1ADDR(EXCITE_OFFS_PCI_MEM)
-+
-+#define EXCITE_OFFS_FPGA	0x1ffdc000
-+#define EXCITE_SIZE_FPGA	(16 << 10)
-+#define EXCITE_PHYS_FPGA	CPHYSADDR(EXCITE_OFFS_FPGA)
-+#define EXCITE_ADDR_FPGA	CKSEG1ADDR(EXCITE_OFFS_FPGA)
-+
-+#define EXCITE_OFFS_NAND	0x1ffd8000
-+#define EXCITE_SIZE_NAND	(16 << 10)
-+#define EXCITE_PHYS_NAND	CPHYSADDR(EXCITE_OFFS_NAND)
-+#define EXCITE_ADDR_NAND	CKSEG1ADDR(EXCITE_OFFS_NAND)
-+
-+#define EXCITE_OFFS_BOOTROM	0x1f000000
-+#define EXCITE_SIZE_BOOTROM	(8 << 20)
-+#define EXCITE_PHYS_BOOTROM	CPHYSADDR(EXCITE_OFFS_BOOTROM)
-+#define EXCITE_ADDR_BOOTROM	CKSEG1ADDR(EXCITE_OFFS_BOOTROM)
-+
-+/* FPGA address offsets */
-+#define EXCITE_FPGA_DPR		0x0104	/* dual-ported ram */
-+#define EXCITE_FPGA_SYSCTL	0x0200	/* system control register block */
-+
-+#endif /* __EXCITE_H__ */
-diff -Naur linux-2.6.17.orig/include/asm-mips/mach-excite/excite_nandflash.h linux-2.6.17/include/asm-mips/mach-excite/excite_nandflash.h
---- linux-2.6.17.orig/include/asm-mips/mach-excite/excite_nandflash.h	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/include/asm-mips/mach-excite/excite_nandflash.h	2006-06-19 18:16:14.000000000 -0700
-@@ -0,0 +1,7 @@
-+#ifndef __EXCITE_NANDFLASH_H__
-+#define __EXCITE_NANDFLASH_H__
-+
-+/* Resource names */
-+#define EXCITE_NANDFLASH_RESOURCE_REGS	"excite_nandflash_regs"
-+
-+#endif /* __EXCITE_NANDFLASH_H__ */
-diff -Naur linux-2.6.17.orig/include/asm-mips/mach-excite/rm9k_eth.h linux-2.6.17/include/asm-mips/mach-excite/rm9k_eth.h
---- linux-2.6.17.orig/include/asm-mips/mach-excite/rm9k_eth.h	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/include/asm-mips/mach-excite/rm9k_eth.h	2006-06-19 18:16:14.000000000 -0700
-@@ -0,0 +1,23 @@
-+#if !defined(__RM9K_ETH_H__)
-+#define __RM9K_ETH_H__
-+
-+#define RM9K_GE_NAME			"rm9k_ge"
-+
-+/* Resource names */
-+#define RM9K_GE_RESOURCE_MAC      	"rm9k_ge_mac"
-+#define RM9K_GE_RESOURCE_MSTAT      	"rm9k_ge_mstat"
-+#define RM9K_GE_RESOURCE_PKTPROC	"rm9k_ge_pktproc"
-+#define RM9K_GE_RESOURCE_XDMA		"rm9k_ge_xdma"
-+#define RM9K_GE_RESOURCE_FIFO_RX  	"rm9k_ge_fifo_rx"
-+#define RM9K_GE_RESOURCE_FIFO_TX  	"rm9k_ge_fifo_tx"
-+#define RM9K_GE_RESOURCE_FIFOMEM_RX  	"rm9k_ge_fifo_memory_rx"
-+#define RM9K_GE_RESOURCE_FIFOMEM_TX  	"rm9k_ge_fifo_memory_tx"
-+#define RM9K_GE_RESOURCE_PHY      	"rm9k_ge_phy"
-+#define RM9K_GE_RESOURCE_DMADESC_RX  	"rm9k_ge_dmadesc_rx"
-+#define RM9K_GE_RESOURCE_DMADESC_TX  	"rm9k_ge_dmadesc_tx"
-+#define RM9K_GE_RESOURCE_IRQ_MAIN	"rm9k_ge_irq_main"
-+#define RM9K_GE_RESOURCE_IRQ_PHY	"rm9k_ge_irq_phy"
-+#define RM9K_GE_RESOURCE_GPI_SLICE	"rm9k_ge_gpi_slice"
-+#define RM9K_GE_RESOURCE_MDIO_CHANNEL	"rm9k_ge_mdio_channel"
-+
-+#endif /* !defined(__RM9K_ETH_H__) */
-diff -Naur linux-2.6.17.orig/include/asm-mips/mach-excite/rm9k_wdt.h linux-2.6.17/include/asm-mips/mach-excite/rm9k_wdt.h
---- linux-2.6.17.orig/include/asm-mips/mach-excite/rm9k_wdt.h	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/include/asm-mips/mach-excite/rm9k_wdt.h	2006-06-19 18:16:14.000000000 -0700
-@@ -0,0 +1,12 @@
-+#ifndef __RM9K_WDT_H__
-+#define __RM9K_WDT_H__
-+
-+/* Device name */
-+#define WDT_NAME		"wdt_gpi"
-+
-+/* Resource names */
-+#define WDT_RESOURCE_REGS	"excite_watchdog_regs"
-+#define WDT_RESOURCE_IRQ	"excite_watchdog_irq"
-+#define WDT_RESOURCE_COUNTER	"excite_watchdog_counter"
-+
-+#endif /* __RM9K_WDT_H__ */
-diff -Naur linux-2.6.17.orig/include/asm-mips/mach-excite/rm9k_xicap.h linux-2.6.17/include/asm-mips/mach-excite/rm9k_xicap.h
---- linux-2.6.17.orig/include/asm-mips/mach-excite/rm9k_xicap.h	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/include/asm-mips/mach-excite/rm9k_xicap.h	2006-06-19 18:16:14.000000000 -0700
-@@ -0,0 +1,16 @@
-+#ifndef __EXCITE_XICAP_H__
-+#define __EXCITE_XICAP_H__
-+
-+
-+/* Resource names */
-+#define XICAP_RESOURCE_FIFO_RX		"xicap_fifo_rx"
-+#define XICAP_RESOURCE_FIFO_TX		"xicap_fifo_tx"
-+#define XICAP_RESOURCE_XDMA 		"xicap_xdma"
-+#define XICAP_RESOURCE_DMADESC		"xicap_dmadesc"
-+#define XICAP_RESOURCE_PKTPROC  	"xicap_pktproc"
-+#define XICAP_RESOURCE_IRQ		"xicap_irq"
-+#define XICAP_RESOURCE_GPI_SLICE	"xicap_gpi_slice"
-+#define XICAP_RESOURCE_FIFO_BLK		"xicap_fifo_blocks"
-+#define XICAP_RESOURCE_PKT_STREAM	"xicap_pkt_stream"
-+
-+#endif /* __EXCITE_XICAP_H__ */
-diff -Naur linux-2.6.17.orig/include/asm-mips/mach-mips/irq.h linux-2.6.17/include/asm-mips/mach-mips/irq.h
---- linux-2.6.17.orig/include/asm-mips/mach-mips/irq.h	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/include/asm-mips/mach-mips/irq.h	2006-06-19 18:16:14.000000000 -0700
-@@ -5,10 +5,4 @@
- 
- #define NR_IRQS	256
- 
--#ifdef CONFIG_SMP
--
--#define ARCH_HAS_IRQ_PER_CPU
--
--#endif
--
- #endif /* __ASM_MACH_MIPS_IRQ_H */
-diff -Naur linux-2.6.17.orig/include/asm-mips/mach-rm200/cpu-feature-overrides.h linux-2.6.17/include/asm-mips/mach-rm200/cpu-feature-overrides.h
---- linux-2.6.17.orig/include/asm-mips/mach-rm200/cpu-feature-overrides.h	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/include/asm-mips/mach-rm200/cpu-feature-overrides.h	2006-06-19 18:16:14.000000000 -0700
-@@ -35,10 +35,8 @@
- #define cpu_has_nofpuex		0
- #define cpu_has_64bits		1
- 
--#define cpu_has_subset_pcaches	0	/* No S-cache on R5000 I think ...  */
- #define cpu_dcache_line_size()	32
- #define cpu_icache_line_size()	32
--#define cpu_scache_line_size()	0	/* No S-cache on R5000 I think ...  */
- 
- #define cpu_has_mips32r1	0
- #define cpu_has_mips32r2	0
-diff -Naur linux-2.6.17.orig/include/asm-mips/mach-vr41xx/timex.h linux-2.6.17/include/asm-mips/mach-vr41xx/timex.h
---- linux-2.6.17.orig/include/asm-mips/mach-vr41xx/timex.h	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/include/asm-mips/mach-vr41xx/timex.h	2006-06-19 18:16:14.000000000 -0700
-@@ -0,0 +1,18 @@
-+/*
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License.  See the file "COPYING" in the main directory of this archive
-+ * for more details.
-+ *
-+ * Copyright (C) 2003 by Ralf Baechle
-+ */
-+/*
-+ * Changes:
-+ *  Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
-+ *  - CLOCK_TICK_RATE is changed into 32768 from 6144000.
-+ */
-+#ifndef __ASM_MACH_VR41XX_TIMEX_H
-+#define __ASM_MACH_VR41XX_TIMEX_H
-+
-+#define CLOCK_TICK_RATE		32768
-+
-+#endif /* __ASM_MACH_VR41XX_TIMEX_H */
-diff -Naur linux-2.6.17.orig/include/asm-mips/mach-wrppmc/mach-gt64120.h linux-2.6.17/include/asm-mips/mach-wrppmc/mach-gt64120.h
---- linux-2.6.17.orig/include/asm-mips/mach-wrppmc/mach-gt64120.h	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/include/asm-mips/mach-wrppmc/mach-gt64120.h	2006-06-19 18:16:14.000000000 -0700
-@@ -0,0 +1,84 @@
-+/*
-+ * This is a direct copy of the ev96100.h file, with a global
-+ * search and replace.  The numbers are the same.
-+ *
-+ * The reason I'm duplicating this is so that the 64120/96100
-+ * defines won't be confusing in the source code.
-+ */
-+#ifndef __ASM_MIPS_GT64120_H
-+#define __ASM_MIPS_GT64120_H
-+
-+/*
-+ * This is the CPU physical memory map of PPMC Board:
-+ *
-+ *    0x00000000-0x03FFFFFF      - 64MB SDRAM (SCS[0]#)
-+ *    0x1C000000-0x1C000000      - LED (CS0)
-+ *    0x1C800000-0x1C800007      - UART 16550 port (CS1)
-+ *    0x1F000000-0x1F000000      - MailBox (CS3)
-+ *    0x1FC00000-0x20000000      - 4MB Flash (BOOT CS)
-+ */
-+
-+#define WRPPMC_SDRAM_SCS0_BASE	0x00000000
-+#define WRPPMC_SDRAM_SCS0_SIZE	0x04000000
-+
-+#define WRPPMC_UART16550_BASE	0x1C800000
-+#define WRPPMC_UART16550_CLOCK	3686400 /* 3.68MHZ */
-+
-+#define WRPPMC_LED_BASE		0x1C000000
-+#define WRPPMC_MBOX_BASE	0x1F000000
-+
-+#define WRPPMC_BOOTROM_BASE	0x1FC00000
-+#define WRPPMC_BOOTROM_SIZE	0x00400000 /* 4M Flash */
-+
-+#define WRPPMC_MIPS_TIMER_IRQ	7 /* MIPS compare/count timer interrupt */
-+#define WRPPMC_UART16550_IRQ	6
-+#define WRPPMC_PCI_INTA_IRQ	3
-+
-+/*
-+ * PCI Bus I/O and Memory resources allocation
-+ *
-+ * NOTE: We only have PCI_0 hose interface
-+ */
-+#define GT_PCI_MEM_BASE	0x13000000UL
-+#define GT_PCI_MEM_SIZE	0x02000000UL
-+#define GT_PCI_IO_BASE	0x11000000UL
-+#define GT_PCI_IO_SIZE	0x02000000UL
-+#define GT_ISA_IO_BASE	PCI_IO_BASE
-+
-+/*
-+ * PCI interrupts will come in on either the INTA or INTD interrups lines,
-+ * which are mapped to the #2 and #5 interrupt pins of the MIPS.  On our
-+ * boards, they all either come in on IntD or they all come in on IntA, they
-+ * aren't mixed. There can be numerous PCI interrupts, so we keep a list of the
-+ * "requested" interrupt numbers and go through the list whenever we get an
-+ * IntA/D.
-+ *
-+ * Interrupts < 8 are directly wired to the processor; PCI INTA is 8 and
-+ * INTD is 11.
-+ */
-+#define GT_TIMER	4
-+#define GT_INTA		2
-+#define GT_INTD		5
-+
-+#ifndef __ASSEMBLY__
-+
-+/*
-+ * GT64120 internal register space base address
-+ */
-+extern unsigned long gt64120_base;
-+
-+#define GT64120_BASE	(gt64120_base)
-+
-+/* define WRPPMC_EARLY_DEBUG to enable early output something to UART */
-+#undef WRPPMC_EARLY_DEBUG
-+
-+#ifdef WRPPMC_EARLY_DEBUG
-+extern void wrppmc_led_on(int mask);
-+extern void wrppmc_led_off(int mask);
-+extern void wrppmc_early_printk(const char *fmt, ...);
-+#else
-+#define wrppmc_early_printk(fmt, ...) do {} while (0)
-+#endif /* WRPPMC_EARLY_DEBUG */
-+
-+#endif /* __ASSEMBLY__ */
-+#endif /* __ASM_MIPS_GT64120_H */
-diff -Naur linux-2.6.17.orig/include/asm-mips/mipsregs.h linux-2.6.17/include/asm-mips/mipsregs.h
---- linux-2.6.17.orig/include/asm-mips/mipsregs.h	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/include/asm-mips/mipsregs.h	2006-06-19 18:16:14.000000000 -0700
-@@ -1451,18 +1451,17 @@
- {
- 	if ((previous & __EMT_ENABLE))
- 		__asm__ __volatile__(
--		"	.set	noreorder				\n"
- 		"	.set	mips32r2				\n"
- 		"	.word	0x41600be1		# emt		\n"
- 		"	ehb						\n"
--		"	.set	mips0					\n"
--		"	.set	reorder					\n");
-+		"	.set	mips0					\n");
- }
- 
- static inline void __ehb(void)
- {
- 	__asm__ __volatile__(
--	"	ehb							\n");
-+	"	.set	mips32r2					\n"
-+	"	ehb							\n"		"	.set	mips0						\n");
- }
- 
- /*
-diff -Naur linux-2.6.17.orig/include/asm-mips/mmzone.h linux-2.6.17/include/asm-mips/mmzone.h
---- linux-2.6.17.orig/include/asm-mips/mmzone.h	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/include/asm-mips/mmzone.h	2006-06-19 18:16:14.000000000 -0700
-@@ -14,17 +14,6 @@
- #define kvaddr_to_nid(kvaddr)	pa_to_nid(__pa(kvaddr))
- #define pfn_to_nid(pfn)		pa_to_nid((pfn) << PAGE_SHIFT)
- 
--#define pfn_valid(pfn)						\
--({								\
-- 	unsigned long __pfn = (pfn);				\
-- 	int __n = pfn_to_nid(__pfn);				\
--	((__n >= 0) ? (__pfn < NODE_DATA(__n)->node_start_pfn +	\
--		       NODE_DATA(__n)->node_spanned_pages) : 0);\
--})
--
--/* XXX: FIXME -- wli */
--#define kern_addr_valid(addr)	(0)
--
- #endif /* CONFIG_DISCONTIGMEM */
- 
- #endif /* _ASM_MMZONE_H_ */
-diff -Naur linux-2.6.17.orig/include/asm-mips/page.h linux-2.6.17/include/asm-mips/page.h
---- linux-2.6.17.orig/include/asm-mips/page.h	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/include/asm-mips/page.h	2006-06-19 18:16:14.000000000 -0700
-@@ -145,6 +145,25 @@
- #endif
- #endif
- 
-+#ifdef CONFIG_FLATMEM
-+
-+#define pfn_valid(pfn)		((pfn) < max_mapnr)
-+
-+#elif defined(CONFIG_NEED_MULTIPLE_NODES)
-+
-+#define pfn_valid(pfn)							\
-+({									\
-+	unsigned long __pfn = (pfn);					\
-+	int __n = pfn_to_nid(__pfn);					\
-+	((__n >= 0) ? (__pfn < NODE_DATA(__n)->node_start_pfn +		\
-+	                       NODE_DATA(__n)->node_spanned_pages)	\
-+	            : 0);						\
-+})
-+
-+#else
-+#error Provide a definition of pfn_valid
-+#endif
-+
- #define virt_to_page(kaddr)	pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
- #define virt_addr_valid(kaddr)	pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
- 
-diff -Naur linux-2.6.17.orig/include/asm-mips/pci/bridge.h linux-2.6.17/include/asm-mips/pci/bridge.h
---- linux-2.6.17.orig/include/asm-mips/pci/bridge.h	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/include/asm-mips/pci/bridge.h	2006-06-19 18:16:14.000000000 -0700
-@@ -15,6 +15,7 @@
- #include <linux/types.h>
- #include <linux/pci.h>
- #include <asm/xtalk/xwidget.h>		/* generic widget header */
-+#include <asm/sn/types.h>
- 
- /* I/O page size */
- 
-@@ -848,4 +849,6 @@
- extern void register_bridge_irq(unsigned int irq);
- extern int request_bridge_irq(struct bridge_controller *bc);
- 
-+extern struct pci_ops bridge_pci_ops;
-+
- #endif /* _ASM_PCI_BRIDGE_H */
-diff -Naur linux-2.6.17.orig/include/asm-mips/pgtable.h linux-2.6.17/include/asm-mips/pgtable.h
---- linux-2.6.17.orig/include/asm-mips/pgtable.h	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/include/asm-mips/pgtable.h	2006-06-19 18:16:14.000000000 -0700
-@@ -379,9 +379,7 @@
- 	__update_cache(vma, address, pte);
- }
- 
--#ifndef CONFIG_NEED_MULTIPLE_NODES
- #define kern_addr_valid(addr)	(1)
--#endif
- 
- #ifdef CONFIG_64BIT_PHYS_ADDR
- extern int remap_pfn_range(struct vm_area_struct *vma, unsigned long from, unsigned long pfn, unsigned long size, pgprot_t prot);
-diff -Naur linux-2.6.17.orig/include/asm-mips/processor.h linux-2.6.17/include/asm-mips/processor.h
---- linux-2.6.17.orig/include/asm-mips/processor.h	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/include/asm-mips/processor.h	2006-06-19 18:16:14.000000000 -0700
-@@ -71,11 +71,6 @@
- 
- typedef __u64 fpureg_t;
- 
--struct mips_fpu_hard_struct {
--	fpureg_t	fpr[NUM_FPU_REGS];
--	unsigned int	fcr31;
--};
--
- /*
-  * It would be nice to add some more fields for emulator statistics, but there
-  * are a number of fixed offsets in offset.h and elsewhere that would have to
-@@ -83,18 +78,13 @@
-  * the FPU emulator for now.  See asm-mips/fpu_emulator.h.
-  */
- 
--struct mips_fpu_soft_struct {
-+struct mips_fpu_struct {
- 	fpureg_t	fpr[NUM_FPU_REGS];
- 	unsigned int	fcr31;
- };
- 
--union mips_fpu_union {
--        struct mips_fpu_hard_struct hard;
--        struct mips_fpu_soft_struct soft;
--};
--
- #define INIT_FPU { \
--	{{0,},} \
-+	{0,} \
- }
- 
- #define NUM_DSP_REGS   6
-@@ -133,7 +123,7 @@
- 	unsigned long cp0_status;
- 
- 	/* Saved fpu/fpu emulator stuff. */
--	union mips_fpu_union fpu;
-+	struct mips_fpu_struct fpu;
- #ifdef CONFIG_MIPS_MT_FPAFF
- 	/* Emulated instruction count */
- 	unsigned long emulated_fp;
-diff -Naur linux-2.6.17.orig/include/asm-mips/qemu.h linux-2.6.17/include/asm-mips/qemu.h
---- linux-2.6.17.orig/include/asm-mips/qemu.h	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/include/asm-mips/qemu.h	2006-06-19 18:16:14.000000000 -0700
-@@ -21,4 +21,10 @@
-  */
- #define QEMU_C0_COUNTER_CLOCK	100000000
- 
-+/*
-+ * Magic qemu system control location.
-+ */
-+#define QEMU_RESTART_REG	0xBFBF0000
-+#define QEMU_HALT_REG		0xBFBF0004
-+
- #endif /* __ASM_QEMU_H */
-diff -Naur linux-2.6.17.orig/include/asm-mips/rm9k-ocd.h linux-2.6.17/include/asm-mips/rm9k-ocd.h
---- linux-2.6.17.orig/include/asm-mips/rm9k-ocd.h	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/include/asm-mips/rm9k-ocd.h	2006-06-19 18:16:14.000000000 -0700
-@@ -0,0 +1,56 @@
-+/*
-+ *  Copyright (C) 2004 by Basler Vision Technologies AG
-+ *  Author: Thomas Koeller <thomas.koeller@baslerweb.com>
-+ *
-+ *  This program is free software; you can redistribute it and/or modify
-+ *  it under the terms of the GNU General Public License as published by
-+ *  the Free Software Foundation; either version 2 of the License, or
-+ *  (at your option) any later version.
-+ *
-+ *  This program is distributed in the hope that it will be useful,
-+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ *  GNU General Public License for more details.
-+ *
-+ *  You should have received a copy of the GNU General Public License
-+ *  along with this program; if not, write to the Free Software
-+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-+ */
-+
-+#if !defined(_ASM_RM9K_OCD_H)
-+#define _ASM_RM9K_OCD_H
-+
-+#include <linux/types.h>
-+#include <linux/spinlock.h>
-+#include <asm/io.h>
-+
-+extern volatile void __iomem * const ocd_base;
-+extern volatile void __iomem * const titan_base;
-+
-+#define ocd_addr(__x__)		(ocd_base + (__x__))
-+#define titan_addr(__x__)	(titan_base + (__x__))
-+#define scram_addr(__x__)	(scram_base + (__x__))
-+
-+/* OCD register access */
-+#define ocd_readl(__offs__) __raw_readl(ocd_addr(__offs__))
-+#define ocd_readw(__offs__) __raw_readw(ocd_addr(__offs__))
-+#define ocd_readb(__offs__) __raw_readb(ocd_addr(__offs__))
-+#define ocd_writel(__val__, __offs__) \
-+	__raw_writel((__val__), ocd_addr(__offs__))
-+#define ocd_writew(__val__, __offs__) \
-+	__raw_writew((__val__), ocd_addr(__offs__))
-+#define ocd_writeb(__val__, __offs__) \
-+	__raw_writeb((__val__), ocd_addr(__offs__))
-+
-+/* TITAN register access - 32 bit-wide only */
-+#define titan_readl(__offs__) __raw_readl(titan_addr(__offs__))
-+#define titan_writel(__val__, __offs__) \
-+	__raw_writel((__val__), titan_addr(__offs__))
-+
-+/* Protect access to shared TITAN registers */
-+extern spinlock_t titan_lock;
-+extern int titan_irqflags;
-+#define lock_titan_regs() spin_lock_irqsave(&titan_lock, titan_irqflags)
-+#define unlock_titan_regs() spin_unlock_irqrestore(&titan_lock, titan_irqflags)
-+
-+#endif	/* !defined(_ASM_RM9K_OCD_H) */
-diff -Naur linux-2.6.17.orig/include/asm-mips/sn/addrs.h linux-2.6.17/include/asm-mips/sn/addrs.h
---- linux-2.6.17.orig/include/asm-mips/sn/addrs.h	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/include/asm-mips/sn/addrs.h	2006-06-19 18:16:14.000000000 -0700
-@@ -27,13 +27,8 @@
- 
- #ifndef __ASSEMBLY__
- 
--#if defined(CONFIG_SGI_IO)	/* FIXME */
--#define PS_UINT_CAST		(__psunsigned_t)
--#define UINT64_CAST		(__uint64_t)
--#else	/* CONFIG_SGI_IO */
- #define PS_UINT_CAST		(unsigned long)
- #define UINT64_CAST		(unsigned long)
--#endif	/* CONFIG_SGI_IO */
- 
- #define HUBREG_CAST		(volatile hubreg_t *)
- 
-@@ -253,14 +248,6 @@
-  * for _x.
-  */
- 
--#ifdef _STANDALONE
--
--/* DO NOT USE THESE DIRECTLY IN THE KERNEL. SEE BELOW. */
--#define LOCAL_HUB(_x)		(HUBREG_CAST (IALIAS_BASE + (_x)))
--#define REMOTE_HUB(_n, _x)	(HUBREG_CAST (NODE_SWIN_BASE(_n, 1) +	\
--					      0x800000 + (_x)))
--#endif /* _STANDALONE */
--
- /*
-  * WARNING:
-  *	When certain Hub chip workaround are defined, it's not sufficient
-@@ -327,20 +314,6 @@
- 	PHYS_TO_K0(NODE_OFFSET(nasid) | ARCS_SPB_OFFSET)
- #define ARCS_SPB_SIZE		0x0400
- 
--#ifdef _STANDALONE
--
--#define ARCS_TVECTOR_OFFSET	0x2800
--#define ARCS_PVECTOR_OFFSET	0x2c00
--
--/*
-- * These addresses are used by the master CPU to install the transfer
-- * and private vectors.  All others use the SPB to find them.
-- */
--#define TVADDR	(NODE_CAC_BASE(get_nasid()) + ARCS_TVECTOR_OFFSET)
--#define PVADDR	(NODE_CAC_BASE(get_nasid()) + ARCS_PVECTOR_OFFSET)
--
--#endif /* _STANDALONE */
--
- #define KLDIR_OFFSET		0x2000
- #define KLDIR_ADDR(nasid)						\
- 	TO_NODE_UNCAC((nasid), KLDIR_OFFSET)
-diff -Naur linux-2.6.17.orig/include/asm-mips/sn/fru.h linux-2.6.17/include/asm-mips/sn/fru.h
---- linux-2.6.17.orig/include/asm-mips/sn/fru.h	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/include/asm-mips/sn/fru.h	2006-06-19 18:16:14.000000000 -0700
-@@ -0,0 +1,44 @@
-+/*
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License.  See the file "COPYING" in the main directory of this archive
-+ * for more details.
-+ *
-+ * Derived from IRIX <sys/SN/SN0/sn0_fru.h>
-+ *
-+ * Copyright (C) 1992 - 1997, 1999 Silcon Graphics, Inc.
-+ * Copyright (C) 1999, 2006 Ralf Baechle (ralf@linux-mips)
-+ */
-+#ifndef __ASM_SN_FRU_H
-+#define __ASM_SN_FRU_H
-+
-+#define MAX_DIMMS			8	 /* max # of dimm banks */
-+#define MAX_PCIDEV			8	 /* max # of pci devices on a pci bus */
-+
-+typedef unsigned char confidence_t;
-+
-+typedef struct kf_mem_s {
-+	confidence_t km_confidence; /* confidence level that the memory is bad
-+				     * is this necessary ?
-+				     */
-+	confidence_t km_dimm[MAX_DIMMS];
-+	                            /* confidence level that dimm[i] is bad
-+				     *I think this is the right number
-+				     */
-+
-+} kf_mem_t;
-+
-+typedef struct kf_cpu_s {
-+	confidence_t  	kc_confidence; /* confidence level that cpu is bad */
-+	confidence_t  	kc_icache; /* confidence level that instr. cache is bad */
-+	confidence_t  	kc_dcache; /* confidence level that data   cache is bad */
-+	confidence_t  	kc_scache; /* confidence level that sec.   cache is bad */
-+	confidence_t	kc_sysbus; /* confidence level that sysad/cmd/state bus is bad */
-+} kf_cpu_t;
-+
-+typedef struct kf_pci_bus_s {
-+	confidence_t	kpb_belief;	/* confidence level  that the  pci bus is bad */
-+	confidence_t	kpb_pcidev_belief[MAX_PCIDEV];
-+	                                /* confidence level that the pci dev is bad */
-+} kf_pci_bus_t;
-+
-+#endif /* __ASM_SN_FRU_H */
-diff -Naur linux-2.6.17.orig/include/asm-mips/sn/klconfig.h linux-2.6.17/include/asm-mips/sn/klconfig.h
---- linux-2.6.17.orig/include/asm-mips/sn/klconfig.h	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/include/asm-mips/sn/klconfig.h	2006-06-19 18:16:14.000000000 -0700
-@@ -37,7 +37,7 @@
- //#include <sys/SN/router.h>
- // XXX Stolen from <sys/SN/router.h>:
- #define MAX_ROUTER_PORTS (6)    /* Max. number of ports on a router */
--#include <asm/sn/sn0/sn0_fru.h>
-+#include <asm/sn/fru.h>
- //#include <sys/graph.h>
- //#include <sys/xtalk/xbow.h>
- 
-@@ -54,32 +54,21 @@
- #include <asm/sn/agent.h>
- #include <asm/arc/types.h>
- #include <asm/arc/hinv.h>
--#if defined(CONFIG_SGI_IO) || defined(CONFIG_SGI_IP35)
-+#if defined(CONFIG_SGI_IP35)
- // The hack file has to be before vector and after sn0_fru....
- #include <asm/hack.h>
- #include <asm/sn/vector.h>
- #include <asm/xtalk/xtalk.h>
--#endif /* CONFIG_SGI_IO || CONFIG_SGI_IP35 */
-+#endif /* CONFIG_SGI_IP35 */
- #endif /* CONFIG_SGI_IP27 || CONFIG_SGI_IP35 */
- 
- #define KLCFGINFO_MAGIC	0xbeedbabe
- 
--#ifdef FRUTEST
--typedef u64 klconf_off_t;
--#else
- typedef s32 klconf_off_t;
--#endif
- 
- /*
-  * Some IMPORTANT OFFSETS. These are the offsets on all NODES.
-  */
--#if 0
--#define RAMBASE                 0
--#define ARCSSPB_OFF             0x1000 /* shift it to sys/arcs/spb.h */
--
--#define OFF_HWGRAPH 		0
--#endif
--
- #define	MAX_MODULE_ID		255
- #define SIZE_PAD		4096 /* 4k padding for structures */
- /*
-@@ -134,15 +123,9 @@
- 
- 
- typedef struct console_s {
--#if defined(CONFIG_SGI_IO)	/* FIXME */
--	__psunsigned_t 	uart_base;
--	__psunsigned_t 	config_base;
--	__psunsigned_t 	memory_base;
--#else
- 	unsigned long 	uart_base;
- 	unsigned long 	config_base;
- 	unsigned long 	memory_base;
--#endif
- 	short		baud;
- 	short		flag;
- 	int		type;
-@@ -174,10 +157,6 @@
- 
- 
- #define KL_CONFIG_HDR(_nasid) 	((kl_config_hdr_t *)(KLCONFIG_ADDR(_nasid)))
--#if 0
--#define KL_CONFIG_MALLOC_HDR(_nasid) \
--                                (KL_CONFIG_HDR(_nasid)->ch_malloc_hdr)
--#endif
- #define KL_CONFIG_INFO_OFFSET(_nasid)					\
-         (KL_CONFIG_HDR(_nasid)->ch_board_info)
- #define KL_CONFIG_INFO_SET_OFFSET(_nasid, _off)				\
-@@ -197,23 +176,13 @@
- 
- /* --- New Macros for the changed kl_config_hdr_t structure --- */
- 
--#if defined(CONFIG_SGI_IO)
--#define PTR_CH_MALLOC_HDR(_k)   ((klc_malloc_hdr_t *)\
--			((__psunsigned_t)_k + (_k->ch_malloc_hdr_off)))
--#else
- #define PTR_CH_MALLOC_HDR(_k)   ((klc_malloc_hdr_t *)\
- 			(unsigned long)_k + (_k->ch_malloc_hdr_off)))
--#endif
- 
- #define KL_CONFIG_CH_MALLOC_HDR(_n)   PTR_CH_MALLOC_HDR(KL_CONFIG_HDR(_n))
- 
--#if defined(CONFIG_SGI_IO)
--#define PTR_CH_CONS_INFO(_k)	((console_t *)\
--			((__psunsigned_t)_k + (_k->ch_cons_off)))
--#else
- #define PTR_CH_CONS_INFO(_k)	((console_t *)\
- 			((unsigned long)_k + (_k->ch_cons_off)))
--#endif
- 
- #define KL_CONFIG_CH_CONS_INFO(_n)   PTR_CH_CONS_INFO(KL_CONFIG_HDR(_n))
- 
-@@ -490,14 +459,6 @@
- #define KLCF_NUM_COMPS(_brd)	((_brd)->brd_numcompts)
- #define KLCF_MODULE_ID(_brd)	((_brd)->brd_module)
- 
--#ifdef FRUTEST
--
--#define KLCF_NEXT(_brd) 		((_brd)->brd_next ? (lboard_t *)((_brd)->brd_next):  NULL)
--#define KLCF_COMP(_brd, _ndx)   	(klinfo_t *)((_brd)->brd_compts[(_ndx)])
--#define KLCF_COMP_ERROR(_brd, _comp)   	(_brd = _brd , (_comp)->errinfo)
--
--#else
--
- #define KLCF_NEXT(_brd) 	\
-         ((_brd)->brd_next ? 	\
- 	 (lboard_t *)(NODE_OFFSET_TO_K1(NASID_GET(_brd), (_brd)->brd_next)):\
-@@ -509,8 +470,6 @@
- #define KLCF_COMP_ERROR(_brd, _comp)	\
-                (NODE_OFFSET_TO_K1(NASID_GET(_brd), (_comp)->errinfo))
- 
--#endif
--
- #define KLCF_COMP_TYPE(_comp)	((_comp)->struct_type)
- #define KLCF_BRIDGE_W_ID(_comp)	((_comp)->physid)	/* Widget ID */
- 
-@@ -631,18 +590,6 @@
- 	klconf_off_t	port_offset;
- } klport_t;
- 
--#if 0
--/*
-- * This is very similar to the klport_s but instead of having a componant
-- * offset it has a board offset.
-- */
--typedef struct klxbow_port_s {
--	nasid_t		port_nasid;
--	unsigned char	port_flag;
--	klconf_off_t	board_offset;
--} klxbow_port_t;
--#endif
--
- typedef struct klcpu_s {                          /* CPU */
- 	klinfo_t 	cpu_info;
- 	unsigned short 	cpu_prid;	/* Processor PRID value */
-@@ -945,36 +892,6 @@
- extern lboard_t *find_lboard_class(lboard_t *start, unsigned char brd_class);
- 
- 
--#if defined(CONFIG_SGI_IO)
--extern xwidgetnum_t nodevertex_widgetnum_get(vertex_hdl_t node_vtx);
--extern vertex_hdl_t nodevertex_xbow_peer_get(vertex_hdl_t node_vtx);
--extern lboard_t *find_gfxpipe(int pipenum);
--extern void setup_gfxpipe_link(vertex_hdl_t vhdl,int pipenum);
--extern lboard_t *find_lboard_module_class(lboard_t *start, moduleid_t mod,
--                                               unsigned char brd_class);
--extern lboard_t *find_nic_lboard(lboard_t *, nic_t);
--extern lboard_t *find_nic_type_lboard(nasid_t, unsigned char, nic_t);
--extern lboard_t *find_lboard_modslot(lboard_t *start, moduleid_t mod, slotid_t slot);
--extern lboard_t *find_lboard_module(lboard_t *start, moduleid_t mod);
--extern lboard_t *get_board_name(nasid_t nasid, moduleid_t mod, slotid_t slot, char *name);
--extern int	config_find_nic_router(nasid_t, nic_t, lboard_t **, klrou_t**);
--extern int	config_find_nic_hub(nasid_t, nic_t, lboard_t **, klhub_t**);
--extern int	config_find_xbow(nasid_t, lboard_t **, klxbow_t**);
--extern klcpu_t *get_cpuinfo(cpuid_t cpu);
--extern int 	update_klcfg_cpuinfo(nasid_t, int);
--extern void 	board_to_path(lboard_t *brd, char *path);
--extern moduleid_t get_module_id(nasid_t nasid);
--extern void 	nic_name_convert(char *old_name, char *new_name);
--extern int 	module_brds(nasid_t nasid, lboard_t **module_brds, int n);
--extern lboard_t *brd_from_key(ulong_t key);
--extern void 	device_component_canonical_name_get(lboard_t *,klinfo_t *,
--						    char *);
--extern int	board_serial_number_get(lboard_t *,char *);
--extern int	is_master_baseio(nasid_t,moduleid_t,slotid_t);
--extern nasid_t	get_actual_nasid(lboard_t *brd) ;
--extern net_vec_t klcfg_discover_route(lboard_t *, lboard_t *, int);
--#else	/* CONFIG_SGI_IO */
- extern klcpu_t *sn_get_cpuinfo(cpuid_t cpu);
--#endif	/* CONFIG_SGI_IO */
- 
- #endif /* _ASM_SN_KLCONFIG_H */
-diff -Naur linux-2.6.17.orig/include/asm-mips/sn/kldir.h linux-2.6.17/include/asm-mips/sn/kldir.h
---- linux-2.6.17.orig/include/asm-mips/sn/kldir.h	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/include/asm-mips/sn/kldir.h	2006-06-19 18:16:14.000000000 -0700
-@@ -13,10 +13,6 @@
- 
- #include <linux/config.h>
- 
--#if defined(CONFIG_SGI_IO)
--#include <asm/hack.h>
--#endif
--
- /*
-  * The kldir memory area resides at a fixed place in each node's memory and
-  * provides pointers to most other IP27 memory areas.  This allows us to
-@@ -136,8 +132,6 @@
- #define KLDIR_OFF_STRIDE		0x28
- #endif /* __ASSEMBLY__ */
- 
--#if !defined(CONFIG_SGI_IO)
--
- /*
-  * This is defined here because IP27_SYMMON_STK_SIZE must be at least what
-  * we define here.  Since it's set up in the prom.  We can't redefine it later
-@@ -147,7 +141,7 @@
-  */
- #define SYMMON_STACK_SIZE		0x8000
- 
--#if defined (PROM) || defined (SABLE)
-+#if defined (PROM)
- 
- /*
-  * These defines are prom version dependent.  No code other than the IP27
-@@ -184,7 +178,7 @@
- #define IP27_FREEMEM_COUNT		1
- #define IP27_FREEMEM_STRIDE		0
- 
--#endif /* PROM || SABLE*/
-+#endif /* PROM */
- /*
-  * There will be only one of these in a partition so the IO6 must set it up.
-  */
-@@ -207,17 +201,11 @@
- #define KLDIR_ENT_SIZE			0x40
- #define KLDIR_MAX_ENTRIES		(0x400 / 0x40)
- 
--#endif	/* !CONFIG_SGI_IO */
--
- #ifndef __ASSEMBLY__
- typedef struct kldir_ent_s {
- 	u64		magic;		/* Indicates validity of entry      */
- 	off_t		offset;		/* Offset from start of node space  */
--#if defined(CONFIG_SGI_IO)	/* FIXME */
--	__psunsigned_t	pointer;	/* Pointer to area in some cases    */
--#else
- 	unsigned long	pointer;	/* Pointer to area in some cases    */
--#endif
- 	size_t		size;		/* Size in bytes 		    */
- 	u64		count;		/* Repeat count if array, 1 if not  */
- 	size_t		stride;		/* Stride if array, 0 if not        */
-@@ -227,22 +215,4 @@
- } kldir_ent_t;
- #endif /* !__ASSEMBLY__ */
- 
--#if defined(CONFIG_SGI_IO)
--
--#define KLDIR_ENT_SIZE			0x40
--#define KLDIR_MAX_ENTRIES		(0x400 / 0x40)
--
--/*
-- * The actual offsets of each memory area are machine-dependent
-- */
--#ifdef CONFIG_SGI_IP27
--// Not yet #include <asm/sn/sn0/kldir.h>
--#elif defined(CONFIG_SGI_IP35)
--#include <asm/sn/sn1/kldir.h>
--#else
--#error "kldir.h is currently defined for IP27 and IP35 platforms only"
--#endif
--
--#endif	/* CONFIG_SGI_IO */
--
- #endif /* _ASM_SN_KLDIR_H */
-diff -Naur linux-2.6.17.orig/include/asm-mips/sn/sn0/addrs.h linux-2.6.17/include/asm-mips/sn/sn0/addrs.h
---- linux-2.6.17.orig/include/asm-mips/sn/sn0/addrs.h	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/include/asm-mips/sn/sn0/addrs.h	2006-06-19 18:16:14.000000000 -0700
-@@ -49,7 +49,7 @@
-  * so for now we just use defines bracketed by an ifdef.
-  */
- 
--#ifdef CONFIG_SGI_SN0_N_MODE
-+#ifdef CONFIG_SGI_SN_N_MODE
- 
- #define NODE_SIZE_BITS		31
- #define BWIN_SIZE_BITS		28
-@@ -63,7 +63,7 @@
- #define BDDIR_UPPER_MASK	(UINT64_CAST 0x7ffff << 10)
- #define BDECC_UPPER_MASK	(UINT64_CAST 0x3ffffff << 3)
- 
--#else /* !defined(CONFIG_SGI_SN0_N_MODE), assume that M-mode is desired */
-+#else /* !defined(CONFIG_SGI_SN_N_MODE), assume that M-mode is desired */
- 
- #define NODE_SIZE_BITS		32
- #define BWIN_SIZE_BITS		29
-@@ -77,7 +77,7 @@
- #define BDDIR_UPPER_MASK	(UINT64_CAST 0xfffff << 10)
- #define BDECC_UPPER_MASK	(UINT64_CAST 0x7ffffff << 3)
- 
--#endif /* !defined(CONFIG_SGI_SN0_N_MODE) */
-+#endif /* !defined(CONFIG_SGI_SN_N_MODE) */
- 
- #define NODE_ADDRSPACE_SIZE	(UINT64_CAST 1 << NODE_SIZE_BITS)
- 
-@@ -85,15 +85,15 @@
- #define NASID_GET(_pa)		(int) ((UINT64_CAST (_pa) >>		\
- 					NASID_SHFT) & NASID_BITMASK)
- 
--#if !defined(__ASSEMBLY__) && !defined(_STANDALONE)
-+#if !defined(__ASSEMBLY__)
- 
- #define NODE_SWIN_BASE(nasid, widget)					\
- 	((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN)		\
- 	: RAW_NODE_SWIN_BASE(nasid, widget))
--#else /* __ASSEMBLY__ || _STANDALONE */
-+#else /* __ASSEMBLY__ */
- #define NODE_SWIN_BASE(nasid, widget) \
-      (NODE_IO_BASE(nasid) + (UINT64_CAST (widget) << SWIN_SIZE_BITS))
--#endif /* __ASSEMBLY__ || _STANDALONE */
-+#endif /* __ASSEMBLY__ */
- 
- /*
-  * The following definitions pertain to the IO special address
-@@ -143,12 +143,7 @@
- #define SN0_WIDGET_BASE(_nasid, _wid)	(NODE_SWIN_BASE((_nasid), (_wid)))
- 
- /* Turn on sable logging for the processors whose bits are set. */
--#ifdef SABLE
--#define SABLE_LOG_TRIGGER(_map)	\
--		*((volatile hubreg_t *)(IO_BASE + 0x17ffff0)) = (_map)
--#else
- #define SABLE_LOG_TRIGGER(_map)
--#endif /* SABLE */
- 
- #ifndef __ASSEMBLY__
- #define KERN_NMI_ADDR(nasid, slice)					\
-@@ -281,76 +276,6 @@
- 
- #define _ARCSPROM
- 
--#ifdef _STANDALONE
--
--/*
-- * The PROM needs to pass the device base address and the
-- * device pci cfg space address to the device drivers during
-- * install. The COMPONENT->Key field is used for this purpose.
-- * Macros needed by SN0 device drivers to convert the
-- * COMPONENT->Key field to the respective base address.
-- * Key field looks as follows:
-- *
-- *  +----------------------------------------------------+
-- *  |devnasid | widget  |pciid |hubwidid|hstnasid | adap |
-- *  |   2     |   1     |  1   |   1    |    2    |   1  |
-- *  +----------------------------------------------------+
-- *  |         |         |      |        |         |      |
-- *  64        48        40     32       24        8      0
-- *
-- * These are used by standalone drivers till the io infrastructure
-- * is in place.
-- */
--
--#ifndef __ASSEMBLY__
--
--#define uchar unsigned char
--
--#define KEY_DEVNASID_SHFT  48
--#define KEY_WIDID_SHFT	   40
--#define KEY_PCIID_SHFT	   32
--#define KEY_HUBWID_SHFT	   24
--#define KEY_HSTNASID_SHFT  8
--
--#define MK_SN0_KEY(nasid, widid, pciid) \
--			((((__psunsigned_t)nasid)<< KEY_DEVNASID_SHFT |\
--				((__psunsigned_t)widid) << KEY_WIDID_SHFT) |\
--				((__psunsigned_t)pciid) << KEY_PCIID_SHFT)
--
--#define ADD_HUBWID_KEY(key,hubwid)\
--			(key|=((__psunsigned_t)hubwid << KEY_HUBWID_SHFT))
--
--#define ADD_HSTNASID_KEY(key,hstnasid)\
--			(key|=((__psunsigned_t)hstnasid << KEY_HSTNASID_SHFT))
--
--#define GET_DEVNASID_FROM_KEY(key)	((short)(key >> KEY_DEVNASID_SHFT))
--#define GET_WIDID_FROM_KEY(key)		((uchar)(key >> KEY_WIDID_SHFT))
--#define GET_PCIID_FROM_KEY(key)		((uchar)(key >> KEY_PCIID_SHFT))
--#define GET_HUBWID_FROM_KEY(key)	((uchar)(key >> KEY_HUBWID_SHFT))
--#define GET_HSTNASID_FROM_KEY(key)	((short)(key >> KEY_HSTNASID_SHFT))
--
--#define PCI_64_TARGID_SHFT		60
--
--#define GET_PCIBASE_FROM_KEY(key)  (NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\
--					GET_WIDID_FROM_KEY(key))\
--					| BRIDGE_DEVIO(GET_PCIID_FROM_KEY(key)))
--
--#define GET_PCICFGBASE_FROM_KEY(key) \
--			(NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\
--			      GET_WIDID_FROM_KEY(key))\
--			| BRIDGE_TYPE0_CFG_DEV(GET_PCIID_FROM_KEY(key)))
--
--#define GET_WIDBASE_FROM_KEY(key) \
--                        (NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\
--                              GET_WIDID_FROM_KEY(key)))
--
--#define PUT_INSTALL_STATUS(c,s)		c->Revision = s
--#define GET_INSTALL_STATUS(c)		c->Revision
--
--#endif /* !__ASSEMBLY__ */
--
--#endif /* _STANDALONE */
--
- #if defined (HUB_ERR_STS_WAR)
- 
- #define ERR_STS_WAR_REGISTER	IIO_IIBUSERR
-diff -Naur linux-2.6.17.orig/include/asm-mips/sn/sn0/arch.h linux-2.6.17/include/asm-mips/sn/sn0/arch.h
---- linux-2.6.17.orig/include/asm-mips/sn/sn0/arch.h	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/include/asm-mips/sn/sn0/arch.h	2006-06-19 18:16:14.000000000 -0700
-@@ -13,8 +13,6 @@
- 
- #include <linux/config.h>
- 
--#ifndef SABLE
--
- #ifndef SN0XXL  /* 128 cpu SMP max */
- /*
-  * This is the maximum number of nodes that can be part of a kernel.
-@@ -54,25 +52,16 @@
-  */
- #define MAX_PARTITIONS		MAX_REGIONS
- 
--
--#else
--
--#define MAX_COMPACT_NODES	4
--#define MAX_NASIDS		4
--#define MAXCPUS			8
--
--#endif
--
- #define NASID_MASK_BYTES	((MAX_NASIDS + 7) / 8)
- 
- /*
-  * Slot constants for SN0
-  */
--#ifdef CONFIG_SGI_SN0_N_MODE
-+#ifdef CONFIG_SGI_SN_N_MODE
- #define MAX_MEM_SLOTS   16                      /* max slots per node */
--#else /* !CONFIG_SGI_SN0_N_MODE, assume M_MODE */
-+#else /* !CONFIG_SGI_SN_N_MODE, assume CONFIG_SGI_SN_M_MODE */
- #define MAX_MEM_SLOTS   32                      /* max slots per node */
--#endif /* defined(N_MODE) */
-+#endif /* CONFIG_SGI_SN_M_MODE */
- 
- #define SLOT_SHIFT      	(27)
- #define SLOT_MIN_MEM_SIZE	(32*1024*1024)
-diff -Naur linux-2.6.17.orig/include/asm-mips/sn/sn0/hub.h linux-2.6.17/include/asm-mips/sn/sn0/hub.h
---- linux-2.6.17.orig/include/asm-mips/sn/sn0/hub.h	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/include/asm-mips/sn/sn0/hub.h	2006-06-19 18:16:14.000000000 -0700
-@@ -31,10 +31,6 @@
- #include <asm/sn/sn0/hubni.h>
- //#include <asm/sn/sn0/hubcore.h>
- 
--#ifdef SABLE
--#define IP27_NO_HUBUART_INT	1
--#endif
--
- /* Translation of uncached attributes */
- #define	UATTR_HSPEC	0
- #define	UATTR_IO	1
-diff -Naur linux-2.6.17.orig/include/asm-mips/sn/sn0/hubio.h linux-2.6.17/include/asm-mips/sn/sn0/hubio.h
---- linux-2.6.17.orig/include/asm-mips/sn/sn0/hubio.h	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/include/asm-mips/sn/sn0/hubio.h	2006-06-19 18:16:14.000000000 -0700
-@@ -486,22 +486,6 @@
- #define ICRBN_A_CERR_SHFT	54
- #define ICRBN_A_ERR_MASK	0x3ff
- 
--#if 0	/* Disabled, this causes namespace polution and break allmodconfig */
--/*
-- * Easy access macros.
-- */
--#define	a_error		icrba_fields_s.error
--#define	a_ecode		icrba_fields_s.ecode
--#define	a_lnetuce	icrba_fields_s.lnetuce
--#define	a_mark		icrba_fields_s.mark
--#define	a_xerr		icrba_fields_s.xerr
--#define	a_sidn		icrba_fields_s.sidn
--#define	a_tnum		icrba_fields_s.tnum
--#define	a_addr		icrba_fields_s.addr
--#define	a_valid		icrba_fields_s.valid
--#define	a_iow		icrba_fields_s.iow
--#endif
--
- #endif /* !__ASSEMBLY__ */
- 
- #define	IIO_ICRB_ADDR_SHFT	2	/* Shift to get proper address */
-diff -Naur linux-2.6.17.orig/include/asm-mips/sn/sn0/hubmd.h linux-2.6.17/include/asm-mips/sn/sn0/hubmd.h
---- linux-2.6.17.orig/include/asm-mips/sn/sn0/hubmd.h	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/include/asm-mips/sn/sn0/hubmd.h	2006-06-19 18:16:14.000000000 -0700
-@@ -92,7 +92,7 @@
- #define MD_UREG1_14		0x2200f0 /* uController/UART 1 register     */
- #define MD_UREG1_15		0x2200f8 /* uController/UART 1 register     */
- 
--#ifdef CONFIG_SGI_SN0_N_MODE
-+#ifdef CONFIG_SGI_SN_N_MODE
- #define MD_MEM_BANKS		4	 /* 4 banks of memory max in N mode */
- #else
- #define MD_MEM_BANKS		8	 /* 8 banks of memory max in M mode */
-diff -Naur linux-2.6.17.orig/include/asm-mips/sn/sn0/hubpi.h linux-2.6.17/include/asm-mips/sn/sn0/hubpi.h
---- linux-2.6.17.orig/include/asm-mips/sn/sn0/hubpi.h	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/include/asm-mips/sn/sn0/hubpi.h	2006-06-19 18:16:14.000000000 -0700
-@@ -398,24 +398,6 @@
- 
- /* PI_RT_FILTER_CTRL mask and shift definitions */
- 
--#if 0
--/*
-- * XXX - This register's definition has changed, but it's only implemented
-- * in Hub 2.
-- */
--#define PRFC_DROP_COUNT_SHFT	27
--#define PRFC_DROP_COUNT_MASK	(UINT64_CAST 0x3ff << 27)
--#define PRFC_DROP_CTR_SHFT	18
--#define PRFC_DROP_CTR_MASK	(UINT64_CAST 0x1ff << 18)
--#define PRFC_MASK_ENABLE_SHFT	10
--#define PRFC_MASK_ENABLE_MASK	(UINT64_CAST 0x7f << 10)
--#define PRFC_MASK_CTR_SHFT	2
--#define PRFC_MASK_CTR_MASK	(UINT64_CAST 0xff << 2)
--#define PRFC_OFFSET_SHFT	0
--#define PRFC_OFFSET_MASK	(UINT64_CAST 3)
--#endif /* 0 */
--
--
- /*
-  * Bits for NACK_CNT_A/B and NACK_CMP
-  */
-diff -Naur linux-2.6.17.orig/include/asm-mips/sn/sn0/ip27.h linux-2.6.17/include/asm-mips/sn/sn0/ip27.h
---- linux-2.6.17.orig/include/asm-mips/sn/sn0/ip27.h	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/include/asm-mips/sn/sn0/ip27.h	2006-06-19 18:16:14.000000000 -0700
-@@ -6,7 +6,7 @@
-  * Derived from IRIX <sys/SN/SN0/IP27.h>.
-  *
-  * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
-- * Copyright (C) 1999 by Ralf Baechle
-+ * Copyright (C) 1999, 2006 by Ralf Baechle
-  */
- #ifndef _ASM_SN_SN0_IP27_H
- #define _ASM_SN_SN0_IP27_H
-@@ -82,11 +82,4 @@
- #define SEND_NMI(_nasid, _slice)	\
-           REMOTE_HUB_S((_nasid),  (PI_NMI_A + ((_slice) * PI_NMI_OFFSET)), 1)
- 
--/* Sanity hazzard ...  Below all the Origin hacks are following.  */
--
--#define SN00_BRIDGE		0x9200000008000000
--#define SN00I_BRIDGE0		0x920000000b000000
--#define SN00I_BRIDGE1		0x920000000e000000
--#define SN00I_BRIDGE2		0x920000000f000000
--
- #endif /* _ASM_SN_SN0_IP27_H */
-diff -Naur linux-2.6.17.orig/include/asm-mips/sn/sn0/sn0_fru.h linux-2.6.17/include/asm-mips/sn/sn0/sn0_fru.h
---- linux-2.6.17.orig/include/asm-mips/sn/sn0/sn0_fru.h	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/include/asm-mips/sn/sn0/sn0_fru.h	1969-12-31 16:00:00.000000000 -0800
-@@ -1,44 +0,0 @@
--/*
-- * This file is subject to the terms and conditions of the GNU General Public
-- * License.  See the file "COPYING" in the main directory of this archive
-- * for more details.
-- *
-- * Derived from IRIX <sys/SN/SN0/sn0_fru.h>
-- *
-- * Copyright (C) 1992 - 1997, 1999 Silcon Graphics, Inc.
-- * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
-- */
--#ifndef _ASM_SN_SN0_SN0_FRU_H
--#define _ASM_SN_SN0_SN0_FRU_H
--
--#define MAX_DIMMS			8	 /* max # of dimm banks */
--#define MAX_PCIDEV			8	 /* max # of pci devices on a pci bus */
--
--typedef unsigned char confidence_t;
--
--typedef struct kf_mem_s {
--	confidence_t km_confidence; /* confidence level that the memory is bad
--				     * is this necessary ?
--				     */
--	confidence_t km_dimm[MAX_DIMMS];
--	                            /* confidence level that dimm[i] is bad
--				     *I think this is the right number
--				     */
--
--} kf_mem_t;
--
--typedef struct kf_cpu_s {
--	confidence_t  	kc_confidence; /* confidence level that cpu is bad */
--	confidence_t  	kc_icache; /* confidence level that instr. cache is bad */
--	confidence_t  	kc_dcache; /* confidence level that data   cache is bad */
--	confidence_t  	kc_scache; /* confidence level that sec.   cache is bad */
--	confidence_t	kc_sysbus; /* confidence level that sysad/cmd/state bus is bad */
--} kf_cpu_t;
--
--typedef struct kf_pci_bus_s {
--	confidence_t	kpb_belief;	/* confidence level  that the  pci bus is bad */
--	confidence_t	kpb_pcidev_belief[MAX_PCIDEV];
--	                                /* confidence level that the pci dev is bad */
--} kf_pci_bus_t;
--
--#endif /* _ASM_SN_SN0_SN0_FRU_H */
-diff -Naur linux-2.6.17.orig/include/asm-mips/sni.h linux-2.6.17/include/asm-mips/sni.h
---- linux-2.6.17.orig/include/asm-mips/sni.h	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/include/asm-mips/sni.h	2006-06-19 18:16:14.000000000 -0700
-@@ -15,9 +15,6 @@
- /*
-  * ASIC PCI registers for little endian configuration.
-  */
--#ifndef __MIPSEL__
--#error "Fix me for big endian"
--#endif
- #define PCIMT_UCONF		0xbfff0000
- #define PCIMT_IOADTIMEOUT2	0xbfff0008
- #define PCIMT_IOMEMCONF		0xbfff0010
-@@ -51,9 +48,9 @@
- #define PCIMT_PCI_CONF		0xbfff0100
- 
- /*
-- * Data port for the PCI bus.
-+ * Data port for the PCI bus in IO space
-  */
--#define PCIMT_CONFIG_DATA	0xb4000cfc
-+#define PCIMT_CONFIG_DATA	0x0cfc
- 
- /*
-  * Board specific registers
-diff -Naur linux-2.6.17.orig/include/asm-mips/stackframe.h linux-2.6.17/include/asm-mips/stackframe.h
---- linux-2.6.17.orig/include/asm-mips/stackframe.h	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/include/asm-mips/stackframe.h	2006-06-19 18:16:14.000000000 -0700
-@@ -305,7 +305,7 @@
- 		mfc0	v0, CP0_TCSTATUS
- 		ori	v0, TCSTATUS_IXMT
- 		mtc0	v0, CP0_TCSTATUS
--		ehb
-+		_ehb
- 		DMT	5				# dmt a1
- 		jal	mips_ihb
- #endif /* CONFIG_MIPS_MT_SMTC */
-@@ -326,14 +326,14 @@
-  * restore TCStatus.IXMT.
-  */
- 		LONG_L	v1, PT_TCSTATUS(sp)
--		ehb
-+		_ehb
- 		mfc0	v0, CP0_TCSTATUS
- 		andi	v1, TCSTATUS_IXMT
- 		/* We know that TCStatua.IXMT should be set from above */
- 		xori	v0, v0, TCSTATUS_IXMT
- 		or	v0, v0, v1
- 		mtc0	v0, CP0_TCSTATUS
--		ehb
-+		_ehb
- 		andi	a1, a1, VPECONTROL_TE
- 		beqz	a1, 1f
- 		emt
-@@ -412,7 +412,7 @@
- 		/* Clear TKSU, leave IXMT */
- 		xori	t0, 0x00001800
- 		mtc0	t0, CP0_TCSTATUS
--		ehb
-+		_ehb
- 		/* We need to leave the global IE bit set, but clear EXL...*/
- 		mfc0	t0, CP0_STATUS
- 		ori	t0, ST0_EXL | ST0_ERL
-@@ -439,7 +439,7 @@
- 		 * and enable interrupts only for the
- 		 * current TC, using the TCStatus register.
- 		 */
--		ehb
-+		_ehb
- 		mfc0	t0,CP0_TCSTATUS
- 		/* Fortunately CU 0 is in the same place in both registers */
- 		/* Set TCU0, TKSU (for later inversion) and IXMT */
-@@ -448,7 +448,7 @@
- 		/* Clear TKSU *and* IXMT */
- 		xori	t0, 0x00001c00
- 		mtc0	t0, CP0_TCSTATUS
--		ehb
-+		_ehb
- 		/* We need to leave the global IE bit set, but clear EXL...*/
- 		mfc0	t0, CP0_STATUS
- 		ori	t0, ST0_EXL
-@@ -480,7 +480,7 @@
- 		andi	v1, v0, TCSTATUS_IXMT
- 		ori	v0, TCSTATUS_IXMT
- 		mtc0	v0, CP0_TCSTATUS
--		ehb
-+		_ehb
- 		DMT	2				# dmt	v0
- 		/*
- 		 * We don't know a priori if ra is "live"
-@@ -496,7 +496,7 @@
- 		xori	t0, 0x1e
- 		mtc0	t0, CP0_STATUS
- #ifdef CONFIG_MIPS_MT_SMTC
--		ehb
-+		_ehb
- 		andi	v0, v0, VPECONTROL_TE
- 		beqz	v0, 2f
- 		nop	/* delay slot */
-diff -Naur linux-2.6.17.orig/include/asm-mips/unistd.h linux-2.6.17/include/asm-mips/unistd.h
---- linux-2.6.17.orig/include/asm-mips/unistd.h	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/include/asm-mips/unistd.h	2006-06-19 18:16:14.000000000 -0700
-@@ -326,16 +326,17 @@
- #define __NR_unshare			(__NR_Linux + 303)
- #define __NR_splice			(__NR_Linux + 304)
- #define __NR_sync_file_range		(__NR_Linux + 305)
-+#define __NR_tee			(__NR_Linux + 306)
- 
- /*
-  * Offset of the last Linux o32 flavoured syscall
-  */
--#define __NR_Linux_syscalls		305
-+#define __NR_Linux_syscalls		306
- 
- #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
- 
- #define __NR_O32_Linux			4000
--#define __NR_O32_Linux_syscalls		305
-+#define __NR_O32_Linux_syscalls		306
- 
- #if _MIPS_SIM == _MIPS_SIM_ABI64
- 
-@@ -608,16 +609,17 @@
- #define __NR_unshare			(__NR_Linux + 262)
- #define __NR_splice			(__NR_Linux + 263)
- #define __NR_sync_file_range		(__NR_Linux + 264)
-+#define __NR_tee			(__NR_Linux + 265)
- 
- /*
-  * Offset of the last Linux 64-bit flavoured syscall
-  */
--#define __NR_Linux_syscalls		264
-+#define __NR_Linux_syscalls		265
- 
- #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
- 
- #define __NR_64_Linux			5000
--#define __NR_64_Linux_syscalls		264
-+#define __NR_64_Linux_syscalls		265
- 
- #if _MIPS_SIM == _MIPS_SIM_NABI32
- 
-@@ -894,16 +896,17 @@
- #define __NR_unshare			(__NR_Linux + 266)
- #define __NR_splice			(__NR_Linux + 267)
- #define __NR_sync_file_range		(__NR_Linux + 268)
-+#define __NR_tee			(__NR_Linux + 269)
- 
- /*
-  * Offset of the last N32 flavoured syscall
-  */
--#define __NR_Linux_syscalls		268
-+#define __NR_Linux_syscalls		269
- 
- #endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
- 
- #define __NR_N32_Linux			6000
--#define __NR_N32_Linux_syscalls		268
-+#define __NR_N32_Linux_syscalls		269
- 
- #ifndef __ASSEMBLY__
- 
-diff -Naur linux-2.6.17.orig/include/asm-mips/war.h linux-2.6.17/include/asm-mips/war.h
---- linux-2.6.17.orig/include/asm-mips/war.h	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/include/asm-mips/war.h	2006-06-19 18:16:14.000000000 -0700
-@@ -172,7 +172,8 @@
-  * On the RM9000 there is a problem which makes the CreateDirtyExclusive
-  * cache operation unusable on SMP systems.
-  */
--#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_PMC_YOSEMITE)
-+#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_PMC_YOSEMITE) || \
-+    defined(CONFIG_BASLER_EXCITE)
- #define  RM9000_CDEX_SMP_WAR		1
- #endif
- 
-@@ -182,7 +183,7 @@
-  * being fetched may case spurious exceptions.
-  */
- #if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_MOMENCO_OCELOT_3) || \
--    defined(CONFIG_PMC_YOSEMITE)
-+    defined(CONFIG_PMC_YOSEMITE) || defined(CONFIG_BASLER_EXCITE)
- #define ICACHE_REFILLS_WORKAROUND_WAR	1
- #endif
- 
-diff -Naur linux-2.6.17.orig/include/linux/elf.h linux-2.6.17/include/linux/elf.h
---- linux-2.6.17.orig/include/linux/elf.h	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/include/linux/elf.h	2006-06-19 18:16:14.000000000 -0700
-@@ -67,7 +67,7 @@
- 
- #define EM_MIPS		8	/* MIPS R3000 (officially, big-endian only) */
- 
--#define EM_MIPS_RS4_BE 10	/* MIPS R4000 big-endian */
-+#define EM_MIPS_RS3_LE 10	/* MIPS R3000 little-endian */
- 
- #define EM_PARISC      15	/* HPPA */
- 
-diff -Naur linux-2.6.17.orig/include/linux/mc146818rtc.h linux-2.6.17/include/linux/mc146818rtc.h
---- linux-2.6.17.orig/include/linux/mc146818rtc.h	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/include/linux/mc146818rtc.h	2006-06-19 18:16:14.000000000 -0700
-@@ -89,4 +89,12 @@
- # define RTC_VRT 0x80		/* valid RAM and time */
- /**********************************************************************/
- 
-+#ifndef RTC_IO_EXTENT
-+#define RTC_IO_EXTENT	0x8
-+#endif
-+
-+#ifndef RTC_IOMAPPED
-+#define RTC_IOMAPPED	1	/* Default to I/O mapping. */
-+#endif
-+
- #endif /* _MC146818RTC_H */
-diff -Naur linux-2.6.17.orig/include/linux/pci_ids.h linux-2.6.17/include/linux/pci_ids.h
---- linux-2.6.17.orig/include/linux/pci_ids.h	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/include/linux/pci_ids.h	2006-06-19 18:16:14.000000000 -0700
-@@ -1569,6 +1569,9 @@
- #define PCI_VENDOR_ID_SATSAGEM		0x1267
- #define PCI_DEVICE_ID_SATSAGEM_NICCY	0x1016
- 
-+#define PCI_VENDOR_ID_SILICON_MOTION		0x126f
-+#define PCI_DEVICE_ID_SM501_VOYAGER_GX_REV_AA	0x0501
-+#define PCI_DEVICE_ID_SM501_VOYAGER_GX_REV_B	0x0510
- 
- #define PCI_VENDOR_ID_ENSONIQ		0x1274
- #define PCI_DEVICE_ID_ENSONIQ_CT5880	0x5880
-diff -Naur linux-2.6.17.orig/include/linux/serial.h linux-2.6.17/include/linux/serial.h
---- linux-2.6.17.orig/include/linux/serial.h	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/include/linux/serial.h	2006-06-19 18:16:14.000000000 -0700
-@@ -76,7 +76,8 @@
- #define PORT_16654	11
- #define PORT_16850	12
- #define PORT_RSA	13	/* RSA-DV II/S card */
--#define PORT_MAX	13
-+#define PORT_SB1250	14
-+#define PORT_MAX	14
- 
- #define SERIAL_IO_PORT	0
- #define SERIAL_IO_HUB6	1
-diff -Naur linux-2.6.17.orig/include/linux/serial_ip3106.h linux-2.6.17/include/linux/serial_ip3106.h
---- linux-2.6.17.orig/include/linux/serial_ip3106.h	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/include/linux/serial_ip3106.h	2006-06-19 18:16:14.000000000 -0700
-@@ -78,4 +78,16 @@
- #define IP3106_UART_FIFO_RXFIFO		0x00001F00
- #define IP3106_UART_FIFO_RBRTHR		0x000000FF
- 
-+#define ip3106_lcr(base,port)    *(volatile u32 *)(base+(port*0x1000) + 0x000)
-+#define ip3106_mcr(base, port)   *(volatile u32 *)(base+(port*0x1000) + 0x004)
-+#define ip3106_baud(base, port)  *(volatile u32 *)(base+(port*0x1000) + 0x008)
-+#define ip3106_cfg(base, port)   *(volatile u32 *)(base+(port*0x1000) + 0x00C)
-+#define ip3106_fifo(base, port)	 *(volatile u32 *)(base+(port*0x1000) + 0x028)
-+#define ip3106_istat(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFE0)
-+#define ip3106_ien(base, port)   *(volatile u32 *)(base+(port*0x1000) + 0xFE4)
-+#define ip3106_iclr(base, port)  *(volatile u32 *)(base+(port*0x1000) + 0xFE8)
-+#define ip3106_iset(base, port)  *(volatile u32 *)(base+(port*0x1000) + 0xFEC)
-+#define ip3106_pd(base, port)    *(volatile u32 *)(base+(port*0x1000) + 0xFF4)
-+#define ip3106_mid(base, port)   *(volatile u32 *)(base+(port*0x1000) + 0xFFC)
-+
- #endif
-diff -Naur linux-2.6.17.orig/sound/oss/au1550_ac97.c linux-2.6.17/sound/oss/au1550_ac97.c
---- linux-2.6.17.orig/sound/oss/au1550_ac97.c	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/sound/oss/au1550_ac97.c	2006-06-19 18:16:14.000000000 -0700
-@@ -60,6 +60,7 @@
- #include <asm/mach-au1x00/au1000.h>
- #include <asm/mach-au1x00/au1xxx_psc.h>
- #include <asm/mach-au1x00/au1xxx_dbdma.h>
-+#include <asm/mach-pb1x00/pb1550.h>
- 
- #undef OSS_DOCUMENTED_MIXER_SEMANTICS
- 
-diff -Naur linux-2.6.17.orig/sound/oss/au1550_i2s.c linux-2.6.17/sound/oss/au1550_i2s.c
---- linux-2.6.17.orig/sound/oss/au1550_i2s.c	1969-12-31 16:00:00.000000000 -0800
-+++ linux-2.6.17/sound/oss/au1550_i2s.c	2006-06-19 18:16:14.000000000 -0700
-@@ -0,0 +1,2029 @@
-+/*
-+ *      au1550_i2s.c  --  Sound driver for Alchemy Au1550 MIPS
-+ *			Internet Edge Processor.
-+ *
-+ * Copyright 2004 Embedded Edge, LLC
-+ *	dan@embeddededge.com
-+ * Copyright 2005 Matt Porter <mporter@kernel.crashing.org>
-+ *
-+ * Mostly copied from the au1550_psc.c driver and some from the
-+ * PowerMac dbdma driver.
-+ * We assume the processor can do memory coherent DMA.
-+ *
-+ * WM8731 mixer support, codec framework, cleanup, and 2.6 port
-+ * Matt Porter <mporter@kernel.crashing.org>
-+ *
-+ * The SMBus (I2C) is required for the control of the
-+ * appears at I2C address 0x36 (I2C binary 0011011).  The Pb1550
-+ * uses the Wolfson WM8731 codec, which is controlled over the I2C.
-+ * It's connected to a 12MHz clock, so we can only reliably support
-+ * 96KHz, 48KHz, 32KHz, and 8KHz data rates.  Variable rate audio is
-+ * unsupported, we currently force it to 48KHz.
-+ *
-+ *  This program is free software; you can redistribute  it and/or modify it
-+ *  under  the terms of  the GNU General  Public License as published by the
-+ *  Free Software Foundation;  either version 2 of the  License, or (at your
-+ *  option) any later version.
-+ *
-+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
-+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
-+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
-+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
-+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
-+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
-+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ *  You should have received a copy of the  GNU General Public License along
-+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
-+ *  675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ */
-+#include <linux/module.h>
-+#include <linux/string.h>
-+#include <linux/ioport.h>
-+#include <linux/sched.h>
-+#include <linux/delay.h>
-+#include <linux/fs.h>
-+#include <linux/hardirq.h>
-+#include <linux/sound.h>
-+#include <linux/slab.h>
-+#include <linux/soundcard.h>
-+#include <linux/init.h>
-+#include <linux/poll.h>
-+#include <linux/pci.h>
-+#include <linux/bitops.h>
-+#include <linux/proc_fs.h>
-+#include <linux/spinlock.h>
-+#include <linux/smp_lock.h>
-+
-+#include <asm/io.h>
-+#include <asm/uaccess.h>
-+#include <asm/hardirq.h>
-+
-+#include <asm/mach-au1x00/au1000.h>
-+#include <asm/mach-au1x00/au1xxx_psc.h>
-+#include <asm/mach-au1x00/au1xxx_dbdma.h>
-+#include <asm/mach-pb1x00/pb1550.h>
-+
-+#undef OSS_DOCUMENTED_MIXER_SEMANTICS
-+
-+#define AU1550_MODULE_NAME "Au1550 I2S Audio"
-+#define PFX AU1550_MODULE_NAME
-+
-+/* Define this if you want to try running at the 44.1 KHz rate.
-+ * It's just a little off, I think it's actually 44117 or something.
-+ * I did this for debugging, since many programs, including this
-+ * driver, will try to upsample from 44.1 to 48 KHz.
-+ * Seems to work well, we'll just leave it this way.
-+ */
-+#define TRY_441KHz
-+
-+#ifdef TRY_441KHz
-+#define SAMP_RATE	44100
-+#else
-+#define SAMP_RATE	48000
-+#endif
-+
-+/* The number of DBDMA ring descriptors to allocate.  No sense making
-+ * this too large....if you can't keep up with a few you aren't likely
-+ * to be able to with lots of them, either.
-+ */
-+#define NUM_DBDMA_DESCRIPTORS 4
-+
-+#define pr_error(format, arg...) printk(KERN_ERR PFX ": " format "\n" , ## arg)
-+
-+static void
-+au1550_delay(int msec)
-+{
-+	unsigned long   tmo;
-+	signed long     tmo2;
-+
-+	if (in_interrupt())
-+		return;
-+
-+	tmo = jiffies + (msec * HZ) / 1000;
-+	for (;;) {
-+		tmo2 = tmo - jiffies;
-+		if (tmo2 <= 0)
-+			break;
-+		schedule_timeout(tmo2);
-+	}
-+}
-+
-+/*
-+ * Codec framework. If somebody supports another codec, they
-+ * should hopefully be able to define another struct i2s_codec
-+ * definition, and #ifdef the support for it and the WM8731 so
-+ * they can be selected via a CONFIG option. For now, we just
-+ * hardcode WM8731_CODEC.
-+ */
-+#define i2s_supported_mixer(CODEC,FOO) ((FOO >= 0) && \
-+                                    (FOO < SOUND_MIXER_NRDEVICES) && \
-+                                    (CODEC)->supported_mixers & (1<<FOO) )
-+
-+struct i2s_codec {
-+	int			modcnt;
-+	int			supported_mixers;
-+	int			stereo_mixers;
-+	int			record_sources;
-+	unsigned int		mixer_state[SOUND_MIXER_NRDEVICES];
-+	void			*data;
-+	int			(*set_mixer) (struct i2s_codec *codec, unsigned int oss_mixer, unsigned int val);
-+	void			(*init_codec) (struct i2s_codec *codec);
-+};
-+
-+#define WM8731_CODEC
-+#ifdef WM8731_CODEC
-+/*
-+ * WM8731 codec support
-+ */
-+#define WM8731_SUPPORTED_MASK (WM8731_STEREO_MASK|WM8731_RECORD_MASK)
-+#define WM8731_STEREO_MASK (SOUND_MASK_VOLUME|SOUND_MASK_LINE)
-+#define WM8731_RECORD_MASK (SOUND_MASK_MIC|SOUND_MASK_LINE)
-+
-+static struct codec_data {
-+	u16			audio_path;
-+} wm8731_data;
-+
-+static void
-+wm8731_wrcodec(u8 ctlreg, u8 val)
-+{
-+	int	rcnt;
-+	extern int pb1550_wm_codec_write(u8 addr, u8 reg, u8 val);
-+
-+	/* The codec is a write only device, with a 16-bit control/data
-+	 * word.  Although it is written as two bytes on the I2C, the
-+	 * format is actually 7 bits of register and 9 bits of data.
-+	 * The ls bit of the first byte is the ms bit of the data.
-+	 */
-+	rcnt = 0;
-+	while ((pb1550_wm_codec_write((0x36 >> 1), ctlreg, val) != 1)
-+							&& (rcnt < 50)) {
-+		rcnt++;
-+	}
-+}
-+
-+static int
-+wm8731_set_mixer(struct i2s_codec *codec, unsigned int oss_mixer, unsigned int val)
-+{
-+	unsigned int lvol, rvol;
-+	struct codec_data *cdata = (struct codec_data *)codec->data;
-+
-+	switch (oss_mixer) {
-+		case SOUND_MIXER_VOLUME:
-+			/* normalize OSS range to fit codec volume control */
-+			lvol = ((((val & 0x7f00) >> 8) * 0x60) / 0x64) + 0x1f;
-+			rvol = (((val & 0x7f) * 0x60) / 0x64) + 0x1f;
-+			lvol |= 0x80;
-+			rvol |= 0x80;
-+			wm8731_wrcodec(0x04, lvol);
-+			au1550_delay(10);
-+			wm8731_wrcodec(0x06, rvol);
-+			au1550_delay(10);
-+			codec->mixer_state[oss_mixer] = val;
-+			break;
-+		case SOUND_MIXER_LINE:
-+			/* normalize OSS range to fit codec line control */
-+			lvol = ((((val & 0x7f00) >> 8) * 0x1f) / 0x64);
-+			rvol = (((val & 0x7f) * 0x1f) / 0x64);
-+			if (!(val & 0x1f00))
-+				lvol |= 0x80;
-+			else
-+				lvol &= ~0x80;
-+			if (!(val & 0x001f))
-+				rvol |= 0x80;
-+			else
-+				rvol &= ~0x80;
-+			wm8731_wrcodec(0x00, lvol);
-+			au1550_delay(10);
-+			wm8731_wrcodec(0x02, rvol);
-+			au1550_delay(10);
-+			codec->mixer_state[oss_mixer] = val;
-+			break;
-+		case SOUND_MIXER_MIC:
-+			if (!val)
-+				cdata->audio_path |= 0x02;
-+			else {
-+				if (val >= 0x32)
-+					cdata->audio_path |= 0x01;
-+				else
-+					cdata->audio_path &= ~0x01;
-+				cdata->audio_path &= ~0x02;
-+			}
-+			wm8731_wrcodec(0x08, cdata->audio_path);
-+			au1550_delay(10);
-+			codec->mixer_state[oss_mixer] = val;
-+			break;
-+		case SOUND_MIXER_RECSRC:
-+			if (val & SOUND_MASK_LINE)
-+				cdata->audio_path &= ~0x04;
-+			else
-+				cdata->audio_path |= 0x04;
-+			wm8731_wrcodec(0x08, cdata->audio_path);
-+			au1550_delay(10);
-+			codec->mixer_state[oss_mixer] = val;
-+			break;
-+		default:
-+			return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+
-+void
-+wm8731_init_codec(struct i2s_codec *codec)
-+{
-+	struct codec_data *cdata = (struct codec_data *)codec->data;
-+
-+	wm8731_wrcodec(0x1e, 0x00);	/* Reset */
-+	au1550_delay(200);
-+	wm8731_wrcodec(0x0c, 0x00);	/* Power up everything */
-+	au1550_delay(10);
-+	wm8731_wrcodec(0x12, 0x00);	/* Deactivate codec */
-+	au1550_delay(10);
-+	cdata->audio_path = 0x10;
-+	/* Select DAC outputs to line out */
-+	wm8731_wrcodec(0x08, cdata->audio_path);
-+	au1550_delay(10);
-+	wm8731_wrcodec(0x0a, 0x00);	/* Disable output mute */
-+	au1550_delay(10);
-+	wm8731_wrcodec(0x0e, 0x02);	/* Set slave, 16-bit, I2S modes */
-+	au1550_delay(10);
-+	wm8731_wrcodec(0x10, 0x01);	/* 12MHz (USB), 250fs */
-+	au1550_delay(10);
-+	wm8731_wrcodec(0x12, 0x01);	/* Activate codec */
-+	au1550_delay(10);
-+
-+	codec->set_mixer(codec, SOUND_MIXER_VOLUME, 0x5050);
-+	codec->set_mixer(codec, SOUND_MIXER_LINE, 0x0000);
-+	codec->set_mixer(codec, SOUND_MIXER_MIC, 0x00);
-+	codec->mixer_state[SOUND_MIXER_RECSRC] = SOUND_MIXER_LINE;
-+}
-+
-+static struct i2s_codec au1550_i2s_codec = {
-+	.supported_mixers	= WM8731_SUPPORTED_MASK,
-+	.stereo_mixers		= WM8731_STEREO_MASK,
-+	.record_sources		= WM8731_RECORD_MASK,
-+	.init_codec		= &wm8731_init_codec,
-+	.set_mixer		= &wm8731_set_mixer,
-+	.data			= &wm8731_data,
-+};
-+#endif /* WM8731_CODEC */
-+
-+static struct au1550_state {
-+	/* soundcore stuff */
-+	int             dev_audio;
-+	int		dev_mixer;
-+
-+	spinlock_t		lock;
-+	struct semaphore	open_sem;
-+	struct semaphore	sem;
-+	mode_t			open_mode;
-+	wait_queue_head_t	open_wait;
-+	volatile psc_i2s_t	*psc_addr;
-+	struct i2s_codec	*codec;
-+
-+	struct dmabuf {
-+		u32		dmanr;
-+		unsigned        sample_rate;
-+		unsigned	src_factor;
-+		unsigned        sample_size;
-+		int             num_channels;
-+		int		dma_bytes_per_sample;
-+		int		user_bytes_per_sample;
-+		int		cnt_factor;
-+
-+		void		*rawbuf;
-+		unsigned        buforder;
-+		unsigned	numfrag;
-+		unsigned        fragshift;
-+		void		*nextIn;
-+		void		*nextOut;
-+		int		count;
-+		unsigned        total_bytes;
-+		unsigned        error;
-+		wait_queue_head_t wait;
-+
-+		/* redundant, but makes calculations easier */
-+		unsigned	fragsize;
-+		unsigned	dma_fragsize;
-+		unsigned	dmasize;
-+		unsigned	dma_qcount;
-+
-+		/* OSS stuff */
-+		unsigned        mapped:1;
-+		unsigned        ready:1;
-+		unsigned        stopped:1;
-+		unsigned        ossfragshift;
-+		int             ossmaxfrags;
-+		unsigned        subdivision;
-+
-+		/* Mixer stuff */
-+		int		dev_mixer;
-+	} dma_dac, dma_adc;
-+} au1550_state;
-+
-+static unsigned
-+ld2(unsigned int x)
-+{
-+	unsigned        r = 0;
-+
-+	if (x >= 0x10000) {
-+		x >>= 16;
-+		r += 16;
-+	}
-+	if (x >= 0x100) {
-+		x >>= 8;
-+		r += 8;
-+	}
-+	if (x >= 0x10) {
-+		x >>= 4;
-+		r += 4;
-+	}
-+	if (x >= 4) {
-+		x >>= 2;
-+		r += 2;
-+	}
-+	if (x >= 2)
-+		r++;
-+	return r;
-+}
-+
-+/* stop the ADC before calling */
-+static void
-+set_adc_rate(struct au1550_state *s, unsigned rate)
-+{
-+	struct dmabuf  *adc = &s->dma_adc;
-+
-+	/* calc SRC factor */
-+	adc->src_factor = (((SAMP_RATE*2) / rate) + 1) >> 1;
-+	adc->sample_rate = SAMP_RATE / adc->src_factor;
-+	return;
-+
-+	adc->src_factor = 1;
-+}
-+
-+/* stop the DAC before calling */
-+static void
-+set_dac_rate(struct au1550_state *s, unsigned rate)
-+{
-+	struct dmabuf  *dac = &s->dma_dac;
-+
-+	/* calc SRC factor */
-+	dac->src_factor = (((SAMP_RATE*2) / rate) + 1) >> 1;
-+	dac->sample_rate = SAMP_RATE / dac->src_factor;
-+	return;
-+
-+	dac->src_factor = 1;
-+}
-+
-+static void
-+stop_dac(struct au1550_state *s)
-+{
-+	struct dmabuf  *db = &s->dma_dac;
-+	unsigned long   flags;
-+	uint	stat;
-+	volatile psc_i2s_t *ip;
-+
-+	if (db->stopped)
-+		return;
-+
-+	ip = s->psc_addr;
-+	spin_lock_irqsave(&s->lock, flags);
-+
-+	ip->psc_i2spcr = PSC_I2SPCR_TP;
-+	au_sync();
-+
-+	/* Wait for Transmit Busy to show disabled.
-+	*/
-+	do {
-+		stat = ip->psc_i2sstat;
-+		au_sync();
-+	} while ((stat & PSC_I2SSTAT_TB) != 0);
-+
-+	au1xxx_dbdma_reset(db->dmanr);
-+
-+	db->stopped = 1;
-+
-+	spin_unlock_irqrestore(&s->lock, flags);
-+}
-+
-+static void
-+stop_adc(struct au1550_state *s)
-+{
-+	struct dmabuf  *db = &s->dma_adc;
-+	unsigned long   flags;
-+	uint	stat;
-+	volatile psc_i2s_t *ip;
-+
-+	if (db->stopped)
-+		return;
-+
-+	ip = s->psc_addr;
-+	spin_lock_irqsave(&s->lock, flags);
-+
-+	ip->psc_i2spcr = PSC_I2SPCR_RP;
-+	au_sync();
-+
-+	/* Wait for Receive Busy to show disabled.
-+	*/
-+	do {
-+		stat = ip->psc_i2sstat;
-+		au_sync();
-+	} while ((stat & PSC_I2SSTAT_RB) != 0);
-+
-+	au1xxx_dbdma_reset(db->dmanr);
-+
-+	db->stopped = 1;
-+
-+	spin_unlock_irqrestore(&s->lock, flags);
-+}
-+
-+static void
-+set_xmit_slots(int num_channels)
-+{
-+	/* This is here just as a place holder.  The WM8731 only
-+	 * supports two fixed channels.
-+	 */
-+}
-+
-+static void
-+set_recv_slots(int num_channels)
-+{
-+	/* This is here just as a place holder.  The WM8731 only
-+	 * supports two fixed channels.
-+	 */
-+}
-+
-+static void
-+start_dac(struct au1550_state *s)
-+{
-+	struct dmabuf  *db = &s->dma_dac;
-+	unsigned long   flags;
-+	volatile psc_i2s_t *ip;
-+
-+	if (!db->stopped)
-+		return;
-+
-+	spin_lock_irqsave(&s->lock, flags);
-+
-+	ip = s->psc_addr;
-+	set_xmit_slots(db->num_channels);
-+	ip->psc_i2spcr = PSC_I2SPCR_TC;
-+	au_sync();
-+	ip->psc_i2spcr = PSC_I2SPCR_TS;
-+	au_sync();
-+
-+	au1xxx_dbdma_start(db->dmanr);
-+
-+	db->stopped = 0;
-+
-+	spin_unlock_irqrestore(&s->lock, flags);
-+}
-+
-+static void
-+start_adc(struct au1550_state *s)
-+{
-+	struct dmabuf  *db = &s->dma_adc;
-+	int	i;
-+	volatile psc_i2s_t *ip;
-+
-+	if (!db->stopped)
-+		return;
-+
-+	/* Put two buffers on the ring to get things started.
-+	*/
-+	for (i=0; i<2; i++) {
-+		au1xxx_dbdma_put_dest(db->dmanr, db->nextIn, db->dma_fragsize);
-+
-+		db->nextIn += db->dma_fragsize;
-+		if (db->nextIn >= db->rawbuf + db->dmasize)
-+			db->nextIn -= db->dmasize;
-+	}
-+
-+	ip = s->psc_addr;
-+	set_recv_slots(db->num_channels);
-+	au1xxx_dbdma_start(db->dmanr);
-+	ip->psc_i2spcr = PSC_I2SPCR_RC;
-+	au_sync();
-+	ip->psc_i2spcr = PSC_I2SPCR_RS;
-+	au_sync();
-+
-+	db->stopped = 0;
-+}
-+
-+static int
-+prog_dmabuf(struct au1550_state *s, struct dmabuf *db)
-+{
-+	unsigned user_bytes_per_sec;
-+	unsigned        bufs;
-+	unsigned        rate = db->sample_rate;
-+
-+	if (!db->rawbuf) {
-+		db->ready = db->mapped = 0;
-+		db->buforder = 5;	/* 32 * PAGE_SIZE */
-+		db->rawbuf = kmalloc((PAGE_SIZE << db->buforder), GFP_KERNEL);
-+		if (!db->rawbuf)
-+			return -ENOMEM;
-+	}
-+
-+	db->cnt_factor = 1;
-+	if (db->sample_size == 8)
-+		db->cnt_factor *= 2;
-+	if (db->num_channels == 1)
-+		db->cnt_factor *= 2;
-+	db->cnt_factor *= db->src_factor;
-+
-+	db->count = 0;
-+	db->dma_qcount = 0;
-+	db->nextIn = db->nextOut = db->rawbuf;
-+
-+	db->user_bytes_per_sample = (db->sample_size>>3) * db->num_channels;
-+	db->dma_bytes_per_sample = 2 * ((db->num_channels == 1) ?
-+					2 : db->num_channels);
-+
-+	user_bytes_per_sec = rate * db->user_bytes_per_sample;
-+	bufs = PAGE_SIZE << db->buforder;
-+	if (db->ossfragshift) {
-+		if ((1000 << db->ossfragshift) < user_bytes_per_sec)
-+			db->fragshift = ld2(user_bytes_per_sec/1000);
-+		else
-+			db->fragshift = db->ossfragshift;
-+	} else {
-+		db->fragshift = ld2(user_bytes_per_sec / 100 /
-+				    (db->subdivision ? db->subdivision : 1));
-+		if (db->fragshift < 3)
-+			db->fragshift = 3;
-+	}
-+
-+	db->fragsize = 1 << db->fragshift;
-+	db->dma_fragsize = db->fragsize * db->cnt_factor;
-+	db->numfrag = bufs / db->dma_fragsize;
-+
-+	while (db->numfrag < 4 && db->fragshift > 3) {
-+		db->fragshift--;
-+		db->fragsize = 1 << db->fragshift;
-+		db->dma_fragsize = db->fragsize * db->cnt_factor;
-+		db->numfrag = bufs / db->dma_fragsize;
-+	}
-+
-+	if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
-+		db->numfrag = db->ossmaxfrags;
-+
-+	db->dmasize = db->dma_fragsize * db->numfrag;
-+	memset(db->rawbuf, 0, bufs);
-+
-+#ifdef AU1000_VERBOSE_DEBUG
-+	dbg("rate=%d, samplesize=%d, channels=%d",
-+	    rate, db->sample_size, db->num_channels);
-+	dbg("fragsize=%d, cnt_factor=%d, dma_fragsize=%d",
-+	    db->fragsize, db->cnt_factor, db->dma_fragsize);
-+	dbg("numfrag=%d, dmasize=%d", db->numfrag, db->dmasize);
-+#endif
-+
-+	db->ready = 1;
-+	return 0;
-+}
-+
-+static int
-+prog_dmabuf_adc(struct au1550_state *s)
-+{
-+	stop_adc(s);
-+	return prog_dmabuf(s, &s->dma_adc);
-+
-+}
-+
-+static int
-+prog_dmabuf_dac(struct au1550_state *s)
-+{
-+	stop_dac(s);
-+	return prog_dmabuf(s, &s->dma_dac);
-+}
-+
-+
-+/* hold spinlock for the following */
-+static void
-+dac_dma_interrupt(int irq, void *dev_id, struct pt_regs *regs)
-+{
-+	struct au1550_state *s = (struct au1550_state *) dev_id;
-+	struct dmabuf  *db = &s->dma_dac;
-+	u32	i2s_stat;
-+	volatile psc_i2s_t *ip;
-+
-+	ip = s->psc_addr;
-+	i2s_stat = ip->psc_i2sstat;
-+#ifdef AU1000_VERBOSE_DEBUG
-+	if (i2s_stat & (PSC_I2SSTAT_TF | PSC_I2SSTAT_TR | PSC_I2SSTAT_TF))
-+		dbg("I2S status = 0x%08x", i2s_stat);
-+#endif
-+	db->dma_qcount--;
-+
-+	if (db->count >= db->fragsize) {
-+		if (au1xxx_dbdma_put_source(db->dmanr, db->nextOut,
-+							db->fragsize) == 0) {
-+			pr_error("qcount < 2 and no ring room!");
-+		}
-+		db->nextOut += db->fragsize;
-+		if (db->nextOut >= db->rawbuf + db->dmasize)
-+			db->nextOut -= db->dmasize;
-+		db->count -= db->fragsize;
-+		db->total_bytes += db->dma_fragsize;
-+		db->dma_qcount++;
-+	}
-+
-+	/* wake up anybody listening */
-+	if (waitqueue_active(&db->wait))
-+		wake_up(&db->wait);
-+}
-+
-+
-+static void
-+adc_dma_interrupt(int irq, void *dev_id, struct pt_regs *regs)
-+{
-+	struct	au1550_state *s = (struct au1550_state *)dev_id;
-+	struct	dmabuf  *dp = &s->dma_adc;
-+	u32	obytes;
-+	char	*obuf;
-+
-+	/* Pull the buffer from the dma queue.
-+	*/
-+	au1xxx_dbdma_get_dest(dp->dmanr, (void *)(&obuf), &obytes);
-+
-+	if ((dp->count + obytes) > dp->dmasize) {
-+		/* Overrun. Stop ADC and log the error
-+		*/
-+		stop_adc(s);
-+		dp->error++;
-+		pr_error("adc overrun");
-+		return;
-+	}
-+
-+	/* Put a new empty buffer on the destination DMA.
-+	*/
-+	au1xxx_dbdma_put_dest(dp->dmanr, dp->nextIn, dp->dma_fragsize);
-+
-+	dp->nextIn += dp->dma_fragsize;
-+	if (dp->nextIn >= dp->rawbuf + dp->dmasize)
-+		dp->nextIn -= dp->dmasize;
-+
-+	dp->count += obytes;
-+	dp->total_bytes += obytes;
-+
-+	/* wake up anybody listening
-+	*/
-+	if (waitqueue_active(&dp->wait))
-+		wake_up(&dp->wait);
-+
-+}
-+
-+static loff_t
-+au1550_llseek(struct file *file, loff_t offset, int origin)
-+{
-+	return -ESPIPE;
-+}
-+
-+static int
-+au1550_open_mixdev(struct inode *inode, struct file *file)
-+{
-+	file->private_data = &au1550_state;
-+	return 0;
-+}
-+
-+static int
-+au1550_release_mixdev(struct inode *inode, struct file *file)
-+{
-+	return 0;
-+}
-+
-+#define I2S_CODEC	"Wolfson WM8731"
-+
-+static int
-+au1550_ioctl_mixdev(struct inode *inode, struct file *file,
-+			       unsigned int cmd, unsigned long arg)
-+{
-+	struct au1550_state *s = (struct au1550_state *)file->private_data;
-+	struct i2s_codec *codec = s->codec;
-+	int i, val = 0;
-+
-+	if (cmd == SOUND_MIXER_INFO) {
-+		mixer_info info;
-+		memset(&info, 0, sizeof(info));
-+		strlcpy(info.id, I2S_CODEC, sizeof(info.id));
-+		strlcpy(info.name, I2S_CODEC, sizeof(info.name));
-+		info.modify_counter = codec->modcnt;
-+		if (copy_to_user((void __user *)arg, &info, sizeof(info)))
-+			return -EFAULT;
-+		return 0;
-+	}
-+	if (cmd == SOUND_OLD_MIXER_INFO) {
-+		_old_mixer_info info;
-+		memset(&info, 0, sizeof(info));
-+		strlcpy(info.id, I2S_CODEC, sizeof(info.id));
-+		strlcpy(info.name, I2S_CODEC, sizeof(info.name));
-+		if (copy_to_user((void __user *)arg, &info, sizeof(info)))
-+			return -EFAULT;
-+		return 0;
-+	}
-+
-+	if (_IOC_TYPE(cmd) != 'M' || _SIOC_SIZE(cmd) != sizeof(int))
-+		return -EINVAL;
-+
-+	if (cmd == OSS_GETVERSION)
-+		return put_user(SOUND_VERSION, (int __user *)arg);
-+
-+	if (_SIOC_DIR(cmd) == _SIOC_READ) {
-+		switch (_IOC_NR(cmd)) {
-+		case SOUND_MIXER_RECSRC: /* give them the current record source */
-+			val = codec->mixer_state[SOUND_MIXER_RECSRC];
-+			break;
-+
-+		case SOUND_MIXER_DEVMASK: /* give them the supported mixers */
-+			val = codec->supported_mixers;
-+			break;
-+
-+		case SOUND_MIXER_RECMASK: /* Arg contains a bit for each supported recording source */
-+			val = codec->record_sources;
-+			break;
-+
-+		case SOUND_MIXER_STEREODEVS: /* Mixer channels supporting stereo */
-+			val = codec->stereo_mixers;
-+			break;
-+
-+		case SOUND_MIXER_CAPS:
-+			val = SOUND_CAP_EXCL_INPUT;
-+			break;
-+
-+		default: /* read a specific mixer */
-+			i = _IOC_NR(cmd);
-+
-+			if (!i2s_supported_mixer(codec, i))
-+				return -EINVAL;
-+
-+			val = codec->mixer_state[i];
-+ 			break;
-+		}
-+		return put_user(val, (int __user *)arg);
-+	}
-+
-+	if (_SIOC_DIR(cmd) == (_SIOC_WRITE|_SIOC_READ)) {
-+		codec->modcnt++;
-+		if (get_user(val, (int __user *)arg))
-+			return -EFAULT;
-+
-+		switch (_IOC_NR(cmd)) {
-+		case SOUND_MIXER_RECSRC: /* Arg contains a bit for each recording source */
-+			if (!val) return 0;
-+			if (!(val &= codec->record_sources)) return -EINVAL;
-+
-+			codec->set_mixer(codec, SOUND_MIXER_RECSRC, val);
-+
-+			return 0;
-+		default: /* write a specific mixer */
-+			i = _IOC_NR(cmd);
-+
-+			if (!i2s_supported_mixer(codec, i))
-+				return -EINVAL;
-+
-+			codec->set_mixer(codec, i, val);
-+
-+			return 0;
-+		}
-+	}
-+	return -EINVAL;
-+}
-+
-+static struct file_operations au1550_mixer_fops = {
-+	owner:THIS_MODULE,
-+	llseek:au1550_llseek,
-+	ioctl:au1550_ioctl_mixdev,
-+	open:au1550_open_mixdev,
-+	release:au1550_release_mixdev,
-+};
-+
-+static int
-+drain_dac(struct au1550_state *s, int nonblock)
-+{
-+	unsigned long   flags;
-+	int             count, tmo;
-+
-+	if (s->dma_dac.mapped || !s->dma_dac.ready || s->dma_dac.stopped)
-+		return 0;
-+
-+	for (;;) {
-+		spin_lock_irqsave(&s->lock, flags);
-+		count = s->dma_dac.count;
-+		spin_unlock_irqrestore(&s->lock, flags);
-+		if (count <= 0)
-+			break;
-+		if (signal_pending(current))
-+			break;
-+		if (nonblock)
-+			return -EBUSY;
-+		tmo = 1000 * count / SAMP_RATE;
-+		tmo /= s->dma_dac.dma_bytes_per_sample;
-+		au1550_delay(tmo);
-+	}
-+	if (signal_pending(current))
-+		return -ERESTARTSYS;
-+	return 0;
-+}
-+
-+static inline u8 S16_TO_U8(s16 ch)
-+{
-+	return (u8) (ch >> 8) + 0x80;
-+}
-+static inline s16 U8_TO_S16(u8 ch)
-+{
-+	return (s16) (ch - 0x80) << 8;
-+}
-+
-+/*
-+ * Translates user samples to dma buffer suitable for audio DAC data:
-+ *     If mono, copy left channel to right channel in dma buffer.
-+ *     If 8 bit samples, cvt to 16-bit before writing to dma buffer.
-+ *     If interpolating (no VRA), duplicate every audio frame src_factor times.
-+ */
-+static int
-+translate_from_user(struct dmabuf *db, char* dmabuf, char* userbuf,
-+							       int dmacount)
-+{
-+	int             sample, i;
-+	int             interp_bytes_per_sample;
-+	int             num_samples;
-+	int             mono = (db->num_channels == 1);
-+	char            usersample[12];
-+	s16             ch, dmasample[6];
-+
-+	if (db->sample_size == 16 && !mono && db->src_factor == 1) {
-+		/* no translation necessary, just copy
-+		*/
-+		if (copy_from_user(dmabuf, userbuf, dmacount))
-+			return -EFAULT;
-+		return dmacount;
-+	}
-+
-+	interp_bytes_per_sample = db->dma_bytes_per_sample * db->src_factor;
-+	num_samples = dmacount / interp_bytes_per_sample;
-+
-+	for (sample = 0; sample < num_samples; sample++) {
-+		if (copy_from_user(usersample, userbuf,
-+				   db->user_bytes_per_sample)) {
-+			return -EFAULT;
-+		}
-+
-+		for (i = 0; i < db->num_channels; i++) {
-+			if (db->sample_size == 8)
-+				ch = U8_TO_S16(usersample[i]);
-+			else
-+				ch = *((s16 *) (&usersample[i * 2]));
-+			dmasample[i] = ch;
-+			if (mono)
-+				dmasample[i + 1] = ch;	/* right channel */
-+		}
-+
-+		/* duplicate every audio frame src_factor times
-+		*/
-+		for (i = 0; i < db->src_factor; i++)
-+			memcpy(dmabuf, dmasample, db->dma_bytes_per_sample);
-+
-+		userbuf += db->user_bytes_per_sample;
-+		dmabuf += interp_bytes_per_sample;
-+	}
-+
-+	return num_samples * interp_bytes_per_sample;
-+}
-+
-+/*
-+ * Translates audio ADC samples to user buffer:
-+ *     If mono, send only left channel to user buffer.
-+ *     If 8 bit samples, cvt from 16 to 8 bit before writing to user buffer.
-+ *     If decimating (no VRA), skip over src_factor audio frames.
-+ */
-+static int
-+translate_to_user(struct dmabuf *db, char* userbuf, char* dmabuf,
-+							     int dmacount)
-+{
-+	int             sample, i;
-+	int             interp_bytes_per_sample;
-+	int             num_samples;
-+	int             mono = (db->num_channels == 1);
-+	char            usersample[12];
-+
-+	if (db->sample_size == 16 && !mono && db->src_factor == 1) {
-+		/* no translation necessary, just copy
-+		*/
-+		if (copy_to_user(userbuf, dmabuf, dmacount))
-+			return -EFAULT;
-+		return dmacount;
-+	}
-+
-+	interp_bytes_per_sample = db->dma_bytes_per_sample * db->src_factor;
-+	num_samples = dmacount / interp_bytes_per_sample;
-+
-+	for (sample = 0; sample < num_samples; sample++) {
-+		for (i = 0; i < db->num_channels; i++) {
-+			if (db->sample_size == 8)
-+				usersample[i] =
-+					S16_TO_U8(*((s16 *) (&dmabuf[i * 2])));
-+			else
-+				*((s16 *) (&usersample[i * 2])) =
-+					*((s16 *) (&dmabuf[i * 2]));
-+		}
-+
-+		if (copy_to_user(userbuf, usersample,
-+				 db->user_bytes_per_sample)) {
-+			return -EFAULT;
-+		}
-+
-+		userbuf += db->user_bytes_per_sample;
-+		dmabuf += interp_bytes_per_sample;
-+	}
-+
-+	return num_samples * interp_bytes_per_sample;
-+}
-+
-+/*
-+ * Copy audio data to/from user buffer from/to dma buffer, taking care
-+ * that we wrap when reading/writing the dma buffer. Returns actual byte
-+ * count written to or read from the dma buffer.
-+ */
-+static int
-+copy_dmabuf_user(struct dmabuf *db, char* userbuf, int count, int to_user)
-+{
-+	char           *bufptr = to_user ? db->nextOut : db->nextIn;
-+	char           *bufend = db->rawbuf + db->dmasize;
-+	int             cnt, ret;
-+
-+	if (bufptr + count > bufend) {
-+		int             partial = (int) (bufend - bufptr);
-+		if (to_user) {
-+			if ((cnt = translate_to_user(db, userbuf,
-+						     bufptr, partial)) < 0)
-+				return cnt;
-+			ret = cnt;
-+			if ((cnt = translate_to_user(db, userbuf + partial,
-+						     db->rawbuf,
-+						     count - partial)) < 0)
-+				return cnt;
-+			ret += cnt;
-+		} else {
-+			if ((cnt = translate_from_user(db, bufptr, userbuf,
-+						       partial)) < 0)
-+				return cnt;
-+			ret = cnt;
-+			if ((cnt = translate_from_user(db, db->rawbuf,
-+						       userbuf + partial,
-+						       count - partial)) < 0)
-+				return cnt;
-+			ret += cnt;
-+		}
-+	} else {
-+		if (to_user)
-+			ret = translate_to_user(db, userbuf, bufptr, count);
-+		else
-+			ret = translate_from_user(db, bufptr, userbuf, count);
-+	}
-+
-+	return ret;
-+}
-+
-+static ssize_t
-+au1550_read(struct file *file, char *buffer, size_t count, loff_t *ppos)
-+{
-+	struct au1550_state *s = (struct au1550_state *)file->private_data;
-+	struct dmabuf  *db = &s->dma_adc;
-+	DECLARE_WAITQUEUE(wait, current);
-+	ssize_t         ret;
-+	unsigned long   flags;
-+	int             cnt, usercnt, avail;
-+
-+	if (db->mapped)
-+		return -ENXIO;
-+	if (!access_ok(VERIFY_WRITE, buffer, count))
-+		return -EFAULT;
-+	ret = 0;
-+
-+	count *= db->cnt_factor;
-+
-+	down(&s->sem);
-+	add_wait_queue(&db->wait, &wait);
-+
-+	while (count > 0) {
-+		/* wait for samples in ADC dma buffer
-+		*/
-+		do {
-+			if (db->stopped)
-+				start_adc(s);
-+			spin_lock_irqsave(&s->lock, flags);
-+			avail = db->count;
-+			if (avail <= 0)
-+				__set_current_state(TASK_INTERRUPTIBLE);
-+			spin_unlock_irqrestore(&s->lock, flags);
-+			if (avail <= 0) {
-+				if (file->f_flags & O_NONBLOCK) {
-+					if (!ret)
-+						ret = -EAGAIN;
-+					goto out;
-+				}
-+				up(&s->sem);
-+				schedule();
-+				if (signal_pending(current)) {
-+					if (!ret)
-+						ret = -ERESTARTSYS;
-+					goto out2;
-+				}
-+				down(&s->sem);
-+			}
-+		} while (avail <= 0);
-+
-+		/* copy from nextOut to user
-+		*/
-+		if ((cnt = copy_dmabuf_user(db, buffer,
-+					    count > avail ?
-+					    avail : count, 1)) < 0) {
-+			if (!ret)
-+				ret = -EFAULT;
-+			goto out;
-+		}
-+
-+		spin_lock_irqsave(&s->lock, flags);
-+		db->count -= cnt;
-+		db->nextOut += cnt;
-+		if (db->nextOut >= db->rawbuf + db->dmasize)
-+			db->nextOut -= db->dmasize;
-+		spin_unlock_irqrestore(&s->lock, flags);
-+
-+		count -= cnt;
-+		usercnt = cnt / db->cnt_factor;
-+		buffer += usercnt;
-+		ret += usercnt;
-+	}			/* while (count > 0) */
-+
-+out:
-+	up(&s->sem);
-+out2:
-+	remove_wait_queue(&db->wait, &wait);
-+	set_current_state(TASK_RUNNING);
-+	return ret;
-+}
-+
-+static ssize_t
-+au1550_write(struct file *file, const char *buffer, size_t count, loff_t * ppos)
-+{
-+	struct au1550_state *s = (struct au1550_state *)file->private_data;
-+	struct dmabuf  *db = &s->dma_dac;
-+	DECLARE_WAITQUEUE(wait, current);
-+	ssize_t         ret = 0;
-+	unsigned long   flags;
-+	int             cnt, usercnt, avail;
-+
-+#ifdef AU1000_VERBOSE_DEBUG
-+	dbg("write: count=%d", count);
-+#endif
-+
-+	if (db->mapped)
-+		return -ENXIO;
-+	if (!access_ok(VERIFY_READ, buffer, count))
-+		return -EFAULT;
-+
-+	count *= db->cnt_factor;
-+
-+	down(&s->sem);
-+	add_wait_queue(&db->wait, &wait);
-+
-+	while (count > 0) {
-+		/* wait for space in playback buffer
-+		*/
-+		do {
-+			spin_lock_irqsave(&s->lock, flags);
-+			avail = (int) db->dmasize - db->count;
-+			if (avail <= 0)
-+				__set_current_state(TASK_INTERRUPTIBLE);
-+			spin_unlock_irqrestore(&s->lock, flags);
-+			if (avail <= 0) {
-+				if (file->f_flags & O_NONBLOCK) {
-+					if (!ret)
-+						ret = -EAGAIN;
-+					goto out;
-+				}
-+				up(&s->sem);
-+				schedule();
-+				if (signal_pending(current)) {
-+					if (!ret)
-+						ret = -ERESTARTSYS;
-+					goto out2;
-+				}
-+				down(&s->sem);
-+			}
-+		} while (avail <= 0);
-+
-+		/* copy from user to nextIn
-+		*/
-+		if ((cnt = copy_dmabuf_user(db, (char *) buffer,
-+					    count > avail ?
-+					    avail : count, 0)) < 0) {
-+			if (!ret)
-+				ret = -EFAULT;
-+			goto out;
-+		}
-+
-+		spin_lock_irqsave(&s->lock, flags);
-+		db->count += cnt;
-+		db->nextIn += cnt;
-+		if (db->nextIn >= db->rawbuf + db->dmasize)
-+			db->nextIn -= db->dmasize;
-+
-+		/* If the data is available, we want to keep two buffers
-+		 * on the dma queue.  If the queue count reaches zero,
-+		 * we know the dma has stopped.
-+		 */
-+		while ((db->dma_qcount < 2) && (db->count >= db->fragsize)) {
-+			if (au1xxx_dbdma_put_source(db->dmanr, db->nextOut,
-+							db->fragsize) == 0) {
-+				pr_error("qcount < 2 and no ring room!");
-+			}
-+			db->nextOut += db->fragsize;
-+			if (db->nextOut >= db->rawbuf + db->dmasize)
-+				db->nextOut -= db->dmasize;
-+			db->count -= db->fragsize;
-+			db->total_bytes += db->dma_fragsize;
-+			if (db->dma_qcount == 0)
-+				start_dac(s);
-+			db->dma_qcount++;
-+		}
-+		spin_unlock_irqrestore(&s->lock, flags);
-+
-+		count -= cnt;
-+		usercnt = cnt / db->cnt_factor;
-+		buffer += usercnt;
-+		ret += usercnt;
-+	}			/* while (count > 0) */
-+
-+out:
-+	up(&s->sem);
-+out2:
-+	remove_wait_queue(&db->wait, &wait);
-+	set_current_state(TASK_RUNNING);
-+	return ret;
-+}
-+
-+
-+/* No kernel lock - we have our own spinlock */
-+static unsigned int
-+au1550_poll(struct file *file, struct poll_table_struct *wait)
-+{
-+	struct au1550_state *s = (struct au1550_state *)file->private_data;
-+	unsigned long   flags;
-+	unsigned int    mask = 0;
-+
-+	if (file->f_mode & FMODE_WRITE) {
-+		if (!s->dma_dac.ready)
-+			return 0;
-+		poll_wait(file, &s->dma_dac.wait, wait);
-+	}
-+	if (file->f_mode & FMODE_READ) {
-+		if (!s->dma_adc.ready)
-+			return 0;
-+		poll_wait(file, &s->dma_adc.wait, wait);
-+	}
-+
-+	spin_lock_irqsave(&s->lock, flags);
-+
-+	if (file->f_mode & FMODE_READ) {
-+		if (s->dma_adc.count >= (signed)s->dma_adc.dma_fragsize)
-+			mask |= POLLIN | POLLRDNORM;
-+	}
-+	if (file->f_mode & FMODE_WRITE) {
-+		if (s->dma_dac.mapped) {
-+			if (s->dma_dac.count >=
-+			    (signed)s->dma_dac.dma_fragsize)
-+				mask |= POLLOUT | POLLWRNORM;
-+		} else {
-+			if ((signed) s->dma_dac.dmasize >=
-+			    s->dma_dac.count + (signed)s->dma_dac.dma_fragsize)
-+				mask |= POLLOUT | POLLWRNORM;
-+		}
-+	}
-+	spin_unlock_irqrestore(&s->lock, flags);
-+	return mask;
-+}
-+
-+static int
-+au1550_mmap(struct file *file, struct vm_area_struct *vma)
-+{
-+	struct au1550_state *s = (struct au1550_state *)file->private_data;
-+	struct dmabuf  *db;
-+	unsigned long   size;
-+	int ret = 0;
-+
-+	lock_kernel();
-+	down(&s->sem);
-+	if (vma->vm_flags & VM_WRITE)
-+		db = &s->dma_dac;
-+	else if (vma->vm_flags & VM_READ)
-+		db = &s->dma_adc;
-+	else {
-+		ret = -EINVAL;
-+		goto out;
-+	}
-+	if (vma->vm_pgoff != 0) {
-+		ret = -EINVAL;
-+		goto out;
-+	}
-+	size = vma->vm_end - vma->vm_start;
-+	if (size > (PAGE_SIZE << db->buforder)) {
-+		ret = -EINVAL;
-+		goto out;
-+	}
-+	if (remap_pfn_range(vma, vma->vm_start,
-+			     page_to_pfn(virt_to_page(db->rawbuf)),
-+			     size, vma->vm_page_prot)) {
-+		ret = -EAGAIN;
-+		goto out;
-+	}
-+	vma->vm_flags &= ~VM_IO;
-+	db->mapped = 1;
-+out:
-+	up(&s->sem);
-+	unlock_kernel();
-+	return ret;
-+}
-+
-+
-+#ifdef AU1000_VERBOSE_DEBUG
-+static struct ioctl_str_t {
-+	unsigned int    cmd;
-+	const char     *str;
-+} ioctl_str[] = {
-+	{SNDCTL_DSP_RESET, "SNDCTL_DSP_RESET"},
-+	{SNDCTL_DSP_SYNC, "SNDCTL_DSP_SYNC"},
-+	{SNDCTL_DSP_SPEED, "SNDCTL_DSP_SPEED"},
-+	{SNDCTL_DSP_STEREO, "SNDCTL_DSP_STEREO"},
-+	{SNDCTL_DSP_GETBLKSIZE, "SNDCTL_DSP_GETBLKSIZE"},
-+	{SNDCTL_DSP_SAMPLESIZE, "SNDCTL_DSP_SAMPLESIZE"},
-+	{SNDCTL_DSP_CHANNELS, "SNDCTL_DSP_CHANNELS"},
-+	{SOUND_PCM_WRITE_CHANNELS, "SOUND_PCM_WRITE_CHANNELS"},
-+	{SOUND_PCM_WRITE_FILTER, "SOUND_PCM_WRITE_FILTER"},
-+	{SNDCTL_DSP_POST, "SNDCTL_DSP_POST"},
-+	{SNDCTL_DSP_SUBDIVIDE, "SNDCTL_DSP_SUBDIVIDE"},
-+	{SNDCTL_DSP_SETFRAGMENT, "SNDCTL_DSP_SETFRAGMENT"},
-+	{SNDCTL_DSP_GETFMTS, "SNDCTL_DSP_GETFMTS"},
-+	{SNDCTL_DSP_SETFMT, "SNDCTL_DSP_SETFMT"},
-+	{SNDCTL_DSP_GETOSPACE, "SNDCTL_DSP_GETOSPACE"},
-+	{SNDCTL_DSP_GETISPACE, "SNDCTL_DSP_GETISPACE"},
-+	{SNDCTL_DSP_NONBLOCK, "SNDCTL_DSP_NONBLOCK"},
-+	{SNDCTL_DSP_GETCAPS, "SNDCTL_DSP_GETCAPS"},
-+	{SNDCTL_DSP_GETTRIGGER, "SNDCTL_DSP_GETTRIGGER"},
-+	{SNDCTL_DSP_SETTRIGGER, "SNDCTL_DSP_SETTRIGGER"},
-+	{SNDCTL_DSP_GETIPTR, "SNDCTL_DSP_GETIPTR"},
-+	{SNDCTL_DSP_GETOPTR, "SNDCTL_DSP_GETOPTR"},
-+	{SNDCTL_DSP_MAPINBUF, "SNDCTL_DSP_MAPINBUF"},
-+	{SNDCTL_DSP_MAPOUTBUF, "SNDCTL_DSP_MAPOUTBUF"},
-+	{SNDCTL_DSP_SETSYNCRO, "SNDCTL_DSP_SETSYNCRO"},
-+	{SNDCTL_DSP_SETDUPLEX, "SNDCTL_DSP_SETDUPLEX"},
-+	{SNDCTL_DSP_GETODELAY, "SNDCTL_DSP_GETODELAY"},
-+	{SNDCTL_DSP_GETCHANNELMASK, "SNDCTL_DSP_GETCHANNELMASK"},
-+	{SNDCTL_DSP_BIND_CHANNEL, "SNDCTL_DSP_BIND_CHANNEL"},
-+	{OSS_GETVERSION, "OSS_GETVERSION"},
-+	{SOUND_PCM_READ_RATE, "SOUND_PCM_READ_RATE"},
-+	{SOUND_PCM_READ_CHANNELS, "SOUND_PCM_READ_CHANNELS"},
-+	{SOUND_PCM_READ_BITS, "SOUND_PCM_READ_BITS"},
-+	{SOUND_PCM_READ_FILTER, "SOUND_PCM_READ_FILTER"}
-+};
-+#endif
-+
-+static int
-+dma_count_done(struct dmabuf *db)
-+{
-+	if (db->stopped)
-+		return 0;
-+
-+	return db->dma_fragsize - au1xxx_get_dma_residue(db->dmanr);
-+}
-+
-+
-+static int
-+au1550_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
-+							unsigned long arg)
-+{
-+	struct au1550_state *s = (struct au1550_state *)file->private_data;
-+	unsigned long   flags;
-+	audio_buf_info  abinfo;
-+	count_info      cinfo;
-+	int             count;
-+	int             val, mapped, ret, diff;
-+
-+	mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
-+		((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
-+
-+#ifdef AU1000_VERBOSE_DEBUG
-+	for (count=0; count<sizeof(ioctl_str)/sizeof(ioctl_str[0]); count++) {
-+		if (ioctl_str[count].cmd == cmd)
-+			break;
-+	}
-+	if (count < sizeof(ioctl_str) / sizeof(ioctl_str[0]))
-+		dbg("ioctl %s, arg=0x%lx", ioctl_str[count].str, arg);
-+	else
-+		dbg("ioctl 0x%x unknown, arg=0x%lx", cmd, arg);
-+#endif
-+
-+	switch (cmd) {
-+	case OSS_GETVERSION:
-+		return put_user(SOUND_VERSION, (int *) arg);
-+
-+	case SNDCTL_DSP_SYNC:
-+		if (file->f_mode & FMODE_WRITE)
-+			return drain_dac(s, file->f_flags & O_NONBLOCK);
-+		return 0;
-+
-+	case SNDCTL_DSP_SETDUPLEX:
-+		return 0;
-+
-+	case SNDCTL_DSP_GETCAPS:
-+		return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME |
-+				DSP_CAP_TRIGGER | DSP_CAP_MMAP, (int *)arg);
-+
-+	case SNDCTL_DSP_RESET:
-+		if (file->f_mode & FMODE_WRITE) {
-+			stop_dac(s);
-+			synchronize_irq();
-+			s->dma_dac.count = s->dma_dac.total_bytes = 0;
-+			s->dma_dac.nextIn = s->dma_dac.nextOut =
-+				s->dma_dac.rawbuf;
-+		}
-+		if (file->f_mode & FMODE_READ) {
-+			stop_adc(s);
-+			synchronize_irq();
-+			s->dma_adc.count = s->dma_adc.total_bytes = 0;
-+			s->dma_adc.nextIn = s->dma_adc.nextOut =
-+				s->dma_adc.rawbuf;
-+		}
-+		return 0;
-+
-+	case SNDCTL_DSP_SPEED:
-+		if (get_user(val, (int *) arg))
-+			return -EFAULT;
-+		if (val >= 0) {
-+			if (file->f_mode & FMODE_READ) {
-+				stop_adc(s);
-+				set_adc_rate(s, val);
-+			}
-+			if (file->f_mode & FMODE_WRITE) {
-+				stop_dac(s);
-+				set_dac_rate(s, val);
-+			}
-+			if (s->open_mode & FMODE_READ)
-+				if ((ret = prog_dmabuf_adc(s)))
-+					return ret;
-+			if (s->open_mode & FMODE_WRITE)
-+				if ((ret = prog_dmabuf_dac(s)))
-+					return ret;
-+		}
-+		return put_user((file->f_mode & FMODE_READ) ?
-+				s->dma_adc.sample_rate :
-+				s->dma_dac.sample_rate,
-+				(int *)arg);
-+
-+	case SNDCTL_DSP_STEREO:
-+		if (get_user(val, (int *) arg))
-+			return -EFAULT;
-+		if (file->f_mode & FMODE_READ) {
-+			stop_adc(s);
-+			s->dma_adc.num_channels = val ? 2 : 1;
-+			if ((ret = prog_dmabuf_adc(s)))
-+				return ret;
-+		}
-+		if (file->f_mode & FMODE_WRITE) {
-+			stop_dac(s);
-+			s->dma_dac.num_channels = val ? 2 : 1;
-+			if ((ret = prog_dmabuf_dac(s)))
-+				return ret;
-+		}
-+		return 0;
-+
-+	case SNDCTL_DSP_CHANNELS:
-+		if (get_user(val, (int *) arg))
-+			return -EFAULT;
-+		if (val != 0) {
-+			if (file->f_mode & FMODE_READ) {
-+				if (val < 0 || val > 2)
-+					return -EINVAL;
-+				stop_adc(s);
-+				s->dma_adc.num_channels = val;
-+				if ((ret = prog_dmabuf_adc(s)))
-+					return ret;
-+			}
-+			if (file->f_mode & FMODE_WRITE) {
-+				switch (val) {
-+				case 1:
-+				case 2:
-+					break;
-+				default:
-+					return -EINVAL;
-+				}
-+
-+				stop_dac(s);
-+				s->dma_dac.num_channels = val;
-+				if ((ret = prog_dmabuf_dac(s)))
-+					return ret;
-+			}
-+		}
-+		return put_user(val, (int *) arg);
-+
-+	case SNDCTL_DSP_GETFMTS:	/* Returns a mask */
-+		return put_user(AFMT_S16_LE | AFMT_U8, (int *) arg);
-+
-+	case SNDCTL_DSP_SETFMT:	/* Selects ONE fmt */
-+		if (get_user(val, (int *) arg))
-+			return -EFAULT;
-+		if (val != AFMT_QUERY) {
-+			if (file->f_mode & FMODE_READ) {
-+				stop_adc(s);
-+				if (val == AFMT_S16_LE)
-+					s->dma_adc.sample_size = 16;
-+				else {
-+					val = AFMT_U8;
-+					s->dma_adc.sample_size = 8;
-+				}
-+				if ((ret = prog_dmabuf_adc(s)))
-+					return ret;
-+			}
-+			if (file->f_mode & FMODE_WRITE) {
-+				stop_dac(s);
-+				if (val == AFMT_S16_LE)
-+					s->dma_dac.sample_size = 16;
-+				else {
-+					val = AFMT_U8;
-+					s->dma_dac.sample_size = 8;
-+				}
-+				if ((ret = prog_dmabuf_dac(s)))
-+					return ret;
-+			}
-+		} else {
-+			if (file->f_mode & FMODE_READ)
-+				val = (s->dma_adc.sample_size == 16) ?
-+					AFMT_S16_LE : AFMT_U8;
-+			else
-+				val = (s->dma_dac.sample_size == 16) ?
-+					AFMT_S16_LE : AFMT_U8;
-+		}
-+		return put_user(val, (int *) arg);
-+
-+	case SNDCTL_DSP_POST:
-+		return 0;
-+
-+	case SNDCTL_DSP_GETTRIGGER:
-+		val = 0;
-+		spin_lock_irqsave(&s->lock, flags);
-+		if (file->f_mode & FMODE_READ && !s->dma_adc.stopped)
-+			val |= PCM_ENABLE_INPUT;
-+		if (file->f_mode & FMODE_WRITE && !s->dma_dac.stopped)
-+			val |= PCM_ENABLE_OUTPUT;
-+		spin_unlock_irqrestore(&s->lock, flags);
-+		return put_user(val, (int *) arg);
-+
-+	case SNDCTL_DSP_SETTRIGGER:
-+		if (get_user(val, (int *) arg))
-+			return -EFAULT;
-+		if (file->f_mode & FMODE_READ) {
-+			if (val & PCM_ENABLE_INPUT)
-+				start_adc(s);
-+			else
-+				stop_adc(s);
-+		}
-+		if (file->f_mode & FMODE_WRITE) {
-+			if (val & PCM_ENABLE_OUTPUT)
-+				start_dac(s);
-+			else
-+				stop_dac(s);
-+		}
-+		return 0;
-+
-+	case SNDCTL_DSP_GETOSPACE:
-+		if (!(file->f_mode & FMODE_WRITE))
-+			return -EINVAL;
-+		abinfo.fragsize = s->dma_dac.fragsize;
-+		spin_lock_irqsave(&s->lock, flags);
-+		count = s->dma_dac.count;
-+		count -= dma_count_done(&s->dma_dac);
-+		spin_unlock_irqrestore(&s->lock, flags);
-+		if (count < 0)
-+			count = 0;
-+		abinfo.bytes = (s->dma_dac.dmasize - count) /
-+			s->dma_dac.cnt_factor;
-+		abinfo.fragstotal = s->dma_dac.numfrag;
-+		abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
-+#ifdef AU1000_VERBOSE_DEBUG
-+		dbg("bytes=%d, fragments=%d", abinfo.bytes, abinfo.fragments);
-+#endif
-+		return copy_to_user((void *) arg, &abinfo,
-+				    sizeof(abinfo)) ? -EFAULT : 0;
-+
-+	case SNDCTL_DSP_GETISPACE:
-+		if (!(file->f_mode & FMODE_READ))
-+			return -EINVAL;
-+		abinfo.fragsize = s->dma_adc.fragsize;
-+		spin_lock_irqsave(&s->lock, flags);
-+		count = s->dma_adc.count;
-+		count += dma_count_done(&s->dma_adc);
-+		spin_unlock_irqrestore(&s->lock, flags);
-+		if (count < 0)
-+			count = 0;
-+		abinfo.bytes = count / s->dma_adc.cnt_factor;
-+		abinfo.fragstotal = s->dma_adc.numfrag;
-+		abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
-+		return copy_to_user((void *) arg, &abinfo,
-+				    sizeof(abinfo)) ? -EFAULT : 0;
-+
-+	case SNDCTL_DSP_NONBLOCK:
-+		file->f_flags |= O_NONBLOCK;
-+		return 0;
-+
-+	case SNDCTL_DSP_GETODELAY:
-+		if (!(file->f_mode & FMODE_WRITE))
-+			return -EINVAL;
-+		spin_lock_irqsave(&s->lock, flags);
-+		count = s->dma_dac.count;
-+		count -= dma_count_done(&s->dma_dac);
-+		spin_unlock_irqrestore(&s->lock, flags);
-+		if (count < 0)
-+			count = 0;
-+		count /= s->dma_dac.cnt_factor;
-+		return put_user(count, (int *) arg);
-+
-+	case SNDCTL_DSP_GETIPTR:
-+		if (!(file->f_mode & FMODE_READ))
-+			return -EINVAL;
-+		spin_lock_irqsave(&s->lock, flags);
-+		cinfo.bytes = s->dma_adc.total_bytes;
-+		count = s->dma_adc.count;
-+		if (!s->dma_adc.stopped) {
-+			diff = dma_count_done(&s->dma_adc);
-+			count += diff;
-+			cinfo.bytes += diff;
-+			cinfo.ptr =  virt_to_phys(s->dma_adc.nextIn) + diff -
-+				virt_to_phys(s->dma_adc.rawbuf);
-+		} else
-+			cinfo.ptr = virt_to_phys(s->dma_adc.nextIn) -
-+				virt_to_phys(s->dma_adc.rawbuf);
-+		if (s->dma_adc.mapped)
-+			s->dma_adc.count &= (s->dma_adc.dma_fragsize-1);
-+		spin_unlock_irqrestore(&s->lock, flags);
-+		if (count < 0)
-+			count = 0;
-+		cinfo.blocks = count >> s->dma_adc.fragshift;
-+		return copy_to_user((void *) arg, &cinfo, sizeof(cinfo));
-+
-+	case SNDCTL_DSP_GETOPTR:
-+		if (!(file->f_mode & FMODE_READ))
-+			return -EINVAL;
-+		spin_lock_irqsave(&s->lock, flags);
-+		cinfo.bytes = s->dma_dac.total_bytes;
-+		count = s->dma_dac.count;
-+		if (!s->dma_dac.stopped) {
-+			diff = dma_count_done(&s->dma_dac);
-+			count -= diff;
-+			cinfo.bytes += diff;
-+			cinfo.ptr = virt_to_phys(s->dma_dac.nextOut) + diff -
-+				virt_to_phys(s->dma_dac.rawbuf);
-+		} else
-+			cinfo.ptr = virt_to_phys(s->dma_dac.nextOut) -
-+				virt_to_phys(s->dma_dac.rawbuf);
-+		if (s->dma_dac.mapped)
-+			s->dma_dac.count &= (s->dma_dac.dma_fragsize-1);
-+		spin_unlock_irqrestore(&s->lock, flags);
-+		if (count < 0)
-+			count = 0;
-+		cinfo.blocks = count >> s->dma_dac.fragshift;
-+		return copy_to_user((void *) arg, &cinfo, sizeof(cinfo));
-+
-+	case SNDCTL_DSP_GETBLKSIZE:
-+		if (file->f_mode & FMODE_WRITE)
-+			return put_user(s->dma_dac.fragsize, (int *) arg);
-+		else
-+			return put_user(s->dma_adc.fragsize, (int *) arg);
-+
-+	case SNDCTL_DSP_SETFRAGMENT:
-+		if (get_user(val, (int *) arg))
-+			return -EFAULT;
-+		if (file->f_mode & FMODE_READ) {
-+			stop_adc(s);
-+			s->dma_adc.ossfragshift = val & 0xffff;
-+			s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
-+			if (s->dma_adc.ossfragshift < 4)
-+				s->dma_adc.ossfragshift = 4;
-+			if (s->dma_adc.ossfragshift > 15)
-+				s->dma_adc.ossfragshift = 15;
-+			if (s->dma_adc.ossmaxfrags < 4)
-+				s->dma_adc.ossmaxfrags = 4;
-+			if ((ret = prog_dmabuf_adc(s)))
-+				return ret;
-+		}
-+		if (file->f_mode & FMODE_WRITE) {
-+			stop_dac(s);
-+			s->dma_dac.ossfragshift = val & 0xffff;
-+			s->dma_dac.ossmaxfrags = (val >> 16) & 0xffff;
-+			if (s->dma_dac.ossfragshift < 4)
-+				s->dma_dac.ossfragshift = 4;
-+			if (s->dma_dac.ossfragshift > 15)
-+				s->dma_dac.ossfragshift = 15;
-+			if (s->dma_dac.ossmaxfrags < 4)
-+				s->dma_dac.ossmaxfrags = 4;
-+			if ((ret = prog_dmabuf_dac(s)))
-+				return ret;
-+		}
-+		return 0;
-+
-+	case SNDCTL_DSP_SUBDIVIDE:
-+		if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
-+		    (file->f_mode & FMODE_WRITE && s->dma_dac.subdivision))
-+			return -EINVAL;
-+		if (get_user(val, (int *) arg))
-+			return -EFAULT;
-+		if (val != 1 && val != 2 && val != 4)
-+			return -EINVAL;
-+		if (file->f_mode & FMODE_READ) {
-+			stop_adc(s);
-+			s->dma_adc.subdivision = val;
-+			if ((ret = prog_dmabuf_adc(s)))
-+				return ret;
-+		}
-+		if (file->f_mode & FMODE_WRITE) {
-+			stop_dac(s);
-+			s->dma_dac.subdivision = val;
-+			if ((ret = prog_dmabuf_dac(s)))
-+				return ret;
-+		}
-+		return 0;
-+
-+	case SOUND_PCM_READ_RATE:
-+		return put_user((file->f_mode & FMODE_READ) ?
-+				s->dma_adc.sample_rate :
-+				s->dma_dac.sample_rate,
-+				(int *)arg);
-+
-+	case SOUND_PCM_READ_CHANNELS:
-+		if (file->f_mode & FMODE_READ)
-+			return put_user(s->dma_adc.num_channels, (int *)arg);
-+		else
-+			return put_user(s->dma_dac.num_channels, (int *)arg);
-+
-+	case SOUND_PCM_READ_BITS:
-+		if (file->f_mode & FMODE_READ)
-+			return put_user(s->dma_adc.sample_size, (int *)arg);
-+		else
-+			return put_user(s->dma_dac.sample_size, (int *)arg);
-+
-+	case SOUND_PCM_WRITE_FILTER:
-+	case SNDCTL_DSP_SETSYNCRO:
-+	case SOUND_PCM_READ_FILTER:
-+		return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+
-+
-+static int
-+au1550_open(struct inode *inode, struct file *file)
-+{
-+	int             minor = MINOR(inode->i_rdev);
-+	DECLARE_WAITQUEUE(wait, current);
-+	struct au1550_state *s = &au1550_state;
-+	int             ret;
-+
-+#ifdef AU1000_VERBOSE_DEBUG
-+	if (file->f_flags & O_NONBLOCK)
-+		dbg(__FUNCTION__ ": non-blocking");
-+	else
-+		dbg(__FUNCTION__ ": blocking");
-+#endif
-+
-+	file->private_data = s;
-+	/* wait for device to become free */
-+	down(&s->open_sem);
-+	while (s->open_mode & file->f_mode) {
-+		if (file->f_flags & O_NONBLOCK) {
-+			up(&s->open_sem);
-+			return -EBUSY;
-+		}
-+		add_wait_queue(&s->open_wait, &wait);
-+		__set_current_state(TASK_INTERRUPTIBLE);
-+		up(&s->open_sem);
-+		schedule();
-+		remove_wait_queue(&s->open_wait, &wait);
-+		set_current_state(TASK_RUNNING);
-+		if (signal_pending(current))
-+			return -ERESTARTSYS;
-+		down(&s->open_sem);
-+	}
-+
-+	stop_dac(s);
-+	stop_adc(s);
-+
-+	if (file->f_mode & FMODE_READ) {
-+		s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags =
-+			s->dma_adc.subdivision = s->dma_adc.total_bytes = 0;
-+		s->dma_adc.num_channels = 1;
-+		s->dma_adc.sample_size = 8;
-+		set_adc_rate(s, 8000);
-+		if ((minor & 0xf) == SND_DEV_DSP16)
-+			s->dma_adc.sample_size = 16;
-+	}
-+
-+	if (file->f_mode & FMODE_WRITE) {
-+		s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags =
-+			s->dma_dac.subdivision = s->dma_dac.total_bytes = 0;
-+		s->dma_dac.num_channels = 1;
-+		s->dma_dac.sample_size = 8;
-+		set_dac_rate(s, 8000);
-+		if ((minor & 0xf) == SND_DEV_DSP16)
-+			s->dma_dac.sample_size = 16;
-+	}
-+
-+	if (file->f_mode & FMODE_READ) {
-+		if ((ret = prog_dmabuf_adc(s)))
-+			return ret;
-+	}
-+	if (file->f_mode & FMODE_WRITE) {
-+		if ((ret = prog_dmabuf_dac(s)))
-+			return ret;
-+	}
-+
-+	s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
-+	up(&s->open_sem);
-+	init_MUTEX(&s->sem);
-+	return 0;
-+}
-+
-+static int
-+au1550_release(struct inode *inode, struct file *file)
-+{
-+	struct au1550_state *s = (struct au1550_state *)file->private_data;
-+
-+	lock_kernel();
-+
-+	if (file->f_mode & FMODE_WRITE) {
-+		unlock_kernel();
-+		drain_dac(s, file->f_flags & O_NONBLOCK);
-+		lock_kernel();
-+	}
-+
-+	down(&s->open_sem);
-+	if (file->f_mode & FMODE_WRITE) {
-+		stop_dac(s);
-+		kfree(s->dma_dac.rawbuf);
-+		s->dma_dac.rawbuf = NULL;
-+	}
-+	if (file->f_mode & FMODE_READ) {
-+		stop_adc(s);
-+		kfree(s->dma_adc.rawbuf);
-+		s->dma_adc.rawbuf = NULL;
-+	}
-+	s->open_mode &= ((~file->f_mode) & (FMODE_READ|FMODE_WRITE));
-+	up(&s->open_sem);
-+	wake_up(&s->open_wait);
-+	unlock_kernel();
-+	return 0;
-+}
-+
-+static struct file_operations au1550_audio_fops = {
-+	owner:		THIS_MODULE,
-+	llseek:		au1550_llseek,
-+	read:		au1550_read,
-+	write:		au1550_write,
-+	poll:		au1550_poll,
-+	ioctl:		au1550_ioctl,
-+	mmap:		au1550_mmap,
-+	open:		au1550_open,
-+	release:	au1550_release,
-+};
-+
-+/* Set up an internal clock for the PSC3.  This will then get
-+ * driven out of the Au1550 as the master.
-+ */
-+static void
-+intclk_setup(void)
-+{
-+	uint clk, rate;
-+
-+	/* Wire up Freq4 as a clock for the PSC3.
-+	 * We know SMBus uses Freq3.
-+	 * By making changes to this rate, plus the word strobe
-+	 * size, we can make fine adjustments to the actual data rate.
-+	 */
-+	rate = get_au1x00_speed();
-+#ifdef TRY_441KHz
-+	rate /= (11 * 1000000);
-+#else
-+	rate /= (12 * 1000000);
-+#endif
-+
-+	/* The FRDIV in the frequency control is (FRDIV + 1) * 2
-+	*/
-+	rate /=2;
-+	rate--;
-+	clk = au_readl(SYS_FREQCTRL1);
-+	au_sync();
-+	clk &= ~(SYS_FC_FRDIV4_MASK | SYS_FC_FS4);;
-+	clk |= (rate << SYS_FC_FRDIV4_BIT);
-+	clk |= SYS_FC_FE4;
-+	au_writel(clk, SYS_FREQCTRL1);
-+	au_sync();
-+
-+	/* Set up the clock source routing to get Freq4 to PSC3_intclk.
-+	*/
-+	clk = au_readl(SYS_CLKSRC);
-+	au_sync();
-+	clk &= ~0x01f00000;
-+	clk |= (6 << 22);
-+	au_writel(clk, SYS_CLKSRC);
-+	au_sync();
-+}
-+
-+static int __devinit
-+au1550_probe(void)
-+{
-+	struct au1550_state *s = &au1550_state;
-+	int val;
-+	volatile psc_i2s_t *ip;
-+#ifdef AU1550_DEBUG
-+	char proc_str[80];
-+#endif
-+
-+	memset(s, 0, sizeof(struct au1550_state));
-+
-+	init_waitqueue_head(&s->dma_adc.wait);
-+	init_waitqueue_head(&s->dma_dac.wait);
-+	init_waitqueue_head(&s->open_wait);
-+	init_MUTEX(&s->open_sem);
-+	spin_lock_init(&s->lock);
-+
-+	s->codec = &au1550_i2s_codec;
-+	s->psc_addr = (volatile psc_i2s_t *)I2S_PSC_BASE;
-+	ip = s->psc_addr;
-+
-+	if (!request_region(CPHYSADDR(ip),
-+			    0x30, AU1550_MODULE_NAME)) {
-+		pr_error("I2S Audio ports in use");
-+	}
-+
-+	/* Allocate the DMA Channels
-+	*/
-+	if ((s->dma_dac.dmanr = au1xxx_dbdma_chan_alloc(DBDMA_MEM_CHAN,
-+	    DBDMA_I2S_TX_CHAN, dac_dma_interrupt, (void *)s)) == 0) {
-+		pr_error("Can't get DAC DMA");
-+		goto err_dma1;
-+	}
-+	au1xxx_dbdma_set_devwidth(s->dma_dac.dmanr, 16);
-+	if (au1xxx_dbdma_ring_alloc(s->dma_dac.dmanr,
-+					NUM_DBDMA_DESCRIPTORS) == 0) {
-+		pr_error("Can't get DAC DMA descriptors");
-+		goto err_dma1;
-+	}
-+
-+	if ((s->dma_adc.dmanr = au1xxx_dbdma_chan_alloc(DBDMA_I2S_RX_CHAN,
-+	    DBDMA_MEM_CHAN, adc_dma_interrupt, (void *)s)) == 0) {
-+		pr_error("Can't get ADC DMA");
-+		goto err_dma2;
-+	}
-+	au1xxx_dbdma_set_devwidth(s->dma_adc.dmanr, 16);
-+	if (au1xxx_dbdma_ring_alloc(s->dma_adc.dmanr,
-+					NUM_DBDMA_DESCRIPTORS) == 0) {
-+		pr_error("Can't get ADC DMA descriptors");
-+		goto err_dma2;
-+	}
-+
-+	pr_info("DAC: DMA%d, ADC: DMA%d", DBDMA_I2S_TX_CHAN, DBDMA_I2S_RX_CHAN);
-+
-+	/* register devices */
-+
-+	if ((s->dev_audio = register_sound_dsp(&au1550_audio_fops, -1)) < 0)
-+		goto err_dev1;
-+
-+	if ((s->dev_mixer = register_sound_mixer(&au1550_mixer_fops, -1)) < 0)
-+		goto err_dev2;
-+
-+#ifdef AU1550_DEBUG
-+	/* intialize the debug proc device */
-+	s->ps = create_proc_read_entry(AU1000_MODULE_NAME, 0, NULL,
-+				       proc_au1550_dump, NULL);
-+#endif /* AU1550_DEBUG */
-+
-+	intclk_setup();
-+
-+	/* The GPIO for the appropriate PSC was configured by the
-+	 * board specific start up.
-+	 *
-+	 * configure PSC for I2S Audio
-+	 */
-+	ip->psc_ctrl = PSC_CTRL_DISABLE;	/* Disable PSC */
-+	au_sync();
-+	ip->psc_sel = (PSC_SEL_CLK_INTCLK | PSC_SEL_PS_I2SMODE);
-+	au_sync();
-+
-+	/* Enable PSC
-+	*/
-+	ip->psc_ctrl = PSC_CTRL_ENABLE;
-+	au_sync();
-+
-+	/* Wait for PSC ready.
-+	*/
-+	do {
-+		val = ip->psc_i2sstat;
-+		au_sync();
-+	} while ((val & PSC_I2SSTAT_SR) == 0);
-+
-+	/* Configure I2S controller.
-+	 * Deep FIFO, 16-bit sample, DMA, make sure DMA matches fifo size.
-+	 * Actual I2S mode (first bit delayed by one clock).
-+	 * Master mode (We provide the clock from the PSC).
-+	 */
-+	val = PSC_I2SCFG_SET_LEN(16);
-+#ifdef TRY_441KHz
-+	/* This really should be 250, but it appears that all of the
-+	 * PLLs, dividers and so on in the chain shift it.  That's the
-+	 * problem with sourceing the clock instead of letting the very
-+	 * stable codec provide it.  But, the PSC doesn't appear to want
-+	 * to work in slave mode, so this is what we get.  It's  not
-+	 * studio quality timing, but it's good enough for listening
-+	 * to mp3s.
-+	 */
-+	val |= PSC_I2SCFG_SET_WS(252);
-+#else
-+	val |= PSC_I2SCFG_SET_WS(250);
-+#endif
-+	val |= PSC_I2SCFG_RT_FIFO8 | PSC_I2SCFG_TT_FIFO8 | \
-+					PSC_I2SCFG_BI | PSC_I2SCFG_XM;
-+
-+	ip->psc_i2scfg = val;
-+	au_sync();
-+	val |= PSC_I2SCFG_DE_ENABLE;
-+	ip->psc_i2scfg = val;
-+	au_sync();
-+
-+	/* Wait for Device ready.
-+	*/
-+	do {
-+		val = ip->psc_i2sstat;
-+		au_sync();
-+	} while ((val & PSC_I2SSTAT_DR) == 0);
-+
-+	val = ip->psc_i2scfg;
-+	au_sync();
-+
-+	s->codec->init_codec(s->codec);
-+
-+	return 0;
-+
-+ err_dev2:
-+	unregister_sound_dsp(s->dev_audio);
-+ err_dev1:
-+	au1xxx_dbdma_chan_free(s->dma_adc.dmanr);
-+ err_dma2:
-+	au1xxx_dbdma_chan_free(s->dma_dac.dmanr);
-+ err_dma1:
-+	release_region(CPHYSADDR(I2S_PSC_BASE), 0x30);
-+
-+	return -1;
-+}
-+
-+static void __devinit
-+au1550_remove(void)
-+{
-+	struct au1550_state *s = &au1550_state;
-+
-+	if (!s)
-+		return;
-+#ifdef AU1550_DEBUG
-+	if (s->ps)
-+		remove_proc_entry(AU1000_MODULE_NAME, NULL);
-+#endif /* AU1000_DEBUG */
-+	synchronize_irq();
-+	au1xxx_dbdma_chan_free(s->dma_adc.dmanr);
-+	au1xxx_dbdma_chan_free(s->dma_dac.dmanr);
-+	release_region(CPHYSADDR(I2S_PSC_BASE), 0x30);
-+	unregister_sound_dsp(s->dev_audio);
-+	unregister_sound_mixer(s->dev_mixer);
-+}
-+
-+static int __init
-+init_au1550(void)
-+{
-+	return au1550_probe();
-+}
-+
-+static void __exit
-+cleanup_au1550(void)
-+{
-+	au1550_remove();
-+}
-+
-+module_init(init_au1550);
-+module_exit(cleanup_au1550);
-+
-+MODULE_AUTHOR("Advanced Micro Devices (AMD), dan@embeddededge.com");
-+MODULE_DESCRIPTION("Au1550 I2S Audio Driver");
-diff -Naur linux-2.6.17.orig/sound/oss/Kconfig linux-2.6.17/sound/oss/Kconfig
---- linux-2.6.17.orig/sound/oss/Kconfig	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/sound/oss/Kconfig	2006-06-19 18:16:14.000000000 -0700
-@@ -117,6 +117,10 @@
- 	tristate "Au1550 AC97 Sound"
- 	depends on SOUND_PRIME && SOC_AU1550
- 
-+config SOUND_AU1550_I2S
-+	tristate "Au1550 I2S Sound"
-+	depends on SOUND_PRIME && SOC_AU1550
-+
- config SOUND_TRIDENT
- 	tristate "Trident 4DWave DX/NX, SiS 7018 or ALi 5451 PCI Audio Core"
- 	depends on SOUND_PRIME && PCI
-diff -Naur linux-2.6.17.orig/sound/oss/Makefile linux-2.6.17/sound/oss/Makefile
---- linux-2.6.17.orig/sound/oss/Makefile	2006-06-17 18:49:35.000000000 -0700
-+++ linux-2.6.17/sound/oss/Makefile	2006-06-19 18:16:14.000000000 -0700
-@@ -66,6 +66,7 @@
- obj-$(CONFIG_SOUND_VRC5477)	+= nec_vrc5477.o ac97_codec.o
- obj-$(CONFIG_SOUND_AU1000)	+= au1000.o ac97_codec.o
- obj-$(CONFIG_SOUND_AU1550_AC97)	+= au1550_ac97.o ac97_codec.o
-+obj-$(CONFIG_SOUND_AU1550_I2S)	+= au1550_i2s.o
- obj-$(CONFIG_SOUND_ESSSOLO1)	+= esssolo1.o
- obj-$(CONFIG_SOUND_FUSION)	+= cs46xx.o ac97_codec.o
- obj-$(CONFIG_SOUND_MAESTRO)	+= maestro.o
Index: patches/linux-2.6.17.1-mips-1.patch
===================================================================
--- patches/linux-2.6.17.1-mips-1.patch	(revision f6231bef18674c543a298ab3023c5cbbebc7fc38)
+++ patches/linux-2.6.17.1-mips-1.patch	(revision f6231bef18674c543a298ab3023c5cbbebc7fc38)
@@ -0,0 +1,34976 @@
+Submitted By: Jim Gifford (patches at jg555 dot com)
+Date: 2006-06-19
+Initial Package Version: 2.6.17
+Origin: Linux-MIPS GIT and Mailling Lists
+Upstream Status: N/A
+Description: Merges Linux-MIPS and Kernel.org Tree's
+
+diff -Naur linux-2.6.17.orig/arch/mips/au1000/common/au1xxx_irqmap.c linux-2.6.17/arch/mips/au1000/common/au1xxx_irqmap.c
+--- linux-2.6.17.orig/arch/mips/au1000/common/au1xxx_irqmap.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/au1000/common/au1xxx_irqmap.c	2006-06-19 18:16:12.000000000 -0700
+@@ -55,7 +55,7 @@
+  * Careful if you change match 2 request!
+  * The interrupt handler is called directly from the low level dispatch code.
+  */
+-au1xxx_irq_map_t au1xxx_ic0_map[] = {
++au1xxx_irq_map_t __initdata au1xxx_ic0_map[] = {
+ 
+ #if defined(CONFIG_SOC_AU1000)
+ 	{ AU1000_UART0_INT, INTC_INT_HIGH_LEVEL, 0},
+@@ -220,5 +220,5 @@
+ 
+ };
+ 
+-int au1xxx_ic0_nr_irqs = sizeof(au1xxx_ic0_map)/sizeof(au1xxx_irq_map_t);
++int __initdata au1xxx_ic0_nr_irqs = ARRAY_SIZE(au1xxx_ic0_map);
+ 
+diff -Naur linux-2.6.17.orig/arch/mips/au1000/common/pci.c linux-2.6.17/arch/mips/au1000/common/pci.c
+--- linux-2.6.17.orig/arch/mips/au1000/common/pci.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/au1000/common/pci.c	2006-06-19 18:16:12.000000000 -0700
+@@ -40,17 +40,17 @@
+ 
+ /* TBD */
+ static struct resource pci_io_resource = {
+-	"pci IO space",
+-	(u32)PCI_IO_START,
+-	(u32)PCI_IO_END,
+-	IORESOURCE_IO
++	.start	= PCI_IO_START,
++	.end	= PCI_IO_END,
++	.name	= "PCI IO space",
++	.flags	= IORESOURCE_IO
+ };
+ 
+ static struct resource pci_mem_resource = {
+-	"pci memory space",
+-	(u32)PCI_MEM_START,
+-	(u32)PCI_MEM_END,
+-	IORESOURCE_MEM
++	.start	= PCI_MEM_START,
++	.end	= PCI_MEM_END,
++	.name	= "PCI memory space",
++	.flags	= IORESOURCE_MEM
+ };
+ 
+ extern struct pci_ops au1x_pci_ops;
+diff -Naur linux-2.6.17.orig/arch/mips/au1000/common/setup.c linux-2.6.17/arch/mips/au1000/common/setup.c
+--- linux-2.6.17.orig/arch/mips/au1000/common/setup.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/au1000/common/setup.c	2006-06-19 18:16:12.000000000 -0700
+@@ -49,17 +49,13 @@
+ extern void au1000_restart(char *);
+ extern void au1000_halt(void);
+ extern void au1000_power_off(void);
+-extern struct resource ioport_resource;
+-extern struct resource iomem_resource;
+-extern void (*board_time_init)(void);
+ extern void au1x_time_init(void);
+-extern void (*board_timer_setup)(struct irqaction *irq);
+ extern void au1x_timer_setup(struct irqaction *irq);
+ extern void au1xxx_time_init(void);
+ extern void au1xxx_timer_setup(struct irqaction *irq);
+ extern void set_cpuspec(void);
+ 
+-void __init plat_setup(void)
++void __init plat_mem_setup(void)
+ {
+ 	struct	cpu_spec *sp;
+ 	char *argptr;
+diff -Naur linux-2.6.17.orig/arch/mips/au1000/common/time.c linux-2.6.17/arch/mips/au1000/common/time.c
+--- linux-2.6.17.orig/arch/mips/au1000/common/time.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/au1000/common/time.c	2006-06-19 18:16:12.000000000 -0700
+@@ -50,10 +50,6 @@
+ #include <linux/mc146818rtc.h>
+ #include <linux/timex.h>
+ 
+-extern void do_softirq(void);
+-extern volatile unsigned long wall_jiffies;
+-unsigned long missed_heart_beats = 0;
+-
+ static unsigned long r4k_offset; /* Amount to increment compare reg each time */
+ static unsigned long r4k_cur;    /* What counter should be at next timer irq */
+ int	no_au1xxx_32khz;
+@@ -388,10 +384,9 @@
+ }
+ #endif
+ 
+-void au1xxx_timer_setup(struct irqaction *irq)
++void __init au1xxx_timer_setup(struct irqaction *irq)
+ {
+-        unsigned int est_freq;
+-	extern unsigned long (*do_gettimeoffset)(void);
++	unsigned int est_freq;
+ 
+ 	printk("calculating r4koff... ");
+ 	r4k_offset = cal_r4koff();
+diff -Naur linux-2.6.17.orig/arch/mips/au1000/csb250/irqmap.c linux-2.6.17/arch/mips/au1000/csb250/irqmap.c
+--- linux-2.6.17.orig/arch/mips/au1000/csb250/irqmap.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/au1000/csb250/irqmap.c	2006-06-19 18:16:12.000000000 -0700
+@@ -47,7 +47,7 @@
+ #include <asm/system.h>
+ #include <asm/au1000.h>
+ 
+-au1xxx_irq_map_t au1xxx_irq_map[] = {
++au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
+ 
+ 	{ AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0},
+ 	{ AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 },
+@@ -57,4 +57,4 @@
+ 	{ AU1500_GPIO_207, INTC_INT_LOW_LEVEL, 0 },
+ };
+ 
+-int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t);
++int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
+diff -Naur linux-2.6.17.orig/arch/mips/au1000/db1x00/irqmap.c linux-2.6.17/arch/mips/au1000/db1x00/irqmap.c
+--- linux-2.6.17.orig/arch/mips/au1000/db1x00/irqmap.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/au1000/db1x00/irqmap.c	2006-06-19 18:16:12.000000000 -0700
+@@ -80,7 +80,7 @@
+ #endif
+ 
+ 
+-au1xxx_irq_map_t au1xxx_irq_map[] = {
++au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
+ 
+ #ifndef CONFIG_MIPS_MIRAGE
+ #ifdef CONFIG_MIPS_DB1550
+@@ -101,4 +101,4 @@
+ 
+ };
+ 
+-int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t);
++int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
+diff -Naur linux-2.6.17.orig/arch/mips/au1000/hydrogen3/irqmap.c linux-2.6.17/arch/mips/au1000/hydrogen3/irqmap.c
+--- linux-2.6.17.orig/arch/mips/au1000/hydrogen3/irqmap.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/au1000/hydrogen3/irqmap.c	2006-06-19 18:16:12.000000000 -0700
+@@ -47,10 +47,10 @@
+ #include <asm/system.h>
+ #include <asm/au1000.h>
+ 
+-au1xxx_irq_map_t au1xxx_irq_map[] = {
++au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
+ 
+ 	/* { AU1500_GPIO_205, INTC_INT_LOW_LEVEL, 0 }, */
+ 	{ AU1000_GPIO_21, INTC_INT_LOW_LEVEL, 0 },
+ };
+ 
+-int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t);
++int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
+diff -Naur linux-2.6.17.orig/arch/mips/au1000/mtx-1/irqmap.c linux-2.6.17/arch/mips/au1000/mtx-1/irqmap.c
+--- linux-2.6.17.orig/arch/mips/au1000/mtx-1/irqmap.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/au1000/mtx-1/irqmap.c	2006-06-19 18:16:12.000000000 -0700
+@@ -58,7 +58,7 @@
+  [7] = { -1, INTD, INTC, INTX, INTX},   /* IDSEL 07 - AdapterD-Slot1 (bottom) */
+ };
+ 
+-au1xxx_irq_map_t au1xxx_irq_map[] = {
++au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
+        { AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0},
+        { AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 },
+        { AU1500_GPIO_202, INTC_INT_LOW_LEVEL, 0 },
+@@ -66,4 +66,4 @@
+        { AU1500_GPIO_205, INTC_INT_LOW_LEVEL, 0 },
+ };
+ 
+-int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t);
++int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
+diff -Naur linux-2.6.17.orig/arch/mips/au1000/pb1000/irqmap.c linux-2.6.17/arch/mips/au1000/pb1000/irqmap.c
+--- linux-2.6.17.orig/arch/mips/au1000/pb1000/irqmap.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/au1000/pb1000/irqmap.c	2006-06-19 18:16:12.000000000 -0700
+@@ -47,8 +47,8 @@
+ #include <asm/system.h>
+ #include <asm/mach-au1x00/au1000.h>
+ 
+-au1xxx_irq_map_t au1xxx_irq_map[] = {
++au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
+ 	{ AU1000_GPIO_15, INTC_INT_LOW_LEVEL, 0 },
+ };
+ 
+-int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t);
++int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
+diff -Naur linux-2.6.17.orig/arch/mips/au1000/pb1100/irqmap.c linux-2.6.17/arch/mips/au1000/pb1100/irqmap.c
+--- linux-2.6.17.orig/arch/mips/au1000/pb1100/irqmap.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/au1000/pb1100/irqmap.c	2006-06-19 18:16:12.000000000 -0700
+@@ -47,11 +47,11 @@
+ #include <asm/system.h>
+ #include <asm/mach-au1x00/au1000.h>
+ 
+-au1xxx_irq_map_t au1xxx_irq_map[] = {
++au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
+ 	{ AU1000_GPIO_9, INTC_INT_LOW_LEVEL, 0 }, // PCMCIA Card Fully_Interted#
+ 	{ AU1000_GPIO_10, INTC_INT_LOW_LEVEL, 0 }, // PCMCIA Card STSCHG#
+ 	{ AU1000_GPIO_11, INTC_INT_LOW_LEVEL, 0 }, // PCMCIA Card IRQ#
+ 	{ AU1000_GPIO_13, INTC_INT_LOW_LEVEL, 0 }, // DC_IRQ#
+ };
+ 
+-int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t);
++int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
+diff -Naur linux-2.6.17.orig/arch/mips/au1000/pb1200/irqmap.c linux-2.6.17/arch/mips/au1000/pb1200/irqmap.c
+--- linux-2.6.17.orig/arch/mips/au1000/pb1200/irqmap.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/au1000/pb1200/irqmap.c	2006-06-19 18:16:12.000000000 -0700
+@@ -55,11 +55,11 @@
+ #define PB1200_INT_END DB1200_INT_END
+ #endif
+ 
+-au1xxx_irq_map_t au1xxx_irq_map[] = {
++au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
+ 	{ AU1000_GPIO_7, INTC_INT_LOW_LEVEL, 0 }, // This is exteranl interrupt cascade
+ };
+ 
+-int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t);
++int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
+ 
+ /*
+  *	Support for External interrupts on the PbAu1200 Development platform.
+diff -Naur linux-2.6.17.orig/arch/mips/au1000/pb1500/irqmap.c linux-2.6.17/arch/mips/au1000/pb1500/irqmap.c
+--- linux-2.6.17.orig/arch/mips/au1000/pb1500/irqmap.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/au1000/pb1500/irqmap.c	2006-06-19 18:16:12.000000000 -0700
+@@ -52,7 +52,7 @@
+  [13] = { -1, INTA, INTB, INTC, INTD},   /* IDSEL 13 - PCI slot */
+ };
+ 
+-au1xxx_irq_map_t au1xxx_irq_map[] = {
++au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
+ 	{ AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0},
+ 	{ AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 },
+ 	{ AU1500_GPIO_202, INTC_INT_LOW_LEVEL, 0 },
+@@ -60,4 +60,4 @@
+ 	{ AU1500_GPIO_205, INTC_INT_LOW_LEVEL, 0 },
+ };
+ 
+-int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t);
++int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
+diff -Naur linux-2.6.17.orig/arch/mips/au1000/pb1550/irqmap.c linux-2.6.17/arch/mips/au1000/pb1550/irqmap.c
+--- linux-2.6.17.orig/arch/mips/au1000/pb1550/irqmap.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/au1000/pb1550/irqmap.c	2006-06-19 18:16:12.000000000 -0700
+@@ -52,9 +52,9 @@
+  [13] =	{ -1, INTA, INTB, INTC, INTD},   /* IDSEL 13 - PCI slot 1 (right) */
+ };
+ 
+-au1xxx_irq_map_t au1xxx_irq_map[] = {
++au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
+ 	{ AU1000_GPIO_0, INTC_INT_LOW_LEVEL, 0 },
+ 	{ AU1000_GPIO_1, INTC_INT_LOW_LEVEL, 0 },
+ };
+ 
+-int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t);
++int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
+diff -Naur linux-2.6.17.orig/arch/mips/au1000/xxs1500/irqmap.c linux-2.6.17/arch/mips/au1000/xxs1500/irqmap.c
+--- linux-2.6.17.orig/arch/mips/au1000/xxs1500/irqmap.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/au1000/xxs1500/irqmap.c	2006-06-19 18:16:12.000000000 -0700
+@@ -47,7 +47,7 @@
+ #include <asm/system.h>
+ #include <asm/au1000.h>
+ 
+-au1xxx_irq_map_t au1xxx_irq_map[] = {
++au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
+ 	{ AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0},
+ 	{ AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 },
+ 	{ AU1500_GPIO_202, INTC_INT_LOW_LEVEL, 0 },
+@@ -63,4 +63,4 @@
+ 	{ AU1000_GPIO_5, INTC_INT_LOW_LEVEL, 0 },
+ };
+ 
+-int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t);
++int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
+diff -Naur linux-2.6.17.orig/arch/mips/basler/excite/excite_dbg_io.c linux-2.6.17/arch/mips/basler/excite/excite_dbg_io.c
+--- linux-2.6.17.orig/arch/mips/basler/excite/excite_dbg_io.c	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/arch/mips/basler/excite/excite_dbg_io.c	2006-06-19 18:16:12.000000000 -0700
+@@ -0,0 +1,122 @@
++/*
++ *  Copyright (C) 2004 by Basler Vision Technologies AG
++ *  Author: Thomas Koeller <thomas.koeller@baslerweb.com>
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License as published by
++ *  the Free Software Foundation; either version 2 of the License, or
++ *  (at your option) any later version.
++ *
++ *  This program is distributed in the hope that it will be useful,
++ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *  GNU General Public License for more details.
++ *
++ *  You should have received a copy of the GNU General Public License
++ *  along with this program; if not, write to the Free Software
++ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
++ */
++
++#include <linux/config.h>
++#include <linux/linkage.h>
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <asm/gdb-stub.h>
++#include <asm/rm9k-ocd.h>
++#include <excite.h>
++
++#if defined(CONFIG_SERIAL_8250) && CONFIG_SERIAL_8250_NR_UARTS > 1
++#error Debug port used by serial driver
++#endif
++
++#define UART_CLK		25000000
++#define BASE_BAUD		(UART_CLK / 16)
++#define REGISTER_BASE_0		0x0208UL
++#define REGISTER_BASE_1		0x0238UL
++
++#define REGISTER_BASE_DBG	REGISTER_BASE_1
++
++#define CPRR	0x0004
++#define UACFG	0x0200
++#define UAINTS	0x0204
++#define UARBR	(REGISTER_BASE_DBG + 0x0000)
++#define UATHR	(REGISTER_BASE_DBG + 0x0004)
++#define UADLL	(REGISTER_BASE_DBG + 0x0008)
++#define UAIER	(REGISTER_BASE_DBG + 0x000c)
++#define UADLH	(REGISTER_BASE_DBG + 0x0010)
++#define UAIIR	(REGISTER_BASE_DBG + 0x0014)
++#define UAFCR	(REGISTER_BASE_DBG + 0x0018)
++#define UALCR	(REGISTER_BASE_DBG + 0x001c)
++#define UAMCR	(REGISTER_BASE_DBG + 0x0020)
++#define UALSR	(REGISTER_BASE_DBG + 0x0024)
++#define UAMSR	(REGISTER_BASE_DBG + 0x0028)
++#define UASCR	(REGISTER_BASE_DBG + 0x002c)
++
++#define	PARITY_NONE	0
++#define	PARITY_ODD	0x08
++#define	PARITY_EVEN	0x18
++#define	PARITY_MARK	0x28
++#define	PARITY_SPACE	0x38
++
++#define	DATA_5BIT	0x0
++#define	DATA_6BIT	0x1
++#define	DATA_7BIT	0x2
++#define	DATA_8BIT	0x3
++
++#define	STOP_1BIT	0x0
++#define	STOP_2BIT	0x4
++
++#define BAUD_DBG	57600
++#define	PARITY_DBG	PARITY_NONE
++#define	DATA_DBG	DATA_8BIT
++#define	STOP_DBG	STOP_1BIT
++
++/* Initialize the serial port for KGDB debugging */
++void __init excite_kgdb_init(void)
++{
++	const u32 divisor = BASE_BAUD / BAUD_DBG;
++
++	/* Take the UART out of reset */
++	titan_writel(0x00ff1cff, CPRR);
++	titan_writel(0x00000000, UACFG);
++	titan_writel(0x00000002, UACFG);
++
++	titan_writel(0x0, UALCR);
++	titan_writel(0x0, UAIER);
++
++	/* Disable FIFOs */
++	titan_writel(0x00, UAFCR);
++
++	titan_writel(0x80, UALCR);
++	titan_writel(divisor & 0xff, UADLL);
++	titan_writel((divisor & 0xff00) >> 8, UADLH);
++	titan_writel(0x0, UALCR);
++
++	titan_writel(DATA_DBG | PARITY_DBG | STOP_DBG, UALCR);
++
++	/* Enable receiver interrupt */
++	titan_readl(UARBR);
++	titan_writel(0x1, UAIER);
++}
++
++int getDebugChar(void)
++{
++	while (!(titan_readl(UALSR) & 0x1));
++	return titan_readl(UARBR);
++}
++
++int putDebugChar(int data)
++{
++	while (!(titan_readl(UALSR) & 0x20));
++	titan_writel(data, UATHR);
++	return 1;
++}
++
++/* KGDB interrupt handler */
++asmlinkage void excite_kgdb_inthdl(struct pt_regs *regs)
++{
++	if (unlikely(
++		((titan_readl(UAIIR) & 0x7) == 4)
++		&& ((titan_readl(UARBR) & 0xff) == 0x3)))
++			set_async_breakpoint(&regs->cp0_epc);
++}
+diff -Naur linux-2.6.17.orig/arch/mips/basler/excite/excite_device.c linux-2.6.17/arch/mips/basler/excite/excite_device.c
+--- linux-2.6.17.orig/arch/mips/basler/excite/excite_device.c	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/arch/mips/basler/excite/excite_device.c	2006-06-19 18:16:12.000000000 -0700
+@@ -0,0 +1,404 @@
++/*
++ *  Copyright (C) 2004 by Basler Vision Technologies AG
++ *  Author: Thomas Koeller <thomas.koeller@baslerweb.com>
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License as published by
++ *  the Free Software Foundation; either version 2 of the License, or
++ *  (at your option) any later version.
++ *
++ *  This program is distributed in the hope that it will be useful,
++ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *  GNU General Public License for more details.
++ *
++ *  You should have received a copy of the GNU General Public License
++ *  along with this program; if not, write to the Free Software
++ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
++ */
++
++#include <linux/config.h>
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <linux/ioport.h>
++#include <linux/err.h>
++#include <linux/jiffies.h>
++#include <linux/sched.h>
++#include <asm/types.h>
++#include <asm/rm9k-ocd.h>
++
++#include <excite.h>
++#include <rm9k_eth.h>
++#include <rm9k_wdt.h>
++#include <rm9k_xicap.h>
++#include <excite_nandflash.h>
++
++#include "excite_iodev.h"
++
++#define RM9K_GE_UNIT	0
++#define XICAP_UNIT	0
++#define NAND_UNIT	0
++
++#define DLL_TIMEOUT	3		/* seconds */
++
++
++#define RINIT(__start__, __end__, __name__, __parent__) {	\
++	.name	= __name__ "_0",				\
++	.start	= (__start__),					\
++	.end	= (__end__),					\
++	.flags	= 0,						\
++	.parent	= (__parent__)					\
++}
++
++#define RINIT_IRQ(__irq__, __name__) {	\
++	.name	= __name__ "_0",	\
++	.start	= (__irq__),		\
++	.end	= (__irq__),		\
++	.flags	= IORESOURCE_IRQ,	\
++	.parent	= NULL			\
++}
++
++
++
++enum {
++	slice_xicap,
++	slice_eth
++};
++
++
++
++static struct resource
++	excite_ctr_resource = {
++		.name		= "GPI counters",
++		.start		= 0,
++		.end		= 5,
++		.flags		= 0,
++		.parent		= NULL,
++		.sibling	= NULL,
++		.child		= NULL
++	},
++	excite_gpislice_resource = {
++		.name		= "GPI slices",
++		.start		= 0,
++		.end		= 1,
++		.flags		= 0,
++		.parent		= NULL,
++		.sibling	= NULL,
++		.child		= NULL
++	},
++	excite_mdio_channel_resource = {
++		.name		= "MDIO channels",
++		.start		= 0,
++		.end		= 1,
++		.flags		= 0,
++		.parent		= NULL,
++		.sibling	= NULL,
++		.child		= NULL
++	},
++	excite_fifomem_resource = {
++		.name		= "FIFO memory",
++		.start		= 0,
++		.end		= 767,
++		.flags		= 0,
++		.parent		= NULL,
++		.sibling	= NULL,
++		.child		= NULL
++	},
++	excite_scram_resource = {
++		.name		= "Scratch RAM",
++		.start		= EXCITE_PHYS_SCRAM,
++		.end		= EXCITE_PHYS_SCRAM + EXCITE_SIZE_SCRAM - 1,
++		.flags		= IORESOURCE_MEM,
++		.parent		= NULL,
++		.sibling	= NULL,
++		.child		= NULL
++	},
++	excite_fpga_resource = {
++		.name		= "System FPGA",
++		.start		= EXCITE_PHYS_FPGA,
++		.end		= EXCITE_PHYS_FPGA + EXCITE_SIZE_FPGA - 1,
++		.flags		= IORESOURCE_MEM,
++		.parent		= NULL,
++		.sibling	= NULL,
++		.child		= NULL
++	},
++	excite_nand_resource = {
++		.name		= "NAND flash control",
++		.start		= EXCITE_PHYS_NAND,
++		.end		= EXCITE_PHYS_NAND + EXCITE_SIZE_NAND - 1,
++		.flags		= IORESOURCE_MEM,
++		.parent		= NULL,
++		.sibling	= NULL,
++		.child		= NULL
++	},
++	excite_titan_resource = {
++		.name		= "TITAN registers",
++		.start		= EXCITE_PHYS_TITAN,
++		.end		= EXCITE_PHYS_TITAN + EXCITE_SIZE_TITAN - 1,
++		.flags		= IORESOURCE_MEM,
++		.parent		= NULL,
++		.sibling	= NULL,
++		.child		= NULL
++	};
++
++
++
++static void adjust_resources(struct resource *res, unsigned int n)
++{
++	struct resource *p;
++	const unsigned long mask = IORESOURCE_IO | IORESOURCE_MEM
++				   | IORESOURCE_IRQ | IORESOURCE_DMA;
++
++	for (p = res; p < res + n; p++) {
++		const struct resource * const parent = p->parent;
++		if (parent) {
++			p->start += parent->start;
++			p->end   += parent->start;
++			p->flags =  parent->flags & mask;
++		}
++	}
++}
++
++
++
++#if defined(CONFIG_EXCITE_FCAP_GPI) || defined(CONFIG_EXCITE_FCAP_GPI_MODULE)
++static struct resource xicap_rsrc[] = {
++	RINIT(0x4840, 0x486f, XICAP_RESOURCE_FIFO_RX, &excite_titan_resource),
++	RINIT(0x4940, 0x494b, XICAP_RESOURCE_FIFO_TX, &excite_titan_resource),
++	RINIT(0x5040, 0x5127, XICAP_RESOURCE_XDMA, &excite_titan_resource),
++	RINIT(0x1000, 0x112f, XICAP_RESOURCE_PKTPROC, &excite_titan_resource),
++	RINIT(0x1100, 0x110f, XICAP_RESOURCE_PKT_STREAM, &excite_fpga_resource),
++	RINIT(0x0800, 0x0bff, XICAP_RESOURCE_DMADESC, &excite_scram_resource),
++	RINIT(slice_xicap, slice_xicap, XICAP_RESOURCE_GPI_SLICE, &excite_gpislice_resource),
++	RINIT(0x0100, 0x02ff, XICAP_RESOURCE_FIFO_BLK, &excite_fifomem_resource),
++	RINIT_IRQ(TITAN_IRQ,  XICAP_RESOURCE_IRQ)
++};
++
++static struct platform_device xicap_pdev = {
++	.name		= XICAP_NAME,
++	.id		= XICAP_UNIT,
++	.num_resources	= ARRAY_SIZE(xicap_rsrc),
++	.resource	= xicap_rsrc
++};
++
++/*
++ * Create a platform device for the GPI port that receives the
++ * image data from the embedded camera.
++ */
++static int __init xicap_devinit(void)
++{
++	unsigned long tend;
++	u32 reg;
++	int retval;
++
++	adjust_resources(xicap_rsrc, ARRAY_SIZE(xicap_rsrc));
++
++	/* Power up the slice and configure it. */
++	reg = titan_readl(CPTC1R);
++	reg &= ~(0x11100 << slice_xicap);
++	titan_writel(reg, CPTC1R);
++
++	/* Enable slice & DLL. */
++	reg= titan_readl(CPRR);
++	reg &= ~(0x00030003 << (slice_xicap * 2));
++	titan_writel(reg, CPRR);
++
++	/* Wait for DLLs to lock */
++	tend = jiffies + DLL_TIMEOUT * HZ;
++	while (time_before(jiffies, tend)) {
++		if (!(~titan_readl(CPDSR) & (0x1 << (slice_xicap * 4))))
++			break;
++		yield();
++	}
++
++	if (~titan_readl(CPDSR) & (0x1 << (slice_xicap * 4))) {
++		printk(KERN_ERR "%s: DLL not locked after %u seconds\n",
++		       xicap_pdev.name, DLL_TIMEOUT);
++		retval = -ETIME;
++	} else {
++		/* Register platform device */
++		retval = platform_device_register(&xicap_pdev);
++	}
++
++	return retval;
++}
++
++device_initcall(xicap_devinit);
++#endif /* defined(CONFIG_EXCITE_FCAP_GPI) || defined(CONFIG_EXCITE_FCAP_GPI_MODULE) */
++
++
++
++#if defined(CONFIG_WDT_RM9K_GPI) || defined(CONFIG_WDT_RM9K_GPI_MODULE)
++static struct resource wdt_rsrc[] = {
++	RINIT(0, 0, WDT_RESOURCE_COUNTER, &excite_ctr_resource),
++	RINIT(0x0084, 0x008f, WDT_RESOURCE_REGS, &excite_titan_resource),
++	RINIT_IRQ(TITAN_IRQ,  WDT_RESOURCE_IRQ)
++};
++
++static struct platform_device wdt_pdev = {
++	.name		= WDT_NAME,
++	.id		= -1,
++	.num_resources	= ARRAY_SIZE(wdt_rsrc),
++	.resource	= wdt_rsrc
++};
++
++/*
++ * Create a platform device for the GPI port that receives the
++ * image data from the embedded camera.
++ */
++static int __init wdt_devinit(void)
++{
++	adjust_resources(wdt_rsrc, ARRAY_SIZE(wdt_rsrc));
++	return platform_device_register(&wdt_pdev);
++}
++
++device_initcall(wdt_devinit);
++#endif /* defined(CONFIG_WDT_RM9K_GPI) || defined(CONFIG_WDT_RM9K_GPI_MODULE) */
++
++
++
++static struct resource excite_nandflash_rsrc[] = {
++ 	RINIT(0x2000, 0x201f, EXCITE_NANDFLASH_RESOURCE_REGS,  &excite_nand_resource)
++};
++
++static struct platform_device excite_nandflash_pdev = {
++	.name		= "excite_nand",
++	.id		= NAND_UNIT,
++	.num_resources	= ARRAY_SIZE(excite_nandflash_rsrc),
++	.resource	= excite_nandflash_rsrc
++};
++
++/*
++ * Create a platform device for the access to the nand-flash
++ * port
++ */
++static int __init excite_nandflash_devinit(void)
++{
++	adjust_resources(excite_nandflash_rsrc, ARRAY_SIZE(excite_nandflash_rsrc));
++
++        /* nothing to be done here */
++
++        /* Register platform device */
++	return platform_device_register(&excite_nandflash_pdev);
++}
++
++device_initcall(excite_nandflash_devinit);
++
++
++
++static struct resource iodev_rsrc[] = {
++	RINIT_IRQ(FPGA1_IRQ,  IODEV_RESOURCE_IRQ)
++};
++
++static struct platform_device io_pdev = {
++	.name		= IODEV_NAME,
++	.id		= -1,
++	.num_resources	= ARRAY_SIZE(iodev_rsrc),
++	.resource	= iodev_rsrc
++};
++
++/*
++ * Create a platform device for the external I/O ports.
++ */
++static int __init io_devinit(void)
++{
++	adjust_resources(iodev_rsrc, ARRAY_SIZE(iodev_rsrc));
++	return platform_device_register(&io_pdev);
++}
++
++device_initcall(io_devinit);
++
++
++
++
++#if defined(CONFIG_RM9K_GE) || defined(CONFIG_RM9K_GE_MODULE)
++static struct resource rm9k_ge_rsrc[] = {
++	RINIT(0x2200, 0x27ff, RM9K_GE_RESOURCE_MAC, &excite_titan_resource),
++	RINIT(0x1800, 0x1fff, RM9K_GE_RESOURCE_MSTAT, &excite_titan_resource),
++	RINIT(0x2000, 0x212f, RM9K_GE_RESOURCE_PKTPROC, &excite_titan_resource),
++	RINIT(0x5140, 0x5227, RM9K_GE_RESOURCE_XDMA, &excite_titan_resource),
++	RINIT(0x4870, 0x489f, RM9K_GE_RESOURCE_FIFO_RX, &excite_titan_resource),
++	RINIT(0x494c, 0x4957, RM9K_GE_RESOURCE_FIFO_TX, &excite_titan_resource),
++	RINIT(0x0000, 0x007f, RM9K_GE_RESOURCE_FIFOMEM_RX, &excite_fifomem_resource),
++	RINIT(0x0080, 0x00ff, RM9K_GE_RESOURCE_FIFOMEM_TX, &excite_fifomem_resource),
++	RINIT(0x0180, 0x019f, RM9K_GE_RESOURCE_PHY, &excite_titan_resource),
++	RINIT(0x0000, 0x03ff, RM9K_GE_RESOURCE_DMADESC_RX, &excite_scram_resource),
++	RINIT(0x0400, 0x07ff, RM9K_GE_RESOURCE_DMADESC_TX, &excite_scram_resource),
++	RINIT(slice_eth, slice_eth, RM9K_GE_RESOURCE_GPI_SLICE, &excite_gpislice_resource),
++	RINIT(0, 0, RM9K_GE_RESOURCE_MDIO_CHANNEL, &excite_mdio_channel_resource),
++	RINIT_IRQ(TITAN_IRQ,  RM9K_GE_RESOURCE_IRQ_MAIN),
++	RINIT_IRQ(PHY_IRQ, RM9K_GE_RESOURCE_IRQ_PHY)
++};
++
++static struct platform_device rm9k_ge_pdev = {
++	.name		= RM9K_GE_NAME,
++	.id		= RM9K_GE_UNIT,
++	.num_resources	= ARRAY_SIZE(rm9k_ge_rsrc),
++	.resource	= rm9k_ge_rsrc
++};
++
++
++
++/*
++ * Create a platform device for the Ethernet port.
++ */
++static int __init rm9k_ge_devinit(void)
++{
++	u32 reg;
++
++	adjust_resources(rm9k_ge_rsrc, ARRAY_SIZE(rm9k_ge_rsrc));
++
++	/* Power up the slice and configure it. */
++	reg = titan_readl(CPTC1R);
++	reg &= ~(0x11000 << slice_eth);
++	reg |= 0x100 << slice_eth;
++	titan_writel(reg, CPTC1R);
++
++	/* Take the MAC out of reset, reset the DLLs. */
++	reg = titan_readl(CPRR);
++	reg &= ~(0x00030000 << (slice_eth * 2));
++	reg |= 0x3 << (slice_eth * 2);
++	titan_writel(reg, CPRR);
++
++	return platform_device_register(&rm9k_ge_pdev);
++}
++
++device_initcall(rm9k_ge_devinit);
++#endif /* defined(CONFIG_RM9K_GE) || defined(CONFIG_RM9K_GE_MODULE) */
++
++
++
++static int __init excite_setup_devs(void)
++{
++	int res;
++	u32 reg;
++
++	/* Enable xdma and fifo interrupts */
++	reg = titan_readl(0x0050);
++	titan_writel(reg | 0x18000000, 0x0050);
++
++	res = request_resource(&iomem_resource, &excite_titan_resource);
++	if (res)
++		return res;
++	res = request_resource(&iomem_resource, &excite_scram_resource);
++	if (res)
++		return res;
++	res = request_resource(&iomem_resource, &excite_fpga_resource);
++	if (res)
++		return res;
++	res = request_resource(&iomem_resource, &excite_nand_resource);
++	if (res)
++		return res;
++	excite_fpga_resource.flags = excite_fpga_resource.parent->flags &
++				   ( IORESOURCE_IO | IORESOURCE_MEM
++				   | IORESOURCE_IRQ | IORESOURCE_DMA);
++	excite_nand_resource.flags = excite_nand_resource.parent->flags &
++				   ( IORESOURCE_IO | IORESOURCE_MEM
++				   | IORESOURCE_IRQ | IORESOURCE_DMA);
++
++	return 0;
++}
++
++arch_initcall(excite_setup_devs);
++
+diff -Naur linux-2.6.17.orig/arch/mips/basler/excite/excite_flashtest.c linux-2.6.17/arch/mips/basler/excite/excite_flashtest.c
+--- linux-2.6.17.orig/arch/mips/basler/excite/excite_flashtest.c	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/arch/mips/basler/excite/excite_flashtest.c	2006-06-19 18:16:12.000000000 -0700
+@@ -0,0 +1,294 @@
++/*
++*  Copyright (C) 2005 by Basler Vision Technologies AG
++*  Author: Thies Moeller <thies.moeller@baslerweb.com>
++*
++*  This program is free software; you can redistribute it and/or modify
++*  it under the terms of the GNU General Public License as published by
++*  the Free Software Foundation; either version 2 of the License, or
++*  (at your option) any later version.
++*
++*  This program is distributed in the hope that it will be useful,
++*  but WITHOUT ANY WARRANTY; without even the implied warranty of
++*  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++*  GNU General Public License for more details.
++*
++*  You should have received a copy of the GNU General Public License
++*  along with this program; if not, write to the Free Software
++*  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
++*/
++
++#include <linux/module.h>
++#include <linux/types.h>
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/string.h>
++#include <linux/ioport.h>
++#include <linux/device.h>
++#include <linux/delay.h>
++#include <linux/err.h>
++#include <linux/kernel.h>
++
++#include <excite.h>
++
++#include <asm/io.h>
++
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/nand.h>
++#include <linux/mtd/nand_ecc.h>
++#include <linux/mtd/partitions.h>
++#include <asm/rm9k-ocd.h> // for ocd_write
++#include <linux/workqueue.h> // for queue
++
++#include "excite_nandflash.h"
++#include "nandflash.h"
++
++#define PFX "excite flashtest: "
++typedef void __iomem *io_reg_t;
++
++#define io_readb(__a__)		__raw_readb((__a__))
++#define io_writeb(__v__, __a__)	__raw_writeb((__v__), (__a__))
++
++
++
++static inline const struct resource *excite_nandflash_get_resource(
++	struct platform_device *d, unsigned long flags, const char *basename)
++{
++	const char fmt[] = "%s_%u";
++	char buf[80];
++
++	if (unlikely(snprintf(buf, sizeof buf, fmt, basename, d->id) >= sizeof buf))
++		return NULL;
++
++	return platform_get_resource_byname(d, flags, buf);
++}
++
++static inline io_reg_t
++excite_nandflash_map_regs(struct platform_device *d, const char *basename)
++{
++	void *result = NULL;
++	const struct resource *const r =
++	    excite_nandflash_get_resource(d, IORESOURCE_MEM, basename);
++	if (r)
++	   result = ioremap_nocache(r->start, r->end + 1 - r->start);
++	return result;
++}
++
++/* controller and mtd information */
++
++struct excite_nandflash_drvdata {
++	struct mtd_info board_mtd;
++	struct nand_chip board_chip;
++	io_reg_t regs;
++};
++
++
++/* command and control functions */
++static void excite_nandflash_hwcontrol(struct mtd_info *mtd, int cmd)
++{
++	struct nand_chip *this = mtd->priv;
++	io_reg_t regs = container_of(mtd,struct excite_nandflash_drvdata,board_mtd)->regs;
++
++	switch (cmd) {
++	/* Select the command latch */
++	case NAND_CTL_SETCLE: this->IO_ADDR_W = regs + EXCITE_NANDFLASH_CMD;
++		break;
++	/* Deselect the command latch */
++	case NAND_CTL_CLRCLE: this->IO_ADDR_W = regs + EXCITE_NANDFLASH_DATA;
++		break;
++	/* Select the address latch */
++	case NAND_CTL_SETALE: this->IO_ADDR_W = regs + EXCITE_NANDFLASH_ADDR;
++		break;
++	/* Deselect the address latch */
++	case NAND_CTL_CLRALE: this->IO_ADDR_W = regs  + EXCITE_NANDFLASH_DATA;
++		break;
++	/* Select the chip  -- not used */
++	case NAND_CTL_SETNCE:
++		break;
++	/* Deselect the chip -- not used */
++	case NAND_CTL_CLRNCE:
++		break;
++	}
++
++	this->IO_ADDR_R = this->IO_ADDR_W;
++}
++
++/* excite_nandflash_devready()
++ *
++ * returns 0 if the nand is busy, 1 if it is ready
++ */
++static int excite_nandflash_devready(struct mtd_info *mtd)
++{
++	struct excite_nandflash_drvdata *drvdata =
++	    container_of(mtd, struct excite_nandflash_drvdata, board_mtd);
++
++	return io_readb(drvdata->regs + EXCITE_NANDFLASH_STATUS);
++}
++
++/* device management functions */
++
++/* excite_nandflash_remove
++ *
++ * called by device layer to remove the driver
++ * the binding to the mtd and all allocated
++ * resources are released
++ */
++static int excite_nandflash_remove(struct device *dev)
++{
++	struct excite_nandflash_drvdata *this = dev_get_drvdata(dev);
++
++	pr_info(PFX "remove");
++
++	dev_set_drvdata(dev, NULL);
++
++	if (this == NULL) {
++		pr_debug(PFX "call remove without private data!!");
++		return 0;
++	}
++
++
++	/* free the common resources */
++	if (this->regs != NULL) {
++		iounmap(this->regs);
++		this->regs = NULL;
++	}
++
++	kfree(this);
++
++	return 0;
++}
++
++static int elapsed;
++
++void my_workqueue_handler(void *arg)
++{
++	elapsed = 1;
++}
++
++DECLARE_WORK(sigElapsed, my_workqueue_handler, 0);
++
++
++/* excite_nandflash_probe
++ *
++ * called by device layer when it finds a device matching
++ * one our driver can handled. This code checks to see if
++ * it can allocate all necessary resources then calls the
++ * nand layer to look for devices
++*/
++static int excite_nandflash_probe(struct device *dev)
++{
++	struct platform_device *pdev = to_platform_device(dev);
++
++	struct excite_nandflash_drvdata *drvdata;	    /* private driver data     */
++	struct nand_chip              *board_chip;  /* private flash chip data */
++	struct mtd_info               *board_mtd;   /* mtd info for this board */
++
++	int err      = 0;
++	int count    = 0;
++	struct timeval tv,endtv;
++	unsigned int dt;
++
++	pr_info(PFX "probe dev: (%p)\n", dev);
++
++	pr_info(PFX "adjust LB timing\n");
++	ocd_writel(0x00000330, LDP2);
++
++	drvdata = kmalloc(sizeof(*drvdata), GFP_KERNEL);
++	if (unlikely(!drvdata)) {
++		printk(KERN_ERR PFX "no memory for drvdata\n");
++		err = -ENOMEM;
++		goto mem_error;
++	}
++
++	/* Initialize structures */
++	memset(drvdata, 0, sizeof(*drvdata));
++
++	/* bind private data into driver */
++	dev_set_drvdata(dev, drvdata);
++
++	/* allocate and map the resource */
++	drvdata->regs =
++	    excite_nandflash_map_regs(pdev, EXCITE_NANDFLASH_RESOURCE_REGS);
++
++	if (unlikely(!drvdata->regs)) {
++		printk(KERN_ERR PFX "cannot reserve register region\n");
++		err = -ENXIO;
++		goto io_error;
++	}
++
++	/* initialise our chip */
++	board_chip = &drvdata->board_chip;
++
++	board_chip->IO_ADDR_R = drvdata->regs + EXCITE_NANDFLASH_DATA;
++	board_chip->IO_ADDR_W = drvdata->regs + EXCITE_NANDFLASH_DATA;
++
++	board_chip->hwcontrol = excite_nandflash_hwcontrol;
++	board_chip->dev_ready = excite_nandflash_devready;
++
++	board_chip->chip_delay = 25;
++	#if 0
++	/* TODO: speedup the initial scan */
++	board_chip->options = NAND_USE_FLASH_BBT;
++	#endif
++	board_chip->eccmode = NAND_ECC_SOFT;
++
++	/* link chip to mtd */
++	board_mtd = &drvdata->board_mtd;
++	board_mtd->priv = board_chip;
++
++
++	pr_info(PFX "FlashTest\n");
++	elapsed = 0;
++/*	schedule_delayed_work(&sigElapsed, 1*HZ);
++	while (!elapsed) {
++		io_readb(drvdata->regs + EXCITE_NANDFLASH_STATUS);
++		count++;
++	}
++	pr_info(PFX "reads in 1 sec --> %d\n",count);
++*/
++	do_gettimeofday(&tv);
++	for (count = 0 ; count < 1000000; count ++) {
++		io_readb(drvdata->regs + EXCITE_NANDFLASH_STATUS);
++	}
++	do_gettimeofday(&endtv);
++	dt = (endtv.tv_sec - tv.tv_sec) * 1000000 + endtv.tv_usec  - tv.tv_usec;
++	pr_info(PFX "%8d us timeval\n",dt);
++	pr_info(PFX "EndFlashTest\n");
++
++/*      return with error to unload everything
++*/
++io_error:
++	iounmap(drvdata->regs);
++
++mem_error:
++	kfree(drvdata);
++
++	if (err == 0)
++		err = -EINVAL;
++	return err;
++}
++
++static struct device_driver excite_nandflash_driver = {
++	.name = "excite_nand",
++	.bus = &platform_bus_type,
++	.probe = excite_nandflash_probe,
++	.remove = excite_nandflash_remove,
++};
++
++static int __init excite_nandflash_init(void)
++{
++	pr_info(PFX "register Driver (Rev: $Revision:$)\n");
++	return driver_register(&excite_nandflash_driver);
++}
++
++static void __exit excite_nandflash_exit(void)
++{
++	driver_unregister(&excite_nandflash_driver);
++	pr_info(PFX "Driver unregistered");
++}
++
++module_init(excite_nandflash_init);
++module_exit(excite_nandflash_exit);
++
++MODULE_AUTHOR("Thies Moeller <thies.moeller@baslerweb.com>");
++MODULE_DESCRIPTION("Basler eXcite NAND-Flash driver");
++MODULE_LICENSE("GPL");
+diff -Naur linux-2.6.17.orig/arch/mips/basler/excite/excite_fpga.h linux-2.6.17/arch/mips/basler/excite/excite_fpga.h
+--- linux-2.6.17.orig/arch/mips/basler/excite/excite_fpga.h	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/arch/mips/basler/excite/excite_fpga.h	2006-06-19 18:16:12.000000000 -0700
+@@ -0,0 +1,80 @@
++#ifndef EXCITE_FPGA_H_INCLUDED
++#define EXCITE_FPGA_H_INCLUDED
++
++
++/**
++ * Adress alignment of the individual FPGA bytes.
++ * The address arrangement of the individual bytes of the FPGA is two
++ * byte aligned at the embedded MK2 platform.
++ */
++#ifdef EXCITE_CCI_FPGA_MK2
++typedef unsigned char excite_cci_fpga_align_t __attribute__ ((aligned(2)));
++#else
++typedef unsigned char excite_cci_fpga_align_t;
++#endif
++
++
++/**
++ * Size of Dual Ported RAM.
++ */
++#define EXCITE_DPR_SIZE 263
++
++
++/**
++ * Size of Reserved Status Fields in Dual Ported RAM.
++ */
++#define EXCITE_DPR_STATUS_SIZE 7
++
++
++
++/**
++ * FPGA.
++ * Hardware register layout of the FPGA interface. The FPGA must accessed
++ * byte wise solely.
++ * @see EXCITE_CCI_DPR_MK2
++ */
++typedef struct excite_fpga {
++
++	/**
++	 * Dual Ported RAM.
++	 */
++	excite_cci_fpga_align_t dpr[EXCITE_DPR_SIZE];
++
++	/**
++	 * Status.
++	 */
++	excite_cci_fpga_align_t status[EXCITE_DPR_STATUS_SIZE];
++
++#ifdef EXCITE_CCI_FPGA_MK2
++	/**
++	 * RM9000 Interrupt.
++	 * Write access initiates interrupt at the RM9000 (MIPS) processor of the eXcite.
++	 */
++	excite_cci_fpga_align_t rm9k_int;
++#else
++	/**
++	 * MK2 Interrupt.
++	 * Write access initiates interrupt at the ARM processor of the MK2.
++	 */
++	excite_cci_fpga_align_t mk2_int;
++
++	excite_cci_fpga_align_t gap[0x1000-0x10f];
++
++	/**
++	 * IRQ Source/Acknowledge.
++	 */
++	excite_cci_fpga_align_t rm9k_irq_src;
++
++	/**
++	 * IRQ Mask.
++	 * Set bits enable the related interrupt.
++	 */
++	excite_cci_fpga_align_t rm9k_irq_mask;
++#endif
++
++
++} excite_fpga;
++
++
++
++#endif	/* ndef EXCITE_FPGA_H_INCLUDED */
+diff -Naur linux-2.6.17.orig/arch/mips/basler/excite/excite_iodev.c linux-2.6.17/arch/mips/basler/excite/excite_iodev.c
+--- linux-2.6.17.orig/arch/mips/basler/excite/excite_iodev.c	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/arch/mips/basler/excite/excite_iodev.c	2006-06-19 18:16:12.000000000 -0700
+@@ -0,0 +1,183 @@
++/*
++ *  Copyright (C) 2005 by Basler Vision Technologies AG
++ *  Author: Thomas Koeller <thomas.koeller@baslerweb.com>
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License as published by
++ *  the Free Software Foundation; either version 2 of the License, or
++ *  (at your option) any later version.
++ *
++ *  This program is distributed in the hope that it will be useful,
++ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *  GNU General Public License for more details.
++ *
++ *  You should have received a copy of the GNU General Public License
++ *  along with this program; if not, write to the Free Software
++ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
++ */
++
++#include <linux/config.h>
++#include <linux/compiler.h>
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/sched.h>
++#include <linux/wait.h>
++#include <linux/poll.h>
++#include <linux/interrupt.h>
++#include <linux/platform_device.h>
++#include <linux/miscdevice.h>
++
++#include "excite_iodev.h"
++
++
++
++static const struct resource *iodev_get_resource(struct platform_device *, const char *, unsigned int);
++static int __init iodev_probe(struct device *);
++static int __exit iodev_remove(struct device *);
++static int iodev_open(struct inode *, struct file *);
++static int iodev_release(struct inode *, struct file *);
++static ssize_t iodev_read(struct file *, char __user *, size_t s, loff_t *);
++static unsigned int iodev_poll(struct file *, struct poll_table_struct *);
++static irqreturn_t iodev_irqhdl(int, void *, struct pt_regs *);
++
++
++
++static const char iodev_name[] = "iodev";
++static unsigned int iodev_irq;
++static DECLARE_WAIT_QUEUE_HEAD(wq);
++
++
++
++static struct file_operations fops =
++{
++	.owner		= THIS_MODULE,
++	.open		= iodev_open,
++	.release	= iodev_release,
++	.read		= iodev_read,
++	.poll		= iodev_poll
++};
++
++static struct miscdevice miscdev =
++{
++	.minor		= MISC_DYNAMIC_MINOR,
++	.name		= iodev_name,
++	.fops		= &fops
++};
++
++static struct device_driver iodev_driver =
++{
++	.name		= (char *) iodev_name,
++	.bus		= &platform_bus_type,
++	.owner		= THIS_MODULE,
++	.probe		= iodev_probe,
++	.remove		= __exit_p(iodev_remove)
++};
++
++
++
++static const struct resource *
++iodev_get_resource(struct platform_device *pdv, const char *name,
++		     unsigned int type)
++{
++	char buf[80];
++	if (snprintf(buf, sizeof buf, "%s_0", name) >= sizeof buf)
++		return NULL;
++	return platform_get_resource_byname(pdv, type, buf);
++}
++
++
++
++/* No hotplugging on the platform bus - use __init */
++static int __init iodev_probe(struct device *dev)
++{
++	struct platform_device * const pdv = to_platform_device(dev);
++	const struct resource * const ri =
++		iodev_get_resource(pdv, IODEV_RESOURCE_IRQ, IORESOURCE_IRQ);
++
++	if (unlikely(!ri))
++		return -ENXIO;
++
++	iodev_irq = ri->start;
++	return misc_register(&miscdev);
++}
++
++
++
++static int __exit iodev_remove(struct device *dev)
++{
++	return misc_deregister(&miscdev);
++}
++
++
++
++static int iodev_open(struct inode *i, struct file *f)
++{
++	return request_irq(iodev_irq, iodev_irqhdl, SA_INTERRUPT,
++			   iodev_name, &miscdev);
++}
++
++
++
++static int iodev_release(struct inode *i, struct file *f)
++{
++	free_irq(iodev_irq, &miscdev);
++	return 0;
++}
++
++
++
++
++static ssize_t
++iodev_read(struct file *f, char __user *d, size_t s, loff_t *o)
++{
++	ssize_t ret;
++	DEFINE_WAIT(w);
++
++	prepare_to_wait(&wq, &w, TASK_INTERRUPTIBLE);
++	if (!signal_pending(current))
++		schedule();
++	ret = signal_pending(current) ? -ERESTARTSYS : 0;
++	finish_wait(&wq, &w);
++	return ret;
++}
++
++
++static unsigned int iodev_poll(struct file *f, struct poll_table_struct *p)
++{
++	poll_wait(f, &wq, p);
++	return POLLOUT | POLLWRNORM;
++}
++
++
++
++
++static irqreturn_t iodev_irqhdl(int irq, void *ctxt, struct pt_regs *regs)
++{
++	wake_up(&wq);
++	return IRQ_HANDLED;
++}
++
++
++
++static int __init iodev_init_module(void)
++{
++	return driver_register(&iodev_driver);
++}
++
++
++
++static void __exit iodev_cleanup_module(void)
++{
++	driver_unregister(&iodev_driver);
++}
++
++module_init(iodev_init_module);
++module_exit(iodev_cleanup_module);
++
++
++
++MODULE_AUTHOR("Thomas Koeller <thomas.koeller@baslerweb.com>");
++MODULE_DESCRIPTION("Basler eXcite i/o interrupt handler");
++MODULE_VERSION("0.0");
++MODULE_LICENSE("GPL");
+diff -Naur linux-2.6.17.orig/arch/mips/basler/excite/excite_iodev.h linux-2.6.17/arch/mips/basler/excite/excite_iodev.h
+--- linux-2.6.17.orig/arch/mips/basler/excite/excite_iodev.h	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/arch/mips/basler/excite/excite_iodev.h	2006-06-19 18:16:12.000000000 -0700
+@@ -0,0 +1,10 @@
++#ifndef __EXCITE_IODEV_H__
++#define __EXCITE_IODEV_H__
++
++/* Device name */
++#define IODEV_NAME		"iodev"
++
++/* Resource names */
++#define IODEV_RESOURCE_IRQ	"excite_iodev_irq"
++
++#endif /* __EXCITE_IODEV_H__ */
+diff -Naur linux-2.6.17.orig/arch/mips/basler/excite/excite_irq.c linux-2.6.17/arch/mips/basler/excite/excite_irq.c
+--- linux-2.6.17.orig/arch/mips/basler/excite/excite_irq.c	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/arch/mips/basler/excite/excite_irq.c	2006-06-19 18:16:12.000000000 -0700
+@@ -0,0 +1,129 @@
++/*
++ *  Copyright (C) by Basler Vision Technologies AG
++ *  Author: Thomas Koeller <thomas.koeller@baslereb.com>
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License as published by
++ *  the Free Software Foundation; either version 2 of the License, or
++ *  (at your option) any later version.
++ *
++ *  This program is distributed in the hope that it will be useful,
++ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *  GNU General Public License for more details.
++ *
++ *  You should have received a copy of the GNU General Public License
++ *  along with this program; if not, write to the Free Software
++ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
++ */
++
++#include <linux/errno.h>
++#include <linux/init.h>
++#include <linux/kernel_stat.h>
++#include <linux/module.h>
++#include <linux/signal.h>
++#include <linux/sched.h>
++#include <linux/types.h>
++#include <linux/interrupt.h>
++#include <linux/ioport.h>
++#include <linux/timex.h>
++#include <linux/slab.h>
++#include <linux/random.h>
++#include <asm/bitops.h>
++#include <asm/bootinfo.h>
++#include <asm/io.h>
++#include <asm/irq.h>
++#include <asm/irq_cpu.h>
++#include <asm/mipsregs.h>
++#include <asm/system.h>
++#include <asm/rm9k-ocd.h>
++
++#include <excite.h>
++
++extern asmlinkage void excite_handle_int(void);
++
++/*
++ * Initialize the interrupt handler
++ */
++void __init arch_init_irq(void)
++{
++	mips_cpu_irq_init(0);
++	rm7k_cpu_irq_init(8);
++	rm9k_cpu_irq_init(12);
++
++#ifdef CONFIG_KGDB
++	excite_kgdb_init();
++#endif
++}
++
++asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
++{
++	const u32
++		interrupts = read_c0_cause() >> 8,
++		mask = ((read_c0_status() >> 8) & 0x000000ff) |
++		       (read_c0_intcontrol() & 0x0000ff00),
++		pending = interrupts & mask;
++	u32 msgintflags, msgintmask, msgint;
++
++	/* process timer interrupt */
++	if (pending & (1 << TIMER_IRQ)) {
++		do_IRQ(TIMER_IRQ, regs);
++		return;
++	}
++
++	/* Process PCI interrupts */
++#if USB_IRQ < 10
++	msgintflags = ocd_readl(INTP0Status0 + (USB_MSGINT / 0x20 * 0x10));
++	msgintmask  = ocd_readl(INTP0Mask0 + (USB_MSGINT / 0x20 * 0x10));
++	msgint	    = msgintflags & msgintmask & (0x1 << (USB_MSGINT % 0x20));
++	if ((pending & (1 << USB_IRQ)) && msgint) {
++#else
++	if (pending & (1 << USB_IRQ)) {
++#endif
++		do_IRQ(USB_IRQ, regs);
++		return;
++	}
++
++	/* Process TITAN interrupts */
++	msgintflags = ocd_readl(INTP0Status0 + (TITAN_MSGINT / 0x20 * 0x10));
++	msgintmask  = ocd_readl(INTP0Mask0 + (TITAN_MSGINT / 0x20 * 0x10));
++	msgint	    = msgintflags & msgintmask & (0x1 << (TITAN_MSGINT % 0x20));
++	if ((pending & (1 << TITAN_IRQ)) && msgint) {
++		ocd_writel(msgint, INTP0Clear0 + (TITAN_MSGINT / 0x20 * 0x10));
++#if defined(CONFIG_KGDB)
++		excite_kgdb_inthdl(regs);
++#endif
++		do_IRQ(TITAN_IRQ, regs);
++		return;
++	}
++
++	/* Process FPGA line #0 interrupts */
++	msgintflags = ocd_readl(INTP0Status0 + (FPGA0_MSGINT / 0x20 * 0x10));
++	msgintmask  = ocd_readl(INTP0Mask0 + (FPGA0_MSGINT / 0x20 * 0x10));
++	msgint	    = msgintflags & msgintmask & (0x1 << (FPGA0_MSGINT % 0x20));
++	if ((pending & (1 << FPGA0_IRQ)) && msgint) {
++		do_IRQ(FPGA0_IRQ, regs);
++		return;
++	}
++
++	/* Process FPGA line #1 interrupts */
++	msgintflags = ocd_readl(INTP0Status0 + (FPGA1_MSGINT / 0x20 * 0x10));
++	msgintmask  = ocd_readl(INTP0Mask0 + (FPGA1_MSGINT / 0x20 * 0x10));
++	msgint	    = msgintflags & msgintmask & (0x1 << (FPGA1_MSGINT % 0x20));
++	if ((pending & (1 << FPGA1_IRQ)) && msgint) {
++		do_IRQ(FPGA1_IRQ, regs);
++		return;
++	}
++
++	/* Process PHY interrupts */
++	msgintflags = ocd_readl(INTP0Status0 + (PHY_MSGINT / 0x20 * 0x10));
++	msgintmask  = ocd_readl(INTP0Mask0 + (PHY_MSGINT / 0x20 * 0x10));
++	msgint	    = msgintflags & msgintmask & (0x1 << (PHY_MSGINT % 0x20));
++	if ((pending & (1 << PHY_IRQ)) && msgint) {
++		do_IRQ(PHY_IRQ, regs);
++		return;
++	}
++
++	/* Process spurious interrupts */
++	spurious_interrupt(regs);
++}
+diff -Naur linux-2.6.17.orig/arch/mips/basler/excite/excite_procfs.c linux-2.6.17/arch/mips/basler/excite/excite_procfs.c
+--- linux-2.6.17.orig/arch/mips/basler/excite/excite_procfs.c	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/arch/mips/basler/excite/excite_procfs.c	2006-06-19 18:16:12.000000000 -0700
+@@ -0,0 +1,81 @@
++/*
++ *  Copyright (C) 2004, 2005 by Basler Vision Technologies AG
++ *  Author: Thomas Koeller <thomas.koeller@baslerweb.com>
++ *
++ *  Procfs support for Basler eXcite
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License as published by
++ *  the Free Software Foundation; either version 2 of the License, or
++ *  (at your option) any later version.
++ *
++ *  This program is distributed in the hope that it will be useful,
++ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *  GNU General Public License for more details.
++ *
++ *  You should have received a copy of the GNU General Public License
++ *  along with this program; if not, write to the Free Software
++ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
++ */
++
++#include <linux/config.h>
++#include <linux/proc_fs.h>
++#include <linux/stat.h>
++#include <asm/page.h>
++#include <asm/io.h>
++#include <asm/system.h>
++#include <asm/rm9k-ocd.h>
++
++#include <excite.h>
++
++static int excite_get_unit_id(char *buf, char **addr, off_t offs, int size)
++{
++	const int len = snprintf(buf, PAGE_SIZE, "%06x", unit_id);
++	const int w = len - offs;
++	*addr = buf + offs;
++	return w < size ? w : size;
++}
++
++static int
++excite_bootrom_read(char *page, char **start, off_t off, int count,
++		  int *eof, void *data)
++{
++	void __iomem * src;
++
++	if (off >= EXCITE_SIZE_BOOTROM) {
++		*eof = 1;
++		return 0;
++	}
++
++	if ((off + count) > EXCITE_SIZE_BOOTROM)
++		count = EXCITE_SIZE_BOOTROM - off;
++
++	src = ioremap(EXCITE_PHYS_BOOTROM + off, count);
++	if (src) {
++		memcpy_fromio(page, src, count);
++		iounmap(src);
++		*start = page;
++	} else {
++		count = -ENOMEM;
++	}
++
++	return count;
++}
++
++void excite_procfs_init(void)
++{
++	/* Create & populate /proc/excite */
++	struct proc_dir_entry * const pdir = proc_mkdir("excite", &proc_root);
++	if (pdir) {
++		struct proc_dir_entry * e;
++
++		e = create_proc_info_entry("unit_id", S_IRUGO, pdir,
++					   excite_get_unit_id);
++		if (e) e->size = 6;
++
++		e = create_proc_read_entry("bootrom", S_IRUGO, pdir,
++					   excite_bootrom_read, NULL);
++		if (e) e->size = EXCITE_SIZE_BOOTROM;
++	}
++}
+diff -Naur linux-2.6.17.orig/arch/mips/basler/excite/excite_prom.c linux-2.6.17/arch/mips/basler/excite/excite_prom.c
+--- linux-2.6.17.orig/arch/mips/basler/excite/excite_prom.c	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/arch/mips/basler/excite/excite_prom.c	2006-06-19 18:16:12.000000000 -0700
+@@ -0,0 +1,148 @@
++/*
++ *  Copyright (C) 2004, 2005 by Thomas Koeller (thomas.koeller@baslerweb.com)
++ *  Based on the PMC-Sierra Yosemite board support by Ralf Baechle and
++ *  Manish Lachwani.
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License as published by
++ *  the Free Software Foundation; either version 2 of the License, or
++ *  (at your option) any later version.
++ *
++ *  This program is distributed in the hope that it will be useful,
++ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *  GNU General Public License for more details.
++ *
++ *  You should have received a copy of the GNU General Public License
++ *  along with this program; if not, write to the Free Software
++ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
++ */
++
++#include <linux/config.h>
++#include <linux/init.h>
++#include <linux/sched.h>
++#include <linux/mm.h>
++#include <linux/delay.h>
++#include <linux/smp.h>
++#include <linux/module.h>
++#include <asm/io.h>
++#include <asm/pgtable.h>
++#include <asm/processor.h>
++#include <asm/reboot.h>
++#include <asm/system.h>
++#include <asm/bootinfo.h>
++#include <asm/string.h>
++
++#include <excite.h>
++
++/* This struct is used by Redboot to pass arguments to the kernel */
++typedef struct
++{
++	char *name;
++	char *val;
++} t_env_var;
++
++struct parmblock {
++	t_env_var memsize;
++	t_env_var modetty0;
++	t_env_var ethaddr;
++	t_env_var env_end;
++	char *argv[2];
++	char text[0];
++};
++
++static unsigned int prom_argc;
++static const char ** prom_argv;
++static const t_env_var * prom_env;
++
++static void prom_halt(void) __attribute__((noreturn));
++static void prom_exit(void) __attribute__((noreturn));
++
++
++
++const char *get_system_type(void)
++{
++	return "Basler eXcite";
++}
++
++/*
++ * Halt the system
++ */
++static void prom_halt(void)
++{
++	printk(KERN_NOTICE "\n** System halted.\n");
++	while (1)
++		asm volatile (
++			"\t.set\tmips3\n"
++			"\twait\n"
++			"\t.set\tmips0\n"
++		);
++}
++
++/*
++ * Reset the CPU and re-enter Redboot
++ */
++static void prom_exit(void)
++{
++	unsigned int i;
++	volatile unsigned char * const flg =
++		(volatile unsigned char *) (EXCITE_ADDR_FPGA + EXCITE_FPGA_DPR);
++
++	/* Clear the watchdog reset flag, set the reboot flag */
++	*flg &= ~0x01;
++	*flg |= 0x80;
++
++	for (i = 0; i < 10; i++) {
++		*(volatile unsigned char *)  (EXCITE_ADDR_FPGA + EXCITE_FPGA_SYSCTL) = 0x02;
++		iob();
++		mdelay(1000);
++	}
++
++	printk(KERN_NOTICE "Reset failed\n");
++	prom_halt();
++}
++
++static const char __init *prom_getenv(char *name)
++{
++	const t_env_var * p;
++	for (p = prom_env; p->name != NULL; p++)
++		if(strcmp(name, p->name) == 0)
++			break;
++	return p->val;
++}
++
++/*
++ * Init routine which accepts the variables from Redboot
++ */
++void __init prom_init(void)
++{
++	const struct parmblock * const pb = (struct parmblock *) fw_arg2;
++
++	prom_argc = fw_arg0;
++	prom_argv = (const char **) fw_arg1;
++	prom_env = &pb->memsize;
++
++	/* Callbacks for halt, restart */
++	_machine_restart = (void (*)(char *)) prom_exit;
++	_machine_halt = prom_halt;
++
++#ifdef CONFIG_32BIT
++	/* copy command line */
++	strcpy(arcs_cmdline, prom_argv[1]);
++	memsize = simple_strtol(prom_getenv("memsize"), NULL, 16);
++	strcpy(modetty, prom_getenv("modetty0"));
++#endif /* CONFIG_32BIT */
++
++#ifdef CONFIG_64BIT
++#	error 64 bit support not implemented
++#endif /* CONFIG_64BIT */
++
++	mips_machgroup = MACH_GROUP_TITAN;
++	mips_machtype = MACH_TITAN_EXCITE;
++}
++
++/* This is called from free_initmem(), so we need to provide it */
++void __init prom_free_prom_memory(void)
++{
++	/* Nothing to do */
++}
+diff -Naur linux-2.6.17.orig/arch/mips/basler/excite/excite_setup.c linux-2.6.17/arch/mips/basler/excite/excite_setup.c
+--- linux-2.6.17.orig/arch/mips/basler/excite/excite_setup.c	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/arch/mips/basler/excite/excite_setup.c	2006-06-19 18:16:12.000000000 -0700
+@@ -0,0 +1,307 @@
++/*
++ *  Copyright (C) 2004, 2005 by Basler Vision Technologies AG
++ *  Author: Thomas Koeller <thomas.koeller@baslerweb.com>
++ *  Based on the PMC-Sierra Yosemite board support by Ralf Baechle and
++ *  Manish Lachwani.
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License as published by
++ *  the Free Software Foundation; either version 2 of the License, or
++ *  (at your option) any later version.
++ *
++ *  This program is distributed in the hope that it will be useful,
++ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *  GNU General Public License for more details.
++ *
++ *  You should have received a copy of the GNU General Public License
++ *  along with this program; if not, write to the Free Software
++ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
++ */
++
++#include <linux/config.h>
++#include <linux/types.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/string.h>
++#include <linux/tty.h>
++#include <linux/serial_core.h>
++#include <linux/serial.h>
++#include <linux/ioport.h>
++#include <linux/spinlock.h>
++#include <asm/bootinfo.h>
++#include <asm/mipsregs.h>
++#include <asm/pgtable-32.h>
++#include <asm/io.h>
++#include <asm/time.h>
++#include <asm/rm9k-ocd.h>
++
++#include <excite.h>
++
++#define TITAN_UART_CLK	25000000
++
++#if 1
++/* normal serial port assignment */
++#define REGBASE_SER0	0x0208
++#define REGBASE_SER1	0x0238
++#define MASK_SER0	0x1
++#define MASK_SER1	0x2
++#else
++/* serial ports swapped */
++#define REGBASE_SER0	0x0238
++#define REGBASE_SER1	0x0208
++#define MASK_SER0	0x2
++#define MASK_SER1	0x1
++#endif
++
++unsigned long memsize;
++char modetty[30];
++unsigned int titan_irq = TITAN_IRQ;
++static void __iomem * ctl_regs;
++u32 unit_id;
++
++volatile void __iomem * const ocd_base = (void *) (EXCITE_ADDR_OCD);
++volatile void __iomem * const titan_base = (void *) (EXCITE_ADDR_TITAN);
++
++/* Protect access to shared GPI registers */
++spinlock_t titan_lock = SPIN_LOCK_UNLOCKED;
++int titan_irqflags;
++
++
++static void excite_timer_init(void)
++{
++	const u32 modebit5 = ocd_readl(0x00e4);
++	unsigned int
++		mult = ((modebit5 >> 11) & 0x1f) + 2,
++		div = ((modebit5 >> 16) & 0x1f) + 2;
++
++	if (div == 33) div = 1;
++	mips_hpt_frequency = EXCITE_CPU_EXT_CLOCK * mult / div / 2;
++}
++
++static void excite_timer_setup(struct irqaction *irq)
++{
++	/* The eXcite platform uses the alternate timer interrupt */
++	set_c0_intcontrol(0x80);
++	setup_irq(TIMER_IRQ, irq);
++}
++
++static int __init excite_init_console(void)
++{
++#if defined(CONFIG_SERIAL_8250)
++	static __initdata char serr[] =
++		KERN_ERR "Serial port #%u setup failed\n";
++	struct uart_port up;
++
++	/* Take the DUART out of reset */
++	titan_writel(0x00ff1cff, CPRR);
++
++#if defined(CONFIG_KGDB) || (CONFIG_SERIAL_8250_NR_UARTS > 1)
++	/* Enable both ports */
++	titan_writel(MASK_SER0 | MASK_SER1, UACFG);
++#else
++	/* Enable port #0 only */
++	titan_writel(MASK_SER0, UACFG);
++#endif	/* defined(CONFIG_KGDB) */
++
++ 	/*
++	 * Set up serial port #0. Do not use autodetection; the result is
++	 * not what we want.
++ 	 */
++	memset(&up, 0, sizeof(up));
++	up.membase	= (char *) titan_addr(REGBASE_SER0);
++	up.irq		= TITAN_IRQ;
++	up.uartclk	= TITAN_UART_CLK;
++	up.regshift	= 0;
++	up.iotype	= UPIO_MEM32;
++	up.type		= PORT_RM9000;
++	up.flags	= UPF_SHARE_IRQ;
++	up.line		= 0;
++	if (early_serial_setup(&up))
++		printk(serr, up.line);
++
++#if CONFIG_SERIAL_8250_NR_UARTS > 1
++	/* And now for port #1. */
++	up.membase	= (char *) titan_addr(REGBASE_SER1);
++	up.line		= 1;
++ 	if (early_serial_setup(&up))
++		printk(serr, up.line);
++#endif /* CONFIG_SERIAL_8250_NR_UARTS > 1 */
++#else
++	/* Leave the DUART in reset */
++	titan_writel(0x00ff3cff, CPRR);
++#endif  /* defined(CONFIG_SERIAL_8250) */
++
++	return 0;
++}
++
++static int __init excite_platform_init(void)
++{
++	unsigned int i;
++	unsigned char buf[3];
++	u8 reg;
++	void __iomem * dpr;
++
++	/* BIU buffer allocations */
++	ocd_writel(8, CPURSLMT);	/* CPU */
++	titan_writel(4, CPGRWL);	/* GPI / Ethernet */
++
++	/* Map control registers located in FPGA */
++	ctl_regs = ioremap_nocache(EXCITE_PHYS_FPGA + EXCITE_FPGA_SYSCTL, 16);
++	if (!ctl_regs)
++		panic("eXcite: failed to map platform control registers\n");
++	memcpy_fromio(buf, ctl_regs + 2, ARRAY_SIZE(buf));
++	unit_id = buf[0] | (buf[1] << 8) | (buf[2] << 16);
++
++	/* Clear the reboot flag */
++	dpr = ioremap_nocache(EXCITE_PHYS_FPGA + EXCITE_FPGA_DPR, 1);
++	reg = __raw_readb(dpr);
++	__raw_writeb(reg & 0x7f, dpr);
++	iounmap(dpr);
++
++	/* Interrupt controller setup */
++	for (i = INTP0Status0; i < INTP0Status0 + 0x80; i += 0x10) {
++		ocd_writel(0x00000000, i + 0x04);
++		ocd_writel(0xffffffff, i + 0x0c);
++	}
++	ocd_writel(0x2, NMICONFIG);
++
++	ocd_writel(0x1 << (TITAN_MSGINT % 0x20),
++		   INTP0Mask0 + (0x10 * (TITAN_MSGINT / 0x20)));
++	ocd_writel((0x1 << (FPGA0_MSGINT % 0x20))
++		   | ocd_readl(INTP0Mask0 + (0x10 * (FPGA0_MSGINT / 0x20))),
++		   INTP0Mask0 + (0x10 * (FPGA0_MSGINT / 0x20)));
++	ocd_writel((0x1 << (FPGA1_MSGINT % 0x20))
++		   | ocd_readl(INTP0Mask0 + (0x10 * (FPGA1_MSGINT / 0x20))),
++		   INTP0Mask0 + (0x10 * (FPGA1_MSGINT / 0x20)));
++	ocd_writel((0x1 << (PHY_MSGINT % 0x20))
++		   | ocd_readl(INTP0Mask0 + (0x10 * (PHY_MSGINT / 0x20))),
++		   INTP0Mask0 + (0x10 * (PHY_MSGINT / 0x20)));
++#if USB_IRQ < 10
++	ocd_writel((0x1 << (USB_MSGINT % 0x20))
++		   | ocd_readl(INTP0Mask0 + (0x10 * (USB_MSGINT / 0x20))),
++		   INTP0Mask0 + (0x10 * (USB_MSGINT / 0x20)));
++#endif
++	/* Enable the packet FIFO, XDMA and XDMA arbiter */
++	titan_writel(0x00ff18ff, CPRR);
++
++	/*
++	 * Set up the PADMUX. Power down all ethernet slices,
++	 * they will be powered up and configured at device startup.
++	 */
++	titan_writel(0x00878206, CPTC1R);
++	titan_writel(0x00001100, CPTC0R); /* latch PADMUX, enable WCIMODE */
++
++	/* Reset and enable the FIFO block */
++	titan_writel(0x00000001, SDRXFCIE);
++	titan_writel(0x00000001, SDTXFCIE);
++	titan_writel(0x00000100, SDRXFCIE);
++	titan_writel(0x00000000, SDTXFCIE);
++
++	/*
++	 * Initialize the common interrupt shared by all components of
++	 * the GPI/Ethernet subsystem.
++	 */
++	titan_writel((EXCITE_PHYS_OCD >> 12), CPCFG0);
++	titan_writel(TITAN_MSGINT, CPCFG1);
++
++	/*
++	 * XDMA configuration.
++	 * In order for the XDMA to be sharable among multiple drivers,
++	 * the setup must be done here in the platform. The reason is that
++	 * this setup can only be done while the XDMA is in reset. If this
++	 * were done in a driver, it would interrupt all other drivers
++	 * using the XDMA.
++	 */
++	titan_writel(0x80021dff, GXCFG);	/* XDMA reset */
++	titan_writel(0x00000000, CPXCISRA);
++	titan_writel(0x00000000, CPXCISRB);	/* clear pending interrupts */
++#if defined (CONFIG_HIGHMEM)
++#	error change for HIGHMEM support!
++#else
++	titan_writel(0x00000000, GXDMADRPFX);	/* buffer address prefix */
++#endif
++	titan_writel(0, GXDMA_DESCADR);
++
++	for (i = 0x5040; i <= 0x5300; i += 0x0040)
++		titan_writel(0x80080000, i);	/* reset channel */
++
++	titan_writel((0x1 << 29)			/* no sparse tx descr. */
++		     | (0x1 << 28)			/* no sparse rx descr. */
++		     | (0x1 << 23) | (0x1 << 24)	/* descriptor coherency */
++		     | (0x1 << 21) | (0x1 << 22)	/* data coherency */
++		     | (0x1 << 17)
++		     | 0x1dff,
++		     GXCFG);
++
++#if defined(CONFIG_SMP)
++#	error No SMP support
++#else
++	/* All interrupts go to core #0 only. */
++	titan_writel(0x1f007fff, CPDST0A);
++	titan_writel(0x00000000, CPDST0B);
++	titan_writel(0x0000ff3f, CPDST1A);
++	titan_writel(0x00000000, CPDST1B);
++	titan_writel(0x00ffffff, CPXDSTA);
++	titan_writel(0x00000000, CPXDSTB);
++#endif
++
++	/* Enable DUART interrupts, disable everything else. */
++	titan_writel(0x04000000, CPGIG0ER);
++	titan_writel(0x000000c0, CPGIG1ER);
++
++	excite_procfs_init();
++	return 0;
++}
++
++void __init plat_setup(void)
++{
++	volatile u32 * const boot_ocd_base = (u32 *) 0xbf7fc000;
++
++	/* Announce RAM to system */
++	add_memory_region(0x00000000, memsize, BOOT_MEM_RAM);
++
++	/* Set up timer initialization hooks */
++	board_time_init = excite_timer_init;
++	board_timer_setup = excite_timer_setup;
++
++	/* Set up the peripheral address map */
++	*(boot_ocd_base + (LKB9 / sizeof (u32))) = 0;
++	*(boot_ocd_base + (LKB10 / sizeof (u32))) = 0;
++	*(boot_ocd_base + (LKB11 / sizeof (u32))) = 0;
++	*(boot_ocd_base + (LKB12 / sizeof (u32))) = 0;
++	wmb();
++	*(boot_ocd_base + (LKB0 / sizeof (u32))) = EXCITE_PHYS_OCD >> 4;
++	wmb();
++
++	ocd_writel((EXCITE_PHYS_TITAN >> 4) | 0x1UL, LKB5);
++	ocd_writel(((EXCITE_SIZE_TITAN >> 4) & 0x7fffff00) - 0x100, LKM5);
++	ocd_writel((EXCITE_PHYS_SCRAM >> 4) | 0x1UL, LKB13);
++	ocd_writel(((EXCITE_SIZE_SCRAM >> 4) & 0xffffff00) - 0x100, LKM13);
++
++	/* Local bus slot #0 */
++	ocd_writel(0x00040510, LDP0);
++	ocd_writel((EXCITE_PHYS_BOOTROM >> 4) | 0x1UL, LKB9);
++	ocd_writel(((EXCITE_SIZE_BOOTROM >> 4) & 0x03ffff00) - 0x100, LKM9);
++
++	/* Local bus slot #2 */
++	ocd_writel(0x00000330, LDP2);
++	ocd_writel((EXCITE_PHYS_FPGA >> 4) | 0x1, LKB11);
++	ocd_writel(((EXCITE_SIZE_FPGA >> 4) - 0x100) & 0x03ffff00, LKM11);
++
++	/* Local bus slot #3 */
++	ocd_writel(0x00123413, LDP3);
++	ocd_writel((EXCITE_PHYS_NAND >> 4) | 0x1, LKB12);
++	ocd_writel(((EXCITE_SIZE_NAND >> 4) - 0x100) & 0x03ffff00, LKM12);
++}
++
++
++
++console_initcall(excite_init_console);
++arch_initcall(excite_platform_init);
++
++EXPORT_SYMBOL(titan_lock);
++EXPORT_SYMBOL(titan_irqflags);
++EXPORT_SYMBOL(titan_irq);
++EXPORT_SYMBOL(ocd_base);
++EXPORT_SYMBOL(titan_base);
+diff -Naur linux-2.6.17.orig/arch/mips/basler/excite/Makefile linux-2.6.17/arch/mips/basler/excite/Makefile
+--- linux-2.6.17.orig/arch/mips/basler/excite/Makefile	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/arch/mips/basler/excite/Makefile	2006-06-19 18:16:12.000000000 -0700
+@@ -0,0 +1,9 @@
++#
++# Makefile for Basler eXcite
++#
++
++obj-$(CONFIG_BASLER_EXCITE)	+= excite_irq.o excite_prom.o excite_setup.o \
++				   excite_device.o excite_procfs.o
++
++obj-$(CONFIG_KGDB)		+= excite_dbg_io.o
++obj-m				+= excite_iodev.o
+diff -Naur linux-2.6.17.orig/arch/mips/cobalt/console.c linux-2.6.17/arch/mips/cobalt/console.c
+--- linux-2.6.17.orig/arch/mips/cobalt/console.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/cobalt/console.c	2006-06-19 18:16:12.000000000 -0700
+@@ -41,3 +41,8 @@
+ 
+ 	printk("Cobalt: early console registered\n");
+ }
++
++void __init disable_early_printk(void)
++{
++	unregister_console(&cons_info);
++}
+diff -Naur linux-2.6.17.orig/arch/mips/cobalt/setup.c linux-2.6.17/arch/mips/cobalt/setup.c
+--- linux-2.6.17.orig/arch/mips/cobalt/setup.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/cobalt/setup.c	2006-06-19 18:16:12.000000000 -0700
+@@ -68,19 +68,46 @@
+ extern struct pci_ops gt64111_pci_ops;
+ 
+ static struct resource cobalt_mem_resource = {
+-	"PCI memory", GT64111_MEM_BASE, GT64111_MEM_END, IORESOURCE_MEM
++	.start	= GT64111_MEM_BASE,
++	.end	= GT64111_MEM_END,
++	.name	= "PCI memory",
++	.flags	= IORESOURCE_MEM
+ };
+ 
+ static struct resource cobalt_io_resource = {
+-	"PCI I/O", 0x1000, 0xffff, IORESOURCE_IO
++	.start	= 0x1000,
++	.end	= 0xffff,
++	.name	= "PCI I/O",
++	.flags	= IORESOURCE_IO
+ };
+ 
+ static struct resource cobalt_io_resources[] = {
+-	{ "dma1", 0x00, 0x1f, IORESOURCE_BUSY },
+-	{ "timer", 0x40, 0x5f, IORESOURCE_BUSY },
+-	{ "keyboard", 0x60, 0x6f, IORESOURCE_BUSY },
+-	{ "dma page reg", 0x80, 0x8f, IORESOURCE_BUSY },
+-	{ "dma2", 0xc0, 0xdf, IORESOURCE_BUSY },
++	{
++		.start	= 0x00,
++		.end	= 0x1f,
++		.name	= "dma1",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	= 0x40,
++		.end	= 0x5f,
++		.name	= "timer",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	= 0x60,
++		.end	= 0x6f,
++		.name	= "keyboard",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	= 0x80,
++		.end	= 0x8f,
++		.name	= "dma page reg",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	= 0xc0,
++		.end	= 0xdf,
++		.name	= "dma2",
++		.flags	= IORESOURCE_BUSY
++	},
+ };
+ 
+ #define COBALT_IO_RESOURCES (sizeof(cobalt_io_resources)/sizeof(struct resource))
+@@ -93,7 +120,7 @@
+ 	.io_offset	= 0 - GT64111_IO_BASE
+ };
+ 
+-void __init plat_setup(void)
++void __init plat_mem_setup(void)
+ {
+ 	static struct uart_port uart;
+ 	unsigned int devfn = PCI_DEVFN(COBALT_PCICONF_VIA, 0);
+diff -Naur linux-2.6.17.orig/arch/mips/configs/atlas_defconfig linux-2.6.17/arch/mips/configs/atlas_defconfig
+--- linux-2.6.17.orig/arch/mips/configs/atlas_defconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/configs/atlas_defconfig	2006-06-19 18:16:12.000000000 -0700
+@@ -41,8 +41,6 @@
+ # CONFIG_MIPS_XXS1500 is not set
+ # CONFIG_PNX8550_V2PCI is not set
+ # CONFIG_PNX8550_JBS is not set
+-# CONFIG_DDB5074 is not set
+-# CONFIG_DDB5476 is not set
+ # CONFIG_DDB5477 is not set
+ # CONFIG_MACH_VR41XX is not set
+ # CONFIG_PMC_YOSEMITE is not set
+@@ -67,6 +65,7 @@
+ CONFIG_GENERIC_FIND_NEXT_BIT=y
+ CONFIG_GENERIC_HWEIGHT=y
+ CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+ CONFIG_DMA_NONCOHERENT=y
+ CONFIG_DMA_NEED_PCI_MAP_STATE=y
+ CONFIG_MIPS_BONITO64=y
+diff -Naur linux-2.6.17.orig/arch/mips/configs/bigsur_defconfig linux-2.6.17/arch/mips/configs/bigsur_defconfig
+--- linux-2.6.17.orig/arch/mips/configs/bigsur_defconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/configs/bigsur_defconfig	2006-06-19 18:16:12.000000000 -0700
+@@ -41,8 +41,6 @@
+ # CONFIG_MIPS_XXS1500 is not set
+ # CONFIG_PNX8550_V2PCI is not set
+ # CONFIG_PNX8550_JBS is not set
+-# CONFIG_DDB5074 is not set
+-# CONFIG_DDB5476 is not set
+ # CONFIG_DDB5477 is not set
+ # CONFIG_MACH_VR41XX is not set
+ # CONFIG_PMC_YOSEMITE is not set
+@@ -83,6 +81,7 @@
+ CONFIG_GENERIC_FIND_NEXT_BIT=y
+ CONFIG_GENERIC_HWEIGHT=y
+ CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+ CONFIG_DMA_COHERENT=y
+ CONFIG_CPU_BIG_ENDIAN=y
+ # CONFIG_CPU_LITTLE_ENDIAN is not set
+diff -Naur linux-2.6.17.orig/arch/mips/configs/capcella_defconfig linux-2.6.17/arch/mips/configs/capcella_defconfig
+--- linux-2.6.17.orig/arch/mips/configs/capcella_defconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/configs/capcella_defconfig	2006-06-19 18:16:12.000000000 -0700
+@@ -41,8 +41,6 @@
+ # CONFIG_MIPS_XXS1500 is not set
+ # CONFIG_PNX8550_V2PCI is not set
+ # CONFIG_PNX8550_JBS is not set
+-# CONFIG_DDB5074 is not set
+-# CONFIG_DDB5476 is not set
+ # CONFIG_DDB5477 is not set
+ CONFIG_MACH_VR41XX=y
+ # CONFIG_PMC_YOSEMITE is not set
+@@ -75,6 +73,7 @@
+ CONFIG_GENERIC_FIND_NEXT_BIT=y
+ CONFIG_GENERIC_HWEIGHT=y
+ CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+ CONFIG_DMA_NONCOHERENT=y
+ CONFIG_DMA_NEED_PCI_MAP_STATE=y
+ # CONFIG_CPU_BIG_ENDIAN is not set
+diff -Naur linux-2.6.17.orig/arch/mips/configs/cobalt_defconfig linux-2.6.17/arch/mips/configs/cobalt_defconfig
+--- linux-2.6.17.orig/arch/mips/configs/cobalt_defconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/configs/cobalt_defconfig	2006-06-19 18:16:12.000000000 -0700
+@@ -41,8 +41,6 @@
+ # CONFIG_MIPS_XXS1500 is not set
+ # CONFIG_PNX8550_V2PCI is not set
+ # CONFIG_PNX8550_JBS is not set
+-# CONFIG_DDB5074 is not set
+-# CONFIG_DDB5476 is not set
+ # CONFIG_DDB5477 is not set
+ # CONFIG_MACH_VR41XX is not set
+ # CONFIG_PMC_YOSEMITE is not set
+@@ -68,6 +66,7 @@
+ CONFIG_GENERIC_FIND_NEXT_BIT=y
+ CONFIG_GENERIC_HWEIGHT=y
+ CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+ CONFIG_DMA_NONCOHERENT=y
+ CONFIG_DMA_NEED_PCI_MAP_STATE=y
+ CONFIG_I8259=y
+diff -Naur linux-2.6.17.orig/arch/mips/configs/db1000_defconfig linux-2.6.17/arch/mips/configs/db1000_defconfig
+--- linux-2.6.17.orig/arch/mips/configs/db1000_defconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/configs/db1000_defconfig	2006-06-19 18:16:12.000000000 -0700
+@@ -41,8 +41,6 @@
+ # CONFIG_MIPS_XXS1500 is not set
+ # CONFIG_PNX8550_V2PCI is not set
+ # CONFIG_PNX8550_JBS is not set
+-# CONFIG_DDB5074 is not set
+-# CONFIG_DDB5476 is not set
+ # CONFIG_DDB5477 is not set
+ # CONFIG_MACH_VR41XX is not set
+ # CONFIG_PMC_YOSEMITE is not set
+@@ -67,6 +65,7 @@
+ CONFIG_GENERIC_FIND_NEXT_BIT=y
+ CONFIG_GENERIC_HWEIGHT=y
+ CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+ CONFIG_DMA_NONCOHERENT=y
+ CONFIG_DMA_NEED_PCI_MAP_STATE=y
+ # CONFIG_CPU_BIG_ENDIAN is not set
+diff -Naur linux-2.6.17.orig/arch/mips/configs/db1100_defconfig linux-2.6.17/arch/mips/configs/db1100_defconfig
+--- linux-2.6.17.orig/arch/mips/configs/db1100_defconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/configs/db1100_defconfig	2006-06-19 18:16:12.000000000 -0700
+@@ -41,8 +41,6 @@
+ # CONFIG_MIPS_XXS1500 is not set
+ # CONFIG_PNX8550_V2PCI is not set
+ # CONFIG_PNX8550_JBS is not set
+-# CONFIG_DDB5074 is not set
+-# CONFIG_DDB5476 is not set
+ # CONFIG_DDB5477 is not set
+ # CONFIG_MACH_VR41XX is not set
+ # CONFIG_PMC_YOSEMITE is not set
+@@ -67,6 +65,7 @@
+ CONFIG_GENERIC_FIND_NEXT_BIT=y
+ CONFIG_GENERIC_HWEIGHT=y
+ CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+ CONFIG_DMA_NONCOHERENT=y
+ CONFIG_DMA_NEED_PCI_MAP_STATE=y
+ # CONFIG_CPU_BIG_ENDIAN is not set
+diff -Naur linux-2.6.17.orig/arch/mips/configs/db1200_defconfig linux-2.6.17/arch/mips/configs/db1200_defconfig
+--- linux-2.6.17.orig/arch/mips/configs/db1200_defconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/configs/db1200_defconfig	2006-06-19 18:16:12.000000000 -0700
+@@ -41,8 +41,6 @@
+ # CONFIG_MIPS_XXS1500 is not set
+ # CONFIG_PNX8550_V2PCI is not set
+ # CONFIG_PNX8550_JBS is not set
+-# CONFIG_DDB5074 is not set
+-# CONFIG_DDB5476 is not set
+ # CONFIG_DDB5477 is not set
+ # CONFIG_MACH_VR41XX is not set
+ # CONFIG_PMC_YOSEMITE is not set
+@@ -67,6 +65,7 @@
+ CONFIG_GENERIC_FIND_NEXT_BIT=y
+ CONFIG_GENERIC_HWEIGHT=y
+ CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+ CONFIG_DMA_COHERENT=y
+ CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y
+ # CONFIG_CPU_BIG_ENDIAN is not set
+diff -Naur linux-2.6.17.orig/arch/mips/configs/db1500_defconfig linux-2.6.17/arch/mips/configs/db1500_defconfig
+--- linux-2.6.17.orig/arch/mips/configs/db1500_defconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/configs/db1500_defconfig	2006-06-19 18:16:12.000000000 -0700
+@@ -41,8 +41,6 @@
+ # CONFIG_MIPS_XXS1500 is not set
+ # CONFIG_PNX8550_V2PCI is not set
+ # CONFIG_PNX8550_JBS is not set
+-# CONFIG_DDB5074 is not set
+-# CONFIG_DDB5476 is not set
+ # CONFIG_DDB5477 is not set
+ # CONFIG_MACH_VR41XX is not set
+ # CONFIG_PMC_YOSEMITE is not set
+@@ -67,6 +65,7 @@
+ CONFIG_GENERIC_FIND_NEXT_BIT=y
+ CONFIG_GENERIC_HWEIGHT=y
+ CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+ CONFIG_DMA_NONCOHERENT=y
+ CONFIG_DMA_NEED_PCI_MAP_STATE=y
+ CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y
+diff -Naur linux-2.6.17.orig/arch/mips/configs/db1550_defconfig linux-2.6.17/arch/mips/configs/db1550_defconfig
+--- linux-2.6.17.orig/arch/mips/configs/db1550_defconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/configs/db1550_defconfig	2006-06-19 18:16:12.000000000 -0700
+@@ -41,8 +41,6 @@
+ # CONFIG_MIPS_XXS1500 is not set
+ # CONFIG_PNX8550_V2PCI is not set
+ # CONFIG_PNX8550_JBS is not set
+-# CONFIG_DDB5074 is not set
+-# CONFIG_DDB5476 is not set
+ # CONFIG_DDB5477 is not set
+ # CONFIG_MACH_VR41XX is not set
+ # CONFIG_PMC_YOSEMITE is not set
+@@ -67,6 +65,7 @@
+ CONFIG_GENERIC_FIND_NEXT_BIT=y
+ CONFIG_GENERIC_HWEIGHT=y
+ CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+ CONFIG_DMA_NONCOHERENT=y
+ CONFIG_DMA_NEED_PCI_MAP_STATE=y
+ CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y
+diff -Naur linux-2.6.17.orig/arch/mips/configs/ddb5476_defconfig linux-2.6.17/arch/mips/configs/ddb5476_defconfig
+--- linux-2.6.17.orig/arch/mips/configs/ddb5476_defconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/configs/ddb5476_defconfig	1969-12-31 16:00:00.000000000 -0800
+@@ -1,917 +0,0 @@
+-#
+-# Automatically generated make config: don't edit
+-# Linux kernel version: 2.6.17-rc2
+-# Mon Apr 24 14:51:00 2006
+-#
+-CONFIG_MIPS=y
+-
+-#
+-# Machine selection
+-#
+-# CONFIG_MIPS_MTX1 is not set
+-# CONFIG_MIPS_BOSPORUS is not set
+-# CONFIG_MIPS_PB1000 is not set
+-# CONFIG_MIPS_PB1100 is not set
+-# CONFIG_MIPS_PB1500 is not set
+-# CONFIG_MIPS_PB1550 is not set
+-# CONFIG_MIPS_PB1200 is not set
+-# CONFIG_MIPS_DB1000 is not set
+-# CONFIG_MIPS_DB1100 is not set
+-# CONFIG_MIPS_DB1500 is not set
+-# CONFIG_MIPS_DB1550 is not set
+-# CONFIG_MIPS_DB1200 is not set
+-# CONFIG_MIPS_MIRAGE is not set
+-# CONFIG_MIPS_COBALT is not set
+-# CONFIG_MACH_DECSTATION is not set
+-# CONFIG_MIPS_EV64120 is not set
+-# CONFIG_MIPS_EV96100 is not set
+-# CONFIG_MIPS_IVR is not set
+-# CONFIG_MIPS_ITE8172 is not set
+-# CONFIG_MACH_JAZZ is not set
+-# CONFIG_LASAT is not set
+-# CONFIG_MIPS_ATLAS is not set
+-# CONFIG_MIPS_MALTA is not set
+-# CONFIG_MIPS_SEAD is not set
+-# CONFIG_MIPS_SIM is not set
+-# CONFIG_MOMENCO_JAGUAR_ATX is not set
+-# CONFIG_MOMENCO_OCELOT is not set
+-# CONFIG_MOMENCO_OCELOT_3 is not set
+-# CONFIG_MOMENCO_OCELOT_C is not set
+-# CONFIG_MOMENCO_OCELOT_G is not set
+-# CONFIG_MIPS_XXS1500 is not set
+-# CONFIG_PNX8550_V2PCI is not set
+-# CONFIG_PNX8550_JBS is not set
+-# CONFIG_DDB5074 is not set
+-CONFIG_DDB5476=y
+-# CONFIG_DDB5477 is not set
+-# CONFIG_MACH_VR41XX is not set
+-# CONFIG_PMC_YOSEMITE is not set
+-# CONFIG_QEMU is not set
+-# CONFIG_SGI_IP22 is not set
+-# CONFIG_SGI_IP27 is not set
+-# CONFIG_SGI_IP32 is not set
+-# CONFIG_SIBYTE_BIGSUR is not set
+-# CONFIG_SIBYTE_SWARM is not set
+-# CONFIG_SIBYTE_SENTOSA is not set
+-# CONFIG_SIBYTE_RHONE is not set
+-# CONFIG_SIBYTE_CARMEL is not set
+-# CONFIG_SIBYTE_PTSWARM is not set
+-# CONFIG_SIBYTE_LITTLESUR is not set
+-# CONFIG_SIBYTE_CRHINE is not set
+-# CONFIG_SIBYTE_CRHONE is not set
+-# CONFIG_SNI_RM200_PCI is not set
+-# CONFIG_TOSHIBA_JMR3927 is not set
+-# CONFIG_TOSHIBA_RBTX4927 is not set
+-# CONFIG_TOSHIBA_RBTX4938 is not set
+-CONFIG_RWSEM_GENERIC_SPINLOCK=y
+-CONFIG_GENERIC_FIND_NEXT_BIT=y
+-CONFIG_GENERIC_HWEIGHT=y
+-CONFIG_GENERIC_CALIBRATE_DELAY=y
+-CONFIG_DMA_NONCOHERENT=y
+-CONFIG_DMA_NEED_PCI_MAP_STATE=y
+-CONFIG_I8259=y
+-# CONFIG_CPU_BIG_ENDIAN is not set
+-CONFIG_CPU_LITTLE_ENDIAN=y
+-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+-CONFIG_IRQ_CPU=y
+-CONFIG_DDB5XXX_COMMON=y
+-CONFIG_MIPS_L1_CACHE_SHIFT=5
+-CONFIG_HAVE_STD_PC_SERIAL_PORT=y
+-
+-#
+-# CPU selection
+-#
+-# CONFIG_CPU_MIPS32_R1 is not set
+-# CONFIG_CPU_MIPS32_R2 is not set
+-# CONFIG_CPU_MIPS64_R1 is not set
+-# CONFIG_CPU_MIPS64_R2 is not set
+-# CONFIG_CPU_R3000 is not set
+-# CONFIG_CPU_TX39XX is not set
+-# CONFIG_CPU_VR41XX is not set
+-# CONFIG_CPU_R4300 is not set
+-# CONFIG_CPU_R4X00 is not set
+-# CONFIG_CPU_TX49XX is not set
+-# CONFIG_CPU_R5000 is not set
+-CONFIG_CPU_R5432=y
+-# CONFIG_CPU_R6000 is not set
+-# CONFIG_CPU_NEVADA is not set
+-# CONFIG_CPU_R8000 is not set
+-# CONFIG_CPU_R10000 is not set
+-# CONFIG_CPU_RM7000 is not set
+-# CONFIG_CPU_RM9000 is not set
+-# CONFIG_CPU_SB1 is not set
+-CONFIG_SYS_HAS_CPU_R5432=y
+-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+-CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
+-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+-CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
+-
+-#
+-# Kernel type
+-#
+-CONFIG_32BIT=y
+-# CONFIG_64BIT is not set
+-CONFIG_PAGE_SIZE_4KB=y
+-# CONFIG_PAGE_SIZE_8KB is not set
+-# CONFIG_PAGE_SIZE_16KB is not set
+-# CONFIG_PAGE_SIZE_64KB is not set
+-# CONFIG_MIPS_MT is not set
+-CONFIG_CPU_HAS_LLSC=y
+-CONFIG_CPU_HAS_SYNC=y
+-CONFIG_GENERIC_HARDIRQS=y
+-CONFIG_GENERIC_IRQ_PROBE=y
+-CONFIG_ARCH_FLATMEM_ENABLE=y
+-CONFIG_SELECT_MEMORY_MODEL=y
+-CONFIG_FLATMEM_MANUAL=y
+-# CONFIG_DISCONTIGMEM_MANUAL is not set
+-# CONFIG_SPARSEMEM_MANUAL is not set
+-CONFIG_FLATMEM=y
+-CONFIG_FLAT_NODE_MEM_MAP=y
+-# CONFIG_SPARSEMEM_STATIC is not set
+-CONFIG_SPLIT_PTLOCK_CPUS=4
+-CONFIG_PREEMPT_NONE=y
+-# CONFIG_PREEMPT_VOLUNTARY is not set
+-# CONFIG_PREEMPT is not set
+-
+-#
+-# Code maturity level options
+-#
+-CONFIG_EXPERIMENTAL=y
+-CONFIG_BROKEN_ON_SMP=y
+-CONFIG_INIT_ENV_ARG_LIMIT=32
+-
+-#
+-# General setup
+-#
+-CONFIG_LOCALVERSION=""
+-CONFIG_LOCALVERSION_AUTO=y
+-CONFIG_SWAP=y
+-CONFIG_SYSVIPC=y
+-# CONFIG_POSIX_MQUEUE is not set
+-# CONFIG_BSD_PROCESS_ACCT is not set
+-CONFIG_SYSCTL=y
+-# CONFIG_AUDIT is not set
+-# CONFIG_IKCONFIG is not set
+-CONFIG_RELAY=y
+-CONFIG_INITRAMFS_SOURCE=""
+-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+-CONFIG_EMBEDDED=y
+-CONFIG_KALLSYMS=y
+-# CONFIG_KALLSYMS_EXTRA_PASS is not set
+-CONFIG_HOTPLUG=y
+-CONFIG_PRINTK=y
+-CONFIG_BUG=y
+-CONFIG_ELF_CORE=y
+-CONFIG_BASE_FULL=y
+-CONFIG_FUTEX=y
+-CONFIG_EPOLL=y
+-CONFIG_SHMEM=y
+-CONFIG_SLAB=y
+-# CONFIG_TINY_SHMEM is not set
+-CONFIG_BASE_SMALL=0
+-# CONFIG_SLOB is not set
+-
+-#
+-# Loadable module support
+-#
+-# CONFIG_MODULES is not set
+-
+-#
+-# Block layer
+-#
+-# CONFIG_LBD is not set
+-# CONFIG_BLK_DEV_IO_TRACE is not set
+-# CONFIG_LSF is not set
+-
+-#
+-# IO Schedulers
+-#
+-CONFIG_IOSCHED_NOOP=y
+-CONFIG_IOSCHED_AS=y
+-CONFIG_IOSCHED_DEADLINE=y
+-CONFIG_IOSCHED_CFQ=y
+-CONFIG_DEFAULT_AS=y
+-# CONFIG_DEFAULT_DEADLINE is not set
+-# CONFIG_DEFAULT_CFQ is not set
+-# CONFIG_DEFAULT_NOOP is not set
+-CONFIG_DEFAULT_IOSCHED="anticipatory"
+-
+-#
+-# Bus options (PCI, PCMCIA, EISA, ISA, TC)
+-#
+-CONFIG_HW_HAS_PCI=y
+-CONFIG_PCI=y
+-CONFIG_ISA=y
+-CONFIG_MMU=y
+-
+-#
+-# PCCARD (PCMCIA/CardBus) support
+-#
+-# CONFIG_PCCARD is not set
+-
+-#
+-# PCI Hotplug Support
+-#
+-# CONFIG_HOTPLUG_PCI is not set
+-
+-#
+-# Executable file formats
+-#
+-CONFIG_BINFMT_ELF=y
+-# CONFIG_BINFMT_MISC is not set
+-CONFIG_TRAD_SIGNALS=y
+-
+-#
+-# Networking
+-#
+-CONFIG_NET=y
+-
+-#
+-# Networking options
+-#
+-# CONFIG_NETDEBUG is not set
+-CONFIG_PACKET=y
+-# CONFIG_PACKET_MMAP is not set
+-CONFIG_UNIX=y
+-CONFIG_XFRM=y
+-CONFIG_XFRM_USER=y
+-CONFIG_NET_KEY=y
+-CONFIG_INET=y
+-# CONFIG_IP_MULTICAST is not set
+-# CONFIG_IP_ADVANCED_ROUTER is not set
+-CONFIG_IP_FIB_HASH=y
+-CONFIG_IP_PNP=y
+-# CONFIG_IP_PNP_DHCP is not set
+-CONFIG_IP_PNP_BOOTP=y
+-# CONFIG_IP_PNP_RARP is not set
+-# CONFIG_NET_IPIP is not set
+-# CONFIG_NET_IPGRE is not set
+-# CONFIG_ARPD is not set
+-# CONFIG_SYN_COOKIES is not set
+-# CONFIG_INET_AH is not set
+-# CONFIG_INET_ESP is not set
+-# CONFIG_INET_IPCOMP is not set
+-# CONFIG_INET_XFRM_TUNNEL is not set
+-# CONFIG_INET_TUNNEL is not set
+-CONFIG_INET_DIAG=y
+-CONFIG_INET_TCP_DIAG=y
+-# CONFIG_TCP_CONG_ADVANCED is not set
+-CONFIG_TCP_CONG_BIC=y
+-# CONFIG_IPV6 is not set
+-# CONFIG_INET6_XFRM_TUNNEL is not set
+-# CONFIG_INET6_TUNNEL is not set
+-# CONFIG_NETFILTER is not set
+-
+-#
+-# DCCP Configuration (EXPERIMENTAL)
+-#
+-# CONFIG_IP_DCCP is not set
+-
+-#
+-# SCTP Configuration (EXPERIMENTAL)
+-#
+-# CONFIG_IP_SCTP is not set
+-
+-#
+-# TIPC Configuration (EXPERIMENTAL)
+-#
+-# CONFIG_TIPC is not set
+-# CONFIG_ATM is not set
+-# CONFIG_BRIDGE is not set
+-# CONFIG_VLAN_8021Q is not set
+-# CONFIG_DECNET is not set
+-# CONFIG_LLC2 is not set
+-# CONFIG_IPX is not set
+-# CONFIG_ATALK is not set
+-# CONFIG_X25 is not set
+-# CONFIG_LAPB is not set
+-# CONFIG_NET_DIVERT is not set
+-# CONFIG_ECONET is not set
+-# CONFIG_WAN_ROUTER is not set
+-
+-#
+-# QoS and/or fair queueing
+-#
+-# CONFIG_NET_SCHED is not set
+-
+-#
+-# Network testing
+-#
+-# CONFIG_NET_PKTGEN is not set
+-# CONFIG_HAMRADIO is not set
+-# CONFIG_IRDA is not set
+-# CONFIG_BT is not set
+-CONFIG_IEEE80211=y
+-# CONFIG_IEEE80211_DEBUG is not set
+-CONFIG_IEEE80211_CRYPT_WEP=y
+-CONFIG_IEEE80211_CRYPT_CCMP=y
+-CONFIG_IEEE80211_SOFTMAC=y
+-# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
+-CONFIG_WIRELESS_EXT=y
+-
+-#
+-# Device Drivers
+-#
+-
+-#
+-# Generic Driver Options
+-#
+-CONFIG_STANDALONE=y
+-CONFIG_PREVENT_FIRMWARE_BUILD=y
+-CONFIG_FW_LOADER=y
+-
+-#
+-# Connector - unified userspace <-> kernelspace linker
+-#
+-CONFIG_CONNECTOR=y
+-CONFIG_PROC_EVENTS=y
+-
+-#
+-# Memory Technology Devices (MTD)
+-#
+-# CONFIG_MTD is not set
+-
+-#
+-# Parallel port support
+-#
+-# CONFIG_PARPORT is not set
+-
+-#
+-# Plug and Play support
+-#
+-# CONFIG_PNP is not set
+-
+-#
+-# Block devices
+-#
+-# CONFIG_BLK_CPQ_DA is not set
+-# CONFIG_BLK_CPQ_CISS_DA is not set
+-# CONFIG_BLK_DEV_DAC960 is not set
+-# CONFIG_BLK_DEV_UMEM is not set
+-# CONFIG_BLK_DEV_COW_COMMON is not set
+-# CONFIG_BLK_DEV_LOOP is not set
+-# CONFIG_BLK_DEV_NBD is not set
+-# CONFIG_BLK_DEV_SX8 is not set
+-# CONFIG_BLK_DEV_RAM is not set
+-# CONFIG_BLK_DEV_INITRD is not set
+-CONFIG_CDROM_PKTCDVD=y
+-CONFIG_CDROM_PKTCDVD_BUFFERS=8
+-# CONFIG_CDROM_PKTCDVD_WCACHE is not set
+-CONFIG_ATA_OVER_ETH=y
+-
+-#
+-# ATA/ATAPI/MFM/RLL support
+-#
+-CONFIG_IDE=y
+-CONFIG_BLK_DEV_IDE=y
+-
+-#
+-# Please see Documentation/ide.txt for help/info on IDE drives
+-#
+-# CONFIG_BLK_DEV_IDE_SATA is not set
+-CONFIG_BLK_DEV_IDEDISK=y
+-# CONFIG_IDEDISK_MULTI_MODE is not set
+-# CONFIG_BLK_DEV_IDECD is not set
+-# CONFIG_BLK_DEV_IDETAPE is not set
+-# CONFIG_BLK_DEV_IDEFLOPPY is not set
+-# CONFIG_IDE_TASK_IOCTL is not set
+-
+-#
+-# IDE chipset support/bugfixes
+-#
+-CONFIG_IDE_GENERIC=y
+-# CONFIG_BLK_DEV_IDEPCI is not set
+-# CONFIG_IDE_ARM is not set
+-# CONFIG_IDE_CHIPSETS is not set
+-# CONFIG_BLK_DEV_IDEDMA is not set
+-# CONFIG_IDEDMA_AUTO is not set
+-# CONFIG_BLK_DEV_HD is not set
+-
+-#
+-# SCSI device support
+-#
+-CONFIG_RAID_ATTRS=y
+-# CONFIG_SCSI is not set
+-
+-#
+-# Old CD-ROM drivers (not SCSI, not IDE)
+-#
+-# CONFIG_CD_NO_IDESCSI is not set
+-
+-#
+-# Multi-device support (RAID and LVM)
+-#
+-# CONFIG_MD is not set
+-
+-#
+-# Fusion MPT device support
+-#
+-# CONFIG_FUSION is not set
+-
+-#
+-# IEEE 1394 (FireWire) support
+-#
+-# CONFIG_IEEE1394 is not set
+-
+-#
+-# I2O device support
+-#
+-# CONFIG_I2O is not set
+-
+-#
+-# Network device support
+-#
+-CONFIG_NETDEVICES=y
+-# CONFIG_DUMMY is not set
+-# CONFIG_BONDING is not set
+-# CONFIG_EQUALIZER is not set
+-# CONFIG_TUN is not set
+-
+-#
+-# ARCnet devices
+-#
+-# CONFIG_ARCNET is not set
+-
+-#
+-# PHY device support
+-#
+-CONFIG_PHYLIB=y
+-
+-#
+-# MII PHY device drivers
+-#
+-CONFIG_MARVELL_PHY=y
+-CONFIG_DAVICOM_PHY=y
+-CONFIG_QSEMI_PHY=y
+-CONFIG_LXT_PHY=y
+-CONFIG_CICADA_PHY=y
+-
+-#
+-# Ethernet (10 or 100Mbit)
+-#
+-CONFIG_NET_ETHERNET=y
+-# CONFIG_MII is not set
+-# CONFIG_HAPPYMEAL is not set
+-# CONFIG_SUNGEM is not set
+-# CONFIG_CASSINI is not set
+-# CONFIG_NET_VENDOR_3COM is not set
+-# CONFIG_NET_VENDOR_SMC is not set
+-# CONFIG_DM9000 is not set
+-# CONFIG_NET_VENDOR_RACAL is not set
+-
+-#
+-# Tulip family network device support
+-#
+-# CONFIG_NET_TULIP is not set
+-# CONFIG_AT1700 is not set
+-# CONFIG_DEPCA is not set
+-# CONFIG_HP100 is not set
+-# CONFIG_NET_ISA is not set
+-# CONFIG_NET_PCI is not set
+-
+-#
+-# Ethernet (1000 Mbit)
+-#
+-# CONFIG_ACENIC is not set
+-# CONFIG_DL2K is not set
+-# CONFIG_E1000 is not set
+-# CONFIG_NS83820 is not set
+-# CONFIG_HAMACHI is not set
+-# CONFIG_YELLOWFIN is not set
+-# CONFIG_R8169 is not set
+-# CONFIG_SIS190 is not set
+-# CONFIG_SKGE is not set
+-# CONFIG_SKY2 is not set
+-# CONFIG_SK98LIN is not set
+-# CONFIG_TIGON3 is not set
+-# CONFIG_BNX2 is not set
+-
+-#
+-# Ethernet (10000 Mbit)
+-#
+-# CONFIG_CHELSIO_T1 is not set
+-# CONFIG_IXGB is not set
+-# CONFIG_S2IO is not set
+-
+-#
+-# Token Ring devices
+-#
+-# CONFIG_TR is not set
+-
+-#
+-# Wireless LAN (non-hamradio)
+-#
+-# CONFIG_NET_RADIO is not set
+-
+-#
+-# Wan interfaces
+-#
+-# CONFIG_WAN is not set
+-# CONFIG_FDDI is not set
+-# CONFIG_HIPPI is not set
+-# CONFIG_PPP is not set
+-# CONFIG_SLIP is not set
+-# CONFIG_SHAPER is not set
+-# CONFIG_NETCONSOLE is not set
+-# CONFIG_NETPOLL is not set
+-# CONFIG_NET_POLL_CONTROLLER is not set
+-
+-#
+-# ISDN subsystem
+-#
+-# CONFIG_ISDN is not set
+-
+-#
+-# Telephony Support
+-#
+-# CONFIG_PHONE is not set
+-
+-#
+-# Input device support
+-#
+-CONFIG_INPUT=y
+-
+-#
+-# Userland interfaces
+-#
+-CONFIG_INPUT_MOUSEDEV=y
+-CONFIG_INPUT_MOUSEDEV_PSAUX=y
+-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+-# CONFIG_INPUT_JOYDEV is not set
+-# CONFIG_INPUT_TSDEV is not set
+-# CONFIG_INPUT_EVDEV is not set
+-# CONFIG_INPUT_EVBUG is not set
+-
+-#
+-# Input Device Drivers
+-#
+-# CONFIG_INPUT_KEYBOARD is not set
+-# CONFIG_INPUT_MOUSE is not set
+-# CONFIG_INPUT_JOYSTICK is not set
+-# CONFIG_INPUT_TOUCHSCREEN is not set
+-# CONFIG_INPUT_MISC is not set
+-
+-#
+-# Hardware I/O ports
+-#
+-CONFIG_SERIO=y
+-# CONFIG_SERIO_I8042 is not set
+-CONFIG_SERIO_SERPORT=y
+-# CONFIG_SERIO_PCIPS2 is not set
+-# CONFIG_SERIO_LIBPS2 is not set
+-CONFIG_SERIO_RAW=y
+-# CONFIG_GAMEPORT is not set
+-
+-#
+-# Character devices
+-#
+-CONFIG_VT=y
+-CONFIG_VT_CONSOLE=y
+-CONFIG_HW_CONSOLE=y
+-# CONFIG_SERIAL_NONSTANDARD is not set
+-
+-#
+-# Serial drivers
+-#
+-CONFIG_SERIAL_8250=y
+-CONFIG_SERIAL_8250_CONSOLE=y
+-CONFIG_SERIAL_8250_PCI=y
+-CONFIG_SERIAL_8250_NR_UARTS=4
+-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+-# CONFIG_SERIAL_8250_EXTENDED is not set
+-
+-#
+-# Non-8250 serial port support
+-#
+-CONFIG_SERIAL_CORE=y
+-CONFIG_SERIAL_CORE_CONSOLE=y
+-# CONFIG_SERIAL_JSM is not set
+-CONFIG_UNIX98_PTYS=y
+-CONFIG_LEGACY_PTYS=y
+-CONFIG_LEGACY_PTY_COUNT=256
+-
+-#
+-# IPMI
+-#
+-# CONFIG_IPMI_HANDLER is not set
+-
+-#
+-# Watchdog Cards
+-#
+-# CONFIG_WATCHDOG is not set
+-# CONFIG_RTC is not set
+-# CONFIG_GEN_RTC is not set
+-# CONFIG_DTLK is not set
+-# CONFIG_R3964 is not set
+-# CONFIG_APPLICOM is not set
+-
+-#
+-# Ftape, the floppy tape device driver
+-#
+-# CONFIG_DRM is not set
+-# CONFIG_RAW_DRIVER is not set
+-
+-#
+-# TPM devices
+-#
+-# CONFIG_TCG_TPM is not set
+-# CONFIG_TELCLOCK is not set
+-
+-#
+-# I2C support
+-#
+-# CONFIG_I2C is not set
+-
+-#
+-# SPI support
+-#
+-# CONFIG_SPI is not set
+-# CONFIG_SPI_MASTER is not set
+-
+-#
+-# Dallas's 1-wire bus
+-#
+-# CONFIG_W1 is not set
+-
+-#
+-# Hardware Monitoring support
+-#
+-# CONFIG_HWMON is not set
+-# CONFIG_HWMON_VID is not set
+-
+-#
+-# Misc devices
+-#
+-
+-#
+-# Multimedia devices
+-#
+-# CONFIG_VIDEO_DEV is not set
+-
+-#
+-# Digital Video Broadcasting Devices
+-#
+-# CONFIG_DVB is not set
+-
+-#
+-# Graphics support
+-#
+-CONFIG_FB=y
+-# CONFIG_FB_CFB_FILLRECT is not set
+-# CONFIG_FB_CFB_COPYAREA is not set
+-# CONFIG_FB_CFB_IMAGEBLIT is not set
+-# CONFIG_FB_MACMODES is not set
+-CONFIG_FB_FIRMWARE_EDID=y
+-# CONFIG_FB_MODE_HELPERS is not set
+-# CONFIG_FB_TILEBLITTING is not set
+-# CONFIG_FB_CIRRUS is not set
+-# CONFIG_FB_PM2 is not set
+-# CONFIG_FB_CYBER2000 is not set
+-# CONFIG_FB_ASILIANT is not set
+-# CONFIG_FB_IMSTT is not set
+-# CONFIG_FB_S1D13XXX is not set
+-# CONFIG_FB_NVIDIA is not set
+-# CONFIG_FB_RIVA is not set
+-# CONFIG_FB_MATROX is not set
+-# CONFIG_FB_RADEON is not set
+-# CONFIG_FB_ATY128 is not set
+-# CONFIG_FB_ATY is not set
+-# CONFIG_FB_SAVAGE is not set
+-# CONFIG_FB_SIS is not set
+-# CONFIG_FB_NEOMAGIC is not set
+-# CONFIG_FB_KYRO is not set
+-# CONFIG_FB_3DFX is not set
+-# CONFIG_FB_VOODOO1 is not set
+-# CONFIG_FB_SMIVGX is not set
+-# CONFIG_FB_TRIDENT is not set
+-# CONFIG_FB_VIRTUAL is not set
+-
+-#
+-# Console display driver support
+-#
+-# CONFIG_VGA_CONSOLE is not set
+-# CONFIG_MDA_CONSOLE is not set
+-CONFIG_DUMMY_CONSOLE=y
+-# CONFIG_FRAMEBUFFER_CONSOLE is not set
+-
+-#
+-# Logo configuration
+-#
+-# CONFIG_LOGO is not set
+-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+-
+-#
+-# Sound
+-#
+-# CONFIG_SOUND is not set
+-
+-#
+-# USB support
+-#
+-CONFIG_USB_ARCH_HAS_HCD=y
+-CONFIG_USB_ARCH_HAS_OHCI=y
+-CONFIG_USB_ARCH_HAS_EHCI=y
+-# CONFIG_USB is not set
+-
+-#
+-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+-#
+-
+-#
+-# USB Gadget Support
+-#
+-# CONFIG_USB_GADGET is not set
+-
+-#
+-# MMC/SD Card support
+-#
+-# CONFIG_MMC is not set
+-
+-#
+-# LED devices
+-#
+-# CONFIG_NEW_LEDS is not set
+-
+-#
+-# LED drivers
+-#
+-
+-#
+-# LED Triggers
+-#
+-
+-#
+-# InfiniBand support
+-#
+-# CONFIG_INFINIBAND is not set
+-
+-#
+-# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
+-#
+-
+-#
+-# Real Time Clock
+-#
+-# CONFIG_RTC_CLASS is not set
+-
+-#
+-# File systems
+-#
+-CONFIG_EXT2_FS=y
+-# CONFIG_EXT2_FS_XATTR is not set
+-# CONFIG_EXT2_FS_XIP is not set
+-# CONFIG_EXT3_FS is not set
+-# CONFIG_REISERFS_FS is not set
+-# CONFIG_JFS_FS is not set
+-# CONFIG_FS_POSIX_ACL is not set
+-# CONFIG_XFS_FS is not set
+-# CONFIG_OCFS2_FS is not set
+-# CONFIG_MINIX_FS is not set
+-# CONFIG_ROMFS_FS is not set
+-CONFIG_INOTIFY=y
+-# CONFIG_QUOTA is not set
+-CONFIG_DNOTIFY=y
+-# CONFIG_AUTOFS_FS is not set
+-# CONFIG_AUTOFS4_FS is not set
+-CONFIG_FUSE_FS=y
+-
+-#
+-# CD-ROM/DVD Filesystems
+-#
+-# CONFIG_ISO9660_FS is not set
+-# CONFIG_UDF_FS is not set
+-
+-#
+-# DOS/FAT/NT Filesystems
+-#
+-# CONFIG_MSDOS_FS is not set
+-# CONFIG_VFAT_FS is not set
+-# CONFIG_NTFS_FS is not set
+-
+-#
+-# Pseudo filesystems
+-#
+-CONFIG_PROC_FS=y
+-CONFIG_PROC_KCORE=y
+-CONFIG_SYSFS=y
+-# CONFIG_TMPFS is not set
+-# CONFIG_HUGETLB_PAGE is not set
+-CONFIG_RAMFS=y
+-# CONFIG_CONFIGFS_FS is not set
+-
+-#
+-# Miscellaneous filesystems
+-#
+-# CONFIG_ADFS_FS is not set
+-# CONFIG_AFFS_FS is not set
+-# CONFIG_HFS_FS is not set
+-# CONFIG_HFSPLUS_FS is not set
+-# CONFIG_BEFS_FS is not set
+-# CONFIG_BFS_FS is not set
+-# CONFIG_EFS_FS is not set
+-# CONFIG_CRAMFS is not set
+-# CONFIG_VXFS_FS is not set
+-# CONFIG_HPFS_FS is not set
+-# CONFIG_QNX4FS_FS is not set
+-# CONFIG_SYSV_FS is not set
+-# CONFIG_UFS_FS is not set
+-
+-#
+-# Network File Systems
+-#
+-CONFIG_NFS_FS=y
+-# CONFIG_NFS_V3 is not set
+-# CONFIG_NFS_V4 is not set
+-# CONFIG_NFS_DIRECTIO is not set
+-# CONFIG_NFSD is not set
+-CONFIG_ROOT_NFS=y
+-CONFIG_LOCKD=y
+-CONFIG_NFS_COMMON=y
+-CONFIG_SUNRPC=y
+-# CONFIG_RPCSEC_GSS_KRB5 is not set
+-# CONFIG_RPCSEC_GSS_SPKM3 is not set
+-# CONFIG_SMB_FS is not set
+-# CONFIG_CIFS is not set
+-# CONFIG_NCP_FS is not set
+-# CONFIG_CODA_FS is not set
+-# CONFIG_AFS_FS is not set
+-# CONFIG_9P_FS is not set
+-
+-#
+-# Partition Types
+-#
+-# CONFIG_PARTITION_ADVANCED is not set
+-CONFIG_MSDOS_PARTITION=y
+-
+-#
+-# Native Language Support
+-#
+-# CONFIG_NLS is not set
+-
+-#
+-# Profiling support
+-#
+-# CONFIG_PROFILING is not set
+-
+-#
+-# Kernel hacking
+-#
+-# CONFIG_PRINTK_TIME is not set
+-# CONFIG_MAGIC_SYSRQ is not set
+-# CONFIG_DEBUG_KERNEL is not set
+-CONFIG_LOG_BUF_SHIFT=14
+-# CONFIG_DEBUG_FS is not set
+-# CONFIG_UNWIND_INFO is not set
+-CONFIG_CROSSCOMPILE=y
+-CONFIG_CMDLINE="ip=any"
+-
+-#
+-# Security options
+-#
+-CONFIG_KEYS=y
+-CONFIG_KEYS_DEBUG_PROC_KEYS=y
+-# CONFIG_SECURITY is not set
+-
+-#
+-# Cryptographic options
+-#
+-CONFIG_CRYPTO=y
+-CONFIG_CRYPTO_HMAC=y
+-CONFIG_CRYPTO_NULL=y
+-CONFIG_CRYPTO_MD4=y
+-CONFIG_CRYPTO_MD5=y
+-CONFIG_CRYPTO_SHA1=y
+-CONFIG_CRYPTO_SHA256=y
+-CONFIG_CRYPTO_SHA512=y
+-CONFIG_CRYPTO_WP512=y
+-CONFIG_CRYPTO_TGR192=y
+-CONFIG_CRYPTO_DES=y
+-CONFIG_CRYPTO_BLOWFISH=y
+-CONFIG_CRYPTO_TWOFISH=y
+-CONFIG_CRYPTO_SERPENT=y
+-CONFIG_CRYPTO_AES=y
+-CONFIG_CRYPTO_CAST5=y
+-CONFIG_CRYPTO_CAST6=y
+-CONFIG_CRYPTO_TEA=y
+-CONFIG_CRYPTO_ARC4=y
+-CONFIG_CRYPTO_KHAZAD=y
+-CONFIG_CRYPTO_ANUBIS=y
+-CONFIG_CRYPTO_DEFLATE=y
+-CONFIG_CRYPTO_MICHAEL_MIC=y
+-CONFIG_CRYPTO_CRC32C=y
+-# CONFIG_CRYPTO_TEST is not set
+-
+-#
+-# Hardware crypto devices
+-#
+-
+-#
+-# Library routines
+-#
+-# CONFIG_CRC_CCITT is not set
+-CONFIG_CRC16=y
+-CONFIG_CRC32=y
+-CONFIG_LIBCRC32C=y
+-CONFIG_ZLIB_INFLATE=y
+-CONFIG_ZLIB_DEFLATE=y
+diff -Naur linux-2.6.17.orig/arch/mips/configs/ddb5477_defconfig linux-2.6.17/arch/mips/configs/ddb5477_defconfig
+--- linux-2.6.17.orig/arch/mips/configs/ddb5477_defconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/configs/ddb5477_defconfig	2006-06-19 18:16:13.000000000 -0700
+@@ -41,8 +41,6 @@
+ # CONFIG_MIPS_XXS1500 is not set
+ # CONFIG_PNX8550_V2PCI is not set
+ # CONFIG_PNX8550_JBS is not set
+-# CONFIG_DDB5074 is not set
+-# CONFIG_DDB5476 is not set
+ CONFIG_DDB5477=y
+ # CONFIG_MACH_VR41XX is not set
+ # CONFIG_PMC_YOSEMITE is not set
+@@ -68,6 +66,7 @@
+ CONFIG_GENERIC_FIND_NEXT_BIT=y
+ CONFIG_GENERIC_HWEIGHT=y
+ CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+ CONFIG_DMA_NONCOHERENT=y
+ CONFIG_DMA_NEED_PCI_MAP_STATE=y
+ CONFIG_I8259=y
+diff -Naur linux-2.6.17.orig/arch/mips/configs/decstation_defconfig linux-2.6.17/arch/mips/configs/decstation_defconfig
+--- linux-2.6.17.orig/arch/mips/configs/decstation_defconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/configs/decstation_defconfig	2006-06-19 18:16:13.000000000 -0700
+@@ -41,8 +41,6 @@
+ # CONFIG_MIPS_XXS1500 is not set
+ # CONFIG_PNX8550_V2PCI is not set
+ # CONFIG_PNX8550_JBS is not set
+-# CONFIG_DDB5074 is not set
+-# CONFIG_DDB5476 is not set
+ # CONFIG_DDB5477 is not set
+ # CONFIG_MACH_VR41XX is not set
+ # CONFIG_PMC_YOSEMITE is not set
+@@ -68,6 +66,7 @@
+ CONFIG_GENERIC_FIND_NEXT_BIT=y
+ CONFIG_GENERIC_HWEIGHT=y
+ CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+ CONFIG_DMA_NONCOHERENT=y
+ CONFIG_DMA_NEED_PCI_MAP_STATE=y
+ # CONFIG_CPU_BIG_ENDIAN is not set
+diff -Naur linux-2.6.17.orig/arch/mips/configs/e55_defconfig linux-2.6.17/arch/mips/configs/e55_defconfig
+--- linux-2.6.17.orig/arch/mips/configs/e55_defconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/configs/e55_defconfig	2006-06-19 18:16:13.000000000 -0700
+@@ -41,8 +41,6 @@
+ # CONFIG_MIPS_XXS1500 is not set
+ # CONFIG_PNX8550_V2PCI is not set
+ # CONFIG_PNX8550_JBS is not set
+-# CONFIG_DDB5074 is not set
+-# CONFIG_DDB5476 is not set
+ # CONFIG_DDB5477 is not set
+ CONFIG_MACH_VR41XX=y
+ # CONFIG_PMC_YOSEMITE is not set
+@@ -73,6 +71,7 @@
+ CONFIG_GENERIC_FIND_NEXT_BIT=y
+ CONFIG_GENERIC_HWEIGHT=y
+ CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+ CONFIG_DMA_NONCOHERENT=y
+ CONFIG_DMA_NEED_PCI_MAP_STATE=y
+ # CONFIG_CPU_BIG_ENDIAN is not set
+diff -Naur linux-2.6.17.orig/arch/mips/configs/emma2rh_defconfig linux-2.6.17/arch/mips/configs/emma2rh_defconfig
+--- linux-2.6.17.orig/arch/mips/configs/emma2rh_defconfig	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/arch/mips/configs/emma2rh_defconfig	2006-06-19 18:16:13.000000000 -0700
+@@ -0,0 +1,1198 @@
++#
++# Automatically generated make config: don't edit
++# Linux kernel version: 2.6.17
++# Sun Jun 18 13:46:53 2006
++#
++CONFIG_MIPS=y
++
++#
++# Machine selection
++#
++# CONFIG_MIPS_MTX1 is not set
++# CONFIG_MIPS_BOSPORUS is not set
++# CONFIG_MIPS_PB1000 is not set
++# CONFIG_MIPS_PB1100 is not set
++# CONFIG_MIPS_PB1500 is not set
++# CONFIG_MIPS_PB1550 is not set
++# CONFIG_MIPS_PB1200 is not set
++# CONFIG_MIPS_DB1000 is not set
++# CONFIG_MIPS_DB1100 is not set
++# CONFIG_MIPS_DB1500 is not set
++# CONFIG_MIPS_DB1550 is not set
++# CONFIG_MIPS_DB1200 is not set
++# CONFIG_MIPS_MIRAGE is not set
++# CONFIG_MIPS_COBALT is not set
++# CONFIG_MACH_DECSTATION is not set
++# CONFIG_MIPS_EV64120 is not set
++# CONFIG_MIPS_EV96100 is not set
++# CONFIG_MIPS_IVR is not set
++# CONFIG_MIPS_ITE8172 is not set
++# CONFIG_MACH_JAZZ is not set
++# CONFIG_LASAT is not set
++# CONFIG_MIPS_ATLAS is not set
++# CONFIG_MIPS_MALTA is not set
++# CONFIG_MIPS_SEAD is not set
++# CONFIG_WR_PPMC is not set
++# CONFIG_MIPS_SIM is not set
++# CONFIG_MOMENCO_JAGUAR_ATX is not set
++# CONFIG_MOMENCO_OCELOT is not set
++# CONFIG_MOMENCO_OCELOT_3 is not set
++# CONFIG_MOMENCO_OCELOT_C is not set
++# CONFIG_MOMENCO_OCELOT_G is not set
++# CONFIG_MIPS_XXS1500 is not set
++# CONFIG_PNX8550_V2PCI is not set
++# CONFIG_PNX8550_JBS is not set
++# CONFIG_DDB5477 is not set
++# CONFIG_MACH_VR41XX is not set
++# CONFIG_PMC_YOSEMITE is not set
++# CONFIG_QEMU is not set
++CONFIG_MARKEINS=y
++# CONFIG_SGI_IP22 is not set
++# CONFIG_SGI_IP27 is not set
++# CONFIG_SGI_IP32 is not set
++# CONFIG_SIBYTE_BIGSUR is not set
++# CONFIG_SIBYTE_SWARM is not set
++# CONFIG_SIBYTE_SENTOSA is not set
++# CONFIG_SIBYTE_RHONE is not set
++# CONFIG_SIBYTE_CARMEL is not set
++# CONFIG_SIBYTE_PTSWARM is not set
++# CONFIG_SIBYTE_LITTLESUR is not set
++# CONFIG_SIBYTE_CRHINE is not set
++# CONFIG_SIBYTE_CRHONE is not set
++# CONFIG_SNI_RM200_PCI is not set
++# CONFIG_TOSHIBA_JMR3927 is not set
++# CONFIG_TOSHIBA_RBTX4927 is not set
++# CONFIG_TOSHIBA_RBTX4938 is not set
++CONFIG_RWSEM_GENERIC_SPINLOCK=y
++CONFIG_GENERIC_FIND_NEXT_BIT=y
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
++CONFIG_DMA_NONCOHERENT=y
++CONFIG_DMA_NEED_PCI_MAP_STATE=y
++CONFIG_CPU_BIG_ENDIAN=y
++# CONFIG_CPU_LITTLE_ENDIAN is not set
++CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
++CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
++CONFIG_IRQ_CPU=y
++CONFIG_SWAP_IO_SPACE=y
++CONFIG_EMMA2RH=y
++CONFIG_MIPS_L1_CACHE_SHIFT=5
++
++#
++# CPU selection
++#
++# CONFIG_CPU_MIPS32_R1 is not set
++# CONFIG_CPU_MIPS32_R2 is not set
++# CONFIG_CPU_MIPS64_R1 is not set
++# CONFIG_CPU_MIPS64_R2 is not set
++# CONFIG_CPU_R3000 is not set
++# CONFIG_CPU_TX39XX is not set
++# CONFIG_CPU_VR41XX is not set
++# CONFIG_CPU_R4300 is not set
++# CONFIG_CPU_R4X00 is not set
++# CONFIG_CPU_TX49XX is not set
++CONFIG_CPU_R5000=y
++# CONFIG_CPU_R5432 is not set
++# CONFIG_CPU_R6000 is not set
++# CONFIG_CPU_NEVADA is not set
++# CONFIG_CPU_R8000 is not set
++# CONFIG_CPU_R10000 is not set
++# CONFIG_CPU_RM7000 is not set
++# CONFIG_CPU_RM9000 is not set
++# CONFIG_CPU_SB1 is not set
++CONFIG_SYS_HAS_CPU_R5000=y
++CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
++CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
++CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
++
++#
++# Kernel type
++#
++CONFIG_32BIT=y
++# CONFIG_64BIT is not set
++CONFIG_PAGE_SIZE_4KB=y
++# CONFIG_PAGE_SIZE_8KB is not set
++# CONFIG_PAGE_SIZE_16KB is not set
++# CONFIG_PAGE_SIZE_64KB is not set
++CONFIG_MIPS_MT_DISABLED=y
++# CONFIG_MIPS_MT_SMTC is not set
++# CONFIG_MIPS_MT_SMP is not set
++# CONFIG_MIPS_VPE_LOADER is not set
++# CONFIG_64BIT_PHYS_ADDR is not set
++CONFIG_CPU_HAS_LLSC=y
++CONFIG_CPU_HAS_SYNC=y
++CONFIG_GENERIC_HARDIRQS=y
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_ARCH_FLATMEM_ENABLE=y
++CONFIG_SELECT_MEMORY_MODEL=y
++CONFIG_FLATMEM_MANUAL=y
++# CONFIG_DISCONTIGMEM_MANUAL is not set
++# CONFIG_SPARSEMEM_MANUAL is not set
++CONFIG_FLATMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++# CONFIG_SPARSEMEM_STATIC is not set
++CONFIG_SPLIT_PTLOCK_CPUS=4
++# CONFIG_PREEMPT_NONE is not set
++# CONFIG_PREEMPT_VOLUNTARY is not set
++CONFIG_PREEMPT=y
++CONFIG_PREEMPT_BKL=y
++
++#
++# Code maturity level options
++#
++CONFIG_EXPERIMENTAL=y
++CONFIG_BROKEN_ON_SMP=y
++CONFIG_LOCK_KERNEL=y
++CONFIG_INIT_ENV_ARG_LIMIT=32
++
++#
++# General setup
++#
++CONFIG_LOCALVERSION=""
++CONFIG_LOCALVERSION_AUTO=y
++CONFIG_SWAP=y
++CONFIG_SYSVIPC=y
++CONFIG_POSIX_MQUEUE=y
++CONFIG_BSD_PROCESS_ACCT=y
++# CONFIG_BSD_PROCESS_ACCT_V3 is not set
++CONFIG_SYSCTL=y
++# CONFIG_AUDIT is not set
++CONFIG_IKCONFIG=y
++CONFIG_IKCONFIG_PROC=y
++# CONFIG_RELAY is not set
++CONFIG_INITRAMFS_SOURCE=""
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
++CONFIG_EMBEDDED=y
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_EXTRA_PASS is not set
++CONFIG_HOTPLUG=y
++CONFIG_PRINTK=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_EPOLL=y
++CONFIG_SHMEM=y
++CONFIG_SLAB=y
++# CONFIG_TINY_SHMEM is not set
++CONFIG_BASE_SMALL=0
++# CONFIG_SLOB is not set
++CONFIG_OBSOLETE_INTERMODULE=y
++
++#
++# Loadable module support
++#
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++CONFIG_MODULE_FORCE_UNLOAD=y
++CONFIG_MODVERSIONS=y
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++CONFIG_KMOD=y
++
++#
++# Block layer
++#
++CONFIG_LBD=y
++# CONFIG_BLK_DEV_IO_TRACE is not set
++# CONFIG_LSF is not set
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++CONFIG_IOSCHED_AS=y
++CONFIG_IOSCHED_DEADLINE=y
++CONFIG_IOSCHED_CFQ=y
++CONFIG_DEFAULT_AS=y
++# CONFIG_DEFAULT_DEADLINE is not set
++# CONFIG_DEFAULT_CFQ is not set
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="anticipatory"
++
++#
++# Bus options (PCI, PCMCIA, EISA, ISA, TC)
++#
++CONFIG_HW_HAS_PCI=y
++CONFIG_PCI=y
++CONFIG_MMU=y
++
++#
++# PCCARD (PCMCIA/CardBus) support
++#
++# CONFIG_PCCARD is not set
++
++#
++# PCI Hotplug Support
++#
++# CONFIG_HOTPLUG_PCI is not set
++
++#
++# Executable file formats
++#
++CONFIG_BINFMT_ELF=y
++# CONFIG_BINFMT_MISC is not set
++CONFIG_TRAD_SIGNALS=y
++
++#
++# Networking
++#
++CONFIG_NET=y
++
++#
++# Networking options
++#
++# CONFIG_NETDEBUG is not set
++CONFIG_PACKET=y
++CONFIG_PACKET_MMAP=y
++CONFIG_UNIX=y
++CONFIG_XFRM=y
++# CONFIG_XFRM_USER is not set
++CONFIG_NET_KEY=y
++CONFIG_INET=y
++CONFIG_IP_MULTICAST=y
++CONFIG_IP_ADVANCED_ROUTER=y
++CONFIG_ASK_IP_FIB_HASH=y
++# CONFIG_IP_FIB_TRIE is not set
++CONFIG_IP_FIB_HASH=y
++CONFIG_IP_MULTIPLE_TABLES=y
++# CONFIG_IP_ROUTE_FWMARK is not set
++CONFIG_IP_ROUTE_MULTIPATH=y
++# CONFIG_IP_ROUTE_MULTIPATH_CACHED is not set
++CONFIG_IP_ROUTE_VERBOSE=y
++CONFIG_IP_PNP=y
++# CONFIG_IP_PNP_DHCP is not set
++CONFIG_IP_PNP_BOOTP=y
++# CONFIG_IP_PNP_RARP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE is not set
++# CONFIG_IP_MROUTE is not set
++# CONFIG_ARPD is not set
++CONFIG_SYN_COOKIES=y
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++# CONFIG_INET_TUNNEL is not set
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_BIC=y
++
++#
++# IP: Virtual Server Configuration
++#
++# CONFIG_IP_VS is not set
++CONFIG_IPV6=m
++# CONFIG_IPV6_PRIVACY is not set
++# CONFIG_IPV6_ROUTER_PREF is not set
++# CONFIG_INET6_AH is not set
++# CONFIG_INET6_ESP is not set
++# CONFIG_INET6_IPCOMP is not set
++# CONFIG_INET6_XFRM_TUNNEL is not set
++# CONFIG_INET6_TUNNEL is not set
++# CONFIG_IPV6_TUNNEL is not set
++CONFIG_NETFILTER=y
++# CONFIG_NETFILTER_DEBUG is not set
++
++#
++# Core Netfilter Configuration
++#
++# CONFIG_NETFILTER_NETLINK is not set
++# CONFIG_NF_CONNTRACK is not set
++# CONFIG_NETFILTER_XTABLES is not set
++
++#
++# IP: Netfilter Configuration
++#
++# CONFIG_IP_NF_CONNTRACK is not set
++# CONFIG_IP_NF_QUEUE is not set
++
++#
++# IPv6: Netfilter Configuration (EXPERIMENTAL)
++#
++# CONFIG_IP6_NF_QUEUE is not set
++
++#
++# DCCP Configuration (EXPERIMENTAL)
++#
++# CONFIG_IP_DCCP is not set
++
++#
++# SCTP Configuration (EXPERIMENTAL)
++#
++CONFIG_IP_SCTP=m
++# CONFIG_SCTP_DBG_MSG is not set
++# CONFIG_SCTP_DBG_OBJCNT is not set
++# CONFIG_SCTP_HMAC_NONE is not set
++# CONFIG_SCTP_HMAC_SHA1 is not set
++CONFIG_SCTP_HMAC_MD5=y
++
++#
++# TIPC Configuration (EXPERIMENTAL)
++#
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_BRIDGE is not set
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_NET_DIVERT is not set
++# CONFIG_ECONET is not set
++# CONFIG_WAN_ROUTER is not set
++
++#
++# QoS and/or fair queueing
++#
++# CONFIG_NET_SCHED is not set
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_IEEE80211 is not set
++
++#
++# Device Drivers
++#
++
++#
++# Generic Driver Options
++#
++CONFIG_STANDALONE=y
++CONFIG_PREVENT_FIRMWARE_BUILD=y
++# CONFIG_FW_LOADER is not set
++
++#
++# Connector - unified userspace <-> kernelspace linker
++#
++# CONFIG_CONNECTOR is not set
++
++#
++# Memory Technology Devices (MTD)
++#
++CONFIG_MTD=y
++# CONFIG_MTD_DEBUG is not set
++# CONFIG_MTD_CONCAT is not set
++CONFIG_MTD_PARTITIONS=y
++# CONFIG_MTD_REDBOOT_PARTS is not set
++CONFIG_MTD_CMDLINE_PARTS=y
++
++#
++# User Modules And Translation Layers
++#
++CONFIG_MTD_CHAR=y
++CONFIG_MTD_BLOCK=y
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++CONFIG_MTD_CFI=y
++# CONFIG_MTD_JEDECPROBE is not set
++CONFIG_MTD_GEN_PROBE=y
++# CONFIG_MTD_CFI_ADV_OPTIONS is not set
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
++CONFIG_MTD_CFI_I1=y
++CONFIG_MTD_CFI_I2=y
++# CONFIG_MTD_CFI_I4 is not set
++# CONFIG_MTD_CFI_I8 is not set
++# CONFIG_MTD_CFI_INTELEXT is not set
++CONFIG_MTD_CFI_AMDSTD=y
++# CONFIG_MTD_CFI_STAA is not set
++CONFIG_MTD_CFI_UTIL=y
++# CONFIG_MTD_RAM is not set
++# CONFIG_MTD_ROM is not set
++# CONFIG_MTD_ABSENT is not set
++# CONFIG_MTD_OBSOLETE_CHIPS is not set
++
++#
++# Mapping drivers for chip access
++#
++# CONFIG_MTD_COMPLEX_MAPPINGS is not set
++CONFIG_MTD_PHYSMAP=y
++CONFIG_MTD_PHYSMAP_START=0x1e000000
++CONFIG_MTD_PHYSMAP_LEN=0x02000000
++CONFIG_MTD_PHYSMAP_BANKWIDTH=2
++# CONFIG_MTD_PLATRAM is not set
++
++#
++# Self-contained MTD device drivers
++#
++# CONFIG_MTD_PMC551 is not set
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++# CONFIG_MTD_BLOCK2MTD is not set
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOC2000 is not set
++# CONFIG_MTD_DOC2001 is not set
++# CONFIG_MTD_DOC2001PLUS is not set
++
++#
++# NAND Flash Device Drivers
++#
++# CONFIG_MTD_NAND is not set
++
++#
++# OneNAND Flash Device Drivers
++#
++# CONFIG_MTD_ONENAND is not set
++
++#
++# Parallel port support
++#
++# CONFIG_PARPORT is not set
++
++#
++# Plug and Play support
++#
++
++#
++# Block devices
++#
++# CONFIG_BLK_CPQ_DA is not set
++# CONFIG_BLK_CPQ_CISS_DA is not set
++# CONFIG_BLK_DEV_DAC960 is not set
++# CONFIG_BLK_DEV_UMEM is not set
++# CONFIG_BLK_DEV_COW_COMMON is not set
++CONFIG_BLK_DEV_LOOP=m
++CONFIG_BLK_DEV_CRYPTOLOOP=m
++# CONFIG_BLK_DEV_NBD is not set
++# CONFIG_BLK_DEV_SX8 is not set
++# CONFIG_BLK_DEV_RAM is not set
++# CONFIG_BLK_DEV_INITRD is not set
++# CONFIG_CDROM_PKTCDVD is not set
++# CONFIG_ATA_OVER_ETH is not set
++
++#
++# ATA/ATAPI/MFM/RLL support
++#
++# CONFIG_IDE is not set
++
++#
++# SCSI device support
++#
++# CONFIG_RAID_ATTRS is not set
++CONFIG_SCSI=m
++# CONFIG_SCSI_PROC_FS is not set
++
++#
++# SCSI support type (disk, tape, CD-ROM)
++#
++CONFIG_BLK_DEV_SD=m
++# CONFIG_CHR_DEV_ST is not set
++# CONFIG_CHR_DEV_OSST is not set
++# CONFIG_BLK_DEV_SR is not set
++CONFIG_CHR_DEV_SG=m
++# CONFIG_CHR_DEV_SCH is not set
++
++#
++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
++#
++# CONFIG_SCSI_MULTI_LUN is not set
++# CONFIG_SCSI_CONSTANTS is not set
++# CONFIG_SCSI_LOGGING is not set
++
++#
++# SCSI Transport Attributes
++#
++# CONFIG_SCSI_SPI_ATTRS is not set
++# CONFIG_SCSI_FC_ATTRS is not set
++# CONFIG_SCSI_ISCSI_ATTRS is not set
++# CONFIG_SCSI_SAS_ATTRS is not set
++
++#
++# SCSI low-level drivers
++#
++# CONFIG_ISCSI_TCP is not set
++# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
++# CONFIG_SCSI_3W_9XXX is not set
++# CONFIG_SCSI_ACARD is not set
++# CONFIG_SCSI_AACRAID is not set
++# CONFIG_SCSI_AIC7XXX is not set
++# CONFIG_SCSI_AIC7XXX_OLD is not set
++# CONFIG_SCSI_AIC79XX is not set
++# CONFIG_SCSI_DPT_I2O is not set
++# CONFIG_MEGARAID_NEWGEN is not set
++# CONFIG_MEGARAID_LEGACY is not set
++# CONFIG_MEGARAID_SAS is not set
++# CONFIG_SCSI_SATA is not set
++# CONFIG_SCSI_DMX3191D is not set
++# CONFIG_SCSI_FUTURE_DOMAIN is not set
++# CONFIG_SCSI_IPS is not set
++# CONFIG_SCSI_INITIO is not set
++# CONFIG_SCSI_INIA100 is not set
++# CONFIG_SCSI_SYM53C8XX_2 is not set
++# CONFIG_SCSI_IPR is not set
++# CONFIG_SCSI_QLOGIC_1280 is not set
++# CONFIG_SCSI_QLA_FC is not set
++# CONFIG_SCSI_LPFC is not set
++# CONFIG_SCSI_DC395x is not set
++# CONFIG_SCSI_DC390T is not set
++# CONFIG_SCSI_NSP32 is not set
++# CONFIG_SCSI_DEBUG is not set
++
++#
++# Multi-device support (RAID and LVM)
++#
++# CONFIG_MD is not set
++
++#
++# Fusion MPT device support
++#
++# CONFIG_FUSION is not set
++# CONFIG_FUSION_SPI is not set
++# CONFIG_FUSION_FC is not set
++# CONFIG_FUSION_SAS is not set
++
++#
++# IEEE 1394 (FireWire) support
++#
++# CONFIG_IEEE1394 is not set
++
++#
++# I2O device support
++#
++# CONFIG_I2O is not set
++
++#
++# Network device support
++#
++CONFIG_NETDEVICES=y
++# CONFIG_DUMMY is not set
++# CONFIG_BONDING is not set
++# CONFIG_EQUALIZER is not set
++CONFIG_TUN=m
++
++#
++# ARCnet devices
++#
++# CONFIG_ARCNET is not set
++
++#
++# PHY device support
++#
++# CONFIG_PHYLIB is not set
++
++#
++# Ethernet (10 or 100Mbit)
++#
++CONFIG_NET_ETHERNET=y
++CONFIG_MII=y
++# CONFIG_HAPPYMEAL is not set
++# CONFIG_SUNGEM is not set
++# CONFIG_CASSINI is not set
++# CONFIG_NET_VENDOR_3COM is not set
++# CONFIG_DM9000 is not set
++
++#
++# Tulip family network device support
++#
++# CONFIG_NET_TULIP is not set
++# CONFIG_HP100 is not set
++CONFIG_NET_PCI=y
++# CONFIG_PCNET32 is not set
++# CONFIG_AMD8111_ETH is not set
++# CONFIG_ADAPTEC_STARFIRE is not set
++# CONFIG_B44 is not set
++# CONFIG_FORCEDETH is not set
++# CONFIG_DGRS is not set
++# CONFIG_EEPRO100 is not set
++# CONFIG_E100 is not set
++# CONFIG_FEALNX is not set
++CONFIG_NATSEMI=y
++# CONFIG_NE2K_PCI is not set
++# CONFIG_8139CP is not set
++# CONFIG_8139TOO is not set
++# CONFIG_SIS900 is not set
++# CONFIG_EPIC100 is not set
++# CONFIG_SUNDANCE is not set
++# CONFIG_TLAN is not set
++# CONFIG_VIA_RHINE is not set
++# CONFIG_LAN_SAA9730 is not set
++
++#
++# Ethernet (1000 Mbit)
++#
++# CONFIG_ACENIC is not set
++# CONFIG_DL2K is not set
++# CONFIG_E1000 is not set
++# CONFIG_NS83820 is not set
++# CONFIG_HAMACHI is not set
++# CONFIG_YELLOWFIN is not set
++# CONFIG_R8169 is not set
++# CONFIG_SIS190 is not set
++# CONFIG_SKGE is not set
++# CONFIG_SKY2 is not set
++# CONFIG_SK98LIN is not set
++# CONFIG_VIA_VELOCITY is not set
++# CONFIG_TIGON3 is not set
++# CONFIG_BNX2 is not set
++
++#
++# Ethernet (10000 Mbit)
++#
++# CONFIG_CHELSIO_T1 is not set
++# CONFIG_IXGB is not set
++# CONFIG_S2IO is not set
++
++#
++# Token Ring devices
++#
++# CONFIG_TR is not set
++
++#
++# Wireless LAN (non-hamradio)
++#
++# CONFIG_NET_RADIO is not set
++
++#
++# Wan interfaces
++#
++# CONFIG_WAN is not set
++# CONFIG_FDDI is not set
++# CONFIG_HIPPI is not set
++CONFIG_PPP=m
++# CONFIG_PPP_MULTILINK is not set
++# CONFIG_PPP_FILTER is not set
++CONFIG_PPP_ASYNC=m
++CONFIG_PPP_SYNC_TTY=m
++CONFIG_PPP_DEFLATE=m
++# CONFIG_PPP_BSDCOMP is not set
++# CONFIG_PPP_MPPE is not set
++# CONFIG_PPPOE is not set
++# CONFIG_SLIP is not set
++# CONFIG_NET_FC is not set
++# CONFIG_SHAPER is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++
++#
++# ISDN subsystem
++#
++# CONFIG_ISDN is not set
++
++#
++# Telephony Support
++#
++# CONFIG_PHONE is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++
++#
++# Userland interfaces
++#
++# CONFIG_INPUT_MOUSEDEV is not set
++# CONFIG_INPUT_JOYDEV is not set
++# CONFIG_INPUT_TSDEV is not set
++CONFIG_INPUT_EVDEV=m
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++# CONFIG_INPUT_KEYBOARD is not set
++# CONFIG_INPUT_MOUSE is not set
++# CONFIG_INPUT_JOYSTICK is not set
++# CONFIG_INPUT_TOUCHSCREEN is not set
++# CONFIG_INPUT_MISC is not set
++
++#
++# Hardware I/O ports
++#
++# CONFIG_SERIO is not set
++# CONFIG_GAMEPORT is not set
++
++#
++# Character devices
++#
++# CONFIG_VT is not set
++# CONFIG_SERIAL_NONSTANDARD is not set
++
++#
++# Serial drivers
++#
++CONFIG_SERIAL_8250=y
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_PCI=y
++CONFIG_SERIAL_8250_NR_UARTS=4
++CONFIG_SERIAL_8250_RUNTIME_UARTS=4
++# CONFIG_SERIAL_8250_EXTENDED is not set
++
++#
++# Non-8250 serial port support
++#
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++# CONFIG_SERIAL_JSM is not set
++CONFIG_UNIX98_PTYS=y
++CONFIG_LEGACY_PTYS=y
++CONFIG_LEGACY_PTY_COUNT=256
++
++#
++# IPMI
++#
++# CONFIG_IPMI_HANDLER is not set
++
++#
++# Watchdog Cards
++#
++# CONFIG_WATCHDOG is not set
++CONFIG_RTC=m
++CONFIG_GEN_RTC=m
++CONFIG_GEN_RTC_X=y
++# CONFIG_DTLK is not set
++# CONFIG_R3964 is not set
++# CONFIG_APPLICOM is not set
++
++#
++# Ftape, the floppy tape device driver
++#
++# CONFIG_DRM is not set
++# CONFIG_RAW_DRIVER is not set
++
++#
++# TPM devices
++#
++# CONFIG_TCG_TPM is not set
++# CONFIG_TELCLOCK is not set
++
++#
++# I2C support
++#
++CONFIG_I2C=y
++CONFIG_I2C_CHARDEV=y
++
++#
++# I2C Algorithms
++#
++# CONFIG_I2C_ALGOBIT is not set
++# CONFIG_I2C_ALGOPCF is not set
++# CONFIG_I2C_ALGOPCA is not set
++
++#
++# I2C Hardware Bus support
++#
++# CONFIG_I2C_ALI1535 is not set
++# CONFIG_I2C_ALI1563 is not set
++# CONFIG_I2C_ALI15X3 is not set
++# CONFIG_I2C_AMD756 is not set
++# CONFIG_I2C_AMD8111 is not set
++# CONFIG_I2C_I801 is not set
++# CONFIG_I2C_I810 is not set
++# CONFIG_I2C_PIIX4 is not set
++# CONFIG_I2C_NFORCE2 is not set
++# CONFIG_I2C_PARPORT_LIGHT is not set
++# CONFIG_I2C_PROSAVAGE is not set
++# CONFIG_I2C_SAVAGE4 is not set
++# CONFIG_I2C_SIS5595 is not set
++# CONFIG_I2C_SIS630 is not set
++# CONFIG_I2C_SIS96X is not set
++# CONFIG_I2C_STUB is not set
++# CONFIG_I2C_VIA is not set
++# CONFIG_I2C_VIAPRO is not set
++# CONFIG_I2C_VOODOO3 is not set
++# CONFIG_I2C_PCA_ISA is not set
++
++#
++# Miscellaneous I2C Chip support
++#
++# CONFIG_SENSORS_DS1337 is not set
++# CONFIG_SENSORS_DS1374 is not set
++# CONFIG_SENSORS_EEPROM is not set
++# CONFIG_SENSORS_PCF8574 is not set
++# CONFIG_SENSORS_PCA9539 is not set
++# CONFIG_SENSORS_PCF8591 is not set
++# CONFIG_SENSORS_MAX6875 is not set
++CONFIG_I2C_DEBUG_CORE=y
++# CONFIG_I2C_DEBUG_ALGO is not set
++CONFIG_I2C_DEBUG_BUS=y
++# CONFIG_I2C_DEBUG_CHIP is not set
++
++#
++# SPI support
++#
++# CONFIG_SPI is not set
++# CONFIG_SPI_MASTER is not set
++
++#
++# Dallas's 1-wire bus
++#
++# CONFIG_W1 is not set
++
++#
++# Hardware Monitoring support
++#
++CONFIG_HWMON=y
++# CONFIG_HWMON_VID is not set
++# CONFIG_SENSORS_ADM1021 is not set
++# CONFIG_SENSORS_ADM1025 is not set
++# CONFIG_SENSORS_ADM1026 is not set
++# CONFIG_SENSORS_ADM1031 is not set
++# CONFIG_SENSORS_ADM9240 is not set
++# CONFIG_SENSORS_ASB100 is not set
++# CONFIG_SENSORS_ATXP1 is not set
++# CONFIG_SENSORS_DS1621 is not set
++# CONFIG_SENSORS_F71805F is not set
++# CONFIG_SENSORS_FSCHER is not set
++# CONFIG_SENSORS_FSCPOS is not set
++# CONFIG_SENSORS_GL518SM is not set
++# CONFIG_SENSORS_GL520SM is not set
++# CONFIG_SENSORS_IT87 is not set
++# CONFIG_SENSORS_LM63 is not set
++# CONFIG_SENSORS_LM75 is not set
++# CONFIG_SENSORS_LM77 is not set
++# CONFIG_SENSORS_LM78 is not set
++# CONFIG_SENSORS_LM80 is not set
++# CONFIG_SENSORS_LM83 is not set
++# CONFIG_SENSORS_LM85 is not set
++# CONFIG_SENSORS_LM87 is not set
++# CONFIG_SENSORS_LM90 is not set
++# CONFIG_SENSORS_LM92 is not set
++# CONFIG_SENSORS_MAX1619 is not set
++# CONFIG_SENSORS_PC87360 is not set
++# CONFIG_SENSORS_SIS5595 is not set
++# CONFIG_SENSORS_SMSC47M1 is not set
++# CONFIG_SENSORS_SMSC47B397 is not set
++# CONFIG_SENSORS_VIA686A is not set
++# CONFIG_SENSORS_VT8231 is not set
++# CONFIG_SENSORS_W83781D is not set
++# CONFIG_SENSORS_W83792D is not set
++# CONFIG_SENSORS_W83L785TS is not set
++# CONFIG_SENSORS_W83627HF is not set
++# CONFIG_SENSORS_W83627EHF is not set
++# CONFIG_HWMON_DEBUG_CHIP is not set
++
++#
++# Misc devices
++#
++
++#
++# Multimedia devices
++#
++# CONFIG_VIDEO_DEV is not set
++CONFIG_VIDEO_V4L2=y
++
++#
++# Digital Video Broadcasting Devices
++#
++# CONFIG_DVB is not set
++
++#
++# Graphics support
++#
++# CONFIG_FB is not set
++
++#
++# Sound
++#
++# CONFIG_SOUND is not set
++
++#
++# USB support
++#
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB_ARCH_HAS_OHCI=y
++CONFIG_USB_ARCH_HAS_EHCI=y
++# CONFIG_USB is not set
++
++#
++# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
++#
++
++#
++# USB Gadget Support
++#
++# CONFIG_USB_GADGET is not set
++
++#
++# MMC/SD Card support
++#
++# CONFIG_MMC is not set
++
++#
++# LED devices
++#
++# CONFIG_NEW_LEDS is not set
++
++#
++# LED drivers
++#
++
++#
++# LED Triggers
++#
++
++#
++# InfiniBand support
++#
++# CONFIG_INFINIBAND is not set
++
++#
++# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
++#
++
++#
++# Real Time Clock
++#
++# CONFIG_RTC_CLASS is not set
++
++#
++# File systems
++#
++CONFIG_EXT2_FS=y
++CONFIG_EXT2_FS_XATTR=y
++CONFIG_EXT2_FS_POSIX_ACL=y
++CONFIG_EXT2_FS_SECURITY=y
++# CONFIG_EXT2_FS_XIP is not set
++CONFIG_EXT3_FS=m
++CONFIG_EXT3_FS_XATTR=y
++# CONFIG_EXT3_FS_POSIX_ACL is not set
++# CONFIG_EXT3_FS_SECURITY is not set
++CONFIG_JBD=m
++# CONFIG_JBD_DEBUG is not set
++CONFIG_FS_MBCACHE=y
++# CONFIG_REISERFS_FS is not set
++# CONFIG_JFS_FS is not set
++CONFIG_FS_POSIX_ACL=y
++CONFIG_XFS_FS=m
++CONFIG_XFS_EXPORT=y
++# CONFIG_XFS_QUOTA is not set
++# CONFIG_XFS_SECURITY is not set
++# CONFIG_XFS_POSIX_ACL is not set
++# CONFIG_XFS_RT is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_MINIX_FS is not set
++# CONFIG_ROMFS_FS is not set
++CONFIG_INOTIFY=y
++# CONFIG_QUOTA is not set
++# CONFIG_DNOTIFY is not set
++# CONFIG_AUTOFS_FS is not set
++CONFIG_AUTOFS4_FS=m
++# CONFIG_FUSE_FS is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++# CONFIG_ISO9660_FS is not set
++# CONFIG_UDF_FS is not set
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++CONFIG_NTFS_FS=m
++# CONFIG_NTFS_DEBUG is not set
++# CONFIG_NTFS_RW is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_PROC_KCORE=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++# CONFIG_HUGETLB_PAGE is not set
++CONFIG_RAMFS=y
++# CONFIG_CONFIGFS_FS is not set
++
++#
++# Miscellaneous filesystems
++#
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++# CONFIG_JFFS_FS is not set
++CONFIG_JFFS2_FS=y
++CONFIG_JFFS2_FS_DEBUG=0
++CONFIG_JFFS2_FS_WRITEBUFFER=y
++# CONFIG_JFFS2_SUMMARY is not set
++CONFIG_JFFS2_COMPRESSION_OPTIONS=y
++CONFIG_JFFS2_ZLIB=y
++CONFIG_JFFS2_RTIME=y
++# CONFIG_JFFS2_RUBIN is not set
++# CONFIG_JFFS2_CMODE_NONE is not set
++CONFIG_JFFS2_CMODE_PRIORITY=y
++# CONFIG_JFFS2_CMODE_SIZE is not set
++CONFIG_CRAMFS=y
++# CONFIG_VXFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++
++#
++# Network File Systems
++#
++CONFIG_NFS_FS=y
++CONFIG_NFS_V3=y
++# CONFIG_NFS_V3_ACL is not set
++CONFIG_NFS_V4=y
++CONFIG_NFS_DIRECTIO=y
++CONFIG_NFSD=m
++CONFIG_NFSD_V3=y
++# CONFIG_NFSD_V3_ACL is not set
++# CONFIG_NFSD_V4 is not set
++CONFIG_NFSD_TCP=y
++CONFIG_ROOT_NFS=y
++CONFIG_LOCKD=y
++CONFIG_LOCKD_V4=y
++CONFIG_EXPORTFS=m
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++CONFIG_SUNRPC_GSS=y
++CONFIG_RPCSEC_GSS_KRB5=y
++# CONFIG_RPCSEC_GSS_SPKM3 is not set
++CONFIG_SMB_FS=m
++# CONFIG_SMB_NLS_DEFAULT is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++# CONFIG_9P_FS is not set
++
++#
++# Partition Types
++#
++# CONFIG_PARTITION_ADVANCED is not set
++CONFIG_MSDOS_PARTITION=y
++
++#
++# Native Language Support
++#
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT=""
++CONFIG_NLS_CODEPAGE_437=m
++# CONFIG_NLS_CODEPAGE_737 is not set
++# CONFIG_NLS_CODEPAGE_775 is not set
++# CONFIG_NLS_CODEPAGE_850 is not set
++# CONFIG_NLS_CODEPAGE_852 is not set
++# CONFIG_NLS_CODEPAGE_855 is not set
++# CONFIG_NLS_CODEPAGE_857 is not set
++# CONFIG_NLS_CODEPAGE_860 is not set
++# CONFIG_NLS_CODEPAGE_861 is not set
++# CONFIG_NLS_CODEPAGE_862 is not set
++# CONFIG_NLS_CODEPAGE_863 is not set
++# CONFIG_NLS_CODEPAGE_864 is not set
++# CONFIG_NLS_CODEPAGE_865 is not set
++# CONFIG_NLS_CODEPAGE_866 is not set
++# CONFIG_NLS_CODEPAGE_869 is not set
++# CONFIG_NLS_CODEPAGE_936 is not set
++# CONFIG_NLS_CODEPAGE_950 is not set
++# CONFIG_NLS_CODEPAGE_932 is not set
++# CONFIG_NLS_CODEPAGE_949 is not set
++# CONFIG_NLS_CODEPAGE_874 is not set
++# CONFIG_NLS_ISO8859_8 is not set
++# CONFIG_NLS_CODEPAGE_1250 is not set
++# CONFIG_NLS_CODEPAGE_1251 is not set
++CONFIG_NLS_ASCII=m
++CONFIG_NLS_ISO8859_1=m
++# CONFIG_NLS_ISO8859_2 is not set
++# CONFIG_NLS_ISO8859_3 is not set
++# CONFIG_NLS_ISO8859_4 is not set
++# CONFIG_NLS_ISO8859_5 is not set
++# CONFIG_NLS_ISO8859_6 is not set
++# CONFIG_NLS_ISO8859_7 is not set
++# CONFIG_NLS_ISO8859_9 is not set
++# CONFIG_NLS_ISO8859_13 is not set
++# CONFIG_NLS_ISO8859_14 is not set
++# CONFIG_NLS_ISO8859_15 is not set
++# CONFIG_NLS_KOI8_R is not set
++# CONFIG_NLS_KOI8_U is not set
++CONFIG_NLS_UTF8=m
++
++#
++# Profiling support
++#
++# CONFIG_PROFILING is not set
++
++#
++# Kernel hacking
++#
++# CONFIG_PRINTK_TIME is not set
++# CONFIG_MAGIC_SYSRQ is not set
++# CONFIG_DEBUG_KERNEL is not set
++CONFIG_LOG_BUF_SHIFT=14
++# CONFIG_DEBUG_FS is not set
++CONFIG_CROSSCOMPILE=y
++CONFIG_CMDLINE="console=ttyS0,115200 mem=192m ip=bootp root=/dev/nfs rw"
++
++#
++# Security options
++#
++# CONFIG_KEYS is not set
++# CONFIG_SECURITY is not set
++
++#
++# Cryptographic options
++#
++CONFIG_CRYPTO=y
++CONFIG_CRYPTO_HMAC=y
++# CONFIG_CRYPTO_NULL is not set
++# CONFIG_CRYPTO_MD4 is not set
++CONFIG_CRYPTO_MD5=y
++# CONFIG_CRYPTO_SHA1 is not set
++# CONFIG_CRYPTO_SHA256 is not set
++# CONFIG_CRYPTO_SHA512 is not set
++# CONFIG_CRYPTO_WP512 is not set
++# CONFIG_CRYPTO_TGR192 is not set
++CONFIG_CRYPTO_DES=y
++# CONFIG_CRYPTO_BLOWFISH is not set
++# CONFIG_CRYPTO_TWOFISH is not set
++# CONFIG_CRYPTO_SERPENT is not set
++# CONFIG_CRYPTO_AES is not set
++# CONFIG_CRYPTO_CAST5 is not set
++# CONFIG_CRYPTO_CAST6 is not set
++# CONFIG_CRYPTO_TEA is not set
++# CONFIG_CRYPTO_ARC4 is not set
++# CONFIG_CRYPTO_KHAZAD is not set
++# CONFIG_CRYPTO_ANUBIS is not set
++# CONFIG_CRYPTO_DEFLATE is not set
++# CONFIG_CRYPTO_MICHAEL_MIC is not set
++# CONFIG_CRYPTO_CRC32C is not set
++# CONFIG_CRYPTO_TEST is not set
++
++#
++# Hardware crypto devices
++#
++
++#
++# Library routines
++#
++CONFIG_CRC_CCITT=m
++# CONFIG_CRC16 is not set
++CONFIG_CRC32=y
++# CONFIG_LIBCRC32C is not set
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=y
+diff -Naur linux-2.6.17.orig/arch/mips/configs/ev64120_defconfig linux-2.6.17/arch/mips/configs/ev64120_defconfig
+--- linux-2.6.17.orig/arch/mips/configs/ev64120_defconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/configs/ev64120_defconfig	2006-06-19 18:16:13.000000000 -0700
+@@ -41,8 +41,6 @@
+ # CONFIG_MIPS_XXS1500 is not set
+ # CONFIG_PNX8550_V2PCI is not set
+ # CONFIG_PNX8550_JBS is not set
+-# CONFIG_DDB5074 is not set
+-# CONFIG_DDB5476 is not set
+ # CONFIG_DDB5477 is not set
+ # CONFIG_MACH_VR41XX is not set
+ # CONFIG_PMC_YOSEMITE is not set
+@@ -68,6 +66,7 @@
+ CONFIG_GENERIC_FIND_NEXT_BIT=y
+ CONFIG_GENERIC_HWEIGHT=y
+ CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+ CONFIG_DMA_NONCOHERENT=y
+ CONFIG_DMA_NEED_PCI_MAP_STATE=y
+ CONFIG_CPU_BIG_ENDIAN=y
+diff -Naur linux-2.6.17.orig/arch/mips/configs/ev96100_defconfig linux-2.6.17/arch/mips/configs/ev96100_defconfig
+--- linux-2.6.17.orig/arch/mips/configs/ev96100_defconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/configs/ev96100_defconfig	2006-06-19 18:16:13.000000000 -0700
+@@ -41,8 +41,6 @@
+ # CONFIG_MIPS_XXS1500 is not set
+ # CONFIG_PNX8550_V2PCI is not set
+ # CONFIG_PNX8550_JBS is not set
+-# CONFIG_DDB5074 is not set
+-# CONFIG_DDB5476 is not set
+ # CONFIG_DDB5477 is not set
+ # CONFIG_MACH_VR41XX is not set
+ # CONFIG_PMC_YOSEMITE is not set
+@@ -67,6 +65,7 @@
+ CONFIG_GENERIC_FIND_NEXT_BIT=y
+ CONFIG_GENERIC_HWEIGHT=y
+ CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+ CONFIG_DMA_NONCOHERENT=y
+ CONFIG_DMA_NEED_PCI_MAP_STATE=y
+ CONFIG_CPU_BIG_ENDIAN=y
+diff -Naur linux-2.6.17.orig/arch/mips/configs/excite_defconfig linux-2.6.17/arch/mips/configs/excite_defconfig
+--- linux-2.6.17.orig/arch/mips/configs/excite_defconfig	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/arch/mips/configs/excite_defconfig	2006-06-19 18:16:13.000000000 -0700
+@@ -0,0 +1,1211 @@
++#
++# Automatically generated make config: don't edit
++# Linux kernel version: 2.6.16-rc4
++# Thu Feb 23 13:15:27 2006
++#
++CONFIG_MIPS=y
++
++#
++# Machine selection
++#
++# CONFIG_MIPS_MTX1 is not set
++# CONFIG_MIPS_BOSPORUS is not set
++# CONFIG_MIPS_PB1000 is not set
++# CONFIG_MIPS_PB1100 is not set
++# CONFIG_MIPS_PB1500 is not set
++# CONFIG_MIPS_PB1550 is not set
++# CONFIG_MIPS_PB1200 is not set
++# CONFIG_MIPS_DB1000 is not set
++# CONFIG_MIPS_DB1100 is not set
++# CONFIG_MIPS_DB1500 is not set
++# CONFIG_MIPS_DB1550 is not set
++# CONFIG_MIPS_DB1200 is not set
++# CONFIG_MIPS_MIRAGE is not set
++# CONFIG_MIPS_COBALT is not set
++# CONFIG_MACH_DECSTATION is not set
++# CONFIG_MIPS_EV64120 is not set
++# CONFIG_MIPS_EV96100 is not set
++# CONFIG_MIPS_IVR is not set
++# CONFIG_MIPS_ITE8172 is not set
++# CONFIG_MACH_JAZZ is not set
++# CONFIG_LASAT is not set
++# CONFIG_MIPS_ATLAS is not set
++# CONFIG_MIPS_MALTA is not set
++# CONFIG_MIPS_SEAD is not set
++# CONFIG_MIPS_SIM is not set
++# CONFIG_MOMENCO_JAGUAR_ATX is not set
++# CONFIG_MOMENCO_OCELOT is not set
++# CONFIG_MOMENCO_OCELOT_3 is not set
++# CONFIG_MOMENCO_OCELOT_C is not set
++# CONFIG_MOMENCO_OCELOT_G is not set
++# CONFIG_MIPS_XXS1500 is not set
++# CONFIG_PNX8550_V2PCI is not set
++# CONFIG_PNX8550_JBS is not set
++CONFIG_BASLER_EXCITE=y
++# CONFIG_BASLER_EXCITE_PROTOTYPE is not set
++# CONFIG_DDB5074 is not set
++# CONFIG_DDB5476 is not set
++# CONFIG_DDB5477 is not set
++# CONFIG_MACH_VR41XX is not set
++# CONFIG_PMC_YOSEMITE is not set
++# CONFIG_QEMU is not set
++# CONFIG_SGI_IP22 is not set
++# CONFIG_SGI_IP27 is not set
++# CONFIG_SGI_IP32 is not set
++# CONFIG_SIBYTE_BIGSUR is not set
++# CONFIG_SIBYTE_SWARM is not set
++# CONFIG_SIBYTE_SENTOSA is not set
++# CONFIG_SIBYTE_RHONE is not set
++# CONFIG_SIBYTE_CARMEL is not set
++# CONFIG_SIBYTE_PTSWARM is not set
++# CONFIG_SIBYTE_LITTLESUR is not set
++# CONFIG_SIBYTE_CRHINE is not set
++# CONFIG_SIBYTE_CRHONE is not set
++# CONFIG_SNI_RM200_PCI is not set
++# CONFIG_TOSHIBA_JMR3927 is not set
++# CONFIG_TOSHIBA_RBTX4927 is not set
++# CONFIG_TOSHIBA_RBTX4938 is not set
++CONFIG_RWSEM_GENERIC_SPINLOCK=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_DMA_COHERENT=y
++CONFIG_SERIAL_RM9000=y
++CONFIG_CPU_BIG_ENDIAN=y
++# CONFIG_CPU_LITTLE_ENDIAN is not set
++CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
++CONFIG_IRQ_CPU=y
++CONFIG_IRQ_CPU_RM7K=y
++CONFIG_IRQ_CPU_RM9K=y
++CONFIG_MIPS_L1_CACHE_SHIFT=5
++
++#
++# CPU selection
++#
++# CONFIG_CPU_MIPS32_R1 is not set
++# CONFIG_CPU_MIPS32_R2 is not set
++# CONFIG_CPU_MIPS64_R1 is not set
++# CONFIG_CPU_MIPS64_R2 is not set
++# CONFIG_CPU_R3000 is not set
++# CONFIG_CPU_TX39XX is not set
++# CONFIG_CPU_VR41XX is not set
++# CONFIG_CPU_R4300 is not set
++# CONFIG_CPU_R4X00 is not set
++# CONFIG_CPU_TX49XX is not set
++# CONFIG_CPU_R5000 is not set
++# CONFIG_CPU_R5432 is not set
++# CONFIG_CPU_R6000 is not set
++# CONFIG_CPU_NEVADA is not set
++# CONFIG_CPU_R8000 is not set
++# CONFIG_CPU_R10000 is not set
++# CONFIG_CPU_RM7000 is not set
++CONFIG_CPU_RM9000=y
++# CONFIG_CPU_SB1 is not set
++CONFIG_SYS_HAS_CPU_RM9000=y
++CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
++CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
++CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
++CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
++
++#
++# Kernel type
++#
++CONFIG_32BIT=y
++# CONFIG_64BIT is not set
++CONFIG_PAGE_SIZE_4KB=y
++# CONFIG_PAGE_SIZE_8KB is not set
++# CONFIG_PAGE_SIZE_16KB is not set
++# CONFIG_PAGE_SIZE_64KB is not set
++CONFIG_CPU_HAS_PREFETCH=y
++# CONFIG_MIPS_MT is not set
++# CONFIG_64BIT_PHYS_ADDR is not set
++# CONFIG_CPU_ADVANCED is not set
++CONFIG_CPU_HAS_LLSC=y
++CONFIG_CPU_HAS_SYNC=y
++CONFIG_GENERIC_HARDIRQS=y
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_CPU_SUPPORTS_HIGHMEM=y
++CONFIG_ARCH_FLATMEM_ENABLE=y
++CONFIG_SELECT_MEMORY_MODEL=y
++CONFIG_FLATMEM_MANUAL=y
++# CONFIG_DISCONTIGMEM_MANUAL is not set
++# CONFIG_SPARSEMEM_MANUAL is not set
++CONFIG_FLATMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++# CONFIG_SPARSEMEM_STATIC is not set
++CONFIG_SPLIT_PTLOCK_CPUS=4
++# CONFIG_SMP is not set
++# CONFIG_PREEMPT_NONE is not set
++# CONFIG_PREEMPT_VOLUNTARY is not set
++CONFIG_PREEMPT=y
++CONFIG_PREEMPT_BKL=y
++
++#
++# Code maturity level options
++#
++CONFIG_EXPERIMENTAL=y
++CONFIG_BROKEN_ON_SMP=y
++CONFIG_LOCK_KERNEL=y
++CONFIG_INIT_ENV_ARG_LIMIT=32
++
++#
++# General setup
++#
++CONFIG_LOCALVERSION=""
++# CONFIG_LOCALVERSION_AUTO is not set
++CONFIG_SWAP=y
++CONFIG_SYSVIPC=y
++CONFIG_POSIX_MQUEUE=y
++# CONFIG_BSD_PROCESS_ACCT is not set
++CONFIG_SYSCTL=y
++# CONFIG_AUDIT is not set
++# CONFIG_IKCONFIG is not set
++CONFIG_INITRAMFS_SOURCE=""
++CONFIG_CC_OPTIMIZE_FOR_SIZE=y
++CONFIG_EMBEDDED=y
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_EXTRA_PASS is not set
++CONFIG_HOTPLUG=y
++CONFIG_PRINTK=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_EPOLL=y
++CONFIG_SHMEM=y
++CONFIG_CC_ALIGN_FUNCTIONS=0
++CONFIG_CC_ALIGN_LABELS=0
++CONFIG_CC_ALIGN_LOOPS=0
++CONFIG_CC_ALIGN_JUMPS=0
++CONFIG_SLAB=y
++# CONFIG_TINY_SHMEM is not set
++CONFIG_BASE_SMALL=0
++# CONFIG_SLOB is not set
++
++#
++# Loadable module support
++#
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++# CONFIG_MODULE_FORCE_UNLOAD is not set
++CONFIG_OBSOLETE_MODPARM=y
++# CONFIG_MODVERSIONS is not set
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++CONFIG_KMOD=y
++
++#
++# Block layer
++#
++# CONFIG_LBD is not set
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++CONFIG_IOSCHED_AS=y
++CONFIG_IOSCHED_DEADLINE=y
++CONFIG_IOSCHED_CFQ=y
++CONFIG_DEFAULT_AS=y
++# CONFIG_DEFAULT_DEADLINE is not set
++# CONFIG_DEFAULT_CFQ is not set
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="anticipatory"
++
++#
++# Bus options (PCI, PCMCIA, EISA, ISA, TC)
++#
++CONFIG_HW_HAS_PCI=y
++CONFIG_PCI=y
++# CONFIG_PCI_LEGACY_PROC is not set
++CONFIG_MMU=y
++
++#
++# PCCARD (PCMCIA/CardBus) support
++#
++# CONFIG_PCCARD is not set
++
++#
++# PCI Hotplug Support
++#
++# CONFIG_HOTPLUG_PCI is not set
++
++#
++# Executable file formats
++#
++CONFIG_BINFMT_ELF=y
++# CONFIG_BINFMT_MISC is not set
++CONFIG_TRAD_SIGNALS=y
++
++#
++# Networking
++#
++CONFIG_NET=y
++
++#
++# Networking options
++#
++# CONFIG_NETDEBUG is not set
++CONFIG_PACKET=y
++CONFIG_PACKET_MMAP=y
++CONFIG_UNIX=y
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++# CONFIG_IP_MULTICAST is not set
++# CONFIG_IP_ADVANCED_ROUTER is not set
++CONFIG_IP_FIB_HASH=y
++CONFIG_IP_PNP=y
++CONFIG_IP_PNP_DHCP=y
++# CONFIG_IP_PNP_BOOTP is not set
++# CONFIG_IP_PNP_RARP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE is not set
++# CONFIG_ARPD is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_TUNNEL is not set
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_BIC=y
++# CONFIG_IPV6 is not set
++# CONFIG_NETFILTER is not set
++
++#
++# DCCP Configuration (EXPERIMENTAL)
++#
++# CONFIG_IP_DCCP is not set
++
++#
++# SCTP Configuration (EXPERIMENTAL)
++#
++# CONFIG_IP_SCTP is not set
++
++#
++# TIPC Configuration (EXPERIMENTAL)
++#
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_BRIDGE is not set
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_NET_DIVERT is not set
++# CONFIG_ECONET is not set
++# CONFIG_WAN_ROUTER is not set
++
++#
++# QoS and/or fair queueing
++#
++# CONFIG_NET_SCHED is not set
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_IEEE80211 is not set
++
++#
++# Device Drivers
++#
++
++#
++# Generic Driver Options
++#
++CONFIG_STANDALONE=y
++CONFIG_PREVENT_FIRMWARE_BUILD=y
++# CONFIG_FW_LOADER is not set
++
++#
++# Connector - unified userspace <-> kernelspace linker
++#
++# CONFIG_CONNECTOR is not set
++
++#
++# Memory Technology Devices (MTD)
++#
++CONFIG_MTD=y
++# CONFIG_MTD_DEBUG is not set
++# CONFIG_MTD_CONCAT is not set
++CONFIG_MTD_PARTITIONS=y
++# CONFIG_MTD_REDBOOT_PARTS is not set
++# CONFIG_MTD_CMDLINE_PARTS is not set
++
++#
++# User Modules And Translation Layers
++#
++CONFIG_MTD_CHAR=y
++CONFIG_MTD_BLOCK=y
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++# CONFIG_MTD_CFI is not set
++# CONFIG_MTD_JEDECPROBE is not set
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
++CONFIG_MTD_CFI_I1=y
++CONFIG_MTD_CFI_I2=y
++# CONFIG_MTD_CFI_I4 is not set
++# CONFIG_MTD_CFI_I8 is not set
++# CONFIG_MTD_RAM is not set
++# CONFIG_MTD_ROM is not set
++# CONFIG_MTD_ABSENT is not set
++# CONFIG_MTD_OBSOLETE_CHIPS is not set
++
++#
++# Mapping drivers for chip access
++#
++# CONFIG_MTD_COMPLEX_MAPPINGS is not set
++# CONFIG_MTD_PLATRAM is not set
++
++#
++# Self-contained MTD device drivers
++#
++# CONFIG_MTD_PMC551 is not set
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++# CONFIG_MTD_BLKMTD is not set
++# CONFIG_MTD_BLOCK2MTD is not set
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOC2000 is not set
++# CONFIG_MTD_DOC2001 is not set
++# CONFIG_MTD_DOC2001PLUS is not set
++
++#
++# NAND Flash Device Drivers
++#
++CONFIG_MTD_NAND=y
++CONFIG_MTD_NAND_VERIFY_WRITE=y
++CONFIG_MTD_NAND_IDS=y
++# CONFIG_MTD_NAND_DISKONCHIP is not set
++CONFIG_MTD_NAND_BASLER_EXCITE=y
++# CONFIG_MTD_NAND_BASLER_EXCITE_RDNBY is not set
++# CONFIG_MTD_NAND_BASLER_EXCITE_PERF is not set
++# CONFIG_MTD_NAND_NANDSIM is not set
++
++#
++# OneNAND Flash Device Drivers
++#
++# CONFIG_MTD_ONENAND is not set
++
++#
++# Parallel port support
++#
++# CONFIG_PARPORT is not set
++
++#
++# Plug and Play support
++#
++
++#
++# Block devices
++#
++# CONFIG_BLK_CPQ_DA is not set
++# CONFIG_BLK_CPQ_CISS_DA is not set
++# CONFIG_BLK_DEV_DAC960 is not set
++# CONFIG_BLK_DEV_UMEM is not set
++# CONFIG_BLK_DEV_COW_COMMON is not set
++CONFIG_BLK_DEV_LOOP=m
++# CONFIG_BLK_DEV_CRYPTOLOOP is not set
++# CONFIG_BLK_DEV_NBD is not set
++# CONFIG_BLK_DEV_SX8 is not set
++# CONFIG_BLK_DEV_UB is not set
++# CONFIG_BLK_DEV_RAM is not set
++CONFIG_BLK_DEV_RAM_COUNT=16
++# CONFIG_CDROM_PKTCDVD is not set
++# CONFIG_ATA_OVER_ETH is not set
++
++#
++# ATA/ATAPI/MFM/RLL support
++#
++# CONFIG_IDE is not set
++
++#
++# SCSI device support
++#
++# CONFIG_RAID_ATTRS is not set
++CONFIG_SCSI=y
++# CONFIG_SCSI_PROC_FS is not set
++
++#
++# SCSI support type (disk, tape, CD-ROM)
++#
++CONFIG_BLK_DEV_SD=y
++# CONFIG_CHR_DEV_ST is not set
++# CONFIG_CHR_DEV_OSST is not set
++# CONFIG_BLK_DEV_SR is not set
++# CONFIG_CHR_DEV_SG is not set
++# CONFIG_CHR_DEV_SCH is not set
++
++#
++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
++#
++# CONFIG_SCSI_MULTI_LUN is not set
++# CONFIG_SCSI_CONSTANTS is not set
++# CONFIG_SCSI_LOGGING is not set
++
++#
++# SCSI Transport Attributes
++#
++# CONFIG_SCSI_SPI_ATTRS is not set
++# CONFIG_SCSI_FC_ATTRS is not set
++# CONFIG_SCSI_ISCSI_ATTRS is not set
++# CONFIG_SCSI_SAS_ATTRS is not set
++
++#
++# SCSI low-level drivers
++#
++# CONFIG_ISCSI_TCP is not set
++# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
++# CONFIG_SCSI_3W_9XXX is not set
++# CONFIG_SCSI_ACARD is not set
++# CONFIG_SCSI_AACRAID is not set
++# CONFIG_SCSI_AIC7XXX is not set
++# CONFIG_SCSI_AIC7XXX_OLD is not set
++# CONFIG_SCSI_AIC79XX is not set
++# CONFIG_SCSI_DPT_I2O is not set
++# CONFIG_MEGARAID_NEWGEN is not set
++# CONFIG_MEGARAID_LEGACY is not set
++# CONFIG_MEGARAID_SAS is not set
++# CONFIG_SCSI_SATA is not set
++# CONFIG_SCSI_DMX3191D is not set
++# CONFIG_SCSI_FUTURE_DOMAIN is not set
++# CONFIG_SCSI_IPS is not set
++# CONFIG_SCSI_INITIO is not set
++# CONFIG_SCSI_INIA100 is not set
++# CONFIG_SCSI_SYM53C8XX_2 is not set
++# CONFIG_SCSI_IPR is not set
++# CONFIG_SCSI_QLOGIC_FC is not set
++# CONFIG_SCSI_QLOGIC_1280 is not set
++# CONFIG_SCSI_QLA_FC is not set
++# CONFIG_SCSI_LPFC is not set
++# CONFIG_SCSI_DC395x is not set
++# CONFIG_SCSI_DC390T is not set
++# CONFIG_SCSI_NSP32 is not set
++# CONFIG_SCSI_DEBUG is not set
++
++#
++# Multi-device support (RAID and LVM)
++#
++# CONFIG_MD is not set
++
++#
++# Fusion MPT device support
++#
++# CONFIG_FUSION is not set
++# CONFIG_FUSION_SPI is not set
++# CONFIG_FUSION_FC is not set
++# CONFIG_FUSION_SAS is not set
++
++#
++# IEEE 1394 (FireWire) support
++#
++# CONFIG_IEEE1394 is not set
++
++#
++# I2O device support
++#
++# CONFIG_I2O is not set
++
++#
++# Network device support
++#
++CONFIG_NETDEVICES=y
++# CONFIG_DUMMY is not set
++# CONFIG_BONDING is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_TUN is not set
++
++#
++# ARCnet devices
++#
++# CONFIG_ARCNET is not set
++
++#
++# PHY device support
++#
++
++#
++# Ethernet (10 or 100Mbit)
++#
++# CONFIG_NET_ETHERNET is not set
++
++#
++# Ethernet (1000 Mbit)
++#
++# CONFIG_ACENIC is not set
++# CONFIG_DL2K is not set
++# CONFIG_E1000 is not set
++# CONFIG_NS83820 is not set
++# CONFIG_HAMACHI is not set
++# CONFIG_YELLOWFIN is not set
++# CONFIG_R8169 is not set
++# CONFIG_SIS190 is not set
++# CONFIG_SKGE is not set
++# CONFIG_SKY2 is not set
++# CONFIG_SK98LIN is not set
++# CONFIG_TIGON3 is not set
++# CONFIG_BNX2 is not set
++# CONFIG_TITAN_GE is not set
++CONFIG_RM9K_GE=m
++
++#
++# Ethernet (10000 Mbit)
++#
++# CONFIG_CHELSIO_T1 is not set
++# CONFIG_IXGB is not set
++# CONFIG_S2IO is not set
++
++#
++# Token Ring devices
++#
++# CONFIG_TR is not set
++
++#
++# Wireless LAN (non-hamradio)
++#
++# CONFIG_NET_RADIO is not set
++
++#
++# Wan interfaces
++#
++# CONFIG_WAN is not set
++# CONFIG_FDDI is not set
++# CONFIG_HIPPI is not set
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++# CONFIG_NET_FC is not set
++# CONFIG_SHAPER is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++
++#
++# ISDN subsystem
++#
++# CONFIG_ISDN is not set
++
++#
++# Telephony Support
++#
++# CONFIG_PHONE is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++
++#
++# Userland interfaces
++#
++CONFIG_INPUT_MOUSEDEV=m
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
++# CONFIG_INPUT_JOYDEV is not set
++# CONFIG_INPUT_TSDEV is not set
++CONFIG_INPUT_EVDEV=m
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++# CONFIG_INPUT_KEYBOARD is not set
++# CONFIG_INPUT_MOUSE is not set
++# CONFIG_INPUT_JOYSTICK is not set
++# CONFIG_INPUT_TOUCHSCREEN is not set
++# CONFIG_INPUT_MISC is not set
++
++#
++# Hardware I/O ports
++#
++# CONFIG_SERIO is not set
++# CONFIG_GAMEPORT is not set
++
++#
++# Character devices
++#
++CONFIG_VT=y
++CONFIG_VT_CONSOLE=y
++CONFIG_HW_CONSOLE=y
++# CONFIG_SERIAL_NONSTANDARD is not set
++
++#
++# Serial drivers
++#
++CONFIG_SERIAL_8250=y
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_NR_UARTS=2
++CONFIG_SERIAL_8250_RUNTIME_UARTS=2
++CONFIG_SERIAL_8250_EXTENDED=y
++# CONFIG_SERIAL_8250_MANY_PORTS is not set
++CONFIG_SERIAL_8250_SHARE_IRQ=y
++# CONFIG_SERIAL_8250_DETECT_IRQ is not set
++# CONFIG_SERIAL_8250_RSA is not set
++
++#
++# Non-8250 serial port support
++#
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++# CONFIG_SERIAL_JSM is not set
++CONFIG_UNIX98_PTYS=y
++# CONFIG_LEGACY_PTYS is not set
++
++#
++# IPMI
++#
++# CONFIG_IPMI_HANDLER is not set
++
++#
++# Watchdog Cards
++#
++CONFIG_WATCHDOG=y
++# CONFIG_WATCHDOG_NOWAYOUT is not set
++
++#
++# Watchdog Device Drivers
++#
++# CONFIG_SOFT_WATCHDOG is not set
++CONFIG_WDT_RM9K_GPI=m
++
++#
++# PCI-based Watchdog Cards
++#
++# CONFIG_PCIPCWATCHDOG is not set
++# CONFIG_WDTPCI is not set
++
++#
++# USB-based Watchdog Cards
++#
++# CONFIG_USBPCWATCHDOG is not set
++# CONFIG_RTC is not set
++# CONFIG_GEN_RTC is not set
++# CONFIG_DTLK is not set
++# CONFIG_R3964 is not set
++# CONFIG_APPLICOM is not set
++
++#
++# Ftape, the floppy tape device driver
++#
++# CONFIG_DRM is not set
++# CONFIG_RAW_DRIVER is not set
++
++#
++# TPM devices
++#
++# CONFIG_TCG_TPM is not set
++# CONFIG_TELCLOCK is not set
++
++#
++# I2C support
++#
++# CONFIG_I2C is not set
++
++#
++# SPI support
++#
++# CONFIG_SPI is not set
++# CONFIG_SPI_MASTER is not set
++
++#
++# Dallas's 1-wire bus
++#
++# CONFIG_W1 is not set
++
++#
++# Hardware Monitoring support
++#
++# CONFIG_HWMON is not set
++# CONFIG_HWMON_VID is not set
++
++#
++# Misc devices
++#
++
++#
++# Multimedia Capabilities Port drivers
++#
++
++#
++# Multimedia devices
++#
++# CONFIG_VIDEO_DEV is not set
++
++#
++# Digital Video Broadcasting Devices
++#
++# CONFIG_DVB is not set
++
++#
++# Graphics support
++#
++CONFIG_FB=y
++CONFIG_FB_CFB_FILLRECT=y
++CONFIG_FB_CFB_COPYAREA=y
++CONFIG_FB_CFB_IMAGEBLIT=y
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_MODE_HELPERS is not set
++# CONFIG_FB_TILEBLITTING is not set
++# CONFIG_FB_CIRRUS is not set
++# CONFIG_FB_PM2 is not set
++# CONFIG_FB_CYBER2000 is not set
++# CONFIG_FB_ASILIANT is not set
++# CONFIG_FB_IMSTT is not set
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_NVIDIA is not set
++# CONFIG_FB_RIVA is not set
++# CONFIG_FB_MATROX is not set
++# CONFIG_FB_RADEON_OLD is not set
++# CONFIG_FB_RADEON is not set
++# CONFIG_FB_ATY128 is not set
++# CONFIG_FB_ATY is not set
++# CONFIG_FB_SAVAGE is not set
++# CONFIG_FB_SIS is not set
++# CONFIG_FB_NEOMAGIC is not set
++# CONFIG_FB_KYRO is not set
++# CONFIG_FB_3DFX is not set
++# CONFIG_FB_VOODOO1 is not set
++# CONFIG_FB_SMIVGX is not set
++# CONFIG_FB_TRIDENT is not set
++# CONFIG_FB_VIRTUAL is not set
++CONFIG_FB_DD=y
++
++#
++# Console display driver support
++#
++# CONFIG_VGA_CONSOLE is not set
++CONFIG_DUMMY_CONSOLE=y
++CONFIG_FRAMEBUFFER_CONSOLE=m
++# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
++# CONFIG_FONTS is not set
++CONFIG_FONT_8x8=y
++CONFIG_FONT_8x16=y
++
++#
++# Logo configuration
++#
++# CONFIG_LOGO is not set
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++
++#
++# Sound
++#
++# CONFIG_SOUND is not set
++
++#
++# USB support
++#
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB_ARCH_HAS_OHCI=y
++CONFIG_USB=y
++# CONFIG_USB_DEBUG is not set
++
++#
++# Miscellaneous USB options
++#
++CONFIG_USB_DEVICEFS=y
++# CONFIG_USB_BANDWIDTH is not set
++# CONFIG_USB_DYNAMIC_MINORS is not set
++# CONFIG_USB_OTG is not set
++
++#
++# USB Host Controller Drivers
++#
++CONFIG_USB_EHCI_HCD=y
++# CONFIG_USB_EHCI_SPLIT_ISO is not set
++# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
++# CONFIG_USB_ISP116X_HCD is not set
++CONFIG_USB_OHCI_HCD=y
++# CONFIG_USB_OHCI_BIG_ENDIAN is not set
++CONFIG_USB_OHCI_LITTLE_ENDIAN=y
++# CONFIG_USB_UHCI_HCD is not set
++# CONFIG_USB_SL811_HCD is not set
++
++#
++# USB Device Class drivers
++#
++# CONFIG_USB_ACM is not set
++# CONFIG_USB_PRINTER is not set
++
++#
++# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
++#
++
++#
++# may also be needed; see USB_STORAGE Help for more information
++#
++CONFIG_USB_STORAGE=y
++# CONFIG_USB_STORAGE_DEBUG is not set
++# CONFIG_USB_STORAGE_DATAFAB is not set
++# CONFIG_USB_STORAGE_FREECOM is not set
++# CONFIG_USB_STORAGE_DPCM is not set
++# CONFIG_USB_STORAGE_USBAT is not set
++# CONFIG_USB_STORAGE_SDDR09 is not set
++# CONFIG_USB_STORAGE_SDDR55 is not set
++# CONFIG_USB_STORAGE_JUMPSHOT is not set
++# CONFIG_USB_STORAGE_ALAUDA is not set
++# CONFIG_USB_STORAGE_ONETOUCH is not set
++# CONFIG_USB_LIBUSUAL is not set
++
++#
++# USB Input Devices
++#
++CONFIG_USB_HID=m
++CONFIG_USB_HIDINPUT=y
++# CONFIG_USB_HIDINPUT_POWERBOOK is not set
++# CONFIG_HID_FF is not set
++# CONFIG_USB_HIDDEV is not set
++
++#
++# USB HID Boot Protocol drivers
++#
++# CONFIG_USB_KBD is not set
++# CONFIG_USB_MOUSE is not set
++# CONFIG_USB_AIPTEK is not set
++# CONFIG_USB_WACOM is not set
++# CONFIG_USB_ACECAD is not set
++# CONFIG_USB_KBTAB is not set
++# CONFIG_USB_POWERMATE is not set
++# CONFIG_USB_MTOUCH is not set
++# CONFIG_USB_ITMTOUCH is not set
++# CONFIG_USB_EGALAX is not set
++# CONFIG_USB_YEALINK is not set
++# CONFIG_USB_XPAD is not set
++# CONFIG_USB_ATI_REMOTE is not set
++# CONFIG_USB_ATI_REMOTE2 is not set
++# CONFIG_USB_KEYSPAN_REMOTE is not set
++# CONFIG_USB_APPLETOUCH is not set
++
++#
++# USB Imaging devices
++#
++# CONFIG_USB_MDC800 is not set
++# CONFIG_USB_MICROTEK is not set
++
++#
++# USB Multimedia devices
++#
++# CONFIG_USB_DABUSB is not set
++
++#
++# Video4Linux support is needed for USB Multimedia device support
++#
++
++#
++# USB Network Adapters
++#
++# CONFIG_USB_CATC is not set
++# CONFIG_USB_KAWETH is not set
++# CONFIG_USB_PEGASUS is not set
++# CONFIG_USB_RTL8150 is not set
++# CONFIG_USB_USBNET is not set
++# CONFIG_USB_MON is not set
++
++#
++# USB port drivers
++#
++
++#
++# USB Serial Converter support
++#
++# CONFIG_USB_SERIAL is not set
++
++#
++# USB Miscellaneous drivers
++#
++# CONFIG_USB_EMI62 is not set
++# CONFIG_USB_EMI26 is not set
++# CONFIG_USB_AUERSWALD is not set
++# CONFIG_USB_RIO500 is not set
++CONFIG_USB_ARTTFT=m
++# CONFIG_USB_ARTTOUCH is not set
++# CONFIG_USB_LEGOTOWER is not set
++# CONFIG_USB_LCD is not set
++# CONFIG_USB_LED is not set
++# CONFIG_USB_CYTHERM is not set
++# CONFIG_USB_PHIDGETKIT is not set
++# CONFIG_USB_PHIDGETSERVO is not set
++# CONFIG_USB_IDMOUSE is not set
++# CONFIG_USB_SISUSBVGA is not set
++# CONFIG_USB_LD is not set
++# CONFIG_USB_TEST is not set
++
++#
++# USB DSL modem support
++#
++
++#
++# USB Gadget Support
++#
++# CONFIG_USB_GADGET is not set
++
++#
++# MMC/SD Card support
++#
++# CONFIG_MMC is not set
++
++#
++# InfiniBand support
++#
++# CONFIG_INFINIBAND is not set
++
++#
++# SN Devices
++#
++
++#
++# EDAC - error detection and reporting (RAS)
++#
++
++#
++# eXcite frame capture support
++#
++CONFIG_EXCITE_FCAP=m
++CONFIG_EXCITE_FCAP_GPI=m
++
++#
++# File systems
++#
++CONFIG_EXT2_FS=y
++# CONFIG_EXT2_FS_XATTR is not set
++# CONFIG_EXT2_FS_XIP is not set
++# CONFIG_EXT3_FS is not set
++# CONFIG_REISERFS_FS is not set
++# CONFIG_JFS_FS is not set
++# CONFIG_FS_POSIX_ACL is not set
++# CONFIG_XFS_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_MINIX_FS is not set
++# CONFIG_ROMFS_FS is not set
++CONFIG_INOTIFY=y
++# CONFIG_QUOTA is not set
++# CONFIG_DNOTIFY is not set
++# CONFIG_AUTOFS_FS is not set
++# CONFIG_AUTOFS4_FS is not set
++# CONFIG_FUSE_FS is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++# CONFIG_ISO9660_FS is not set
++# CONFIG_UDF_FS is not set
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=m
++CONFIG_MSDOS_FS=m
++CONFIG_VFAT_FS=m
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_PROC_KCORE=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++# CONFIG_HUGETLB_PAGE is not set
++CONFIG_RAMFS=y
++# CONFIG_RELAYFS_FS is not set
++# CONFIG_CONFIGFS_FS is not set
++
++#
++# Miscellaneous filesystems
++#
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++# CONFIG_JFFS_FS is not set
++CONFIG_JFFS2_FS=y
++CONFIG_JFFS2_FS_DEBUG=0
++CONFIG_JFFS2_FS_WRITEBUFFER=y
++# CONFIG_JFFS2_SUMMARY is not set
++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
++CONFIG_JFFS2_ZLIB=y
++CONFIG_JFFS2_RTIME=y
++# CONFIG_JFFS2_RUBIN is not set
++# CONFIG_CRAMFS is not set
++# CONFIG_VXFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++
++#
++# Network File Systems
++#
++CONFIG_NFS_FS=y
++CONFIG_NFS_V3=y
++# CONFIG_NFS_V3_ACL is not set
++# CONFIG_NFS_V4 is not set
++# CONFIG_NFS_DIRECTIO is not set
++# CONFIG_NFSD is not set
++CONFIG_ROOT_NFS=y
++CONFIG_LOCKD=y
++CONFIG_LOCKD_V4=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++# CONFIG_RPCSEC_GSS_KRB5 is not set
++# CONFIG_RPCSEC_GSS_SPKM3 is not set
++# CONFIG_SMB_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++# CONFIG_9P_FS is not set
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_ATARI_PARTITION is not set
++# CONFIG_MAC_PARTITION is not set
++CONFIG_MSDOS_PARTITION=y
++# CONFIG_BSD_DISKLABEL is not set
++# CONFIG_MINIX_SUBPARTITION is not set
++# CONFIG_SOLARIS_X86_PARTITION is not set
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++# CONFIG_KARMA_PARTITION is not set
++# CONFIG_EFI_PARTITION is not set
++
++#
++# Native Language Support
++#
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++CONFIG_NLS_CODEPAGE_437=m
++# CONFIG_NLS_CODEPAGE_737 is not set
++# CONFIG_NLS_CODEPAGE_775 is not set
++CONFIG_NLS_CODEPAGE_850=m
++# CONFIG_NLS_CODEPAGE_852 is not set
++# CONFIG_NLS_CODEPAGE_855 is not set
++# CONFIG_NLS_CODEPAGE_857 is not set
++# CONFIG_NLS_CODEPAGE_860 is not set
++# CONFIG_NLS_CODEPAGE_861 is not set
++# CONFIG_NLS_CODEPAGE_862 is not set
++# CONFIG_NLS_CODEPAGE_863 is not set
++# CONFIG_NLS_CODEPAGE_864 is not set
++# CONFIG_NLS_CODEPAGE_865 is not set
++# CONFIG_NLS_CODEPAGE_866 is not set
++# CONFIG_NLS_CODEPAGE_869 is not set
++# CONFIG_NLS_CODEPAGE_936 is not set
++# CONFIG_NLS_CODEPAGE_950 is not set
++# CONFIG_NLS_CODEPAGE_932 is not set
++# CONFIG_NLS_CODEPAGE_949 is not set
++# CONFIG_NLS_CODEPAGE_874 is not set
++# CONFIG_NLS_ISO8859_8 is not set
++# CONFIG_NLS_CODEPAGE_1250 is not set
++# CONFIG_NLS_CODEPAGE_1251 is not set
++# CONFIG_NLS_ASCII is not set
++CONFIG_NLS_ISO8859_1=m
++# CONFIG_NLS_ISO8859_2 is not set
++# CONFIG_NLS_ISO8859_3 is not set
++# CONFIG_NLS_ISO8859_4 is not set
++# CONFIG_NLS_ISO8859_5 is not set
++# CONFIG_NLS_ISO8859_6 is not set
++# CONFIG_NLS_ISO8859_7 is not set
++# CONFIG_NLS_ISO8859_9 is not set
++# CONFIG_NLS_ISO8859_13 is not set
++# CONFIG_NLS_ISO8859_14 is not set
++# CONFIG_NLS_ISO8859_15 is not set
++# CONFIG_NLS_KOI8_R is not set
++# CONFIG_NLS_KOI8_U is not set
++# CONFIG_NLS_UTF8 is not set
++
++#
++# Profiling support
++#
++# CONFIG_PROFILING is not set
++
++#
++# Kernel hacking
++#
++# CONFIG_PRINTK_TIME is not set
++# CONFIG_MAGIC_SYSRQ is not set
++# CONFIG_DEBUG_KERNEL is not set
++CONFIG_LOG_BUF_SHIFT=14
++CONFIG_CROSSCOMPILE=y
++CONFIG_CMDLINE=""
++
++#
++# Security options
++#
++# CONFIG_KEYS is not set
++# CONFIG_SECURITY is not set
++
++#
++# Cryptographic options
++#
++CONFIG_CRYPTO=y
++# CONFIG_CRYPTO_HMAC is not set
++# CONFIG_CRYPTO_NULL is not set
++# CONFIG_CRYPTO_MD4 is not set
++# CONFIG_CRYPTO_MD5 is not set
++# CONFIG_CRYPTO_SHA1 is not set
++# CONFIG_CRYPTO_SHA256 is not set
++# CONFIG_CRYPTO_SHA512 is not set
++# CONFIG_CRYPTO_WP512 is not set
++# CONFIG_CRYPTO_TGR192 is not set
++# CONFIG_CRYPTO_DES is not set
++# CONFIG_CRYPTO_BLOWFISH is not set
++# CONFIG_CRYPTO_TWOFISH is not set
++# CONFIG_CRYPTO_SERPENT is not set
++# CONFIG_CRYPTO_AES is not set
++# CONFIG_CRYPTO_CAST5 is not set
++# CONFIG_CRYPTO_CAST6 is not set
++# CONFIG_CRYPTO_TEA is not set
++# CONFIG_CRYPTO_ARC4 is not set
++# CONFIG_CRYPTO_KHAZAD is not set
++# CONFIG_CRYPTO_ANUBIS is not set
++# CONFIG_CRYPTO_DEFLATE is not set
++# CONFIG_CRYPTO_MICHAEL_MIC is not set
++# CONFIG_CRYPTO_CRC32C is not set
++# CONFIG_CRYPTO_TEST is not set
++
++#
++# Hardware crypto devices
++#
++
++#
++# Library routines
++#
++# CONFIG_CRC_CCITT is not set
++# CONFIG_CRC16 is not set
++CONFIG_CRC32=y
++# CONFIG_LIBCRC32C is not set
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=y
+diff -Naur linux-2.6.17.orig/arch/mips/configs/ip22_defconfig linux-2.6.17/arch/mips/configs/ip22_defconfig
+--- linux-2.6.17.orig/arch/mips/configs/ip22_defconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/configs/ip22_defconfig	2006-06-19 18:16:13.000000000 -0700
+@@ -41,8 +41,6 @@
+ # CONFIG_MIPS_XXS1500 is not set
+ # CONFIG_PNX8550_V2PCI is not set
+ # CONFIG_PNX8550_JBS is not set
+-# CONFIG_DDB5074 is not set
+-# CONFIG_DDB5476 is not set
+ # CONFIG_DDB5477 is not set
+ # CONFIG_MACH_VR41XX is not set
+ # CONFIG_PMC_YOSEMITE is not set
+@@ -67,6 +65,7 @@
+ CONFIG_GENERIC_FIND_NEXT_BIT=y
+ CONFIG_GENERIC_HWEIGHT=y
+ CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+ CONFIG_ARC=y
+ CONFIG_DMA_NONCOHERENT=y
+ CONFIG_DMA_NEED_PCI_MAP_STATE=y
+diff -Naur linux-2.6.17.orig/arch/mips/configs/ip27_defconfig linux-2.6.17/arch/mips/configs/ip27_defconfig
+--- linux-2.6.17.orig/arch/mips/configs/ip27_defconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/configs/ip27_defconfig	2006-06-19 18:16:13.000000000 -0700
+@@ -41,8 +41,6 @@
+ # CONFIG_MIPS_XXS1500 is not set
+ # CONFIG_PNX8550_V2PCI is not set
+ # CONFIG_PNX8550_JBS is not set
+-# CONFIG_DDB5074 is not set
+-# CONFIG_DDB5476 is not set
+ # CONFIG_DDB5477 is not set
+ # CONFIG_MACH_VR41XX is not set
+ # CONFIG_PMC_YOSEMITE is not set
+@@ -63,7 +61,7 @@
+ # CONFIG_TOSHIBA_JMR3927 is not set
+ # CONFIG_TOSHIBA_RBTX4927 is not set
+ # CONFIG_TOSHIBA_RBTX4938 is not set
+-# CONFIG_SGI_SN0_N_MODE is not set
++# CONFIG_SGI_SN_N_MODE is not set
+ CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
+ CONFIG_NUMA=y
+ # CONFIG_MAPPED_KERNEL is not set
+@@ -73,6 +71,7 @@
+ CONFIG_GENERIC_FIND_NEXT_BIT=y
+ CONFIG_GENERIC_HWEIGHT=y
+ CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+ CONFIG_ARC=y
+ CONFIG_DMA_IP27=y
+ CONFIG_CPU_BIG_ENDIAN=y
+diff -Naur linux-2.6.17.orig/arch/mips/configs/ip32_defconfig linux-2.6.17/arch/mips/configs/ip32_defconfig
+--- linux-2.6.17.orig/arch/mips/configs/ip32_defconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/configs/ip32_defconfig	2006-06-19 18:16:13.000000000 -0700
+@@ -41,8 +41,6 @@
+ # CONFIG_MIPS_XXS1500 is not set
+ # CONFIG_PNX8550_V2PCI is not set
+ # CONFIG_PNX8550_JBS is not set
+-# CONFIG_DDB5074 is not set
+-# CONFIG_DDB5476 is not set
+ # CONFIG_DDB5477 is not set
+ # CONFIG_MACH_VR41XX is not set
+ # CONFIG_PMC_YOSEMITE is not set
+@@ -67,6 +65,7 @@
+ CONFIG_GENERIC_FIND_NEXT_BIT=y
+ CONFIG_GENERIC_HWEIGHT=y
+ CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+ CONFIG_ARC=y
+ CONFIG_DMA_IP32=y
+ CONFIG_DMA_NONCOHERENT=y
+diff -Naur linux-2.6.17.orig/arch/mips/configs/it8172_defconfig linux-2.6.17/arch/mips/configs/it8172_defconfig
+--- linux-2.6.17.orig/arch/mips/configs/it8172_defconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/configs/it8172_defconfig	2006-06-19 18:16:13.000000000 -0700
+@@ -41,8 +41,6 @@
+ # CONFIG_MIPS_XXS1500 is not set
+ # CONFIG_PNX8550_V2PCI is not set
+ # CONFIG_PNX8550_JBS is not set
+-# CONFIG_DDB5074 is not set
+-# CONFIG_DDB5476 is not set
+ # CONFIG_DDB5477 is not set
+ # CONFIG_MACH_VR41XX is not set
+ # CONFIG_PMC_YOSEMITE is not set
+@@ -68,6 +66,7 @@
+ CONFIG_GENERIC_FIND_NEXT_BIT=y
+ CONFIG_GENERIC_HWEIGHT=y
+ CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+ CONFIG_DMA_NONCOHERENT=y
+ CONFIG_DMA_NEED_PCI_MAP_STATE=y
+ # CONFIG_CPU_BIG_ENDIAN is not set
+diff -Naur linux-2.6.17.orig/arch/mips/configs/ivr_defconfig linux-2.6.17/arch/mips/configs/ivr_defconfig
+--- linux-2.6.17.orig/arch/mips/configs/ivr_defconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/configs/ivr_defconfig	2006-06-19 18:16:13.000000000 -0700
+@@ -41,8 +41,6 @@
+ # CONFIG_MIPS_XXS1500 is not set
+ # CONFIG_PNX8550_V2PCI is not set
+ # CONFIG_PNX8550_JBS is not set
+-# CONFIG_DDB5074 is not set
+-# CONFIG_DDB5476 is not set
+ # CONFIG_DDB5477 is not set
+ # CONFIG_MACH_VR41XX is not set
+ # CONFIG_PMC_YOSEMITE is not set
+@@ -67,6 +65,7 @@
+ CONFIG_GENERIC_FIND_NEXT_BIT=y
+ CONFIG_GENERIC_HWEIGHT=y
+ CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+ CONFIG_DMA_NONCOHERENT=y
+ CONFIG_DMA_NEED_PCI_MAP_STATE=y
+ # CONFIG_CPU_BIG_ENDIAN is not set
+diff -Naur linux-2.6.17.orig/arch/mips/configs/jaguar-atx_defconfig linux-2.6.17/arch/mips/configs/jaguar-atx_defconfig
+--- linux-2.6.17.orig/arch/mips/configs/jaguar-atx_defconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/configs/jaguar-atx_defconfig	2006-06-19 18:16:13.000000000 -0700
+@@ -41,8 +41,6 @@
+ # CONFIG_MIPS_XXS1500 is not set
+ # CONFIG_PNX8550_V2PCI is not set
+ # CONFIG_PNX8550_JBS is not set
+-# CONFIG_DDB5074 is not set
+-# CONFIG_DDB5476 is not set
+ # CONFIG_DDB5477 is not set
+ # CONFIG_MACH_VR41XX is not set
+ # CONFIG_PMC_YOSEMITE is not set
+@@ -68,6 +66,7 @@
+ CONFIG_GENERIC_FIND_NEXT_BIT=y
+ CONFIG_GENERIC_HWEIGHT=y
+ CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+ CONFIG_DMA_NONCOHERENT=y
+ CONFIG_DMA_NEED_PCI_MAP_STATE=y
+ CONFIG_LIMITED_DMA=y
+diff -Naur linux-2.6.17.orig/arch/mips/configs/jmr3927_defconfig linux-2.6.17/arch/mips/configs/jmr3927_defconfig
+--- linux-2.6.17.orig/arch/mips/configs/jmr3927_defconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/configs/jmr3927_defconfig	2006-06-19 18:16:13.000000000 -0700
+@@ -41,8 +41,6 @@
+ # CONFIG_MIPS_XXS1500 is not set
+ # CONFIG_PNX8550_V2PCI is not set
+ # CONFIG_PNX8550_JBS is not set
+-# CONFIG_DDB5074 is not set
+-# CONFIG_DDB5476 is not set
+ # CONFIG_DDB5477 is not set
+ # CONFIG_MACH_VR41XX is not set
+ # CONFIG_PMC_YOSEMITE is not set
+@@ -67,6 +65,7 @@
+ CONFIG_GENERIC_FIND_NEXT_BIT=y
+ CONFIG_GENERIC_HWEIGHT=y
+ CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+ CONFIG_DMA_NONCOHERENT=y
+ CONFIG_DMA_NEED_PCI_MAP_STATE=y
+ CONFIG_CPU_BIG_ENDIAN=y
+diff -Naur linux-2.6.17.orig/arch/mips/configs/lasat200_defconfig linux-2.6.17/arch/mips/configs/lasat200_defconfig
+--- linux-2.6.17.orig/arch/mips/configs/lasat200_defconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/configs/lasat200_defconfig	2006-06-19 18:16:13.000000000 -0700
+@@ -41,8 +41,6 @@
+ # CONFIG_MIPS_XXS1500 is not set
+ # CONFIG_PNX8550_V2PCI is not set
+ # CONFIG_PNX8550_JBS is not set
+-# CONFIG_DDB5074 is not set
+-# CONFIG_DDB5476 is not set
+ # CONFIG_DDB5477 is not set
+ # CONFIG_MACH_VR41XX is not set
+ # CONFIG_PMC_YOSEMITE is not set
+@@ -71,6 +69,7 @@
+ CONFIG_GENERIC_FIND_NEXT_BIT=y
+ CONFIG_GENERIC_HWEIGHT=y
+ CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+ CONFIG_DMA_NONCOHERENT=y
+ CONFIG_DMA_NEED_PCI_MAP_STATE=y
+ CONFIG_MIPS_NILE4=y
+diff -Naur linux-2.6.17.orig/arch/mips/configs/malta_defconfig linux-2.6.17/arch/mips/configs/malta_defconfig
+--- linux-2.6.17.orig/arch/mips/configs/malta_defconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/configs/malta_defconfig	2006-06-19 18:16:13.000000000 -0700
+@@ -41,8 +41,6 @@
+ # CONFIG_MIPS_XXS1500 is not set
+ # CONFIG_PNX8550_V2PCI is not set
+ # CONFIG_PNX8550_JBS is not set
+-# CONFIG_DDB5074 is not set
+-# CONFIG_DDB5476 is not set
+ # CONFIG_DDB5477 is not set
+ # CONFIG_MACH_VR41XX is not set
+ # CONFIG_PMC_YOSEMITE is not set
+@@ -67,6 +65,7 @@
+ CONFIG_GENERIC_FIND_NEXT_BIT=y
+ CONFIG_GENERIC_HWEIGHT=y
+ CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+ CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+ CONFIG_DMA_NONCOHERENT=y
+ CONFIG_DMA_NEED_PCI_MAP_STATE=y
+diff -Naur linux-2.6.17.orig/arch/mips/configs/mipssim_defconfig linux-2.6.17/arch/mips/configs/mipssim_defconfig
+--- linux-2.6.17.orig/arch/mips/configs/mipssim_defconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/configs/mipssim_defconfig	2006-06-19 18:16:13.000000000 -0700
+@@ -41,8 +41,6 @@
+ # CONFIG_MIPS_XXS1500 is not set
+ # CONFIG_PNX8550_V2PCI is not set
+ # CONFIG_PNX8550_JBS is not set
+-# CONFIG_DDB5074 is not set
+-# CONFIG_DDB5476 is not set
+ # CONFIG_DDB5477 is not set
+ # CONFIG_MACH_VR41XX is not set
+ # CONFIG_PMC_YOSEMITE is not set
+@@ -67,6 +65,7 @@
+ CONFIG_GENERIC_FIND_NEXT_BIT=y
+ CONFIG_GENERIC_HWEIGHT=y
+ CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+ CONFIG_DMA_NONCOHERENT=y
+ CONFIG_DMA_NEED_PCI_MAP_STATE=y
+ # CONFIG_CPU_BIG_ENDIAN is not set
+diff -Naur linux-2.6.17.orig/arch/mips/configs/mpc30x_defconfig linux-2.6.17/arch/mips/configs/mpc30x_defconfig
+--- linux-2.6.17.orig/arch/mips/configs/mpc30x_defconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/configs/mpc30x_defconfig	2006-06-19 18:16:13.000000000 -0700
+@@ -41,8 +41,6 @@
+ # CONFIG_MIPS_XXS1500 is not set
+ # CONFIG_PNX8550_V2PCI is not set
+ # CONFIG_PNX8550_JBS is not set
+-# CONFIG_DDB5074 is not set
+-# CONFIG_DDB5476 is not set
+ # CONFIG_DDB5477 is not set
+ CONFIG_MACH_VR41XX=y
+ # CONFIG_PMC_YOSEMITE is not set
+@@ -75,6 +73,7 @@
+ CONFIG_GENERIC_FIND_NEXT_BIT=y
+ CONFIG_GENERIC_HWEIGHT=y
+ CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+ CONFIG_DMA_NONCOHERENT=y
+ CONFIG_DMA_NEED_PCI_MAP_STATE=y
+ # CONFIG_CPU_BIG_ENDIAN is not set
+diff -Naur linux-2.6.17.orig/arch/mips/configs/ocelot_3_defconfig linux-2.6.17/arch/mips/configs/ocelot_3_defconfig
+--- linux-2.6.17.orig/arch/mips/configs/ocelot_3_defconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/configs/ocelot_3_defconfig	2006-06-19 18:16:13.000000000 -0700
+@@ -41,8 +41,6 @@
+ # CONFIG_MIPS_XXS1500 is not set
+ # CONFIG_PNX8550_V2PCI is not set
+ # CONFIG_PNX8550_JBS is not set
+-# CONFIG_DDB5074 is not set
+-# CONFIG_DDB5476 is not set
+ # CONFIG_DDB5477 is not set
+ # CONFIG_MACH_VR41XX is not set
+ # CONFIG_PMC_YOSEMITE is not set
+@@ -67,6 +65,7 @@
+ CONFIG_GENERIC_FIND_NEXT_BIT=y
+ CONFIG_GENERIC_HWEIGHT=y
+ CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+ CONFIG_DMA_NONCOHERENT=y
+ CONFIG_DMA_NEED_PCI_MAP_STATE=y
+ CONFIG_CPU_BIG_ENDIAN=y
+diff -Naur linux-2.6.17.orig/arch/mips/configs/ocelot_c_defconfig linux-2.6.17/arch/mips/configs/ocelot_c_defconfig
+--- linux-2.6.17.orig/arch/mips/configs/ocelot_c_defconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/configs/ocelot_c_defconfig	2006-06-19 18:16:13.000000000 -0700
+@@ -41,8 +41,6 @@
+ # CONFIG_MIPS_XXS1500 is not set
+ # CONFIG_PNX8550_V2PCI is not set
+ # CONFIG_PNX8550_JBS is not set
+-# CONFIG_DDB5074 is not set
+-# CONFIG_DDB5476 is not set
+ # CONFIG_DDB5477 is not set
+ # CONFIG_MACH_VR41XX is not set
+ # CONFIG_PMC_YOSEMITE is not set
+@@ -67,6 +65,7 @@
+ CONFIG_GENERIC_FIND_NEXT_BIT=y
+ CONFIG_GENERIC_HWEIGHT=y
+ CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+ CONFIG_DMA_NONCOHERENT=y
+ CONFIG_DMA_NEED_PCI_MAP_STATE=y
+ CONFIG_CPU_BIG_ENDIAN=y
+diff -Naur linux-2.6.17.orig/arch/mips/configs/ocelot_defconfig linux-2.6.17/arch/mips/configs/ocelot_defconfig
+--- linux-2.6.17.orig/arch/mips/configs/ocelot_defconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/configs/ocelot_defconfig	2006-06-19 18:16:13.000000000 -0700
+@@ -41,8 +41,6 @@
+ # CONFIG_MIPS_XXS1500 is not set
+ # CONFIG_PNX8550_V2PCI is not set
+ # CONFIG_PNX8550_JBS is not set
+-# CONFIG_DDB5074 is not set
+-# CONFIG_DDB5476 is not set
+ # CONFIG_DDB5477 is not set
+ # CONFIG_MACH_VR41XX is not set
+ # CONFIG_PMC_YOSEMITE is not set
+@@ -67,6 +65,7 @@
+ CONFIG_GENERIC_FIND_NEXT_BIT=y
+ CONFIG_GENERIC_HWEIGHT=y
+ CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+ CONFIG_DMA_NONCOHERENT=y
+ CONFIG_DMA_NEED_PCI_MAP_STATE=y
+ CONFIG_CPU_BIG_ENDIAN=y
+diff -Naur linux-2.6.17.orig/arch/mips/configs/ocelot_g_defconfig linux-2.6.17/arch/mips/configs/ocelot_g_defconfig
+--- linux-2.6.17.orig/arch/mips/configs/ocelot_g_defconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/configs/ocelot_g_defconfig	2006-06-19 18:16:13.000000000 -0700
+@@ -41,8 +41,6 @@
+ # CONFIG_MIPS_XXS1500 is not set
+ # CONFIG_PNX8550_V2PCI is not set
+ # CONFIG_PNX8550_JBS is not set
+-# CONFIG_DDB5074 is not set
+-# CONFIG_DDB5476 is not set
+ # CONFIG_DDB5477 is not set
+ # CONFIG_MACH_VR41XX is not set
+ # CONFIG_PMC_YOSEMITE is not set
+@@ -67,6 +65,7 @@
+ CONFIG_GENERIC_FIND_NEXT_BIT=y
+ CONFIG_GENERIC_HWEIGHT=y
+ CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+ CONFIG_DMA_NONCOHERENT=y
+ CONFIG_DMA_NEED_PCI_MAP_STATE=y
+ CONFIG_CPU_BIG_ENDIAN=y
+diff -Naur linux-2.6.17.orig/arch/mips/configs/pb1100_defconfig linux-2.6.17/arch/mips/configs/pb1100_defconfig
+--- linux-2.6.17.orig/arch/mips/configs/pb1100_defconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/configs/pb1100_defconfig	2006-06-19 18:16:13.000000000 -0700
+@@ -41,8 +41,6 @@
+ # CONFIG_MIPS_XXS1500 is not set
+ # CONFIG_PNX8550_V2PCI is not set
+ # CONFIG_PNX8550_JBS is not set
+-# CONFIG_DDB5074 is not set
+-# CONFIG_DDB5476 is not set
+ # CONFIG_DDB5477 is not set
+ # CONFIG_MACH_VR41XX is not set
+ # CONFIG_PMC_YOSEMITE is not set
+@@ -67,6 +65,7 @@
+ CONFIG_GENERIC_FIND_NEXT_BIT=y
+ CONFIG_GENERIC_HWEIGHT=y
+ CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+ CONFIG_DMA_NONCOHERENT=y
+ CONFIG_DMA_NEED_PCI_MAP_STATE=y
+ # CONFIG_CPU_BIG_ENDIAN is not set
+diff -Naur linux-2.6.17.orig/arch/mips/configs/pb1500_defconfig linux-2.6.17/arch/mips/configs/pb1500_defconfig
+--- linux-2.6.17.orig/arch/mips/configs/pb1500_defconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/configs/pb1500_defconfig	2006-06-19 18:16:13.000000000 -0700
+@@ -41,8 +41,6 @@
+ # CONFIG_MIPS_XXS1500 is not set
+ # CONFIG_PNX8550_V2PCI is not set
+ # CONFIG_PNX8550_JBS is not set
+-# CONFIG_DDB5074 is not set
+-# CONFIG_DDB5476 is not set
+ # CONFIG_DDB5477 is not set
+ # CONFIG_MACH_VR41XX is not set
+ # CONFIG_PMC_YOSEMITE is not set
+@@ -67,6 +65,7 @@
+ CONFIG_GENERIC_FIND_NEXT_BIT=y
+ CONFIG_GENERIC_HWEIGHT=y
+ CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+ CONFIG_DMA_NONCOHERENT=y
+ CONFIG_DMA_NEED_PCI_MAP_STATE=y
+ # CONFIG_CPU_BIG_ENDIAN is not set
+diff -Naur linux-2.6.17.orig/arch/mips/configs/pb1550_defconfig linux-2.6.17/arch/mips/configs/pb1550_defconfig
+--- linux-2.6.17.orig/arch/mips/configs/pb1550_defconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/configs/pb1550_defconfig	2006-06-19 18:16:13.000000000 -0700
+@@ -41,8 +41,6 @@
+ # CONFIG_MIPS_XXS1500 is not set
+ # CONFIG_PNX8550_V2PCI is not set
+ # CONFIG_PNX8550_JBS is not set
+-# CONFIG_DDB5074 is not set
+-# CONFIG_DDB5476 is not set
+ # CONFIG_DDB5477 is not set
+ # CONFIG_MACH_VR41XX is not set
+ # CONFIG_PMC_YOSEMITE is not set
+@@ -67,6 +65,7 @@
+ CONFIG_GENERIC_FIND_NEXT_BIT=y
+ CONFIG_GENERIC_HWEIGHT=y
+ CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+ CONFIG_DMA_NONCOHERENT=y
+ CONFIG_DMA_NEED_PCI_MAP_STATE=y
+ CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y
+diff -Naur linux-2.6.17.orig/arch/mips/configs/pnx8550-jbs_defconfig linux-2.6.17/arch/mips/configs/pnx8550-jbs_defconfig
+--- linux-2.6.17.orig/arch/mips/configs/pnx8550-jbs_defconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/configs/pnx8550-jbs_defconfig	2006-06-19 18:16:13.000000000 -0700
+@@ -41,8 +41,6 @@
+ # CONFIG_MIPS_XXS1500 is not set
+ # CONFIG_PNX8550_V2PCI is not set
+ CONFIG_PNX8550_JBS=y
+-# CONFIG_DDB5074 is not set
+-# CONFIG_DDB5476 is not set
+ # CONFIG_DDB5477 is not set
+ # CONFIG_MACH_VR41XX is not set
+ # CONFIG_PMC_YOSEMITE is not set
+@@ -67,6 +65,7 @@
+ CONFIG_GENERIC_FIND_NEXT_BIT=y
+ CONFIG_GENERIC_HWEIGHT=y
+ CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+ CONFIG_DMA_NONCOHERENT=y
+ CONFIG_DMA_NEED_PCI_MAP_STATE=y
+ # CONFIG_CPU_BIG_ENDIAN is not set
+diff -Naur linux-2.6.17.orig/arch/mips/configs/pnx8550-v2pci_defconfig linux-2.6.17/arch/mips/configs/pnx8550-v2pci_defconfig
+--- linux-2.6.17.orig/arch/mips/configs/pnx8550-v2pci_defconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/configs/pnx8550-v2pci_defconfig	2006-06-19 18:16:13.000000000 -0700
+@@ -41,8 +41,6 @@
+ # CONFIG_MIPS_XXS1500 is not set
+ CONFIG_PNX8550_V2PCI=y
+ # CONFIG_PNX8550_JBS is not set
+-# CONFIG_DDB5074 is not set
+-# CONFIG_DDB5476 is not set
+ # CONFIG_DDB5477 is not set
+ # CONFIG_MACH_VR41XX is not set
+ # CONFIG_PMC_YOSEMITE is not set
+@@ -67,6 +65,7 @@
+ CONFIG_GENERIC_FIND_NEXT_BIT=y
+ CONFIG_GENERIC_HWEIGHT=y
+ CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+ CONFIG_DMA_NONCOHERENT=y
+ CONFIG_DMA_NEED_PCI_MAP_STATE=y
+ # CONFIG_CPU_BIG_ENDIAN is not set
+diff -Naur linux-2.6.17.orig/arch/mips/configs/qemu_defconfig linux-2.6.17/arch/mips/configs/qemu_defconfig
+--- linux-2.6.17.orig/arch/mips/configs/qemu_defconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/configs/qemu_defconfig	2006-06-19 18:16:13.000000000 -0700
+@@ -41,8 +41,6 @@
+ # CONFIG_MIPS_XXS1500 is not set
+ # CONFIG_PNX8550_V2PCI is not set
+ # CONFIG_PNX8550_JBS is not set
+-# CONFIG_DDB5074 is not set
+-# CONFIG_DDB5476 is not set
+ # CONFIG_DDB5477 is not set
+ # CONFIG_MACH_VR41XX is not set
+ # CONFIG_PMC_YOSEMITE is not set
+@@ -67,6 +65,7 @@
+ CONFIG_GENERIC_FIND_NEXT_BIT=y
+ CONFIG_GENERIC_HWEIGHT=y
+ CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+ CONFIG_DMA_COHERENT=y
+ CONFIG_GENERIC_ISA_DMA=y
+ CONFIG_I8259=y
+diff -Naur linux-2.6.17.orig/arch/mips/configs/rbhma4500_defconfig linux-2.6.17/arch/mips/configs/rbhma4500_defconfig
+--- linux-2.6.17.orig/arch/mips/configs/rbhma4500_defconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/configs/rbhma4500_defconfig	2006-06-19 18:16:13.000000000 -0700
+@@ -41,8 +41,6 @@
+ # CONFIG_MIPS_XXS1500 is not set
+ # CONFIG_PNX8550_V2PCI is not set
+ # CONFIG_PNX8550_JBS is not set
+-# CONFIG_DDB5074 is not set
+-# CONFIG_DDB5476 is not set
+ # CONFIG_DDB5477 is not set
+ # CONFIG_MACH_VR41XX is not set
+ # CONFIG_PMC_YOSEMITE is not set
+@@ -74,6 +72,7 @@
+ CONFIG_GENERIC_FIND_NEXT_BIT=y
+ CONFIG_GENERIC_HWEIGHT=y
+ CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+ CONFIG_DMA_NONCOHERENT=y
+ CONFIG_DMA_NEED_PCI_MAP_STATE=y
+ CONFIG_GENERIC_ISA_DMA=y
+diff -Naur linux-2.6.17.orig/arch/mips/configs/rm200_defconfig linux-2.6.17/arch/mips/configs/rm200_defconfig
+--- linux-2.6.17.orig/arch/mips/configs/rm200_defconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/configs/rm200_defconfig	2006-06-19 18:16:13.000000000 -0700
+@@ -41,8 +41,6 @@
+ # CONFIG_MIPS_XXS1500 is not set
+ # CONFIG_PNX8550_V2PCI is not set
+ # CONFIG_PNX8550_JBS is not set
+-# CONFIG_DDB5074 is not set
+-# CONFIG_DDB5476 is not set
+ # CONFIG_DDB5477 is not set
+ # CONFIG_MACH_VR41XX is not set
+ # CONFIG_PMC_YOSEMITE is not set
+@@ -67,6 +65,7 @@
+ CONFIG_GENERIC_FIND_NEXT_BIT=y
+ CONFIG_GENERIC_HWEIGHT=y
+ CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+ CONFIG_ARC=y
+ CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+ CONFIG_DMA_NONCOHERENT=y
+diff -Naur linux-2.6.17.orig/arch/mips/configs/sb1250-swarm_defconfig linux-2.6.17/arch/mips/configs/sb1250-swarm_defconfig
+--- linux-2.6.17.orig/arch/mips/configs/sb1250-swarm_defconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/configs/sb1250-swarm_defconfig	2006-06-19 18:16:13.000000000 -0700
+@@ -41,8 +41,6 @@
+ # CONFIG_MIPS_XXS1500 is not set
+ # CONFIG_PNX8550_V2PCI is not set
+ # CONFIG_PNX8550_JBS is not set
+-# CONFIG_DDB5074 is not set
+-# CONFIG_DDB5476 is not set
+ # CONFIG_DDB5477 is not set
+ # CONFIG_MACH_VR41XX is not set
+ # CONFIG_PMC_YOSEMITE is not set
+@@ -84,6 +82,7 @@
+ CONFIG_GENERIC_FIND_NEXT_BIT=y
+ CONFIG_GENERIC_HWEIGHT=y
+ CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+ CONFIG_DMA_COHERENT=y
+ CONFIG_CPU_BIG_ENDIAN=y
+ # CONFIG_CPU_LITTLE_ENDIAN is not set
+diff -Naur linux-2.6.17.orig/arch/mips/configs/sead_defconfig linux-2.6.17/arch/mips/configs/sead_defconfig
+--- linux-2.6.17.orig/arch/mips/configs/sead_defconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/configs/sead_defconfig	2006-06-19 18:16:13.000000000 -0700
+@@ -41,8 +41,6 @@
+ # CONFIG_MIPS_XXS1500 is not set
+ # CONFIG_PNX8550_V2PCI is not set
+ # CONFIG_PNX8550_JBS is not set
+-# CONFIG_DDB5074 is not set
+-# CONFIG_DDB5476 is not set
+ # CONFIG_DDB5477 is not set
+ # CONFIG_MACH_VR41XX is not set
+ # CONFIG_PMC_YOSEMITE is not set
+@@ -67,6 +65,7 @@
+ CONFIG_GENERIC_FIND_NEXT_BIT=y
+ CONFIG_GENERIC_HWEIGHT=y
+ CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+ CONFIG_DMA_NONCOHERENT=y
+ CONFIG_DMA_NEED_PCI_MAP_STATE=y
+ # CONFIG_CPU_BIG_ENDIAN is not set
+diff -Naur linux-2.6.17.orig/arch/mips/configs/tb0226_defconfig linux-2.6.17/arch/mips/configs/tb0226_defconfig
+--- linux-2.6.17.orig/arch/mips/configs/tb0226_defconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/configs/tb0226_defconfig	2006-06-19 18:16:13.000000000 -0700
+@@ -41,8 +41,6 @@
+ # CONFIG_MIPS_XXS1500 is not set
+ # CONFIG_PNX8550_V2PCI is not set
+ # CONFIG_PNX8550_JBS is not set
+-# CONFIG_DDB5074 is not set
+-# CONFIG_DDB5476 is not set
+ # CONFIG_DDB5477 is not set
+ CONFIG_MACH_VR41XX=y
+ # CONFIG_PMC_YOSEMITE is not set
+@@ -77,6 +75,7 @@
+ CONFIG_GENERIC_FIND_NEXT_BIT=y
+ CONFIG_GENERIC_HWEIGHT=y
+ CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+ CONFIG_DMA_NONCOHERENT=y
+ CONFIG_DMA_NEED_PCI_MAP_STATE=y
+ # CONFIG_CPU_BIG_ENDIAN is not set
+diff -Naur linux-2.6.17.orig/arch/mips/configs/tb0229_defconfig linux-2.6.17/arch/mips/configs/tb0229_defconfig
+--- linux-2.6.17.orig/arch/mips/configs/tb0229_defconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/configs/tb0229_defconfig	2006-06-19 18:16:13.000000000 -0700
+@@ -41,8 +41,6 @@
+ # CONFIG_MIPS_XXS1500 is not set
+ # CONFIG_PNX8550_V2PCI is not set
+ # CONFIG_PNX8550_JBS is not set
+-# CONFIG_DDB5074 is not set
+-# CONFIG_DDB5476 is not set
+ # CONFIG_DDB5477 is not set
+ CONFIG_MACH_VR41XX=y
+ # CONFIG_PMC_YOSEMITE is not set
+@@ -77,6 +75,7 @@
+ CONFIG_GENERIC_FIND_NEXT_BIT=y
+ CONFIG_GENERIC_HWEIGHT=y
+ CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+ CONFIG_DMA_NONCOHERENT=y
+ CONFIG_DMA_NEED_PCI_MAP_STATE=y
+ # CONFIG_CPU_BIG_ENDIAN is not set
+diff -Naur linux-2.6.17.orig/arch/mips/configs/tb0287_defconfig linux-2.6.17/arch/mips/configs/tb0287_defconfig
+--- linux-2.6.17.orig/arch/mips/configs/tb0287_defconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/configs/tb0287_defconfig	2006-06-19 18:16:13.000000000 -0700
+@@ -41,8 +41,6 @@
+ # CONFIG_MIPS_XXS1500 is not set
+ # CONFIG_PNX8550_V2PCI is not set
+ # CONFIG_PNX8550_JBS is not set
+-# CONFIG_DDB5074 is not set
+-# CONFIG_DDB5476 is not set
+ # CONFIG_DDB5477 is not set
+ CONFIG_MACH_VR41XX=y
+ # CONFIG_PMC_YOSEMITE is not set
+diff -Naur linux-2.6.17.orig/arch/mips/configs/workpad_defconfig linux-2.6.17/arch/mips/configs/workpad_defconfig
+--- linux-2.6.17.orig/arch/mips/configs/workpad_defconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/configs/workpad_defconfig	2006-06-19 18:16:13.000000000 -0700
+@@ -41,8 +41,6 @@
+ # CONFIG_MIPS_XXS1500 is not set
+ # CONFIG_PNX8550_V2PCI is not set
+ # CONFIG_PNX8550_JBS is not set
+-# CONFIG_DDB5074 is not set
+-# CONFIG_DDB5476 is not set
+ # CONFIG_DDB5477 is not set
+ CONFIG_MACH_VR41XX=y
+ # CONFIG_PMC_YOSEMITE is not set
+@@ -73,6 +71,7 @@
+ CONFIG_GENERIC_FIND_NEXT_BIT=y
+ CONFIG_GENERIC_HWEIGHT=y
+ CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+ CONFIG_DMA_NONCOHERENT=y
+ CONFIG_DMA_NEED_PCI_MAP_STATE=y
+ # CONFIG_CPU_BIG_ENDIAN is not set
+diff -Naur linux-2.6.17.orig/arch/mips/configs/wrppmc_defconfig linux-2.6.17/arch/mips/configs/wrppmc_defconfig
+--- linux-2.6.17.orig/arch/mips/configs/wrppmc_defconfig	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/arch/mips/configs/wrppmc_defconfig	2006-06-19 18:16:13.000000000 -0700
+@@ -0,0 +1,799 @@
++#
++# Automatically generated make config: don't edit
++# Linux kernel version: 2.6.16.11
++# Fri May  5 17:11:22 2006
++#
++CONFIG_MIPS=y
++
++#
++# Machine selection
++#
++# CONFIG_MIPS_MTX1 is not set
++# CONFIG_MIPS_BOSPORUS is not set
++# CONFIG_MIPS_PB1000 is not set
++# CONFIG_MIPS_PB1100 is not set
++# CONFIG_MIPS_PB1500 is not set
++# CONFIG_MIPS_PB1550 is not set
++# CONFIG_MIPS_PB1200 is not set
++# CONFIG_MIPS_DB1000 is not set
++# CONFIG_MIPS_DB1100 is not set
++# CONFIG_MIPS_DB1500 is not set
++# CONFIG_MIPS_DB1550 is not set
++# CONFIG_MIPS_DB1200 is not set
++# CONFIG_MIPS_MIRAGE is not set
++# CONFIG_MIPS_COBALT is not set
++# CONFIG_MACH_DECSTATION is not set
++# CONFIG_MIPS_EV64120 is not set
++# CONFIG_MIPS_EV96100 is not set
++# CONFIG_MIPS_IVR is not set
++# CONFIG_MIPS_ITE8172 is not set
++# CONFIG_MACH_JAZZ is not set
++# CONFIG_LASAT is not set
++# CONFIG_MIPS_ATLAS is not set
++# CONFIG_MIPS_MALTA is not set
++# CONFIG_MIPS_SEAD is not set
++CONFIG_WR_PPMC=y
++# CONFIG_MIPS_SIM is not set
++# CONFIG_MOMENCO_JAGUAR_ATX is not set
++# CONFIG_MOMENCO_OCELOT is not set
++# CONFIG_MOMENCO_OCELOT_3 is not set
++# CONFIG_MOMENCO_OCELOT_C is not set
++# CONFIG_MOMENCO_OCELOT_G is not set
++# CONFIG_MIPS_XXS1500 is not set
++# CONFIG_PNX8550_V2PCI is not set
++# CONFIG_PNX8550_JBS is not set
++# CONFIG_DDB5477 is not set
++# CONFIG_MACH_VR41XX is not set
++# CONFIG_PMC_YOSEMITE is not set
++# CONFIG_QEMU is not set
++# CONFIG_SGI_IP22 is not set
++# CONFIG_SGI_IP27 is not set
++# CONFIG_SGI_IP32 is not set
++# CONFIG_SIBYTE_BIGSUR is not set
++# CONFIG_SIBYTE_SWARM is not set
++# CONFIG_SIBYTE_SENTOSA is not set
++# CONFIG_SIBYTE_RHONE is not set
++# CONFIG_SIBYTE_CARMEL is not set
++# CONFIG_SIBYTE_PTSWARM is not set
++# CONFIG_SIBYTE_LITTLESUR is not set
++# CONFIG_SIBYTE_CRHINE is not set
++# CONFIG_SIBYTE_CRHONE is not set
++# CONFIG_SNI_RM200_PCI is not set
++# CONFIG_TOSHIBA_JMR3927 is not set
++# CONFIG_TOSHIBA_RBTX4927 is not set
++# CONFIG_TOSHIBA_RBTX4938 is not set
++CONFIG_RWSEM_GENERIC_SPINLOCK=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_DMA_NONCOHERENT=y
++CONFIG_DMA_NEED_PCI_MAP_STATE=y
++CONFIG_CPU_BIG_ENDIAN=y
++# CONFIG_CPU_LITTLE_ENDIAN is not set
++CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
++CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
++CONFIG_IRQ_CPU=y
++CONFIG_MIPS_GT64120=y
++CONFIG_SWAP_IO_SPACE=y
++CONFIG_BOOT_ELF32=y
++CONFIG_MIPS_L1_CACHE_SHIFT=5
++
++#
++# CPU selection
++#
++CONFIG_CPU_MIPS32_R1=y
++# CONFIG_CPU_MIPS32_R2 is not set
++# CONFIG_CPU_MIPS64_R1 is not set
++# CONFIG_CPU_MIPS64_R2 is not set
++# CONFIG_CPU_R3000 is not set
++# CONFIG_CPU_TX39XX is not set
++# CONFIG_CPU_VR41XX is not set
++# CONFIG_CPU_R4300 is not set
++# CONFIG_CPU_R4X00 is not set
++# CONFIG_CPU_TX49XX is not set
++# CONFIG_CPU_R5000 is not set
++# CONFIG_CPU_R5432 is not set
++# CONFIG_CPU_R6000 is not set
++# CONFIG_CPU_NEVADA is not set
++# CONFIG_CPU_R8000 is not set
++# CONFIG_CPU_R10000 is not set
++# CONFIG_CPU_RM7000 is not set
++# CONFIG_CPU_RM9000 is not set
++# CONFIG_CPU_SB1 is not set
++CONFIG_SYS_HAS_CPU_MIPS32_R1=y
++CONFIG_SYS_HAS_CPU_MIPS32_R2=y
++CONFIG_SYS_HAS_CPU_MIPS64_R1=y
++CONFIG_SYS_HAS_CPU_NEVADA=y
++CONFIG_SYS_HAS_CPU_RM7000=y
++CONFIG_CPU_MIPS32=y
++CONFIG_CPU_MIPSR1=y
++CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
++CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
++CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
++
++#
++# Kernel type
++#
++CONFIG_32BIT=y
++# CONFIG_64BIT is not set
++CONFIG_PAGE_SIZE_4KB=y
++# CONFIG_PAGE_SIZE_8KB is not set
++# CONFIG_PAGE_SIZE_16KB is not set
++# CONFIG_PAGE_SIZE_64KB is not set
++CONFIG_CPU_HAS_PREFETCH=y
++# CONFIG_MIPS_MT is not set
++# CONFIG_64BIT_PHYS_ADDR is not set
++# CONFIG_CPU_ADVANCED is not set
++CONFIG_CPU_HAS_LLSC=y
++CONFIG_CPU_HAS_SYNC=y
++CONFIG_GENERIC_HARDIRQS=y
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_CPU_SUPPORTS_HIGHMEM=y
++CONFIG_ARCH_FLATMEM_ENABLE=y
++CONFIG_SELECT_MEMORY_MODEL=y
++CONFIG_FLATMEM_MANUAL=y
++# CONFIG_DISCONTIGMEM_MANUAL is not set
++# CONFIG_SPARSEMEM_MANUAL is not set
++CONFIG_FLATMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++# CONFIG_SPARSEMEM_STATIC is not set
++CONFIG_SPLIT_PTLOCK_CPUS=4
++CONFIG_PREEMPT_NONE=y
++# CONFIG_PREEMPT_VOLUNTARY is not set
++# CONFIG_PREEMPT is not set
++
++#
++# Code maturity level options
++#
++CONFIG_EXPERIMENTAL=y
++CONFIG_BROKEN_ON_SMP=y
++CONFIG_INIT_ENV_ARG_LIMIT=32
++
++#
++# General setup
++#
++CONFIG_LOCALVERSION=""
++CONFIG_LOCALVERSION_AUTO=y
++# CONFIG_SWAP is not set
++CONFIG_SYSVIPC=y
++# CONFIG_POSIX_MQUEUE is not set
++CONFIG_BSD_PROCESS_ACCT=y
++# CONFIG_BSD_PROCESS_ACCT_V3 is not set
++CONFIG_SYSCTL=y
++# CONFIG_AUDIT is not set
++# CONFIG_IKCONFIG is not set
++CONFIG_INITRAMFS_SOURCE=""
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
++CONFIG_EMBEDDED=y
++CONFIG_KALLSYMS=y
++CONFIG_KALLSYMS_EXTRA_PASS=y
++CONFIG_HOTPLUG=y
++CONFIG_PRINTK=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++# CONFIG_EPOLL is not set
++CONFIG_SHMEM=y
++CONFIG_CC_ALIGN_FUNCTIONS=0
++CONFIG_CC_ALIGN_LABELS=0
++CONFIG_CC_ALIGN_LOOPS=0
++CONFIG_CC_ALIGN_JUMPS=0
++CONFIG_SLAB=y
++# CONFIG_TINY_SHMEM is not set
++CONFIG_BASE_SMALL=0
++# CONFIG_SLOB is not set
++
++#
++# Loadable module support
++#
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++# CONFIG_MODULE_FORCE_UNLOAD is not set
++CONFIG_OBSOLETE_MODPARM=y
++CONFIG_MODVERSIONS=y
++CONFIG_MODULE_SRCVERSION_ALL=y
++# CONFIG_KMOD is not set
++
++#
++# Block layer
++#
++# CONFIG_LBD is not set
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++CONFIG_IOSCHED_AS=y
++CONFIG_IOSCHED_DEADLINE=y
++CONFIG_IOSCHED_CFQ=y
++CONFIG_DEFAULT_AS=y
++# CONFIG_DEFAULT_DEADLINE is not set
++# CONFIG_DEFAULT_CFQ is not set
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="anticipatory"
++
++#
++# Bus options (PCI, PCMCIA, EISA, ISA, TC)
++#
++CONFIG_HW_HAS_PCI=y
++CONFIG_PCI=y
++CONFIG_PCI_LEGACY_PROC=y
++CONFIG_MMU=y
++
++#
++# PCCARD (PCMCIA/CardBus) support
++#
++# CONFIG_PCCARD is not set
++
++#
++# PCI Hotplug Support
++#
++CONFIG_HOTPLUG_PCI=y
++# CONFIG_HOTPLUG_PCI_FAKE is not set
++# CONFIG_HOTPLUG_PCI_CPCI is not set
++# CONFIG_HOTPLUG_PCI_SHPC is not set
++
++#
++# Executable file formats
++#
++CONFIG_BINFMT_ELF=y
++CONFIG_BINFMT_MISC=y
++CONFIG_TRAD_SIGNALS=y
++
++#
++# Networking
++#
++CONFIG_NET=y
++
++#
++# Networking options
++#
++# CONFIG_NETDEBUG is not set
++CONFIG_PACKET=y
++CONFIG_PACKET_MMAP=y
++CONFIG_UNIX=y
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++CONFIG_IP_MULTICAST=y
++# CONFIG_IP_ADVANCED_ROUTER is not set
++CONFIG_IP_FIB_HASH=y
++CONFIG_IP_PNP=y
++CONFIG_IP_PNP_DHCP=y
++CONFIG_IP_PNP_BOOTP=y
++CONFIG_IP_PNP_RARP=y
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE is not set
++CONFIG_IP_MROUTE=y
++# CONFIG_IP_PIMSM_V1 is not set
++# CONFIG_IP_PIMSM_V2 is not set
++CONFIG_ARPD=y
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_TUNNEL is not set
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_BIC=y
++# CONFIG_IPV6 is not set
++# CONFIG_NETFILTER is not set
++
++#
++# DCCP Configuration (EXPERIMENTAL)
++#
++# CONFIG_IP_DCCP is not set
++
++#
++# SCTP Configuration (EXPERIMENTAL)
++#
++# CONFIG_IP_SCTP is not set
++
++#
++# TIPC Configuration (EXPERIMENTAL)
++#
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_BRIDGE is not set
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_NET_DIVERT is not set
++# CONFIG_ECONET is not set
++# CONFIG_WAN_ROUTER is not set
++
++#
++# QoS and/or fair queueing
++#
++# CONFIG_NET_SCHED is not set
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_IEEE80211 is not set
++
++#
++# Device Drivers
++#
++
++#
++# Generic Driver Options
++#
++CONFIG_STANDALONE=y
++CONFIG_PREVENT_FIRMWARE_BUILD=y
++# CONFIG_FW_LOADER is not set
++
++#
++# Connector - unified userspace <-> kernelspace linker
++#
++# CONFIG_CONNECTOR is not set
++
++#
++# Memory Technology Devices (MTD)
++#
++# CONFIG_MTD is not set
++
++#
++# Parallel port support
++#
++# CONFIG_PARPORT is not set
++
++#
++# Plug and Play support
++#
++
++#
++# Block devices
++#
++# CONFIG_BLK_CPQ_DA is not set
++# CONFIG_BLK_CPQ_CISS_DA is not set
++# CONFIG_BLK_DEV_DAC960 is not set
++# CONFIG_BLK_DEV_UMEM is not set
++# CONFIG_BLK_DEV_COW_COMMON is not set
++# CONFIG_BLK_DEV_LOOP is not set
++# CONFIG_BLK_DEV_NBD is not set
++# CONFIG_BLK_DEV_SX8 is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=4096
++CONFIG_BLK_DEV_INITRD=y
++# CONFIG_CDROM_PKTCDVD is not set
++# CONFIG_ATA_OVER_ETH is not set
++
++#
++# ATA/ATAPI/MFM/RLL support
++#
++# CONFIG_IDE is not set
++
++#
++# SCSI device support
++#
++# CONFIG_RAID_ATTRS is not set
++# CONFIG_SCSI is not set
++
++#
++# Multi-device support (RAID and LVM)
++#
++# CONFIG_MD is not set
++
++#
++# Fusion MPT device support
++#
++# CONFIG_FUSION is not set
++
++#
++# IEEE 1394 (FireWire) support
++#
++# CONFIG_IEEE1394 is not set
++
++#
++# I2O device support
++#
++# CONFIG_I2O is not set
++
++#
++# Network device support
++#
++CONFIG_NETDEVICES=y
++# CONFIG_DUMMY is not set
++# CONFIG_BONDING is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_TUN is not set
++
++#
++# ARCnet devices
++#
++# CONFIG_ARCNET is not set
++
++#
++# PHY device support
++#
++CONFIG_PHYLIB=y
++
++#
++# MII PHY device drivers
++#
++# CONFIG_MARVELL_PHY is not set
++# CONFIG_DAVICOM_PHY is not set
++# CONFIG_QSEMI_PHY is not set
++# CONFIG_LXT_PHY is not set
++# CONFIG_CICADA_PHY is not set
++
++#
++# Ethernet (10 or 100Mbit)
++#
++CONFIG_NET_ETHERNET=y
++CONFIG_MII=y
++# CONFIG_HAPPYMEAL is not set
++# CONFIG_SUNGEM is not set
++# CONFIG_CASSINI is not set
++# CONFIG_NET_VENDOR_3COM is not set
++# CONFIG_DM9000 is not set
++
++#
++# Tulip family network device support
++#
++# CONFIG_NET_TULIP is not set
++# CONFIG_HP100 is not set
++CONFIG_NET_PCI=y
++# CONFIG_PCNET32 is not set
++# CONFIG_AMD8111_ETH is not set
++# CONFIG_ADAPTEC_STARFIRE is not set
++# CONFIG_B44 is not set
++# CONFIG_FORCEDETH is not set
++# CONFIG_DGRS is not set
++# CONFIG_EEPRO100 is not set
++CONFIG_E100=y
++# CONFIG_FEALNX is not set
++# CONFIG_NATSEMI is not set
++# CONFIG_NE2K_PCI is not set
++# CONFIG_8139CP is not set
++# CONFIG_8139TOO is not set
++# CONFIG_SIS900 is not set
++# CONFIG_EPIC100 is not set
++# CONFIG_SUNDANCE is not set
++# CONFIG_TLAN is not set
++# CONFIG_VIA_RHINE is not set
++# CONFIG_LAN_SAA9730 is not set
++
++#
++# Ethernet (1000 Mbit)
++#
++# CONFIG_ACENIC is not set
++# CONFIG_DL2K is not set
++# CONFIG_E1000 is not set
++# CONFIG_NS83820 is not set
++# CONFIG_HAMACHI is not set
++# CONFIG_YELLOWFIN is not set
++# CONFIG_R8169 is not set
++# CONFIG_SIS190 is not set
++# CONFIG_SKGE is not set
++# CONFIG_SKY2 is not set
++# CONFIG_SK98LIN is not set
++# CONFIG_VIA_VELOCITY is not set
++# CONFIG_TIGON3 is not set
++# CONFIG_BNX2 is not set
++
++#
++# Ethernet (10000 Mbit)
++#
++# CONFIG_CHELSIO_T1 is not set
++# CONFIG_IXGB is not set
++# CONFIG_S2IO is not set
++
++#
++# Token Ring devices
++#
++# CONFIG_TR is not set
++
++#
++# Wireless LAN (non-hamradio)
++#
++# CONFIG_NET_RADIO is not set
++
++#
++# Wan interfaces
++#
++# CONFIG_WAN is not set
++# CONFIG_FDDI is not set
++# CONFIG_HIPPI is not set
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++# CONFIG_SHAPER is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++
++#
++# ISDN subsystem
++#
++# CONFIG_ISDN is not set
++
++#
++# Telephony Support
++#
++# CONFIG_PHONE is not set
++
++#
++# Input device support
++#
++# CONFIG_INPUT is not set
++
++#
++# Hardware I/O ports
++#
++# CONFIG_SERIO is not set
++# CONFIG_GAMEPORT is not set
++
++#
++# Character devices
++#
++# CONFIG_VT is not set
++# CONFIG_SERIAL_NONSTANDARD is not set
++
++#
++# Serial drivers
++#
++CONFIG_SERIAL_8250=y
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_NR_UARTS=1
++CONFIG_SERIAL_8250_RUNTIME_UARTS=1
++# CONFIG_SERIAL_8250_EXTENDED is not set
++
++#
++# Non-8250 serial port support
++#
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++# CONFIG_SERIAL_JSM is not set
++CONFIG_UNIX98_PTYS=y
++CONFIG_LEGACY_PTYS=y
++CONFIG_LEGACY_PTY_COUNT=256
++
++#
++# IPMI
++#
++# CONFIG_IPMI_HANDLER is not set
++
++#
++# Watchdog Cards
++#
++# CONFIG_WATCHDOG is not set
++CONFIG_RTC=y
++# CONFIG_DTLK is not set
++# CONFIG_R3964 is not set
++# CONFIG_APPLICOM is not set
++
++#
++# Ftape, the floppy tape device driver
++#
++# CONFIG_DRM is not set
++# CONFIG_RAW_DRIVER is not set
++
++#
++# TPM devices
++#
++# CONFIG_TCG_TPM is not set
++# CONFIG_TELCLOCK is not set
++
++#
++# I2C support
++#
++# CONFIG_I2C is not set
++
++#
++# SPI support
++#
++# CONFIG_SPI is not set
++# CONFIG_SPI_MASTER is not set
++
++#
++# Dallas's 1-wire bus
++#
++# CONFIG_W1 is not set
++
++#
++# Hardware Monitoring support
++#
++CONFIG_HWMON=y
++# CONFIG_HWMON_VID is not set
++# CONFIG_SENSORS_F71805F is not set
++# CONFIG_HWMON_DEBUG_CHIP is not set
++
++#
++# Misc devices
++#
++
++#
++# Multimedia Capabilities Port drivers
++#
++
++#
++# Multimedia devices
++#
++# CONFIG_VIDEO_DEV is not set
++
++#
++# Digital Video Broadcasting Devices
++#
++# CONFIG_DVB is not set
++
++#
++# Graphics support
++#
++# CONFIG_FB is not set
++
++#
++# Sound
++#
++# CONFIG_SOUND is not set
++
++#
++# USB support
++#
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB_ARCH_HAS_OHCI=y
++# CONFIG_USB is not set
++
++#
++# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
++#
++
++#
++# USB Gadget Support
++#
++# CONFIG_USB_GADGET is not set
++
++#
++# MMC/SD Card support
++#
++# CONFIG_MMC is not set
++
++#
++# InfiniBand support
++#
++# CONFIG_INFINIBAND is not set
++
++#
++# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
++#
++
++#
++# File systems
++#
++# CONFIG_EXT2_FS is not set
++# CONFIG_EXT3_FS is not set
++# CONFIG_REISERFS_FS is not set
++# CONFIG_JFS_FS is not set
++# CONFIG_FS_POSIX_ACL is not set
++# CONFIG_XFS_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_MINIX_FS is not set
++# CONFIG_ROMFS_FS is not set
++CONFIG_INOTIFY=y
++# CONFIG_QUOTA is not set
++CONFIG_DNOTIFY=y
++# CONFIG_AUTOFS_FS is not set
++# CONFIG_AUTOFS4_FS is not set
++# CONFIG_FUSE_FS is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++# CONFIG_ISO9660_FS is not set
++# CONFIG_UDF_FS is not set
++
++#
++# DOS/FAT/NT Filesystems
++#
++# CONFIG_MSDOS_FS is not set
++# CONFIG_VFAT_FS is not set
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_PROC_KCORE=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++# CONFIG_HUGETLB_PAGE is not set
++CONFIG_RAMFS=y
++# CONFIG_RELAYFS_FS is not set
++# CONFIG_CONFIGFS_FS is not set
++
++#
++# Miscellaneous filesystems
++#
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++# CONFIG_CRAMFS is not set
++# CONFIG_VXFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++
++#
++# Network File Systems
++#
++CONFIG_NFS_FS=y
++CONFIG_NFS_V3=y
++# CONFIG_NFS_V3_ACL is not set
++# CONFIG_NFS_V4 is not set
++# CONFIG_NFS_DIRECTIO is not set
++# CONFIG_NFSD is not set
++CONFIG_ROOT_NFS=y
++CONFIG_LOCKD=y
++CONFIG_LOCKD_V4=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++# CONFIG_RPCSEC_GSS_KRB5 is not set
++# CONFIG_RPCSEC_GSS_SPKM3 is not set
++# CONFIG_SMB_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++# CONFIG_9P_FS is not set
++
++#
++# Partition Types
++#
++# CONFIG_PARTITION_ADVANCED is not set
++CONFIG_MSDOS_PARTITION=y
++
++#
++# Native Language Support
++#
++# CONFIG_NLS is not set
++
++#
++# Profiling support
++#
++# CONFIG_PROFILING is not set
++
++#
++# Kernel hacking
++#
++# CONFIG_PRINTK_TIME is not set
++# CONFIG_MAGIC_SYSRQ is not set
++# CONFIG_DEBUG_KERNEL is not set
++CONFIG_LOG_BUF_SHIFT=14
++CONFIG_CROSSCOMPILE=y
++CONFIG_CMDLINE="console=ttyS0,115200n8"
++
++#
++# Security options
++#
++# CONFIG_KEYS is not set
++# CONFIG_SECURITY is not set
++
++#
++# Cryptographic options
++#
++# CONFIG_CRYPTO is not set
++
++#
++# Hardware crypto devices
++#
++
++#
++# Library routines
++#
++CONFIG_CRC_CCITT=y
++CONFIG_CRC16=y
++CONFIG_CRC32=y
++CONFIG_LIBCRC32C=y
+diff -Naur linux-2.6.17.orig/arch/mips/configs/yosemite_defconfig linux-2.6.17/arch/mips/configs/yosemite_defconfig
+--- linux-2.6.17.orig/arch/mips/configs/yosemite_defconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/configs/yosemite_defconfig	2006-06-19 18:16:13.000000000 -0700
+@@ -41,8 +41,6 @@
+ # CONFIG_MIPS_XXS1500 is not set
+ # CONFIG_PNX8550_V2PCI is not set
+ # CONFIG_PNX8550_JBS is not set
+-# CONFIG_DDB5074 is not set
+-# CONFIG_DDB5476 is not set
+ # CONFIG_DDB5477 is not set
+ # CONFIG_MACH_VR41XX is not set
+ CONFIG_PMC_YOSEMITE=y
+@@ -68,6 +66,7 @@
+ CONFIG_GENERIC_FIND_NEXT_BIT=y
+ CONFIG_GENERIC_HWEIGHT=y
+ CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+ CONFIG_DMA_COHERENT=y
+ CONFIG_CPU_BIG_ENDIAN=y
+ # CONFIG_CPU_LITTLE_ENDIAN is not set
+diff -Naur linux-2.6.17.orig/arch/mips/ddb5xxx/common/prom.c linux-2.6.17/arch/mips/ddb5xxx/common/prom.c
+--- linux-2.6.17.orig/arch/mips/ddb5xxx/common/prom.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/ddb5xxx/common/prom.c	2006-06-19 18:16:13.000000000 -0700
+@@ -56,13 +56,7 @@
+ 
+ 	mips_machgroup = MACH_GROUP_NEC_DDB;
+ 
+-#if defined(CONFIG_DDB5074)
+-	mips_machtype = MACH_NEC_DDB5074;
+-	add_memory_region(0, DDB_SDRAM_SIZE, BOOT_MEM_RAM);
+-#elif defined(CONFIG_DDB5476)
+-	mips_machtype = MACH_NEC_DDB5476;
+-	add_memory_region(0, DDB_SDRAM_SIZE, BOOT_MEM_RAM);
+-#elif defined(CONFIG_DDB5477)
++#if defined(CONFIG_DDB5477)
+ 	ddb5477_runtime_detection();
+ 	add_memory_region(0, board_ram_size, BOOT_MEM_RAM);
+ #endif
+diff -Naur linux-2.6.17.orig/arch/mips/ddb5xxx/ddb5074/irq.c linux-2.6.17/arch/mips/ddb5xxx/ddb5074/irq.c
+--- linux-2.6.17.orig/arch/mips/ddb5xxx/ddb5074/irq.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/ddb5xxx/ddb5074/irq.c	1969-12-31 16:00:00.000000000 -0800
+@@ -1,169 +0,0 @@
+-/*
+- *  arch/mips/ddb5074/irq.c -- NEC DDB Vrc-5074 interrupt routines
+- *
+- *  Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
+- *                     Sony Software Development Center Europe (SDCE), Brussels
+- */
+-#include <linux/init.h>
+-#include <linux/irq.h>
+-#include <linux/signal.h>
+-#include <linux/sched.h>
+-#include <linux/types.h>
+-#include <linux/interrupt.h>
+-#include <linux/ioport.h>
+-
+-#include <asm/i8259.h>
+-#include <asm/io.h>
+-#include <asm/irq_cpu.h>
+-#include <asm/ptrace.h>
+-#include <asm/nile4.h>
+-#include <asm/ddb5xxx/ddb5xxx.h>
+-#include <asm/ddb5xxx/ddb5074.h>
+-
+-
+-static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL };
+-
+-#define M1543_PNP_CONFIG	0x03f0	/* PnP Config Port */
+-#define M1543_PNP_INDEX		0x03f0	/* PnP Index Port */
+-#define M1543_PNP_DATA		0x03f1	/* PnP Data Port */
+-
+-#define M1543_PNP_ALT_CONFIG	0x0370	/* Alternative PnP Config Port */
+-#define M1543_PNP_ALT_INDEX	0x0370	/* Alternative PnP Index Port */
+-#define M1543_PNP_ALT_DATA	0x0371	/* Alternative PnP Data Port */
+-
+-#define M1543_INT1_MASTER_CTRL	0x0020	/* INT_1 (master) Control Register */
+-#define M1543_INT1_MASTER_MASK	0x0021	/* INT_1 (master) Mask Register */
+-
+-#define M1543_INT1_SLAVE_CTRL	0x00a0	/* INT_1 (slave) Control Register */
+-#define M1543_INT1_SLAVE_MASK	0x00a1	/* INT_1 (slave) Mask Register */
+-
+-#define M1543_INT1_MASTER_ELCR	0x04d0	/* INT_1 (master) Edge/Level Control */
+-#define M1543_INT1_SLAVE_ELCR	0x04d1	/* INT_1 (slave) Edge/Level Control */
+-
+-
+-static void m1543_irq_setup(void)
+-{
+-	/*
+-	 *  The ALI M1543 has 13 interrupt inputs, IRQ1..IRQ13.  Not all
+-	 *  the possible IO sources in the M1543 are in use by us.  We will
+-	 *  use the following mapping:
+-	 *
+-	 *      IRQ1  - keyboard (default set by M1543)
+-	 *      IRQ3  - reserved for UART B (default set by M1543) (note that
+-	 *              the schematics for the DDB Vrc-5074 board seem to
+-	 *              indicate that IRQ3 is connected to the DS1386
+-	 *              watchdog timer interrupt output so we might have
+-	 *              a conflict)
+-	 *      IRQ4  - reserved for UART A (default set by M1543)
+-	 *      IRQ5  - parallel (default set by M1543)
+-	 *      IRQ8  - DS1386 time of day (RTC) interrupt
+-	 *      IRQ12 - mouse
+-	 */
+-
+-	/*
+-	 *  Assing mouse interrupt to IRQ12
+-	 */
+-
+-	/* Enter configuration mode */
+-	outb(0x51, M1543_PNP_CONFIG);
+-	outb(0x23, M1543_PNP_CONFIG);
+-
+-	/* Select logical device 7 (Keyboard) */
+-	outb(0x07, M1543_PNP_INDEX);
+-	outb(0x07, M1543_PNP_DATA);
+-
+-	/* Select IRQ12 */
+-	outb(0x72, M1543_PNP_INDEX);
+-	outb(0x0c, M1543_PNP_DATA);
+-
+-	outb(0x30, M1543_PNP_INDEX);
+-	printk("device 7, 0x30: %02x\n",inb(M1543_PNP_DATA));
+-
+-	outb(0x70, M1543_PNP_INDEX);
+-	printk("device 7, 0x70: %02x\n",inb(M1543_PNP_DATA));
+-
+-	/* Leave configration mode */
+-	outb(0xbb, M1543_PNP_CONFIG);
+-
+-
+-}
+-
+-static void ddb_local0_irqdispatch(struct pt_regs *regs)
+-{
+-	u32 mask;
+-	int nile4_irq;
+-
+-	mask = nile4_get_irq_stat(0);
+-
+-	/* Handle the timer interrupt first */
+-#if 0
+-	if (mask & (1 << NILE4_INT_GPT)) {
+-		do_IRQ(nile4_to_irq(NILE4_INT_GPT), regs);
+-		mask &= ~(1 << NILE4_INT_GPT);
+-	}
+-#endif
+-	for (nile4_irq = 0; mask; nile4_irq++, mask >>= 1)
+-		if (mask & 1) {
+-			if (nile4_irq == NILE4_INT_INTE) {
+-				int i8259_irq;
+-
+-				nile4_clear_irq(NILE4_INT_INTE);
+-				i8259_irq = nile4_i8259_iack();
+-				do_IRQ(i8259_irq, regs);
+-			} else
+-				do_IRQ(nile4_to_irq(nile4_irq), regs);
+-
+-		}
+-}
+-
+-static void ddb_local1_irqdispatch(void)
+-{
+-	printk("ddb_local1_irqdispatch called\n");
+-}
+-
+-static void ddb_buserror_irq(void)
+-{
+-	printk("ddb_buserror_irq called\n");
+-}
+-
+-static void ddb_8254timer_irq(void)
+-{
+-	printk("ddb_8254timer_irq called\n");
+-}
+-
+-asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
+-{
+-	unsigned int pending = read_c0_cause() & read_c0_status();
+-
+-	if (pending & CAUSEF_IP2)
+-		ddb_local0_irqdispatch(regs);
+-	else if (pending & CAUSEF_IP3)
+-		ddb_local1_irqdispatch();
+-	else if (pending & CAUSEF_IP6)
+-		ddb_buserror_irq();
+-	else if (pending & (CAUSEF_IP4 | CAUSEF_IP5))
+-		ddb_8254timer_irq();
+-}
+-
+-void __init arch_init_irq(void)
+-{
+-	/* setup cascade interrupts */
+-	setup_irq(NILE4_IRQ_BASE  + NILE4_INT_INTE, &irq_cascade);
+-	setup_irq(CPU_IRQ_BASE + CPU_NILE4_CASCADE, &irq_cascade);
+-
+-	nile4_irq_setup(NILE4_IRQ_BASE);
+-	m1543_irq_setup();
+-	init_i8259_irqs();
+-
+-
+-	printk("CPU_IRQ_BASE: %d\n",CPU_IRQ_BASE);
+-
+-	mips_cpu_irq_init(CPU_IRQ_BASE);
+-
+-	printk("enabling 8259 cascade\n");
+-
+-	ddb5074_led_hex(0);
+-
+-	/* Enable the interrupt cascade */
+-	nile4_enable_irq(NILE4_IRQ_BASE+IRQ_I8259_CASCADE);
+-}
+diff -Naur linux-2.6.17.orig/arch/mips/ddb5xxx/ddb5074/Makefile linux-2.6.17/arch/mips/ddb5xxx/ddb5074/Makefile
+--- linux-2.6.17.orig/arch/mips/ddb5xxx/ddb5074/Makefile	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/ddb5xxx/ddb5074/Makefile	1969-12-31 16:00:00.000000000 -0800
+@@ -1,8 +0,0 @@
+-#
+-# Makefile for the NEC DDB Vrc-5074 specific kernel interface routines
+-# under Linux.
+-#
+-
+-obj-y			+= setup.o irq.o nile4_pic.o
+-
+-EXTRA_AFLAGS := $(CFLAGS)
+diff -Naur linux-2.6.17.orig/arch/mips/ddb5xxx/ddb5074/nile4_pic.c linux-2.6.17/arch/mips/ddb5xxx/ddb5074/nile4_pic.c
+--- linux-2.6.17.orig/arch/mips/ddb5xxx/ddb5074/nile4_pic.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/ddb5xxx/ddb5074/nile4_pic.c	1969-12-31 16:00:00.000000000 -0800
+@@ -1,286 +0,0 @@
+-/*
+- *  arch/mips/ddb5476/nile4.c --
+- *  	low-level PIC code for NEC Vrc-5476 (Nile 4)
+- *
+- *  Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
+- *                     Sony Software Development Center Europe (SDCE), Brussels
+- *
+- *  Copyright 2001 MontaVista Software Inc.
+- *  Author: jsun@mvista.com or jsun@junsun.net
+- *
+- */
+-#include <linux/config.h>
+-#include <linux/kernel.h>
+-#include <linux/types.h>
+-#include <linux/interrupt.h>
+-#include <linux/ioport.h>
+-
+-#include <asm/addrspace.h>
+-
+-#include <asm/ddb5xxx/ddb5xxx.h>
+-
+-static int irq_base;
+-
+-/*
+- *  Interrupt Programming
+- */
+-void nile4_map_irq(int nile4_irq, int cpu_irq)
+-{
+-	u32 offset, t;
+-
+-	offset = DDB_INTCTRL;
+-	if (nile4_irq >= 8) {
+-		offset += 4;
+-		nile4_irq -= 8;
+-	}
+-	t = ddb_in32(offset);
+-	t &= ~(7 << (nile4_irq * 4));
+-	t |= cpu_irq << (nile4_irq * 4);
+-	ddb_out32(offset, t);
+-}
+-
+-void nile4_map_irq_all(int cpu_irq)
+-{
+-	u32 all, t;
+-
+-	all = cpu_irq;
+-	all |= all << 4;
+-	all |= all << 8;
+-	all |= all << 16;
+-	t = ddb_in32(DDB_INTCTRL);
+-	t &= 0x88888888;
+-	t |= all;
+-	ddb_out32(DDB_INTCTRL, t);
+-	t = ddb_in32(DDB_INTCTRL + 4);
+-	t &= 0x88888888;
+-	t |= all;
+-	ddb_out32(DDB_INTCTRL + 4, t);
+-}
+-
+-void nile4_enable_irq(unsigned int nile4_irq)
+-{
+-	u32 offset, t;
+-
+-	nile4_irq-=irq_base;
+-
+-	ddb5074_led_hex(8);
+-
+-	offset = DDB_INTCTRL;
+-	if (nile4_irq >= 8) {
+-		offset += 4;
+-		nile4_irq -= 8;
+-	}
+-	ddb5074_led_hex(9);
+-	t = ddb_in32(offset);
+-	ddb5074_led_hex(0xa);
+-	t |= 8 << (nile4_irq * 4);
+-	ddb_out32(offset, t);
+-	ddb5074_led_hex(0xb);
+-}
+-
+-void nile4_disable_irq(unsigned int nile4_irq)
+-{
+-	u32 offset, t;
+-
+-	nile4_irq-=irq_base;
+-
+-	offset = DDB_INTCTRL;
+-	if (nile4_irq >= 8) {
+-		offset += 4;
+-		nile4_irq -= 8;
+-	}
+-	t = ddb_in32(offset);
+-	t &= ~(8 << (nile4_irq * 4));
+-	ddb_out32(offset, t);
+-}
+-
+-void nile4_disable_irq_all(void)
+-{
+-	ddb_out32(DDB_INTCTRL, 0);
+-	ddb_out32(DDB_INTCTRL + 4, 0);
+-}
+-
+-u16 nile4_get_irq_stat(int cpu_irq)
+-{
+-	return ddb_in16(DDB_INTSTAT0 + cpu_irq * 2);
+-}
+-
+-void nile4_enable_irq_output(int cpu_irq)
+-{
+-	u32 t;
+-
+-	t = ddb_in32(DDB_INTSTAT1 + 4);
+-	t |= 1 << (16 + cpu_irq);
+-	ddb_out32(DDB_INTSTAT1, t);
+-}
+-
+-void nile4_disable_irq_output(int cpu_irq)
+-{
+-	u32 t;
+-
+-	t = ddb_in32(DDB_INTSTAT1 + 4);
+-	t &= ~(1 << (16 + cpu_irq));
+-	ddb_out32(DDB_INTSTAT1, t);
+-}
+-
+-void nile4_set_pci_irq_polarity(int pci_irq, int high)
+-{
+-	u32 t;
+-
+-	t = ddb_in32(DDB_INTPPES);
+-	if (high)
+-		t &= ~(1 << (pci_irq * 2));
+-	else
+-		t |= 1 << (pci_irq * 2);
+-	ddb_out32(DDB_INTPPES, t);
+-}
+-
+-void nile4_set_pci_irq_level_or_edge(int pci_irq, int level)
+-{
+-	u32 t;
+-
+-	t = ddb_in32(DDB_INTPPES);
+-	if (level)
+-		t |= 2 << (pci_irq * 2);
+-	else
+-		t &= ~(2 << (pci_irq * 2));
+-	ddb_out32(DDB_INTPPES, t);
+-}
+-
+-void nile4_clear_irq(int nile4_irq)
+-{
+-	nile4_irq-=irq_base;
+-	ddb_out32(DDB_INTCLR, 1 << nile4_irq);
+-}
+-
+-void nile4_clear_irq_mask(u32 mask)
+-{
+-	ddb_out32(DDB_INTCLR, mask);
+-}
+-
+-u8 nile4_i8259_iack(void)
+-{
+-	u8 irq;
+-	u32 reg;
+-
+-	/* Set window 0 for interrupt acknowledge */
+-	reg = ddb_in32(DDB_PCIINIT0);
+-
+-	ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IACK, 0, DDB_PCI_ACCESS_32);
+-	irq = *(volatile u8 *) KSEG1ADDR(DDB_PCI_IACK_BASE);
+-	/* restore window 0 for PCI I/O space */
+-	// ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32);
+-	ddb_out32(DDB_PCIINIT0, reg);
+-
+-	/* i8269.c set the base vector to be 0x0 */
+-	return irq ;
+-}
+-
+-static unsigned int nile4_irq_startup(unsigned int irq) {
+-
+-	nile4_enable_irq(irq);
+-	return 0;
+-
+-}
+-
+-static void nile4_ack_irq(unsigned int irq) {
+-
+-    ddb5074_led_hex(4);
+-
+-	nile4_clear_irq(irq);
+-    ddb5074_led_hex(2);
+-	nile4_disable_irq(irq);
+-
+-    ddb5074_led_hex(0);
+-}
+-
+-static void nile4_irq_end(unsigned int irq) {
+-
+-	ddb5074_led_hex(3);
+-	if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
+-	ddb5074_led_hex(5);
+-		nile4_enable_irq(irq);
+-	ddb5074_led_hex(7);
+-	}
+-
+-	ddb5074_led_hex(1);
+-}
+-
+-#define nile4_irq_shutdown nile4_disable_irq
+-
+-static hw_irq_controller nile4_irq_controller = {
+-	.typename = "nile4",
+-	.startup = nile4_irq_startup,
+-	.shutdown = nile4_irq_shutdown,
+-	.enable = nile4_enable_irq,
+-	.disable = nile4_disable_irq,
+-	.ack = nile4_ack_irq,
+-	.end = nile4_irq_end,
+-};
+-
+-void nile4_irq_setup(u32 base) {
+-
+-	int i;
+-
+-	irq_base=base;
+-
+-	/* Map all interrupts to CPU int #0 */
+-	nile4_map_irq_all(0);
+-
+-	/* PCI INTA#-E# must be level triggered */
+-	nile4_set_pci_irq_level_or_edge(0, 1);
+-	nile4_set_pci_irq_level_or_edge(1, 1);
+-	nile4_set_pci_irq_level_or_edge(2, 1);
+-	nile4_set_pci_irq_level_or_edge(3, 1);
+-	nile4_set_pci_irq_level_or_edge(4, 1);
+-
+-	/* PCI INTA#-D# must be active low, INTE# must be active high */
+-	nile4_set_pci_irq_polarity(0, 0);
+-	nile4_set_pci_irq_polarity(1, 0);
+-	nile4_set_pci_irq_polarity(2, 0);
+-	nile4_set_pci_irq_polarity(3, 0);
+-	nile4_set_pci_irq_polarity(4, 1);
+-
+-
+-	for (i = 0; i < 16; i++) {
+-		nile4_clear_irq(i);
+-		nile4_disable_irq(i);
+-	}
+-
+-	/* Enable CPU int #0 */
+-	nile4_enable_irq_output(0);
+-
+-	for (i= base; i< base + NUM_NILE4_INTERRUPTS; i++) {
+-		irq_desc[i].status = IRQ_DISABLED;
+-		irq_desc[i].action = NULL;
+-		irq_desc[i].depth = 1;
+-		irq_desc[i].handler = &nile4_irq_controller;
+-	}
+-}
+-
+-#if defined(CONFIG_RUNTIME_DEBUG)
+-void nile4_dump_irq_status(void)
+-{
+-	printk(KERN_DEBUG "
+-	       CPUSTAT = %p:%p\n", (void *) ddb_in32(DDB_CPUSTAT + 4),
+-	       (void *) ddb_in32(DDB_CPUSTAT));
+-	printk(KERN_DEBUG "
+-	       INTCTRL = %p:%p\n", (void *) ddb_in32(DDB_INTCTRL + 4),
+-	       (void *) ddb_in32(DDB_INTCTRL));
+-	printk(KERN_DEBUG
+-	       "INTSTAT0 = %p:%p\n",
+-	       (void *) ddb_in32(DDB_INTSTAT0 + 4),
+-	       (void *) ddb_in32(DDB_INTSTAT0));
+-	printk(KERN_DEBUG
+-	       "INTSTAT1 = %p:%p\n",
+-	       (void *) ddb_in32(DDB_INTSTAT1 + 4),
+-	       (void *) ddb_in32(DDB_INTSTAT1));
+-	printk(KERN_DEBUG
+-	       "INTCLR = %p:%p\n", (void *) ddb_in32(DDB_INTCLR + 4),
+-	       (void *) ddb_in32(DDB_INTCLR));
+-	printk(KERN_DEBUG
+-	       "INTPPES = %p:%p\n", (void *) ddb_in32(DDB_INTPPES + 4),
+-	       (void *) ddb_in32(DDB_INTPPES));
+-}
+-
+-#endif
+diff -Naur linux-2.6.17.orig/arch/mips/ddb5xxx/ddb5074/setup.c linux-2.6.17/arch/mips/ddb5xxx/ddb5074/setup.c
+--- linux-2.6.17.orig/arch/mips/ddb5xxx/ddb5074/setup.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/ddb5xxx/ddb5074/setup.c	1969-12-31 16:00:00.000000000 -0800
+@@ -1,234 +0,0 @@
+-/*
+- *  arch/mips/ddb5074/setup.c -- NEC DDB Vrc-5074 setup routines
+- *
+- *  Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
+- *                     Sony Software Development Center Europe (SDCE), Brussels
+- */
+-#include <linux/init.h>
+-#include <linux/kbd_ll.h>
+-#include <linux/kernel.h>
+-#include <linux/kdev_t.h>
+-#include <linux/types.h>
+-#include <linux/sched.h>
+-#include <linux/pci.h>
+-#include <linux/ide.h>
+-#include <linux/ioport.h>
+-#include <linux/irq.h>
+-#include <linux/pm.h>
+-
+-#include <asm/addrspace.h>
+-#include <asm/bcache.h>
+-#include <asm/irq.h>
+-#include <asm/reboot.h>
+-#include <asm/gdb-stub.h>
+-#include <asm/time.h>
+-#include <asm/nile4.h>
+-#include <asm/ddb5xxx/ddb5074.h>
+-#include <asm/ddb5xxx/ddb5xxx.h>
+-
+-static void (*back_to_prom) (void) = (void (*)(void)) 0xbfc00000;
+-
+-static void ddb_machine_restart(char *command)
+-{
+-	u32 t;
+-
+-	/* PCI cold reset */
+-	t = nile4_in32(NILE4_PCICTRL + 4);
+-	t |= 0x40000000;
+-	nile4_out32(NILE4_PCICTRL + 4, t);
+-	/* CPU cold reset */
+-	t = nile4_in32(NILE4_CPUSTAT);
+-	t |= 1;
+-	nile4_out32(NILE4_CPUSTAT, t);
+-	/* Call the PROM */
+-	back_to_prom();
+-}
+-
+-static void ddb_machine_halt(void)
+-{
+-	printk("DDB Vrc-5074 halted.\n");
+-	do {
+-	} while (1);
+-}
+-
+-static void ddb_machine_power_off(void)
+-{
+-	printk("DDB Vrc-5074 halted. Please turn off the power.\n");
+-	do {
+-	} while (1);
+-}
+-
+-extern void rtc_ds1386_init(unsigned long base);
+-
+-extern void (*board_timer_setup) (struct irqaction * irq);
+-
+-static void __init ddb_timer_init(struct irqaction *irq)
+-{
+-	/* set the clock to 1 Hz */
+-	nile4_out32(NILE4_T2CTRL, 1000000);
+-	/* enable the General-Purpose Timer */
+-	nile4_out32(NILE4_T2CTRL + 4, 0x00000001);
+-	/* reset timer */
+-	nile4_out32(NILE4_T2CNTR, 0);
+-	/* enable interrupt */
+-	setup_irq(nile4_to_irq(NILE4_INT_GPT), irq);
+-	nile4_enable_irq(nile4_to_irq(NILE4_INT_GPT));
+-	change_c0_status(ST0_IM,
+-		          IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4);
+-
+-}
+-
+-static void __init ddb_time_init(void)
+-{
+-	/* we have ds1396 RTC chip */
+-	rtc_ds1386_init(KSEG1ADDR(DDB_PCI_MEM_BASE));
+-}
+-
+-
+-
+-void __init plat_setup(void)
+-{
+-	set_io_port_base(NILE4_PCI_IO_BASE);
+-	isa_slot_offset = NILE4_PCI_MEM_BASE;
+-	board_timer_setup = ddb_timer_init;
+-	board_time_init = ddb_time_init;
+-
+-
+-	_machine_restart = ddb_machine_restart;
+-	_machine_halt = ddb_machine_halt;
+-	pm_power_off = ddb_machine_power_off;
+-
+-	ddb_out32(DDB_BAR0, 0);
+-
+-	ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, 0x10);
+-	ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_MEM, DDB_PCI_MEM_BASE , 0x10);
+-
+-	/* Reboot on panic */
+-	panic_timeout = 180;
+-}
+-
+-#define USE_NILE4_SERIAL	0
+-
+-#if USE_NILE4_SERIAL
+-#define ns16550_in(reg)		nile4_in8((reg)*8)
+-#define ns16550_out(reg, val)	nile4_out8((reg)*8, (val))
+-#else
+-#define NS16550_BASE		(NILE4_PCI_IO_BASE+0x03f8)
+-static inline u8 ns16550_in(u32 reg)
+-{
+-	return *(volatile u8 *) (NS16550_BASE + reg);
+-}
+-
+-static inline void ns16550_out(u32 reg, u8 val)
+-{
+-	*(volatile u8 *) (NS16550_BASE + reg) = val;
+-}
+-#endif
+-
+-#define NS16550_RBR		0
+-#define NS16550_THR		0
+-#define NS16550_DLL		0
+-#define NS16550_IER		1
+-#define NS16550_DLM		1
+-#define NS16550_FCR		2
+-#define NS16550_IIR		2
+-#define NS16550_LCR		3
+-#define NS16550_MCR		4
+-#define NS16550_LSR		5
+-#define NS16550_MSR		6
+-#define NS16550_SCR		7
+-
+-#define NS16550_LSR_DR		0x01	/* Data ready */
+-#define NS16550_LSR_OE		0x02	/* Overrun */
+-#define NS16550_LSR_PE		0x04	/* Parity error */
+-#define NS16550_LSR_FE		0x08	/* Framing error */
+-#define NS16550_LSR_BI		0x10	/* Break */
+-#define NS16550_LSR_THRE	0x20	/* Xmit holding register empty */
+-#define NS16550_LSR_TEMT	0x40	/* Xmitter empty */
+-#define NS16550_LSR_ERR		0x80	/* Error */
+-
+-
+-void _serinit(void)
+-{
+-#if USE_NILE4_SERIAL
+-	ns16550_out(NS16550_LCR, 0x80);
+-	ns16550_out(NS16550_DLM, 0x00);
+-	ns16550_out(NS16550_DLL, 0x36);	/* 9600 baud */
+-	ns16550_out(NS16550_LCR, 0x00);
+-	ns16550_out(NS16550_LCR, 0x03);
+-	ns16550_out(NS16550_FCR, 0x47);
+-#else
+-	/* done by PMON */
+-#endif
+-}
+-
+-void _putc(char c)
+-{
+-	while (!(ns16550_in(NS16550_LSR) & NS16550_LSR_THRE));
+-	ns16550_out(NS16550_THR, c);
+-	if (c == '\n') {
+-		while (!(ns16550_in(NS16550_LSR) & NS16550_LSR_THRE));
+-		ns16550_out(NS16550_THR, '\r');
+-	}
+-}
+-
+-void _puts(const char *s)
+-{
+-	char c;
+-	while ((c = *s++))
+-		_putc(c);
+-}
+-
+-char _getc(void)
+-{
+-	while (!(ns16550_in(NS16550_LSR) & NS16550_LSR_DR));
+-	return ns16550_in(NS16550_RBR);
+-}
+-
+-int _testc(void)
+-{
+-	return (ns16550_in(NS16550_LSR) & NS16550_LSR_DR) != 0;
+-}
+-
+-
+-/*
+- *  Hexadecimal 7-segment LED
+- */
+-void ddb5074_led_hex(int hex)
+-{
+-	outb(hex, 0x80);
+-}
+-
+-
+-/*
+- *  LEDs D2 and D3, connected to the GPIO pins of the PMU in the ALi M1543
+- */
+-struct pci_dev *pci_pmu = NULL;
+-
+-void ddb5074_led_d2(int on)
+-{
+-	u8 t;
+-
+-	if (pci_pmu) {
+-		pci_read_config_byte(pci_pmu, 0x7e, &t);
+-		if (on)
+-			t &= 0x7f;
+-		else
+-			t |= 0x80;
+-		pci_write_config_byte(pci_pmu, 0x7e, t);
+-	}
+-}
+-
+-void ddb5074_led_d3(int on)
+-{
+-	u8 t;
+-
+-	if (pci_pmu) {
+-		pci_read_config_byte(pci_pmu, 0x7e, &t);
+-		if (on)
+-			t &= 0xbf;
+-		else
+-			t |= 0x40;
+-		pci_write_config_byte(pci_pmu, 0x7e, t);
+-	}
+-}
+diff -Naur linux-2.6.17.orig/arch/mips/ddb5xxx/ddb5476/dbg_io.c linux-2.6.17/arch/mips/ddb5xxx/ddb5476/dbg_io.c
+--- linux-2.6.17.orig/arch/mips/ddb5xxx/ddb5476/dbg_io.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/ddb5xxx/ddb5476/dbg_io.c	1969-12-31 16:00:00.000000000 -0800
+@@ -1,136 +0,0 @@
+-/*
+- * kgdb io functions for DDB5476.  We use the second serial port.
+- *
+- * Copyright (C) 2001 MontaVista Software Inc.
+- * Author: jsun@mvista.com or jsun@junsun.net
+- *
+- * This program is free software; you can redistribute  it and/or modify it
+- * under  the terms of  the GNU General  Public License as published by the
+- * Free Software Foundation;  either version 2 of the  License, or (at your
+- * option) any later version.
+- *
+- */
+-
+-/* ======================= CONFIG ======================== */
+-
+-/* [jsun] we use the second serial port for kdb */
+-#define         BASE                    0xa60002f8
+-#define         MAX_BAUD                115200
+-
+-/* distance in bytes between two serial registers */
+-#define         REG_OFFSET              1
+-
+-/*
+- * 0 - kgdb does serial init
+- * 1 - kgdb skip serial init
+- */
+-static int remoteDebugInitialized = 0;
+-
+-/*
+- * the default baud rate *if* kgdb does serial init
+- */
+-#define		BAUD_DEFAULT		UART16550_BAUD_38400
+-
+-/* ======================= END OF CONFIG ======================== */
+-
+-typedef unsigned char uint8;
+-typedef unsigned int uint32;
+-
+-#define         UART16550_BAUD_2400             2400
+-#define         UART16550_BAUD_4800             4800
+-#define         UART16550_BAUD_9600             9600
+-#define         UART16550_BAUD_19200            19200
+-#define         UART16550_BAUD_38400            38400
+-#define         UART16550_BAUD_57600            57600
+-#define         UART16550_BAUD_115200           115200
+-
+-#define         UART16550_PARITY_NONE           0
+-#define         UART16550_PARITY_ODD            0x08
+-#define         UART16550_PARITY_EVEN           0x18
+-#define         UART16550_PARITY_MARK           0x28
+-#define         UART16550_PARITY_SPACE          0x38
+-
+-#define         UART16550_DATA_5BIT             0x0
+-#define         UART16550_DATA_6BIT             0x1
+-#define         UART16550_DATA_7BIT             0x2
+-#define         UART16550_DATA_8BIT             0x3
+-
+-#define         UART16550_STOP_1BIT             0x0
+-#define         UART16550_STOP_2BIT             0x4
+-
+-/* register offset */
+-#define         OFS_RCV_BUFFER          0
+-#define         OFS_TRANS_HOLD          0
+-#define         OFS_SEND_BUFFER         0
+-#define         OFS_INTR_ENABLE         (1*REG_OFFSET)
+-#define         OFS_INTR_ID             (2*REG_OFFSET)
+-#define         OFS_DATA_FORMAT         (3*REG_OFFSET)
+-#define         OFS_LINE_CONTROL        (3*REG_OFFSET)
+-#define         OFS_MODEM_CONTROL       (4*REG_OFFSET)
+-#define         OFS_RS232_OUTPUT        (4*REG_OFFSET)
+-#define         OFS_LINE_STATUS         (5*REG_OFFSET)
+-#define         OFS_MODEM_STATUS        (6*REG_OFFSET)
+-#define         OFS_RS232_INPUT         (6*REG_OFFSET)
+-#define         OFS_SCRATCH_PAD         (7*REG_OFFSET)
+-
+-#define         OFS_DIVISOR_LSB         (0*REG_OFFSET)
+-#define         OFS_DIVISOR_MSB         (1*REG_OFFSET)
+-
+-
+-/* memory-mapped read/write of the port */
+-#define         UART16550_READ(y)    (*((volatile uint8*)(BASE + y)))
+-#define         UART16550_WRITE(y, z)  ((*((volatile uint8*)(BASE + y))) = z)
+-
+-void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
+-{
+-        /* disable interrupts */
+-        UART16550_WRITE(OFS_INTR_ENABLE, 0);
+-
+-        /* set up baud rate */
+-        {
+-                uint32 divisor;
+-
+-                /* set DIAB bit */
+-                UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
+-
+-                /* set divisor */
+-                divisor = MAX_BAUD / baud;
+-                UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
+-                UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
+-
+-                /* clear DIAB bit */
+-                UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
+-        }
+-
+-        /* set data format */
+-        UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
+-}
+-
+-
+-uint8 getDebugChar(void)
+-{
+-        if (!remoteDebugInitialized) {
+-                remoteDebugInitialized = 1;
+-                debugInit(BAUD_DEFAULT,
+-                          UART16550_DATA_8BIT,
+-                          UART16550_PARITY_NONE, UART16550_STOP_1BIT);
+-        }
+-
+-        while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
+-        return UART16550_READ(OFS_RCV_BUFFER);
+-}
+-
+-
+-int putDebugChar(uint8 byte)
+-{
+-        if (!remoteDebugInitialized) {
+-                remoteDebugInitialized = 1;
+-                debugInit(BAUD_DEFAULT,
+-                          UART16550_DATA_8BIT,
+-                          UART16550_PARITY_NONE, UART16550_STOP_1BIT);
+-        }
+-
+-        while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
+-        UART16550_WRITE(OFS_SEND_BUFFER, byte);
+-        return 1;
+-}
+diff -Naur linux-2.6.17.orig/arch/mips/ddb5xxx/ddb5476/irq.c linux-2.6.17/arch/mips/ddb5xxx/ddb5476/irq.c
+--- linux-2.6.17.orig/arch/mips/ddb5xxx/ddb5476/irq.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/ddb5xxx/ddb5476/irq.c	1969-12-31 16:00:00.000000000 -0800
+@@ -1,165 +0,0 @@
+-/*
+- *  arch/mips/ddb5476/irq.c -- NEC DDB Vrc-5476 interrupt routines
+- *
+- *  Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
+- *                     Sony Software Development Center Europe (SDCE), Brussels
+- *
+- * Re-write the whole thing to use new irq.c file.
+- * Copyright (C) 2001 MontaVista Software Inc.
+- * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
+- *
+- */
+-#include <linux/init.h>
+-#include <linux/sched.h>
+-#include <linux/types.h>
+-#include <linux/interrupt.h>
+-
+-#include <asm/i8259.h>
+-#include <asm/io.h>
+-#include <asm/ptrace.h>
+-
+-#include <asm/ddb5xxx/ddb5xxx.h>
+-
+-#define M1543_PNP_CONFIG	0x03f0	/* PnP Config Port */
+-#define M1543_PNP_INDEX		0x03f0	/* PnP Index Port */
+-#define M1543_PNP_DATA		0x03f1	/* PnP Data Port */
+-
+-#define M1543_PNP_ALT_CONFIG	0x0370	/* Alternative PnP Config Port */
+-#define M1543_PNP_ALT_INDEX	0x0370	/* Alternative PnP Index Port */
+-#define M1543_PNP_ALT_DATA	0x0371	/* Alternative PnP Data Port */
+-
+-#define M1543_INT1_MASTER_CTRL	0x0020	/* INT_1 (master) Control Register */
+-#define M1543_INT1_MASTER_MASK	0x0021	/* INT_1 (master) Mask Register */
+-
+-#define M1543_INT1_SLAVE_CTRL	0x00a0	/* INT_1 (slave) Control Register */
+-#define M1543_INT1_SLAVE_MASK	0x00a1	/* INT_1 (slave) Mask Register */
+-
+-#define M1543_INT1_MASTER_ELCR	0x04d0	/* INT_1 (master) Edge/Level Control */
+-#define M1543_INT1_SLAVE_ELCR	0x04d1	/* INT_1 (slave) Edge/Level Control */
+-
+-static void m1543_irq_setup(void)
+-{
+-	/*
+-	 *  The ALI M1543 has 13 interrupt inputs, IRQ1..IRQ13.  Not all
+-	 *  the possible IO sources in the M1543 are in use by us.  We will
+-	 *  use the following mapping:
+-	 *
+-	 *      IRQ1  - keyboard (default set by M1543)
+-	 *      IRQ3  - reserved for UART B (default set by M1543) (note that
+-	 *              the schematics for the DDB Vrc-5476 board seem to
+-	 *              indicate that IRQ3 is connected to the DS1386
+-	 *              watchdog timer interrupt output so we might have
+-	 *              a conflict)
+-	 *      IRQ4  - reserved for UART A (default set by M1543)
+-	 *      IRQ5  - parallel (default set by M1543)
+-	 *      IRQ8  - DS1386 time of day (RTC) interrupt
+-	 *      IRQ9  - USB (hardwired in ddb_setup)
+-	 *      IRQ10 - PMU (hardwired in ddb_setup)
+-	 *      IRQ12 - mouse
+-	 *      IRQ14,15 - IDE controller (need to be confirmed, jsun)
+-	 */
+-
+-	/*
+-	 *  Assing mouse interrupt to IRQ12
+-	 */
+-
+-	/* Enter configuration mode */
+-	outb(0x51, M1543_PNP_CONFIG);
+-	outb(0x23, M1543_PNP_CONFIG);
+-
+-	/* Select logical device 7 (Keyboard) */
+-	outb(0x07, M1543_PNP_INDEX);
+-	outb(0x07, M1543_PNP_DATA);
+-
+-	/* Select IRQ12 */
+-	outb(0x72, M1543_PNP_INDEX);
+-	outb(0x0c, M1543_PNP_DATA);
+-
+-	/* Leave configration mode */
+-	outb(0xbb, M1543_PNP_CONFIG);
+-}
+-
+-static void nile4_irq_setup(void)
+-{
+-	int i;
+-
+-	/* Map all interrupts to CPU int #0 (IP2) */
+-	nile4_map_irq_all(0);
+-
+-	/* PCI INTA#-E# must be level triggered */
+-	nile4_set_pci_irq_level_or_edge(0, 1);
+-	nile4_set_pci_irq_level_or_edge(1, 1);
+-	nile4_set_pci_irq_level_or_edge(2, 1);
+-	nile4_set_pci_irq_level_or_edge(3, 1);
+-
+-	/* PCI INTA#, B#, D# must be active low, INTC# must be active high */
+-	nile4_set_pci_irq_polarity(0, 0);
+-	nile4_set_pci_irq_polarity(1, 0);
+-	nile4_set_pci_irq_polarity(2, 1);
+-	nile4_set_pci_irq_polarity(3, 0);
+-
+-	for (i = 0; i < 16; i++)
+-		nile4_clear_irq(i);
+-
+-	/* Enable CPU int #0 */
+-	nile4_enable_irq_output(0);
+-
+-	/* memory resource acquire in ddb_setup */
+-}
+-
+-static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL };
+-static struct irqaction irq_error = { no_action, 0, CPU_MASK_NONE, "error", NULL, NULL };
+-
+-extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
+-extern void mips_cpu_irq_init(u32 irq_base);
+-extern void vrc5476_irq_init(u32 irq_base);
+-
+-extern void vrc5476_irq_dispatch(struct pt_regs *regs);
+-
+-asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
+-{
+-	unsigned int pending = read_c0_cause() & read_c0_status();
+-
+-	if (pending & STATUSF_IP7)
+-		do_IRQ(CPU_IRQ_BASE + 7, regs);
+-	else if (pending & STATUSF_IP2)
+-		vrc5476_irq_dispatch(regs);
+-	else if (pending & STATUSF_IP3)
+-		do_IRQ(CPU_IRQ_BASE + 3, regs);
+-	else if (pending & STATUSF_IP4)
+-		do_IRQ(CPU_IRQ_BASE + 4, regs);
+-	else if (pending & STATUSF_IP5)
+-		do_IRQ(CPU_IRQ_BASE + 5, regs);
+-	else if (pending & STATUSF_IP6)
+-		do_IRQ(CPU_IRQ_BASE + 6, regs);
+-	else if (pending & STATUSF_IP0)
+-		do_IRQ(CPU_IRQ_BASE, regs);
+-	else if (pending & STATUSF_IP1)
+-		do_IRQ(CPU_IRQ_BASE + 1, regs);
+-
+-	vrc5476_irq_dispatch(regs);
+-}
+-
+-void __init arch_init_irq(void)
+-{
+-	/* hardware initialization */
+-	nile4_irq_setup();
+-	m1543_irq_setup();
+-
+-	/* controller setup */
+-	init_i8259_irqs();
+-	vrc5476_irq_init(VRC5476_IRQ_BASE);
+-	mips_cpu_irq_init(CPU_IRQ_BASE);
+-
+-	/* setup cascade interrupts */
+-	setup_irq(VRC5476_IRQ_BASE + VRC5476_I8259_CASCADE, &irq_cascade);
+-	setup_irq(CPU_IRQ_BASE + CPU_VRC5476_CASCADE, &irq_cascade);
+-
+-	/* setup error interrupts for debugging */
+-	setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_CPCE, &irq_error);
+-	setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_CNTD, &irq_error);
+-	setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_MCE, &irq_error);
+-	setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_LBRT, &irq_error);
+-	setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_PCIS, &irq_error);
+-	setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_PCI, &irq_error);
+-}
+diff -Naur linux-2.6.17.orig/arch/mips/ddb5xxx/ddb5476/Makefile linux-2.6.17/arch/mips/ddb5xxx/ddb5476/Makefile
+--- linux-2.6.17.orig/arch/mips/ddb5xxx/ddb5476/Makefile	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/ddb5xxx/ddb5476/Makefile	1969-12-31 16:00:00.000000000 -0800
+@@ -1,9 +0,0 @@
+-#
+-# Makefile for the NEC DDB Vrc-5476 specific kernel interface routines
+-# under Linux.
+-#
+-
+-obj-y			+= setup.o irq.o nile4_pic.o vrc5476_irq.o
+-obj-$(CONFIG_KGDB)	+= dbg_io.o
+-
+-EXTRA_AFLAGS := $(CFLAGS)
+diff -Naur linux-2.6.17.orig/arch/mips/ddb5xxx/ddb5476/nile4_pic.c linux-2.6.17/arch/mips/ddb5xxx/ddb5476/nile4_pic.c
+--- linux-2.6.17.orig/arch/mips/ddb5xxx/ddb5476/nile4_pic.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/ddb5xxx/ddb5476/nile4_pic.c	1969-12-31 16:00:00.000000000 -0800
+@@ -1,190 +0,0 @@
+-/*
+- *  arch/mips/ddb5476/nile4.c --
+- *  	low-level PIC code for NEC Vrc-5476 (Nile 4)
+- *
+- *  Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
+- *                     Sony Software Development Center Europe (SDCE), Brussels
+- *
+- *  Copyright 2001 MontaVista Software Inc.
+- *  Author: jsun@mvista.com or jsun@junsun.net
+- *
+- */
+-#include <linux/config.h>
+-#include <linux/kernel.h>
+-#include <linux/types.h>
+-
+-#include <asm/addrspace.h>
+-
+-#include <asm/ddb5xxx/ddb5xxx.h>
+-
+-
+-/*
+- *  Interrupt Programming
+- */
+-void nile4_map_irq(int nile4_irq, int cpu_irq)
+-{
+-	u32 offset, t;
+-
+-	offset = DDB_INTCTRL;
+-	if (nile4_irq >= 8) {
+-		offset += 4;
+-		nile4_irq -= 8;
+-	}
+-	t = ddb_in32(offset);
+-	t &= ~(7 << (nile4_irq * 4));
+-	t |= cpu_irq << (nile4_irq * 4);
+-	ddb_out32(offset, t);
+-}
+-
+-void nile4_map_irq_all(int cpu_irq)
+-{
+-	u32 all, t;
+-
+-	all = cpu_irq;
+-	all |= all << 4;
+-	all |= all << 8;
+-	all |= all << 16;
+-	t = ddb_in32(DDB_INTCTRL);
+-	t &= 0x88888888;
+-	t |= all;
+-	ddb_out32(DDB_INTCTRL, t);
+-	t = ddb_in32(DDB_INTCTRL + 4);
+-	t &= 0x88888888;
+-	t |= all;
+-	ddb_out32(DDB_INTCTRL + 4, t);
+-}
+-
+-void nile4_enable_irq(int nile4_irq)
+-{
+-	u32 offset, t;
+-
+-	offset = DDB_INTCTRL;
+-	if (nile4_irq >= 8) {
+-		offset += 4;
+-		nile4_irq -= 8;
+-	}
+-	t = ddb_in32(offset);
+-	t |= 8 << (nile4_irq * 4);
+-	ddb_out32(offset, t);
+-}
+-
+-void nile4_disable_irq(int nile4_irq)
+-{
+-	u32 offset, t;
+-
+-	offset = DDB_INTCTRL;
+-	if (nile4_irq >= 8) {
+-		offset += 4;
+-		nile4_irq -= 8;
+-	}
+-	t = ddb_in32(offset);
+-	t &= ~(8 << (nile4_irq * 4));
+-	ddb_out32(offset, t);
+-}
+-
+-void nile4_disable_irq_all(void)
+-{
+-	ddb_out32(DDB_INTCTRL, 0);
+-	ddb_out32(DDB_INTCTRL + 4, 0);
+-}
+-
+-u16 nile4_get_irq_stat(int cpu_irq)
+-{
+-	return ddb_in16(DDB_INTSTAT0 + cpu_irq * 2);
+-}
+-
+-void nile4_enable_irq_output(int cpu_irq)
+-{
+-	u32 t;
+-
+-	t = ddb_in32(DDB_INTSTAT1 + 4);
+-	t |= 1 << (16 + cpu_irq);
+-	ddb_out32(DDB_INTSTAT1, t);
+-}
+-
+-void nile4_disable_irq_output(int cpu_irq)
+-{
+-	u32 t;
+-
+-	t = ddb_in32(DDB_INTSTAT1 + 4);
+-	t &= ~(1 << (16 + cpu_irq));
+-	ddb_out32(DDB_INTSTAT1, t);
+-}
+-
+-void nile4_set_pci_irq_polarity(int pci_irq, int high)
+-{
+-	u32 t;
+-
+-	t = ddb_in32(DDB_INTPPES);
+-	if (high)
+-		t &= ~(1 << (pci_irq * 2));
+-	else
+-		t |= 1 << (pci_irq * 2);
+-	ddb_out32(DDB_INTPPES, t);
+-}
+-
+-void nile4_set_pci_irq_level_or_edge(int pci_irq, int level)
+-{
+-	u32 t;
+-
+-	t = ddb_in32(DDB_INTPPES);
+-	if (level)
+-		t |= 2 << (pci_irq * 2);
+-	else
+-		t &= ~(2 << (pci_irq * 2));
+-	ddb_out32(DDB_INTPPES, t);
+-}
+-
+-void nile4_clear_irq(int nile4_irq)
+-{
+-	ddb_out32(DDB_INTCLR, 1 << nile4_irq);
+-}
+-
+-void nile4_clear_irq_mask(u32 mask)
+-{
+-	ddb_out32(DDB_INTCLR, mask);
+-}
+-
+-u8 nile4_i8259_iack(void)
+-{
+-	u8 irq;
+-	u32 reg;
+-
+-	/* Set window 0 for interrupt acknowledge */
+-	reg = ddb_in32(DDB_PCIINIT0);
+-
+-	ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IACK, 0, DDB_PCI_ACCESS_32);
+-	irq = *(volatile u8 *) KSEG1ADDR(DDB_PCI_IACK_BASE);
+-	/* restore window 0 for PCI I/O space */
+-	// ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32);
+-	ddb_out32(DDB_PCIINIT0, reg);
+-
+-	/* i8269.c set the base vector to be 0x0 */
+-	return irq + I8259_IRQ_BASE;
+-}
+-
+-#if defined(CONFIG_RUNTIME_DEBUG)
+-void nile4_dump_irq_status(void)
+-{
+-	printk(KERN_DEBUG "
+-	       CPUSTAT = %p:%p\n", (void *) ddb_in32(DDB_CPUSTAT + 4),
+-	       (void *) ddb_in32(DDB_CPUSTAT));
+-	printk(KERN_DEBUG "
+-	       INTCTRL = %p:%p\n", (void *) ddb_in32(DDB_INTCTRL + 4),
+-	       (void *) ddb_in32(DDB_INTCTRL));
+-	printk(KERN_DEBUG
+-	       "INTSTAT0 = %p:%p\n",
+-	       (void *) ddb_in32(DDB_INTSTAT0 + 4),
+-	       (void *) ddb_in32(DDB_INTSTAT0));
+-	printk(KERN_DEBUG
+-	       "INTSTAT1 = %p:%p\n",
+-	       (void *) ddb_in32(DDB_INTSTAT1 + 4),
+-	       (void *) ddb_in32(DDB_INTSTAT1));
+-	printk(KERN_DEBUG
+-	       "INTCLR = %p:%p\n", (void *) ddb_in32(DDB_INTCLR + 4),
+-	       (void *) ddb_in32(DDB_INTCLR));
+-	printk(KERN_DEBUG
+-	       "INTPPES = %p:%p\n", (void *) ddb_in32(DDB_INTPPES + 4),
+-	       (void *) ddb_in32(DDB_INTPPES));
+-}
+-#endif
+diff -Naur linux-2.6.17.orig/arch/mips/ddb5xxx/ddb5476/setup.c linux-2.6.17/arch/mips/ddb5xxx/ddb5476/setup.c
+--- linux-2.6.17.orig/arch/mips/ddb5xxx/ddb5476/setup.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/ddb5xxx/ddb5476/setup.c	1969-12-31 16:00:00.000000000 -0800
+@@ -1,296 +0,0 @@
+-/*
+- *  arch/mips/ddb5476/setup.c -- NEC DDB Vrc-5476 setup routines
+- *
+- *  Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
+- *                     Sony Software Development Center Europe (SDCE), Brussels
+- */
+-#include <linux/init.h>
+-#include <linux/kbd_ll.h>
+-#include <linux/kernel.h>
+-#include <linux/kdev_t.h>
+-#include <linux/types.h>
+-#include <linux/sched.h>
+-#include <linux/pci.h>
+-#include <linux/pm.h>
+-
+-#include <asm/addrspace.h>
+-#include <asm/bcache.h>
+-#include <asm/irq.h>
+-#include <asm/reboot.h>
+-#include <asm/gdb-stub.h>
+-#include <asm/time.h>
+-#include <asm/debug.h>
+-#include <asm/traps.h>
+-
+-#include <asm/ddb5xxx/ddb5xxx.h>
+-
+-// #define USE_CPU_COUNTER_TIMER	/* whether we use cpu counter */
+-
+-#ifdef USE_CPU_COUNTER_TIMER
+-
+-#define CPU_COUNTER_FREQUENCY           83000000
+-#else
+-/* otherwise we use general purpose timer */
+-#define TIMER_FREQUENCY			83000000
+-#define TIMER_BASE			DDB_T2CTRL
+-#define TIMER_IRQ			(VRC5476_IRQ_BASE + VRC5476_IRQ_GPT)
+-#endif
+-
+-static void (*back_to_prom) (void) = (void (*)(void)) 0xbfc00000;
+-
+-static void ddb_machine_restart(char *command)
+-{
+-	u32 t;
+-
+-	/* PCI cold reset */
+-	t = ddb_in32(DDB_PCICTRL + 4);
+-	t |= 0x40000000;
+-	ddb_out32(DDB_PCICTRL + 4, t);
+-	/* CPU cold reset */
+-	t = ddb_in32(DDB_CPUSTAT);
+-	t |= 1;
+-	ddb_out32(DDB_CPUSTAT, t);
+-	/* Call the PROM */
+-	back_to_prom();
+-}
+-
+-static void ddb_machine_halt(void)
+-{
+-	printk(KERN_NOTICE "DDB Vrc-5476 halted.\n");
+-	while (1);
+-}
+-
+-static void ddb_machine_power_off(void)
+-{
+-	printk(KERN_NOTICE "DDB Vrc-5476 halted. Please turn off the power.\n");
+-	while (1);
+-}
+-
+-extern void rtc_ds1386_init(unsigned long base);
+-
+-static void __init ddb_time_init(void)
+-{
+-#if defined(USE_CPU_COUNTER_TIMER)
+-	mips_hpt_frequency = CPU_COUNTER_FREQUENCY;
+-#endif
+-
+-	/* we have ds1396 RTC chip */
+-	rtc_ds1386_init(KSEG1ADDR(DDB_PCI_MEM_BASE));
+-}
+-
+-
+-extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
+-static void __init ddb_timer_setup(struct irqaction *irq)
+-{
+-#if defined(USE_CPU_COUNTER_TIMER)
+-
+-	unsigned int count;
+-
+-	/* we are using the cpu counter for timer interrupts */
+-	setup_irq(CPU_IRQ_BASE + 7, irq);
+-
+-	/* to generate the first timer interrupt */
+-	count = read_c0_count();
+-	write_c0_compare(count + 1000);
+-
+-#else
+-
+-	ddb_out32(TIMER_BASE, TIMER_FREQUENCY/HZ);
+-	ddb_out32(TIMER_BASE+4, 0x1);	/* enable timer */
+-	setup_irq(TIMER_IRQ, irq);
+-#endif
+-}
+-
+-static struct {
+-	struct resource dma1;
+-	struct resource timer;
+-	struct resource rtc;
+-	struct resource dma_page_reg;
+-	struct resource dma2;
+-} ddb5476_ioport = {
+-	{
+-	"dma1", 0x00, 0x1f, IORESOURCE_BUSY}, {
+-	"timer", 0x40, 0x5f, IORESOURCE_BUSY}, {
+-	"rtc", 0x70, 0x7f, IORESOURCE_BUSY}, {
+-	"dma page reg", 0x80, 0x8f, IORESOURCE_BUSY}, {
+-	"dma2", 0xc0, 0xdf, IORESOURCE_BUSY}
+-};
+-
+-static struct {
+-	struct resource nile4;
+-} ddb5476_iomem = {
+-	{ "Nile 4", DDB_BASE, DDB_BASE + DDB_SIZE - 1, IORESOURCE_BUSY}
+-};
+-
+-
+-static void ddb5476_board_init(void);
+-
+-void __init plat_setup(void)
+-{
+-	set_io_port_base(KSEG1ADDR(DDB_PCI_IO_BASE));
+-
+-	board_time_init = ddb_time_init;
+-	board_timer_setup = ddb_timer_setup;
+-
+-	_machine_restart = ddb_machine_restart;
+-	_machine_halt = ddb_machine_halt;
+-	pm_power_off = ddb_machine_power_off;
+-
+-	/* request io port/mem resources  */
+-	if (request_resource(&ioport_resource, &ddb5476_ioport.dma1) ||
+-	    request_resource(&ioport_resource, &ddb5476_ioport.timer) ||
+-	    request_resource(&ioport_resource, &ddb5476_ioport.rtc) ||
+-	    request_resource(&ioport_resource,
+-			     &ddb5476_ioport.dma_page_reg)
+-	    || request_resource(&ioport_resource, &ddb5476_ioport.dma2)
+-	    || request_resource(&iomem_resource, &ddb5476_iomem.nile4)) {
+-		printk
+-		    ("ddb_setup - requesting oo port resources failed.\n");
+-		for (;;);
+-	}
+-
+-	/* Reboot on panic */
+-	panic_timeout = 180;
+-
+-	/* [jsun] we need to set BAR0 so that SDRAM 0 appears at 0x0 in PCI */
+-	/* *(long*)0xbfa00218 = 0x8; */
+-
+-	/* board initialization stuff */
+-	ddb5476_board_init();
+-}
+-
+-/*
+- * We don't trust bios.  We essentially does hardware re-initialization
+- * as complete as possible, as far as we know we can safely do.
+- */
+-static void ddb5476_board_init(void)
+-{
+-	/* ----------- setup PDARs ------------ */
+-	/* check SDRAM0, whether we are on MEM bus does not matter */
+-	db_assert((ddb_in32(DDB_SDRAM0) & 0xffffffef) ==
+-		  ddb_calc_pdar(DDB_SDRAM_BASE, DDB_SDRAM_SIZE, 32, 0, 1));
+-
+-	/* SDRAM1 should be turned off.  What is this for anyway ? */
+-	db_assert( (ddb_in32(DDB_SDRAM1) & 0xf) == 0);
+-
+-	/* flash 1&2, DDB status, DDB control */
+-	ddb_set_pdar(DDB_DCS2, DDB_DCS2_BASE, DDB_DCS2_SIZE, 16, 0, 0);
+-	ddb_set_pdar(DDB_DCS3, DDB_DCS3_BASE, DDB_DCS3_SIZE, 16, 0, 0);
+-	ddb_set_pdar(DDB_DCS4, DDB_DCS4_BASE, DDB_DCS4_SIZE, 8, 0, 0);
+-	ddb_set_pdar(DDB_DCS5, DDB_DCS5_BASE, DDB_DCS5_SIZE, 8, 0, 0);
+-
+-	/* shut off other pdar so they don't accidentally get into the way */
+-	ddb_set_pdar(DDB_DCS6, 0xffffffff, 0, 32, 0, 0);
+-	ddb_set_pdar(DDB_DCS7, 0xffffffff, 0, 32, 0, 0);
+-	ddb_set_pdar(DDB_DCS8, 0xffffffff, 0, 32, 0, 0);
+-
+-	/* verify VRC5477 base addr */
+-	/* don't care about some details */
+-	db_assert((ddb_in32(DDB_INTCS) & 0xffffff0f) ==
+-		  ddb_calc_pdar(DDB_INTCS_BASE, DDB_INTCS_SIZE, 8, 0, 0));
+-
+-	/* verify BOOT ROM addr */
+-	/* don't care about some details */
+-	db_assert((ddb_in32(DDB_BOOTCS) & 0xffffff0f) ==
+-		  ddb_calc_pdar(DDB_BOOTCS_BASE, DDB_BOOTCS_SIZE, 8, 0, 0));
+-
+-	/* setup PCI windows - window1 for MEM/config, window0 for IO */
+-	ddb_set_pdar(DDB_PCIW0, DDB_PCI_IO_BASE, DDB_PCI_IO_SIZE, 32, 0, 1);
+-	ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32);
+-
+-	ddb_set_pdar(DDB_PCIW1, DDB_PCI_MEM_BASE, DDB_PCI_MEM_SIZE, 32, 0, 1);
+-	ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_MEM, DDB_PCI_MEM_BASE, DDB_PCI_ACCESS_32);
+-
+-	/* ----------- setup PDARs ------------ */
+-	/* this is problematic - it will reset Aladin which cause we loose
+-	 * serial port, and we don't know how to set up Aladin chip again.
+-	 */
+-	// ddb_pci_reset_bus();
+-
+-	ddb_out32(DDB_BAR0, 0x00000008);
+-
+-	ddb_out32(DDB_BARC, 0xffffffff);
+-	ddb_out32(DDB_BARB, 0xffffffff);
+-	ddb_out32(DDB_BAR1, 0xffffffff);
+-	ddb_out32(DDB_BAR2, 0xffffffff);
+-	ddb_out32(DDB_BAR3, 0xffffffff);
+-	ddb_out32(DDB_BAR4, 0xffffffff);
+-	ddb_out32(DDB_BAR5, 0xffffffff);
+-	ddb_out32(DDB_BAR6, 0xffffffff);
+-	ddb_out32(DDB_BAR7, 0xffffffff);
+-	ddb_out32(DDB_BAR8, 0xffffffff);
+-
+-	/* ----------- switch PCI1 to PCI CONFIG space  ------------ */
+-	ddb_set_pdar(DDB_PCIW1, DDB_PCI_CONFIG_BASE, DDB_PCI_CONFIG_SIZE, 32, 0, 1);
+-	ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_CFG, 0x0, DDB_PCI_ACCESS_32);
+-
+-	/* ----- M1543 PCI setup ------ */
+-
+-	/* we know M1543 PCI-ISA controller is at addr:18 */
+-	/* xxxx1010 makes USB at addr:13 and PMU at addr:14 */
+-	*(volatile unsigned char *) 0xa8040072 &= 0xf0;
+-	*(volatile unsigned char *) 0xa8040072 |= 0xa;
+-
+-	/* setup USB interrupt to IRQ 9, (bit 0:3 - 0001)
+-	 * no IOCHRDY signal, (bit 7 - 1)
+-	 * M1543C & M7101 VID and Subsys Device ID are read-only (bit 6 - 1)
+-	 * Make USB Master INTAJ level to edge conversion (bit 4 - 1)
+-	 */
+-	*(unsigned char *) 0xa8040074 = 0xd1;
+-
+-	/* setup PMU(SCI to IRQ 10 (bit 0:3 - 0011)
+-	 * SCI routing to IRQ 13 disabled (bit 7 - 1)
+-	 * SCI interrupt level to edge conversion bypassed (bit 4 - 0)
+-	 */
+-	*(unsigned char *) 0xa8040076 = 0x83;
+-
+-	/* setup IDE controller
+-	 * enable IDE controller (bit 6 - 1)
+-	 * IDE IDSEL to be addr:24 (bit 4:5 - 11)
+-	 * no IDE ATA Secondary Bus Signal Pad Control (bit 3 - 0)
+-	 * no IDE ATA Primary Bus Signal Pad Control (bit 2 - 0)
+-	 * primary IRQ is 14, secondary is 15 (bit 1:0 - 01
+-	 */
+-	// *(unsigned char*)0xa8040058 = 0x71;
+-	// *(unsigned char*)0xa8040058 = 0x79;
+-	// *(unsigned char*)0xa8040058 = 0x74;              // use SIRQ, primary tri-state
+-	*(unsigned char *) 0xa8040058 = 0x75;	// primary tri-state
+-
+-#if 0
+-	/* this is not necessary if M5229 does not use SIRQ */
+-	*(unsigned char *) 0xa8040044 = 0x0d;	// primary to IRQ 14
+-	*(unsigned char *) 0xa8040075 = 0x0d;	// secondary to IRQ 14
+-#endif
+-
+-	/* enable IDE in the M5229 config register 0x50 (bit 0 - 1) */
+-	/* M5229 IDSEL is addr:24; see above setting */
+-	*(unsigned char *) 0xa9000050 |= 0x1;
+-
+-	/* enable bus master (bit 2)  and IO decoding  (bit 0) */
+-	*(unsigned char *) 0xa9000004 |= 0x5;
+-
+-	/* enable native, copied from arch/ppc/k2boot/head.S */
+-	/* TODO - need volatile, need to be portable */
+-	*(unsigned char *) 0xa9000009 = 0xff;
+-
+-	/* ----- end of M1543 PCI setup ------ */
+-
+-	/* ----- reset on-board ether chip  ------ */
+-	*((volatile u32 *) 0xa8020004) |= 1;	/* decode I/O */
+-	*((volatile u32 *) 0xa8020010) = 0;	/* set BAR address */
+-
+-	/* send reset command */
+-	*((volatile u32 *) 0xa6000000) = 1;	/* do a soft reset */
+-
+-	/* disable ether chip */
+-	*((volatile u32 *) 0xa8020004) = 0;	/* disable any decoding */
+-
+-	/* put it into sleep */
+-	*((volatile u32 *) 0xa8020040) = 0x80000000;
+-
+-	/* ----- end of reset on-board ether chip  ------ */
+-
+-	/* ----------- switch PCI1 back to PCI MEM space  ------------ */
+-	ddb_set_pdar(DDB_PCIW1, DDB_PCI_MEM_BASE, DDB_PCI_MEM_SIZE, 32, 0, 1);
+-	ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_MEM, DDB_PCI_MEM_BASE, DDB_PCI_ACCESS_32);
+-}
+diff -Naur linux-2.6.17.orig/arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c linux-2.6.17/arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c
+--- linux-2.6.17.orig/arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c	1969-12-31 16:00:00.000000000 -0800
+@@ -1,109 +0,0 @@
+-/*
+- * The irq controller for vrc5476.
+- *
+- * Copyright (C) 2001 MontaVista Software Inc.
+- * Author: jsun@mvista.com or jsun@junsun.net
+- *
+- * This program is free software; you can redistribute  it and/or modify it
+- * under  the terms of  the GNU General  Public License as published by the
+- * Free Software Foundation;  either version 2 of the  License, or (at your
+- * option) any later version.
+- *
+- */
+-#include <linux/init.h>
+-#include <linux/interrupt.h>
+-#include <linux/irq.h>
+-#include <linux/types.h>
+-#include <linux/ptrace.h>
+-
+-#include <asm/system.h>
+-
+-#include <asm/ddb5xxx/ddb5xxx.h>
+-
+-static int irq_base;
+-
+-static void vrc5476_irq_enable(uint irq)
+-{
+-	nile4_enable_irq(irq - irq_base);
+-}
+-
+-static void vrc5476_irq_disable(uint irq)
+-{
+-	nile4_disable_irq(irq - irq_base);
+-}
+-
+-static unsigned int vrc5476_irq_startup(uint irq)
+-{
+-	nile4_enable_irq(irq - irq_base);
+-	return 0;
+-}
+-
+-#define vrc5476_irq_shutdown	vrc5476_irq_disable
+-
+-static void vrc5476_irq_ack(uint irq)
+-{
+-	nile4_clear_irq(irq - irq_base);
+-	nile4_disable_irq(irq - irq_base);
+-}
+-
+-static void vrc5476_irq_end(uint irq)
+-{
+-	if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
+-		vrc5476_irq_enable(irq);
+-}
+-
+-static hw_irq_controller vrc5476_irq_controller = {
+-	.typename = "vrc5476",
+-	.startup = vrc5476_irq_startup,
+-	.shutdown = vrc5476_irq_shutdown,
+-	.enable = vrc5476_irq_enable,
+-	.disable = vrc5476_irq_disable,
+-	.ack = vrc5476_irq_ack,
+-	.end = vrc5476_irq_end
+-};
+-
+-void __init
+-vrc5476_irq_init(u32 base)
+-{
+-	u32 i;
+-
+-	irq_base = base;
+-	for (i= base; i< base + NUM_VRC5476_IRQ; i++) {
+-		irq_desc[i].status = IRQ_DISABLED;
+-		irq_desc[i].action = NULL;
+-		irq_desc[i].depth = 1;
+-		irq_desc[i].handler = &vrc5476_irq_controller;
+-	}
+-}
+-
+-
+-void
+-vrc5476_irq_dispatch(struct pt_regs *regs)
+-{
+-	u32 mask;
+-	int nile4_irq;
+-
+-	mask = nile4_get_irq_stat(0);
+-
+-	/* quick check for possible time interrupt */
+-	if (mask & (1 << VRC5476_IRQ_GPT)) {
+-		do_IRQ(VRC5476_IRQ_BASE + VRC5476_IRQ_GPT, regs);
+-		return;
+-	}
+-
+-	/* check for i8259 interrupts */
+-	if (mask & (1 << VRC5476_I8259_CASCADE)) {
+-		int i8259_irq = nile4_i8259_iack();
+-		do_IRQ(I8259_IRQ_BASE + i8259_irq, regs);
+-		return;
+-	}
+-
+-	/* regular nile4 interrupts (we should not really have any */
+-	for (nile4_irq = 0; mask; nile4_irq++, mask >>= 1) {
+-		if (mask & 1) {
+-			do_IRQ(VRC5476_IRQ_BASE + nile4_irq, regs);
+-			return;
+-		}
+-	}
+-	spurious_interrupt(regs);
+-}
+diff -Naur linux-2.6.17.orig/arch/mips/ddb5xxx/ddb5477/setup.c linux-2.6.17/arch/mips/ddb5xxx/ddb5477/setup.c
+--- linux-2.6.17.orig/arch/mips/ddb5xxx/ddb5477/setup.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/ddb5xxx/ddb5477/setup.c	2006-06-19 18:16:13.000000000 -0700
+@@ -171,7 +171,7 @@
+ extern struct pci_controller ddb5477_ext_controller;
+ extern struct pci_controller ddb5477_io_controller;
+ 
+-void __init plat_setup(void)
++void __init plat_mem_setup(void)
+ {
+ 	/* initialize board - we don't trust the loader */
+         ddb5477_board_init();
+diff -Naur linux-2.6.17.orig/arch/mips/dec/setup.c linux-2.6.17/arch/mips/dec/setup.c
+--- linux-2.6.17.orig/arch/mips/dec/setup.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/dec/setup.c	2006-06-19 18:16:13.000000000 -0700
+@@ -147,7 +147,7 @@
+ extern void dec_time_init(void);
+ extern void dec_timer_setup(struct irqaction *);
+ 
+-void __init plat_setup(void)
++void __init plat_mem_setup(void)
+ {
+ 	board_be_init = dec_be_init;
+ 	board_time_init = dec_time_init;
+diff -Naur linux-2.6.17.orig/arch/mips/defconfig linux-2.6.17/arch/mips/defconfig
+--- linux-2.6.17.orig/arch/mips/defconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/defconfig	2006-06-19 18:16:13.000000000 -0700
+@@ -41,8 +41,6 @@
+ # CONFIG_MIPS_XXS1500 is not set
+ # CONFIG_PNX8550_V2PCI is not set
+ # CONFIG_PNX8550_JBS is not set
+-# CONFIG_DDB5074 is not set
+-# CONFIG_DDB5476 is not set
+ # CONFIG_DDB5477 is not set
+ # CONFIG_MACH_VR41XX is not set
+ # CONFIG_PMC_YOSEMITE is not set
+@@ -67,6 +65,7 @@
+ CONFIG_GENERIC_FIND_NEXT_BIT=y
+ CONFIG_GENERIC_HWEIGHT=y
+ CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+ CONFIG_ARC=y
+ CONFIG_DMA_NONCOHERENT=y
+ CONFIG_DMA_NEED_PCI_MAP_STATE=y
+diff -Naur linux-2.6.17.orig/arch/mips/emma2rh/common/irq.c linux-2.6.17/arch/mips/emma2rh/common/irq.c
+--- linux-2.6.17.orig/arch/mips/emma2rh/common/irq.c	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/arch/mips/emma2rh/common/irq.c	2006-06-19 18:16:13.000000000 -0700
+@@ -0,0 +1,108 @@
++/*
++ *  arch/mips/emma2rh/common/irq.c
++ *      This file is common irq dispatcher.
++ *
++ *  Copyright (C) NEC Electronics Corporation 2005-2006
++ *
++ *  This file is based on the arch/mips/ddb5xxx/ddb5477/irq.c
++ *
++ *	Copyright 2001 MontaVista Software Inc.
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License as published by
++ *  the Free Software Foundation; either version 2 of the License, or
++ *  (at your option) any later version.
++ *
++ *  This program is distributed in the hope that it will be useful,
++ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *  GNU General Public License for more details.
++ *
++ *  You should have received a copy of the GNU General Public License
++ *  along with this program; if not, write to the Free Software
++ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
++ */
++#include <linux/config.h>
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/irq.h>
++#include <linux/types.h>
++
++#include <asm/i8259.h>
++#include <asm/system.h>
++#include <asm/mipsregs.h>
++#include <asm/debug.h>
++#include <asm/addrspace.h>
++#include <asm/bootinfo.h>
++
++#include <asm/emma2rh/emma2rh.h>
++
++/*
++ * the first level int-handler will jump here if it is a emma2rh irq
++ */
++asmlinkage void emma2rh_irq_dispatch(struct pt_regs *regs)
++{
++	u32 intStatus;
++	u32 bitmask;
++	u32 i;
++
++	intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_0)
++	    & emma2rh_in32(EMMA2RH_BHIF_INT_EN_0);
++
++#ifdef EMMA2RH_SW_CASCADE
++	if (intStatus &
++	    (1 << ((EMMA2RH_SW_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) {
++		u32 swIntStatus;
++		swIntStatus = emma2rh_in32(EMMA2RH_BHIF_SW_INT)
++		    & emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
++		for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
++			if (swIntStatus & bitmask) {
++				do_IRQ(EMMA2RH_SW_IRQ_BASE + i, regs);
++				return;
++			}
++		}
++	}
++#endif
++
++	for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
++		if (intStatus & bitmask) {
++			do_IRQ(EMMA2RH_IRQ_BASE + i, regs);
++			return;
++		}
++	}
++
++	intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_1)
++	    & emma2rh_in32(EMMA2RH_BHIF_INT_EN_1);
++
++#ifdef EMMA2RH_GPIO_CASCADE
++	if (intStatus &
++	    (1 << ((EMMA2RH_GPIO_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) {
++		u32 gpioIntStatus;
++		gpioIntStatus = emma2rh_in32(EMMA2RH_GPIO_INT_ST)
++		    & emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
++		for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
++			if (gpioIntStatus & bitmask) {
++				do_IRQ(EMMA2RH_GPIO_IRQ_BASE + i, regs);
++				return;
++			}
++		}
++	}
++#endif
++
++	for (i = 32, bitmask = 1; i < 64; i++, bitmask <<= 1) {
++		if (intStatus & bitmask) {
++			do_IRQ(EMMA2RH_IRQ_BASE + i, regs);
++			return;
++		}
++	}
++
++	intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_2)
++	    & emma2rh_in32(EMMA2RH_BHIF_INT_EN_2);
++
++	for (i = 64, bitmask = 1; i < 96; i++, bitmask <<= 1) {
++		if (intStatus & bitmask) {
++			do_IRQ(EMMA2RH_IRQ_BASE + i, regs);
++			return;
++		}
++	}
++}
+diff -Naur linux-2.6.17.orig/arch/mips/emma2rh/common/irq_emma2rh.c linux-2.6.17/arch/mips/emma2rh/common/irq_emma2rh.c
+--- linux-2.6.17.orig/arch/mips/emma2rh/common/irq_emma2rh.c	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/arch/mips/emma2rh/common/irq_emma2rh.c	2006-06-19 18:16:13.000000000 -0700
+@@ -0,0 +1,134 @@
++/*
++ *  arch/mips/emma2rh/common/irq_emma2rh.c
++ *      This file defines the irq handler for EMMA2RH.
++ *
++ *  Copyright (C) NEC Electronics Corporation 2005-2006
++ *
++ *  This file is based on the arch/mips/ddb5xxx/ddb5477/irq_5477.c
++ *
++ *	Copyright 2001 MontaVista Software Inc.
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License as published by
++ *  the Free Software Foundation; either version 2 of the License, or
++ *  (at your option) any later version.
++ *
++ *  This program is distributed in the hope that it will be useful,
++ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *  GNU General Public License for more details.
++ *
++ *  You should have received a copy of the GNU General Public License
++ *  along with this program; if not, write to the Free Software
++ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
++ */
++
++/*
++ * EMMA2RH defines 64 IRQs.
++ *
++ * This file exports one function:
++ *	emma2rh_irq_init(u32 irq_base);
++ */
++
++#include <linux/interrupt.h>
++#include <linux/types.h>
++#include <linux/ptrace.h>
++
++#include <asm/debug.h>
++
++#include <asm/emma2rh/emma2rh.h>
++
++/* number of total irqs supported by EMMA2RH */
++#define	NUM_EMMA2RH_IRQ		96
++
++static int emma2rh_irq_base = -1;
++
++void ll_emma2rh_irq_enable(int);
++void ll_emma2rh_irq_disable(int);
++
++static void emma2rh_irq_enable(unsigned int irq)
++{
++	ll_emma2rh_irq_enable(irq - emma2rh_irq_base);
++}
++
++static void emma2rh_irq_disable(unsigned int irq)
++{
++	ll_emma2rh_irq_disable(irq - emma2rh_irq_base);
++}
++
++static unsigned int emma2rh_irq_startup(unsigned int irq)
++{
++	emma2rh_irq_enable(irq);
++	return 0;
++}
++
++#define	emma2rh_irq_shutdown	emma2rh_irq_disable
++
++static void emma2rh_irq_ack(unsigned int irq)
++{
++	/* disable interrupt - some handler will re-enable the irq
++	 * and if the interrupt is leveled, we will have infinite loop
++	 */
++	ll_emma2rh_irq_disable(irq - emma2rh_irq_base);
++}
++
++static void emma2rh_irq_end(unsigned int irq)
++{
++	if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
++		ll_emma2rh_irq_enable(irq - emma2rh_irq_base);
++}
++
++hw_irq_controller emma2rh_irq_controller = {
++	.typename = "emma2rh_irq",
++	.startup = emma2rh_irq_startup,
++	.shutdown = emma2rh_irq_shutdown,
++	.enable = emma2rh_irq_enable,
++	.disable = emma2rh_irq_disable,
++	.ack = emma2rh_irq_ack,
++	.end = emma2rh_irq_end,
++	.set_affinity = NULL	/* no affinity stuff for UP */
++};
++
++void emma2rh_irq_init(u32 irq_base)
++{
++	u32 i;
++
++	for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ; i++) {
++		irq_desc[i].status = IRQ_DISABLED;
++		irq_desc[i].action = NULL;
++		irq_desc[i].depth = 1;
++		irq_desc[i].handler = &emma2rh_irq_controller;
++	}
++
++	emma2rh_irq_base = irq_base;
++}
++
++void ll_emma2rh_irq_enable(int emma2rh_irq)
++{
++	u32 reg_value;
++	u32 reg_bitmask;
++	u32 reg_index;
++
++	reg_index = EMMA2RH_BHIF_INT_EN_0
++	    + (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0)
++	    * (emma2rh_irq / 32);
++	reg_value = emma2rh_in32(reg_index);
++	reg_bitmask = 0x1 << (emma2rh_irq % 32);
++	db_assert((reg_value & reg_bitmask) == 0);
++	emma2rh_out32(reg_index, reg_value | reg_bitmask);
++}
++
++void ll_emma2rh_irq_disable(int emma2rh_irq)
++{
++	u32 reg_value;
++	u32 reg_bitmask;
++	u32 reg_index;
++
++	reg_index = EMMA2RH_BHIF_INT_EN_0
++	    + (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0)
++	    * (emma2rh_irq / 32);
++	reg_value = emma2rh_in32(reg_index);
++	reg_bitmask = 0x1 << (emma2rh_irq % 32);
++	db_assert((reg_value & reg_bitmask) != 0);
++	emma2rh_out32(reg_index, reg_value & ~reg_bitmask);
++}
+diff -Naur linux-2.6.17.orig/arch/mips/emma2rh/common/Makefile linux-2.6.17/arch/mips/emma2rh/common/Makefile
+--- linux-2.6.17.orig/arch/mips/emma2rh/common/Makefile	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/arch/mips/emma2rh/common/Makefile	2006-06-19 18:16:13.000000000 -0700
+@@ -0,0 +1,13 @@
++#
++#  arch/mips/emma2rh/common/Makefile
++#       Makefile for the common code of NEC EMMA2RH based board.
++#
++#  Copyright (C) NEC Electronics Corporation 2005-2006
++#
++#  This program is free software; you can redistribute it and/or modify
++#  it under the terms of the GNU General Public License as published by
++#  the Free Software Foundation; either version 2 of the License, or
++#  (at your option) any later version.
++#
++
++obj-$(CONFIG_MARKEINS)	+= irq.o irq_emma2rh.o prom.o
+diff -Naur linux-2.6.17.orig/arch/mips/emma2rh/common/prom.c linux-2.6.17/arch/mips/emma2rh/common/prom.c
+--- linux-2.6.17.orig/arch/mips/emma2rh/common/prom.c	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/arch/mips/emma2rh/common/prom.c	2006-06-19 18:16:13.000000000 -0700
+@@ -0,0 +1,77 @@
++/*
++ *  arch/mips/emma2rh/common/prom.c
++ *      This file is prom file.
++ *
++ *  Copyright (C) NEC Electronics Corporation 2004-2006
++ *
++ *  This file is based on the arch/mips/ddb5xxx/common/prom.c
++ *
++ *	Copyright 2001 MontaVista Software Inc.
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License as published by
++ *  the Free Software Foundation; either version 2 of the License, or
++ *  (at your option) any later version.
++ *
++ *  This program is distributed in the hope that it will be useful,
++ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *  GNU General Public License for more details.
++ *
++ *  You should have received a copy of the GNU General Public License
++ *  along with this program; if not, write to the Free Software
++ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
++ */
++#include <linux/config.h>
++#include <linux/init.h>
++#include <linux/mm.h>
++#include <linux/sched.h>
++#include <linux/bootmem.h>
++
++#include <asm/addrspace.h>
++#include <asm/bootinfo.h>
++#include <asm/emma2rh/emma2rh.h>
++#include <asm/debug.h>
++
++const char *get_system_type(void)
++{
++	switch (mips_machtype) {
++	case MACH_NEC_MARKEINS:
++		return "NEC EMMA2RH Mark-eins";
++	default:
++		return "Unknown NEC board";
++	}
++}
++
++/* [jsun@junsun.net] PMON passes arguments in C main() style */
++void __init prom_init(void)
++{
++	int argc = fw_arg0;
++	char **arg = (char **)fw_arg1;
++	int i;
++
++	/* if user passes kernel args, ignore the default one */
++	if (argc > 1)
++		arcs_cmdline[0] = '\0';
++
++	/* arg[0] is "g", the rest is boot parameters */
++	for (i = 1; i < argc; i++) {
++		if (strlen(arcs_cmdline) + strlen(arg[i] + 1)
++		    >= sizeof(arcs_cmdline))
++			break;
++		strcat(arcs_cmdline, arg[i]);
++		strcat(arcs_cmdline, " ");
++	}
++
++	mips_machgroup = MACH_GROUP_NEC_EMMA2RH;
++
++#if defined(CONFIG_MARKEINS)
++	mips_machtype = MACH_NEC_MARKEINS;
++	add_memory_region(0, EMMA2RH_RAM_SIZE, BOOT_MEM_RAM);
++#endif
++
++}
++
++void __init prom_free_prom_memory(void)
++{
++}
+diff -Naur linux-2.6.17.orig/arch/mips/emma2rh/markeins/irq.c linux-2.6.17/arch/mips/emma2rh/markeins/irq.c
+--- linux-2.6.17.orig/arch/mips/emma2rh/markeins/irq.c	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/arch/mips/emma2rh/markeins/irq.c	2006-06-19 18:16:13.000000000 -0700
+@@ -0,0 +1,134 @@
++/*
++ *  arch/mips/emma2rh/markeins/irq.c
++ *      This file defines the irq handler for EMMA2RH.
++ *
++ *  Copyright (C) NEC Electronics Corporation 2004-2006
++ *
++ *  This file is based on the arch/mips/ddb5xxx/ddb5477/irq.c
++ *
++ *	Copyright 2001 MontaVista Software Inc.
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License as published by
++ *  the Free Software Foundation; either version 2 of the License, or
++ *  (at your option) any later version.
++ *
++ *  This program is distributed in the hope that it will be useful,
++ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *  GNU General Public License for more details.
++ *
++ *  You should have received a copy of the GNU General Public License
++ *  along with this program; if not, write to the Free Software
++ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
++ */
++#include <linux/config.h>
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/irq.h>
++#include <linux/types.h>
++#include <linux/ptrace.h>
++#include <linux/delay.h>
++
++#include <asm/i8259.h>
++#include <asm/irq_cpu.h>
++#include <asm/system.h>
++#include <asm/mipsregs.h>
++#include <asm/debug.h>
++#include <asm/addrspace.h>
++#include <asm/bootinfo.h>
++
++#include <asm/emma2rh/emma2rh.h>
++
++/*
++ * IRQ mapping
++ *
++ *  0-7: 8 CPU interrupts
++ *	0 -	software interrupt 0
++ *	1 - 	software interrupt 1
++ *	2 - 	most Vrc5477 interrupts are routed to this pin
++ *	3 - 	(optional) some other interrupts routed to this pin for debugg
++ *	4 - 	not used
++ *	5 - 	not used
++ *	6 - 	not used
++ *	7 - 	cpu timer (used by default)
++ *
++ */
++
++extern void emma2rh_sw_irq_init(u32 base);
++extern void emma2rh_gpio_irq_init(u32 base);
++extern void emma2rh_irq_init(u32 base);
++extern asmlinkage void emma2rh_irq_dispatch(struct pt_regs *regs);
++
++static struct irqaction irq_cascade = {
++	   .handler = no_action,
++	   .flags = 0,
++	   .mask = CPU_MASK_NONE,
++	   .name = "cascade",
++	   .dev_id = NULL,
++	   .next = NULL,
++};
++
++void __init arch_init_irq(void)
++{
++	u32 reg;
++
++	db_run(printk("markeins_irq_setup invoked.\n"));
++
++	/* by default, interrupts are disabled. */
++	emma2rh_out32(EMMA2RH_BHIF_INT_EN_0, 0);
++	emma2rh_out32(EMMA2RH_BHIF_INT_EN_1, 0);
++	emma2rh_out32(EMMA2RH_BHIF_INT_EN_2, 0);
++	emma2rh_out32(EMMA2RH_BHIF_INT1_EN_0, 0);
++	emma2rh_out32(EMMA2RH_BHIF_INT1_EN_1, 0);
++	emma2rh_out32(EMMA2RH_BHIF_INT1_EN_2, 0);
++	emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, 0);
++
++	clear_c0_status(0xff00);
++	set_c0_status(0x0400);
++
++#define GPIO_PCI (0xf<<15)
++	/* setup GPIO interrupt for PCI interface */
++	/* direction input */
++	reg = emma2rh_in32(EMMA2RH_GPIO_DIR);
++	emma2rh_out32(EMMA2RH_GPIO_DIR, reg & ~GPIO_PCI);
++	/* disable interrupt */
++	reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
++	emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg & ~GPIO_PCI);
++	/* level triggerd */
++	reg = emma2rh_in32(EMMA2RH_GPIO_INT_MODE);
++	emma2rh_out32(EMMA2RH_GPIO_INT_MODE, reg | GPIO_PCI);
++	reg = emma2rh_in32(EMMA2RH_GPIO_INT_CND_A);
++	emma2rh_out32(EMMA2RH_GPIO_INT_CND_A, reg & (~GPIO_PCI));
++	/* interrupt clear */
++	emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~GPIO_PCI);
++
++	/* init all controllers */
++	emma2rh_irq_init(EMMA2RH_IRQ_BASE);
++	emma2rh_sw_irq_init(EMMA2RH_SW_IRQ_BASE);
++	emma2rh_gpio_irq_init(EMMA2RH_GPIO_IRQ_BASE);
++	mips_cpu_irq_init(CPU_IRQ_BASE);
++
++	/* setup cascade interrupts */
++	setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_SW_CASCADE, &irq_cascade);
++	setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_GPIO_CASCADE, &irq_cascade);
++	setup_irq(CPU_IRQ_BASE + CPU_EMMA2RH_CASCADE, &irq_cascade);
++}
++
++asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
++{
++        unsigned int pending = read_c0_status() & read_c0_cause();
++
++	if (pending & STATUSF_IP7)
++		do_IRQ(CPU_IRQ_BASE + 7, regs);
++	else if (pending & STATUSF_IP2)
++		emma2rh_irq_dispatch(regs);
++	else if (pending & STATUSF_IP1)
++		do_IRQ(CPU_IRQ_BASE + 1, regs);
++	else if (pending & STATUSF_IP0)
++		do_IRQ(CPU_IRQ_BASE + 0, regs);
++	else
++		spurious_interrupt(regs);
++}
++
++
+diff -Naur linux-2.6.17.orig/arch/mips/emma2rh/markeins/irq_markeins.c linux-2.6.17/arch/mips/emma2rh/markeins/irq_markeins.c
+--- linux-2.6.17.orig/arch/mips/emma2rh/markeins/irq_markeins.c	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/arch/mips/emma2rh/markeins/irq_markeins.c	2006-06-19 18:16:13.000000000 -0700
+@@ -0,0 +1,197 @@
++/*
++ *  arch/mips/emma2rh/markeins/irq_markeins.c
++ *      This file defines the irq handler for Mark-eins.
++ *
++ *  Copyright (C) NEC Electronics Corporation 2004-2006
++ *
++ *  This file is based on the arch/mips/ddb5xxx/ddb5477/irq_5477.c
++ *
++ *	Copyright 2001 MontaVista Software Inc.
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License as published by
++ *  the Free Software Foundation; either version 2 of the License, or
++ *  (at your option) any later version.
++ *
++ *  This program is distributed in the hope that it will be useful,
++ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *  GNU General Public License for more details.
++ *
++ *  You should have received a copy of the GNU General Public License
++ *  along with this program; if not, write to the Free Software
++ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
++ */
++#include <linux/interrupt.h>
++#include <linux/irq.h>
++#include <linux/types.h>
++#include <linux/ptrace.h>
++
++#include <asm/debug.h>
++#include <asm/emma2rh/emma2rh.h>
++
++static int emma2rh_sw_irq_base = -1;
++static int emma2rh_gpio_irq_base = -1;
++
++void ll_emma2rh_sw_irq_enable(int reg);
++void ll_emma2rh_sw_irq_disable(int reg);
++void ll_emma2rh_gpio_irq_enable(int reg);
++void ll_emma2rh_gpio_irq_disable(int reg);
++
++static void emma2rh_sw_irq_enable(unsigned int irq)
++{
++	ll_emma2rh_sw_irq_enable(irq - emma2rh_sw_irq_base);
++}
++
++static void emma2rh_sw_irq_disable(unsigned int irq)
++{
++	ll_emma2rh_sw_irq_disable(irq - emma2rh_sw_irq_base);
++}
++
++static unsigned int emma2rh_sw_irq_startup(unsigned int irq)
++{
++	emma2rh_sw_irq_enable(irq);
++	return 0;
++}
++
++#define emma2rh_sw_irq_shutdown emma2rh_sw_irq_disable
++
++static void emma2rh_sw_irq_ack(unsigned int irq)
++{
++	ll_emma2rh_sw_irq_disable(irq - emma2rh_sw_irq_base);
++}
++
++static void emma2rh_sw_irq_end(unsigned int irq)
++{
++	if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
++		ll_emma2rh_sw_irq_enable(irq - emma2rh_sw_irq_base);
++}
++
++hw_irq_controller emma2rh_sw_irq_controller = {
++	.typename = "emma2rh_sw_irq",
++	.startup = emma2rh_sw_irq_startup,
++	.shutdown = emma2rh_sw_irq_shutdown,
++	.enable = emma2rh_sw_irq_enable,
++	.disable = emma2rh_sw_irq_disable,
++	.ack = emma2rh_sw_irq_ack,
++	.end = emma2rh_sw_irq_end,
++	.set_affinity = NULL,
++};
++
++void emma2rh_sw_irq_init(u32 irq_base)
++{
++	u32 i;
++
++	for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ_SW; i++) {
++		irq_desc[i].status = IRQ_DISABLED;
++		irq_desc[i].action = NULL;
++		irq_desc[i].depth = 2;
++		irq_desc[i].handler = &emma2rh_sw_irq_controller;
++	}
++
++	emma2rh_sw_irq_base = irq_base;
++}
++
++void ll_emma2rh_sw_irq_enable(int irq)
++{
++	u32 reg;
++
++	db_assert(irq >= 0);
++	db_assert(irq < NUM_EMMA2RH_IRQ_SW);
++
++	reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
++	reg |= 1 << irq;
++	emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg);
++}
++
++void ll_emma2rh_sw_irq_disable(int irq)
++{
++	u32 reg;
++
++	db_assert(irq >= 0);
++	db_assert(irq < 32);
++
++	reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
++	reg &= ~(1 << irq);
++	emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg);
++}
++
++static void emma2rh_gpio_irq_enable(unsigned int irq)
++{
++	ll_emma2rh_gpio_irq_enable(irq - emma2rh_gpio_irq_base);
++}
++
++static void emma2rh_gpio_irq_disable(unsigned int irq)
++{
++	ll_emma2rh_gpio_irq_disable(irq - emma2rh_gpio_irq_base);
++}
++
++static unsigned int emma2rh_gpio_irq_startup(unsigned int irq)
++{
++	emma2rh_gpio_irq_enable(irq);
++	return 0;
++}
++
++#define emma2rh_gpio_irq_shutdown emma2rh_gpio_irq_disable
++
++static void emma2rh_gpio_irq_ack(unsigned int irq)
++{
++	irq -= emma2rh_gpio_irq_base;
++	emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq));
++	ll_emma2rh_gpio_irq_disable(irq);
++}
++
++static void emma2rh_gpio_irq_end(unsigned int irq)
++{
++	if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
++		ll_emma2rh_gpio_irq_enable(irq - emma2rh_gpio_irq_base);
++}
++
++hw_irq_controller emma2rh_gpio_irq_controller = {
++	.typename = "emma2rh_gpio_irq",
++	.startup = emma2rh_gpio_irq_startup,
++	.shutdown = emma2rh_gpio_irq_shutdown,
++	.enable = emma2rh_gpio_irq_enable,
++	.disable = emma2rh_gpio_irq_disable,
++	.ack = emma2rh_gpio_irq_ack,
++	.end = emma2rh_gpio_irq_end,
++	.set_affinity = NULL,
++};
++
++void emma2rh_gpio_irq_init(u32 irq_base)
++{
++	u32 i;
++
++	for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ_GPIO; i++) {
++		irq_desc[i].status = IRQ_DISABLED;
++		irq_desc[i].action = NULL;
++		irq_desc[i].depth = 2;
++		irq_desc[i].handler = &emma2rh_gpio_irq_controller;
++	}
++
++	emma2rh_gpio_irq_base = irq_base;
++}
++
++void ll_emma2rh_gpio_irq_enable(int irq)
++{
++	u32 reg;
++
++	db_assert(irq >= 0);
++	db_assert(irq < NUM_EMMA2RH_IRQ_GPIO);
++
++	reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
++	reg |= 1 << irq;
++	emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
++}
++
++void ll_emma2rh_gpio_irq_disable(int irq)
++{
++	u32 reg;
++
++	db_assert(irq >= 0);
++	db_assert(irq < NUM_EMMA2RH_IRQ_GPIO);
++
++	reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
++	reg &= ~(1 << irq);
++	emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
++}
+diff -Naur linux-2.6.17.orig/arch/mips/emma2rh/markeins/led.c linux-2.6.17/arch/mips/emma2rh/markeins/led.c
+--- linux-2.6.17.orig/arch/mips/emma2rh/markeins/led.c	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/arch/mips/emma2rh/markeins/led.c	2006-06-19 18:16:13.000000000 -0700
+@@ -0,0 +1,60 @@
++/*
++ *  arch/mips/emma2rh/markeins/led.c
++ *      This file defines the led display for Mark-eins.
++ *
++ *  Copyright (C) NEC Electronics Corporation 2004-2006
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License as published by
++ *  the Free Software Foundation; either version 2 of the License, or
++ *  (at your option) any later version.
++ *
++ *  This program is distributed in the hope that it will be useful,
++ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *  GNU General Public License for more details.
++ *
++ *  You should have received a copy of the GNU General Public License
++ *  along with this program; if not, write to the Free Software
++ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
++ */
++#include <linux/kernel.h>
++#include <linux/types.h>
++#include <linux/string.h>
++#include <asm/emma2rh/emma2rh.h>
++
++const unsigned long clear = 0x20202020;
++
++#define LED_BASE 0xb1400038
++
++void markeins_led_clear(void)
++{
++	emma2rh_out32(LED_BASE, clear);
++	emma2rh_out32(LED_BASE + 4, clear);
++}
++
++void markeins_led(const char *str)
++{
++	int i;
++	int len = strlen(str);
++
++	markeins_led_clear();
++	if (len > 8)
++		len = 8;
++
++	if (emma2rh_in32(0xb0000800) & (0x1 << 18))
++		for (i = 0; i < len; i++)
++			emma2rh_out8(LED_BASE + i, str[i]);
++	else
++		for (i = 0; i < len; i++)
++			emma2rh_out8(LED_BASE + (i & 4) + (3 - (i & 3)),
++				     str[i]);
++}
++
++void markeins_led_hex(u32 val)
++{
++	char str[10];
++
++	sprintf(str, "%08x", val);
++	markeins_led(str);
++}
+diff -Naur linux-2.6.17.orig/arch/mips/emma2rh/markeins/Makefile linux-2.6.17/arch/mips/emma2rh/markeins/Makefile
+--- linux-2.6.17.orig/arch/mips/emma2rh/markeins/Makefile	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/arch/mips/emma2rh/markeins/Makefile	2006-06-19 18:16:13.000000000 -0700
+@@ -0,0 +1,13 @@
++#
++#  arch/mips/emma2rh/markeins/Makefile
++#       Makefile for the common code of NEC EMMA2RH based board.
++#
++#  Copyright (C) NEC Electronics Corporation 2005-2006
++#
++#  This program is free software; you can redistribute it and/or modify
++#  it under the terms of the GNU General Public License as published by
++#  the Free Software Foundation; either version 2 of the License, or
++#  (at your option) any later version.
++#
++
++obj-$(CONFIG_MARKEINS) += irq.o irq_markeins.o setup.o led.o platform.o
+diff -Naur linux-2.6.17.orig/arch/mips/emma2rh/markeins/platform.c linux-2.6.17/arch/mips/emma2rh/markeins/platform.c
+--- linux-2.6.17.orig/arch/mips/emma2rh/markeins/platform.c	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/arch/mips/emma2rh/markeins/platform.c	2006-06-19 18:16:13.000000000 -0700
+@@ -0,0 +1,170 @@
++/*
++ *  arch/mips/emma2rh/markeins/platofrm.c
++ *      This file sets up platform devices for EMMA2RH Mark-eins.
++ *
++ *  Copyright(C) MontaVista Software Inc, 2006
++ *
++ *  Author: dmitry pervushin <dpervushin@ru.mvista.com>
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License as published by
++ *  the Free Software Foundation; either version 2 of the License, or
++ *  (at your option) any later version.
++ *
++ *  This program is distributed in the hope that it will be useful,
++ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *  GNU General Public License for more details.
++ *
++ *  You should have received a copy of the GNU General Public License
++ *  along with this program; if not, write to the Free Software
++ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
++ */
++#include <linux/config.h>
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/types.h>
++#include <linux/ioport.h>
++#include <linux/serial_8250.h>
++#include <linux/mtd/physmap.h>
++
++#include <asm/cpu.h>
++#include <asm/bootinfo.h>
++#include <asm/addrspace.h>
++#include <asm/time.h>
++#include <asm/bcache.h>
++#include <asm/irq.h>
++#include <asm/reboot.h>
++#include <asm/gdb-stub.h>
++#include <asm/traps.h>
++#include <asm/debug.h>
++
++#include <asm/emma2rh/emma2rh.h>
++
++
++#define I2C_EMMA2RH "emma2rh-iic" /* must be in sync with IIC driver */
++
++static struct resource i2c_emma_resources_0[] = {
++	{ NULL, EMMA2RH_IRQ_PIIC0, EMMA2RH_IRQ_PIIC0, IORESOURCE_IRQ },
++	{ NULL, KSEG1ADDR(EMMA2RH_PIIC0_BASE), KSEG1ADDR(EMMA2RH_PIIC0_BASE + 0x1000), 0 },
++};
++
++struct resource i2c_emma_resources_1[] = {
++	{ NULL, EMMA2RH_IRQ_PIIC1, EMMA2RH_IRQ_PIIC1, IORESOURCE_IRQ },
++	{ NULL, KSEG1ADDR(EMMA2RH_PIIC1_BASE), KSEG1ADDR(EMMA2RH_PIIC1_BASE + 0x1000), 0 },
++};
++
++struct resource i2c_emma_resources_2[] = {
++	{ NULL, EMMA2RH_IRQ_PIIC2, EMMA2RH_IRQ_PIIC2, IORESOURCE_IRQ },
++	{ NULL, KSEG1ADDR(EMMA2RH_PIIC2_BASE), KSEG1ADDR(EMMA2RH_PIIC2_BASE + 0x1000), 0 },
++};
++
++struct platform_device i2c_emma_devices[] = {
++	[0] = {
++		.name = I2C_EMMA2RH,
++		.id = 0,
++		.resource = i2c_emma_resources_0,
++		.num_resources = ARRAY_SIZE(i2c_emma_resources_0),
++	},
++	[1] = {
++		.name = I2C_EMMA2RH,
++		.id = 1,
++		.resource = i2c_emma_resources_1,
++		.num_resources = ARRAY_SIZE(i2c_emma_resources_1),
++	},
++	[2] = {
++		.name = I2C_EMMA2RH,
++		.id = 2,
++		.resource = i2c_emma_resources_2,
++		.num_resources = ARRAY_SIZE(i2c_emma_resources_2),
++	},
++};
++
++#define EMMA2RH_SERIAL_CLOCK 18544000
++#define EMMA2RH_SERIAL_FLAGS UPF_BOOT_AUTOCONF | UPF_SKIP_TEST
++
++static struct  plat_serial8250_port platform_serial_ports[] = {
++       [0] = {
++         .membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR0_BASE + 3),
++         .irq = EMMA2RH_IRQ_PFUR0,
++         .uartclk = EMMA2RH_SERIAL_CLOCK,
++         .regshift = 4,
++         .iotype = UPIO_MEM,
++         .flags = EMMA2RH_SERIAL_FLAGS,
++       },
++       [1] = {
++         .membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR1_BASE + 3),
++         .irq = EMMA2RH_IRQ_PFUR1,
++         .uartclk = EMMA2RH_SERIAL_CLOCK,
++         .regshift = 4,
++         .iotype = UPIO_MEM,
++         .flags = EMMA2RH_SERIAL_FLAGS,
++       },
++       [2] = {
++         .membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR2_BASE + 3),
++         .irq = EMMA2RH_IRQ_PFUR2,
++         .uartclk = EMMA2RH_SERIAL_CLOCK,
++         .regshift = 4,
++         .iotype = UPIO_MEM,
++         .flags = EMMA2RH_SERIAL_FLAGS,
++       },
++       [3] = {
++	 .flags = 0,
++       },
++};
++
++static struct  platform_device serial_emma = {
++	.name = "serial8250",
++	.dev = {
++		.platform_data = &platform_serial_ports,
++	},
++};
++
++static struct platform_device *devices[] = {
++	&i2c_emma_devices[0],
++	&i2c_emma_devices[1],
++	&i2c_emma_devices[2],
++	&serial_emma,
++};
++
++static struct mtd_partition markeins_parts[] = {
++	[0] = {
++		.name = "RootFS",
++		.offset = 0x00000000,
++		.size = 0x00c00000,
++	},
++	[1] = {
++		.name = "boot code area",
++		.offset = MTDPART_OFS_APPEND,
++		.size = 0x00100000,
++	},
++	[2] = {
++		.name = "kernel image",
++		.offset = MTDPART_OFS_APPEND,
++		.size = 0x00300000,
++	},
++	[3] = {
++		.name = "RootFS2",
++		.offset = MTDPART_OFS_APPEND,
++		.size = 0x00c00000,
++	},
++	[4] = {
++		.name = "boot code area2",
++		.offset = MTDPART_OFS_APPEND,
++		.size = 0x00100000,
++	},
++	[5] = {
++		.name = "kernel image2",
++		.offset = MTDPART_OFS_APPEND,
++		.size = MTDPART_SIZ_FULL,
++	},
++};
++
++static int __init platform_devices_setup(void)
++{
++	physmap_set_partitions(markeins_parts, ARRAY_SIZE(markeins_parts));
++	return platform_add_devices(devices, ARRAY_SIZE(devices));
++}
++
++arch_initcall(platform_devices_setup);
++
+diff -Naur linux-2.6.17.orig/arch/mips/emma2rh/markeins/setup.c linux-2.6.17/arch/mips/emma2rh/markeins/setup.c
+--- linux-2.6.17.orig/arch/mips/emma2rh/markeins/setup.c	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/arch/mips/emma2rh/markeins/setup.c	2006-06-19 18:16:13.000000000 -0700
+@@ -0,0 +1,182 @@
++/*
++ *  arch/mips/emma2rh/markeins/setup.c
++ *      This file is setup for EMMA2RH Mark-eins.
++ *
++ *  Copyright (C) NEC Electronics Corporation 2004-2006
++ *
++ *  This file is based on the arch/mips/ddb5xxx/ddb5477/setup.c.
++ *
++ *	Copyright 2001 MontaVista Software Inc.
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License as published by
++ *  the Free Software Foundation; either version 2 of the License, or
++ *  (at your option) any later version.
++ *
++ *  This program is distributed in the hope that it will be useful,
++ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *  GNU General Public License for more details.
++ *
++ *  You should have received a copy of the GNU General Public License
++ *  along with this program; if not, write to the Free Software
++ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
++ */
++#include <linux/config.h>
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/types.h>
++#include <linux/initrd.h>
++#include <linux/irq.h>
++#include <linux/ide.h>
++#include <linux/ioport.h>
++#include <linux/param.h>	/* for HZ */
++#include <linux/root_dev.h>
++#include <linux/serial.h>
++#include <linux/serial_core.h>
++
++#include <asm/cpu.h>
++#include <asm/bootinfo.h>
++#include <asm/addrspace.h>
++#include <asm/time.h>
++#include <asm/bcache.h>
++#include <asm/irq.h>
++#include <asm/reboot.h>
++#include <asm/gdb-stub.h>
++#include <asm/traps.h>
++#include <asm/debug.h>
++
++#include <asm/emma2rh/emma2rh.h>
++
++#define	USE_CPU_COUNTER_TIMER	/* whether we use cpu counter */
++
++extern void markeins_led(const char *);
++
++static int bus_frequency = 0;
++
++static void markeins_machine_restart(char *command)
++{
++	static void (*back_to_prom) (void) = (void (*)(void))0xbfc00000;
++
++	printk("cannot EMMA2RH Mark-eins restart.\n");
++	markeins_led("restart.");
++	back_to_prom();
++}
++
++static void markeins_machine_halt(void)
++{
++	printk("EMMA2RH Mark-eins halted.\n");
++	markeins_led("halted.");
++	while (1) ;
++}
++
++static void markeins_machine_power_off(void)
++{
++	printk("EMMA2RH Mark-eins halted. Please turn off the power.\n");
++	markeins_led("poweroff.");
++	while (1) ;
++}
++
++static unsigned long clock[4] = { 166500000, 187312500, 199800000, 210600000 };
++
++static unsigned int __init detect_bus_frequency(unsigned long rtc_base)
++{
++	u32 reg;
++
++	/* detect from boot strap */
++	reg = emma2rh_in32(EMMA2RH_BHIF_STRAP_0);
++	reg = (reg >> 4) & 0x3;
++	return clock[reg];
++}
++
++static void __init emma2rh_time_init(void)
++{
++	u32 reg;
++	if (bus_frequency == 0)
++		bus_frequency = detect_bus_frequency(0);
++
++	reg = emma2rh_in32(EMMA2RH_BHIF_STRAP_0);
++	if ((reg & 0x3) == 0)
++		reg = (reg >> 6) & 0x3;
++	else {
++		reg = emma2rh_in32(EMMA2RH_BHIF_MAIN_CTRL);
++		reg = (reg >> 4) & 0x3;
++	}
++	mips_hpt_frequency = (bus_frequency * (4 + reg)) / 4 / 2;
++}
++
++static void __init emma2rh_timer_setup(struct irqaction *irq)
++{
++	/* we are using the cpu counter for timer interrupts */
++	setup_irq(CPU_IRQ_BASE + 7, irq);
++}
++
++static void markeins_board_init(void);
++extern void markeins_irq_setup(void);
++
++static void inline __init markeins_sio_setup(void)
++{
++#ifdef CONFIG_KGDB_8250
++	struct uart_port emma_port;
++
++	memset(&emma_port, 0, sizeof(emma_port));
++
++	emma_port.flags =
++	    UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
++	emma_port.iotype = UPIO_MEM;
++	emma_port.regshift = 4;	/* I/O addresses are every 8 bytes */
++	emma_port.uartclk = 18544000;	/* Clock rate of the chip */
++
++	emma_port.line = 0;
++	emma_port.mapbase = KSEG1ADDR(EMMA2RH_PFUR0_BASE + 3);
++	emma_port.membase = (u8*)emma_port.mapbase;
++	early_serial_setup(&emma_port);
++
++	emma_port.line = 1;
++	emma_port.mapbase = KSEG1ADDR(EMMA2RH_PFUR1_BASE + 3);
++	emma_port.membase = (u8*)emma_port.mapbase;
++	early_serial_setup(&emma_port);
++
++	emma_port.irq = EMMA2RH_IRQ_PFUR1;
++	kgdb8250_add_port(1, &emma_port);
++#endif
++}
++
++void __init plat_mem_setup(void)
++{
++	/* initialize board - we don't trust the loader */
++	markeins_board_init();
++
++	set_io_port_base(KSEG1ADDR(EMMA2RH_PCI_IO_BASE));
++
++	board_time_init = emma2rh_time_init;
++	board_timer_setup = emma2rh_timer_setup;
++
++	_machine_restart = markeins_machine_restart;
++	_machine_halt = markeins_machine_halt;
++	pm_power_off = markeins_machine_power_off;
++
++	/* setup resource limits */
++	ioport_resource.start = EMMA2RH_PCI_IO_BASE;
++	ioport_resource.end = EMMA2RH_PCI_IO_BASE + EMMA2RH_PCI_IO_SIZE - 1;
++	iomem_resource.start = EMMA2RH_IO_BASE;
++	iomem_resource.end = EMMA2RH_ROM_BASE - 1;
++
++	/* Reboot on panic */
++	panic_timeout = 180;
++
++	markeins_sio_setup();
++}
++
++static void __init markeins_board_init(void)
++{
++	u32 val;
++
++	val = emma2rh_in32(EMMA2RH_PBRD_INT_EN);	/* open serial interrupts. */
++	emma2rh_out32(EMMA2RH_PBRD_INT_EN, val | 0xaa);
++	val = emma2rh_in32(EMMA2RH_PBRD_CLKSEL);	/* set serial clocks. */
++	emma2rh_out32(EMMA2RH_PBRD_CLKSEL, val | 0x5);	/* 18MHz */
++	emma2rh_out32(EMMA2RH_PCI_CONTROL, 0);
++
++	markeins_led("MVL E2RH");
++}
+diff -Naur linux-2.6.17.orig/arch/mips/galileo-boards/ev96100/setup.c linux-2.6.17/arch/mips/galileo-boards/ev96100/setup.c
+--- linux-2.6.17.orig/arch/mips/galileo-boards/ev96100/setup.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/galileo-boards/ev96100/setup.c	2006-06-19 18:16:13.000000000 -0700
+@@ -55,7 +55,7 @@
+ 
+ unsigned char mac_0_1[12];
+ 
+-void __init plat_setup(void)
++void __init plat_mem_setup(void)
+ {
+ 	unsigned int config = read_c0_config();
+ 	unsigned int status = read_c0_status();
+diff -Naur linux-2.6.17.orig/arch/mips/gt64120/ev64120/setup.c linux-2.6.17/arch/mips/gt64120/ev64120/setup.c
+--- linux-2.6.17.orig/arch/mips/gt64120/ev64120/setup.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/gt64120/ev64120/setup.c	2006-06-19 18:16:13.000000000 -0700
+@@ -71,7 +71,7 @@
+  */
+ extern void gt64120_time_init(void);
+ 
+-void __init plat_setup(void)
++void __init plat_mem_setup(void)
+ {
+ 	_machine_restart = galileo_machine_restart;
+ 	_machine_halt = galileo_machine_halt;
+diff -Naur linux-2.6.17.orig/arch/mips/gt64120/momenco_ocelot/setup.c linux-2.6.17/arch/mips/gt64120/momenco_ocelot/setup.c
+--- linux-2.6.17.orig/arch/mips/gt64120/momenco_ocelot/setup.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/gt64120/momenco_ocelot/setup.c	2006-06-19 18:16:13.000000000 -0700
+@@ -152,7 +152,7 @@
+ 	gt64120_base = 0xe0000000;
+ }
+ 
+-void __init plat_setup(void)
++void __init plat_mem_setup(void)
+ {
+ 	void (*l3func)(unsigned long)=KSEG1ADDR(&setup_l3cache);
+ 	unsigned int tmpword;
+diff -Naur linux-2.6.17.orig/arch/mips/gt64120/wrppmc/int-handler.S linux-2.6.17/arch/mips/gt64120/wrppmc/int-handler.S
+--- linux-2.6.17.orig/arch/mips/gt64120/wrppmc/int-handler.S	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/arch/mips/gt64120/wrppmc/int-handler.S	2006-06-19 18:16:13.000000000 -0700
+@@ -0,0 +1,59 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 1995, 1996, 1997, 2003 by Ralf Baechle
++ * Copyright (C) Wind River System Inc. Rongkai.Zhan <rongkai.zhan@windriver.com>
++ */
++#include <asm/asm.h>
++#include <asm/mipsregs.h>
++#include <asm/addrspace.h>
++#include <asm/regdef.h>
++#include <asm/stackframe.h>
++#include <asm/mach-wrppmc/mach-gt64120.h>
++
++	.align	5
++	.set	noat
++NESTED(handle_IRQ, PT_SIZE, sp)
++	SAVE_ALL
++	CLI				# Important: mark KERNEL mode !
++	.set	at
++
++	mfc0	t0, CP0_CAUSE		# get pending interrupts
++	mfc0	t1, CP0_STATUS		# get enabled interrupts
++	and	t0, t0, t1		# get allowed interrupts
++	andi	t0, t0, 0xFF00
++	beqz	t0, 1f
++	move	a1, sp			# Prepare 'struct pt_regs *regs' pointer
++
++	andi	t1, t0, CAUSEF_IP7	# CPU Compare/Count internal timer
++	bnez	t1, handle_cputimer_irq
++	andi	t1, t0, CAUSEF_IP6	# UART 16550 port
++	bnez	t1, handle_uart_irq
++	andi	t1, t0, CAUSEF_IP3	# PCI INT_A
++	bnez	t1, handle_pci_intA_irq
++
++	/* wrong alarm or masked ... */
++1:	j	spurious_interrupt
++	nop
++END(handle_IRQ)
++
++	.align	5
++handle_cputimer_irq:
++	li	a0, WRPPMC_MIPS_TIMER_IRQ
++	jal	do_IRQ
++	j	ret_from_irq
++
++	.align	5
++handle_uart_irq:
++	li	a0, WRPPMC_UART16550_IRQ
++	jal	do_IRQ
++	j	ret_from_irq
++
++	.align	5
++handle_pci_intA_irq:
++	li	a0, WRPPMC_PCI_INTA_IRQ
++	jal	do_IRQ
++	j	ret_from_irq
++
+diff -Naur linux-2.6.17.orig/arch/mips/gt64120/wrppmc/irq.c linux-2.6.17/arch/mips/gt64120/wrppmc/irq.c
+--- linux-2.6.17.orig/arch/mips/gt64120/wrppmc/irq.c	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/arch/mips/gt64120/wrppmc/irq.c	2006-06-19 18:16:13.000000000 -0700
+@@ -0,0 +1,63 @@
++/*
++ * irq.c: GT64120 Interrupt Controller
++ *
++ * Copyright (C) 2006, Wind River System Inc.
++ * Author: Rongkai.Zhan, <rongkai.zhan@windriver.com>
++ *
++ * This program is free software; you can redistribute  it and/or modify it
++ * under  the terms of  the GNU General  Public License as published by the
++ * Free Software Foundation;  either version 2 of the  License, or (at your
++ * option) any later version.
++ */
++#include <linux/errno.h>
++#include <linux/init.h>
++#include <linux/kernel_stat.h>
++#include <linux/module.h>
++#include <linux/signal.h>
++#include <linux/sched.h>
++#include <linux/types.h>
++#include <linux/interrupt.h>
++#include <linux/ioport.h>
++#include <linux/timex.h>
++#include <linux/slab.h>
++#include <linux/random.h>
++#include <linux/bitops.h>
++#include <asm/bootinfo.h>
++#include <asm/io.h>
++#include <asm/bitops.h>
++#include <asm/mipsregs.h>
++#include <asm/system.h>
++#include <asm/irq_cpu.h>
++#include <asm/gt64120.h>
++
++extern asmlinkage void handle_IRQ(void);
++
++/**
++ * Initialize GT64120 Interrupt Controller
++ */
++void gt64120_init_pic(void)
++{
++	/* clear CPU Interrupt Cause Registers */
++	GT_WRITE(GT_INTRCAUSE_OFS, (0x1F << 21));
++	GT_WRITE(GT_HINTRCAUSE_OFS, 0x00);
++
++	/* Disable all interrupts from GT64120 bridge chip */
++	GT_WRITE(GT_INTRMASK_OFS, 0x00);
++	GT_WRITE(GT_HINTRMASK_OFS, 0x00);
++	GT_WRITE(GT_PCI0_ICMASK_OFS, 0x00);
++	GT_WRITE(GT_PCI0_HICMASK_OFS, 0x00);
++}
++
++void __init arch_init_irq(void)
++{
++	/* enable all CPU interrupt bits. */
++	set_c0_status(ST0_IM);	/* IE bit is still 0 */
++
++	/* Install MIPS Interrupt Trap Vector */
++	set_except_vector(0, handle_IRQ);
++
++	/* IRQ 0 - 7 are for MIPS common irq_cpu controller */
++	mips_cpu_irq_init(0);
++
++	gt64120_init_pic();
++}
+diff -Naur linux-2.6.17.orig/arch/mips/gt64120/wrppmc/Makefile linux-2.6.17/arch/mips/gt64120/wrppmc/Makefile
+--- linux-2.6.17.orig/arch/mips/gt64120/wrppmc/Makefile	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/arch/mips/gt64120/wrppmc/Makefile	2006-06-19 18:16:13.000000000 -0700
+@@ -0,0 +1,14 @@
++#
++# This file is subject to the terms and conditions of the GNU General Public
++# License.  See the file "COPYING" in the main directory of this archive
++# for more details.
++#
++# Copyright 2006 Wind River System, Inc.
++# Author: Rongkai.Zhan <rongkai.zhan@windriver.com>
++#
++# Makefile for the Wind River MIPS 4KC PPMC Eval Board
++#
++
++obj-y	+= int-handler.o irq.o reset.o setup.o time.o pci.o
++
++EXTRA_AFLAGS := $(CFLAGS)
+diff -Naur linux-2.6.17.orig/arch/mips/gt64120/wrppmc/pci.c linux-2.6.17/arch/mips/gt64120/wrppmc/pci.c
+--- linux-2.6.17.orig/arch/mips/gt64120/wrppmc/pci.c	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/arch/mips/gt64120/wrppmc/pci.c	2006-06-19 18:16:13.000000000 -0700
+@@ -0,0 +1,53 @@
++/*
++ * pci.c: GT64120 PCI support.
++ *
++ * Copyright (C) 2006, Wind River System Inc. Rongkai.Zhan <rongkai.zhan@windriver.com>
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ */
++#include <linux/init.h>
++#include <linux/types.h>
++#include <linux/pci.h>
++#include <linux/kernel.h>
++#include <asm/gt64120.h>
++
++extern struct pci_ops gt64120_pci_ops;
++
++static struct resource pci0_io_resource = {
++	.name  = "pci_0 io",
++	.start = GT_PCI_IO_BASE,
++	.end   = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1,
++	.flags = IORESOURCE_IO,
++};
++
++static struct resource pci0_mem_resource = {
++	.name  = "pci_0 memory",
++	.start = GT_PCI_MEM_BASE,
++	.end   = GT_PCI_MEM_BASE + GT_PCI_MEM_SIZE - 1,
++	.flags = IORESOURCE_MEM,
++};
++
++static struct pci_controller hose_0 = {
++	.pci_ops	= &gt64120_pci_ops,
++	.io_resource	= &pci0_io_resource,
++	.mem_resource	= &pci0_mem_resource,
++};
++
++static int __init gt64120_pci_init(void)
++{
++	u32 tmp;
++
++	tmp = GT_READ(GT_PCI0_CMD_OFS);		/* Huh??? -- Ralf  */
++	tmp = GT_READ(GT_PCI0_BARE_OFS);
++
++	/* reset the whole PCI I/O space range */
++	ioport_resource.start = GT_PCI_IO_BASE;
++	ioport_resource.end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1;
++
++	register_pci_controller(&hose_0);
++	return 0;
++}
++
++arch_initcall(gt64120_pci_init);
+diff -Naur linux-2.6.17.orig/arch/mips/gt64120/wrppmc/reset.c linux-2.6.17/arch/mips/gt64120/wrppmc/reset.c
+--- linux-2.6.17.orig/arch/mips/gt64120/wrppmc/reset.c	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/arch/mips/gt64120/wrppmc/reset.c	2006-06-19 18:16:13.000000000 -0700
+@@ -0,0 +1,50 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 1997 Ralf Baechle
++ */
++#include <linux/sched.h>
++#include <linux/mm.h>
++#include <asm/io.h>
++#include <asm/pgtable.h>
++#include <asm/processor.h>
++#include <asm/reboot.h>
++#include <asm/system.h>
++#include <asm/cacheflush.h>
++
++void wrppmc_machine_restart(char *command)
++{
++	/*
++	 * Ouch, we're still alive ... This time we take the silver bullet ...
++	 * ... and find that we leave the hardware in a state in which the
++	 * kernel in the flush locks up somewhen during of after the PCI
++	 * detection stuff.
++	 */
++	local_irq_disable();
++	set_c0_status(ST0_BEV | ST0_ERL);
++	change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
++	flush_cache_all();
++	write_c0_wired(0);
++	__asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
++}
++
++void wrppmc_machine_halt(void)
++{
++	local_irq_disable();
++
++	printk(KERN_NOTICE "You can safely turn off the power\n");
++	while (1) {
++		__asm__(
++			".set\tmips3\n\t"
++			"wait\n\t"
++			".set\tmips0"
++		);
++	}
++}
++
++void wrppmc_machine_power_off(void)
++{
++	wrppmc_machine_halt();
++}
+diff -Naur linux-2.6.17.orig/arch/mips/gt64120/wrppmc/setup.c linux-2.6.17/arch/mips/gt64120/wrppmc/setup.c
+--- linux-2.6.17.orig/arch/mips/gt64120/wrppmc/setup.c	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/arch/mips/gt64120/wrppmc/setup.c	2006-06-19 18:16:13.000000000 -0700
+@@ -0,0 +1,173 @@
++/*
++ * setup.c: Setup pointers to hardware dependent routines.
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 1996, 1997, 2004 by Ralf Baechle (ralf@linux-mips.org)
++ * Copyright (C) 2006, Wind River System Inc. Rongkai.zhan <rongkai.zhan@windriver.com>
++ */
++#include <linux/config.h>
++#include <linux/init.h>
++#include <linux/string.h>
++#include <linux/kernel.h>
++#include <linux/tty.h>
++#include <linux/serial.h>
++#include <linux/serial_core.h>
++#include <linux/pm.h>
++
++#include <asm/io.h>
++#include <asm/bootinfo.h>
++#include <asm/reboot.h>
++#include <asm/time.h>
++#include <asm/gt64120.h>
++
++unsigned long gt64120_base = KSEG1ADDR(0x14000000);
++
++#ifdef WRPPMC_EARLY_DEBUG
++
++static volatile unsigned char * wrppmc_led = \
++	(volatile unsigned char *)KSEG1ADDR(WRPPMC_LED_BASE);
++
++/*
++ * PPMC LED control register:
++ * -) bit[0] controls DS1 LED (1 - OFF, 0 - ON)
++ * -) bit[1] controls DS2 LED (1 - OFF, 0 - ON)
++ * -) bit[2] controls DS4 LED (1 - OFF, 0 - ON)
++ */
++void wrppmc_led_on(int mask)
++{
++	unsigned char value = *wrppmc_led;
++
++	value &= (0xF8 | mask);
++	*wrppmc_led = value;
++}
++
++/* If mask = 0, turn off all LEDs */
++void wrppmc_led_off(int mask)
++{
++	unsigned char value = *wrppmc_led;
++
++	value |= (0x7 & mask);
++	*wrppmc_led = value;
++}
++
++/*
++ * We assume that bootloader has initialized UART16550 correctly
++ */
++void __init wrppmc_early_putc(char ch)
++{
++	static volatile unsigned char *wrppmc_uart = \
++		(volatile unsigned char *)KSEG1ADDR(WRPPMC_UART16550_BASE);
++	unsigned char value;
++
++	/* Wait until Transmit-Holding-Register is empty */
++	while (1) {
++		value = *(wrppmc_uart + 5);
++		if (value & 0x20)
++			break;
++	}
++
++	*wrppmc_uart = ch;
++}
++
++void __init wrppmc_early_printk(const char *fmt, ...)
++{
++	static char pbuf[256] = {'\0', };
++	char *ch = pbuf;
++	va_list args;
++	unsigned int i;
++
++	memset(pbuf, 0, 256);
++	va_start(args, fmt);
++	i = vsprintf(pbuf, fmt, args);
++	va_end(args);
++
++	/* Print the string */
++	while (*ch != '\0') {
++		wrppmc_early_putc(*ch);
++		/* if print '\n', also print '\r' */
++		if (*ch++ == '\n')
++			wrppmc_early_putc('\r');
++	}
++}
++#endif /* WRPPMC_EARLY_DEBUG */
++
++unsigned long __init prom_free_prom_memory(void)
++{
++	return 0;
++}
++
++#ifdef CONFIG_SERIAL_8250
++static void wrppmc_setup_serial(void)
++{
++	struct uart_port up;
++
++	memset(&up, 0x00, sizeof(struct uart_port));
++
++	/*
++	 * A note about mapbase/membase
++	 * -) mapbase is the physical address of the IO port.
++	 * -) membase is an 'ioremapped' cookie.
++	 */
++	up.line = 0;
++	up.type = PORT_16550;
++	up.iotype = UPIO_MEM;
++	up.mapbase = WRPPMC_UART16550_BASE;
++	up.membase = ioremap(up.mapbase, 8);
++	up.irq = WRPPMC_UART16550_IRQ;
++	up.uartclk = WRPPMC_UART16550_CLOCK;
++	up.flags = UPF_SKIP_TEST/* | UPF_BOOT_AUTOCONF */;
++	up.regshift = 0;
++
++	early_serial_setup(&up);
++}
++#endif
++
++void __init plat_setup(void)
++{
++	extern void wrppmc_time_init(void);
++	extern void wrppmc_timer_setup(struct irqaction *);
++	extern void wrppmc_machine_restart(char *command);
++	extern void wrppmc_machine_halt(void);
++	extern void wrppmc_machine_power_off(void);
++
++	_machine_restart = wrppmc_machine_restart;
++	_machine_halt	 = wrppmc_machine_halt;
++	pm_power_off	 = wrppmc_machine_power_off;
++
++	/* Use MIPS Count/Compare Timer */
++	board_time_init   = wrppmc_time_init;
++	board_timer_setup = wrppmc_timer_setup;
++
++	/* This makes the operations of 'in/out[bwl]' to the
++	 * physical address ( < KSEG0) can work via KSEG1
++	 */
++	set_io_port_base(KSEG1);
++
++#ifdef CONFIG_SERIAL_8250
++	wrppmc_setup_serial();
++#endif
++}
++
++const char *get_system_type(void)
++{
++	return "Wind River PPMC (GT64120)";
++}
++
++/*
++ * Initializes basic routines and structures pointers, memory size (as
++ * given by the bios and saves the command line.
++ */
++void __init prom_init(void)
++{
++	mips_machgroup = MACH_GROUP_GALILEO;
++	mips_machtype = MACH_EV64120A;
++
++	add_memory_region(WRPPMC_SDRAM_SCS0_BASE, WRPPMC_SDRAM_SCS0_SIZE, BOOT_MEM_RAM);
++	add_memory_region(WRPPMC_BOOTROM_BASE, WRPPMC_BOOTROM_SIZE, BOOT_MEM_ROM_DATA);
++
++	wrppmc_early_printk("prom_init: GT64120 SDRAM Bank 0: 0x%x - 0x%08lx\n",
++			WRPPMC_SDRAM_SCS0_BASE, (WRPPMC_SDRAM_SCS0_BASE + WRPPMC_SDRAM_SCS0_SIZE));
++}
+diff -Naur linux-2.6.17.orig/arch/mips/gt64120/wrppmc/time.c linux-2.6.17/arch/mips/gt64120/wrppmc/time.c
+--- linux-2.6.17.orig/arch/mips/gt64120/wrppmc/time.c	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/arch/mips/gt64120/wrppmc/time.c	2006-06-19 18:16:13.000000000 -0700
+@@ -0,0 +1,57 @@
++/*
++ * time.c: MIPS CPU Count/Compare timer hookup
++ *
++ * Author: Mark.Zhan, <rongkai.zhan@windriver.com>
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 1996, 1997, 2004 by Ralf Baechle (ralf@linux-mips.org)
++ * Copyright (C) 2006, Wind River System Inc.
++ */
++#include <linux/config.h>
++#include <linux/init.h>
++#include <linux/string.h>
++#include <linux/kernel.h>
++#include <linux/param.h>	/* for HZ */
++#include <linux/irq.h>
++#include <linux/timex.h>
++#include <linux/interrupt.h>
++
++#include <asm/reboot.h>
++#include <asm/time.h>
++#include <asm/io.h>
++#include <asm/bootinfo.h>
++#include <asm/gt64120.h>
++
++#define WRPPMC_CPU_CLK_FREQ 40000000 /* 40MHZ */
++
++void __init wrppmc_timer_setup(struct irqaction *irq)
++{
++	/* Install ISR for timer interrupt */
++	setup_irq(WRPPMC_MIPS_TIMER_IRQ, irq);
++
++	/* to generate the first timer interrupt */
++	write_c0_compare(mips_hpt_frequency/HZ);
++	write_c0_count(0);
++}
++
++/*
++ * Estimate CPU frequency.  Sets mips_hpt_frequency as a side-effect
++ *
++ * NOTE: We disable all GT64120 timers, and use MIPS processor internal
++ * timer as the source of kernel clock tick.
++ */
++void __init wrppmc_time_init(void)
++{
++	/* Disable GT64120 timers */
++	GT_WRITE(GT_TC_CONTROL_OFS, 0x00);
++	GT_WRITE(GT_TC0_OFS, 0x00);
++	GT_WRITE(GT_TC1_OFS, 0x00);
++	GT_WRITE(GT_TC2_OFS, 0x00);
++	GT_WRITE(GT_TC3_OFS, 0x00);
++
++	/* Use MIPS compare/count internal timer */
++	mips_hpt_frequency = WRPPMC_CPU_CLK_FREQ;
++}
+diff -Naur linux-2.6.17.orig/arch/mips/ite-boards/generic/it8172_setup.c linux-2.6.17/arch/mips/ite-boards/generic/it8172_setup.c
+--- linux-2.6.17.orig/arch/mips/ite-boards/generic/it8172_setup.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/ite-boards/generic/it8172_setup.c	2006-06-19 18:16:13.000000000 -0700
+@@ -72,11 +72,29 @@
+     struct resource flash;
+     struct resource boot;
+ } it8172_resources = {
+-    { "RAM",           0,          0,          IORESOURCE_MEM }, /* to be initted */
+-    { "PCI Mem",       0x10000000, 0x13FFFFFF, IORESOURCE_MEM },
+-    { "PCI I/O",       0x14000000, 0x17FFFFFF                 },
+-    { "Flash",         0x08000000, 0x0CFFFFFF                 },
+-    { "Boot ROM",      0x1FC00000, 0x1FFFFFFF                 }
++	{
++		.start	= 0,				/* to be initted */
++		.end	= 0,
++		.name	= "RAM",
++		.flags	= IORESOURCE_MEM
++	}, {
++		.start	= 0x10000000,
++		.end	= 0x13FFFFFF,
++		.name	= "PCI Mem",
++		.flags	= IORESOURCE_MEM
++	}, {
++		.start	= 0x14000000,
++		.end	= 0x17FFFFFF
++		.name	= "PCI I/O",
++	}, {
++		.start	= 0x08000000,
++		.end	= 0x0CFFFFFF
++		.name	= "Flash",
++	}, {
++		.start	= 0x1FC00000,
++		.end	= 0x1FFFFFFF
++		.name	= "Boot ROM",
++	}
+ };
+ #else
+ struct {
+@@ -89,14 +107,44 @@
+     struct resource flash;
+     struct resource boot;
+ } it8172_resources = {
+-    { "RAM",           0,          0,          IORESOURCE_MEM }, /* to be initted */
+-    { "PCI Mem0",      0x0C000000, 0x0FFFFFFF, IORESOURCE_MEM },
+-    { "PCI Mem1",      0x10000000, 0x13FFFFFF, IORESOURCE_MEM },
+-    { "PCI I/O",       0x14000000, 0x17FFFFFF                 },
+-    { "PCI Mem2",      0x1A000000, 0x1BFFFFFF, IORESOURCE_MEM },
+-    { "PCI Mem3",      0x1C000000, 0x1FBFFFFF, IORESOURCE_MEM },
+-    { "Flash",         0x08000000, 0x0CFFFFFF                 },
+-    { "Boot ROM",      0x1FC00000, 0x1FFFFFFF                 }
++	{
++		.start	= 0,				/* to be initted */
++		.end	= 0,
++		.name	= "RAM",
++		.flags	= IORESOURCE_MEM
++	}, {
++		.start	= 0x0C000000,
++		.end	= 0x0FFFFFFF,
++		.name	= "PCI Mem0",
++		.flags	= IORESOURCE_MEM
++	 }, {
++		.start	= 0x10000000,
++		.end	= 0x13FFFFFF,
++		.name	= "PCI Mem1",
++		.flags	= IORESOURCE_MEM
++	 }, {
++		.start	= 0x14000000,
++		.end	= 0x17FFFFFF
++		.name	= "PCI I/O",
++	}, {
++		.start	= 0x1A000000,
++		.end	= 0x1BFFFFFF,
++		.name	= "PCI Mem2",
++		.flags	= IORESOURCE_MEM
++	}, {
++		.start	= 0x1C000000,
++		.end	= 0x1FBFFFFF,
++		.name	= "PCI Mem3",
++		.flags	= IORESOURCE_MEM
++	}, {
++		.start	= 0x08000000,
++		.end	= 0x0CFFFFFF
++		.name	= "Flash",
++	}, {
++		.start	= 0x1FC00000,
++		.end	= 0x1FFFFFFF
++		.name	= "Boot ROM",
++	}
+ };
+ #endif
+ 
+@@ -106,7 +154,7 @@
+ 	it8172_resources.ram.end = memsize;
+ }
+ 
+-void __init plat_setup(void)
++void __init plat_mem_setup(void)
+ {
+ 	unsigned short dsr;
+ 	char *argptr;
+diff -Naur linux-2.6.17.orig/arch/mips/jazz/setup.c linux-2.6.17/arch/mips/jazz/setup.c
+--- linux-2.6.17.orig/arch/mips/jazz/setup.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/jazz/setup.c	2006-06-19 18:16:13.000000000 -0700
+@@ -52,7 +52,7 @@
+ 	{ "dma2", 0xc0, 0xdf, IORESOURCE_BUSY },
+ };
+ 
+-void __init plat_setup(void)
++void __init plat_mem_setup(void)
+ {
+ 	int i;
+ 
+diff -Naur linux-2.6.17.orig/arch/mips/jmr3927/rbhma3100/setup.c linux-2.6.17/arch/mips/jmr3927/rbhma3100/setup.c
+--- linux-2.6.17.orig/arch/mips/jmr3927/rbhma3100/setup.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/jmr3927/rbhma3100/setup.c	2006-06-19 18:16:13.000000000 -0700
+@@ -82,17 +82,54 @@
+     struct resource sio0;
+     struct resource sio1;
+ } jmr3927_resources = {
+-    { "RAM0",           0,         0x01FFFFFF,  IORESOURCE_MEM },
+-    { "RAM1",          0x02000000, 0x03FFFFFF,  IORESOURCE_MEM },
+-    { "PCIMEM",        0x08000000, 0x07FFFFFF,  IORESOURCE_MEM },
+-    { "IOB",           0x10000000, 0x13FFFFFF                  },
+-    { "IOC",           0x14000000, 0x14FFFFFF                  },
+-    { "PCIIO",         0x15000000, 0x15FFFFFF                  },
+-    { "JMY1394",       0x1D000000, 0x1D3FFFFF                  },
+-    { "ROM1",          0x1E000000, 0x1E3FFFFF                  },
+-    { "ROM0",          0x1FC00000, 0x1FFFFFFF                  },
+-    { "SIO0",          0xFFFEF300, 0xFFFEF3FF                  },
+-    { "SIO1",          0xFFFEF400, 0xFFFEF4FF                  },
++	{
++		.start	= 0,
++		.end	= 0x01FFFFFF,
++		.name	= "RAM0",
++		.flags = IORESOURCE_MEM
++	}, {
++		.start	= 0x02000000,
++		.end	= 0x03FFFFFF,
++		.name	= "RAM1",
++		.flags = IORESOURCE_MEM
++	}, {
++		.start	= 0x08000000,
++		.end	= 0x07FFFFFF,
++		.name	= "PCIMEM",
++		.flags = IORESOURCE_MEM
++	}, {
++		.start	= 0x10000000,
++		.end	= 0x13FFFFFF,
++		.name	= "IOB"
++	}, {
++		.start	= 0x14000000,
++		.end	= 0x14FFFFFF,
++		.name	= "IOC"
++	}, {
++		.start	= 0x15000000,
++		.end	= 0x15FFFFFF,
++		.name	= "PCIIO"
++	}, {
++		.start	= 0x1D000000,
++		.end	= 0x1D3FFFFF,
++		.name	= "JMY1394"
++	}, {
++		.start	= 0x1E000000,
++		.end	= 0x1E3FFFFF,
++		.name	= "ROM1"
++	}, {
++		.start	= 0x1FC00000,
++		.end	= 0x1FFFFFFF,
++		.name	= "ROM0"
++	}, {
++		.start	= 0xFFFEF300,
++		.end	= 0xFFFEF3FF,
++		.name	= "SIO0"
++	}, {
++		.start	= 0xFFFEF400,
++		.end	= 0xFFFEF4FF,
++		.name	= "SIO1"
++	},
+ };
+ 
+ /* don't enable - see errata */
+@@ -201,7 +238,7 @@
+ extern struct resource pci_io_resource;
+ extern struct resource pci_mem_resource;
+ 
+-void __init plat_setup(void)
++void __init plat_mem_setup(void)
+ {
+ 	char *argptr;
+ 
+diff -Naur linux-2.6.17.orig/arch/mips/Kconfig linux-2.6.17/arch/mips/Kconfig
+--- linux-2.6.17.orig/arch/mips/Kconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/Kconfig	2006-06-19 18:16:13.000000000 -0700
+@@ -119,6 +119,32 @@
+ 	select SYS_HAS_CPU_MIPS32_R1
+ 	select SYS_SUPPORTS_LITTLE_ENDIAN
+ 
++config BASLER_EXCITE
++	bool "Basler eXcite smart camera support"
++	select DMA_COHERENT
++	select HW_HAS_PCI
++	select IRQ_CPU
++	select IRQ_CPU_RM7K
++	select IRQ_CPU_RM9K
++	select SERIAL_RM9000
++	select SYS_HAS_CPU_RM9000
++	select SYS_SUPPORTS_32BIT_KERNEL
++	select SYS_SUPPORTS_64BIT_KERNEL
++	select SYS_SUPPORTS_BIG_ENDIAN
++	help
++	  The eXcite is a smart camera platform manufactured by
++	  Basler Vision Technologies AG
++
++config BASLER_EXCITE_PROTOTYPE
++	bool "Support for pre-release units"
++	depends on BASLER_EXCITE
++	default n
++	help
++	  Pre-series (prototype) units are different from later ones in
++	  some ways. Select this option if you have one of these. Please
++	  note that a kernel built with this option selected will not be
++	  able to run on normal units.
++
+ config MIPS_COBALT
+ 	bool "Cobalt Server"
+ 	select DMA_NONCOHERENT
+@@ -278,6 +304,7 @@
+ 	select SYS_SUPPORTS_64BIT_KERNEL
+ 	select SYS_SUPPORTS_BIG_ENDIAN
+ 	select SYS_SUPPORTS_LITTLE_ENDIAN
++	select SYS_SUPPORTS_MULTITHREADING if EXPERIMENTAL
+ 	help
+ 	  This enables support for the MIPS Technologies Atlas evaluation
+ 	  board.
+@@ -306,6 +333,7 @@
+ 	select SYS_SUPPORTS_64BIT_KERNEL
+ 	select SYS_SUPPORTS_BIG_ENDIAN
+ 	select SYS_SUPPORTS_LITTLE_ENDIAN
++	select SYS_SUPPORTS_MULTITHREADING
+ 	help
+ 	  This enables support for the MIPS Technologies Malta evaluation
+ 	  board.
+@@ -327,6 +355,27 @@
+ 	  This enables support for the MIPS Technologies SEAD evaluation
+ 	  board.
+ 
++config WR_PPMC
++	bool "Support for Wind River PPMC board"
++	select IRQ_CPU
++	select BOOT_ELF32
++	select DMA_NONCOHERENT
++	select HW_HAS_PCI
++	select MIPS_GT64120
++	select SWAP_IO_SPACE
++	select SYS_HAS_CPU_MIPS32_R1
++	select SYS_HAS_CPU_MIPS32_R2
++	select SYS_HAS_CPU_MIPS64_R1
++	select SYS_HAS_CPU_NEVADA
++	select SYS_HAS_CPU_RM7000
++	select SYS_SUPPORTS_32BIT_KERNEL
++	select SYS_SUPPORTS_64BIT_KERNEL
++	select SYS_SUPPORTS_BIG_ENDIAN
++	select SYS_SUPPORTS_LITTLE_ENDIAN
++	help
++	  This enables support for the Wind River MIPS32 4KC PPMC evaluation
++	  board, which is based on GT64120 bridge chip.
++
+ config MIPS_SIM
+ 	bool 'MIPS simulator (MIPSsim)'
+ 	select DMA_NONCOHERENT
+@@ -438,53 +487,16 @@
+ 
+ config PNX8550_V2PCI
+ 	bool "Philips PNX8550 based Viper2-PCI board"
++	depends on BROKEN
+ 	select PNX8550
+ 	select SYS_SUPPORTS_LITTLE_ENDIAN
+ 
+ config PNX8550_JBS
+ 	bool "Philips PNX8550 based JBS board"
++	depends on BROKEN
+ 	select PNX8550
+ 	select SYS_SUPPORTS_LITTLE_ENDIAN
+ 
+-config DDB5074
+-	bool "NEC DDB Vrc-5074 (EXPERIMENTAL)"
+-	depends on EXPERIMENTAL
+-	select DDB5XXX_COMMON
+-	select DMA_NONCOHERENT
+-	select HAVE_STD_PC_SERIAL_PORT
+-	select HW_HAS_PCI
+-	select IRQ_CPU
+-	select I8259
+-	select ISA
+-	select SYS_HAS_CPU_R5000
+-	select SYS_SUPPORTS_32BIT_KERNEL
+-	select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
+-	select SYS_SUPPORTS_LITTLE_ENDIAN
+-	help
+-	  This enables support for the VR5000-based NEC DDB Vrc-5074
+-	  evaluation board.
+-
+-config DDB5476
+-	bool "NEC DDB Vrc-5476"
+-	select DDB5XXX_COMMON
+-	select DMA_NONCOHERENT
+-	select HAVE_STD_PC_SERIAL_PORT
+-	select HW_HAS_PCI
+-	select IRQ_CPU
+-	select I8259
+-	select ISA
+-	select SYS_HAS_CPU_R5432
+-	select SYS_SUPPORTS_32BIT_KERNEL
+-	select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
+-	select SYS_SUPPORTS_LITTLE_ENDIAN
+-	help
+-	  This enables support for the R5432-based NEC DDB Vrc-5476
+-	  evaluation board.
+-
+-	  Features : kernel debugging, serial terminal, NFS root fs, on-board
+-	  ether port USB, AC97, PCI, PCI VGA card & framebuffer console,
+-	  IDE controller, PS2 keyboard, PS2 mouse, etc.
+-
+ config DDB5477
+ 	bool "NEC DDB Vrc-5477"
+ 	select DDB5XXX_COMMON
+@@ -506,8 +518,6 @@
+ config MACH_VR41XX
+ 	bool "NEC VR41XX-based machines"
+ 	select SYS_HAS_CPU_VR41XX
+-	select SYS_SUPPORTS_32BIT_KERNEL
+-	select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
+ 
+ config PMC_YOSEMITE
+ 	bool "PMC-Sierra Yosemite eval board"
+@@ -522,6 +532,7 @@
+ 	select SYS_SUPPORTS_64BIT_KERNEL
+ 	select SYS_SUPPORTS_BIG_ENDIAN
+ 	select SYS_SUPPORTS_HIGHMEM
++	select SYS_SUPPORTS_SMP
+ 	help
+ 	  Yosemite is an evaluation board for the RM9000x2 processor
+ 	  manufactured by PMC-Sierra.
+@@ -546,6 +557,20 @@
+ 	  simulate actual MIPS hardware platforms.  More information on Qemu
+ 	  can be found at http://www.linux-mips.org/wiki/Qemu.
+ 
++config MARKEINS
++	bool "Support for NEC EMMA2RH Mark-eins"
++	select DMA_NONCOHERENT
++	select HW_HAS_PCI
++	select IRQ_CPU
++	select SWAP_IO_SPACE
++	select SYS_SUPPORTS_32BIT_KERNEL
++	select SYS_SUPPORTS_BIG_ENDIAN
++	select SYS_SUPPORTS_LITTLE_ENDIAN
++	select SYS_HAS_CPU_R5000
++	help
++	  This enables support for the R5432-based NEC Mark-eins
++	  boards with R5500 CPU.
++
+ config SGI_IP22
+ 	bool "SGI IP22 (Indy/Indigo2)"
+ 	select ARC
+@@ -555,6 +580,7 @@
+ 	select HW_HAS_EISA
+ 	select IP22_CPU_SCACHE
+ 	select IRQ_CPU
++	select NO_ISA if ISA
+ 	select SWAP_IO_SPACE
+ 	select SYS_HAS_CPU_R4X00
+ 	select SYS_HAS_CPU_R5000
+@@ -577,6 +603,8 @@
+ 	select SYS_HAS_CPU_R10000
+ 	select SYS_SUPPORTS_64BIT_KERNEL
+ 	select SYS_SUPPORTS_BIG_ENDIAN
++	select SYS_SUPPORTS_NUMA
++	select SYS_SUPPORTS_SMP
+ 	help
+ 	  This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
+ 	  workstations.  To compile a Linux kernel that runs on these, say Y
+@@ -707,8 +735,8 @@
+ 
+ config SNI_RM200_PCI
+ 	bool "SNI RM200 PCI"
+-	select ARC
+-	select ARC32
++	select ARC if CPU_LITTLE_ENDIAN
++	select ARC32 if CPU_LITTLE_ENDIAN
+ 	select ARCH_MAY_HAVE_PC_FDC
+ 	select BOOT_ELF32
+ 	select DMA_NONCOHERENT
+@@ -719,10 +747,13 @@
+ 	select I8253
+ 	select I8259
+ 	select ISA
++	select SWAP_IO_SPACE if CPU_BIG_ENDIAN
+ 	select SYS_HAS_CPU_R4X00
++	select SYS_HAS_CPU_R5000
++	select R5000_CPU_SCACHE
+ 	select SYS_SUPPORTS_32BIT_KERNEL
+ 	select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
+-	select SYS_SUPPORTS_BIG_ENDIAN if EXPERIMENTAL
++	select SYS_SUPPORTS_BIG_ENDIAN
+ 	select SYS_SUPPORTS_HIGHMEM
+ 	select SYS_SUPPORTS_LITTLE_ENDIAN
+ 	help
+@@ -979,6 +1010,11 @@
+ config SWAP_IO_SPACE
+ 	bool
+ 
++config EMMA2RH
++	bool
++	depends on MARKEINS
++	default y
++
+ #
+ # Unfortunately not all GT64120 systems run the chip at the same clock.
+ # As the user for the clock rate and try to minimize the available options.
+@@ -1035,6 +1071,9 @@
+ config HAVE_STD_PC_SERIAL_PORT
+ 	bool
+ 
++config VR4181
++	bool
++
+ config ARC_CONSOLE
+ 	bool "ARC console support"
+ 	depends on SGI_IP22 || SNI_RM200_PCI
+@@ -1155,7 +1194,7 @@
+ 	select CPU_SUPPORTS_32BIT_KERNEL
+ 	select CPU_SUPPORTS_64BIT_KERNEL
+ 	help
+-	  The options selects support for the NEC VR4100 series of processors.
++	  The options selects support for the NEC VR41xx series of processors.
+ 	  Only choose this option if you have one of these processors as a
+ 	  kernel built with this option will not run on any other type of
+ 	  processor or vice versa.
+@@ -1455,32 +1494,57 @@
+ config CPU_HAS_PREFETCH
+ 	bool
+ 
+-config MIPS_MT
+-	bool "Enable MIPS MT"
+-
+ choice
+ 	prompt "MIPS MT options"
+-	depends on MIPS_MT
++
++config MIPS_MT_DISABLED
++	bool "Disable multithreading support."
++	help
++	  Use this option if your workload can't take advantage of
++	  MIPS hardware multithreading support.  On systems that don't have
++	  the option of an MT-enabled processor this option will be the only
++	  option in this menu.
+ 
+ config MIPS_MT_SMTC
+ 	bool "SMTC: Use all TCs on all VPEs for SMP"
++	depends on CPU_MIPS32_R2
++	#depends on CPU_MIPS64_R2		# once there is hardware ...
++	depends on SYS_SUPPORTS_MULTITHREADING
+ 	select CPU_MIPSR2_IRQ_VI
+ 	select CPU_MIPSR2_SRS
++	select MIPS_MT
+ 	select SMP
++	help
++	  This is a kernel model which is known a SMTC or lately has been
++	  marketesed into SMVP.
+ 
+ config MIPS_MT_SMP
+ 	bool "Use 1 TC on each available VPE for SMP"
++	depends on SYS_SUPPORTS_MULTITHREADING
++	select CPU_MIPSR2_IRQ_VI
++	select CPU_MIPSR2_SRS
++	select MIPS_MT
+ 	select SMP
++	help
++	  This is a kernel model which is also known a VSMP or lately
++	  has been marketesed into SMVP.
+ 
+ config MIPS_VPE_LOADER
+ 	bool "VPE loader support."
+-	depends on MIPS_MT
++	depends on SYS_SUPPORTS_MULTITHREADING
++	select MIPS_MT
+ 	help
+ 	  Includes a loader for loading an elf relocatable object
+ 	  onto another VPE and running it.
+ 
+ endchoice
+ 
++config MIPS_MT
++	bool
++
++config SYS_SUPPORTS_MULTITHREADING
++	bool
++
+ config MIPS_MT_FPAFF
+ 	bool "Dynamic FPU affinity for FP-intensive threads"
+ 	depends on MIPS_MT
+@@ -1537,32 +1601,23 @@
+ config CPU_HAS_WB
+ 	bool
+ 
++#
++# Vectored interrupt mode is an R2 feature
++#
+ config CPU_MIPSR2_IRQ_VI
+-	bool "Vectored interrupt mode"
+-	depends on CPU_MIPSR2
+-	help
+-	   Vectored interrupt mode allowing faster dispatching of interrupts.
+-	   The board support code needs to be written to take advantage of this
+-	   mode.  Compatibility code is included to allow the kernel to run on
+-	   a CPU that does not support vectored interrupts.  It's safe to
+-	   say Y here.
++	bool
+ 
++#
++# Extended interrupt mode is an R2 feature
++#
+ config CPU_MIPSR2_IRQ_EI
+-	bool "External interrupt controller mode"
+-	depends on CPU_MIPSR2
+-	help
+-	   Extended interrupt mode takes advantage of an external interrupt
+-	   controller to allow fast dispatching from many possible interrupt
+-	   sources. Say N unless you know that external interrupt support is
+-	   required.
++	bool
+ 
++#
++# Shadow registers are an R2 feature
++#
+ config CPU_MIPSR2_SRS
+-	bool "Make shadow set registers available for interrupt handlers"
+-	depends on CPU_MIPSR2_IRQ_VI || CPU_MIPSR2_IRQ_EI
+-	help
+-	   Allow the kernel to use shadow register sets for fast interrupts.
+-	   Interrupt handlers must be specially written to use shadow sets.
+-	   Say N unless you know that shadow register set upport is needed.
++	bool
+ 
+ config CPU_HAS_SYNC
+ 	bool
+@@ -1607,6 +1662,28 @@
+ 	def_bool y
+ 	depends on !NUMA
+ 
++config ARCH_DISCONTIGMEM_ENABLE
++	bool
++	default y if SGI_IP27
++	help
++	  Say Y to upport efficient handling of discontiguous physical memory,
++	  for architectures which are either NUMA (Non-Uniform Memory Access)
++	  or have huge holes in the physical address space for other reasons.
++	  See <file:Documentation/vm/numa> for more.
++
++config NUMA
++	bool "NUMA Support"
++	depends on SYS_SUPPORTS_NUMA
++	help
++	  Say Y to compile the kernel to support NUMA (Non-Uniform Memory
++	  Access).  This option improves performance on systems with more
++	  than two nodes; on two node systems it is generally better to
++	  leave it disabled; on single node systems disable this option
++	  disabled.
++
++config SYS_SUPPORTS_NUMA
++	bool
++
+ config NODES_SHIFT
+ 	int
+ 	default "6"
+@@ -1616,8 +1693,8 @@
+ 
+ config SMP
+ 	bool "Multi-Processing support"
+-	depends on CPU_RM9000 || ((SIBYTE_BCM1x80 || SIBYTE_BCM1x55 || SIBYTE_SB1250 || QEMU) && !SIBYTE_STANDALONE) || SGI_IP27 || MIPS_MT_SMP || MIPS_MT_SMTC
+-	---help---
++	depends on SYS_SUPPORTS_SMP
++	help
+ 	  This enables support for systems with more than one CPU. If you have
+ 	  a system with only one CPU, like most personal computers, say N. If
+ 	  you have a system with more than one CPU, say Y.
+@@ -1636,6 +1713,9 @@
+ 
+ 	  If you don't know what to do here, say N.
+ 
++config SYS_SUPPORTS_SMP
++	bool
++
+ config NR_CPUS
+ 	int "Maximum number of CPUs (2-64)"
+ 	range 2 64
+@@ -1710,6 +1790,9 @@
+ config ISA
+ 	bool
+ 
++config NO_ISA
++	bool
++
+ config EISA
+ 	bool "EISA support"
+ 	depends on HW_HAS_EISA
+@@ -1840,6 +1923,32 @@
+ 	bool "Power Management support (EXPERIMENTAL)"
+ 	depends on EXPERIMENTAL && SOC_AU1X00
+ 
++config APM
++        tristate "Advanced Power Management Emulation"
++	depends on PM
++        ---help---
++	  APM is a BIOS specification for saving power using several different
++	  techniques. This is mostly useful for battery powered systems with
++	  APM compliant BIOSes. If you say Y here, the system time will be
++	  reset after a RESUME operation, the /proc/apm device will provide
++	  battery status information, and user-space programs will receive
++	  notification of APM "events" (e.g. battery status change).
++
++	  In order to use APM, you will need supporting software. For location
++	  and more information, read <file:Documentation/pm.txt> and the
++	  Battery Powered Linux mini-HOWTO, available from
++	  <http://www.tldp.org/docs.html#howto>.
++
++	  This driver does not spin down disk drives (see the hdparm(8)
++	  manpage ("man 8 hdparm") for that), and it doesn't turn off
++	  VESA-compliant "green" monitors.
++
++	  Generally, if you don't have a battery in your machine, there isn't
++	  much point in using this driver and you should say N. If you get
++	  random kernel OOPSes or reboots that don't seem to be related to
++	  anything, try disabling/enabling this option (or disabling/enabling
++	  APM in your BIOS).
++
+ endmenu
+ 
+ source "net/Kconfig"
+diff -Naur linux-2.6.17.orig/arch/mips/kernel/apm.c linux-2.6.17/arch/mips/kernel/apm.c
+--- linux-2.6.17.orig/arch/mips/kernel/apm.c	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/arch/mips/kernel/apm.c	2006-06-19 18:16:13.000000000 -0700
+@@ -0,0 +1,605 @@
++/*
++ * bios-less APM driver for MIPS Linux
++ *  Jamey Hicks <jamey@crl.dec.com>
++ *  adapted from the APM BIOS driver for Linux by Stephen Rothwell (sfr@linuxcare.com)
++ *
++ * APM 1.2 Reference:
++ *   Intel Corporation, Microsoft Corporation. Advanced Power Management
++ *   (APM) BIOS Interface Specification, Revision 1.2, February 1996.
++ *
++ * [This document is available from Microsoft at:
++ *    http://www.microsoft.com/hwdev/busbios/amp_12.htm]
++ */
++#include <linux/config.h>
++#include <linux/module.h>
++#include <linux/poll.h>
++#include <linux/timer.h>
++#include <linux/slab.h>
++#include <linux/proc_fs.h>
++#include <linux/miscdevice.h>
++#include <linux/apm_bios.h>
++#include <linux/capability.h>
++#include <linux/sched.h>
++#include <linux/pm.h>
++#include <linux/device.h>
++#include <linux/kernel.h>
++#include <linux/list.h>
++#include <linux/init.h>
++#include <linux/completion.h>
++
++#include <asm/apm.h> /* apm_power_info */
++#include <asm/system.h>
++
++/*
++ * The apm_bios device is one of the misc char devices.
++ * This is its minor number.
++ */
++#define APM_MINOR_DEV	134
++
++/*
++ * See Documentation/Config.help for the configuration options.
++ *
++ * Various options can be changed at boot time as follows:
++ * (We allow underscores for compatibility with the modules code)
++ *	apm=on/off			enable/disable APM
++ */
++
++/*
++ * Maximum number of events stored
++ */
++#define APM_MAX_EVENTS		16
++
++struct apm_queue {
++	unsigned int		event_head;
++	unsigned int		event_tail;
++	apm_event_t		events[APM_MAX_EVENTS];
++};
++
++/*
++ * The per-file APM data
++ */
++struct apm_user {
++	struct list_head	list;
++
++	unsigned int		suser: 1;
++	unsigned int		writer: 1;
++	unsigned int		reader: 1;
++
++	int			suspend_result;
++	unsigned int		suspend_state;
++#define SUSPEND_NONE	0		/* no suspend pending */
++#define SUSPEND_PENDING	1		/* suspend pending read */
++#define SUSPEND_READ	2		/* suspend read, pending ack */
++#define SUSPEND_ACKED	3		/* suspend acked */
++#define SUSPEND_DONE	4		/* suspend completed */
++
++	struct apm_queue	queue;
++};
++
++/*
++ * Local variables
++ */
++static int suspends_pending;
++static int apm_disabled;
++static int mips_apm_active;
++
++static DECLARE_WAIT_QUEUE_HEAD(apm_waitqueue);
++static DECLARE_WAIT_QUEUE_HEAD(apm_suspend_waitqueue);
++
++/*
++ * This is a list of everyone who has opened /dev/apm_bios
++ */
++static DECLARE_RWSEM(user_list_lock);
++static LIST_HEAD(apm_user_list);
++
++/*
++ * kapmd info.  kapmd provides us a process context to handle
++ * "APM" events within - specifically necessary if we're going
++ * to be suspending the system.
++ */
++static DECLARE_WAIT_QUEUE_HEAD(kapmd_wait);
++static DECLARE_COMPLETION(kapmd_exit);
++static DEFINE_SPINLOCK(kapmd_queue_lock);
++static struct apm_queue kapmd_queue;
++
++
++static const char driver_version[] = "1.13";	/* no spaces */
++
++
++
++/*
++ * Compatibility cruft until the IPAQ people move over to the new
++ * interface.
++ */
++static void __apm_get_power_status(struct apm_power_info *info)
++{
++}
++
++/*
++ * This allows machines to provide their own "apm get power status" function.
++ */
++void (*apm_get_power_status)(struct apm_power_info *) = __apm_get_power_status;
++EXPORT_SYMBOL(apm_get_power_status);
++
++
++/*
++ * APM event queue management.
++ */
++static inline int queue_empty(struct apm_queue *q)
++{
++	return q->event_head == q->event_tail;
++}
++
++static inline apm_event_t queue_get_event(struct apm_queue *q)
++{
++	q->event_tail = (q->event_tail + 1) % APM_MAX_EVENTS;
++	return q->events[q->event_tail];
++}
++
++static void queue_add_event(struct apm_queue *q, apm_event_t event)
++{
++	q->event_head = (q->event_head + 1) % APM_MAX_EVENTS;
++	if (q->event_head == q->event_tail) {
++		static int notified;
++
++		if (notified++ == 0)
++		    printk(KERN_ERR "apm: an event queue overflowed\n");
++		q->event_tail = (q->event_tail + 1) % APM_MAX_EVENTS;
++	}
++	q->events[q->event_head] = event;
++}
++
++static void queue_event_one_user(struct apm_user *as, apm_event_t event)
++{
++	if (as->suser && as->writer) {
++		switch (event) {
++		case APM_SYS_SUSPEND:
++		case APM_USER_SUSPEND:
++			/*
++			 * If this user already has a suspend pending,
++			 * don't queue another one.
++			 */
++			if (as->suspend_state != SUSPEND_NONE)
++				return;
++
++			as->suspend_state = SUSPEND_PENDING;
++			suspends_pending++;
++			break;
++		}
++	}
++	queue_add_event(&as->queue, event);
++}
++
++static void queue_event(apm_event_t event, struct apm_user *sender)
++{
++	struct apm_user *as;
++
++	down_read(&user_list_lock);
++	list_for_each_entry(as, &apm_user_list, list) {
++		if (as != sender && as->reader)
++			queue_event_one_user(as, event);
++	}
++	up_read(&user_list_lock);
++	wake_up_interruptible(&apm_waitqueue);
++}
++
++static void apm_suspend(void)
++{
++	struct apm_user *as;
++	int err = pm_suspend(PM_SUSPEND_MEM);
++
++	/*
++	 * Anyone on the APM queues will think we're still suspended.
++	 * Send a message so everyone knows we're now awake again.
++	 */
++	queue_event(APM_NORMAL_RESUME, NULL);
++
++	/*
++	 * Finally, wake up anyone who is sleeping on the suspend.
++	 */
++	down_read(&user_list_lock);
++	list_for_each_entry(as, &apm_user_list, list) {
++		as->suspend_result = err;
++		as->suspend_state = SUSPEND_DONE;
++	}
++	up_read(&user_list_lock);
++
++	wake_up(&apm_suspend_waitqueue);
++}
++
++static ssize_t apm_read(struct file *fp, char __user *buf, size_t count, loff_t *ppos)
++{
++	struct apm_user *as = fp->private_data;
++	apm_event_t event;
++	int i = count, ret = 0;
++
++	if (count < sizeof(apm_event_t))
++		return -EINVAL;
++
++	if (queue_empty(&as->queue) && fp->f_flags & O_NONBLOCK)
++		return -EAGAIN;
++
++	wait_event_interruptible(apm_waitqueue, !queue_empty(&as->queue));
++
++	while ((i >= sizeof(event)) && !queue_empty(&as->queue)) {
++		event = queue_get_event(&as->queue);
++
++		ret = -EFAULT;
++		if (copy_to_user(buf, &event, sizeof(event)))
++			break;
++
++		if (event == APM_SYS_SUSPEND || event == APM_USER_SUSPEND)
++			as->suspend_state = SUSPEND_READ;
++
++		buf += sizeof(event);
++		i -= sizeof(event);
++	}
++
++	if (i < count)
++		ret = count - i;
++
++	return ret;
++}
++
++static unsigned int apm_poll(struct file *fp, poll_table * wait)
++{
++	struct apm_user *as = fp->private_data;
++
++	poll_wait(fp, &apm_waitqueue, wait);
++	return queue_empty(&as->queue) ? 0 : POLLIN | POLLRDNORM;
++}
++
++/*
++ * apm_ioctl - handle APM ioctl
++ *
++ * APM_IOC_SUSPEND
++ *   This IOCTL is overloaded, and performs two functions.  It is used to:
++ *     - initiate a suspend
++ *     - acknowledge a suspend read from /dev/apm_bios.
++ *   Only when everyone who has opened /dev/apm_bios with write permission
++ *   has acknowledge does the actual suspend happen.
++ */
++static int
++apm_ioctl(struct inode * inode, struct file *filp, u_int cmd, u_long arg)
++{
++	struct apm_user *as = filp->private_data;
++	unsigned long flags;
++	int err = -EINVAL;
++
++	if (!as->suser || !as->writer)
++		return -EPERM;
++
++	switch (cmd) {
++	case APM_IOC_SUSPEND:
++		as->suspend_result = -EINTR;
++
++		if (as->suspend_state == SUSPEND_READ) {
++			/*
++			 * If we read a suspend command from /dev/apm_bios,
++			 * then the corresponding APM_IOC_SUSPEND ioctl is
++			 * interpreted as an acknowledge.
++			 */
++			as->suspend_state = SUSPEND_ACKED;
++			suspends_pending--;
++		} else {
++			/*
++			 * Otherwise it is a request to suspend the system.
++			 * Queue an event for all readers, and expect an
++			 * acknowledge from all writers who haven't already
++			 * acknowledged.
++			 */
++			queue_event(APM_USER_SUSPEND, as);
++		}
++
++		/*
++		 * If there are no further acknowledges required, suspend
++		 * the system.
++		 */
++		if (suspends_pending == 0)
++			apm_suspend();
++
++		/*
++		 * Wait for the suspend/resume to complete.  If there are
++		 * pending acknowledges, we wait here for them.
++		 *
++		 * Note that we need to ensure that the PM subsystem does
++		 * not kick us out of the wait when it suspends the threads.
++		 */
++		flags = current->flags;
++		current->flags |= PF_NOFREEZE;
++
++		/*
++		 * Note: do not allow a thread which is acking the suspend
++		 * to escape until the resume is complete.
++		 */
++		if (as->suspend_state == SUSPEND_ACKED)
++			wait_event(apm_suspend_waitqueue,
++					 as->suspend_state == SUSPEND_DONE);
++		else
++			wait_event_interruptible(apm_suspend_waitqueue,
++					 as->suspend_state == SUSPEND_DONE);
++
++		current->flags = flags;
++		err = as->suspend_result;
++		as->suspend_state = SUSPEND_NONE;
++		break;
++	}
++
++	return err;
++}
++
++static int apm_release(struct inode * inode, struct file * filp)
++{
++	struct apm_user *as = filp->private_data;
++	filp->private_data = NULL;
++
++	down_write(&user_list_lock);
++	list_del(&as->list);
++	up_write(&user_list_lock);
++
++	/*
++	 * We are now unhooked from the chain.  As far as new
++	 * events are concerned, we no longer exist.  However, we
++	 * need to balance suspends_pending, which means the
++	 * possibility of sleeping.
++	 */
++	if (as->suspend_state != SUSPEND_NONE) {
++		suspends_pending -= 1;
++		if (suspends_pending == 0)
++			apm_suspend();
++	}
++
++	kfree(as);
++	return 0;
++}
++
++static int apm_open(struct inode * inode, struct file * filp)
++{
++	struct apm_user *as;
++
++	as = (struct apm_user *)kzalloc(sizeof(*as), GFP_KERNEL);
++	if (as) {
++		/*
++		 * XXX - this is a tiny bit broken, when we consider BSD
++		 * process accounting. If the device is opened by root, we
++		 * instantly flag that we used superuser privs. Who knows,
++		 * we might close the device immediately without doing a
++		 * privileged operation -- cevans
++		 */
++		as->suser = capable(CAP_SYS_ADMIN);
++		as->writer = (filp->f_mode & FMODE_WRITE) == FMODE_WRITE;
++		as->reader = (filp->f_mode & FMODE_READ) == FMODE_READ;
++
++		down_write(&user_list_lock);
++		list_add(&as->list, &apm_user_list);
++		up_write(&user_list_lock);
++
++		filp->private_data = as;
++	}
++
++	return as ? 0 : -ENOMEM;
++}
++
++static struct file_operations apm_bios_fops = {
++	.owner		= THIS_MODULE,
++	.read		= apm_read,
++	.poll		= apm_poll,
++	.ioctl		= apm_ioctl,
++	.open		= apm_open,
++	.release	= apm_release,
++};
++
++static struct miscdevice apm_device = {
++	.minor		= APM_MINOR_DEV,
++	.name		= "apm_bios",
++	.fops		= &apm_bios_fops
++};
++
++
++#ifdef CONFIG_PROC_FS
++/*
++ * Arguments, with symbols from linux/apm_bios.h.
++ *
++ *   0) Linux driver version (this will change if format changes)
++ *   1) APM BIOS Version.  Usually 1.0, 1.1 or 1.2.
++ *   2) APM flags from APM Installation Check (0x00):
++ *	bit 0: APM_16_BIT_SUPPORT
++ *	bit 1: APM_32_BIT_SUPPORT
++ *	bit 2: APM_IDLE_SLOWS_CLOCK
++ *	bit 3: APM_BIOS_DISABLED
++ *	bit 4: APM_BIOS_DISENGAGED
++ *   3) AC line status
++ *	0x00: Off-line
++ *	0x01: On-line
++ *	0x02: On backup power (BIOS >= 1.1 only)
++ *	0xff: Unknown
++ *   4) Battery status
++ *	0x00: High
++ *	0x01: Low
++ *	0x02: Critical
++ *	0x03: Charging
++ *	0x04: Selected battery not present (BIOS >= 1.2 only)
++ *	0xff: Unknown
++ *   5) Battery flag
++ *	bit 0: High
++ *	bit 1: Low
++ *	bit 2: Critical
++ *	bit 3: Charging
++ *	bit 7: No system battery
++ *	0xff: Unknown
++ *   6) Remaining battery life (percentage of charge):
++ *	0-100: valid
++ *	-1: Unknown
++ *   7) Remaining battery life (time units):
++ *	Number of remaining minutes or seconds
++ *	-1: Unknown
++ *   8) min = minutes; sec = seconds
++ */
++static int apm_get_info(char *buf, char **start, off_t fpos, int length)
++{
++	struct apm_power_info info;
++	char *units;
++	int ret;
++
++	info.ac_line_status = 0xff;
++	info.battery_status = 0xff;
++	info.battery_flag   = 0xff;
++	info.battery_life   = -1;
++	info.time	    = -1;
++	info.units	    = -1;
++
++	if (apm_get_power_status)
++		apm_get_power_status(&info);
++
++	switch (info.units) {
++	default:	units = "?";	break;
++	case 0: 	units = "min";	break;
++	case 1: 	units = "sec";	break;
++	}
++
++	ret = sprintf(buf, "%s 1.2 0x%02x 0x%02x 0x%02x 0x%02x %d%% %d %s\n",
++		     driver_version, APM_32_BIT_SUPPORT,
++		     info.ac_line_status, info.battery_status,
++		     info.battery_flag, info.battery_life,
++		     info.time, units);
++
++ 	return ret;
++}
++#endif
++
++static int kapmd(void *arg)
++{
++	daemonize("kapmd");
++	current->flags |= PF_NOFREEZE;
++
++	do {
++		apm_event_t event;
++
++		wait_event_interruptible(kapmd_wait,
++				!queue_empty(&kapmd_queue) || !mips_apm_active);
++
++		if (!mips_apm_active)
++			break;
++
++		spin_lock_irq(&kapmd_queue_lock);
++		event = 0;
++		if (!queue_empty(&kapmd_queue))
++			event = queue_get_event(&kapmd_queue);
++		spin_unlock_irq(&kapmd_queue_lock);
++
++		switch (event) {
++		case 0:
++			break;
++
++		case APM_LOW_BATTERY:
++		case APM_POWER_STATUS_CHANGE:
++			queue_event(event, NULL);
++			break;
++
++		case APM_USER_SUSPEND:
++		case APM_SYS_SUSPEND:
++			queue_event(event, NULL);
++			if (suspends_pending == 0)
++				apm_suspend();
++			break;
++
++		case APM_CRITICAL_SUSPEND:
++			apm_suspend();
++			break;
++		}
++	} while (1);
++
++	complete_and_exit(&kapmd_exit, 0);
++}
++
++static int __init apm_init(void)
++{
++	int ret;
++
++	if (apm_disabled) {
++		printk(KERN_NOTICE "apm: disabled on user request.\n");
++		return -ENODEV;
++	}
++
++	mips_apm_active = 1;
++
++	ret = kernel_thread(kapmd, NULL, CLONE_KERNEL);
++	if (ret < 0) {
++		mips_apm_active = 0;
++		return ret;
++	}
++
++#ifdef CONFIG_PROC_FS
++	create_proc_info_entry("apm", 0, NULL, apm_get_info);
++#endif
++
++	ret = misc_register(&apm_device);
++	if (ret != 0) {
++		remove_proc_entry("apm", NULL);
++
++		mips_apm_active = 0;
++		wake_up(&kapmd_wait);
++		wait_for_completion(&kapmd_exit);
++	}
++
++	return ret;
++}
++
++static void __exit apm_exit(void)
++{
++	misc_deregister(&apm_device);
++	remove_proc_entry("apm", NULL);
++
++	mips_apm_active = 0;
++	wake_up(&kapmd_wait);
++	wait_for_completion(&kapmd_exit);
++}
++
++module_init(apm_init);
++module_exit(apm_exit);
++
++MODULE_AUTHOR("Stephen Rothwell");
++MODULE_DESCRIPTION("Advanced Power Management");
++MODULE_LICENSE("GPL");
++
++#ifndef MODULE
++static int __init apm_setup(char *str)
++{
++	while ((str != NULL) && (*str != '\0')) {
++		if (strncmp(str, "off", 3) == 0)
++			apm_disabled = 1;
++		if (strncmp(str, "on", 2) == 0)
++			apm_disabled = 0;
++		str = strchr(str, ',');
++		if (str != NULL)
++			str += strspn(str, ", \t");
++	}
++	return 1;
++}
++
++__setup("apm=", apm_setup);
++#endif
++
++/**
++ * apm_queue_event - queue an APM event for kapmd
++ * @event: APM event
++ *
++ * Queue an APM event for kapmd to process and ultimately take the
++ * appropriate action.  Only a subset of events are handled:
++ *   %APM_LOW_BATTERY
++ *   %APM_POWER_STATUS_CHANGE
++ *   %APM_USER_SUSPEND
++ *   %APM_SYS_SUSPEND
++ *   %APM_CRITICAL_SUSPEND
++ */
++void apm_queue_event(apm_event_t event)
++{
++	unsigned long flags;
++
++	spin_lock_irqsave(&kapmd_queue_lock, flags);
++	queue_add_event(&kapmd_queue, event);
++	spin_unlock_irqrestore(&kapmd_queue_lock, flags);
++
++	wake_up_interruptible(&kapmd_wait);
++}
++EXPORT_SYMBOL(apm_queue_event);
+diff -Naur linux-2.6.17.orig/arch/mips/kernel/asm-offsets.c linux-2.6.17/arch/mips/kernel/asm-offsets.c
+--- linux-2.6.17.orig/arch/mips/kernel/asm-offsets.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/kernel/asm-offsets.c	2006-06-19 18:16:13.000000000 -0700
+@@ -141,72 +141,72 @@
+ void output_thread_fpu_defines(void)
+ {
+ 	offset("#define THREAD_FPR0    ",
+-	       struct task_struct, thread.fpu.hard.fpr[0]);
++	       struct task_struct, thread.fpu.fpr[0]);
+ 	offset("#define THREAD_FPR1    ",
+-	       struct task_struct, thread.fpu.hard.fpr[1]);
++	       struct task_struct, thread.fpu.fpr[1]);
+ 	offset("#define THREAD_FPR2    ",
+-	       struct task_struct, thread.fpu.hard.fpr[2]);
++	       struct task_struct, thread.fpu.fpr[2]);
+ 	offset("#define THREAD_FPR3    ",
+-	       struct task_struct, thread.fpu.hard.fpr[3]);
++	       struct task_struct, thread.fpu.fpr[3]);
+ 	offset("#define THREAD_FPR4    ",
+-	       struct task_struct, thread.fpu.hard.fpr[4]);
++	       struct task_struct, thread.fpu.fpr[4]);
+ 	offset("#define THREAD_FPR5    ",
+-	       struct task_struct, thread.fpu.hard.fpr[5]);
++	       struct task_struct, thread.fpu.fpr[5]);
+ 	offset("#define THREAD_FPR6    ",
+-	       struct task_struct, thread.fpu.hard.fpr[6]);
++	       struct task_struct, thread.fpu.fpr[6]);
+ 	offset("#define THREAD_FPR7    ",
+-	       struct task_struct, thread.fpu.hard.fpr[7]);
++	       struct task_struct, thread.fpu.fpr[7]);
+ 	offset("#define THREAD_FPR8    ",
+-	       struct task_struct, thread.fpu.hard.fpr[8]);
++	       struct task_struct, thread.fpu.fpr[8]);
+ 	offset("#define THREAD_FPR9    ",
+-	       struct task_struct, thread.fpu.hard.fpr[9]);
++	       struct task_struct, thread.fpu.fpr[9]);
+ 	offset("#define THREAD_FPR10   ",
+-	       struct task_struct, thread.fpu.hard.fpr[10]);
++	       struct task_struct, thread.fpu.fpr[10]);
+ 	offset("#define THREAD_FPR11   ",
+-	       struct task_struct, thread.fpu.hard.fpr[11]);
++	       struct task_struct, thread.fpu.fpr[11]);
+ 	offset("#define THREAD_FPR12   ",
+-	       struct task_struct, thread.fpu.hard.fpr[12]);
++	       struct task_struct, thread.fpu.fpr[12]);
+ 	offset("#define THREAD_FPR13   ",
+-	       struct task_struct, thread.fpu.hard.fpr[13]);
++	       struct task_struct, thread.fpu.fpr[13]);
+ 	offset("#define THREAD_FPR14   ",
+-	       struct task_struct, thread.fpu.hard.fpr[14]);
++	       struct task_struct, thread.fpu.fpr[14]);
+ 	offset("#define THREAD_FPR15   ",
+-	       struct task_struct, thread.fpu.hard.fpr[15]);
++	       struct task_struct, thread.fpu.fpr[15]);
+ 	offset("#define THREAD_FPR16   ",
+-	       struct task_struct, thread.fpu.hard.fpr[16]);
++	       struct task_struct, thread.fpu.fpr[16]);
+ 	offset("#define THREAD_FPR17   ",
+-	       struct task_struct, thread.fpu.hard.fpr[17]);
++	       struct task_struct, thread.fpu.fpr[17]);
+ 	offset("#define THREAD_FPR18   ",
+-	       struct task_struct, thread.fpu.hard.fpr[18]);
++	       struct task_struct, thread.fpu.fpr[18]);
+ 	offset("#define THREAD_FPR19   ",
+-	       struct task_struct, thread.fpu.hard.fpr[19]);
++	       struct task_struct, thread.fpu.fpr[19]);
+ 	offset("#define THREAD_FPR20   ",
+-	       struct task_struct, thread.fpu.hard.fpr[20]);
++	       struct task_struct, thread.fpu.fpr[20]);
+ 	offset("#define THREAD_FPR21   ",
+-	       struct task_struct, thread.fpu.hard.fpr[21]);
++	       struct task_struct, thread.fpu.fpr[21]);
+ 	offset("#define THREAD_FPR22   ",
+-	       struct task_struct, thread.fpu.hard.fpr[22]);
++	       struct task_struct, thread.fpu.fpr[22]);
+ 	offset("#define THREAD_FPR23   ",
+-	       struct task_struct, thread.fpu.hard.fpr[23]);
++	       struct task_struct, thread.fpu.fpr[23]);
+ 	offset("#define THREAD_FPR24   ",
+-	       struct task_struct, thread.fpu.hard.fpr[24]);
++	       struct task_struct, thread.fpu.fpr[24]);
+ 	offset("#define THREAD_FPR25   ",
+-	       struct task_struct, thread.fpu.hard.fpr[25]);
++	       struct task_struct, thread.fpu.fpr[25]);
+ 	offset("#define THREAD_FPR26   ",
+-	       struct task_struct, thread.fpu.hard.fpr[26]);
++	       struct task_struct, thread.fpu.fpr[26]);
+ 	offset("#define THREAD_FPR27   ",
+-	       struct task_struct, thread.fpu.hard.fpr[27]);
++	       struct task_struct, thread.fpu.fpr[27]);
+ 	offset("#define THREAD_FPR28   ",
+-	       struct task_struct, thread.fpu.hard.fpr[28]);
++	       struct task_struct, thread.fpu.fpr[28]);
+ 	offset("#define THREAD_FPR29   ",
+-	       struct task_struct, thread.fpu.hard.fpr[29]);
++	       struct task_struct, thread.fpu.fpr[29]);
+ 	offset("#define THREAD_FPR30   ",
+-	       struct task_struct, thread.fpu.hard.fpr[30]);
++	       struct task_struct, thread.fpu.fpr[30]);
+ 	offset("#define THREAD_FPR31   ",
+-	       struct task_struct, thread.fpu.hard.fpr[31]);
++	       struct task_struct, thread.fpu.fpr[31]);
+ 
+ 	offset("#define THREAD_FCR31   ",
+-	       struct task_struct, thread.fpu.hard.fcr31);
++	       struct task_struct, thread.fpu.fcr31);
+ 	linefeed;
+ }
+ 
+diff -Naur linux-2.6.17.orig/arch/mips/kernel/branch.c linux-2.6.17/arch/mips/kernel/branch.c
+--- linux-2.6.17.orig/arch/mips/kernel/branch.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/kernel/branch.c	2006-06-19 18:16:13.000000000 -0700
+@@ -178,7 +178,7 @@
+ 		if (is_fpu_owner())
+ 			asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
+ 		else
+-			fcr31 = current->thread.fpu.hard.fcr31;
++			fcr31 = current->thread.fpu.fcr31;
+ 		preempt_enable();
+ 
+ 		bit = (insn.i_format.rt >> 2);
+diff -Naur linux-2.6.17.orig/arch/mips/kernel/cpu-probe.c linux-2.6.17/arch/mips/kernel/cpu-probe.c
+--- linux-2.6.17.orig/arch/mips/kernel/cpu-probe.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/kernel/cpu-probe.c	2006-06-19 18:16:13.000000000 -0700
+@@ -111,7 +111,6 @@
+ 	case CPU_R5000:
+ 	case CPU_NEVADA:
+ 	case CPU_RM7000:
+-	case CPU_RM9000:
+ 	case CPU_TX49XX:
+ 	case CPU_4KC:
+ 	case CPU_4KEC:
+@@ -137,6 +136,14 @@
+ 		} else
+ 			printk(" unavailable.\n");
+ 		break;
++	case CPU_RM9000:
++		if ((c->processor_id & 0x00ff) >= 0x40) {
++			cpu_wait = r4k_wait;
++			printk(" available.\n");
++		} else {
++			printk(" unavailable.\n");
++		}
++		break;
+ 	default:
+ 		printk(" unavailable.\n");
+ 		break;
+@@ -243,9 +250,15 @@
+ 		break;
+ 	case PRID_IMP_VR41XX:
+ 		switch (c->processor_id & 0xf0) {
++#ifndef CONFIG_VR4181
+ 		case PRID_REV_VR4111:
+ 			c->cputype = CPU_VR4111;
+ 			break;
++#else
++		case PRID_REV_VR4181:
++			c->cputype = CPU_VR4181;
++			break;
++#endif
+ 		case PRID_REV_VR4121:
+ 			c->cputype = CPU_VR4121;
+ 			break;
+diff -Naur linux-2.6.17.orig/arch/mips/kernel/entry.S linux-2.6.17/arch/mips/kernel/entry.S
+--- linux-2.6.17.orig/arch/mips/kernel/entry.S	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/kernel/entry.S	2006-06-19 18:16:13.000000000 -0700
+@@ -87,7 +87,7 @@
+ 	ori	v1, v0, TCSTATUS_IXMT
+ 	mtc0	v1, CP0_TCSTATUS
+ 	andi	v0, TCSTATUS_IXMT
+-	ehb
++	_ehb
+ 	mfc0	t0, CP0_TCCONTEXT
+ 	DMT	9				# dmt t1
+ 	jal	mips_ihb
+@@ -95,7 +95,7 @@
+ 	andi	t3, t0, 0xff00
+ 	or	t2, t2, t3
+ 	mtc0	t2, CP0_STATUS
+-	ehb
++	_ehb
+ 	andi	t1, t1, VPECONTROL_TE
+ 	beqz	t1, 1f
+ 	EMT
+@@ -105,7 +105,7 @@
+ 	xori	v1, v1, TCSTATUS_IXMT
+ 	or	v1, v0, v1
+ 	mtc0	v1, CP0_TCSTATUS
+-	ehb
++	_ehb
+ 	xor	t0, t0, t3
+ 	mtc0	t0, CP0_TCCONTEXT
+ #endif /* CONFIG_MIPS_MT_SMTC */
+diff -Naur linux-2.6.17.orig/arch/mips/kernel/gdb-low.S linux-2.6.17/arch/mips/kernel/gdb-low.S
+--- linux-2.6.17.orig/arch/mips/kernel/gdb-low.S	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/kernel/gdb-low.S	2006-06-19 18:16:13.000000000 -0700
+@@ -291,7 +291,7 @@
+ 		ori	t1, t2, TCSTATUS_IXMT
+ 		mtc0	t1, CP0_TCSTATUS
+ 		andi	t2, t2, TCSTATUS_IXMT
+-		ehb
++		_ehb
+ 		DMT	9				# dmt	t1
+ 		jal	mips_ihb
+ 		nop
+@@ -310,7 +310,7 @@
+ 		xori	t1, t1, TCSTATUS_IXMT
+ 		or	t1, t1, t2
+ 		mtc0	t1, CP0_TCSTATUS
+-		ehb
++		_ehb
+ #endif /* CONFIG_MIPS_MT_SMTC */
+ 		LONG_L	v0, GDB_FR_STATUS(sp)
+ 		LONG_L	v1, GDB_FR_EPC(sp)
+diff -Naur linux-2.6.17.orig/arch/mips/kernel/genex.S linux-2.6.17/arch/mips/kernel/genex.S
+--- linux-2.6.17.orig/arch/mips/kernel/genex.S	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/kernel/genex.S	2006-06-19 18:16:13.000000000 -0700
+@@ -214,7 +214,7 @@
+ 	mtc0	t0, CP0_TCCONTEXT
+ 	xor	t1, t1, t0
+ 	mtc0	t1, CP0_STATUS
+-	ehb
++	_ehb
+ #endif /* CONFIG_MIPS_MT_SMTC */
+ 	CLI
+ 	move	a0, sp
+diff -Naur linux-2.6.17.orig/arch/mips/kernel/head.S linux-2.6.17/arch/mips/kernel/head.S
+--- linux-2.6.17.orig/arch/mips/kernel/head.S	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/kernel/head.S	2006-06-19 18:16:13.000000000 -0700
+@@ -96,7 +96,7 @@
+ 	/* Clear TKSU, leave IXMT */
+ 	xori	t0, 0x00001800
+ 	mtc0	t0, CP0_TCSTATUS
+-	ehb
++	_ehb
+ 	/* We need to leave the global IE bit set, but clear EXL...*/
+ 	mfc0	t0, CP0_STATUS
+ 	or	t0, ST0_CU0 | ST0_EXL | ST0_ERL | \set | \clr
+diff -Naur linux-2.6.17.orig/arch/mips/kernel/i8259.c linux-2.6.17/arch/mips/kernel/i8259.c
+--- linux-2.6.17.orig/arch/mips/kernel/i8259.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/kernel/i8259.c	2006-06-19 18:16:13.000000000 -0700
+@@ -302,11 +302,11 @@
+ };
+ 
+ static struct resource pic1_io_resource = {
+-	"pic1", 0x20, 0x3f, IORESOURCE_BUSY
++	.name = "pic1", .start = 0x20, .end = 0x3f, .flags = IORESOURCE_BUSY
+ };
+ 
+ static struct resource pic2_io_resource = {
+-	"pic2", 0xa0, 0xbf, IORESOURCE_BUSY
++	.name = "pic2", .start = 0xa0, .end = 0xbf, .flags = IORESOURCE_BUSY
+ };
+ 
+ /*
+diff -Naur linux-2.6.17.orig/arch/mips/kernel/irixsig.c linux-2.6.17/arch/mips/kernel/irixsig.c
+--- linux-2.6.17.orig/arch/mips/kernel/irixsig.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/kernel/irixsig.c	2006-06-19 18:16:13.000000000 -0700
+@@ -260,7 +260,7 @@
+ 
+ 		for(i = 0; i < 32; i++)
+ 			error |= __get_user(fregs[i], &context->fpregs[i]);
+-		error |= __get_user(current->thread.fpu.hard.fcr31, &context->fpcsr);
++		error |= __get_user(current->thread.fpu.fcr31, &context->fpcsr);
+ 	}
+ 
+ 	/* XXX do sigstack crapola here... XXX */
+diff -Naur linux-2.6.17.orig/arch/mips/kernel/Makefile linux-2.6.17/arch/mips/kernel/Makefile
+--- linux-2.6.17.orig/arch/mips/kernel/Makefile	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/kernel/Makefile	2006-06-19 18:16:13.000000000 -0700
+@@ -13,6 +13,8 @@
+ 
+ obj-$(CONFIG_MODULES)		+= mips_ksyms.o module.o
+ 
++obj-$(CONFIG_APM)		+= apm.o
++
+ obj-$(CONFIG_CPU_R3000)		+= r2300_fpu.o r2300_switch.o
+ obj-$(CONFIG_CPU_TX39XX)	+= r2300_fpu.o r2300_switch.o
+ obj-$(CONFIG_CPU_TX49XX)	+= r4k_fpu.o r4k_switch.o
+diff -Naur linux-2.6.17.orig/arch/mips/kernel/ptrace32.c linux-2.6.17/arch/mips/kernel/ptrace32.c
+--- linux-2.6.17.orig/arch/mips/kernel/ptrace32.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/kernel/ptrace32.c	2006-06-19 18:16:13.000000000 -0700
+@@ -166,10 +166,7 @@
+ 			tmp = regs->lo;
+ 			break;
+ 		case FPC_CSR:
+-			if (cpu_has_fpu)
+-				tmp = child->thread.fpu.hard.fcr31;
+-			else
+-				tmp = child->thread.fpu.soft.fcr31;
++			tmp = child->thread.fpu.fcr31;
+ 			break;
+ 		case FPC_EIR: {	/* implementation / version register */
+ 			unsigned int flags;
+@@ -288,9 +285,9 @@
+ 
+ 			if (!tsk_used_math(child)) {
+ 				/* FP not yet used  */
+-				memset(&child->thread.fpu.hard, ~0,
+-				       sizeof(child->thread.fpu.hard));
+-				child->thread.fpu.hard.fcr31 = 0;
++				memset(&child->thread.fpu, ~0,
++				       sizeof(child->thread.fpu));
++				child->thread.fpu.fcr31 = 0;
+ 			}
+ 			/*
+ 			 * The odd registers are actually the high order bits
+@@ -318,10 +315,7 @@
+ 			regs->lo = data;
+ 			break;
+ 		case FPC_CSR:
+-			if (cpu_has_fpu)
+-				child->thread.fpu.hard.fcr31 = data;
+-			else
+-				child->thread.fpu.soft.fcr31 = data;
++			child->thread.fpu.fcr31 = data;
+ 			break;
+ 		case DSP_BASE ... DSP_BASE + 5: {
+ 			dspreg_t *dregs;
+diff -Naur linux-2.6.17.orig/arch/mips/kernel/ptrace.c linux-2.6.17/arch/mips/kernel/ptrace.c
+--- linux-2.6.17.orig/arch/mips/kernel/ptrace.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/kernel/ptrace.c	2006-06-19 18:16:13.000000000 -0700
+@@ -21,12 +21,12 @@
+ #include <linux/mm.h>
+ #include <linux/errno.h>
+ #include <linux/ptrace.h>
+-#include <linux/audit.h>
+ #include <linux/smp.h>
+ #include <linux/smp_lock.h>
+ #include <linux/user.h>
+ #include <linux/security.h>
+-#include <linux/signal.h>
++#include <linux/audit.h>
++#include <linux/seccomp.h>
+ 
+ #include <asm/byteorder.h>
+ #include <asm/cpu.h>
+@@ -120,11 +120,11 @@
+ 			__put_user ((__u64) -1, i + (__u64 __user *) data);
+ 	}
+ 
++	__put_user (child->thread.fpu.fcr31, data + 64);
++
+ 	if (cpu_has_fpu) {
+ 		unsigned int flags, tmp;
+ 
+-		__put_user (child->thread.fpu.hard.fcr31, data + 64);
+-
+ 		preempt_disable();
+ 		if (cpu_has_mipsmt) {
+ 			unsigned int vpflags = dvpe();
+@@ -142,7 +142,6 @@
+ 		preempt_enable();
+ 		__put_user (tmp, data + 65);
+ 	} else {
+-		__put_user (child->thread.fpu.soft.fcr31, data + 64);
+ 		__put_user ((__u32) 0, data + 65);
+ 	}
+ 
+@@ -162,10 +161,7 @@
+ 	for (i = 0; i < 32; i++)
+ 		__get_user (fregs[i], i + (__u64 __user *) data);
+ 
+-	if (cpu_has_fpu)
+-		__get_user (child->thread.fpu.hard.fcr31, data + 64);
+-	else
+-		__get_user (child->thread.fpu.soft.fcr31, data + 64);
++	__get_user (child->thread.fpu.fcr31, data + 64);
+ 
+ 	/* FIR may not be written.  */
+ 
+@@ -241,10 +237,7 @@
+ 			tmp = regs->lo;
+ 			break;
+ 		case FPC_CSR:
+-			if (cpu_has_fpu)
+-				tmp = child->thread.fpu.hard.fcr31;
+-			else
+-				tmp = child->thread.fpu.soft.fcr31;
++			tmp = child->thread.fpu.fcr31;
+ 			break;
+ 		case FPC_EIR: {	/* implementation / version register */
+ 			unsigned int flags;
+@@ -336,9 +329,9 @@
+ 
+ 			if (!tsk_used_math(child)) {
+ 				/* FP not yet used  */
+-				memset(&child->thread.fpu.hard, ~0,
+-				       sizeof(child->thread.fpu.hard));
+-				child->thread.fpu.hard.fcr31 = 0;
++				memset(&child->thread.fpu, ~0,
++				       sizeof(child->thread.fpu));
++				child->thread.fpu.fcr31 = 0;
+ 			}
+ #ifdef CONFIG_32BIT
+ 			/*
+@@ -369,10 +362,7 @@
+ 			regs->lo = data;
+ 			break;
+ 		case FPC_CSR:
+-			if (cpu_has_fpu)
+-				child->thread.fpu.hard.fcr31 = data;
+-			else
+-				child->thread.fpu.soft.fcr31 = data;
++			child->thread.fpu.fcr31 = data;
+ 			break;
+ 		case DSP_BASE ... DSP_BASE + 5: {
+ 			dspreg_t *dregs;
+@@ -482,12 +472,16 @@
+  */
+ asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit)
+ {
++	/* do the secure computing check first */
++	secure_computing(regs->orig_eax);
++
+ 	if (unlikely(current->audit_context) && entryexit)
+ 		audit_syscall_exit(AUDITSC_RESULT(regs->regs[2]),
+ 		                   regs->regs[2]);
+ 
+ 	if (!(current->ptrace & PT_PTRACED))
+ 		goto out;
++
+ 	if (!test_thread_flag(TIF_SYSCALL_TRACE))
+ 		goto out;
+ 
+@@ -505,9 +499,14 @@
+ 		send_sig(current->exit_code, current, 1);
+ 		current->exit_code = 0;
+ 	}
+- out:
++
++out:
++	/* There is no ->orig_eax and that's quite intensional for now making
++	   this work will require some work in various other place before it's
++	   more than a placebo.  */
++
+ 	if (unlikely(current->audit_context) && !entryexit)
+-		audit_syscall_entry(audit_arch(), regs->regs[2],
+-				    regs->regs[4], regs->regs[5],
+-				    regs->regs[6], regs->regs[7]);
++		audit_syscall_entry(audit_arch(), regs->orig_eax,
++		                    regs->regs[4], regs->regs[5],
++		                    regs->regs[6], regs->regs[7]);
+ }
+diff -Naur linux-2.6.17.orig/arch/mips/kernel/r4k_switch.S linux-2.6.17/arch/mips/kernel/r4k_switch.S
+--- linux-2.6.17.orig/arch/mips/kernel/r4k_switch.S	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/kernel/r4k_switch.S	2006-06-19 18:16:13.000000000 -0700
+@@ -75,8 +75,8 @@
+ 	and	t0, t0, t1
+ 	LONG_S	t0, ST_OFF(t3)
+ 
+-	fpu_save_double a0 t1 t0 t2		# c0_status passed in t1
+-						# clobbers t0 and t2
++	fpu_save_double a0 t0 t1		# c0_status passed in t0
++						# clobbers t1
+ 1:
+ 
+ 	/*
+@@ -94,7 +94,7 @@
+ 	ori	t1, t2, TCSTATUS_IXMT
+ 	mtc0	t1, CP0_TCSTATUS
+ 	andi	t2, t2, TCSTATUS_IXMT
+-	ehb
++	_ehb
+ 	DMT	8				# dmt	t0
+ 	move	t1,ra
+ 	jal	mips_ihb
+@@ -109,7 +109,7 @@
+ 	or	a2, t1
+ 	mtc0	a2, CP0_STATUS
+ #ifdef CONFIG_MIPS_MT_SMTC
+-	ehb
++	_ehb
+ 	andi	t0, t0, VPECONTROL_TE
+ 	beqz	t0, 1f
+ 	emt
+@@ -118,7 +118,7 @@
+ 	xori	t1, t1, TCSTATUS_IXMT
+ 	or	t1, t1, t2
+ 	mtc0	t1, CP0_TCSTATUS
+-	ehb
++	_ehb
+ #endif /* CONFIG_MIPS_MT_SMTC */
+ 	move	v0, a0
+ 	jr	ra
+@@ -129,9 +129,9 @@
+  */
+ LEAF(_save_fp)
+ #ifdef CONFIG_64BIT
+-	mfc0	t1, CP0_STATUS
++	mfc0	t0, CP0_STATUS
+ #endif
+-	fpu_save_double a0 t1 t0 t2		# clobbers t1
++	fpu_save_double a0 t0 t1		# clobbers t1
+ 	jr	ra
+ 	END(_save_fp)
+ 
+@@ -139,7 +139,10 @@
+  * Restore a thread's fp context.
+  */
+ LEAF(_restore_fp)
+-	fpu_restore_double a0, t1		# clobbers t1
++#ifdef CONFIG_64BIT
++	mfc0	t0, CP0_STATUS
++#endif
++	fpu_restore_double a0 t0 t1		# clobbers t1
+ 	jr	ra
+ 	END(_restore_fp)
+ 
+diff -Naur linux-2.6.17.orig/arch/mips/kernel/scall32-o32.S linux-2.6.17/arch/mips/kernel/scall32-o32.S
+--- linux-2.6.17.orig/arch/mips/kernel/scall32-o32.S	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/kernel/scall32-o32.S	2006-06-19 18:16:13.000000000 -0700
+@@ -497,7 +497,7 @@
+ 	sys	sys_sched_get_priority_min 1
+ 	sys	sys_sched_rr_get_interval 2	/* 4165 */
+ 	sys	sys_nanosleep,		2
+-	sys	sys_mremap,		4
++	sys	sys_mremap,		5
+ 	sys	sys_accept		3
+ 	sys	sys_bind		3
+ 	sys	sys_connect		3	/* 4170 */
+@@ -647,6 +647,7 @@
+ 	sys	sys_unshare		1
+ 	sys	sys_splice		4
+ 	sys	sys_sync_file_range	7	/* 4305 */
++	sys	sys_tee			4
+ 	.endm
+ 
+ 	/* We pre-compute the number of _instruction_ bytes needed to
+diff -Naur linux-2.6.17.orig/arch/mips/kernel/scall64-64.S linux-2.6.17/arch/mips/kernel/scall64-64.S
+--- linux-2.6.17.orig/arch/mips/kernel/scall64-64.S	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/kernel/scall64-64.S	2006-06-19 18:16:13.000000000 -0700
+@@ -462,3 +462,4 @@
+ 	PTR	sys_unshare
+ 	PTR	sys_splice
+ 	PTR	sys_sync_file_range
++	PTR	sys_tee				/* 5265 */
+diff -Naur linux-2.6.17.orig/arch/mips/kernel/scall64-n32.S linux-2.6.17/arch/mips/kernel/scall64-n32.S
+--- linux-2.6.17.orig/arch/mips/kernel/scall64-n32.S	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/kernel/scall64-n32.S	2006-06-19 18:16:13.000000000 -0700
+@@ -388,3 +388,4 @@
+ 	PTR	sys_unshare
+ 	PTR	sys_splice
+ 	PTR	sys_sync_file_range
++	PTR	sys_tee
+diff -Naur linux-2.6.17.orig/arch/mips/kernel/scall64-o32.S linux-2.6.17/arch/mips/kernel/scall64-o32.S
+--- linux-2.6.17.orig/arch/mips/kernel/scall64-o32.S	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/kernel/scall64-o32.S	2006-06-19 18:16:13.000000000 -0700
+@@ -510,4 +510,5 @@
+ 	PTR	sys_unshare
+ 	PTR	sys_splice
+ 	PTR	sys32_sync_file_range		/* 4305 */
++	PTR	sys_tee
+ 	.size	sys_call_table,.-sys_call_table
+diff -Naur linux-2.6.17.orig/arch/mips/kernel/setup.c linux-2.6.17/arch/mips/kernel/setup.c
+--- linux-2.6.17.orig/arch/mips/kernel/setup.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/kernel/setup.c	2006-06-19 18:16:13.000000000 -0700
+@@ -442,6 +442,48 @@
+ #endif /* CONFIG_BLK_DEV_INITRD  */
+ }
+ 
++/*
++ * arch_mem_init - initialize memory managment subsystem
++ *
++ *  o plat_mem_setup() detects the memory configuration and will record detected
++ *    memory areas using add_memory_region.
++ *  o parse_cmdline_early() parses the command line for mem= options which,
++ *    iff detected, will override the results of the automatic detection.
++ *
++ * At this stage the memory configuration of the system is known to the
++ * kernel but generic memory managment system is still entirely uninitialized.
++ *
++ *  o bootmem_init()
++ *  o sparse_init()
++ *  o paging_init()
++ *
++ * At this stage the bootmem allocator is ready to use.
++ *
++ * NOTE: historically plat_mem_setup did the entire platform initialization.
++ *       This was rather impractical because it meant plat_mem_setup had to
++ * get away without any kind of memory allocator.  To keep old code from
++ * breaking plat_setup was just renamed to plat_setup and a second platform
++ * initialization hook for anything else was introduced.
++ */
++
++extern void plat_mem_setup(void);
++
++static void __init arch_mem_init(char **cmdline_p)
++{
++	/* call board setup routine */
++	plat_mem_setup();
++
++	strlcpy(command_line, arcs_cmdline, sizeof(command_line));
++	strlcpy(saved_command_line, command_line, COMMAND_LINE_SIZE);
++
++	*cmdline_p = command_line;
++
++	parse_cmdline_early();
++	bootmem_init();
++	sparse_init();
++	paging_init();
++}
++
+ static inline void resource_init(void)
+ {
+ 	int i;
+@@ -495,8 +537,6 @@
+ #undef MAXMEM
+ #undef MAXMEM_PFN
+ 
+-extern void plat_setup(void);
+-
+ void __init setup_arch(char **cmdline_p)
+ {
+ 	cpu_probe();
+@@ -511,18 +551,8 @@
+ #endif
+ #endif
+ 
+-	/* call board setup routine */
+-	plat_setup();
+-
+-	strlcpy(command_line, arcs_cmdline, sizeof(command_line));
+-	strlcpy(saved_command_line, command_line, COMMAND_LINE_SIZE);
++	arch_mem_init(cmdline_p);
+ 
+-	*cmdline_p = command_line;
+-
+-	parse_cmdline_early();
+-	bootmem_init();
+-	sparse_init();
+-	paging_init();
+ 	resource_init();
+ #ifdef CONFIG_SMP
+ 	plat_smp_setup();
+diff -Naur linux-2.6.17.orig/arch/mips/kernel/smtc-asm.S linux-2.6.17/arch/mips/kernel/smtc-asm.S
+--- linux-2.6.17.orig/arch/mips/kernel/smtc-asm.S	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/kernel/smtc-asm.S	2006-06-19 18:16:13.000000000 -0700
+@@ -52,12 +52,12 @@
+ 	.set	noat
+ 	/* Disable thread scheduling to make Status update atomic */
+ 	DMT	27					# dmt	k1
+-	ehb
++	_ehb
+ 	/* Set EXL */
+ 	mfc0	k0,CP0_STATUS
+ 	ori	k0,k0,ST0_EXL
+ 	mtc0	k0,CP0_STATUS
+-	ehb
++	_ehb
+ 	/* Thread scheduling now inhibited by EXL. Restore TE state. */
+ 	andi	k1,k1,VPECONTROL_TE
+ 	beqz	k1,1f
+@@ -82,7 +82,7 @@
+ 	li	k1,ST0_CU0
+ 	or	k1,k1,k0
+ 	mtc0	k1,CP0_STATUS
+-	ehb
++	_ehb
+ 	get_saved_sp
+ 	/* Interrupting TC will have pre-set values in slots in the new frame */
+ 2:	subu	k1,k1,PT_SIZE
+@@ -90,7 +90,7 @@
+ 	lw	k0,PT_TCSTATUS(k1)
+ 	/* Write it to TCStatus to restore CU/KSU/IXMT state */
+ 	mtc0	k0,$2,1
+-	ehb
++	_ehb
+ 	lw	k0,PT_EPC(k1)
+ 	mtc0	k0,CP0_EPC
+ 	/* Save all will redundantly recompute the SP, but use it for now */
+@@ -116,7 +116,7 @@
+ 	mfc0	t0,CP0_TCSTATUS
+ 	ori	t1,t0,TCSTATUS_IXMT
+ 	mtc0	t1,CP0_TCSTATUS
+-	ehb
++	_ehb
+ 	/* We know we're in kernel mode, so prepare stack frame */
+ 	subu	t1,sp,PT_SIZE
+ 	sw	ra,PT_EPC(t1)
+diff -Naur linux-2.6.17.orig/arch/mips/kernel/traps.c linux-2.6.17/arch/mips/kernel/traps.c
+--- linux-2.6.17.orig/arch/mips/kernel/traps.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/kernel/traps.c	2006-06-19 18:16:13.000000000 -0700
+@@ -65,7 +65,7 @@
+ extern asmlinkage void handle_reserved(void);
+ 
+ extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
+-	struct mips_fpu_soft_struct *ctx);
++	struct mips_fpu_struct *ctx);
+ 
+ void (*board_be_init)(void);
+ int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
+@@ -600,8 +600,7 @@
+ 		preempt_enable();
+ 
+ 		/* Run the emulator */
+-		sig = fpu_emulator_cop1Handler (regs,
+-			&current->thread.fpu.soft);
++		sig = fpu_emulator_cop1Handler (regs, &current->thread.fpu);
+ 
+ 		preempt_disable();
+ 
+@@ -610,7 +609,7 @@
+ 		 * We can't allow the emulated instruction to leave any of
+ 		 * the cause bit set in $fcr31.
+ 		 */
+-		current->thread.fpu.soft.fcr31 &= ~FPU_CSR_ALL_X;
++		current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
+ 
+ 		/* Restore the hardware register state */
+ 		restore_fp(current);
+@@ -755,7 +754,7 @@
+ 
+ 		if (!cpu_has_fpu) {
+ 			int sig = fpu_emulator_cop1Handler(regs,
+-						&current->thread.fpu.soft);
++						&current->thread.fpu);
+ 			if (sig)
+ 				force_sig(sig, current);
+ #ifdef CONFIG_MIPS_MT_FPAFF
+@@ -1051,7 +1050,7 @@
+ 	return (void *)old_handler;
+ }
+ 
+-#ifdef CONFIG_CPU_MIPSR2
++#ifdef CONFIG_CPU_MIPSR2_SRS
+ /*
+  * MIPSR2 shadow register set allocation
+  * FIXME: SMP...
+@@ -1070,11 +1069,9 @@
+ 
+ static void mips_srs_init(void)
+ {
+-#ifdef CONFIG_CPU_MIPSR2_SRS
+ 	shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
+ 	printk(KERN_INFO "%d MIPSR2 register sets available\n",
+ 	       shadow_registers.sr_supported);
+-#endif
+ 	shadow_registers.sr_allocated = 1;	/* Set 0 used by kernel */
+ }
+ 
+@@ -1199,7 +1196,14 @@
+ {
+ 	return set_vi_srs_handler(n, addr, 0);
+ }
+-#endif
++
++#else
++
++static inline void mips_srs_init(void)
++{
++}
++
++#endif /* CONFIG_CPU_MIPSR2_SRS */
+ 
+ /*
+  * This is used by native signal handling
+@@ -1389,9 +1393,7 @@
+ 	else
+ 		ebase = CAC_BASE;
+ 
+-#ifdef CONFIG_CPU_MIPSR2
+ 	mips_srs_init();
+-#endif
+ 
+ 	per_cpu_trap_init();
+ 
+diff -Naur linux-2.6.17.orig/arch/mips/lasat/setup.c linux-2.6.17/arch/mips/lasat/setup.c
+--- linux-2.6.17.orig/arch/mips/lasat/setup.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/lasat/setup.c	2006-06-19 18:16:13.000000000 -0700
+@@ -155,7 +155,7 @@
+ }
+ #endif
+ 
+-void __init plat_setup(void)
++void __init plat_mem_setup(void)
+ {
+ 	int i;
+ 	lasat_misc  = &lasat_misc_info[mips_machtype];
+diff -Naur linux-2.6.17.orig/arch/mips/lib/ashldi3.c linux-2.6.17/arch/mips/lib/ashldi3.c
+--- linux-2.6.17.orig/arch/mips/lib/ashldi3.c	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/arch/mips/lib/ashldi3.c	2006-06-19 18:16:13.000000000 -0700
+@@ -0,0 +1,29 @@
++#include <linux/module.h>
++
++#include "libgcc.h"
++
++long long __ashldi3(long long u, word_type b)
++{
++	DWunion uu, w;
++	word_type bm;
++
++	if (b == 0)
++		return u;
++
++	uu.ll = u;
++	bm = 32 - b;
++
++	if (bm <= 0) {
++		w.s.low = 0;
++		w.s.high = (unsigned int) uu.s.low << -bm;
++	} else {
++		const unsigned int carries = (unsigned int) uu.s.low >> bm;
++
++		w.s.low = (unsigned int) uu.s.low << b;
++		w.s.high = ((unsigned int) uu.s.high << b) | carries;
++	}
++
++	return w.ll;
++}
++
++EXPORT_SYMBOL(__ashldi3);
+diff -Naur linux-2.6.17.orig/arch/mips/lib/ashrdi3.c linux-2.6.17/arch/mips/lib/ashrdi3.c
+--- linux-2.6.17.orig/arch/mips/lib/ashrdi3.c	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/arch/mips/lib/ashrdi3.c	2006-06-19 18:16:13.000000000 -0700
+@@ -0,0 +1,31 @@
++#include <linux/module.h>
++
++#include "libgcc.h"
++
++long long __ashrdi3(long long u, word_type b)
++{
++	DWunion uu, w;
++	word_type bm;
++
++	if (b == 0)
++		return u;
++
++	uu.ll = u;
++	bm = 32 - b;
++
++	if (bm <= 0) {
++		/* w.s.high = 1..1 or 0..0 */
++		w.s.high =
++		    uu.s.high >> 31;
++		w.s.low = uu.s.high >> -bm;
++	} else {
++		const unsigned int carries = (unsigned int) uu.s.high << bm;
++
++		w.s.high = uu.s.high >> b;
++		w.s.low = ((unsigned int) uu.s.low >> b) | carries;
++	}
++
++	return w.ll;
++}
++
++EXPORT_SYMBOL(__ashrdi3);
+diff -Naur linux-2.6.17.orig/arch/mips/lib/libgcc.h linux-2.6.17/arch/mips/lib/libgcc.h
+--- linux-2.6.17.orig/arch/mips/lib/libgcc.h	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/arch/mips/lib/libgcc.h	2006-06-19 18:16:13.000000000 -0700
+@@ -0,0 +1,26 @@
++#ifndef __ASM_LIBGCC_H
++#define __ASM_LIBGCC_H
++
++#include <asm/byteorder.h>
++
++typedef int word_type __attribute__ ((mode (__word__)));
++
++#ifdef __BIG_ENDIAN
++struct DWstruct {
++	int high, low;
++};
++#elif defined(__LITTLE_ENDIAN)
++struct DWstruct {
++	int low, high;
++};
++#else
++#error I feel sick.
++#endif
++
++typedef union
++{
++	struct DWstruct s;
++	long long ll;
++} DWunion;
++
++#endif /* __ASM_LIBGCC_H */
+diff -Naur linux-2.6.17.orig/arch/mips/lib/lshrdi3.c linux-2.6.17/arch/mips/lib/lshrdi3.c
+--- linux-2.6.17.orig/arch/mips/lib/lshrdi3.c	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/arch/mips/lib/lshrdi3.c	2006-06-19 18:16:13.000000000 -0700
+@@ -0,0 +1,29 @@
++#include <linux/module.h>
++
++#include "libgcc.h"
++
++long long __lshrdi3(long long u, word_type b)
++{
++	DWunion uu, w;
++	word_type bm;
++
++	if (b == 0)
++		return u;
++
++	uu.ll = u;
++	bm = 32 - b;
++
++	if (bm <= 0) {
++		w.s.high = 0;
++		w.s.low = (unsigned int) uu.s.high >> -bm;
++	} else {
++		const unsigned int carries = (unsigned int) uu.s.high << bm;
++
++		w.s.high = (unsigned int) uu.s.high >> b;
++		w.s.low = ((unsigned int) uu.s.low >> b) | carries;
++	}
++
++	return w.ll;
++}
++
++EXPORT_SYMBOL(__lshrdi3);
+diff -Naur linux-2.6.17.orig/arch/mips/lib/Makefile linux-2.6.17/arch/mips/lib/Makefile
+--- linux-2.6.17.orig/arch/mips/lib/Makefile	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/lib/Makefile	2006-06-19 18:16:40.000000000 -0700
+@@ -7,4 +7,7 @@
+ 
+ obj-y	+= iomap.o
+ 
++# libgcc-style stuff needed in the kernel
++lib-y += ashldi3.o ashrdi3.o lshrdi3.o
++
+ EXTRA_AFLAGS := $(CFLAGS)
+diff -Naur linux-2.6.17.orig/arch/mips/lib-32/dump_tlb.c linux-2.6.17/arch/mips/lib-32/dump_tlb.c
+--- linux-2.6.17.orig/arch/mips/lib-32/dump_tlb.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/lib-32/dump_tlb.c	2006-06-19 18:16:13.000000000 -0700
+@@ -41,8 +41,6 @@
+ 		return "256Mb";
+ #endif
+ 	}
+-
+-	return "unknown";
+ }
+ 
+ #define BARRIER()					\
+diff -Naur linux-2.6.17.orig/arch/mips/lib-64/dump_tlb.c linux-2.6.17/arch/mips/lib-64/dump_tlb.c
+--- linux-2.6.17.orig/arch/mips/lib-64/dump_tlb.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/lib-64/dump_tlb.c	2006-06-19 18:16:13.000000000 -0700
+@@ -32,8 +32,6 @@
+ 	case PM_256M:	return "256Mb";
+ #endif
+ 	}
+-
+-	return "unknown";
+ }
+ 
+ #define BARRIER()					\
+diff -Naur linux-2.6.17.orig/arch/mips/Makefile linux-2.6.17/arch/mips/Makefile
+--- linux-2.6.17.orig/arch/mips/Makefile	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/Makefile	2006-06-19 18:16:13.000000000 -0700
+@@ -83,6 +83,8 @@
+ LDFLAGS_vmlinux			+= -G 0 -static -n -nostdlib
+ MODFLAGS			+= -mlong-calls
+ 
++cflags-y += -ffreestanding
++
+ #
+ # We explicitly add the endianness specifier if needed, this allows
+ # to compile kernels with a toolchain for the other endianness. We
+@@ -285,6 +287,13 @@
+ load-$(CONFIG_MIPS_EV96100)	+= 0xffffffff80100000
+ 
+ #
++# Wind River PPMC Board (4KC + GT64120)
++#
++core-$(CONFIG_WR_PPMC)		+= arch/mips/gt64120/wrppmc/
++cflags-$(CONFIG_WR_PPMC)		+= -Iinclude/asm-mips/mach-wrppmc
++load-$(CONFIG_WR_PPMC)		+= 0xffffffff80100000
++
++#
+ # Globespan IVR eval board with QED 5231 CPU
+ #
+ core-$(CONFIG_ITE_BOARD_GEN)	+= arch/mips/ite-boards/generic/
+@@ -365,6 +374,7 @@
+ cflags-$(CONFIG_PMC_YOSEMITE)	+= -Iinclude/asm-mips/mach-yosemite
+ load-$(CONFIG_PMC_YOSEMITE)	+= 0xffffffff80100000
+ 
++#
+ # Qemu simulating MIPS32 4Kc
+ #
+ core-$(CONFIG_QEMU)		+= arch/mips/qemu/
+@@ -379,6 +389,13 @@
+ load-$(CONFIG_MOMENCO_OCELOT_3) 	+= 0xffffffff80100000
+ 
+ #
++# Basler eXcite
++#
++core-$(CONFIG_BASLER_EXCITE)	+= arch/mips/basler/excite/
++cflags-$(CONFIG_BASLER_EXCITE)	+= -Iinclude/asm-mips/mach-excite
++load-$(CONFIG_BASLER_EXCITE)	+= 0x80100000
++
++#
+ # Momentum Jaguar ATX
+ #
+ core-$(CONFIG_MOMENCO_JAGUAR_ATX)	+= arch/mips/momentum/jaguar_atx/
+@@ -395,18 +412,6 @@
+ core-$(CONFIG_DDB5XXX_COMMON)	+= arch/mips/ddb5xxx/common/
+ 
+ #
+-# NEC DDB Vrc-5074
+-#
+-core-$(CONFIG_DDB5074)		+= arch/mips/ddb5xxx/ddb5074/
+-load-$(CONFIG_DDB5074)		+= 0xffffffff80080000
+-
+-#
+-# NEC DDB Vrc-5476
+-#
+-core-$(CONFIG_DDB5476)		+= arch/mips/ddb5xxx/ddb5476/
+-load-$(CONFIG_DDB5476)		+= 0xffffffff80080000
+-
+-#
+ # NEC DDB Vrc-5477
+ #
+ core-$(CONFIG_DDB5477)		+= arch/mips/ddb5xxx/ddb5477/
+@@ -468,6 +473,15 @@
+ #cflags-$(CONFIG_PNX8550_JBS)	+= -Iinclude/asm-mips/mach-pnx8550
+ load-$(CONFIG_PNX8550_JBS)	+= 0xffffffff80060000
+ 
++# NEC EMMA2RH boards
++#
++core-$(CONFIG_EMMA2RH)          += arch/mips/emma2rh/common/
++cflags-$(CONFIG_EMMA2RH)        += -Iinclude/asm-mips/mach-emma2rh
++
++# NEC EMMA2RH Mark-eins
++core-$(CONFIG_MARKEINS)         += arch/mips/emma2rh/markeins/
++load-$(CONFIG_MARKEINS)         += 0xffffffff88100000
++
+ #
+ # SGI IP22 (Indy/Indigo2)
+ #
+diff -Naur linux-2.6.17.orig/arch/mips/math-emu/cp1emu.c linux-2.6.17/arch/mips/math-emu/cp1emu.c
+--- linux-2.6.17.orig/arch/mips/math-emu/cp1emu.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/math-emu/cp1emu.c	2006-06-19 18:16:13.000000000 -0700
+@@ -60,15 +60,15 @@
+ 
+ /* Function which emulates a floating point instruction. */
+ 
+-static int fpu_emu(struct pt_regs *, struct mips_fpu_soft_struct *,
++static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
+ 	mips_instruction);
+ 
+ #if __mips >= 4 && __mips != 32
+ static int fpux_emu(struct pt_regs *,
+-	struct mips_fpu_soft_struct *, mips_instruction);
++	struct mips_fpu_struct *, mips_instruction);
+ #endif
+ 
+-/* Further private data for which no space exists in mips_fpu_soft_struct */
++/* Further private data for which no space exists in mips_fpu_struct */
+ 
+ struct mips_fpu_emulator_stats fpuemustats;
+ 
+@@ -203,7 +203,7 @@
+  * Two instructions if the instruction is in a branch delay slot.
+  */
+ 
+-static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
++static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
+ {
+ 	mips_instruction ir;
+ 	void * emulpc, *contpc;
+@@ -595,7 +595,7 @@
+ DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
+ DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
+ 
+-static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
++static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
+ 	mips_instruction ir)
+ {
+ 	unsigned rcsr = 0;	/* resulting csr */
+@@ -759,7 +759,7 @@
+ /*
+  * Emulate a single COP1 arithmetic instruction.
+  */
+-static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
++static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
+ 	mips_instruction ir)
+ {
+ 	int rfmt;		/* resulting format */
+@@ -1233,8 +1233,7 @@
+ 	return 0;
+ }
+ 
+-int fpu_emulator_cop1Handler(struct pt_regs *xcp,
+-	struct mips_fpu_soft_struct *ctx)
++int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
+ {
+ 	unsigned long oldepc, prevepc;
+ 	mips_instruction insn;
+diff -Naur linux-2.6.17.orig/arch/mips/math-emu/ieee754.h linux-2.6.17/arch/mips/math-emu/ieee754.h
+--- linux-2.6.17.orig/arch/mips/math-emu/ieee754.h	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/math-emu/ieee754.h	2006-06-19 18:16:13.000000000 -0700
+@@ -329,7 +329,7 @@
+ 	unsigned pad0:7;
+ #endif
+ };
+-#define ieee754_csr (*(struct _ieee754_csr *)(&current->thread.fpu.soft.fcr31))
++#define ieee754_csr (*(struct _ieee754_csr *)(&current->thread.fpu.fcr31))
+ 
+ static inline unsigned ieee754_getrm(void)
+ {
+diff -Naur linux-2.6.17.orig/arch/mips/math-emu/kernel_linkage.c linux-2.6.17/arch/mips/math-emu/kernel_linkage.c
+--- linux-2.6.17.orig/arch/mips/math-emu/kernel_linkage.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/math-emu/kernel_linkage.c	2006-06-19 18:16:13.000000000 -0700
+@@ -39,9 +39,9 @@
+ 		printk("Algorithmics/MIPS FPU Emulator v1.5\n");
+ 	}
+ 
+-	current->thread.fpu.soft.fcr31 = 0;
++	current->thread.fpu.fcr31 = 0;
+ 	for (i = 0; i < 32; i++) {
+-		current->thread.fpu.soft.fpr[i] = SIGNALLING_NAN;
++		current->thread.fpu.fpr[i] = SIGNALLING_NAN;
+ 	}
+ }
+ 
+@@ -59,10 +59,9 @@
+ 
+ 	for (i = 0; i < 32; i++) {
+ 		err |=
+-		    __put_user(current->thread.fpu.soft.fpr[i],
+-			       &sc->sc_fpregs[i]);
++		    __put_user(current->thread.fpu.fpr[i], &sc->sc_fpregs[i]);
+ 	}
+-	err |= __put_user(current->thread.fpu.soft.fcr31, &sc->sc_fpc_csr);
++	err |= __put_user(current->thread.fpu.fcr31, &sc->sc_fpc_csr);
+ 
+ 	return err;
+ }
+@@ -74,10 +73,9 @@
+ 
+ 	for (i = 0; i < 32; i++) {
+ 		err |=
+-		    __get_user(current->thread.fpu.soft.fpr[i],
+-			       &sc->sc_fpregs[i]);
++		    __get_user(current->thread.fpu.fpr[i], &sc->sc_fpregs[i]);
+ 	}
+-	err |= __get_user(current->thread.fpu.soft.fcr31, &sc->sc_fpc_csr);
++	err |= __get_user(current->thread.fpu.fcr31, &sc->sc_fpc_csr);
+ 
+ 	return err;
+ }
+@@ -94,10 +92,9 @@
+ 
+ 	for (i = 0; i < 32; i+=2) {
+ 		err |=
+-		    __put_user(current->thread.fpu.soft.fpr[i],
+-			       &sc->sc_fpregs[i]);
++		    __put_user(current->thread.fpu.fpr[i], &sc->sc_fpregs[i]);
+ 	}
+-	err |= __put_user(current->thread.fpu.soft.fcr31, &sc->sc_fpc_csr);
++	err |= __put_user(current->thread.fpu.fcr31, &sc->sc_fpc_csr);
+ 
+ 	return err;
+ }
+@@ -109,10 +106,9 @@
+ 
+ 	for (i = 0; i < 32; i+=2) {
+ 		err |=
+-		    __get_user(current->thread.fpu.soft.fpr[i],
+-			       &sc->sc_fpregs[i]);
++		    __get_user(current->thread.fpu.fpr[i], &sc->sc_fpregs[i]);
+ 	}
+-	err |= __get_user(current->thread.fpu.soft.fcr31, &sc->sc_fpc_csr);
++	err |= __get_user(current->thread.fpu.fcr31, &sc->sc_fpc_csr);
+ 
+ 	return err;
+ }
+diff -Naur linux-2.6.17.orig/arch/mips/mips-boards/atlas/atlas_setup.c linux-2.6.17/arch/mips/mips-boards/atlas/atlas_setup.c
+--- linux-2.6.17.orig/arch/mips/mips-boards/atlas/atlas_setup.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/mips-boards/atlas/atlas_setup.c	2006-06-19 18:16:13.000000000 -0700
+@@ -50,7 +50,7 @@
+ 	return "MIPS Atlas";
+ }
+ 
+-void __init plat_setup(void)
++void __init plat_mem_setup(void)
+ {
+ 	mips_pcibios_init();
+ 
+diff -Naur linux-2.6.17.orig/arch/mips/mips-boards/generic/memory.c linux-2.6.17/arch/mips/mips-boards/generic/memory.c
+--- linux-2.6.17.orig/arch/mips/mips-boards/generic/memory.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/mips-boards/generic/memory.c	2006-06-19 18:16:13.000000000 -0700
+@@ -76,6 +76,15 @@
+ 			memsize = simple_strtol(memsize_str, NULL, 0);
+ 		}
+ 	}
++
++#ifdef CONFIG_CPU_BIG_ENDIAN
++	/*
++	 * SOC-it swaps, or perhaps doesn't swap, when DMA'ing the last
++	 * word of physical memory
++	 */
++	memsize -= PAGE_SIZE;
++#endif
++
+ 	memset(mdesc, 0, sizeof(mdesc));
+ 
+ 	mdesc[0].type = yamon_dontuse;
+diff -Naur linux-2.6.17.orig/arch/mips/mips-boards/malta/malta_int.c linux-2.6.17/arch/mips/mips-boards/malta/malta_int.c
+--- linux-2.6.17.orig/arch/mips/mips-boards/malta/malta_int.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/mips-boards/malta/malta_int.c	2006-06-19 18:16:13.000000000 -0700
+@@ -208,23 +208,23 @@
+ 	unsigned int a0 = 7;
+ 	unsigned int t0;
+ 
+-	t0 = s0 & 0xf000;
++	t0 = pending & 0xf000;
+ 	t0 = t0 < 1;
+ 	t0 = t0 << 2;
+ 	a0 = a0 - t0;
+-	s0 = s0 << t0;
++	pending = pending << t0;
+ 
+-	t0 = s0 & 0xc000;
++	t0 = pending & 0xc000;
+ 	t0 = t0 < 1;
+ 	t0 = t0 << 1;
+ 	a0 = a0 - t0;
+-	s0 = s0 << t0;
++	pending = pending << t0;
+ 
+-	t0 = s0 & 0x8000;
++	t0 = pending & 0x8000;
+ 	t0 = t0 < 1;
+ 	//t0 = t0 << 2;
+ 	a0 = a0 - t0;
+-	//s0 = s0 << t0;
++	//pending = pending << t0;
+ 
+ 	return a0;
+ #endif
+diff -Naur linux-2.6.17.orig/arch/mips/mips-boards/malta/malta_setup.c linux-2.6.17/arch/mips/mips-boards/malta/malta_setup.c
+--- linux-2.6.17.orig/arch/mips/mips-boards/malta/malta_setup.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/mips-boards/malta/malta_setup.c	2006-06-19 18:16:13.000000000 -0700
+@@ -53,11 +53,11 @@
+ #endif
+ 
+ struct resource standard_io_resources[] = {
+-	{ "dma1", 0x00, 0x1f, IORESOURCE_BUSY },
+-	{ "timer", 0x40, 0x5f, IORESOURCE_BUSY },
+-	{ "keyboard", 0x60, 0x6f, IORESOURCE_BUSY },
+-	{ "dma page reg", 0x80, 0x8f, IORESOURCE_BUSY },
+-	{ "dma2", 0xc0, 0xdf, IORESOURCE_BUSY },
++	{ .name = "dma1", .start = 0x00, .end = 0x1f, .flags = IORESOURCE_BUSY },
++	{ .name = "timer", .start = 0x40, .end = 0x5f, .flags = IORESOURCE_BUSY },
++	{ .name = "keyboard", .start = 0x60, .end = 0x6f, .flags = IORESOURCE_BUSY },
++	{ .name = "dma page reg", .start = 0x80, .end = 0x8f, .flags = IORESOURCE_BUSY },
++	{ .name = "dma2", .start = 0xc0, .end = 0xdf, .flags = IORESOURCE_BUSY },
+ };
+ 
+ #ifdef CONFIG_MTD
+@@ -111,7 +111,7 @@
+ }
+ #endif
+ 
+-void __init plat_setup(void)
++void __init plat_mem_setup(void)
+ {
+ 	unsigned int i;
+ 
+diff -Naur linux-2.6.17.orig/arch/mips/mips-boards/malta/malta_smp.c linux-2.6.17/arch/mips/mips-boards/malta/malta_smp.c
+--- linux-2.6.17.orig/arch/mips/mips-boards/malta/malta_smp.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/mips-boards/malta/malta_smp.c	2006-06-19 18:16:13.000000000 -0700
+@@ -34,25 +34,6 @@
+ }
+ 
+ /*
+- * Detect available CPUs/VPEs/TCs and populate phys_cpu_present_map
+- */
+-
+-void __init prom_build_cpu_map(void)
+-{
+-	int nextslot;
+-
+-	/*
+-	 * As of November, 2004, MIPSsim only simulates one core
+-	 * at a time.  However, that core may be a MIPS MT core
+-	 * with multiple virtual processors and thread contexts.
+-	 */
+-
+-	if (read_c0_config3() & (1<<2)) {
+-		nextslot = mipsmt_build_cpu_map(1);
+-	}
+-}
+-
+-/*
+  * Platform "CPU" startup hook
+  */
+ 
+diff -Naur linux-2.6.17.orig/arch/mips/mips-boards/sead/sead_setup.c linux-2.6.17/arch/mips/mips-boards/sead/sead_setup.c
+--- linux-2.6.17.orig/arch/mips/mips-boards/sead/sead_setup.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/mips-boards/sead/sead_setup.c	2006-06-19 18:16:13.000000000 -0700
+@@ -45,7 +45,7 @@
+ 	return "MIPS SEAD";
+ }
+ 
+-void __init plat_setup(void)
++void __init plat_mem_setup(void)
+ {
+ 	ioport_resource.end = 0x7fffffff;
+ 
+diff -Naur linux-2.6.17.orig/arch/mips/mips-boards/sim/sim_setup.c linux-2.6.17/arch/mips/mips-boards/sim/sim_setup.c
+--- linux-2.6.17.orig/arch/mips/mips-boards/sim/sim_setup.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/mips-boards/sim/sim_setup.c	2006-06-19 18:16:13.000000000 -0700
+@@ -50,7 +50,7 @@
+ 	return "MIPSsim";
+ }
+ 
+-void __init plat_setup(void)
++void __init plat_mem_setup(void)
+ {
+ 	set_io_port_base(0xbfd00000);
+ 
+diff -Naur linux-2.6.17.orig/arch/mips/mips-boards/sim/sim_smp.c linux-2.6.17/arch/mips/mips-boards/sim/sim_smp.c
+--- linux-2.6.17.orig/arch/mips/mips-boards/sim/sim_smp.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/mips-boards/sim/sim_smp.c	2006-06-19 18:16:13.000000000 -0700
+@@ -51,27 +51,6 @@
+ }
+ 
+ /*
+- * Detect available CPUs/VPEs/TCs and populate phys_cpu_present_map
+- */
+-
+-void __init prom_build_cpu_map(void)
+-{
+-#ifdef CONFIG_MIPS_MT_SMTC
+-	int nextslot;
+-
+-	/*
+-	 * As of November, 2004, MIPSsim only simulates one core
+-	 * at a time.  However, that core may be a MIPS MT core
+-	 * with multiple virtual processors and thread contexts.
+-	 */
+-
+-	if (read_c0_config3() & (1<<2)) {
+-		nextslot = mipsmt_build_cpu_map(1);
+-	}
+-#endif /* CONFIG_MIPS_MT_SMTC */
+-}
+-
+-/*
+  * Platform "CPU" startup hook
+  */
+ 
+diff -Naur linux-2.6.17.orig/arch/mips/mm/tlb-r4k.c linux-2.6.17/arch/mips/mm/tlb-r4k.c
+--- linux-2.6.17.orig/arch/mips/mm/tlb-r4k.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/mm/tlb-r4k.c	2006-06-19 18:16:13.000000000 -0700
+@@ -413,7 +413,6 @@
+ 	return ret;
+ }
+ 
+-extern void __init sanitize_tlb_entries(void);
+ static void __init probe_tlb(unsigned long config)
+ {
+ 	struct cpuinfo_mips *c = &current_cpu_data;
+diff -Naur linux-2.6.17.orig/arch/mips/momentum/jaguar_atx/setup.c linux-2.6.17/arch/mips/momentum/jaguar_atx/setup.c
+--- linux-2.6.17.orig/arch/mips/momentum/jaguar_atx/setup.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/momentum/jaguar_atx/setup.c	2006-06-19 18:16:13.000000000 -0700
+@@ -359,7 +359,7 @@
+ 
+ arch_initcall(ja_pci_init);
+ 
+-void __init plat_setup(void)
++void __init plat_mem_setup(void)
+ {
+ 	unsigned int tmpword;
+ 
+diff -Naur linux-2.6.17.orig/arch/mips/momentum/ocelot_3/setup.c linux-2.6.17/arch/mips/momentum/ocelot_3/setup.c
+--- linux-2.6.17.orig/arch/mips/momentum/ocelot_3/setup.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/momentum/ocelot_3/setup.c	2006-06-19 18:16:13.000000000 -0700
+@@ -313,7 +313,7 @@
+ 
+ arch_initcall(ja_pci_init);
+ 
+-void __init plat_setup(void)
++void __init plat_mem_setup(void)
+ {
+ 	unsigned int tmpword;
+ 
+diff -Naur linux-2.6.17.orig/arch/mips/momentum/ocelot_c/setup.c linux-2.6.17/arch/mips/momentum/ocelot_c/setup.c
+--- linux-2.6.17.orig/arch/mips/momentum/ocelot_c/setup.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/momentum/ocelot_c/setup.c	2006-06-19 18:16:13.000000000 -0700
+@@ -231,7 +231,7 @@
+ 	rtc_mips_set_time = m48t37y_set_time;
+ }
+ 
+-void __init plat_setup(void)
++void __init plat_mem_setup(void)
+ {
+ 	unsigned int tmpword;
+ 
+diff -Naur linux-2.6.17.orig/arch/mips/momentum/ocelot_g/setup.c linux-2.6.17/arch/mips/momentum/ocelot_g/setup.c
+--- linux-2.6.17.orig/arch/mips/momentum/ocelot_g/setup.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/momentum/ocelot_g/setup.c	2006-06-19 18:16:13.000000000 -0700
+@@ -162,7 +162,7 @@
+ 	printk("Done\n");
+ }
+ 
+-void __init plat_setup(void)
++void __init plat_mem_setup(void)
+ {
+ 	void (*l3func)(unsigned long) = (void *) KSEG1ADDR(setup_l3cache);
+ 	unsigned int tmpword;
+diff -Naur linux-2.6.17.orig/arch/mips/pci/fixup-ddb5074.c linux-2.6.17/arch/mips/pci/fixup-ddb5074.c
+--- linux-2.6.17.orig/arch/mips/pci/fixup-ddb5074.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/pci/fixup-ddb5074.c	1969-12-31 16:00:00.000000000 -0800
+@@ -1,21 +0,0 @@
+-/*
+- * It's nice to have the LEDs on the GPIO pins available for debugging
+- */
+-static void ddb5074_fixup(struct pci_dev *dev)
+-{
+-	extern struct pci_dev *pci_pmu;
+-	u8 t8;
+-
+-	pci_pmu = dev;  /* for LEDs D2 and D3 */
+-	/* Program the lines for LEDs D2 and D3 to output */
+-	pci_read_config_byte(dev, 0x7d, &t8);
+-	t8 |= 0xc0;
+-	pci_write_config_byte(dev, 0x7d, t8);
+-	/* Turn LEDs D2 and D3 off */
+-	pci_read_config_byte(dev, 0x7e, &t8);
+-	t8 |= 0xc0;
+-	pci_write_config_byte(dev, 0x7e, t8);
+-}
+-
+-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101,
+-	  ddb5074_fixup);
+diff -Naur linux-2.6.17.orig/arch/mips/pci/fixup-emma2rh.c linux-2.6.17/arch/mips/pci/fixup-emma2rh.c
+--- linux-2.6.17.orig/arch/mips/pci/fixup-emma2rh.c	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/arch/mips/pci/fixup-emma2rh.c	2006-06-19 18:16:13.000000000 -0700
+@@ -0,0 +1,102 @@
++/*
++ *  arch/mips/pci/fixup-emma2rh.c
++ *      This file defines the PCI configration.
++ *
++ *  Copyright (C) NEC Electronics Corporation 2004-2006
++ *
++ *  This file is based on the arch/mips/ddb5xxx/ddb5477/pci.c
++ *
++ *	Copyright 2001 MontaVista Software Inc.
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License as published by
++ *  the Free Software Foundation; either version 2 of the License, or
++ *  (at your option) any later version.
++ *
++ *  This program is distributed in the hope that it will be useful,
++ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *  GNU General Public License for more details.
++ *
++ *  You should have received a copy of the GNU General Public License
++ *  along with this program; if not, write to the Free Software
++ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
++ */
++
++#include <linux/config.h>
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/types.h>
++#include <linux/pci.h>
++
++#include <asm/bootinfo.h>
++#include <asm/debug.h>
++
++#include <asm/emma2rh/emma2rh.h>
++
++#define EMMA2RH_PCI_HOST_SLOT 0x09
++#define EMMA2RH_USB_SLOT 0x03
++#define PCI_DEVICE_ID_NEC_EMMA2RH      0x014b /* EMMA2RH PCI Host */
++
++/*
++ * we fix up irqs based on the slot number.
++ * The first entry is at AD:11.
++ * Fortunately this works because, although we have two pci buses,
++ * they all have different slot numbers (except for rockhopper slot 20
++ * which is handled below).
++ *
++ */
++
++#define	MAX_SLOT_NUM 10
++static unsigned char irq_map[][5] __initdata = {
++	[3] = {0, MARKEINS_PCI_IRQ_INTB, MARKEINS_PCI_IRQ_INTC,
++	       MARKEINS_PCI_IRQ_INTD, 0,},
++	[4] = {0, MARKEINS_PCI_IRQ_INTA, 0, 0, 0,},
++	[5] = {0, 0, 0, 0, 0,},
++	[6] = {0, MARKEINS_PCI_IRQ_INTC, MARKEINS_PCI_IRQ_INTD,
++	       MARKEINS_PCI_IRQ_INTA, MARKEINS_PCI_IRQ_INTB,},
++};
++
++static void __devinit nec_usb_controller_fixup(struct pci_dev *dev)
++{
++	if (PCI_SLOT(dev->devfn) == EMMA2RH_USB_SLOT)
++		/* on board USB controller configuration */
++		pci_write_config_dword(dev, 0xe4, 1 << 5);
++}
++
++DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB,
++			nec_usb_controller_fixup);
++
++/*
++ * Prevent the PCI layer from seeing the resources allocated to this device
++ * if it is the host bridge by marking it as such.  These resources are of
++ * no consequence to the PCI layer (they are handled elsewhere).
++ */
++static void __devinit emma2rh_pci_host_fixup(struct pci_dev *dev)
++{
++	int i;
++
++	if (PCI_SLOT(dev->devfn) == EMMA2RH_PCI_HOST_SLOT) {
++		dev->class &= 0xff;
++		dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
++		for (i = 0; i < PCI_NUM_RESOURCES; i++) {
++			dev->resource[i].start = 0;
++			dev->resource[i].end = 0;
++			dev->resource[i].flags = 0;
++		}
++	}
++}
++
++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_EMMA2RH,
++			 emma2rh_pci_host_fixup);
++
++int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
++{
++	return irq_map[slot][pin];
++}
++
++/* Do platform specific device initialization at pci_enable_device() time */
++int pcibios_plat_dev_init(struct pci_dev *dev)
++{
++	return 0;
++}
+diff -Naur linux-2.6.17.orig/arch/mips/pci/fixup-excite.c linux-2.6.17/arch/mips/pci/fixup-excite.c
+--- linux-2.6.17.orig/arch/mips/pci/fixup-excite.c	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/arch/mips/pci/fixup-excite.c	2006-06-19 18:16:13.000000000 -0700
+@@ -0,0 +1,36 @@
++/*
++ *  Copyright (C) 2004 by Basler Vision Technologies AG
++ *  Author: Thomas Koeller <thomas.koeller@baslerweb.com>
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License as published by
++ *  the Free Software Foundation; either version 2 of the License, or
++ *  (at your option) any later version.
++ *
++ *  This program is distributed in the hope that it will be useful,
++ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *  GNU General Public License for more details.
++ *
++ *  You should have received a copy of the GNU General Public License
++ *  along with this program; if not, write to the Free Software
++ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
++ */
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/pci.h>
++#include <excite.h>
++
++int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
++{
++	if (pin == 0)
++		return -1;
++
++	return USB_IRQ;		/* USB controller is the only PCI device */
++}
++
++/* Do platform specific device initialization at pci_enable_device() time */
++int pcibios_plat_dev_init(struct pci_dev *dev)
++{
++	return 0;
++}
+diff -Naur linux-2.6.17.orig/arch/mips/pci/fixup-tb0219.c linux-2.6.17/arch/mips/pci/fixup-tb0219.c
+--- linux-2.6.17.orig/arch/mips/pci/fixup-tb0219.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/pci/fixup-tb0219.c	2006-06-19 18:16:13.000000000 -0700
+@@ -2,7 +2,7 @@
+  *  fixup-tb0219.c, The TANBAC TB0219 specific PCI fixups.
+  *
+  *  Copyright (C) 2003  Megasolution Inc. <matsu@megasolution.jp>
+- *  Copyright (C) 2004  Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
++ *  Copyright (C) 2004-2005  Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
+  *
+  *  This program is free software; you can redistribute it and/or modify
+  *  it under the terms of the GNU General Public License as published by
+diff -Naur linux-2.6.17.orig/arch/mips/pci/fixup-wrppmc.c linux-2.6.17/arch/mips/pci/fixup-wrppmc.c
+--- linux-2.6.17.orig/arch/mips/pci/fixup-wrppmc.c	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/arch/mips/pci/fixup-wrppmc.c	2006-06-19 18:16:13.000000000 -0700
+@@ -0,0 +1,37 @@
++/*
++ * fixup-wrppmc.c: PPMC board specific PCI fixup
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2006, Wind River Inc. Rongkai.zhan (rongkai.zhan@windriver.com)
++ */
++#include <linux/init.h>
++#include <linux/pci.h>
++#include <asm/gt64120.h>
++
++/* PCI interrupt pins */
++#define PCI_INTA		1
++#define PCI_INTB		2
++#define PCI_INTC		3
++#define PCI_INTD		4
++
++#define PCI_SLOT_MAXNR	32 /* Each PCI bus has 32 physical slots */
++
++static char pci_irq_tab[PCI_SLOT_MAXNR][5] __initdata = {
++	/* 0    INTA   INTB   INTC   INTD */
++	[0] = {0, 0, 0, 0, 0},		/* Slot 0: GT64120 PCI bridge */
++	[6] = {0, WRPPMC_PCI_INTA_IRQ, 0, 0, 0},
++};
++
++int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
++{
++	return pci_irq_tab[slot][pin];
++}
++
++/* Do platform specific device initialization at pci_enable_device() time */
++int pcibios_plat_dev_init(struct pci_dev *dev)
++{
++	return 0;
++}
+diff -Naur linux-2.6.17.orig/arch/mips/pci/Makefile linux-2.6.17/arch/mips/pci/Makefile
+--- linux-2.6.17.orig/arch/mips/pci/Makefile	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/pci/Makefile	2006-06-19 18:16:13.000000000 -0700
+@@ -18,12 +18,12 @@
+ obj-$(CONFIG_MIPS_TX3927)	+= ops-tx3927.o
+ obj-$(CONFIG_PCI_VR41XX)	+= ops-vr41xx.o pci-vr41xx.o
+ obj-$(CONFIG_NEC_CMBVR4133)	+= fixup-vr4133.o
++obj-$(CONFIG_MARKEINS)		+= ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o
+ 
+ #
+ # These are still pretty much in the old state, watch, go blind.
+ #
+-obj-$(CONFIG_DDB5074)		+= fixup-ddb5074.o pci-ddb5074.o ops-ddb5074.o
+-obj-$(CONFIG_DDB5476)		+= ops-ddb5476.o pci-ddb5476.o
++obj-$(CONFIG_BASLER_EXCITE)	= ops-titan.o pci-excite.o fixup-excite.o
+ obj-$(CONFIG_DDB5477)		+= fixup-ddb5477.o pci-ddb5477.o ops-ddb5477.o
+ obj-$(CONFIG_LASAT)		+= pci-lasat.o
+ obj-$(CONFIG_MIPS_ATLAS)	+= fixup-atlas.o
+@@ -43,7 +43,7 @@
+ obj-$(CONFIG_MOMENCO_OCELOT_G)	+= fixup-ocelot-g.o pci-ocelot-g.o
+ obj-$(CONFIG_PMC_YOSEMITE)	+= fixup-yosemite.o ops-titan.o ops-titan-ht.o \
+ 				   pci-yosemite.o
+-obj-$(CONFIG_SGI_IP27)		+= pci-ip27.o
++obj-$(CONFIG_SGI_IP27)		+= ops-bridge.o pci-ip27.o
+ obj-$(CONFIG_SGI_IP32)		+= fixup-ip32.o ops-mace.o pci-ip32.o
+ obj-$(CONFIG_SIBYTE_SB1250)	+= fixup-sb1250.o pci-sb1250.o
+ obj-$(CONFIG_SIBYTE_BCM112X)	+= fixup-sb1250.o pci-sb1250.o
+@@ -57,3 +57,4 @@
+ obj-$(CONFIG_TOSHIBA_RBTX4938)	+= fixup-tx4938.o ops-tx4938.o
+ obj-$(CONFIG_VICTOR_MPC30X)	+= fixup-mpc30x.o
+ obj-$(CONFIG_ZAO_CAPCELLA)	+= fixup-capcella.o
++obj-$(CONFIG_WR_PPMC)		+= fixup-wrppmc.o
+diff -Naur linux-2.6.17.orig/arch/mips/pci/ops-bridge.c linux-2.6.17/arch/mips/pci/ops-bridge.c
+--- linux-2.6.17.orig/arch/mips/pci/ops-bridge.c	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/arch/mips/pci/ops-bridge.c	2006-06-19 18:16:13.000000000 -0700
+@@ -0,0 +1,306 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 1999, 2000, 04, 06 Ralf Baechle (ralf@linux-mips.org)
++ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
++ */
++#include <linux/pci.h>
++#include <asm/paccess.h>
++#include <asm/pci/bridge.h>
++#include <asm/sn/arch.h>
++#include <asm/sn/intr.h>
++#include <asm/sn/sn0/hub.h>
++
++/*
++ * The Bridge ASIC supports both type 0 and type 1 access.  Type 1 is
++ * not really documented, so right now I can't write code which uses it.
++ * Therefore we use type 0 accesses for now even though they won't work
++ * correcly for PCI-to-PCI bridges.
++ *
++ * The function is complicated by the ultimate brokeness of the IOC3 chip
++ * which is used in SGI systems.  The IOC3 can only handle 32-bit PCI
++ * accesses and does only decode parts of it's address space.
++ */
++
++static int pci_conf0_read_config(struct pci_bus *bus, unsigned int devfn,
++				 int where, int size, u32 * value)
++{
++	struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
++	bridge_t *bridge = bc->base;
++	int slot = PCI_SLOT(devfn);
++	int fn = PCI_FUNC(devfn);
++	volatile void *addr;
++	u32 cf, shift, mask;
++	int res;
++
++	addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID];
++	if (get_dbe(cf, (u32 *) addr))
++		return PCIBIOS_DEVICE_NOT_FOUND;
++
++	/*
++	 * IOC3 is fucked fucked beyond believe ...  Don't even give the
++	 * generic PCI code a chance to look at it for real ...
++	 */
++	if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
++		goto oh_my_gawd;
++
++	addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)];
++
++	if (size == 1)
++		res = get_dbe(*value, (u8 *) addr);
++	else if (size == 2)
++		res = get_dbe(*value, (u16 *) addr);
++	else
++		res = get_dbe(*value, (u32 *) addr);
++
++	return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
++
++oh_my_gawd:
++
++	/*
++	 * IOC3 is fucked fucked beyond believe ...  Don't even give the
++	 * generic PCI code a chance to look at the wrong register.
++	 */
++	if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) {
++		*value = 0;
++		return PCIBIOS_SUCCESSFUL;
++	}
++
++	/*
++	 * IOC3 is fucked fucked beyond believe ...  Don't try to access
++	 * anything but 32-bit words ...
++	 */
++	addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
++
++	if (get_dbe(cf, (u32 *) addr))
++		return PCIBIOS_DEVICE_NOT_FOUND;
++
++	shift = ((where & 3) << 3);
++	mask = (0xffffffffU >> ((4 - size) << 3));
++	*value = (cf >> shift) & mask;
++
++	return PCIBIOS_SUCCESSFUL;
++}
++
++static int pci_conf1_read_config(struct pci_bus *bus, unsigned int devfn,
++				 int where, int size, u32 * value)
++{
++	struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
++	bridge_t *bridge = bc->base;
++	int busno = bus->number;
++	int slot = PCI_SLOT(devfn);
++	int fn = PCI_FUNC(devfn);
++	volatile void *addr;
++	u32 cf, shift, mask;
++	int res;
++
++	bridge->b_pci_cfg = (busno << 16) | (slot << 11);
++	addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID];
++	if (get_dbe(cf, (u32 *) addr))
++		return PCIBIOS_DEVICE_NOT_FOUND;
++
++	/*
++	 * IOC3 is fucked fucked beyond believe ...  Don't even give the
++	 * generic PCI code a chance to look at it for real ...
++	 */
++	if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
++		goto oh_my_gawd;
++
++	bridge->b_pci_cfg = (busno << 16) | (slot << 11);
++	addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))];
++
++	if (size == 1)
++		res = get_dbe(*value, (u8 *) addr);
++	else if (size == 2)
++		res = get_dbe(*value, (u16 *) addr);
++	else
++		res = get_dbe(*value, (u32 *) addr);
++
++	return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
++
++oh_my_gawd:
++
++	/*
++	 * IOC3 is fucked fucked beyond believe ...  Don't even give the
++	 * generic PCI code a chance to look at the wrong register.
++	 */
++	if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) {
++		*value = 0;
++		return PCIBIOS_SUCCESSFUL;
++	}
++
++	/*
++	 * IOC3 is fucked fucked beyond believe ...  Don't try to access
++	 * anything but 32-bit words ...
++	 */
++	bridge->b_pci_cfg = (busno << 16) | (slot << 11);
++	addr = &bridge->b_type1_cfg.c[(fn << 8) | where];
++
++	if (get_dbe(cf, (u32 *) addr))
++		return PCIBIOS_DEVICE_NOT_FOUND;
++
++	shift = ((where & 3) << 3);
++	mask = (0xffffffffU >> ((4 - size) << 3));
++	*value = (cf >> shift) & mask;
++
++	return PCIBIOS_SUCCESSFUL;
++}
++
++static int pci_read_config(struct pci_bus *bus, unsigned int devfn,
++			   int where, int size, u32 * value)
++{
++	if (bus->number > 0)
++		return pci_conf1_read_config(bus, devfn, where, size, value);
++
++	return pci_conf0_read_config(bus, devfn, where, size, value);
++}
++
++static int pci_conf0_write_config(struct pci_bus *bus, unsigned int devfn,
++				  int where, int size, u32 value)
++{
++	struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
++	bridge_t *bridge = bc->base;
++	int slot = PCI_SLOT(devfn);
++	int fn = PCI_FUNC(devfn);
++	volatile void *addr;
++	u32 cf, shift, mask, smask;
++	int res;
++
++	addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID];
++	if (get_dbe(cf, (u32 *) addr))
++		return PCIBIOS_DEVICE_NOT_FOUND;
++
++	/*
++	 * IOC3 is fucked fucked beyond believe ...  Don't even give the
++	 * generic PCI code a chance to look at it for real ...
++	 */
++	if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
++		goto oh_my_gawd;
++
++	addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)];
++
++	if (size == 1) {
++		res = put_dbe(value, (u8 *) addr);
++	} else if (size == 2) {
++		res = put_dbe(value, (u16 *) addr);
++	} else {
++		res = put_dbe(value, (u32 *) addr);
++	}
++
++	if (res)
++		return PCIBIOS_DEVICE_NOT_FOUND;
++
++	return PCIBIOS_SUCCESSFUL;
++
++oh_my_gawd:
++
++	/*
++	 * IOC3 is fucked fucked beyond believe ...  Don't even give the
++	 * generic PCI code a chance to touch the wrong register.
++	 */
++	if ((where >= 0x14 && where < 0x40) || (where >= 0x48))
++		return PCIBIOS_SUCCESSFUL;
++
++	/*
++	 * IOC3 is fucked fucked beyond believe ...  Don't try to access
++	 * anything but 32-bit words ...
++	 */
++	addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
++
++	if (get_dbe(cf, (u32 *) addr))
++		return PCIBIOS_DEVICE_NOT_FOUND;
++
++	shift = ((where & 3) << 3);
++	mask = (0xffffffffU >> ((4 - size) << 3));
++	smask = mask << shift;
++
++	cf = (cf & ~smask) | ((value & mask) << shift);
++	if (put_dbe(cf, (u32 *) addr))
++		return PCIBIOS_DEVICE_NOT_FOUND;
++
++	return PCIBIOS_SUCCESSFUL;
++}
++
++static int pci_conf1_write_config(struct pci_bus *bus, unsigned int devfn,
++				  int where, int size, u32 value)
++{
++	struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
++	bridge_t *bridge = bc->base;
++	int slot = PCI_SLOT(devfn);
++	int fn = PCI_FUNC(devfn);
++	int busno = bus->number;
++	volatile void *addr;
++	u32 cf, shift, mask, smask;
++	int res;
++
++	bridge->b_pci_cfg = (busno << 16) | (slot << 11);
++	addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID];
++	if (get_dbe(cf, (u32 *) addr))
++		return PCIBIOS_DEVICE_NOT_FOUND;
++
++	/*
++	 * IOC3 is fucked fucked beyond believe ...  Don't even give the
++	 * generic PCI code a chance to look at it for real ...
++	 */
++	if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
++		goto oh_my_gawd;
++
++	addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))];
++
++	if (size == 1) {
++		res = put_dbe(value, (u8 *) addr);
++	} else if (size == 2) {
++		res = put_dbe(value, (u16 *) addr);
++	} else {
++		res = put_dbe(value, (u32 *) addr);
++	}
++
++	if (res)
++		return PCIBIOS_DEVICE_NOT_FOUND;
++
++	return PCIBIOS_SUCCESSFUL;
++
++oh_my_gawd:
++
++	/*
++	 * IOC3 is fucked fucked beyond believe ...  Don't even give the
++	 * generic PCI code a chance to touch the wrong register.
++	 */
++	if ((where >= 0x14 && where < 0x40) || (where >= 0x48))
++		return PCIBIOS_SUCCESSFUL;
++
++	/*
++	 * IOC3 is fucked fucked beyond believe ...  Don't try to access
++	 * anything but 32-bit words ...
++	 */
++	addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
++
++	if (get_dbe(cf, (u32 *) addr))
++		return PCIBIOS_DEVICE_NOT_FOUND;
++
++	shift = ((where & 3) << 3);
++	mask = (0xffffffffU >> ((4 - size) << 3));
++	smask = mask << shift;
++
++	cf = (cf & ~smask) | ((value & mask) << shift);
++	if (put_dbe(cf, (u32 *) addr))
++		return PCIBIOS_DEVICE_NOT_FOUND;
++
++	return PCIBIOS_SUCCESSFUL;
++}
++
++static int pci_write_config(struct pci_bus *bus, unsigned int devfn,
++	int where, int size, u32 value)
++{
++	if (bus->number > 0)
++		return pci_conf1_write_config(bus, devfn, where, size, value);
++
++	return pci_conf0_write_config(bus, devfn, where, size, value);
++}
++
++struct pci_ops bridge_pci_ops = {
++	.read	= pci_read_config,
++	.write	= pci_write_config,
++};
+diff -Naur linux-2.6.17.orig/arch/mips/pci/ops-ddb5074.c linux-2.6.17/arch/mips/pci/ops-ddb5074.c
+--- linux-2.6.17.orig/arch/mips/pci/ops-ddb5074.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/pci/ops-ddb5074.c	1969-12-31 16:00:00.000000000 -0800
+@@ -1,271 +0,0 @@
+-/*
+- * Copyright 2001 MontaVista Software Inc.
+- * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
+- *
+- * arch/mips/ddb5xxx/ddb5476/pci_ops.c
+- *     Define the pci_ops for DB5477.
+- *
+- * Much of the code is derived from the original DDB5074 port by
+- * Geert Uytterhoeven <geert@sonycom.com>
+- *
+- * This program is free software; you can redistribute  it and/or modify it
+- * under  the terms of  the GNU General  Public License as published by the
+- * Free Software Foundation;  either version 2 of the  License, or (at your
+- * option) any later version.
+- *
+- */
+-#include <linux/pci.h>
+-#include <linux/kernel.h>
+-#include <linux/types.h>
+-
+-#include <asm/addrspace.h>
+-#include <asm/debug.h>
+-
+-#include <asm/ddb5xxx/ddb5xxx.h>
+-
+-/*
+- * config_swap structure records what set of pdar/pmr are used
+- * to access pci config space.  It also provides a place hold the
+- * original values for future restoring.
+- */
+-struct pci_config_swap {
+-	u32 pdar;
+-	u32 pmr;
+-	u32 config_base;
+-	u32 config_size;
+-	u32 pdar_backup;
+-	u32 pmr_backup;
+-};
+-
+-/*
+- * On DDB5476, we have one set of swap registers
+- */
+-struct pci_config_swap ext_pci_swap = {
+-	DDB_PCIW0,
+-	DDB_PCIINIT0,
+-	DDB_PCI_CONFIG_BASE,
+-	DDB_PCI_CONFIG_SIZE
+-};
+-
+-static int pci_config_workaround = 1;
+-
+-/*
+- * access config space
+- */
+-static inline u32 ddb_access_config_base(struct pci_config_swap *swap, u32 bus,	/* 0 means top level bus */
+-					 u32 slot_num)
+-{
+-	u32 pci_addr = 0;
+-	u32 pciinit_offset = 0;
+-	u32 virt_addr = swap->config_base;
+-	u32 option;
+-
+-	if (pci_config_workaround) {
+-		if (slot_num == 5)
+-			slot_num = 14;
+-	} else {
+-		if (slot_num == 5)
+-			return DDB_BASE + DDB_PCI_BASE;
+-	}
+-
+-	/* minimum pdar (window) size is 2MB */
+-	db_assert(swap->config_size >= (2 << 20));
+-
+-	db_assert(slot_num < (1 << 5));
+-	db_assert(bus < (1 << 8));
+-
+-	/* backup registers */
+-	swap->pdar_backup = ddb_in32(swap->pdar);
+-	swap->pmr_backup = ddb_in32(swap->pmr);
+-
+-	/* set the pdar (pci window) register */
+-	ddb_set_pdar(swap->pdar, swap->config_base, swap->config_size, 32,	/* 32 bit wide */
+-		     0,		/* not on local memory bus */
+-		     0);	/* not visible from PCI bus (N/A) */
+-
+-	/*
+-	 * calcuate the absolute pci config addr;
+-	 * according to the spec, we start scanning from adr:11 (0x800)
+-	 */
+-	if (bus == 0) {
+-		/* type 0 config */
+-		pci_addr = 0x00040000 << slot_num;
+-	} else {
+-		/* type 1 config */
+-		pci_addr = 0x00040000 << slot_num;
+-		panic
+-		    ("ddb_access_config_base: we don't support type 1 config Yet");
+-	}
+-
+-	/*
+-	 * if pci_addr is less than pci config window size,  we set
+-	 * pciinit_offset to 0 and adjust the virt_address.
+-	 * Otherwise we will try to adjust pciinit_offset.
+-	 */
+-	if (pci_addr < swap->config_size) {
+-		virt_addr = KSEG1ADDR(swap->config_base + pci_addr);
+-		pciinit_offset = 0;
+-	} else {
+-		db_assert((pci_addr & (swap->config_size - 1)) == 0);
+-		virt_addr = KSEG1ADDR(swap->config_base);
+-		pciinit_offset = pci_addr;
+-	}
+-
+-	/* set the pmr register */
+-	option = DDB_PCI_ACCESS_32;
+-	if (bus != 0)
+-		option |= DDB_PCI_CFGTYPE1;
+-	ddb_set_pmr(swap->pmr, DDB_PCICMD_CFG, pciinit_offset, option);
+-
+-	return virt_addr;
+-}
+-
+-static inline void ddb_close_config_base(struct pci_config_swap *swap)
+-{
+-	ddb_out32(swap->pdar, swap->pdar_backup);
+-	ddb_out32(swap->pmr, swap->pmr_backup);
+-}
+-
+-static int read_config_dword(struct pci_config_swap *swap,
+-			     struct pci_dev *dev, u32 where, u32 * val)
+-{
+-	u32 bus, slot_num, func_num;
+-	u32 base;
+-
+-	db_assert((where & 3) == 0);
+-	db_assert(where < (1 << 8));
+-
+-	/* check if the bus is top-level */
+-	if (dev->bus->parent != NULL) {
+-		bus = dev->bus->number;
+-		db_assert(bus != 0);
+-	} else {
+-		bus = 0;
+-	}
+-
+-	slot_num = PCI_SLOT(dev->devfn);
+-	func_num = PCI_FUNC(dev->devfn);
+-	base = ddb_access_config_base(swap, bus, slot_num);
+-	*val = *(volatile u32 *) (base + (func_num << 8) + where);
+-	ddb_close_config_base(swap);
+-	return PCIBIOS_SUCCESSFUL;
+-}
+-
+-static int read_config_word(struct pci_config_swap *swap,
+-			    struct pci_dev *dev, u32 where, u16 * val)
+-{
+-	int status;
+-	u32 result;
+-
+-	db_assert((where & 1) == 0);
+-
+-	status = read_config_dword(swap, dev, where & ~3, &result);
+-	if (where & 2)
+-		result >>= 16;
+-	*val = result & 0xffff;
+-	return status;
+-}
+-
+-static int read_config_byte(struct pci_config_swap *swap,
+-			    struct pci_dev *dev, u32 where, u8 * val)
+-{
+-	int status;
+-	u32 result;
+-
+-	status = read_config_dword(swap, dev, where & ~3, &result);
+-	if (where & 1)
+-		result >>= 8;
+-	if (where & 2)
+-		result >>= 16;
+-	*val = result & 0xff;
+-	return status;
+-}
+-
+-static int write_config_dword(struct pci_config_swap *swap,
+-			      struct pci_dev *dev, u32 where, u32 val)
+-{
+-	u32 bus, slot_num, func_num;
+-	u32 base;
+-
+-	db_assert((where & 3) == 0);
+-	db_assert(where < (1 << 8));
+-
+-	/* check if the bus is top-level */
+-	if (dev->bus->parent != NULL) {
+-		bus = dev->bus->number;
+-		db_assert(bus != 0);
+-	} else {
+-		bus = 0;
+-	}
+-
+-	slot_num = PCI_SLOT(dev->devfn);
+-	func_num = PCI_FUNC(dev->devfn);
+-	base = ddb_access_config_base(swap, bus, slot_num);
+-	*(volatile u32 *) (base + (func_num << 8) + where) = val;
+-	ddb_close_config_base(swap);
+-	return PCIBIOS_SUCCESSFUL;
+-}
+-
+-static int write_config_word(struct pci_config_swap *swap,
+-			     struct pci_dev *dev, u32 where, u16 val)
+-{
+-	int status, shift = 0;
+-	u32 result;
+-
+-	db_assert((where & 1) == 0);
+-
+-	status = read_config_dword(swap, dev, where & ~3, &result);
+-	if (status != PCIBIOS_SUCCESSFUL)
+-		return status;
+-
+-	if (where & 2)
+-		shift += 16;
+-	result &= ~(0xffff << shift);
+-	result |= val << shift;
+-	return write_config_dword(swap, dev, where & ~3, result);
+-}
+-
+-static int write_config_byte(struct pci_config_swap *swap,
+-			     struct pci_dev *dev, u32 where, u8 val)
+-{
+-	int status, shift = 0;
+-	u32 result;
+-
+-	status = read_config_dword(swap, dev, where & ~3, &result);
+-	if (status != PCIBIOS_SUCCESSFUL)
+-		return status;
+-
+-	if (where & 2)
+-		shift += 16;
+-	if (where & 1)
+-		shift += 8;
+-	result &= ~(0xff << shift);
+-	result |= val << shift;
+-	return write_config_dword(swap, dev, where & ~3, result);
+-}
+-
+-#define	MAKE_PCI_OPS(prefix, rw, unitname, unittype, pciswap) \
+-static int prefix##_##rw##_config_##unitname(struct pci_dev *dev, int where, unittype val) \
+-{ \
+-     return rw##_config_##unitname(pciswap, \
+-                                   dev, \
+-                                   where, \
+-                                   val); \
+-}
+-
+-MAKE_PCI_OPS(extpci, read, byte, u8 *, &ext_pci_swap)
+-    MAKE_PCI_OPS(extpci, read, word, u16 *, &ext_pci_swap)
+-    MAKE_PCI_OPS(extpci, read, dword, u32 *, &ext_pci_swap)
+-
+-    MAKE_PCI_OPS(extpci, write, byte, u8, &ext_pci_swap)
+-    MAKE_PCI_OPS(extpci, write, word, u16, &ext_pci_swap)
+-    MAKE_PCI_OPS(extpci, write, dword, u32, &ext_pci_swap)
+-
+-struct pci_ops ddb5476_ext_pci_ops = {
+-	extpci_read_config_byte,
+-	extpci_read_config_word,
+-	extpci_read_config_dword,
+-	extpci_write_config_byte,
+-	extpci_write_config_word,
+-	extpci_write_config_dword
+-};
+diff -Naur linux-2.6.17.orig/arch/mips/pci/ops-ddb5476.c linux-2.6.17/arch/mips/pci/ops-ddb5476.c
+--- linux-2.6.17.orig/arch/mips/pci/ops-ddb5476.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/pci/ops-ddb5476.c	1969-12-31 16:00:00.000000000 -0800
+@@ -1,286 +0,0 @@
+-/*
+- * Copyright 2001 MontaVista Software Inc.
+- * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
+- *
+- * arch/mips/ddb5xxx/ddb5476/pci_ops.c
+- *     Define the pci_ops for DB5477.
+- *
+- * Much of the code is derived from the original DDB5074 port by
+- * Geert Uytterhoeven <geert@sonycom.com>
+- *
+- * This program is free software; you can redistribute  it and/or modify it
+- * under  the terms of  the GNU General  Public License as published by the
+- * Free Software Foundation;  either version 2 of the  License, or (at your
+- * option) any later version.
+- *
+- */
+-#include <linux/pci.h>
+-#include <linux/kernel.h>
+-#include <linux/types.h>
+-
+-#include <asm/addrspace.h>
+-#include <asm/debug.h>
+-
+-#include <asm/ddb5xxx/ddb5xxx.h>
+-
+-/*
+- * config_swap structure records what set of pdar/pmr are used
+- * to access pci config space.  It also provides a place hold the
+- * original values for future restoring.
+- */
+-struct pci_config_swap {
+-	u32 pdar;
+-	u32 pmr;
+-	u32 config_base;
+-	u32 config_size;
+-	u32 pdar_backup;
+-	u32 pmr_backup;
+-};
+-
+-/*
+- * On DDB5476, we have one set of swap registers
+- */
+-struct pci_config_swap ext_pci_swap = {
+-	DDB_PCIW0,
+-	DDB_PCIINIT0,
+-	DDB_PCI_CONFIG_BASE,
+-	DDB_PCI_CONFIG_SIZE
+-};
+-
+-static int pci_config_workaround = 1;
+-
+-/*
+- * access config space
+- */
+-static inline u32 ddb_access_config_base(struct pci_config_swap *swap, u32 bus,	/* 0 means top level bus */
+-					 u32 slot_num)
+-{
+-	u32 pci_addr = 0;
+-	u32 pciinit_offset = 0;
+-	u32 virt_addr = swap->config_base;
+-	u32 option;
+-
+-	if (pci_config_workaround) {
+-		/* [jsun] work around Vrc5476 controller itself, returnning
+-		 * slot 0 essentially makes vrc5476 invisible
+-		 */
+-		if (slot_num == 12)
+-			slot_num = 0;
+-
+-#if 0
+-		/* BUG : skip P2P bridge for now */
+-		if (slot_num == 5)
+-			slot_num = 0;
+-#endif
+-
+-	} else {
+-		/* now we have to be hornest, returning the true
+-		 * PCI config headers for vrc5476
+-		 */
+-		if (slot_num == 12) {
+-			swap->pdar_backup = ddb_in32(swap->pdar);
+-			swap->pmr_backup = ddb_in32(swap->pmr);
+-			return DDB_BASE + DDB_PCI_BASE;
+-		}
+-	}
+-
+-	/* minimum pdar (window) size is 2MB */
+-	db_assert(swap->config_size >= (2 << 20));
+-
+-	db_assert(slot_num < (1 << 5));
+-	db_assert(bus < (1 << 8));
+-
+-	/* backup registers */
+-	swap->pdar_backup = ddb_in32(swap->pdar);
+-	swap->pmr_backup = ddb_in32(swap->pmr);
+-
+-	/* set the pdar (pci window) register */
+-	ddb_set_pdar(swap->pdar, swap->config_base, swap->config_size, 32,	/* 32 bit wide */
+-		     0,		/* not on local memory bus */
+-		     0);	/* not visible from PCI bus (N/A) */
+-
+-	/*
+-	 * calcuate the absolute pci config addr;
+-	 * according to the spec, we start scanning from adr:11 (0x800)
+-	 */
+-	if (bus == 0) {
+-		/* type 0 config */
+-		pci_addr = 0x800 << slot_num;
+-	} else {
+-		/* type 1 config */
+-		pci_addr = (bus << 16) | (slot_num << 11);
+-		/* panic("ddb_access_config_base: we don't support type 1 config Yet"); */
+-	}
+-
+-	/*
+-	 * if pci_addr is less than pci config window size,  we set
+-	 * pciinit_offset to 0 and adjust the virt_address.
+-	 * Otherwise we will try to adjust pciinit_offset.
+-	 */
+-	if (pci_addr < swap->config_size) {
+-		virt_addr = KSEG1ADDR(swap->config_base + pci_addr);
+-		pciinit_offset = 0;
+-	} else {
+-		db_assert((pci_addr & (swap->config_size - 1)) == 0);
+-		virt_addr = KSEG1ADDR(swap->config_base);
+-		pciinit_offset = pci_addr;
+-	}
+-
+-	/* set the pmr register */
+-	option = DDB_PCI_ACCESS_32;
+-	if (bus != 0)
+-		option |= DDB_PCI_CFGTYPE1;
+-	ddb_set_pmr(swap->pmr, DDB_PCICMD_CFG, pciinit_offset, option);
+-
+-	return virt_addr;
+-}
+-
+-static inline void ddb_close_config_base(struct pci_config_swap *swap)
+-{
+-	ddb_out32(swap->pdar, swap->pdar_backup);
+-	ddb_out32(swap->pmr, swap->pmr_backup);
+-}
+-
+-static int read_config_dword(struct pci_config_swap *swap,
+-			     struct pci_dev *dev, u32 where, u32 * val)
+-{
+-	u32 bus, slot_num, func_num;
+-	u32 base;
+-
+-	db_assert((where & 3) == 0);
+-	db_assert(where < (1 << 8));
+-
+-	/* check if the bus is top-level */
+-	if (dev->bus->parent != NULL) {
+-		bus = dev->bus->number;
+-		db_assert(bus != 0);
+-	} else {
+-		bus = 0;
+-	}
+-
+-	slot_num = PCI_SLOT(dev->devfn);
+-	func_num = PCI_FUNC(dev->devfn);
+-	base = ddb_access_config_base(swap, bus, slot_num);
+-	*val = *(volatile u32 *) (base + (func_num << 8) + where);
+-	ddb_close_config_base(swap);
+-	return PCIBIOS_SUCCESSFUL;
+-}
+-
+-static int read_config_word(struct pci_config_swap *swap,
+-			    struct pci_dev *dev, u32 where, u16 * val)
+-{
+-	int status;
+-	u32 result;
+-
+-	db_assert((where & 1) == 0);
+-
+-	status = read_config_dword(swap, dev, where & ~3, &result);
+-	if (where & 2)
+-		result >>= 16;
+-	*val = result & 0xffff;
+-	return status;
+-}
+-
+-static int read_config_byte(struct pci_config_swap *swap,
+-			    struct pci_dev *dev, u32 where, u8 * val)
+-{
+-	int status;
+-	u32 result;
+-
+-	status = read_config_dword(swap, dev, where & ~3, &result);
+-	if (where & 1)
+-		result >>= 8;
+-	if (where & 2)
+-		result >>= 16;
+-	*val = result & 0xff;
+-	return status;
+-}
+-
+-static int write_config_dword(struct pci_config_swap *swap,
+-			      struct pci_dev *dev, u32 where, u32 val)
+-{
+-	u32 bus, slot_num, func_num;
+-	u32 base;
+-
+-	db_assert((where & 3) == 0);
+-	db_assert(where < (1 << 8));
+-
+-	/* check if the bus is top-level */
+-	if (dev->bus->parent != NULL) {
+-		bus = dev->bus->number;
+-		db_assert(bus != 0);
+-	} else {
+-		bus = 0;
+-	}
+-
+-	slot_num = PCI_SLOT(dev->devfn);
+-	func_num = PCI_FUNC(dev->devfn);
+-	base = ddb_access_config_base(swap, bus, slot_num);
+-	*(volatile u32 *) (base + (func_num << 8) + where) = val;
+-	ddb_close_config_base(swap);
+-	return PCIBIOS_SUCCESSFUL;
+-}
+-
+-static int write_config_word(struct pci_config_swap *swap,
+-			     struct pci_dev *dev, u32 where, u16 val)
+-{
+-	int status, shift = 0;
+-	u32 result;
+-
+-	db_assert((where & 1) == 0);
+-
+-	status = read_config_dword(swap, dev, where & ~3, &result);
+-	if (status != PCIBIOS_SUCCESSFUL)
+-		return status;
+-
+-	if (where & 2)
+-		shift += 16;
+-	result &= ~(0xffff << shift);
+-	result |= val << shift;
+-	return write_config_dword(swap, dev, where & ~3, result);
+-}
+-
+-static int write_config_byte(struct pci_config_swap *swap,
+-			     struct pci_dev *dev, u32 where, u8 val)
+-{
+-	int status, shift = 0;
+-	u32 result;
+-
+-	status = read_config_dword(swap, dev, where & ~3, &result);
+-	if (status != PCIBIOS_SUCCESSFUL)
+-		return status;
+-
+-	if (where & 2)
+-		shift += 16;
+-	if (where & 1)
+-		shift += 8;
+-	result &= ~(0xff << shift);
+-	result |= val << shift;
+-	return write_config_dword(swap, dev, where & ~3, result);
+-}
+-
+-#define	MAKE_PCI_OPS(prefix, rw, unitname, unittype, pciswap) \
+-static int prefix##_##rw##_config_##unitname(struct pci_dev *dev, int where, unittype val) \
+-{ \
+-     return rw##_config_##unitname(pciswap, \
+-                                   dev, \
+-                                   where, \
+-                                   val); \
+-}
+-
+-MAKE_PCI_OPS(extpci, read, byte, u8 *, &ext_pci_swap)
+-    MAKE_PCI_OPS(extpci, read, word, u16 *, &ext_pci_swap)
+-    MAKE_PCI_OPS(extpci, read, dword, u32 *, &ext_pci_swap)
+-
+-    MAKE_PCI_OPS(extpci, write, byte, u8, &ext_pci_swap)
+-    MAKE_PCI_OPS(extpci, write, word, u16, &ext_pci_swap)
+-    MAKE_PCI_OPS(extpci, write, dword, u32, &ext_pci_swap)
+-
+-struct pci_ops ddb5476_ext_pci_ops = {
+-	extpci_read_config_byte,
+-	extpci_read_config_word,
+-	extpci_read_config_dword,
+-	extpci_write_config_byte,
+-	extpci_write_config_word,
+-	extpci_write_config_dword
+-};
+diff -Naur linux-2.6.17.orig/arch/mips/pci/ops-emma2rh.c linux-2.6.17/arch/mips/pci/ops-emma2rh.c
+--- linux-2.6.17.orig/arch/mips/pci/ops-emma2rh.c	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/arch/mips/pci/ops-emma2rh.c	2006-06-19 18:16:13.000000000 -0700
+@@ -0,0 +1,186 @@
++/*
++ *  arch/mips/pci/ops-emma2rh.c
++ *      This file defines the PCI operation for EMMA2RH.
++ *
++ *  Copyright (C) NEC Electronics Corporation 2004-2006
++ *
++ *  This file is based on the arch/mips/pci/ops-vr41xx.c
++ *
++ *	Copyright 2001 MontaVista Software Inc.
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License as published by
++ *  the Free Software Foundation; either version 2 of the License, or
++ *  (at your option) any later version.
++ *
++ *  This program is distributed in the hope that it will be useful,
++ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *  GNU General Public License for more details.
++ *
++ *  You should have received a copy of the GNU General Public License
++ *  along with this program; if not, write to the Free Software
++ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
++ */
++
++#include <linux/config.h>
++#include <linux/pci.h>
++#include <linux/kernel.h>
++#include <linux/types.h>
++
++#include <asm/addrspace.h>
++#include <asm/debug.h>
++
++#include <asm/emma2rh/emma2rh.h>
++
++#define RTABORT (0x1<<9)
++#define RMABORT (0x1<<10)
++#define EMMA2RH_PCI_SLOT_NUM 9	/* 0000:09.0 is final PCI device */
++
++/*
++ * access config space
++ */
++
++static int check_args(struct pci_bus *bus, u32 devfn, u32 * bus_num)
++{
++	/* check if the bus is top-level */
++	if (bus->parent != NULL) {
++		*bus_num = bus->number;
++		db_assert(bus_num != 0);
++	} else
++		*bus_num = 0;
++
++	if (*bus_num == 0) {
++		/* Type 0 */
++		if (PCI_SLOT(devfn) >= 10)
++			return PCIBIOS_DEVICE_NOT_FOUND;
++	} else {
++		/* Type 1 */
++		if ((*bus_num >= 64) || (PCI_SLOT(devfn) >= 16))
++			return PCIBIOS_DEVICE_NOT_FOUND;
++	}
++	return 0;
++}
++
++static inline int set_pci_configuration_address(unsigned char bus_num,
++						unsigned int devfn, int where)
++{
++	u32 config_win0;
++
++	emma2rh_out32(EMMA2RH_PCI_INT, ~RMABORT);
++	if (bus_num == 0)
++		/*
++		 * Type 0 configuration
++		 */
++		config_win0 = (1 << (22 + PCI_SLOT(devfn))) | (5 << 9);
++	else
++		/*
++		 * Type 1 configuration
++		 */
++		config_win0 = (bus_num << 26) | (PCI_SLOT(devfn) << 22) |
++		    (1 << 15) | (5 << 9);
++
++	emma2rh_out32(EMMA2RH_PCI_IWIN0_CTR, config_win0);
++
++	return 0;
++}
++
++static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where,
++			   int size, uint32_t * val)
++{
++	u32 bus_num;
++	u32 base = KSEG1ADDR(EMMA2RH_PCI_CONFIG_BASE);
++	u32 backup_win0;
++	u32 data;
++
++	*val = 0xffffffffU;
++
++	if (check_args(bus, devfn, &bus_num) == PCIBIOS_DEVICE_NOT_FOUND)
++		return PCIBIOS_DEVICE_NOT_FOUND;
++
++	backup_win0 = emma2rh_in32(EMMA2RH_PCI_IWIN0_CTR);
++
++	if (set_pci_configuration_address(bus_num, devfn, where) < 0)
++		return PCIBIOS_DEVICE_NOT_FOUND;
++
++	data =
++	    *(volatile u32 *)(base + (PCI_FUNC(devfn) << 8) +
++			      (where & 0xfffffffc));
++
++	switch (size) {
++	case 1:
++		*val = (data >> ((where & 3) << 3)) & 0xffU;
++		break;
++	case 2:
++		*val = (data >> ((where & 2) << 3)) & 0xffffU;
++		break;
++	case 4:
++		*val = data;
++		break;
++	default:
++		emma2rh_out32(EMMA2RH_PCI_IWIN0_CTR, backup_win0);
++		return PCIBIOS_FUNC_NOT_SUPPORTED;
++	}
++
++	emma2rh_out32(EMMA2RH_PCI_IWIN0_CTR, backup_win0);
++
++	if (emma2rh_in32(EMMA2RH_PCI_INT) & RMABORT)
++		return PCIBIOS_DEVICE_NOT_FOUND;
++
++	return PCIBIOS_SUCCESSFUL;
++}
++
++static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where,
++			    int size, u32 val)
++{
++	u32 bus_num;
++	u32 base = KSEG1ADDR(EMMA2RH_PCI_CONFIG_BASE);
++	u32 backup_win0;
++	u32 data;
++	int shift;
++
++	if (check_args(bus, devfn, &bus_num) == PCIBIOS_DEVICE_NOT_FOUND)
++		return PCIBIOS_DEVICE_NOT_FOUND;
++
++	backup_win0 = emma2rh_in32(EMMA2RH_PCI_IWIN0_CTR);
++
++	if (set_pci_configuration_address(bus_num, devfn, where) < 0)
++		return PCIBIOS_DEVICE_NOT_FOUND;
++
++	/* read modify write */
++	data =
++	    *(volatile u32 *)(base + (PCI_FUNC(devfn) << 8) +
++			      (where & 0xfffffffc));
++
++	switch (size) {
++	case 1:
++		shift = (where & 3) << 3;
++		data &= ~(0xffU << shift);
++		data |= ((val & 0xffU) << shift);
++		break;
++	case 2:
++		shift = (where & 2) << 3;
++		data &= ~(0xffffU << shift);
++		data |= ((val & 0xffffU) << shift);
++		break;
++	case 4:
++		data = val;
++		break;
++	default:
++		emma2rh_out32(EMMA2RH_PCI_IWIN0_CTR, backup_win0);
++		return PCIBIOS_FUNC_NOT_SUPPORTED;
++	}
++	*(volatile u32 *)(base + (PCI_FUNC(devfn) << 8) +
++			  (where & 0xfffffffc)) = data;
++
++	emma2rh_out32(EMMA2RH_PCI_IWIN0_CTR, backup_win0);
++	if (emma2rh_in32(EMMA2RH_PCI_INT) & RMABORT)
++		return PCIBIOS_DEVICE_NOT_FOUND;
++
++	return PCIBIOS_SUCCESSFUL;
++}
++
++struct pci_ops emma2rh_pci_ops = {
++	.read = pci_config_read,
++	.write = pci_config_write,
++};
+diff -Naur linux-2.6.17.orig/arch/mips/pci/ops-it8172.c linux-2.6.17/arch/mips/pci/ops-it8172.c
+--- linux-2.6.17.orig/arch/mips/pci/ops-it8172.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/pci/ops-it8172.c	2006-06-19 18:16:13.000000000 -0700
+@@ -50,30 +50,28 @@
+ static struct resource pci_mem_resource_1;
+ 
+ static struct resource pci_io_resource = {
+-	"io pci IO space",
+-	0x14018000,
+-	0x17FFFFFF,
+-	IORESOURCE_IO
++	.start	= 0x14018000,
++	.end	= 0x17FFFFFF,
++	.name	= "io pci IO space",
++	.flags	= IORESOURCE_IO
+ };
+ 
+ static struct resource pci_mem_resource_0 = {
+-	"ext pci memory space 0/1",
+-	0x10101000,
+-	0x13FFFFFF,
+-	IORESOURCE_MEM,
+-	&pci_mem_resource_0,
+-	NULL,
+-	&pci_mem_resource_1
++	.start	= 0x10101000,
++	.end	= 0x13FFFFFF,
++	.name	= "ext pci memory space 0/1",
++	.flags	= IORESOURCE_MEM,
++	.parent	= &pci_mem_resource_0,
++	.sibling = NULL,
++	.child	= &pci_mem_resource_1
+ };
+ 
+ static struct resource pci_mem_resource_1 = {
+-	"ext pci memory space 2/3",
+-	0x1A000000,
+-	0x1FBFFFFF,
+-	IORESOURCE_MEM,
+-	&pci_mem_resource_0,
+-	NULL,
+-	NULL
++	.start	= 0x1A000000,
++	.end	= 0x1FBFFFFF,
++	.name	= "ext pci memory space 2/3",
++	.flags	= IORESOURCE_MEM,
++	.parent	= &pci_mem_resource_0
+ };
+ 
+ extern struct pci_ops it8172_pci_ops;
+diff -Naur linux-2.6.17.orig/arch/mips/pci/ops-sni.c linux-2.6.17/arch/mips/pci/ops-sni.c
+--- linux-2.6.17.orig/arch/mips/pci/ops-sni.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/pci/ops-sni.c	2006-06-19 18:16:13.000000000 -0700
+@@ -47,13 +47,13 @@
+ 
+ 	switch (size) {
+ 	case 1:
+-		*val = *(volatile  u8 *) (PCIMT_CONFIG_DATA + (reg & 3));
++		*val = inb(PCIMT_CONFIG_DATA + (reg & 3));
+ 		break;
+ 	case 2:
+-		*val = *(volatile u16 *) (PCIMT_CONFIG_DATA + (reg & 2));
++		*val = inw(PCIMT_CONFIG_DATA + (reg & 2));
+ 		break;
+ 	case 4:
+-		*val = *(volatile u32 *) PCIMT_CONFIG_DATA;
++		*val = inl(PCIMT_CONFIG_DATA);
+ 		break;
+ 	}
+ 
+@@ -70,13 +70,13 @@
+ 
+ 	switch (size) {
+ 	case 1:
+-		*(volatile  u8 *) (PCIMT_CONFIG_DATA + (reg & 3)) = val;
++		outb (val, PCIMT_CONFIG_DATA + (reg & 3));
+ 		break;
+ 	case 2:
+-		*(volatile u16 *) (PCIMT_CONFIG_DATA + (reg & 2)) = val;
++		outw (val, PCIMT_CONFIG_DATA + (reg & 2));
+ 		break;
+ 	case 4:
+-		*(volatile u32 *) PCIMT_CONFIG_DATA = val;
++		outl (val, PCIMT_CONFIG_DATA);
+ 		break;
+ 	}
+ 
+diff -Naur linux-2.6.17.orig/arch/mips/pci/ops-titan.c linux-2.6.17/arch/mips/pci/ops-titan.c
+--- linux-2.6.17.orig/arch/mips/pci/ops-titan.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/pci/ops-titan.c	2006-06-19 18:16:13.000000000 -0700
+@@ -26,8 +26,19 @@
+ #include <linux/pci.h>
+ #include <linux/kernel.h>
+ 
+-#include <asm/titan_dep.h>
++#include <asm/pci.h>
++#include <asm/io.h>
++#include <asm/rm9k-ocd.h>
+ 
++/*
++ * PCI specific defines
++ */
++#define	TITAN_PCI_0_CONFIG_ADDRESS	0x780
++#define	TITAN_PCI_0_CONFIG_DATA		0x784
++
++/*
++ * Titan PCI Config Read Byte
++ */
+ static int titan_read_config(struct pci_bus *bus, unsigned int devfn, int reg,
+ 	int size, u32 * val)
+ {
+@@ -43,8 +54,8 @@
+ 
+ 
+ 	/* start the configuration cycle */
+-	TITAN_WRITE(TITAN_PCI_0_CONFIG_ADDRESS, address);
+-	tmp = TITAN_READ(TITAN_PCI_0_CONFIG_DATA) >> ((reg & 3) << 3);
++	ocd_writel(address, TITAN_PCI_0_CONFIG_ADDRESS);
++	tmp = ocd_readl(TITAN_PCI_0_CONFIG_DATA) >> ((reg & 3) << 3);
+ 
+ 	switch (size) {
+ 	case 1:
+@@ -71,20 +82,20 @@
+ 		(reg & 0xfc) | 0x80000000;
+ 
+ 	/* start the configuration cycle */
+-	TITAN_WRITE(TITAN_PCI_0_CONFIG_ADDRESS, address);
++	ocd_writel(address, TITAN_PCI_0_CONFIG_ADDRESS);
+ 
+ 	/* write the data */
+ 	switch (size) {
+ 	case 1:
+-		TITAN_WRITE_8(TITAN_PCI_0_CONFIG_DATA + (~reg & 0x3), val);
++		ocd_writeb(val, TITAN_PCI_0_CONFIG_DATA + (~reg & 0x3));
+ 		break;
+ 
+ 	case 2:
+-		TITAN_WRITE_16(TITAN_PCI_0_CONFIG_DATA + (~reg & 0x2), val);
++		ocd_writew(val, TITAN_PCI_0_CONFIG_DATA + (~reg & 0x2));
+ 		break;
+ 
+ 	case 4:
+-		TITAN_WRITE(TITAN_PCI_0_CONFIG_DATA, val);
++		ocd_writel(val, TITAN_PCI_0_CONFIG_DATA);
+ 		break;
+ 	}
+ 
+diff -Naur linux-2.6.17.orig/arch/mips/pci/pci.c linux-2.6.17/arch/mips/pci/pci.c
+--- linux-2.6.17.orig/arch/mips/pci/pci.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/pci/pci.c	2006-06-19 18:16:13.000000000 -0700
+@@ -76,11 +76,6 @@
+ 	res->start = start;
+ }
+ 
+-struct pci_controller * __init alloc_pci_controller(void)
+-{
+-	return alloc_bootmem(sizeof(struct pci_controller));
+-}
+-
+ void __init register_pci_controller(struct pci_controller *hose)
+ {
+ 	*hose_tail = hose;
+diff -Naur linux-2.6.17.orig/arch/mips/pci/pci-ddb5074.c linux-2.6.17/arch/mips/pci/pci-ddb5074.c
+--- linux-2.6.17.orig/arch/mips/pci/pci-ddb5074.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/pci/pci-ddb5074.c	1969-12-31 16:00:00.000000000 -0800
+@@ -1,79 +0,0 @@
+-#include <linux/kernel.h>
+-#include <linux/init.h>
+-#include <linux/types.h>
+-#include <linux/pci.h>
+-
+-#include <asm/debug.h>
+-
+-#include <asm/ddb5xxx/ddb5xxx.h>
+-
+-static struct resource extpci_io_resource = {
+-	"pci IO space",
+-	0x1000,			/* leave some room for ISA bus */
+-	DDB_PCI_IO_SIZE - 1,
+-	IORESOURCE_IO
+-};
+-
+-static struct resource extpci_mem_resource = {
+-	"pci memory space",
+-	DDB_PCI_MEM_BASE + 0x00100000,	/* leave 1 MB for RTC */
+-	DDB_PCI_MEM_BASE + DDB_PCI_MEM_SIZE - 1,
+-	IORESOURCE_MEM
+-};
+-
+-extern struct pci_ops ddb5476_ext_pci_ops;
+-
+-struct pci_controller ddb5476_controller = {
+-	.pci_ops	= &ddb5476_ext_pci_ops,
+-	.io_resource	= &extpci_io_resource,
+-	.mem_resource	= &extpci_mem_resource,
+-};
+-
+-#define     PCI_EXT_INTA        8
+-#define     PCI_EXT_INTB        9
+-#define     PCI_EXT_INTC        10
+-#define     PCI_EXT_INTD        11
+-#define     PCI_EXT_INTE        12
+-
+-#define     MAX_SLOT_NUM        14
+-
+-static unsigned char irq_map[MAX_SLOT_NUM] = {
+-  [ 0] = nile4_to_irq(PCI_EXT_INTE),
+-  [ 1] = nile4_to_irq(PCI_EXT_INTA),
+-  [ 2] = nile4_to_irq(PCI_EXT_INTA),
+-  [ 3] = nile4_to_irq(PCI_EXT_INTB),
+-  [ 4] = nile4_to_irq(PCI_EXT_INTC),
+-  [ 5] = nile4_to_irq(NILE4_INT_UART),
+-  [10] = nile4_to_irq(PCI_EXT_INTE),
+-  [13] = nile4_to_irq(PCI_EXT_INTE),
+-};
+-
+-int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+-{
+-	return irq_map[slot];
+-}
+-
+-/* Do platform specific device initialization at pci_enable_device() time */
+-int pcibios_plat_dev_init(struct pci_dev *dev)
+-{
+-	return 0;
+-}
+-
+-void __init ddb_pci_reset_bus(void)
+-{
+-	u32 temp;
+-
+-	/*
+-	 * I am not sure about the "official" procedure, the following
+-	 * steps work as far as I know:
+-	 * We first set PCI cold reset bit (bit 31) in PCICTRL-H.
+-	 * Then we clear the PCI warm reset bit (bit 30) to 0 in PCICTRL-H.
+-	 * The same is true for both PCI channels.
+-	 */
+-	temp = ddb_in32(DDB_PCICTRL + 4);
+-	temp |= 0x80000000;
+-	ddb_out32(DDB_PCICTRL + 4, temp);
+-	temp &= ~0xc0000000;
+-	ddb_out32(DDB_PCICTRL + 4, temp);
+-
+-}
+diff -Naur linux-2.6.17.orig/arch/mips/pci/pci-ddb5476.c linux-2.6.17/arch/mips/pci/pci-ddb5476.c
+--- linux-2.6.17.orig/arch/mips/pci/pci-ddb5476.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/pci/pci-ddb5476.c	1969-12-31 16:00:00.000000000 -0800
+@@ -1,93 +0,0 @@
+-#include <linux/kernel.h>
+-#include <linux/init.h>
+-#include <linux/types.h>
+-#include <linux/pci.h>
+-
+-#include <asm/debug.h>
+-
+-#include <asm/ddb5xxx/ddb5xxx.h>
+-
+-static struct resource extpci_io_resource = {
+-	"pci IO space",
+-	0x1000,			/* leave some room for ISA bus */
+-	DDB_PCI_IO_SIZE - 1,
+-	IORESOURCE_IO
+-};
+-
+-static struct resource extpci_mem_resource = {
+-	"pci memory space",
+-	DDB_PCI_MEM_BASE + 0x00100000,	/* leave 1 MB for RTC */
+-	DDB_PCI_MEM_BASE + DDB_PCI_MEM_SIZE - 1,
+-	IORESOURCE_MEM
+-};
+-
+-extern struct pci_ops ddb5476_ext_pci_ops;
+-
+-struct pci_controller ddb5476_controller = {
+-	.pci_ops	= &ddb5476_ext_pci_ops,
+-	.io_resource	= &extpci_io_resource,
+-	.mem_resource	= &extpci_mem_resource
+-};
+-
+-
+-/*
+- * we fix up irqs based on the slot number.
+- * The first entry is at AD:11.
+- *
+- * This does not work for devices on sub-buses yet.
+- */
+-
+-/*
+- * temporary
+- */
+-
+-#define		PCI_EXT_INTA		8
+-#define		PCI_EXT_INTB		9
+-#define		PCI_EXT_INTC		10
+-#define		PCI_EXT_INTD		11
+-#define		PCI_EXT_INTE		12
+-
+-/*
+- * based on ddb5477 manual page 11
+- */
+-#define		MAX_SLOT_NUM		21
+-static unsigned char irq_map[MAX_SLOT_NUM] = {
+- [ 2] = 9,				/* AD:13	USB		*/
+- [ 3] = 10,				/* AD:14	PMU		*/
+- [ 5] = 0,				/* AD:16 	P2P bridge	*/
+- [ 6] = nile4_to_irq(PCI_EXT_INTB),	/* AD:17			*/
+- [ 7] =	nile4_to_irq(PCI_EXT_INTC),	/* AD:18			*/
+- [ 8] = nile4_to_irq(PCI_EXT_INTD),	/* AD:19			*/
+- [ 9] = nile4_to_irq(PCI_EXT_INTA),	/* AD:20			*/
+- [13] = 14,				/* AD:24 HD controller, M5229	*/
+-};
+-
+-int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+-{
+-	return irq_map[slot];
+-}
+-
+-/* Do platform specific device initialization at pci_enable_device() time */
+-int pcibios_plat_dev_init(struct pci_dev *dev)
+-{
+-	return 0;
+-}
+-
+-void __init ddb_pci_reset_bus(void)
+-{
+-	u32 temp;
+-
+-	/*
+-	 * I am not sure about the "official" procedure, the following
+-	 * steps work as far as I know:
+-	 * We first set PCI cold reset bit (bit 31) in PCICTRL-H.
+-	 * Then we clear the PCI warm reset bit (bit 30) to 0 in PCICTRL-H.
+-	 * The same is true for both PCI channels.
+-	 */
+-	temp = ddb_in32(DDB_PCICTRL + 4);
+-	temp |= 0x80000000;
+-	ddb_out32(DDB_PCICTRL + 4, temp);
+-	temp &= ~0xc0000000;
+-	ddb_out32(DDB_PCICTRL + 4, temp);
+-
+-}
+diff -Naur linux-2.6.17.orig/arch/mips/pci/pci-ddb5477.c linux-2.6.17/arch/mips/pci/pci-ddb5477.c
+--- linux-2.6.17.orig/arch/mips/pci/pci-ddb5477.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/pci/pci-ddb5477.c	2006-06-19 18:16:13.000000000 -0700
+@@ -22,31 +22,31 @@
+ #include <asm/ddb5xxx/ddb5xxx.h>
+ 
+ static struct resource extpci_io_resource = {
+-	"ext pci IO space",
+-	DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE + 0x4000,
+-	DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI0_IO_SIZE - 1,
+-	IORESOURCE_IO
++	.start	= DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE + 0x4000,
++	.end	= DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI0_IO_SIZE - 1,
++	.name	= "ext pci IO space",
++	.flags	= IORESOURCE_IO
+ };
+ 
+ static struct resource extpci_mem_resource = {
+-	"ext pci memory space",
+-	DDB_PCI0_MEM_BASE + 0x100000,
+-	DDB_PCI0_MEM_BASE + DDB_PCI0_MEM_SIZE - 1,
+-	IORESOURCE_MEM
++	.start	= DDB_PCI0_MEM_BASE + 0x100000,
++	.end	= DDB_PCI0_MEM_BASE + DDB_PCI0_MEM_SIZE - 1,
++	.name	= "ext pci memory space",
++	.flags	= IORESOURCE_MEM
+ };
+ 
+ static struct resource iopci_io_resource = {
+-	"io pci IO space",
+-	DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE,
+-	DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI1_IO_SIZE - 1,
+-	IORESOURCE_IO
++	.start	= DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE,
++	.end	= DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI1_IO_SIZE - 1,
++	.name	= "io pci IO space",
++	.flags	= IORESOURCE_IO
+ };
+ 
+ static struct resource iopci_mem_resource = {
+-	"ext pci memory space",
+-	DDB_PCI1_MEM_BASE,
+-	DDB_PCI1_MEM_BASE + DDB_PCI1_MEM_SIZE - 1,
+-	IORESOURCE_MEM
++	.start	= DDB_PCI1_MEM_BASE,
++	.end	= DDB_PCI1_MEM_BASE + DDB_PCI1_MEM_SIZE - 1,
++	.name	= "ext pci memory space",
++	.flags	= IORESOURCE_MEM
+ };
+ 
+ extern struct pci_ops ddb5477_ext_pci_ops;
+diff -Naur linux-2.6.17.orig/arch/mips/pci/pci-emma2rh.c linux-2.6.17/arch/mips/pci/pci-emma2rh.c
+--- linux-2.6.17.orig/arch/mips/pci/pci-emma2rh.c	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/arch/mips/pci/pci-emma2rh.c	2006-06-19 18:16:13.000000000 -0700
+@@ -0,0 +1,90 @@
++/*
++ *  arch/mips/pci/pci-emma2rh.c
++ *      This file defines the PCI configration.
++ *
++ *  Copyright (C) NEC Electronics Corporation 2004-2006
++ *
++ *  This file is based on the arch/mips/ddb5xxx/ddb5477/pci.c
++ *
++ *	Copyright 2001 MontaVista Software Inc.
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License as published by
++ *  the Free Software Foundation; either version 2 of the License, or
++ *  (at your option) any later version.
++ *
++ *  This program is distributed in the hope that it will be useful,
++ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *  GNU General Public License for more details.
++ *
++ *  You should have received a copy of the GNU General Public License
++ *  along with this program; if not, write to the Free Software
++ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
++ */
++
++#include <linux/config.h>
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/types.h>
++#include <linux/pci.h>
++
++#include <asm/bootinfo.h>
++#include <asm/debug.h>
++
++#include <asm/emma2rh/emma2rh.h>
++
++static struct resource pci_io_resource = {
++	.name = "pci IO space",
++	.start = EMMA2RH_PCI_IO_BASE,
++	.end = EMMA2RH_PCI_IO_BASE + EMMA2RH_PCI_IO_SIZE - 1,
++	.flags = IORESOURCE_IO,
++};
++
++static struct resource pci_mem_resource = {
++	.name = "pci memory space",
++	.start = EMMA2RH_PCI_MEM_BASE,
++	.end = EMMA2RH_PCI_MEM_BASE + EMMA2RH_PCI_MEM_SIZE - 1,
++	.flags = IORESOURCE_MEM,
++};
++
++extern struct pci_ops emma2rh_pci_ops;
++
++static struct pci_controller emma2rh_pci_controller = {
++	.pci_ops = &emma2rh_pci_ops,
++	.mem_resource = &pci_mem_resource,
++	.io_resource = &pci_io_resource,
++	.mem_offset = -0x04000000,
++	.io_offset = 0,
++};
++
++static void __init emma2rh_pci_init(void)
++{
++	/* setup PCI interface */
++	emma2rh_out32(EMMA2RH_PCI_ARBIT_CTR, 0x70f);
++
++	emma2rh_out32(EMMA2RH_PCI_IWIN0_CTR, 0x80000a18);
++	emma2rh_out32(EMMA2RH_PCI_CONFIG_BASE + PCI_COMMAND,
++		      PCI_STATUS_DEVSEL_MEDIUM | PCI_STATUS_CAP_LIST |
++		      PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
++	emma2rh_out32(EMMA2RH_PCI_CONFIG_BASE + PCI_BASE_ADDRESS_0, 0x10000000);
++	emma2rh_out32(EMMA2RH_PCI_CONFIG_BASE + PCI_BASE_ADDRESS_1, 0x00000000);
++
++	emma2rh_out32(EMMA2RH_PCI_IWIN0_CTR, 0x12000000 | 0x218);
++	emma2rh_out32(EMMA2RH_PCI_IWIN1_CTR, 0x18000000 | 0x600);
++	emma2rh_out32(EMMA2RH_PCI_INIT_ESWP, 0x00000200);
++
++	emma2rh_out32(EMMA2RH_PCI_TWIN_CTR, 0x00009200);
++	emma2rh_out32(EMMA2RH_PCI_TWIN_BADR, 0x00000000);
++	emma2rh_out32(EMMA2RH_PCI_TWIN0_DADR, 0x00000000);
++	emma2rh_out32(EMMA2RH_PCI_TWIN1_DADR, 0x00000000);
++}
++
++static int __init emma2rh_pci_setup(void)
++{
++	emma2rh_pci_init();
++	register_pci_controller(&emma2rh_pci_controller);
++	return 0;
++}
++
++arch_initcall(emma2rh_pci_setup);
+diff -Naur linux-2.6.17.orig/arch/mips/pci/pci-excite.c linux-2.6.17/arch/mips/pci/pci-excite.c
+--- linux-2.6.17.orig/arch/mips/pci/pci-excite.c	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/arch/mips/pci/pci-excite.c	2006-06-19 18:16:13.000000000 -0700
+@@ -0,0 +1,149 @@
++/*
++ *  Copyright (C) 2004 by Basler Vision Technologies AG
++ *  Author: Thomas Koeller <thomas.koeller@baslerweb.com>
++ *  Based on the PMC-Sierra Yosemite board support by Ralf Baechle.
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License as published by
++ *  the Free Software Foundation; either version 2 of the License, or
++ *  (at your option) any later version.
++ *
++ *  This program is distributed in the hope that it will be useful,
++ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *  GNU General Public License for more details.
++ *
++ *  You should have received a copy of the GNU General Public License
++ *  along with this program; if not, write to the Free Software
++ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
++ */
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/types.h>
++#include <linux/pci.h>
++#include <linux/bitops.h>
++#include <asm/rm9k-ocd.h>
++#include <excite.h>
++
++
++extern struct pci_ops titan_pci_ops;
++
++
++static struct resource
++	mem_resource = 	{
++		.name	= "PCI memory",
++		.start	= EXCITE_PHYS_PCI_MEM,
++		.end	= EXCITE_PHYS_PCI_MEM + EXCITE_SIZE_PCI_MEM - 1,
++		.flags	= IORESOURCE_MEM
++	},
++	io_resource = {
++		.name	= "PCI I/O",
++		.start	= EXCITE_PHYS_PCI_IO,
++		.end	= EXCITE_PHYS_PCI_IO + EXCITE_SIZE_PCI_IO - 1,
++		.flags	= IORESOURCE_IO
++	};
++
++
++static struct pci_controller bx_controller = {
++	.pci_ops	= &titan_pci_ops,
++	.mem_resource	= &mem_resource,
++	.mem_offset	= 0x00000000UL,
++	.io_resource	= &io_resource,
++	.io_offset	= 0x00000000UL
++};
++
++
++static char
++	iopage_failed[] __initdata   = "Cannot allocate PCI I/O page",
++	modebits_no_pci[] __initdata = "PCI is not configured in mode bits";
++
++#define RM9000x2_OCD_HTSC	0x0604
++#define RM9000x2_OCD_HTBHL	0x060c
++#define RM9000x2_OCD_PCIHRST	0x078c
++
++#define RM9K_OCD_MODEBIT1	0x00d4 /* (MODEBIT1) Mode Bit 1 */
++#define RM9K_OCD_CPHDCR		0x00f4 /* CPU-PCI/HT Data Control. */
++
++#define PCISC_FB2B 		0x00000200
++#define PCISC_MWICG		0x00000010
++#define PCISC_EMC		0x00000004
++#define PCISC_ERMA		0x00000002
++
++
++
++static int __init basler_excite_pci_setup(void)
++{
++	const unsigned int fullbars = memsize / (256 << 20);
++	unsigned int i;
++
++	/* Check modebits to see if PCI is really enabled. */
++	if (!((ocd_readl(RM9K_OCD_MODEBIT1) >> (47-32)) & 0x1))
++		panic(modebits_no_pci);
++
++	if (NULL == request_mem_region(EXCITE_PHYS_PCI_IO, EXCITE_SIZE_PCI_IO,
++				       "Memory-mapped PCI I/O page"))
++		panic(iopage_failed);
++
++	/* Enable PCI 0 as master for config cycles */
++	ocd_writel(PCISC_EMC | PCISC_ERMA, RM9000x2_OCD_HTSC);
++
++
++	/* Set up latency timer */
++	ocd_writel(0x8008, RM9000x2_OCD_HTBHL);
++
++	/*  Setup host IO and Memory space */
++	ocd_writel((EXCITE_PHYS_PCI_IO >> 4) | 1, LKB7);
++	ocd_writel(((EXCITE_SIZE_PCI_IO >> 4) & 0x7fffff00) - 0x100, LKM7);
++	ocd_writel((EXCITE_PHYS_PCI_MEM >> 4) | 1, LKB8);
++	ocd_writel(((EXCITE_SIZE_PCI_MEM >> 4) & 0x7fffff00) - 0x100, LKM8);
++
++	/* Set up PCI BARs to map all installed memory */
++	for (i = 0; i < 6; i++) {
++		const unsigned int bar = 0x610 + i * 4;
++
++	     	if (i < fullbars) {
++			ocd_writel(0x10000000 * i, bar);
++			ocd_writel(0x01000000 * i, bar + 0x140);
++			ocd_writel(0x0ffff029, bar + 0x100);
++			continue;
++		}
++
++	     	if (i == fullbars) {
++			int o;
++			u32 mask;
++
++			const unsigned long rem = memsize - i * 0x10000000;
++			if (!rem) {
++				ocd_writel(0x00000000, bar + 0x100);
++				continue;
++			}
++
++			o = ffs(rem) - 1;
++			if (rem & ~(0x1 << o))
++				o++;
++			mask = ((0x1 << o) & 0x0ffff000) - 0x1000;
++			ocd_writel(0x10000000 * i, bar);
++			ocd_writel(0x01000000 * i, bar + 0x140);
++			ocd_writel(0x00000029 | mask, bar + 0x100);
++			continue;
++		}
++
++		ocd_writel(0x00000000, bar + 0x100);
++	}
++
++	/* Finally, enable the PCI interupt */
++#if USB_IRQ > 7
++	set_c0_intcontrol(1 << USB_IRQ);
++#else
++	set_c0_status(1 << (USB_IRQ + 8));
++#endif
++
++	ioport_resource.start = EXCITE_PHYS_PCI_IO;
++	ioport_resource.end = EXCITE_PHYS_PCI_IO + EXCITE_SIZE_PCI_IO - 1;
++	set_io_port_base((unsigned long) ioremap_nocache(EXCITE_PHYS_PCI_IO, EXCITE_SIZE_PCI_IO));
++	register_pci_controller(&bx_controller);
++	return 0;
++}
++
++
++arch_initcall(basler_excite_pci_setup);
+diff -Naur linux-2.6.17.orig/arch/mips/pci/pci-ip27.c linux-2.6.17/arch/mips/pci/pci-ip27.c
+--- linux-2.6.17.orig/arch/mips/pci/pci-ip27.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/pci/pci-ip27.c	2006-06-19 18:16:13.000000000 -0700
+@@ -40,297 +40,7 @@
+ struct bridge_controller *irq_to_bridge[MAX_PCI_BUSSES * MAX_DEVICES_PER_PCIBUS];
+ int irq_to_slot[MAX_PCI_BUSSES * MAX_DEVICES_PER_PCIBUS];
+ 
+-/*
+- * The Bridge ASIC supports both type 0 and type 1 access.  Type 1 is
+- * not really documented, so right now I can't write code which uses it.
+- * Therefore we use type 0 accesses for now even though they won't work
+- * correcly for PCI-to-PCI bridges.
+- *
+- * The function is complicated by the ultimate brokeness of the IOC3 chip
+- * which is used in SGI systems.  The IOC3 can only handle 32-bit PCI
+- * accesses and does only decode parts of it's address space.
+- */
+-
+-static int pci_conf0_read_config(struct pci_bus *bus, unsigned int devfn,
+-				 int where, int size, u32 * value)
+-{
+-	struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
+-	bridge_t *bridge = bc->base;
+-	int slot = PCI_SLOT(devfn);
+-	int fn = PCI_FUNC(devfn);
+-	volatile void *addr;
+-	u32 cf, shift, mask;
+-	int res;
+-
+-	addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID];
+-	if (get_dbe(cf, (u32 *) addr))
+-		return PCIBIOS_DEVICE_NOT_FOUND;
+-
+-	/*
+-	 * IOC3 is fucked fucked beyond believe ...  Don't even give the
+-	 * generic PCI code a chance to look at it for real ...
+-	 */
+-	if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
+-		goto oh_my_gawd;
+-
+-	addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)];
+-
+-	if (size == 1)
+-		res = get_dbe(*value, (u8 *) addr);
+-	else if (size == 2)
+-		res = get_dbe(*value, (u16 *) addr);
+-	else
+-		res = get_dbe(*value, (u32 *) addr);
+-
+-	return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
+-
+-oh_my_gawd:
+-
+-	/*
+-	 * IOC3 is fucked fucked beyond believe ...  Don't even give the
+-	 * generic PCI code a chance to look at the wrong register.
+-	 */
+-	if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) {
+-		*value = 0;
+-		return PCIBIOS_SUCCESSFUL;
+-	}
+-
+-	/*
+-	 * IOC3 is fucked fucked beyond believe ...  Don't try to access
+-	 * anything but 32-bit words ...
+-	 */
+-	addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
+-
+-	if (get_dbe(cf, (u32 *) addr))
+-		return PCIBIOS_DEVICE_NOT_FOUND;
+-
+-	shift = ((where & 3) << 3);
+-	mask = (0xffffffffU >> ((4 - size) << 3));
+-	*value = (cf >> shift) & mask;
+-
+-	return PCIBIOS_SUCCESSFUL;
+-}
+-
+-static int pci_conf1_read_config(struct pci_bus *bus, unsigned int devfn,
+-				 int where, int size, u32 * value)
+-{
+-	struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
+-	bridge_t *bridge = bc->base;
+-	int busno = bus->number;
+-	int slot = PCI_SLOT(devfn);
+-	int fn = PCI_FUNC(devfn);
+-	volatile void *addr;
+-	u32 cf, shift, mask;
+-	int res;
+-
+-	bridge->b_pci_cfg = (busno << 16) | (slot << 11);
+-	addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID];
+-	if (get_dbe(cf, (u32 *) addr))
+-		return PCIBIOS_DEVICE_NOT_FOUND;
+-
+-	/*
+-	 * IOC3 is fucked fucked beyond believe ...  Don't even give the
+-	 * generic PCI code a chance to look at it for real ...
+-	 */
+-	if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
+-		goto oh_my_gawd;
+-
+-	bridge->b_pci_cfg = (busno << 16) | (slot << 11);
+-	addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))];
+-
+-	if (size == 1)
+-		res = get_dbe(*value, (u8 *) addr);
+-	else if (size == 2)
+-		res = get_dbe(*value, (u16 *) addr);
+-	else
+-		res = get_dbe(*value, (u32 *) addr);
+-
+-	return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
+-
+-oh_my_gawd:
+-
+-	/*
+-	 * IOC3 is fucked fucked beyond believe ...  Don't even give the
+-	 * generic PCI code a chance to look at the wrong register.
+-	 */
+-	if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) {
+-		*value = 0;
+-		return PCIBIOS_SUCCESSFUL;
+-	}
+-
+-	/*
+-	 * IOC3 is fucked fucked beyond believe ...  Don't try to access
+-	 * anything but 32-bit words ...
+-	 */
+-	bridge->b_pci_cfg = (busno << 16) | (slot << 11);
+-	addr = &bridge->b_type1_cfg.c[(fn << 8) | where];
+-
+-	if (get_dbe(cf, (u32 *) addr))
+-		return PCIBIOS_DEVICE_NOT_FOUND;
+-
+-	shift = ((where & 3) << 3);
+-	mask = (0xffffffffU >> ((4 - size) << 3));
+-	*value = (cf >> shift) & mask;
+-
+-	return PCIBIOS_SUCCESSFUL;
+-}
+-
+-static int pci_read_config(struct pci_bus *bus, unsigned int devfn,
+-			   int where, int size, u32 * value)
+-{
+-	if (bus->number > 0)
+-		return pci_conf1_read_config(bus, devfn, where, size, value);
+-
+-	return pci_conf0_read_config(bus, devfn, where, size, value);
+-}
+-
+-static int pci_conf0_write_config(struct pci_bus *bus, unsigned int devfn,
+-				  int where, int size, u32 value)
+-{
+-	struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
+-	bridge_t *bridge = bc->base;
+-	int slot = PCI_SLOT(devfn);
+-	int fn = PCI_FUNC(devfn);
+-	volatile void *addr;
+-	u32 cf, shift, mask, smask;
+-	int res;
+-
+-	addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID];
+-	if (get_dbe(cf, (u32 *) addr))
+-		return PCIBIOS_DEVICE_NOT_FOUND;
+-
+-	/*
+-	 * IOC3 is fucked fucked beyond believe ...  Don't even give the
+-	 * generic PCI code a chance to look at it for real ...
+-	 */
+-	if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
+-		goto oh_my_gawd;
+-
+-	addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)];
+-
+-	if (size == 1) {
+-		res = put_dbe(value, (u8 *) addr);
+-	} else if (size == 2) {
+-		res = put_dbe(value, (u16 *) addr);
+-	} else {
+-		res = put_dbe(value, (u32 *) addr);
+-	}
+-
+-	if (res)
+-		return PCIBIOS_DEVICE_NOT_FOUND;
+-
+-	return PCIBIOS_SUCCESSFUL;
+-
+-oh_my_gawd:
+-
+-	/*
+-	 * IOC3 is fucked fucked beyond believe ...  Don't even give the
+-	 * generic PCI code a chance to touch the wrong register.
+-	 */
+-	if ((where >= 0x14 && where < 0x40) || (where >= 0x48))
+-		return PCIBIOS_SUCCESSFUL;
+-
+-	/*
+-	 * IOC3 is fucked fucked beyond believe ...  Don't try to access
+-	 * anything but 32-bit words ...
+-	 */
+-	addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
+-
+-	if (get_dbe(cf, (u32 *) addr))
+-		return PCIBIOS_DEVICE_NOT_FOUND;
+-
+-	shift = ((where & 3) << 3);
+-	mask = (0xffffffffU >> ((4 - size) << 3));
+-	smask = mask << shift;
+-
+-	cf = (cf & ~smask) | ((value & mask) << shift);
+-	if (put_dbe(cf, (u32 *) addr))
+-		return PCIBIOS_DEVICE_NOT_FOUND;
+-
+-	return PCIBIOS_SUCCESSFUL;
+-}
+-
+-static int pci_conf1_write_config(struct pci_bus *bus, unsigned int devfn,
+-				  int where, int size, u32 value)
+-{
+-	struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
+-	bridge_t *bridge = bc->base;
+-	int slot = PCI_SLOT(devfn);
+-	int fn = PCI_FUNC(devfn);
+-	int busno = bus->number;
+-	volatile void *addr;
+-	u32 cf, shift, mask, smask;
+-	int res;
+-
+-	bridge->b_pci_cfg = (busno << 16) | (slot << 11);
+-	addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID];
+-	if (get_dbe(cf, (u32 *) addr))
+-		return PCIBIOS_DEVICE_NOT_FOUND;
+-
+-	/*
+-	 * IOC3 is fucked fucked beyond believe ...  Don't even give the
+-	 * generic PCI code a chance to look at it for real ...
+-	 */
+-	if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
+-		goto oh_my_gawd;
+-
+-	addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))];
+-
+-	if (size == 1) {
+-		res = put_dbe(value, (u8 *) addr);
+-	} else if (size == 2) {
+-		res = put_dbe(value, (u16 *) addr);
+-	} else {
+-		res = put_dbe(value, (u32 *) addr);
+-	}
+-
+-	if (res)
+-		return PCIBIOS_DEVICE_NOT_FOUND;
+-
+-	return PCIBIOS_SUCCESSFUL;
+-
+-oh_my_gawd:
+-
+-	/*
+-	 * IOC3 is fucked fucked beyond believe ...  Don't even give the
+-	 * generic PCI code a chance to touch the wrong register.
+-	 */
+-	if ((where >= 0x14 && where < 0x40) || (where >= 0x48))
+-		return PCIBIOS_SUCCESSFUL;
+-
+-	/*
+-	 * IOC3 is fucked fucked beyond believe ...  Don't try to access
+-	 * anything but 32-bit words ...
+-	 */
+-	addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
+-
+-	if (get_dbe(cf, (u32 *) addr))
+-		return PCIBIOS_DEVICE_NOT_FOUND;
+-
+-	shift = ((where & 3) << 3);
+-	mask = (0xffffffffU >> ((4 - size) << 3));
+-	smask = mask << shift;
+-
+-	cf = (cf & ~smask) | ((value & mask) << shift);
+-	if (put_dbe(cf, (u32 *) addr))
+-		return PCIBIOS_DEVICE_NOT_FOUND;
+-
+-	return PCIBIOS_SUCCESSFUL;
+-}
+-
+-static int pci_write_config(struct pci_bus *bus, unsigned int devfn,
+-	int where, int size, u32 value)
+-{
+-	if (bus->number > 0)
+-		return pci_conf1_write_config(bus, devfn, where, size, value);
+-
+-	return pci_conf0_write_config(bus, devfn, where, size, value);
+-}
+-
+-static struct pci_ops bridge_pci_ops = {
+-	.read = pci_read_config,
+-	.write = pci_write_config,
+-};
++extern struct pci_ops bridge_pci_ops;
+ 
+ int __init bridge_probe(nasid_t nasid, int widget_id, int masterwid)
+ {
+@@ -370,8 +80,7 @@
+ 	bc->widget_id = widget_id;
+ 	bc->nasid = nasid;
+ 
+-	bc->baddr = (u64)masterwid << 60;
+-	bc->baddr |= (1UL << 56);	/* Barrier set */
++	bc->baddr = (u64)masterwid << 60 | PCI64_ATTR_BAR;
+ 
+ 	/*
+ 	 * point to this bridge
+diff -Naur linux-2.6.17.orig/arch/mips/pci/pci-jmr3927.c linux-2.6.17/arch/mips/pci/pci-jmr3927.c
+--- linux-2.6.17.orig/arch/mips/pci/pci-jmr3927.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/pci/pci-jmr3927.c	2006-06-19 18:16:13.000000000 -0700
+@@ -35,17 +35,17 @@
+ #include <asm/debug.h>
+ 
+ struct resource pci_io_resource = {
+-	"IO MEM",
+-	0x1000,			/* reserve regacy I/O space */
+-	0x1000 + JMR3927_PCIIO_SIZE - 1,
+-	IORESOURCE_IO
++	.name	= "IO MEM",
++	.start	= 0x1000,			/* reserve regacy I/O space */
++	.end	= 0x1000 + JMR3927_PCIIO_SIZE - 1,
++	.flags	= IORESOURCE_IO
+ };
+ 
+ struct resource pci_mem_resource = {
+-	"PCI MEM",
+-	JMR3927_PCIMEM,
+-	JMR3927_PCIMEM + JMR3927_PCIMEM_SIZE - 1,
+-	IORESOURCE_MEM
++	.name	= "PCI MEM",
++	.start	= JMR3927_PCIMEM,
++	.end	= JMR3927_PCIMEM + JMR3927_PCIMEM_SIZE - 1,
++	.flags	= IORESOURCE_MEM
+ };
+ 
+ extern struct pci_ops jmr3927_pci_ops;
+diff -Naur linux-2.6.17.orig/arch/mips/pci/pci-ocelot.c linux-2.6.17/arch/mips/pci/pci-ocelot.c
+--- linux-2.6.17.orig/arch/mips/pci/pci-ocelot.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/pci/pci-ocelot.c	2006-06-19 18:16:13.000000000 -0700
+@@ -71,13 +71,13 @@
+ }
+ 
+ static struct resource ocelot_mem_resource = {
+-	iomem_resource.start = GT_PCI_MEM_BASE;
+-	iomem_resource.end = GT_PCI_MEM_BASE + GT_PCI_MEM_BASE - 1;
++	start	= GT_PCI_MEM_BASE;
++	end	= GT_PCI_MEM_BASE + GT_PCI_MEM_BASE - 1;
+ };
+ 
+ static struct resource ocelot_io_resource = {
+-	ioport_resource.start = GT_PCI_IO_BASE;
+-	ioport_resource.end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1;
++	start	= GT_PCI_IO_BASE;
++	end	= GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1;
+ };
+ 
+ static struct pci_controller ocelot_pci_controller = {
+diff -Naur linux-2.6.17.orig/arch/mips/pci/pci-yosemite.c linux-2.6.17/arch/mips/pci/pci-yosemite.c
+--- linux-2.6.17.orig/arch/mips/pci/pci-yosemite.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/pci/pci-yosemite.c	2006-06-19 18:16:13.000000000 -0700
+@@ -14,7 +14,10 @@
+ extern struct pci_ops titan_pci_ops;
+ 
+ static struct resource py_mem_resource = {
+-	"Titan PCI MEM", 0xe0000000UL, 0xe3ffffffUL, IORESOURCE_MEM
++	.start	= 0xe0000000UL,
++	.end	= 0xe3ffffffUL,
++	.name	= "Titan PCI MEM",
++	.flags	= IORESOURCE_MEM
+ };
+ 
+ /*
+@@ -26,7 +29,10 @@
+ #define TITAN_IO_BASE	0xe8000000UL
+ 
+ static struct resource py_io_resource = {
+-	"Titan IO MEM", 0x00001000UL, TITAN_IO_SIZE - 1, IORESOURCE_IO,
++	.start	= 0x00001000UL,
++	.end	= TITAN_IO_SIZE - 1,
++	.name	= "Titan IO MEM",
++	.flags	= IORESOURCE_IO,
+ };
+ 
+ static struct pci_controller py_controller = {
+diff -Naur linux-2.6.17.orig/arch/mips/philips/pnx8550/common/pci.c linux-2.6.17/arch/mips/philips/pnx8550/common/pci.c
+--- linux-2.6.17.orig/arch/mips/philips/pnx8550/common/pci.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/philips/pnx8550/common/pci.c	2006-06-19 18:16:13.000000000 -0700
+@@ -27,17 +27,17 @@
+ #include <nand.h>
+ 
+ static struct resource pci_io_resource = {
+-	"pci IO space",
+-	(u32)(PNX8550_PCIIO + 0x1000),	/* reserve regacy I/O space */
+-	(u32)(PNX8550_PCIIO + PNX8550_PCIIO_SIZE),
+-	IORESOURCE_IO
++	.start	= PNX8550_PCIIO + 0x1000,	/* reserve regacy I/O space */
++	.end	= PNX8550_PCIIO + PNX8550_PCIIO_SIZE,
++	.name	= "pci IO space",
++	.flags	= IORESOURCE_IO
+ };
+ 
+ static struct resource pci_mem_resource = {
+-	"pci memory space",
+-	(u32)(PNX8550_PCIMEM),
+-	(u32)(PNX8550_PCIMEM + PNX8550_PCIMEM_SIZE - 1),
+-	IORESOURCE_MEM
++	.start	= PNX8550_PCIMEM,
++	.end	= PNX8550_PCIMEM + PNX8550_PCIMEM_SIZE - 1,
++	.name	= "pci memory space",
++	.flags	= IORESOURCE_MEM
+ };
+ 
+ extern struct pci_ops pnx8550_pci_ops;
+diff -Naur linux-2.6.17.orig/arch/mips/philips/pnx8550/common/setup.c linux-2.6.17/arch/mips/philips/pnx8550/common/setup.c
+--- linux-2.6.17.orig/arch/mips/philips/pnx8550/common/setup.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/philips/pnx8550/common/setup.c	2006-06-19 18:16:13.000000000 -0700
+@@ -58,10 +58,27 @@
+ extern char *prom_getcmdline(void);
+ 
+ struct resource standard_io_resources[] = {
+-	{"dma1", 0x00, 0x1f, IORESOURCE_BUSY},
+-	{"timer", 0x40, 0x5f, IORESOURCE_BUSY},
+-	{"dma page reg", 0x80, 0x8f, IORESOURCE_BUSY},
+-	{"dma2", 0xc0, 0xdf, IORESOURCE_BUSY},
++	{
++		.start	= .0x00,
++		.end	= 0x1f,
++		.name	= "dma1",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	= 0x40,
++		.end	= 0x5f,
++		.name	= "timer",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	= 0x80,
++		.end	= 0x8f,
++		.name	= "dma page reg",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	= 0xc0,
++		.end	= 0xdf,
++		.name	= "dma2",
++		.flags	= IORESOURCE_BUSY
++	},
+ };
+ 
+ #define STANDARD_IO_RESOURCES (sizeof(standard_io_resources)/sizeof(struct resource))
+@@ -82,7 +99,7 @@
+ 
+ int pnx8550_console_port = -1;
+ 
+-void __init plat_setup(void)
++void __init plat_mem_setup(void)
+ {
+ 	int i;
+ 	char* argptr;
+diff -Naur linux-2.6.17.orig/arch/mips/pmc-sierra/yosemite/setup.c linux-2.6.17/arch/mips/pmc-sierra/yosemite/setup.c
+--- linux-2.6.17.orig/arch/mips/pmc-sierra/yosemite/setup.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/pmc-sierra/yosemite/setup.c	2006-06-19 18:16:13.000000000 -0700
+@@ -218,7 +218,7 @@
+ 	py_rtc_setup();
+ }
+ 
+-void __init plat_setup(void)
++void __init plat_mem_setup(void)
+ {
+ 	board_time_init = yosemite_time_init;
+ 	late_time_init = py_late_time_init;
+diff -Naur linux-2.6.17.orig/arch/mips/qemu/Makefile linux-2.6.17/arch/mips/qemu/Makefile
+--- linux-2.6.17.orig/arch/mips/qemu/Makefile	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/qemu/Makefile	2006-06-19 18:16:13.000000000 -0700
+@@ -2,6 +2,7 @@
+ # Makefile for Qemu specific kernel interface routines under Linux.
+ #
+ 
+-obj-y		= q-firmware.o q-irq.o q-mem.o q-setup.o
++obj-y		= q-firmware.o q-irq.o q-mem.o q-setup.o q-reset.o
+ 
++obj-$(CONFIG_VT) += q-vga.o
+ obj-$(CONFIG_SMP) += q-smp.o
+diff -Naur linux-2.6.17.orig/arch/mips/qemu/q-reset.c linux-2.6.17/arch/mips/qemu/q-reset.c
+--- linux-2.6.17.orig/arch/mips/qemu/q-reset.c	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/arch/mips/qemu/q-reset.c	2006-06-19 18:16:13.000000000 -0700
+@@ -0,0 +1,34 @@
++#include <linux/config.h>
++
++#include <asm/io.h>
++#include <asm/reboot.h>
++#include <asm/cacheflush.h>
++#include <asm/qemu.h>
++
++static void qemu_machine_restart(char *command)
++{
++	volatile unsigned int *reg = (unsigned int *)QEMU_RESTART_REG;
++
++	set_c0_status(ST0_BEV | ST0_ERL);
++	change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
++	flush_cache_all();
++	write_c0_wired(0);
++	*reg = 42;
++	while (1)
++		cpu_wait();
++}
++
++static void qemu_machine_halt(void)
++{
++	volatile unsigned int *reg = (unsigned int *)QEMU_HALT_REG;
++
++	*reg = 42;
++	while (1)
++		cpu_wait();
++}
++
++void qemu_reboot_setup(void)
++{
++	_machine_restart = qemu_machine_restart;
++	_machine_halt = qemu_machine_halt;
++}
+diff -Naur linux-2.6.17.orig/arch/mips/qemu/q-setup.c linux-2.6.17/arch/mips/qemu/q-setup.c
+--- linux-2.6.17.orig/arch/mips/qemu/q-setup.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/qemu/q-setup.c	2006-06-19 18:16:13.000000000 -0700
+@@ -2,6 +2,9 @@
+ #include <asm/io.h>
+ #include <asm/time.h>
+ 
++extern void qvga_init(void);
++extern void qemu_reboot_setup(void);
++
+ #define QEMU_PORT_BASE 0xb4000000
+ 
+ const char *get_system_type(void)
+@@ -18,8 +21,13 @@
+ 	setup_irq(0, irq);
+ }
+ 
+-void __init plat_setup(void)
++void __init plat_mem_setup(void)
+ {
+ 	set_io_port_base(QEMU_PORT_BASE);
++#ifdef CONFIG_VT
++	qvga_init();
++#endif
+ 	board_timer_setup = qemu_timer_setup;
++
++	qemu_reboot_setup();
+ }
+diff -Naur linux-2.6.17.orig/arch/mips/qemu/q-vga.c linux-2.6.17/arch/mips/qemu/q-vga.c
+--- linux-2.6.17.orig/arch/mips/qemu/q-vga.c	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/arch/mips/qemu/q-vga.c	2006-06-19 18:16:13.000000000 -0700
+@@ -0,0 +1,188 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2005 by Ralf Baechle (ralf@linux-mips.org)
++ *
++ * This will eventually go into the qemu firmware.
++ */
++#include <linux/init.h>
++#include <linux/tty.h>
++#include <asm/io.h>
++#include <video/vga.h>
++
++/*
++ * This will eventually be done by the firmware; right now Linux assumes to
++ * run on the uninitialized hardware.
++ */
++#undef LOAD_VGA_FONT
++
++static unsigned char sr[8] __initdata = {	/* Sequencer */
++	0x03, 0x00, 0x03, 0x04, 0x02, 0x00, 0x00, 0x00
++};
++
++static unsigned char gr[16] __initdata= {	/* Graphics Controller */
++	0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0e, 0x00,
++	0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
++};
++
++static unsigned char ar[21] __initdata= {	/* Attribute Controller */
++	0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
++	0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
++	0x0c, 0x01, 0x07, 0x13, 0x00
++};
++
++static unsigned char cr[32] __initdata= {	/* CRT Controller */
++	0x91, 0x4f, 0x4f, 0x95, 0x57, 0x4f, 0xc0, 0x1f,
++	0x00, 0x4f, 0x0d, 0x0e, 0x02, 0x30, 0x09, 0xb0,
++	0x90, 0x83, 0x8f, 0x28, 0x1f, 0x8f, 0xc1, 0xa3,
++	0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
++};
++
++static struct rgb {
++	unsigned char r;
++	unsigned char g;
++	unsigned char b;
++} palette[16] __initdata= {
++	[ 0] = {0x00, 0x00, 0x00},
++	[ 1] = {0x00, 0x00, 0x2a},
++	[ 2] = {0x00, 0x2a, 0x00},
++	[ 3] = {0x00, 0x2a, 0x2a},
++	[ 4] = {0x2a, 0x00, 0x00},
++	[ 5] = {0x2a, 0x00, 0x2a},
++	[ 6] = {0x2a, 0x15, 0x00},
++	[ 7] = {0x2a, 0x2a, 0x2a},
++	[ 8] = {0x15, 0x15, 0x15},
++	[ 9] = {0x15, 0x15, 0x3f},
++	[10] = {0x15, 0x3f, 0x15},
++	[11] = {0x15, 0x3f, 0x3f},
++	[12] = {0x3f, 0x15, 0x15},
++	[13] = {0x3f, 0x15, 0x3f},
++	[14] = {0x3f, 0x3f, 0x15},
++	[15] = {0x3f, 0x3f, 0x3f}
++
++};
++
++void __init qvga_init_ibm(void)
++{
++	int i;
++
++	for (i = 0; i < 8; i++) {	/* Sequencer registers */
++		outb(i, 0x3c4);
++		outb(sr[i], 0x3c5);
++	}
++
++	for (i = 0; i < 16; i++) {	/* Graphics Controller registers */
++		outb(i, 0x3ce);
++		outb(gr[i], 0x3cf);
++	}
++
++	for (i = 0; i < 21; i++) {	/* Attribute Controller registers */
++		outb(i, 0x3c0);
++		outb(ar[i], 0x3c1);
++	}
++	outb(0x20, 0x3c0);		/* enable bit in *index* register */
++
++	for (i = 0; i < 32; i++) {	/* CRT Controller registers */
++		outb(i, 0x3d4);
++		outb(cr[i], 0x3d5);
++	}
++
++	for (i = 0; i < 16; i++) {	/* palette */
++		outb(i, 0x3c8);
++		outb(palette[i].r, 0x3c9);
++		outb(palette[i].g, 0x3c9);
++		outb(palette[i].b, 0x3c9);
++	}
++
++#if 1
++	 for (i = 0; i < 0x20000; i += 2)
++		*(volatile unsigned short *) (0xb00a0000 + i) = 0xaaaa;
++#endif
++}
++
++#ifdef LOAD_VGA_FONT
++#include "/home/ralf/src/qemu/qemu-mips/vgafont.h"
++
++static void __init
++qvga_load_font(unsigned char *def, unsigned int c)
++{
++	volatile void *w = (volatile void *) 0xb00a0000;
++
++	vga_wseq(NULL, 0, 1);
++	vga_wseq(NULL, 2, 4);
++	vga_wseq(NULL, 4, 7);
++	vga_wseq(NULL, 0, 3);
++	vga_wgfx(NULL, 4, 2);
++	vga_wgfx(NULL, 5, 0);
++	vga_wgfx(NULL, 6, 0);
++
++	memcpy(w, def, c);
++
++	vga_wseq(NULL, 0, 1);
++	vga_wseq(NULL, 2, 3);
++	vga_wseq(NULL, 4, 3);
++	vga_wseq(NULL, 0, 3);
++	vga_wgfx(NULL, 4, 0);
++	vga_wgfx(NULL, 5, 0x10);
++	vga_wgfx(NULL, 6, 0xe);
++}
++#endif
++
++void __init qvga_init(void)
++{
++	struct screen_info *si = &screen_info;
++	unsigned int h;
++	int i;
++
++#if LOAD_VGA_FONT
++	qvga_load_font(vgafont16, 4096);
++#endif
++
++	vga_wgfx(NULL, 5, 0x10);	/* Set odd/even mode */
++	vga_wgfx(NULL, 6, 0x0c);	/* map to offset 0xb8000, text mode */
++	vga_wseq(NULL, 2, 3);		/* Planes 0 & 1 */
++	vga_wseq(NULL, 3, 4);		/* Font offset */
++	outb(1, VGA_MIS_W);		/* set msr to MSR_COLOR_EMULATION */
++	vga_wcrt(NULL, 1, 79);		/* 80 columns */
++	vga_wcrt(NULL, 9, 15);		/* 16 pixels per character */
++	vga_wcrt(NULL, 0x0c, 0);	/* start address high 8 bit */
++	vga_wcrt(NULL, 0x0d, 0);	/* start address low 8 bit */
++	vga_wcrt(NULL, 0x13, 0x28);	/* line offset */
++	vga_wcrt(NULL, 0x07, 0x1f);	/* line compare bit 8 */
++	vga_wcrt(NULL, 0x09, 0x4f);	/* line compare bit 9 */
++	vga_wcrt(NULL, 0x18, 0xff);	/* line compare low 8 bit */
++
++	h = (25 * 16);
++	vga_wcrt(NULL, 0x12, h);
++
++	outb(7, 0x3d4);
++	outb((inb(0x3d5) & ~0x42) | ((h >> 7) & 2) | ((h >> 3) & 0x40), 0x3d5);
++
++	for (i = 0; i < 21; i++)	/* Attribute Controller */
++		vga_wattr(NULL, i, ar[i]);
++	outb(0x20, 0x3c0);		/* Set bit 5 in Attribute Controller */
++					/* index ...  VGA is so stupid I want */
++					/* to cry all day ... */
++	outb(0, VGA_PEL_IW);
++	for (i = 0; i < 16; i++) {	/* palette */
++		outb(palette[i].r, VGA_PEL_D);
++		outb(palette[i].g, VGA_PEL_D);
++		outb(palette[i].b, VGA_PEL_D);
++	}
++
++	si->orig_x		= 0; 			/* Cursor x position */
++	si->orig_y		= 0;			/* Cursor y position */
++	si->orig_video_cols	= 80;			/* Columns */
++	si->orig_video_lines	= 25;			/* Lines */
++	si->orig_video_isVGA	= VIDEO_TYPE_VGAC;	/* Card type */
++	si->orig_video_points	= 16;
++
++#if 0
++	for (i = 0; i < 80; i += 2)
++		//*(volatile unsigned short *) (0xb00b8000 + i) = 0x0100 | 'A';
++		scr_writew(0x0100 | 'A', (volatile unsigned short *) (0xb00b8000 + i));
++	while (1);
++#endif
++}
+diff -Naur linux-2.6.17.orig/arch/mips/sgi-ip22/ip22-setup.c linux-2.6.17/arch/mips/sgi-ip22/ip22-setup.c
+--- linux-2.6.17.orig/arch/mips/sgi-ip22/ip22-setup.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/sgi-ip22/ip22-setup.c	2006-06-19 18:16:13.000000000 -0700
+@@ -53,7 +53,7 @@
+ extern void ip22_be_init(void) __init;
+ extern void ip22_time_init(void) __init;
+ 
+-void __init plat_setup(void)
++void __init plat_mem_setup(void)
+ {
+ 	char *ctype;
+ 	char *cserial;
+diff -Naur linux-2.6.17.orig/arch/mips/sgi-ip27/ip27-init.c linux-2.6.17/arch/mips/sgi-ip27/ip27-init.c
+--- linux-2.6.17.orig/arch/mips/sgi-ip27/ip27-init.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/sgi-ip27/ip27-init.c	2006-06-19 18:16:13.000000000 -0700
+@@ -196,7 +196,7 @@
+ extern void ip27_time_init(void);
+ extern void ip27_reboot_setup(void);
+ 
+-void __init plat_setup(void)
++void __init plat_mem_setup(void)
+ {
+ 	hubreg_t p, e, n_mode;
+ 	nasid_t nid;
+@@ -228,7 +228,7 @@
+ 	 */
+ 	n_mode = LOCAL_HUB_L(NI_STATUS_REV_ID) & NSRI_MORENODES_MASK;
+ 	printk("Machine is in %c mode.\n", n_mode ? 'N' : 'M');
+-#ifdef CONFIG_SGI_SN0_N_MODE
++#ifdef CONFIG_SGI_SN_N_MODE
+ 	if (!n_mode)
+ 		panic("Kernel compiled for M mode.");
+ #else
+diff -Naur linux-2.6.17.orig/arch/mips/sgi-ip27/ip27-irq.c linux-2.6.17/arch/mips/sgi-ip27/ip27-irq.c
+--- linux-2.6.17.orig/arch/mips/sgi-ip27/ip27-irq.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/sgi-ip27/ip27-irq.c	2006-06-19 18:16:13.000000000 -0700
+@@ -360,7 +360,7 @@
+ 
+ static unsigned long irq_map[NR_IRQS / BITS_PER_LONG];
+ 
+-static int allocate_irqno(void)
++int allocate_irqno(void)
+ {
+ 	int irq;
+ 
+diff -Naur linux-2.6.17.orig/arch/mips/sgi-ip27/ip27-timer.c linux-2.6.17/arch/mips/sgi-ip27/ip27-timer.c
+--- linux-2.6.17.orig/arch/mips/sgi-ip27/ip27-timer.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/sgi-ip27/ip27-timer.c	2006-06-19 18:16:13.000000000 -0700
+@@ -89,11 +89,13 @@
+ }
+ #endif
+ 
++static unsigned int rt_timer_irq;
++
+ void ip27_rt_timer_interrupt(struct pt_regs *regs)
+ {
+ 	int cpu = smp_processor_id();
+ 	int cpuA = cputoslice(cpu) == 0;
+-	int irq = 9;				/* XXX Assign number */
++	unsigned int irq = rt_timer_irq;
+ 
+ 	irq_enter();
+ 	write_seqlock(&xtime_lock);
+@@ -179,13 +181,68 @@
+         return mktime(year, month, date, hour, min, sec);
+ }
+ 
++static void startup_rt_irq(unsigned int irq)
++{
++}
++
++static void shutdown_rt_irq(unsigned int irq)
++{
++}
++
++static void enable_rt_irq(unsigned int irq)
++{
++}
++
++static void disable_rt_irq(unsigned int irq)
++{
++}
++
++static void mask_and_ack_rt(unsigned int irq)
++{
++}
++
++static void end_rt_irq(unsigned int irq)
++{
++}
++
++static struct hw_interrupt_type rt_irq_type = {
++	.typename	= "SN HUB RT timer",
++	.startup	= startup_rt_irq,
++	.shutdown	= shutdown_rt_irq,
++	.enable		= enable_rt_irq,
++	.disable	= disable_rt_irq,
++	.ack		= mask_and_ack_rt,
++	.end		= end_rt_irq,
++};
++
++static struct irqaction rt_irqaction = {
++	.handler	= ip27_rt_timer_interrupt,
++	.flags		= SA_INTERRUPT,
++	.mask		= CPU_MASK_NONE,
++	.name		= "timer"
++};
++
++extern int allocate_irqno(void);
++
+ static void ip27_timer_setup(struct irqaction *irq)
+ {
++	int irqno  = allocate_irqno();
++
++	if (irqno < 0)
++		panic("Can't allocate interrupt number for timer interrupt");
++
++	irq_desc[irqno].status = IRQ_DISABLED;
++	irq_desc[irqno].action = NULL;
++	irq_desc[irqno].depth = 1;
++	irq_desc[irqno].handler = &rt_irq_type;
++
+ 	/* over-write the handler, we use our own way */
+ 	irq->handler = no_action;
+ 
+ 	/* setup irqaction */
+-//	setup_irq(IP27_TIMER_IRQ, irq);		/* XXX Can't do this yet.  */
++	irq_desc[irqno].status |= IRQ_PER_CPU;
++
++	rt_timer_irq = irqno;
+ }
+ 
+ void __init ip27_time_init(void)
+diff -Naur linux-2.6.17.orig/arch/mips/sgi-ip27/Kconfig linux-2.6.17/arch/mips/sgi-ip27/Kconfig
+--- linux-2.6.17.orig/arch/mips/sgi-ip27/Kconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/sgi-ip27/Kconfig	2006-06-19 18:16:13.000000000 -0700
+@@ -4,43 +4,42 @@
+ #	  This options adds support for userspace processes upto 16TB size.
+ #	  Normally the limit is just .5TB.
+ 
+-config SGI_SN0_N_MODE
+-	bool "IP27 N-Mode"
++choice
++	prompt "Node addressing mode"
+ 	depends on SGI_IP27
++	default SGI_SN_M_MODE
++
++config SGI_SN_M_MODE
++	bool "IP27 M-Mode"
+ 	help
+-	  The nodes of Origin 200, Origin 2000 and Onyx 2 systems can be
+-	  configured in either N-Modes which allows for more nodes or M-Mode
+-	  which allows for more memory.  Your system is most probably
+-	  running in M-Mode, so you should say N here.
+-
+-config ARCH_DISCONTIGMEM_ENABLE
+-	bool
+-	default y if SGI_IP27
+-	help
+-	  Say Y to upport efficient handling of discontiguous physical memory,
+-	  for architectures which are either NUMA (Non-Uniform Memory Access)
+-	  or have huge holes in the physical address space for other reasons.
+-	  See <file:Documentation/vm/numa> for more.
++	  The nodes of Origin, Onyx, Fuel and Tezro systems can be configured
++	  in either N-Modes which allows for more nodes or M-Mode which allows
++	  for more memory.  Your hardware is almost certainly running in
++	  M-Mode, so choose M-mode here.
+ 
+-config NUMA
+-	bool "NUMA Support"
+-	depends on SGI_IP27
++config SGI_SN_N_MODE
++	bool "IP27 N-Mode"
++	depends on EXPERIMENTAL
+ 	help
+-	  Say Y to compile the kernel to support NUMA (Non-Uniform Memory
+-	  Access).  This option is for configuring high-end multiprocessor
+-	  server machines.  If in doubt, say N.
++	  The nodes of Origin, Onyx, Fuel and Tezro systems can be configured
++	  in either N-Modes which allows for more nodes or M-Mode which allows
++	  for more memory.  Your hardware is almost certainly running in
++	  M-Mode, so choose M-mode here.
++
++endchoice
+ 
+ config MAPPED_KERNEL
+ 	bool "Mapped kernel support"
+ 	depends on SGI_IP27
+ 	help
+ 	  Change the way a Linux kernel is loaded into memory on a MIPS64
+-	  machine.  This is required in order to support text replication and
++	  machine.  This is required in order to support text replication on
+ 	  NUMA.  If you need to understand it, read the source code.
+ 
+ config REPLICATE_KTEXT
+ 	bool "Kernel text replication support"
+ 	depends on SGI_IP27
++	select MAPPED_KERNEL
+ 	help
+ 	  Say Y here to enable replicating the kernel text across multiple
+ 	  nodes in a NUMA cluster.  This trades memory for speed.
+diff -Naur linux-2.6.17.orig/arch/mips/sgi-ip32/ip32-setup.c linux-2.6.17/arch/mips/sgi-ip32/ip32-setup.c
+--- linux-2.6.17.orig/arch/mips/sgi-ip32/ip32-setup.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/sgi-ip32/ip32-setup.c	2006-06-19 18:16:13.000000000 -0700
+@@ -87,7 +87,7 @@
+ 	setup_irq(IP32_R4K_TIMER_IRQ, irq);
+ }
+ 
+-void __init plat_setup(void)
++void __init plat_mem_setup(void)
+ {
+ 	board_be_init = ip32_be_init;
+ 
+diff -Naur linux-2.6.17.orig/arch/mips/sibyte/bcm1480/time.c linux-2.6.17/arch/mips/sibyte/bcm1480/time.c
+--- linux-2.6.17.orig/arch/mips/sibyte/bcm1480/time.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/sibyte/bcm1480/time.c	2006-06-19 18:16:13.000000000 -0700
+@@ -110,17 +110,18 @@
+ 	__raw_writeq(M_SCD_TIMER_ENABLE|M_SCD_TIMER_MODE_CONTINUOUS,
+ 	      IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
+ 
+-	/*
+-	 * CPU 0 handles the global timer interrupt job
+-	 */
+ 	if (cpu == 0) {
++		/*
++		 * CPU 0 handles the global timer interrupt job
++		 */
+ 		ll_timer_interrupt(irq, regs);
+ 	}
+-
+-	/*
+-	 * every CPU should do profiling and process accouting
+-	 */
+-	ll_local_timer_interrupt(irq, regs);
++	else {
++		/*
++		 * other CPUs should just do profiling and process accounting
++		 */
++		ll_local_timer_interrupt(irq, regs);
++	}
+ }
+ 
+ /*
+diff -Naur linux-2.6.17.orig/arch/mips/sibyte/Kconfig linux-2.6.17/arch/mips/sibyte/Kconfig
+--- linux-2.6.17.orig/arch/mips/sibyte/Kconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/sibyte/Kconfig	2006-06-19 18:16:13.000000000 -0700
+@@ -3,6 +3,7 @@
+ 	select HW_HAS_PCI
+ 	select SIBYTE_HAS_LDT
+ 	select SIBYTE_SB1xxx_SOC
++	select SYS_SUPPORTS_SMP
+ 
+ config SIBYTE_BCM1120
+ 	bool
+@@ -30,11 +31,13 @@
+ 	bool
+ 	select HW_HAS_PCI
+ 	select SIBYTE_SB1xxx_SOC
++	select SYS_SUPPORTS_SMP
+ 
+ config SIBYTE_BCM1x55
+ 	bool
+ 	select HW_HAS_PCI
+ 	select SIBYTE_SB1xxx_SOC
++	select SYS_SUPPORTS_SMP
+ 
+ config SIBYTE_SB1xxx_SOC
+ 	bool
+diff -Naur linux-2.6.17.orig/arch/mips/sibyte/sb1250/irq.c linux-2.6.17/arch/mips/sibyte/sb1250/irq.c
+--- linux-2.6.17.orig/arch/mips/sibyte/sb1250/irq.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/sibyte/sb1250/irq.c	2006-06-19 18:16:13.000000000 -0700
+@@ -435,13 +435,17 @@
+ 	return lz;
+ }
+ 
++extern void sb1250_timer_interrupt(struct pt_regs *regs);
++extern void sb1250_mailbox_interrupt(struct pt_regs *regs);
++extern void sb1250_kgdb_interrupt(struct pt_regs *regs);
++
+ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
+ {
+ 	unsigned int pending;
+ 
+ #ifdef CONFIG_SIBYTE_SB1250_PROF
+ 	/* Set compare to count to silence count/compare timer interrupts */
+-	write_c0_count(read_c0_count());
++	write_c0_compare(read_c0_count());
+ #endif
+ 
+ 	/*
+@@ -482,7 +486,7 @@
+ 		 * Default...we've hit an IP[2] interrupt, which means we've
+ 		 * got to check the 1250 interrupt registers to figure out what
+ 		 * to do.  Need to detect which CPU we're on, now that
+-		 ~ smp_affinity is supported.
++		 * smp_affinity is supported.
+ 		 */
+ 		mask = __raw_readq(IOADDR(A_IMR_REGISTER(smp_processor_id(),
+ 		                              R_IMR_INTERRUPT_STATUS_BASE)));
+diff -Naur linux-2.6.17.orig/arch/mips/sibyte/swarm/setup.c linux-2.6.17/arch/mips/sibyte/swarm/setup.c
+--- linux-2.6.17.orig/arch/mips/sibyte/swarm/setup.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/sibyte/swarm/setup.c	2006-06-19 18:16:13.000000000 -0700
+@@ -72,8 +72,10 @@
+ 
+ void __init swarm_time_init(void)
+ {
++#if defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
+ 	/* Setup HPT */
+ 	sb1250_hpt_setup();
++#endif
+ }
+ 
+ void __init swarm_timer_setup(struct irqaction *irq)
+@@ -103,7 +105,7 @@
+ 	return (is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL);
+ }
+ 
+-void __init plat_setup(void)
++void __init plat_mem_setup(void)
+ {
+ #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
+ 	bcm1480_setup();
+diff -Naur linux-2.6.17.orig/arch/mips/sni/Makefile linux-2.6.17/arch/mips/sni/Makefile
+--- linux-2.6.17.orig/arch/mips/sni/Makefile	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/sni/Makefile	2006-06-19 18:16:13.000000000 -0700
+@@ -3,5 +3,6 @@
+ #
+ 
+ obj-y	 	+= irq.o pcimt_scache.o reset.o setup.o
++obj-$(CONFIG_CPU_BIG_ENDIAN) += sniprom.o
+ 
+ EXTRA_AFLAGS := $(CFLAGS)
+diff -Naur linux-2.6.17.orig/arch/mips/sni/setup.c linux-2.6.17/arch/mips/sni/setup.c
+--- linux-2.6.17.orig/arch/mips/sni/setup.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/sni/setup.c	2006-06-19 18:16:13.000000000 -0700
+@@ -21,8 +21,11 @@
+ #include <linux/fb.h>
+ #include <linux/tty.h>
+ 
++#ifdef CONFIG_ARC
+ #include <asm/arc/types.h>
+ #include <asm/sgialib.h>
++#endif
++
+ #include <asm/bcache.h>
+ #include <asm/bootinfo.h>
+ #include <asm/io.h>
+@@ -72,8 +75,7 @@
+ 
+ static void __init sni_display_setup(void)
+ {
+-#ifdef CONFIG_VT
+-#if defined(CONFIG_VGA_CONSOLE)
++#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE) && defined(CONFIG_ARC)
+ 	struct screen_info *si = &screen_info;
+ 	DISPLAY_STATUS *di;
+ 
+@@ -88,24 +90,54 @@
+ 		si->orig_video_points	= 16;
+ 	}
+ #endif
+-#endif
+ }
+ 
+ static struct resource sni_io_resource = {
+-	"PCIMT IO MEM", 0x00001000UL, 0x03bfffffUL, IORESOURCE_IO,
++	.start	= 0x00001000UL,
++	.end	= 0x03bfffffUL,
++	.name	= "PCIMT IO MEM",
++	.flags	= IORESOURCE_IO,
+ };
+ 
+ static struct resource pcimt_io_resources[] = {
+-	{ "dma1", 0x00, 0x1f, IORESOURCE_BUSY },
+-	{ "timer", 0x40, 0x5f, IORESOURCE_BUSY },
+-	{ "keyboard", 0x60, 0x6f, IORESOURCE_BUSY },
+-	{ "dma page reg", 0x80, 0x8f, IORESOURCE_BUSY },
+-	{ "dma2", 0xc0, 0xdf, IORESOURCE_BUSY },
+-	{ "PCI config data", 0xcfc, 0xcff, IORESOURCE_BUSY }
++	{
++		.start	= 0x00,
++		.end	= 0x1f,
++		.name	= "dma1",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	=  0x40,
++		.end	= 0x5f,
++		.name	= "timer",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	=  0x60,
++		.end	= 0x6f,
++		.name	= "keyboard",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	=  0x80,
++		.end	= 0x8f,
++		.name	= "dma page reg",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	=  0xc0,
++		.end	= 0xdf,
++		.name	= "dma2",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	=  0xcfc,
++		.end	= 0xcff,
++		.name	= "PCI config data",
++		.flags	= IORESOURCE_BUSY
++	}
+ };
+ 
+ static struct resource sni_mem_resource = {
+-	"PCIMT PCI MEM", 0x10000000UL, 0xffffffffUL, IORESOURCE_MEM
++	.start	= 0x10000000UL,
++	.end	= 0xffffffffUL,
++	.name	= "PCIMT PCI MEM",
++	.flags	= IORESOURCE_MEM
+ };
+ 
+ /*
+@@ -122,19 +154,72 @@
+  * 0xa0000000 - 0xffffffff (1.5GB) PCI/EISA Bus Memory
+  */
+ static struct resource pcimt_mem_resources[] = {
+-	{ "Video RAM area", 0x100a0000, 0x100bffff, IORESOURCE_BUSY },
+-	{ "ISA Reserved", 0x100c0000, 0x100fffff, IORESOURCE_BUSY },
+-	{ "PCI IO", 0x14000000, 0x17bfffff, IORESOURCE_BUSY },
+-	{ "Cache Replacement Area", 0x17c00000, 0x17ffffff, IORESOURCE_BUSY},
+-	{ "PCI INT Acknowledge", 0x1a000000, 0x1a000003, IORESOURCE_BUSY },
+-	{ "Boot PROM", 0x1fc00000, 0x1fc7ffff, IORESOURCE_BUSY},
+-	{ "Diag PROM", 0x1fc80000, 0x1fcfffff, IORESOURCE_BUSY},
+-	{ "X-Bus", 0x1fd00000, 0x1fdfffff, IORESOURCE_BUSY},
+-	{ "BIOS map", 0x1fe00000, 0x1fefffff, IORESOURCE_BUSY},
+-	{ "NVRAM / EEPROM", 0x1ff00000, 0x1ff7ffff, IORESOURCE_BUSY},
+-	{ "ASIC PCI", 0x1fff0000, 0x1fffefff, IORESOURCE_BUSY},
+-	{ "MP Agent", 0x1ffff000, 0x1fffffff, IORESOURCE_BUSY},
+-	{ "Main Memory", 0x20000000, 0x9fffffff, IORESOURCE_BUSY}
++	{
++		.start	= 0x100a0000,
++		.end	= 0x100bffff,
++		.name	= "Video RAM area",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	= 0x100c0000,
++		.end	= 0x100fffff,
++		.name	= "ISA Reserved",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	= 0x14000000,
++		.end	= 0x17bfffff,
++		.name	= "PCI IO",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	= 0x17c00000,
++		.end	= 0x17ffffff,
++		.name	= "Cache Replacement Area",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	= 0x1a000000,
++		.end	= 0x1a000003,
++		.name	= "PCI INT Acknowledge",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	= 0x1fc00000,
++		.end	= 0x1fc7ffff,
++		.name	= "Boot PROM",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	= 0x1fc80000,
++		.end	= 0x1fcfffff,
++		.name	= "Diag PROM",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	= 0x1fd00000,
++		.end	= 0x1fdfffff,
++		.name	= "X-Bus",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	= 0x1fe00000,
++		.end	= 0x1fefffff,
++		.name	= "BIOS map",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	= 0x1ff00000,
++		.end	= 0x1ff7ffff,
++		.name	= "NVRAM / EEPROM",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	= 0x1fff0000,
++		.end	= 0x1fffefff,
++		.name	= "ASIC PCI",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	= 0x1ffff000,
++		.end	= 0x1fffffff,
++		.name	= "MP Agent",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	= 0x20000000,
++		.end	= 0x9fffffff,
++		.name	= "Main Memory",
++		.flags	= IORESOURCE_BUSY
++	}
+ };
+ 
+ static void __init sni_resource_init(void)
+@@ -168,7 +253,7 @@
+ 	rtc_mips_set_time = mc146818_set_rtc_mmss;
+ }
+ 
+-void __init plat_setup(void)
++void __init plat_mem_setup(void)
+ {
+ 	sni_pcimt_detect();
+ 	sni_pcimt_sc_init();
+diff -Naur linux-2.6.17.orig/arch/mips/sni/sniprom.c linux-2.6.17/arch/mips/sni/sniprom.c
+--- linux-2.6.17.orig/arch/mips/sni/sniprom.c	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/arch/mips/sni/sniprom.c	2006-06-19 18:16:13.000000000 -0700
+@@ -0,0 +1,158 @@
++/*
++ * Big Endian PROM code for SNI RM machines
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2005-2006 Florian Lohoff (flo@rfc822.org)
++ * Copyright (C) 2005-2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
++ */
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/string.h>
++
++#include <asm/addrspace.h>
++#include <asm/sni.h>
++#include <asm/mipsprom.h>
++#include <asm/bootinfo.h>
++
++/* special SNI prom calls */
++/*
++ * This does not exist in all proms - SINIX compares
++ * the prom env variable "version" against "2.0008"
++ * or greater. If lesser it tries to probe interesting
++ * registers
++ */
++#define PROM_GET_MEMCONF	58
++
++#define PROM_VEC		(u64 *)CKSEG1ADDR(0x1fc00000)
++#define PROM_ENTRY(x)		(PROM_VEC + (x))
++
++
++#undef DEBUG
++#ifdef DEBUG
++#define DBG_PRINTF(x...)     prom_printf(x)
++#else
++#define DBG_PRINTF(x...)
++#endif
++
++static int *(*__prom_putchar)(int)        = (int *(*)(int))PROM_ENTRY(PROM_PUTCHAR);
++static char *(*__prom_getenv)(char *)     = (char *(*)(char *))PROM_ENTRY(PROM_GETENV);
++static void (*__prom_get_memconf)(void *) = (void (*)(void *))PROM_ENTRY(PROM_GET_MEMCONF);
++
++char *prom_getenv (char *s)
++{
++	return __prom_getenv(s);
++}
++
++void prom_printf(char *fmt, ...)
++{
++	va_list args;
++	char ppbuf[1024];
++	char *bptr;
++
++	va_start(args, fmt);
++	vsprintf(ppbuf, fmt, args);
++
++	bptr = ppbuf;
++
++	while (*bptr != 0) {
++		if (*bptr == '\n')
++			__prom_putchar('\r');
++
++		__prom_putchar(*bptr++);
++	}
++	va_end(args);
++}
++
++unsigned long prom_free_prom_memory(void)
++{
++	return 0;
++}
++
++/*
++ * /proc/cpuinfo system type
++ *
++ */
++static const char *systype = "Unknown";
++const char *get_system_type(void)
++{
++	return systype;
++}
++
++#define SNI_IDPROM_BASE                0xbff00000
++#define SNI_IDPROM_MEMSIZE             (SNI_IDPROM_BASE+0x28)  /* Memsize in 16MB quantities */
++#define SNI_IDPROM_BRDTYPE             (SNI_IDPROM_BASE+0x29)  /* Board Type */
++#define SNI_IDPROM_CPUTYPE             (SNI_IDPROM_BASE+0x30)  /* CPU Type */
++
++#define SNI_IDPROM_SIZE	0x1000
++
++#ifdef DEBUG
++static void sni_idprom_dump(void)
++{
++	int	i;
++
++	prom_printf("SNI IDProm dump (first 128byte):\n");
++	for(i=0;i<128;i++) {
++		if (i%16 == 0)
++			prom_printf("%04x ", i);
++
++		prom_printf("%02x ", *(unsigned char *) (SNI_IDPROM_BASE+i));
++
++		if (i%16 == 15)
++			prom_printf("\n");
++	}
++}
++#endif
++
++static void sni_mem_init(void )
++{
++	int i, memsize;
++	struct membank {
++	        u32		size;
++	        u32		base;
++	        u32		size2;
++	        u32		pad1;
++	        u32		pad2;
++	} memconf[8];
++
++	/* MemSIZE from prom in 16MByte chunks */
++	memsize=*((unsigned char *) SNI_IDPROM_MEMSIZE) * 16;
++
++	DBG_PRINTF("IDProm memsize: %lu MByte\n", memsize);
++
++	/* get memory bank layout from prom */
++	__prom_get_memconf(&memconf);
++
++	DBG_PRINTF("prom_get_mem_conf memory configuration:\n");
++	for(i=0;i<8 && memconf[i].size;i++) {
++		prom_printf("Bank%d: %08x @ %08x\n", i,
++			memconf[i].size, memconf[i].base);
++		add_memory_region(memconf[i].base, memconf[i].size, BOOT_MEM_RAM);
++	}
++}
++
++void __init prom_init(void)
++{
++	int argc = fw_arg0;
++	char **argv = (void *)fw_arg1;
++	unsigned int sni_brd_type = *(unsigned char *) SNI_IDPROM_BRDTYPE;
++	int i;
++
++	DBG_PRINTF("Found SNI brdtype %02x\n", sni_brd_type);
++
++#ifdef DEBUG
++	sni_idprom_dump();
++#endif
++	sni_mem_init();
++
++	/* copy prom cmdline parameters to kernel cmdline */
++	for (i = 1; i < argc; i++) {
++		strcat(arcs_cmdline, argv[i]);
++		if (i < (argc - 1))
++			strcat(arcs_cmdline, " ");
++	}
++}
++
+diff -Naur linux-2.6.17.orig/arch/mips/tx4927/common/tx4927_setup.c linux-2.6.17/arch/mips/tx4927/common/tx4927_setup.c
+--- linux-2.6.17.orig/arch/mips/tx4927/common/tx4927_setup.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/tx4927/common/tx4927_setup.c	2006-06-19 18:16:13.000000000 -0700
+@@ -64,7 +64,7 @@
+ }
+ 
+ 
+-void __init plat_setup(void)
++void __init plat_mem_setup(void)
+ {
+ 	board_time_init = tx4927_time_init;
+ 	board_timer_setup = tx4927_timer_setup;
+diff -Naur linux-2.6.17.orig/arch/mips/tx4938/common/setup.c linux-2.6.17/arch/mips/tx4938/common/setup.c
+--- linux-2.6.17.orig/arch/mips/tx4938/common/setup.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/tx4938/common/setup.c	2006-06-19 18:16:13.000000000 -0700
+@@ -61,7 +61,7 @@
+ }
+ 
+ void __init
+-plat_setup(void)
++plat_mem_setup(void)
+ {
+ 	board_time_init = tx4938_time_init;
+ 	board_timer_setup = tx4938_timer_setup;
+diff -Naur linux-2.6.17.orig/arch/mips/tx4938/toshiba_rbtx4938/setup.c linux-2.6.17/arch/mips/tx4938/toshiba_rbtx4938/setup.c
+--- linux-2.6.17.orig/arch/mips/tx4938/toshiba_rbtx4938/setup.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/tx4938/toshiba_rbtx4938/setup.c	2006-06-19 18:16:13.000000000 -0700
+@@ -664,7 +664,10 @@
+ 
+ static char pcode_str[8];
+ static struct resource tx4938_reg_resource = {
+-	pcode_str, TX4938_REG_BASE, TX4938_REG_BASE+TX4938_REG_SIZE, IORESOURCE_MEM
++	.start	= TX4938_REG_BASE,
++	.end	= TX4938_REG_BASE + TX4938_REG_SIZE,
++	.name	= pcode_str,
++	.flags	= IORESOURCE_MEM
+ };
+ 
+ void __init tx4938_board_setup(void)
+diff -Naur linux-2.6.17.orig/arch/mips/vr41xx/common/init.c linux-2.6.17/arch/mips/vr41xx/common/init.c
+--- linux-2.6.17.orig/arch/mips/vr41xx/common/init.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/vr41xx/common/init.c	2006-06-19 18:16:13.000000000 -0700
+@@ -58,7 +58,7 @@
+ 	board_timer_setup = setup_timer_irq;
+ }
+ 
+-void __init plat_setup(void)
++void __init plat_mem_setup(void)
+ {
+ 	vr41xx_calculate_clock_frequency();
+ 
+diff -Naur linux-2.6.17.orig/arch/mips/vr41xx/Kconfig linux-2.6.17/arch/mips/vr41xx/Kconfig
+--- linux-2.6.17.orig/arch/mips/vr41xx/Kconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/arch/mips/vr41xx/Kconfig	2006-06-19 18:16:13.000000000 -0700
+@@ -4,7 +4,6 @@
+ 	select DMA_NONCOHERENT
+ 	select IRQ_CPU
+ 	select ISA
+-	select SYS_HAS_CPU_VR41XX
+ 	select SYS_SUPPORTS_32BIT_KERNEL
+ 	select SYS_SUPPORTS_LITTLE_ENDIAN
+ 
+@@ -14,18 +13,15 @@
+ 	select DMA_NONCOHERENT
+ 	select IRQ_CPU
+ 	select ISA
+-	select SYS_HAS_CPU_VR41XX
+ 	select SYS_SUPPORTS_32BIT_KERNEL
+ 	select SYS_SUPPORTS_LITTLE_ENDIAN
+ 
+ config NEC_CMBVR4133
+ 	bool "Support for NEC CMB-VR4133"
+ 	depends on MACH_VR41XX
+-	select CPU_VR41XX
+ 	select DMA_NONCOHERENT
+ 	select IRQ_CPU
+ 	select HW_HAS_PCI
+-	select SYS_HAS_CPU_VR41XX
+ 	select SYS_SUPPORTS_32BIT_KERNEL
+ 	select SYS_SUPPORTS_LITTLE_ENDIAN
+ 
+@@ -41,7 +37,6 @@
+ 	select DMA_NONCOHERENT
+ 	select HW_HAS_PCI
+ 	select IRQ_CPU
+-	select SYS_HAS_CPU_VR41XX
+ 	select SYS_SUPPORTS_32BIT_KERNEL
+ 	select SYS_SUPPORTS_LITTLE_ENDIAN
+ 	help
+@@ -74,7 +69,6 @@
+ 	select DMA_NONCOHERENT
+ 	select HW_HAS_PCI
+ 	select IRQ_CPU
+-	select SYS_HAS_CPU_VR41XX
+ 	select SYS_SUPPORTS_32BIT_KERNEL
+ 	select SYS_SUPPORTS_LITTLE_ENDIAN
+ 
+@@ -84,7 +78,6 @@
+ 	select DMA_NONCOHERENT
+ 	select HW_HAS_PCI
+ 	select IRQ_CPU
+-	select SYS_HAS_CPU_VR41XX
+ 	select SYS_SUPPORTS_32BIT_KERNEL
+ 	select SYS_SUPPORTS_LITTLE_ENDIAN
+ 
+diff -Naur linux-2.6.17.orig/Documentation/feature-removal-schedule.txt linux-2.6.17/Documentation/feature-removal-schedule.txt
+--- linux-2.6.17.orig/Documentation/feature-removal-schedule.txt	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/Documentation/feature-removal-schedule.txt	2006-06-19 18:16:13.000000000 -0700
+@@ -147,16 +147,6 @@
+ 
+ ---------------------------
+ 
+-What:	au1x00_uart driver
+-When:	January 2006
+-Why:	The 8250 serial driver now has the ability to deal with the differences
+-	between the standard 8250 family of UARTs and their slightly strange
+-	brother on Alchemy SOCs.  The loss of features is not considered an
+-	issue.
+-Who:	Ralf Baechle <ralf@linux-mips.org>
+-
+----------------------------
+-
+ What:   eepro100 network driver
+ When:   January 2007
+ Why:    replaced by the e100 driver
+@@ -212,15 +202,6 @@
+ 
+ ---------------------------
+ 
+-What:	Support for NEC DDB5074 and DDB5476 evaluation boards.
+-When:	June 2006
+-Why:	Board specific code doesn't build anymore since ~2.6.0 and no
+-	users have complained indicating there is no more need for these
+-	boards.  This should really be considered a last call.
+-Who:	Ralf Baechle <ralf@linux-mips.org>
+-
+----------------------------
+-
+ What:	USB driver API moves to EXPORT_SYMBOL_GPL
+ When:	Febuary 2008
+ Files:	include/linux/usb.h, drivers/usb/core/driver.c
+diff -Naur linux-2.6.17.orig/drivers/char/au1000_gpio.c linux-2.6.17/drivers/char/au1000_gpio.c
+--- linux-2.6.17.orig/drivers/char/au1000_gpio.c	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/drivers/char/au1000_gpio.c	2006-06-19 18:16:13.000000000 -0700
+@@ -0,0 +1,266 @@
++/*
++ * FILE NAME au1000_gpio.c
++ *
++ * BRIEF MODULE DESCRIPTION
++ *  Driver for Alchemy Au1000 GPIO.
++ *
++ *  Author: MontaVista Software, Inc.  <source@mvista.com>
++ *          Steve Longerbeam <stevel@mvista.com>
++ *
++ * Copyright 2001 MontaVista Software Inc.
++ *
++ *  This program is free software; you can redistribute  it and/or modify it
++ *  under  the terms of  the GNU General  Public License as published by the
++ *  Free Software Foundation;  either version 2 of the  License, or (at your
++ *  option) any later version.
++ *
++ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
++ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
++ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
++ *  NO  EVENT  SHALL   THE AUTHOR  BE	LIABLE FOR ANY   DIRECT, INDIRECT,
++ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
++ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
++ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
++ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
++ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
++ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ *  You should have received a copy of the  GNU General Public License along
++ *  with this program; if not, write  to the Free Software Foundation, Inc.,
++ *  675 Mass Ave, Cambridge, MA 02139, USA.
++ */
++
++#include <linux/module.h>
++#include <linux/config.h>
++#include <linux/types.h>
++#include <linux/kernel.h>
++#include <linux/miscdevice.h>
++#include <linux/init.h>
++#include <asm/uaccess.h>
++#include <asm/io.h>
++#include <asm/au1000.h>
++#include <asm/au1000_gpio.h>
++
++#define VERSION "0.01"
++
++static const struct {
++	u32 active_hi;
++	u32 avail_mask;
++} pinfunc_to_avail[15] = {
++	{1,  0x7<<16},   // 0  = SSI0     / GPIO[18:16]
++	{-1, 0},         // 1  = AC97     / SSI1
++	{1,  1<<19},     // 2  = IRDA     / GPIO19
++	{1,  1<<20},     // 3  = UART0    / GPIO20
++	{1,  0x1f<<24},  // 4  = NIC2     / GPIO[28:24]
++	{1,  0x7<<29},   // 5  = I2S      / GPIO[31:29]
++	{0,  1<<8},      // 6  = I2SDI    / GPIO8
++	{0,  0x3f<<9},   // 7  = UART3    / GPIO[14:9]
++	{0,  1<<15},     // 8  = IRFIRSEL / GPIO15
++	{0,  1<<2},      // 9  = EXTCLK0 or OSC / GPIO2
++	{0,  1<<3},      // 10 = EXTCLK1  / GPIO3
++	{0,  1<<6},      // 11 = SMROMCKE / GPIO6
++	{1,  1<<21},     // 12 = UART1    / GPIO21
++	{1,  1<<22},     // 13 = UART2    / GPIO22
++	{1,  1<<23}      // 14 = UART3    / GPIO23
++};
++
++	
++u32 get_au1000_avail_gpio_mask(void)
++{
++	int i;
++	u32 pinfunc = inl(SYS_PINFUNC);
++	u32 avail_mask = 0; // start with no gpio available
++
++	// first, check for GPIO's reprogrammed as peripheral pins
++	for (i=0; i<15; i++) {
++		if (pinfunc_to_avail[i].active_hi < 0)
++			continue;
++		if (!(pinfunc_to_avail[i].active_hi ^
++		      ((pinfunc & (1<<i)) ? 1:0)))
++			avail_mask |= pinfunc_to_avail[i].avail_mask;
++	}
++
++	// check for GPIO's used as interrupt sources
++	avail_mask &= ~(inl(IC1_MASKRD) &
++			(inl(IC1_CFG0RD) | inl(IC1_CFG1RD)));
++
++#ifdef CONFIG_USB_OHCI
++	avail_mask &= ~((1<<4) | (1<<11));
++#ifndef CONFIG_AU1X00_USB_DEVICE
++	avail_mask &= ~((1<<5) | (1<<13));
++#endif
++#endif
++	
++	return avail_mask;
++}
++
++
++/*
++ * Tristate the requested GPIO pins specified in data.
++ * Only available GPIOs will be tristated.
++ */
++int au1000gpio_tristate(u32 data)
++{
++	data &= get_au1000_avail_gpio_mask();
++
++	if (data)
++		outl(data, SYS_TRIOUTCLR);
++
++	return 0;
++}
++
++
++/*
++ * Return the pin state. Pins configured as outputs will return
++ * the output state, and pins configured as inputs (tri-stated)
++ * will return input pin state.
++ */
++int au1000gpio_in(u32 *data)
++{
++	*data = inl(SYS_PINSTATERD);
++	return 0;
++}
++
++
++/*
++ * Set/clear GPIO pins. Only available GPIOs will be affected.
++ */
++int au1000gpio_set(u32 data)
++{
++	data &= get_au1000_avail_gpio_mask();
++
++	if (data)
++		outl(data, SYS_OUTPUTSET);
++	return 0;
++}
++
++int au1000gpio_clear(u32 data)
++{
++	data &= get_au1000_avail_gpio_mask();
++
++	if (data)
++		outl(data, SYS_OUTPUTCLR);
++	return 0;
++}
++
++/*
++ * Output data to GPIO pins. Only available GPIOs will be affected.
++ */
++int au1000gpio_out(u32 data)
++{
++	au1000gpio_set(data);
++	au1000gpio_clear(~data);
++	return 0;
++}
++
++
++EXPORT_SYMBOL(get_au1000_avail_gpio_mask);
++EXPORT_SYMBOL(au1000gpio_tristate);
++EXPORT_SYMBOL(au1000gpio_in);
++EXPORT_SYMBOL(au1000gpio_set);
++EXPORT_SYMBOL(au1000gpio_clear);
++EXPORT_SYMBOL(au1000gpio_out);
++
++
++static int au1000gpio_open(struct inode *inode, struct file *file)
++{
++	return 0;
++}
++
++
++static int au1000gpio_release(struct inode *inode, struct file *file)
++{
++	return 0;
++}
++
++
++static int au1000gpio_ioctl(struct inode *inode, struct file *file,
++			    unsigned int cmd, unsigned long arg)
++{
++	int status;
++	u32 val;
++	
++	switch(cmd) {
++	case AU1000GPIO_IN:
++		
++		status = au1000gpio_in(&val);
++		if (status != 0)
++			return status;
++
++		return put_user(val, (u32 *)arg);
++
++	case AU1000GPIO_OUT:
++
++		if (get_user(val, (u32 *)arg)) 
++			return -EFAULT;
++
++		return au1000gpio_out(val);
++
++	case AU1000GPIO_SET:
++
++		if (get_user(val, (u32 *)arg)) 
++			return -EFAULT;
++
++		return au1000gpio_set(val);
++		
++	case AU1000GPIO_CLEAR:
++
++		if (get_user(val, (u32 *)arg)) 
++			return -EFAULT;
++
++		return au1000gpio_clear(val);
++
++	case AU1000GPIO_TRISTATE:
++
++		if (get_user(val, (u32 *)arg)) 
++			return -EFAULT;
++
++		return au1000gpio_tristate(val);
++
++	case AU1000GPIO_AVAIL_MASK:
++		
++		return put_user(get_au1000_avail_gpio_mask(),
++				(u32 *)arg);
++		
++	default:
++		return -ENOIOCTLCMD;
++
++	}
++
++	return 0;
++}
++
++
++static struct file_operations au1000gpio_fops =
++{
++	.owner		= THIS_MODULE,
++	.ioctl		= au1000gpio_ioctl,
++	.open		= au1000gpio_open,
++	.release	= au1000gpio_release,
++};
++
++
++static struct miscdevice au1000gpio_miscdev =
++{
++	MISC_DYNAMIC_MINOR,
++	"au1000_gpio",
++	&au1000gpio_fops
++};
++
++
++int __init au1000gpio_init(void)
++{
++	misc_register(&au1000gpio_miscdev);
++	printk("Au1000 gpio driver, version %s\n", VERSION);
++	return 0;
++}	
++
++
++void __exit au1000gpio_exit(void)
++{
++	misc_deregister(&au1000gpio_miscdev);
++}
++
++
++module_init(au1000gpio_init);
++module_exit(au1000gpio_exit);
+diff -Naur linux-2.6.17.orig/drivers/char/au1000_ts.c linux-2.6.17/drivers/char/au1000_ts.c
+--- linux-2.6.17.orig/drivers/char/au1000_ts.c	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/drivers/char/au1000_ts.c	2006-06-19 18:16:13.000000000 -0700
+@@ -0,0 +1,677 @@
++/*
++ *      au1000_ts.c  --  Touch screen driver for the Alchemy Au1000's
++ *                       SSI Port 0 talking to the ADS7846 touch screen
++ *                       controller.
++ *
++ * Copyright 2001 MontaVista Software Inc.
++ * Author: MontaVista Software, Inc.
++ *         	stevel@mvista.com or source@mvista.com
++ *
++ *  This program is free software; you can redistribute  it and/or modify it
++ *  under  the terms of  the GNU General  Public License as published by the
++ *  Free Software Foundation;  either version 2 of the  License, or (at your
++ *  option) any later version.
++ *
++ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
++ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
++ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
++ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
++ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
++ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
++ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
++ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
++ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
++ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ *  You should have received a copy of the  GNU General Public License along
++ *  with this program; if not, write  to the Free Software Foundation, Inc.,
++ *  675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ * Notes:
++ *
++ *  Revision history
++ *    06.27.2001  Initial version
++ */
++
++#include <linux/module.h>
++#include <linux/version.h>
++
++#include <linux/init.h>
++#include <linux/fs.h>
++#include <linux/delay.h>
++#include <linux/poll.h>
++#include <linux/string.h>
++#include <linux/ioport.h>       /* request_region */
++#include <linux/interrupt.h>    /* mark_bh */
++#include <asm/uaccess.h>        /* get_user,copy_to_user */
++#include <asm/io.h>
++#include <asm/au1000.h>
++
++#define TS_NAME "au1000-ts"
++#define TS_MAJOR 11
++
++#define PFX TS_NAME
++#define AU1000_TS_DEBUG 1
++
++#ifdef AU1000_TS_DEBUG
++#define dbg(format, arg...) printk(KERN_DEBUG PFX ": " format "\n" , ## arg)
++#else
++#define dbg(format, arg...) do {} while (0)
++#endif
++#define err(format, arg...) printk(KERN_ERR PFX ": " format "\n" , ## arg)
++#define info(format, arg...) printk(KERN_INFO PFX ": " format "\n" , ## arg)
++#define warn(format, arg...) printk(KERN_WARNING PFX ": " format "\n" , ## arg)
++
++
++// SSI Status register bit defines
++#define SSISTAT_BF    (1<<4)
++#define SSISTAT_OF    (1<<3)
++#define SSISTAT_UF    (1<<2)
++#define SSISTAT_DONE  (1<<1)
++#define SSISTAT_BUSY  (1<<0)
++
++// SSI Interrupt Pending and Enable register bit defines
++#define SSIINT_OI     (1<<3)
++#define SSIINT_UI     (1<<2)
++#define SSIINT_DI     (1<<1)
++
++// SSI Address/Data register bit defines
++#define SSIADAT_D         (1<<24)
++#define SSIADAT_ADDR_BIT  16
++#define SSIADAT_ADDR_MASK (0xff<<SSIADAT_ADDR_BIT)
++#define SSIADAT_DATA_BIT  0
++#define SSIADAT_DATA_MASK (0xfff<<SSIADAT_DATA_BIT)
++
++// SSI Enable register bit defines
++#define SSIEN_CD (1<<1)
++#define SSIEN_E  (1<<0)
++
++// SSI Config register bit defines
++#define SSICFG_AO (1<<24)
++#define SSICFG_DO (1<<23)
++#define SSICFG_ALEN_BIT 20
++#define SSICFG_ALEN_MASK (0x7<<SSICFG_ALEN_BIT)
++#define SSICFG_DLEN_BIT 16
++#define SSICFG_DLEN_MASK (0xf<<SSICFG_DLEN_BIT)
++#define SSICFG_DD (1<<11)
++#define SSICFG_AD (1<<10)
++#define SSICFG_BM_BIT 8
++#define SSICFG_BM_MASK (0x3<<SSICFG_BM_BIT)
++#define SSICFG_CE (1<<7)
++#define SSICFG_DP (1<<6)
++#define SSICFG_DL (1<<5)
++#define SSICFG_EP (1<<4)
++
++// Bus Turnaround Selection
++#define SCLK_HOLD_HIGH 0
++#define SCLK_HOLD_LOW  1
++#define SCLK_CYCLE     2
++
++/*
++ * Default config for SSI0:
++ *
++ *   - transmit MSBit first
++ *   - expect MSBit first on data receive
++ *   - address length 7 bits
++ *   - expect data length 12 bits
++ *   - do not disable Direction bit
++ *   - do not disable Address bits
++ *   - SCLK held low during bus turnaround
++ *   - Address and Data bits clocked out on falling edge of SCLK
++ *   - Direction bit high is a read, low is a write
++ *   - Direction bit precedes Address bits
++ *   - Active low enable signal
++ */
++
++#define DEFAULT_SSI_CONFIG \
++    (SSICFG_AO | SSICFG_DO | (6<<SSICFG_ALEN_BIT) | (11<<SSICFG_DLEN_BIT) |\
++    (SCLK_HOLD_LOW<<SSICFG_BM_BIT) | SSICFG_DP | SSICFG_EP)
++
++
++// ADS7846 Control Byte bit defines
++#define ADS7846_ADDR_BIT  4
++#define ADS7846_ADDR_MASK (0x7<<ADS7846_ADDR_BIT)
++#define   ADS7846_MEASURE_X  (0x5<<ADS7846_ADDR_BIT)
++#define   ADS7846_MEASURE_Y  (0x1<<ADS7846_ADDR_BIT)
++#define   ADS7846_MEASURE_Z1 (0x3<<ADS7846_ADDR_BIT)
++#define   ADS7846_MEASURE_Z2 (0x4<<ADS7846_ADDR_BIT)
++#define ADS7846_8BITS     (1<<3)
++#define ADS7846_12BITS    0
++#define ADS7846_SER       (1<<2)
++#define ADS7846_DFR       0
++#define ADS7846_PWR_BIT   0
++#define   ADS7846_PD      0
++#define   ADS7846_ADC_ON  (0x1<<ADS7846_PWR_BIT)
++#define   ADS7846_REF_ON  (0x2<<ADS7846_PWR_BIT)
++#define   ADS7846_REF_ADC_ON (0x3<<ADS7846_PWR_BIT)
++
++#define MEASURE_12BIT_X \
++    (ADS7846_MEASURE_X | ADS7846_12BITS | ADS7846_DFR | ADS7846_PD)
++#define MEASURE_12BIT_Y \
++    (ADS7846_MEASURE_Y | ADS7846_12BITS | ADS7846_DFR | ADS7846_PD)
++#define MEASURE_12BIT_Z1 \
++    (ADS7846_MEASURE_Z1 | ADS7846_12BITS | ADS7846_DFR | ADS7846_PD)
++#define MEASURE_12BIT_Z2 \
++    (ADS7846_MEASURE_Z2 | ADS7846_12BITS | ADS7846_DFR | ADS7846_PD)
++
++typedef enum {
++	IDLE = 0,
++	ACQ_X,
++	ACQ_Y,
++	ACQ_Z1,
++	ACQ_Z2
++} acq_state_t;
++
++/* +++++++++++++ Lifted from include/linux/h3600_ts.h ++++++++++++++*/
++typedef struct {
++	unsigned short pressure;  // touch pressure
++	unsigned short x;         // calibrated X
++	unsigned short y;         // calibrated Y
++	unsigned short millisecs; // timestamp of this event
++} TS_EVENT;
++
++typedef struct {
++	int xscale;
++	int xtrans;
++	int yscale;
++	int ytrans;
++	int xyswap;
++} TS_CAL;
++
++/* Use 'f' as magic number */
++#define IOC_MAGIC  'f'
++
++#define TS_GET_RATE             _IO(IOC_MAGIC, 8)
++#define TS_SET_RATE             _IO(IOC_MAGIC, 9)
++#define TS_GET_CAL              _IOR(IOC_MAGIC, 10, TS_CAL)
++#define TS_SET_CAL              _IOW(IOC_MAGIC, 11, TS_CAL)
++
++/* +++++++++++++ Done lifted from include/linux/h3600_ts.h +++++++++*/
++
++
++#define EVENT_BUFSIZE 128
++
++/*
++ * Which pressure equation to use from ADS7846 datasheet.
++ * The first equation requires knowing only the X plate
++ * resistance, but needs 4 measurements (X, Y, Z1, Z2).
++ * The second equation requires knowing both X and Y plate
++ * resistance, but only needs 3 measurements (X, Y, Z1).
++ * The second equation is preferred because of the shorter
++ * acquisition time required.
++ */
++enum {
++	PRESSURE_EQN_1 = 0,
++	PRESSURE_EQN_2
++};
++
++
++/*
++ * The touch screen's X and Y plate resistances, used by
++ * pressure equations.
++ */
++#define DEFAULT_X_PLATE_OHMS 580
++#define DEFAULT_Y_PLATE_OHMS 580
++
++/*
++ * Pen up/down pressure resistance thresholds.
++ *
++ * FIXME: these are bogus and will have to be found empirically.
++ *
++ * These are hysteresis points. If pen state is up and pressure
++ * is greater than pen-down threshold, pen transitions to down.
++ * If pen state is down and pressure is less than pen-up threshold,
++ * pen transitions to up. If pressure is in-between, pen status
++ * doesn't change.
++ *
++ * This wouldn't be needed if PENIRQ* from the ADS7846 were
++ * routed to an interrupt line on the Au1000. This would issue
++ * an interrupt when the panel is touched.
++ */
++#define DEFAULT_PENDOWN_THRESH_OHMS 100
++#define DEFAULT_PENUP_THRESH_OHMS    80
++
++typedef struct {
++	int baudrate;
++	u32 clkdiv;
++	acq_state_t acq_state;            // State of acquisition state machine
++	int x_raw, y_raw, z1_raw, z2_raw; // The current raw acquisition values
++	TS_CAL cal;                       // Calibration values
++	// The X and Y plate resistance, needed to calculate pressure
++	int x_plate_ohms, y_plate_ohms;
++	// pressure resistance at which pen is considered down/up
++	int pendown_thresh_ohms;
++	int penup_thresh_ohms;
++	int pressure_eqn;                 // eqn to use for pressure calc
++	int pendown;                      // 1 = pen is down, 0 = pen is up
++	TS_EVENT event_buf[EVENT_BUFSIZE];// The event queue
++	int nextIn, nextOut;
++	int event_count;
++	struct fasync_struct *fasync;     // asynch notification
++	struct timer_list acq_timer;      // Timer for triggering acquisitions
++	wait_queue_head_t wait;           // read wait queue
++	spinlock_t lock;
++	struct tq_struct chug_tq;
++} au1000_ts_t;
++
++static au1000_ts_t au1000_ts;
++
++
++static inline u32
++calc_clkdiv(int baud)
++{
++	u32 sys_busclk =
++		(get_au1000_speed() / (int)(inl(PM_POWERUP_CONTROL)&0x03) + 2);
++	return (sys_busclk / (2 * baud)) - 1;
++}
++
++static inline int
++calc_baudrate(u32 clkdiv)
++{
++	u32 sys_busclk =
++		(get_au1000_speed() / (int)(inl(PM_POWERUP_CONTROL)&0x03) + 2);
++	return sys_busclk / (2 * (clkdiv + 1));
++}
++
++
++/*
++ * This is a bottom-half handler that is scheduled after
++ * raw X,Y,Z1,Z2 coordinates have been acquired, and does
++ * the following:
++ *
++ *   - computes touch screen pressure resistance
++ *   - if pressure is above a threshold considered to be pen-down:
++ *         - compute calibrated X and Y coordinates
++ *         - queue a new TS_EVENT
++ *         - signal asynchronously and wake up any read
++ */
++static void
++chug_raw_data(void* private)
++{
++	au1000_ts_t* ts = (au1000_ts_t*)private;
++	TS_EVENT event;
++	int Rt, Xcal, Ycal;
++	unsigned long flags;
++
++	// timestamp this new event.
++	event.millisecs = jiffies;
++
++	// Calculate touch pressure resistance
++	if (ts->pressure_eqn == PRESSURE_EQN_2) {
++		Rt = (ts->x_plate_ohms * ts->x_raw *
++		      (4096 - ts->z1_raw)) / ts->z1_raw;
++		Rt -= (ts->y_plate_ohms * ts->y_raw);
++		Rt = (Rt + 2048) >> 12; // round up to nearest ohm
++	} else {
++		Rt = (ts->x_plate_ohms * ts->x_raw *
++		      (ts->z2_raw - ts->z1_raw)) / ts->z1_raw;
++		Rt = (Rt + 2048) >> 12; // round up to nearest ohm
++	}
++
++	// hysteresis
++	if (!ts->pendown && Rt > ts->pendown_thresh_ohms)
++		ts->pendown = 1;
++	else if (ts->pendown && Rt < ts->penup_thresh_ohms)
++		ts->pendown = 0;
++
++	if (ts->pendown) {
++		// Pen is down
++		// Calculate calibrated X,Y
++		Xcal = ((ts->cal.xscale * ts->x_raw) >> 8) + ts->cal.xtrans;
++		Ycal = ((ts->cal.yscale * ts->y_raw) >> 8) + ts->cal.ytrans;
++
++		event.x = (unsigned short)Xcal;
++		event.y = (unsigned short)Ycal;
++		event.pressure = (unsigned short)Rt;
++
++		// add this event to the event queue
++		spin_lock_irqsave(&ts->lock, flags);
++		ts->event_buf[ts->nextIn++] = event;
++		if (ts->nextIn == EVENT_BUFSIZE)
++			ts->nextIn = 0;
++		if (ts->event_count < EVENT_BUFSIZE) {
++			ts->event_count++;
++		} else {
++			// throw out the oldest event
++			if (++ts->nextOut == EVENT_BUFSIZE)
++				ts->nextOut = 0;
++		}
++		spin_unlock_irqrestore(&ts->lock, flags);
++
++		// async notify
++		if (ts->fasync)
++			kill_fasync(&ts->fasync, SIGIO, POLL_IN);
++		// wake up any read call
++		if (waitqueue_active(&ts->wait))
++			wake_up_interruptible(&ts->wait);
++	}
++}
++
++
++/*
++ * Raw X,Y,pressure acquisition timer function. This triggers
++ * the start of a new acquisition. Its duration between calls
++ * is the touch screen polling rate.
++ */
++static void
++au1000_acq_timer(unsigned long data)
++{
++	au1000_ts_t* ts = (au1000_ts_t*)data;
++	unsigned long flags;
++
++	spin_lock_irqsave(&ts->lock, flags);
++
++	// start acquisition with X coordinate
++	ts->acq_state = ACQ_X;
++	// start me up
++	outl(SSIADAT_D | (MEASURE_12BIT_X << SSIADAT_ADDR_BIT), SSI0_ADATA);
++
++	// schedule next acquire
++	ts->acq_timer.expires = jiffies + HZ / 100;
++	add_timer(&ts->acq_timer);
++
++	spin_unlock_irqrestore(&ts->lock, flags);
++}
++
++static void
++ssi0_interrupt(int irq, void *dev_id, struct pt_regs *regs)
++{
++	au1000_ts_t *ts = (au1000_ts_t*)dev_id;
++	u32 stat, int_stat, data;
++
++	spin_lock(&ts->lock);
++
++	stat = inl(SSI0_STATUS);
++	// clear sticky status bits
++	outl(stat & (SSISTAT_OF|SSISTAT_UF|SSISTAT_DONE), SSI0_STATUS);
++
++	int_stat = inl(SSI0_INT);
++	// clear sticky intr status bits
++	outl(int_stat & (SSIINT_OI|SSIINT_UI|SSIINT_DI), SSI0_INT);
++
++	if ((int_stat & (SSIINT_OI|SSIINT_UI|SSIINT_DI)) != SSIINT_DI) {
++		if (int_stat & SSIINT_OI)
++			err("overflow");
++		if (int_stat & SSIINT_UI)
++			err("underflow");
++		spin_unlock(&ts->lock);
++		return;
++	}
++
++	data = inl(SSI0_ADATA) & SSIADAT_DATA_MASK;
++
++	switch (ts->acq_state) {
++	case IDLE:
++		break;
++	case ACQ_X:
++		ts->x_raw = data;
++		ts->acq_state = ACQ_Y;
++		// trigger Y acq
++		outl(SSIADAT_D | (MEASURE_12BIT_Y << SSIADAT_ADDR_BIT),
++		     SSI0_ADATA);
++		break;
++	case ACQ_Y:
++		ts->y_raw = data;
++		ts->acq_state = ACQ_Z1;
++		// trigger Z1 acq
++		outl(SSIADAT_D | (MEASURE_12BIT_Z1 << SSIADAT_ADDR_BIT),
++		     SSI0_ADATA);
++		break;
++	case ACQ_Z1:
++		ts->z1_raw = data;
++		if (ts->pressure_eqn == PRESSURE_EQN_2) {
++			// don't acq Z2, using 2nd eqn for touch pressure
++			ts->acq_state = IDLE;
++			// got the raw stuff, now mark BH
++			queue_task(&ts->chug_tq, &tq_immediate);
++			mark_bh(IMMEDIATE_BH);
++		} else {
++			ts->acq_state = ACQ_Z2;
++			// trigger Z2 acq
++			outl(SSIADAT_D | (MEASURE_12BIT_Z2<<SSIADAT_ADDR_BIT),
++			     SSI0_ADATA);
++		}
++		break;
++	case ACQ_Z2:
++		ts->z2_raw = data;
++		ts->acq_state = IDLE;
++		// got the raw stuff, now mark BH
++		queue_task(&ts->chug_tq, &tq_immediate);
++		mark_bh(IMMEDIATE_BH);
++		break;
++	}
++
++	spin_unlock(&ts->lock);
++}
++
++
++/* +++++++++++++ File operations ++++++++++++++*/
++
++static int
++au1000_fasync(int fd, struct file *filp, int mode)
++{
++	au1000_ts_t* ts = (au1000_ts_t*)filp->private_data;
++	return fasync_helper(fd, filp, mode, &ts->fasync);
++}
++
++static int
++au1000_ioctl(struct inode * inode, struct file *filp,
++	     unsigned int cmd, unsigned long arg)
++{
++	au1000_ts_t* ts = (au1000_ts_t*)filp->private_data;
++
++	switch(cmd) {
++	case TS_GET_RATE:       /* TODO: what is this? */
++		break;
++	case TS_SET_RATE:       /* TODO: what is this? */
++		break;
++	case TS_GET_CAL:
++		copy_to_user((char *)arg, (char *)&ts->cal, sizeof(TS_CAL));
++		break;
++	case TS_SET_CAL:
++		copy_from_user((char *)&ts->cal, (char *)arg, sizeof(TS_CAL));
++		break;
++	default:
++		err("unknown cmd %04x", cmd);
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static unsigned int
++au1000_poll(struct file * filp, poll_table * wait)
++{
++	au1000_ts_t* ts = (au1000_ts_t*)filp->private_data;
++	poll_wait(filp, &ts->wait, wait);
++	if (ts->event_count)
++		return POLLIN | POLLRDNORM;
++	return 0;
++}
++
++static ssize_t
++au1000_read(struct file * filp, char * buf, size_t count, loff_t * l)
++{
++	au1000_ts_t* ts = (au1000_ts_t*)filp->private_data;
++	unsigned long flags;
++	TS_EVENT event;
++	int i;
++
++	if (ts->event_count == 0) {
++		if (filp->f_flags & O_NONBLOCK)
++			return -EAGAIN;
++		interruptible_sleep_on(&ts->wait);
++		if (signal_pending(current))
++			return -ERESTARTSYS;
++	}
++
++	for (i = count;
++	     i >= sizeof(TS_EVENT);
++	     i -= sizeof(TS_EVENT), buf += sizeof(TS_EVENT)) {
++		if (ts->event_count == 0)
++			break;
++		spin_lock_irqsave(&ts->lock, flags);
++		event = ts->event_buf[ts->nextOut++];
++		if (ts->nextOut == EVENT_BUFSIZE)
++			ts->nextOut = 0;
++		if (ts->event_count)
++			ts->event_count--;
++		spin_unlock_irqrestore(&ts->lock, flags);
++		copy_to_user(buf, &event, sizeof(TS_EVENT));
++	}
++
++	return count - i;
++}
++
++
++static int
++au1000_open(struct inode * inode, struct file * filp)
++{
++	au1000_ts_t* ts;
++	unsigned long flags;
++
++	filp->private_data = ts = &au1000_ts;
++
++	spin_lock_irqsave(&ts->lock, flags);
++
++	// setup SSI0 config
++	outl(DEFAULT_SSI_CONFIG, SSI0_CONFIG);
++
++	// clear out SSI0 status bits
++	outl(SSISTAT_OF|SSISTAT_UF|SSISTAT_DONE, SSI0_STATUS);
++	// clear out SSI0 interrupt pending bits
++	outl(SSIINT_OI|SSIINT_UI|SSIINT_DI, SSI0_INT);
++
++	// enable SSI0 interrupts
++	outl(SSIINT_OI|SSIINT_UI|SSIINT_DI, SSI0_INT_ENABLE);
++
++	/*
++	 * init bh handler that chugs the raw data (calibrates and
++	 * calculates touch pressure).
++	 */
++	ts->chug_tq.routine = chug_raw_data;
++	ts->chug_tq.data = ts;
++	ts->pendown = 0; // pen up
++	
++	// flush event queue
++	ts->nextIn = ts->nextOut = ts->event_count = 0;
++	
++	// Start acquisition timer function
++	init_timer(&ts->acq_timer);
++	ts->acq_timer.function = au1000_acq_timer;
++	ts->acq_timer.data = (unsigned long)ts;
++	ts->acq_timer.expires = jiffies + HZ / 100;
++	add_timer(&ts->acq_timer);
++
++	spin_unlock_irqrestore(&ts->lock, flags);
++
++	return 0;
++}
++
++static int
++au1000_release(struct inode * inode, struct file * filp)
++{
++	au1000_ts_t* ts = (au1000_ts_t*)filp->private_data;
++	unsigned long flags;
++	
++	au1000_fasync(-1, filp, 0);
++	del_timer_sync(&ts->acq_timer);
++
++	spin_lock_irqsave(&ts->lock, flags);
++	// disable SSI0 interrupts
++	outl(0, SSI0_INT_ENABLE);
++	spin_unlock_irqrestore(&ts->lock, flags);
++
++	return 0;
++}
++
++
++static struct file_operations ts_fops = {
++	.read           = au1000_read,
++	.poll           = au1000_poll,
++	.ioctl		= au1000_ioctl,
++	.fasync         = au1000_fasync,
++	.open		= au1000_open,
++	.release	= au1000_release,
++};
++
++/* +++++++++++++ End File operations ++++++++++++++*/
++
++
++int __init
++au1000ts_init_module(void)
++{
++	au1000_ts_t* ts = &au1000_ts;
++	int ret;
++
++	/* register our character device */
++	if ((ret = register_chrdev(TS_MAJOR, TS_NAME, &ts_fops)) < 0) {
++		err("can't get major number");
++		return ret;
++	}
++	info("registered");
++
++	memset(ts, 0, sizeof(au1000_ts_t));
++	init_waitqueue_head(&ts->wait);
++	spin_lock_init(&ts->lock);
++
++	if (!request_region(virt_to_phys((void*)SSI0_STATUS), 0x100, TS_NAME)) {
++		err("SSI0 ports in use");
++		return -ENXIO;
++	}
++
++	if ((ret = request_irq(AU1000_SSI0_INT, ssi0_interrupt,
++			       SA_SHIRQ | SA_INTERRUPT, TS_NAME, ts))) {
++		err("could not get IRQ");
++		return ret;
++	}
++
++	// initial calibration values
++	ts->cal.xscale = -93;
++	ts->cal.xtrans = 346;
++	ts->cal.yscale = -64;
++	ts->cal.ytrans = 251;
++
++	// init pen up/down hysteresis points
++	ts->pendown_thresh_ohms = DEFAULT_PENDOWN_THRESH_OHMS;
++	ts->penup_thresh_ohms = DEFAULT_PENUP_THRESH_OHMS;
++	ts->pressure_eqn = PRESSURE_EQN_2;
++	// init X and Y plate resistances
++	ts->x_plate_ohms = DEFAULT_X_PLATE_OHMS;
++	ts->y_plate_ohms = DEFAULT_Y_PLATE_OHMS;
++
++	// set GPIO to SSI0 function
++	outl(inl(PIN_FUNCTION) & ~1, PIN_FUNCTION);
++	
++	// enable SSI0 clock and bring SSI0 out of reset
++	outl(0, SSI0_CONTROL);
++	udelay(1000);
++	outl(SSIEN_E, SSI0_CONTROL);
++	udelay(100);
++	
++	// FIXME: is this a working baudrate?
++	ts->clkdiv = 0;
++	ts->baudrate = calc_baudrate(ts->clkdiv);
++	outl(ts->clkdiv, SSI0_CLKDIV);
++
++	info("baudrate = %d Hz", ts->baudrate);
++	
++	return 0;
++}
++
++void
++au1000ts_cleanup_module(void)
++{
++	// disable clocks and hold in reset
++	outl(SSIEN_CD, SSI0_CONTROL);
++	free_irq(AU1000_SSI0_INT, &au1000_ts);
++	release_region(virt_to_phys((void*)SSI0_STATUS), 0x100);
++	unregister_chrdev(TS_MAJOR, TS_NAME);
++}
++
++/* Module information */
++MODULE_AUTHOR("Steve Longerbeam, stevel@mvista.com, www.mvista.com");
++MODULE_DESCRIPTION("Au1000/ADS7846 Touch Screen Driver");
++
++module_init(au1000ts_init_module);
++module_exit(au1000ts_cleanup_module);
+diff -Naur linux-2.6.17.orig/drivers/char/au1000_usbraw.c linux-2.6.17/drivers/char/au1000_usbraw.c
+--- linux-2.6.17.orig/drivers/char/au1000_usbraw.c	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/drivers/char/au1000_usbraw.c	2006-06-19 18:16:13.000000000 -0700
+@@ -0,0 +1,573 @@
++/*
++ * BRIEF MODULE DESCRIPTION
++ *	Au1x00 USB Device-Side Raw Block Driver (function layer)
++ *
++ * Copyright 2001-2002 MontaVista Software Inc.
++ * Author: MontaVista Software, Inc.
++ *		stevel@mvista.com or source@mvista.com
++ *
++ *  This program is free software; you can redistribute	 it and/or modify it
++ *  under  the terms of	 the GNU General  Public License as published by the
++ *  Free Software Foundation;  either version 2 of the	License, or (at your
++ *  option) any later version.
++ *
++ *  THIS  SOFTWARE  IS PROVIDED	  ``AS	IS'' AND   ANY	EXPRESS OR IMPLIED
++ *  WARRANTIES,	  INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
++ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
++ *  NO	EVENT  SHALL   THE AUTHOR  BE	 LIABLE FOR ANY	  DIRECT, INDIRECT,
++ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
++ *  NOT LIMITED	  TO, PROCUREMENT OF  SUBSTITUTE GOODS	OR SERVICES; LOSS OF
++ *  USE, DATA,	OR PROFITS; OR	BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
++ *  ANY THEORY OF LIABILITY, WHETHER IN	 CONTRACT, STRICT LIABILITY, OR TORT
++ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
++ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ *  You should have received a copy of the  GNU General Public License along
++ *  with this program; if not, write  to the Free Software Foundation, Inc.,
++ *  675 Mass Ave, Cambridge, MA 02139, USA.
++ */
++
++#include <linux/config.h>
++#include <linux/kernel.h>
++#include <linux/ioport.h>
++#include <linux/sched.h>
++#include <linux/signal.h>
++#include <linux/errno.h>
++#include <linux/poll.h>
++#include <linux/init.h>
++#include <linux/slab.h>
++#include <linux/fcntl.h>
++#include <linux/module.h>
++#include <linux/spinlock.h>
++#include <linux/list.h>
++#include <linux/smp_lock.h>
++#undef DEBUG
++#include <linux/usb.h>
++
++#include <asm/io.h>
++#include <asm/uaccess.h>
++#include <asm/irq.h>
++#include <asm/au1000.h>
++#include <asm/au1000_usbdev.h>
++
++#define USBRAW_MAJOR 190 // FIXME: need a legal major
++#define USBRAW_NAME "usbraw"
++
++#define MAX_NUM_PORTS 2
++
++#define IN_MAX_PACKET_SIZE  64
++#define OUT_MAX_PACKET_SIZE 64
++
++// FIXME: when Au1x00 endpoints 3 and 5 are fixed, make NUM_PORTS=2
++#define NUM_PORTS 1
++#define NUM_EP 2*NUM_PORTS
++
++#define CONFIG_DESC_LEN \
++ USB_DT_CONFIG_SIZE + USB_DT_INTERFACE_SIZE + NUM_EP*USB_DT_ENDPOINT_SIZE
++
++/* must be power of two */
++#define READ_BUF_SIZE (1<<12)
++
++struct usb_raw_port {
++	unsigned char number;
++	spinlock_t port_lock;
++
++	struct usb_endpoint_descriptor* out_desc;
++	struct usb_endpoint_descriptor* in_desc;
++
++	int out_ep_addr; /* endpoint address of OUT endpoint */
++	int in_ep_addr;  /* endpoint address of IN endpoint */
++	
++	__u8 read_buf[READ_BUF_SIZE]; // FIXME: allocate with get_free_pages
++	int read_nextin, read_nextout;
++	int read_count;
++
++	wait_queue_head_t wait;
++	struct fasync_struct *fasync;     // asynch notification
++
++	int active;	/* someone has this device open */
++	int open_count;	/* number of times this port has been opened */
++};
++
++static struct usb_serial {
++	struct usb_device_descriptor* dev_desc;
++	struct usb_config_descriptor* config_desc;
++	struct usb_interface_descriptor* if_desc;
++	struct usb_string_descriptor * str_desc[6];
++	void* str_desc_buf;
++
++	usbdev_state_t dev_state;
++
++	struct usb_raw_port port[NUM_PORTS];
++} usbraw;
++
++static struct usb_device_descriptor dev_desc = {
++	bLength:USB_DT_DEVICE_SIZE,
++	bDescriptorType:USB_DT_DEVICE,
++	bcdUSB:USBDEV_REV,		//usb rev
++	bDeviceClass:USB_CLASS_PER_INTERFACE,	//class    (none)
++	bDeviceSubClass:0x00,	//subclass (none)
++	bDeviceProtocol:0x00,	//protocol (none)
++	bMaxPacketSize0:USBDEV_EP0_MAX_PACKET_SIZE, //max packet size for ep0
++	idVendor:0x6d04,	//vendor  id
++	idProduct:0x0bc0,	//product id
++	bcdDevice:0x0001,	//BCD rev 0.1
++	iManufacturer:0x01,	//manufactuer string index
++	iProduct:0x02,		//product string index
++	iSerialNumber:0x03,	//serial# string index
++	bNumConfigurations:0x01	//num configurations
++};
++
++static struct usb_endpoint_descriptor ep_desc[] = {
++	{
++		// Bulk IN for Port 0
++		bLength:USB_DT_ENDPOINT_SIZE,
++		bDescriptorType:USB_DT_ENDPOINT,
++		bEndpointAddress:USB_DIR_IN,
++		bmAttributes:USB_ENDPOINT_XFER_BULK,
++		wMaxPacketSize:IN_MAX_PACKET_SIZE,
++		bInterval:0x00	// ignored for bulk
++	},
++	{
++		// Bulk OUT for Port 0
++		bLength:USB_DT_ENDPOINT_SIZE,
++		bDescriptorType:USB_DT_ENDPOINT,
++		bEndpointAddress:USB_DIR_OUT,
++		bmAttributes:USB_ENDPOINT_XFER_BULK,
++		wMaxPacketSize:OUT_MAX_PACKET_SIZE,
++		bInterval:0x00	// ignored for bulk
++	},
++	{
++		// Bulk IN for Port 1
++		bLength:USB_DT_ENDPOINT_SIZE,
++		bDescriptorType:USB_DT_ENDPOINT,
++		bEndpointAddress:USB_DIR_IN,
++		bmAttributes:USB_ENDPOINT_XFER_BULK,
++		wMaxPacketSize:IN_MAX_PACKET_SIZE,
++		bInterval:0x00	// ignored for bulk
++	},
++	{
++		// Bulk OUT for Port 1
++		bLength:USB_DT_ENDPOINT_SIZE,
++		bDescriptorType:USB_DT_ENDPOINT,
++		bEndpointAddress:USB_DIR_OUT,
++		bmAttributes:USB_ENDPOINT_XFER_BULK,
++		wMaxPacketSize:OUT_MAX_PACKET_SIZE,
++		bInterval:0x00	// ignored for bulk
++	}
++};
++
++static struct usb_interface_descriptor if_desc = {
++	bLength:USB_DT_INTERFACE_SIZE,
++	bDescriptorType:USB_DT_INTERFACE,
++	bInterfaceNumber:0x00,
++	bAlternateSetting:0x00,
++	bNumEndpoints:NUM_EP,
++	bInterfaceClass:0xff,
++	bInterfaceSubClass:0xab,
++	bInterfaceProtocol:0x00,
++	iInterface:0x05
++};
++
++static struct usb_config_descriptor config_desc = {
++	bLength:USB_DT_CONFIG_SIZE,
++	bDescriptorType:USB_DT_CONFIG,
++	wTotalLength:CONFIG_DESC_LEN,
++	bNumInterfaces:0x01,
++	bConfigurationValue:0x01,
++	iConfiguration:0x04,	// configuration string
++	bmAttributes:0xc0,	// self-powered
++	MaxPower:20		// 40 mA
++};
++
++// String[0] is a list of Language IDs supported by this device
++static struct usb_string_descriptor string_desc0 = {
++	bLength:4,
++	bDescriptorType:USB_DT_STRING,
++	wData:{0x0409} // English, US
++};
++
++// These strings will be converted to Unicode in string_desc[]
++static char *strings[5] = {
++	"Alchemy Semiconductor",  // iManufacturer
++	"USB Raw Block Device",   // iProduct
++	"0.1",                    // iSerialNumber
++	"USB Raw Config",         // iConfiguration
++	"USB Raw Interface"       // iInterface
++};
++
++
++static void
++receive_callback(struct usb_raw_port *port)
++{
++	int i, pkt_size;
++	usbdev_pkt_t* pkt;
++	
++	if ((pkt_size = usbdev_receive_packet(port->out_ep_addr,
++					      &pkt)) <= 0) {
++		dbg(__FUNCTION__ ": usbdev_receive_packet returns %d",
++		    pkt_size);
++		return;
++	}
++
++	dbg(__FUNCTION__ ": ep%d, size=%d", port->out_ep_addr, pkt_size);
++
++	spin_lock(&port->port_lock);
++	for (i=0; i < pkt_size; i++) {
++		port->read_buf[port->read_nextin++] = pkt->payload[i];
++		port->read_nextin &= (READ_BUF_SIZE - 1);
++		if (++port->read_count == READ_BUF_SIZE)
++			break;
++	}
++	spin_unlock(&port->port_lock);
++
++	/* free the packet */
++	kfree(pkt);
++	
++	// async notify
++	if (port->fasync)
++		kill_fasync(&port->fasync, SIGIO, POLL_IN);
++	// wake up any read call
++	if (waitqueue_active(&port->wait))
++		wake_up_interruptible(&port->wait);
++}
++
++static void
++transmit_callback(struct usb_raw_port *port, usbdev_pkt_t* pkt)
++{
++	dbg(__FUNCTION__ ": ep%d", port->in_ep_addr);
++	/* just free the returned packet */
++	kfree(pkt);
++}
++
++
++static void
++usbraw_callback(usbdev_cb_type_t cb_type, unsigned long arg, void* data)
++{
++	usbdev_pkt_t* pkt;
++	int i;
++	
++	switch (cb_type) {
++	case CB_NEW_STATE:
++		usbraw.dev_state = (usbdev_state_t)arg;
++		break;
++	case CB_PKT_COMPLETE:
++		pkt = (usbdev_pkt_t*)arg;
++		for (i=0; i<NUM_PORTS; i++) {
++			struct usb_raw_port *port = &usbraw.port[i];
++			if (pkt->ep_addr == port->in_ep_addr) {
++				transmit_callback(port, pkt);
++				break;
++			} else if (pkt->ep_addr == port->out_ep_addr) {
++				receive_callback(port);
++				break;
++			}
++		}
++		break;
++	}
++}
++
++/*****************************************************************************
++ * Here begins the driver interface functions
++ *****************************************************************************/
++
++static unsigned int usbraw_poll(struct file * filp, poll_table * wait)
++{
++	struct usb_raw_port *port = (struct usb_raw_port *)filp->private_data;
++	unsigned long flags;
++	int count;
++	
++	poll_wait(filp, &port->wait, wait);
++
++	spin_lock_irqsave(&port->port_lock, flags);
++	count = port->read_count;
++	spin_unlock_irqrestore(&port->port_lock, flags);
++
++	if (count > 0) {
++		dbg(__FUNCTION__ ": count=%d", count);
++		return POLLIN | POLLRDNORM;
++	}
++	
++	return 0;
++}
++
++static int usbraw_fasync(int fd, struct file *filp, int mode)
++{
++	struct usb_raw_port *port = (struct usb_raw_port *)filp->private_data;
++	return fasync_helper(fd, filp, mode, &port->fasync);
++}
++
++static int usbraw_open(struct inode * inode, struct file *filp)
++{
++	int portNumber;
++	struct usb_raw_port *port;
++	unsigned long flags;
++
++	/*
++	 * the device-layer must be in the configured state before the
++	 * function layer can operate.
++	 */
++	if (usbraw.dev_state != CONFIGURED)
++		return -ENODEV;
++	
++	/* set up our port structure making the tty driver remember
++	   our port object, and us it */
++	portNumber = MINOR(inode->i_rdev);
++	port = &usbraw.port[portNumber];
++	filp->private_data = port;
++
++	dbg(__FUNCTION__ ": port %d", port->number);
++
++	spin_lock_irqsave(&port->port_lock, flags);
++
++	++port->open_count;
++
++	if (!port->active) {
++		port->active = 1;
++	}
++
++	/* flush read buffer */
++	port->read_nextin = port->read_nextout = port->read_count = 0;
++
++	spin_unlock_irqrestore(&port->port_lock, flags);
++
++	return 0;
++}
++
++static int usbraw_release(struct inode * inode, struct file * filp)
++{
++	struct usb_raw_port *port = (struct usb_raw_port *)filp->private_data;
++	unsigned long flags;
++
++	dbg(__FUNCTION__ ": port %d", port->number);
++
++	if (!port->active) {
++		err(__FUNCTION__ ": port not opened");
++		return -ENODEV;
++	}
++
++	usbraw_fasync(-1, filp, 0);
++
++	spin_lock_irqsave(&port->port_lock, flags);
++
++	--port->open_count;
++
++	if (port->open_count <= 0) {
++		port->active = 0;
++		port->open_count = 0;
++	}
++
++	spin_unlock_irqrestore(&port->port_lock, flags);
++
++	return 0;
++}
++
++
++static ssize_t usbraw_read(struct file * filp, char * buf,
++			   size_t count, loff_t * l)
++{
++	struct usb_raw_port *port = (struct usb_raw_port *)filp->private_data;
++	unsigned long flags;
++	int i, cnt;
++
++	/*
++	 * the device-layer must be in the configured state before the
++	 * function layer can operate.
++	 */
++	if (usbraw.dev_state != CONFIGURED)
++		return -ENODEV;
++
++	do { 
++		spin_lock_irqsave(&port->port_lock, flags);
++		cnt = port->read_count;
++		spin_unlock_irqrestore(&port->port_lock, flags);
++		if (cnt == 0) {
++			if (filp->f_flags & O_NONBLOCK)
++				return -EAGAIN;
++			interruptible_sleep_on(&port->wait);
++			if (signal_pending(current))
++				return -ERESTARTSYS;
++		}
++	} while (cnt == 0);
++
++	count = (count > cnt) ? cnt : count;
++
++	for (i=0; i<count; i++) {
++		put_user(port->read_buf[port->read_nextout++], &buf[i]);
++		port->read_nextout &= (READ_BUF_SIZE - 1);
++		spin_lock_irqsave(&port->port_lock, flags);
++		port->read_count--;
++		spin_unlock_irqrestore(&port->port_lock, flags);
++		if (port->read_count == 0)
++			break;
++	}
++
++	return i+1;
++}
++
++static ssize_t usbraw_write(struct file * filp, const char * buf,
++			    size_t count, loff_t *ppos)
++{
++	struct usb_raw_port *port = (struct usb_raw_port *)filp->private_data;
++	usbdev_pkt_t* pkt;
++	int ret, max_pkt_sz;
++	
++	/*
++	 * the device-layer must be in the configured state before the
++	 * function layer can operate.
++	 */
++	if (usbraw.dev_state != CONFIGURED)
++		return -ENODEV;
++
++	if (!port->active) {
++		err(__FUNCTION__ ": port not opened");
++		return -EINVAL;
++	}
++
++	if (count == 0) {
++		dbg(__FUNCTION__ ": write request of 0 bytes");
++		return (0);
++	}
++
++	max_pkt_sz = port->in_desc->wMaxPacketSize;
++	count = (count > max_pkt_sz) ? max_pkt_sz : count;
++
++	if ((ret = usbdev_alloc_packet(port->in_ep_addr, count, &pkt)) < 0)
++		return ret;
++
++	copy_from_user(pkt->payload, buf, count);
++	
++	return usbdev_send_packet(port->in_ep_addr, pkt);
++}
++
++static int usbraw_ioctl(struct inode *inode, struct file *filp,
++			unsigned int cmd, unsigned long arg)
++{
++	struct usb_raw_port *port = (struct usb_raw_port *)filp->private_data;
++
++	if (!port->active) {
++		err(__FUNCTION__ ": port not open");
++		return -ENODEV;
++	}
++	// FIXME: need any IOCTLs?
++
++	return -ENOIOCTLCMD;
++}
++
++
++static struct file_operations usbraw_fops = {
++        .owner          = THIS_MODULE,
++        .write          = usbraw_write,
++	.read           = usbraw_read,
++	.poll           = usbraw_poll,
++	.ioctl		= usbraw_ioctl,
++	.fasync         = usbraw_fasync,
++	.open		= usbraw_open,
++	.release	= usbraw_release,
++};
++
++void usbfn_raw_exit(void)
++{
++	/* kill the device layer */
++	usbdev_exit();
++
++	unregister_chrdev(USBRAW_MAJOR, USBRAW_NAME);
++
++	if (usbraw.str_desc_buf)
++		kfree(usbraw.str_desc_buf);
++}
++
++
++int usbfn_raw_init(void)
++{
++	int ret = 0, i, str_desc_len;
++
++	/* register our character device */
++	if ((ret = register_chrdev(USBRAW_MAJOR, USBRAW_NAME,
++				   &usbraw_fops)) < 0) {
++		err("can't get major number");
++		return ret;
++	}
++	info("registered");
++
++	/*
++	 * initialize pointers to descriptors
++	 */
++	usbraw.dev_desc = &dev_desc;
++	usbraw.config_desc = &config_desc;
++	usbraw.if_desc = &if_desc;
++
++	/*
++	 * initialize the string descriptors
++	 */
++
++	/* alloc buffer big enough for all string descriptors */
++	str_desc_len = string_desc0.bLength;
++	for (i = 0; i < 5; i++)
++		str_desc_len += 2 + 2 * strlen(strings[i]);
++	usbraw.str_desc_buf = (void *) kmalloc(str_desc_len, GFP_KERNEL);
++	if (!usbraw.str_desc_buf) {
++		err(__FUNCTION__ ": failed to alloc string descriptors");
++		ret = -ENOMEM;
++		goto out;
++	}
++
++	usbraw.str_desc[0] =
++		(struct usb_string_descriptor *)usbraw.str_desc_buf;
++	memcpy(usbraw.str_desc[0], &string_desc0, string_desc0.bLength);
++	usbraw.str_desc[1] = (struct usb_string_descriptor *)
++		(usbraw.str_desc_buf + string_desc0.bLength);
++	for (i = 1; i < 6; i++) {
++		struct usb_string_descriptor *desc = usbraw.str_desc[i];
++		char *str = strings[i - 1];
++		int j, str_len = strlen(str);
++
++		desc->bLength = 2 + 2 * str_len;
++		desc->bDescriptorType = USB_DT_STRING;
++		for (j = 0; j < str_len; j++) {
++			desc->wData[j] = (u16) str[j];
++		}
++		if (i < 5)
++			usbraw.str_desc[i + 1] =
++				(struct usb_string_descriptor *)
++				((u8 *) desc + desc->bLength);
++	}
++
++	/*
++	 * start the device layer. The device layer assigns us
++	 * our endpoint addresses
++	 */
++	if ((ret = usbdev_init(&dev_desc, &config_desc, &if_desc, ep_desc,
++			       usbraw.str_desc, usbraw_callback, NULL))) {
++		err(__FUNCTION__ ": device-layer init failed");
++		goto out;
++	}
++	
++	/* initialize the devfs nodes for this device and let the user
++	   know what ports we are bound to */
++	for (i = 0; i < NUM_PORTS; ++i) {
++		struct usb_raw_port *port = &usbraw.port[i];
++
++		port->number = i;
++		port->in_desc = &ep_desc[NUM_PORTS*i];
++		port->out_desc = &ep_desc[NUM_PORTS*i + 1];
++		port->in_ep_addr = port->in_desc->bEndpointAddress & 0x0f;
++		port->out_ep_addr = port->out_desc->bEndpointAddress & 0x0f;
++		init_waitqueue_head(&port->wait);
++		spin_lock_init(&port->port_lock);
++	}
++
++ out:
++	if (ret)
++		usbfn_raw_exit();
++	return ret;
++}
++
++
++/* Module information */
++MODULE_AUTHOR("Steve Longerbeam, stevel@mvista.com, www.mvista.com");
++MODULE_DESCRIPTION("Au1x00 USB Device-Side Raw Block Driver");
++MODULE_LICENSE("GPL");
++
++module_init(usbfn_raw_init);
++module_exit(usbfn_raw_exit);
+diff -Naur linux-2.6.17.orig/drivers/char/au1000_usbtty.c linux-2.6.17/drivers/char/au1000_usbtty.c
+--- linux-2.6.17.orig/drivers/char/au1000_usbtty.c	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/drivers/char/au1000_usbtty.c	2006-06-19 18:16:13.000000000 -0700
+@@ -0,0 +1,761 @@
++/*
++ * BRIEF MODULE DESCRIPTION
++ *	Au1x00 USB Device-Side Serial TTY Driver (function layer)
++ *
++ * Copyright 2001-2002 MontaVista Software Inc.
++ * Author: MontaVista Software, Inc.
++ *		stevel@mvista.com or source@mvista.com
++ *
++ *  Derived from drivers/usb/serial/usbserial.c:
++ *
++ *  Copyright (C) 1999 - 2001 Greg Kroah-Hartman (greg@kroah.com)
++ *  Copyright (c) 2000 Peter Berger (pberger@brimson.com)
++ *  Copyright (c) 2000 Al Borchers (borchers@steinerpoint.com)
++ *
++ *  This program is free software; you can redistribute	 it and/or modify it
++ *  under  the terms of	 the GNU General  Public License as published by the
++ *  Free Software Foundation;  either version 2 of the	License, or (at your
++ *  option) any later version.
++ *
++ *  THIS  SOFTWARE  IS PROVIDED	  ``AS	IS'' AND   ANY	EXPRESS OR IMPLIED
++ *  WARRANTIES,	  INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
++ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
++ *  NO	EVENT  SHALL   THE AUTHOR  BE	 LIABLE FOR ANY	  DIRECT, INDIRECT,
++ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
++ *  NOT LIMITED	  TO, PROCUREMENT OF  SUBSTITUTE GOODS	OR SERVICES; LOSS OF
++ *  USE, DATA,	OR PROFITS; OR	BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
++ *  ANY THEORY OF LIABILITY, WHETHER IN	 CONTRACT, STRICT LIABILITY, OR TORT
++ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
++ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ *  You should have received a copy of the  GNU General Public License along
++ *  with this program; if not, write  to the Free Software Foundation, Inc.,
++ *  675 Mass Ave, Cambridge, MA 02139, USA.
++ */
++
++#include <linux/config.h>
++#include <linux/kernel.h>
++#include <linux/ioport.h>
++#include <linux/sched.h>
++#include <linux/signal.h>
++#include <linux/errno.h>
++#include <linux/poll.h>
++#include <linux/init.h>
++#include <linux/slab.h>
++#include <linux/fcntl.h>
++#include <linux/tty.h>
++#include <linux/tty_driver.h>
++#include <linux/tty_flip.h>
++#include <linux/module.h>
++#include <linux/spinlock.h>
++#include <linux/list.h>
++#include <linux/smp_lock.h>
++#undef DEBUG
++#include <linux/usb.h>
++
++#include <asm/io.h>
++#include <asm/uaccess.h>
++#include <asm/irq.h>
++#include <asm/au1000.h>
++#include <asm/au1000_usbdev.h>
++
++
++/* local function prototypes */
++static int serial_open(struct tty_struct *tty, struct file *filp);
++static void serial_close(struct tty_struct *tty, struct file *filp);
++static int serial_write(struct tty_struct *tty, int from_user,
++			const unsigned char *buf, int count);
++static int serial_write_room(struct tty_struct *tty);
++static int serial_chars_in_buffer(struct tty_struct *tty);
++static void serial_throttle(struct tty_struct *tty);
++static void serial_unthrottle(struct tty_struct *tty);
++static int serial_ioctl(struct tty_struct *tty, struct file *file,
++			unsigned int cmd, unsigned long arg);
++static void serial_set_termios (struct tty_struct *tty, struct termios * old);
++
++#define SERIAL_TTY_MAJOR 189 // FIXME: need a legal major
++
++#define MAX_NUM_PORTS 2
++
++#define IN_MAX_PACKET_SIZE  32
++#define OUT_MAX_PACKET_SIZE 32
++
++// FIXME: when Au1x00 endpoints 3 and 5 are fixed, make NUM_PORTS=2
++#define NUM_PORTS 2
++#define NUM_EP 2*NUM_PORTS
++
++#define CONFIG_DESC_LEN \
++ USB_DT_CONFIG_SIZE + USB_DT_INTERFACE_SIZE + NUM_EP*USB_DT_ENDPOINT_SIZE
++
++struct usb_serial_port {
++	struct tty_struct *tty;	   /* the coresponding tty for this port */
++	unsigned char number;
++	spinlock_t port_lock;
++
++	struct usb_endpoint_descriptor* out_desc;
++	struct usb_endpoint_descriptor* in_desc;
++
++	int out_ep_addr; /* endpoint address of OUT endpoint */
++	int in_ep_addr;  /* endpoint address of IN endpoint */
++	
++	/* task queue for line discipline waking up on send packet complete */
++	struct tq_struct send_complete_tq;
++	/* task queue for line discipline wakeup on receive packet complete */
++	struct tq_struct receive_complete_tq;
++
++	int active;	/* someone has this device open */
++	int writing;    /* a packet write is in progress */
++	int open_count;	/* number of times this port has been opened */
++
++};
++
++static struct usb_serial {
++	usbdev_state_t dev_state; // current state of device layer
++	struct usb_device_descriptor* dev_desc;
++	struct usb_config_descriptor* config_desc;
++	struct usb_interface_descriptor* if_desc;
++	struct usb_string_descriptor * str_desc[6];
++	void* str_desc_buf;
++
++	struct usb_serial_port port[NUM_PORTS];
++} usbtty;
++
++static int                 serial_refcount;
++static struct tty_driver   serial_tty_driver;
++static struct tty_struct * serial_tty[NUM_PORTS];
++static struct termios *    serial_termios[NUM_PORTS];
++static struct termios *    serial_termios_locked[NUM_PORTS];
++
++static struct usb_device_descriptor dev_desc = {
++	bLength:USB_DT_DEVICE_SIZE,
++	bDescriptorType:USB_DT_DEVICE,
++	bcdUSB:USBDEV_REV,		//usb rev
++	bDeviceClass:USB_CLASS_PER_INTERFACE,	//class    (none)
++	bDeviceSubClass:0x00,	//subclass (none)
++	bDeviceProtocol:0x00,	//protocol (none)
++	bMaxPacketSize0:USBDEV_EP0_MAX_PACKET_SIZE, //max packet size for ep0
++	idVendor:0x6d04,	//vendor  id
++	idProduct:0x0bc0,	//product id
++	bcdDevice:0x0001,	//BCD rev 0.1
++	iManufacturer:0x01,	//manufactuer string index
++	iProduct:0x02,		//product string index
++	iSerialNumber:0x03,	//serial# string index
++	bNumConfigurations:0x01	//num configurations
++};
++
++static struct usb_endpoint_descriptor ep_desc[] = {
++	{
++		// Bulk IN for Port 0
++		bLength:USB_DT_ENDPOINT_SIZE,
++		bDescriptorType:USB_DT_ENDPOINT,
++		bEndpointAddress:USB_DIR_IN,
++		bmAttributes:USB_ENDPOINT_XFER_BULK,
++		wMaxPacketSize:IN_MAX_PACKET_SIZE,
++		bInterval:0x00	// ignored for bulk
++	},
++	{
++		// Bulk OUT for Port 0
++		bLength:USB_DT_ENDPOINT_SIZE,
++		bDescriptorType:USB_DT_ENDPOINT,
++		bEndpointAddress:USB_DIR_OUT,
++		bmAttributes:USB_ENDPOINT_XFER_BULK,
++		wMaxPacketSize:OUT_MAX_PACKET_SIZE,
++		bInterval:0x00	// ignored for bulk
++	},
++	{
++		// Bulk IN for Port 1
++		bLength:USB_DT_ENDPOINT_SIZE,
++		bDescriptorType:USB_DT_ENDPOINT,
++		bEndpointAddress:USB_DIR_IN,
++		bmAttributes:USB_ENDPOINT_XFER_BULK,
++		wMaxPacketSize:IN_MAX_PACKET_SIZE,
++		bInterval:0x00	// ignored for bulk
++	},
++	{
++		// Bulk OUT for Port 1
++		bLength:USB_DT_ENDPOINT_SIZE,
++		bDescriptorType:USB_DT_ENDPOINT,
++		bEndpointAddress:USB_DIR_OUT,
++		bmAttributes:USB_ENDPOINT_XFER_BULK,
++		wMaxPacketSize:OUT_MAX_PACKET_SIZE,
++		bInterval:0x00	// ignored for bulk
++	}
++};
++
++static struct usb_interface_descriptor if_desc = {
++	bLength:USB_DT_INTERFACE_SIZE,
++	bDescriptorType:USB_DT_INTERFACE,
++	bInterfaceNumber:0x00,
++	bAlternateSetting:0x00,
++	bNumEndpoints:NUM_EP,
++	bInterfaceClass:0xff,
++	bInterfaceSubClass:0xab,
++	bInterfaceProtocol:0x00,
++	iInterface:0x05
++};
++
++static struct usb_config_descriptor config_desc = {
++	bLength:USB_DT_CONFIG_SIZE,
++	bDescriptorType:USB_DT_CONFIG,
++	wTotalLength:CONFIG_DESC_LEN,
++	bNumInterfaces:0x01,
++	bConfigurationValue:0x01,
++	iConfiguration:0x04,	// configuration string
++	bmAttributes:0xc0,	// self-powered
++	MaxPower:20		// 40 mA
++};
++
++// String[0] is a list of Language IDs supported by this device
++static struct usb_string_descriptor string_desc0 = {
++	bLength:4,
++	bDescriptorType:USB_DT_STRING,
++	wData:{0x0409} // English, US
++};
++
++// These strings will be converted to Unicode in string_desc[]
++static char *strings[5] = {
++	"Alchemy Semiconductor",  // iManufacturer
++	"WutzAMattaU",            // iProduct
++	"1.0.doh!",               // iSerialNumber
++	"Au1000 TTY Config",      // iConfiguration
++	"Au1000 TTY Interface"    // iInterface
++};
++
++static inline int
++port_paranoia_check(struct usb_serial_port *port, const char *function)
++{
++	if (!port) {
++		err("%s: port is NULL", function);
++		return -1;
++	}
++	if (!port->tty) {
++		err("%s: port->tty is NULL", function);
++		return -1;
++	}
++
++	return 0;
++}
++
++
++static void
++port_rx_callback(struct usb_serial_port *port)
++{
++	dbg(__FUNCTION__ ": ep%d", port->out_ep_addr);
++	// mark a bh to push this data up to the tty
++	queue_task(&port->receive_complete_tq, &tq_immediate);
++	mark_bh(IMMEDIATE_BH);
++}
++
++static void
++port_tx_callback(struct usb_serial_port *port, usbdev_pkt_t* pkt)
++{
++	dbg(__FUNCTION__ ": ep%d", port->in_ep_addr);
++	// mark a bh to wakeup any tty write system call on the port.
++	queue_task(&port->send_complete_tq, &tq_immediate);
++	mark_bh(IMMEDIATE_BH);
++
++	/* free the returned packet */
++	kfree(pkt);
++}
++
++static void
++usbtty_callback(usbdev_cb_type_t cb_type, unsigned long arg, void* data)
++{
++	usbdev_pkt_t* pkt;
++	int i;
++	
++	switch (cb_type) {
++	case CB_NEW_STATE:
++		dbg(__FUNCTION__ ": new dev_state=%d", (int)arg);
++		usbtty.dev_state = (usbdev_state_t)arg;
++		break;
++	case CB_PKT_COMPLETE:
++		pkt = (usbdev_pkt_t*)arg;
++		for (i=0; i<NUM_PORTS; i++) {
++			struct usb_serial_port *port = &usbtty.port[i];
++			if (pkt->ep_addr == port->in_ep_addr) {
++				port_tx_callback(port, pkt);
++				break;
++			} else if (pkt->ep_addr == port->out_ep_addr) {
++				port_rx_callback(port);
++				break;
++			}
++		}
++		break;
++	}
++}
++
++
++/*****************************************************************************
++ * Here begins the tty driver interface functions
++ *****************************************************************************/
++
++static int serial_open(struct tty_struct *tty, struct file *filp)
++{
++	int portNumber;
++	struct usb_serial_port *port;
++	unsigned long flags;
++
++	/* initialize the pointer incase something fails */
++	tty->driver_data = NULL;
++
++	/* set up our port structure making the tty driver remember
++	   our port object, and us it */
++	portNumber = MINOR(tty->device);
++	port = &usbtty.port[portNumber];
++	tty->driver_data = port;
++	port->tty = tty;
++
++	if (usbtty.dev_state != CONFIGURED ||
++	    port_paranoia_check(port, __FUNCTION__)) {
++		/*
++		 * the device-layer must be in the configured state before
++		 * the function layer can operate.
++		 */
++		return -ENODEV;
++	}
++	
++	dbg(__FUNCTION__ ": port %d", port->number);
++
++	spin_lock_irqsave(&port->port_lock, flags);
++
++	++port->open_count;
++
++	if (!port->active) {
++		port->active = 1;
++
++		/*
++		 * force low_latency on so that our tty_push actually forces
++		 * the data through, otherwise it is scheduled, and with high
++		 * data rates (like with OHCI) data can get lost.
++		 */
++		port->tty->low_latency = 1;
++
++	}
++
++	spin_unlock_irqrestore(&port->port_lock, flags);
++
++	return 0;
++}
++
++
++static void serial_close(struct tty_struct *tty, struct file *filp)
++{
++	struct usb_serial_port *port =
++		(struct usb_serial_port *) tty->driver_data;
++	unsigned long flags;
++
++	dbg(__FUNCTION__ ": port %d", port->number);
++
++	if (!port->active) {
++		err(__FUNCTION__ ": port not opened");
++		return;
++	}
++
++	spin_lock_irqsave(&port->port_lock, flags);
++
++	--port->open_count;
++
++	if (port->open_count <= 0) {
++		port->active = 0;
++		port->open_count = 0;
++	}
++
++	spin_unlock_irqrestore(&port->port_lock, flags);
++	MOD_DEC_USE_COUNT;
++}
++
++
++static int serial_write(struct tty_struct *tty, int from_user,
++			const unsigned char *buf, int count)
++{
++	struct usb_serial_port *port =
++		(struct usb_serial_port *) tty->driver_data;
++	usbdev_pkt_t* pkt;
++	int max_pkt_sz, ret;
++	unsigned long flags;
++	
++	/*
++	 * the device-layer must be in the configured state before the
++	 * function layer can operate.
++	 */
++	if (usbtty.dev_state != CONFIGURED)
++		return -ENODEV;
++
++	if (!port->active) {
++		err(__FUNCTION__ ": port not open");
++		return -EINVAL;
++	}
++
++	if (count == 0) {
++		dbg(__FUNCTION__ ": request of 0 bytes");
++		return (0);
++	}
++
++#if 0
++	if (port->writing) {
++		dbg(__FUNCTION__ ": already writing");
++		return 0;
++	}
++#endif
++	
++	max_pkt_sz = port->in_desc->wMaxPacketSize;
++	count = (count > max_pkt_sz) ? max_pkt_sz : count;
++
++	if ((ret = usbdev_alloc_packet(port->in_ep_addr, count, &pkt)))
++		return ret;
++
++	if (from_user)
++		copy_from_user(pkt->payload, buf, count);
++	else
++		memcpy(pkt->payload, buf, count);
++	
++	ret = usbdev_send_packet(port->in_ep_addr, pkt);
++
++	spin_lock_irqsave(&port->port_lock, flags);
++	port->writing = 1;
++	spin_unlock_irqrestore(&port->port_lock, flags);
++
++	return ret;
++}
++
++
++static int serial_write_room(struct tty_struct *tty)
++{
++	struct usb_serial_port *port =
++		(struct usb_serial_port *) tty->driver_data;
++	int room = 0;
++	
++	/*
++	 * the device-layer must be in the configured state before the
++	 * function layer can operate.
++	 */
++	if (usbtty.dev_state != CONFIGURED)
++		return -ENODEV;
++
++	if (!port->active) {
++		err(__FUNCTION__ ": port not open");
++		return -EINVAL;
++	}
++
++	//room = port->writing ? 0 : port->in_desc->wMaxPacketSize;
++	room = port->in_desc->wMaxPacketSize;
++	
++	dbg(__FUNCTION__ ": %d", room);
++	return room;
++}
++
++
++static int serial_chars_in_buffer(struct tty_struct *tty)
++{
++	struct usb_serial_port *port =
++		(struct usb_serial_port *) tty->driver_data;
++	int chars = 0;
++	
++	/*
++	 * the device-layer must be in the configured state before the
++	 * function layer can operate.
++	 */
++	if (usbtty.dev_state != CONFIGURED)
++		return -ENODEV;
++
++	if (!port->active) {
++		err(__FUNCTION__ ": port not open");
++		return -EINVAL;
++	}
++
++	//chars = port->writing ? usbdev_get_byte_count(port->in_ep_addr) : 0;
++	chars = usbdev_get_byte_count(port->in_ep_addr);
++
++	dbg(__FUNCTION__ ": %d", chars);
++	return chars;
++}
++
++
++static void serial_throttle(struct tty_struct *tty)
++{
++	struct usb_serial_port *port =
++		(struct usb_serial_port *) tty->driver_data;
++
++	if (!port->active || usbtty.dev_state != CONFIGURED) {
++		err(__FUNCTION__ ": port not open");
++		return;
++	}
++
++	// FIXME: anything to do?
++	dbg(__FUNCTION__);
++}
++
++
++static void serial_unthrottle(struct tty_struct *tty)
++{
++	struct usb_serial_port *port =
++		(struct usb_serial_port *) tty->driver_data;
++
++	if (!port->active || usbtty.dev_state != CONFIGURED) {
++		err(__FUNCTION__ ": port not open");
++		return;
++	}
++
++	// FIXME: anything to do?
++	dbg(__FUNCTION__);
++}
++
++
++static int serial_ioctl(struct tty_struct *tty, struct file *file,
++			unsigned int cmd, unsigned long arg)
++{
++	struct usb_serial_port *port =
++		(struct usb_serial_port *) tty->driver_data;
++
++	if (!port->active) {
++		err(__FUNCTION__ ": port not open");
++		return -ENODEV;
++	}
++	// FIXME: need any IOCTLs?
++	dbg(__FUNCTION__);
++
++	return -ENOIOCTLCMD;
++}
++
++
++static void serial_set_termios(struct tty_struct *tty, struct termios *old)
++{
++	struct usb_serial_port *port =
++		(struct usb_serial_port *) tty->driver_data;
++
++	if (!port->active || usbtty.dev_state != CONFIGURED)  {
++		err(__FUNCTION__ ": port not open");
++		return;
++	}
++
++	dbg(__FUNCTION__);
++	// FIXME: anything to do?
++}
++
++
++static void serial_break(struct tty_struct *tty, int break_state)
++{
++	struct usb_serial_port *port =
++		(struct usb_serial_port *) tty->driver_data;
++
++	if (!port->active || usbtty.dev_state != CONFIGURED)  {
++		err(__FUNCTION__ ": port not open");
++		return;
++	}
++
++	dbg(__FUNCTION__);
++	// FIXME: anything to do?
++}
++
++
++static void port_send_complete(void *private)
++{
++	struct usb_serial_port *port = (struct usb_serial_port *) private;
++	struct tty_struct *tty;
++	unsigned long flags;
++
++	dbg(__FUNCTION__ ": port %d, ep%d", port->number, port->in_ep_addr);
++
++	tty = port->tty;
++	if ((tty->flags & (1 << TTY_DO_WRITE_WAKEUP)) &&
++	    tty->ldisc.write_wakeup) {
++		dbg(__FUNCTION__ ": write wakeup call.");
++		(tty->ldisc.write_wakeup) (tty);
++	}
++
++	wake_up_interruptible(&tty->write_wait);
++
++	spin_lock_irqsave(&port->port_lock, flags);
++	port->writing = usbdev_get_byte_count(port->in_ep_addr) <= 0 ? 0 : 1;
++	spin_unlock_irqrestore(&port->port_lock, flags);
++}
++
++
++static void port_receive_complete(void *private)
++{
++	struct usb_serial_port *port = (struct usb_serial_port *) private;
++	struct tty_struct *tty = port->tty;
++	usbdev_pkt_t* pkt = NULL;
++	int i, count;
++
++	/* while there is a packet available */
++	while ((count = usbdev_receive_packet(port->out_ep_addr,
++					      &pkt)) != -ENODATA) {
++		if (count < 0) {
++			if (pkt)
++				kfree(pkt);
++			break; /* exit if error other than ENODATA */
++		}
++		
++		dbg(__FUNCTION__ ": port %d, ep%d, size=%d",
++		    port->number, port->out_ep_addr, count);
++
++		for (i = 0; i < count; i++) {
++			/* if we insert more than TTY_FLIPBUF_SIZE characters,
++			   we drop them. */
++			if (tty->flip.count >= TTY_FLIPBUF_SIZE) {
++				tty_flip_buffer_push(tty);
++			}
++			/* this doesn't actually push the data through
++			   unless tty->low_latency is set */
++			tty_insert_flip_char(tty, pkt->payload[i], 0);
++		}
++		tty_flip_buffer_push(tty);
++
++		kfree(pkt); /* make sure we free the packet */
++	}
++
++}
++
++
++static struct tty_driver serial_tty_driver = {
++	.magic= TTY_DRIVER_MAGIC,
++	.driver_name= "usbfn-tty",
++	.name= "usb/ttsdev/%d",
++	.major= SERIAL_TTY_MAJOR,
++	.minor_start= 0,
++	.num= NUM_PORTS,
++	.type= TTY_DRIVER_TYPE_SERIAL,
++	.subtype= SERIAL_TYPE_NORMAL,
++	.flags= TTY_DRIVER_REAL_RAW | TTY_DRIVER_NO_DEVFS,
++	.refcount= &serial_refcount,
++	.table= serial_tty,
++	.termios= serial_termios,
++	.termios_locked= serial_termios_locked,
++
++	.open= serial_open,
++	.close= serial_close,
++	.write= serial_write,
++	.write_room= serial_write_room,
++	.ioctl= serial_ioctl,
++	.set_termios= serial_set_termios,
++	.throttle= serial_throttle,
++	.unthrottle= serial_unthrottle,
++	.break_ctl= serial_break,
++	.chars_in_buffer= serial_chars_in_buffer,
++};
++
++
++void usbfn_tty_exit(void)
++{
++	int i;
++	
++	/* kill the device layer */
++	usbdev_exit();
++
++	for (i=0; i < NUM_PORTS; i++) {
++		tty_unregister_devfs(&serial_tty_driver, i);
++		info("usb serial converter now disconnected from ttyUSBdev%d",
++		     i);
++	}
++
++	tty_unregister_driver(&serial_tty_driver);
++
++	if (usbtty.str_desc_buf)
++		kfree(usbtty.str_desc_buf);
++}
++
++
++int usbfn_tty_init(void)
++{
++	int ret = 0, i, str_desc_len;
++
++	/* register the tty driver */
++	serial_tty_driver.init_termios = tty_std_termios;
++	serial_tty_driver.init_termios.c_cflag =
++		B9600 | CS8 | CREAD | HUPCL | CLOCAL;
++	
++	if (tty_register_driver(&serial_tty_driver)) {
++		err(__FUNCTION__ ": failed to register tty driver");
++		ret = -ENXIO;
++		goto out;
++	}
++
++	/*
++	 * initialize pointers to descriptors
++	 */
++	usbtty.dev_desc = &dev_desc;
++	usbtty.config_desc = &config_desc;
++	usbtty.if_desc = &if_desc;
++
++	/*
++	 * initialize the string descriptors
++	 */
++
++	/* alloc buffer big enough for all string descriptors */
++	str_desc_len = string_desc0.bLength;
++	for (i = 0; i < 5; i++)
++		str_desc_len += 2 + 2 * strlen(strings[i]);
++	usbtty.str_desc_buf = (void *) kmalloc(str_desc_len, GFP_KERNEL);
++	if (!usbtty.str_desc_buf) {
++		err(__FUNCTION__ ": failed to alloc string descriptors");
++		ret = -ENOMEM;
++		goto out;
++	}
++
++	usbtty.str_desc[0] =
++		(struct usb_string_descriptor *)usbtty.str_desc_buf;
++	memcpy(usbtty.str_desc[0], &string_desc0, string_desc0.bLength);
++	usbtty.str_desc[1] = (struct usb_string_descriptor *)
++		(usbtty.str_desc_buf + string_desc0.bLength);
++	for (i = 1; i < 6; i++) {
++		struct usb_string_descriptor *desc = usbtty.str_desc[i];
++		char *str = strings[i - 1];
++		int j, str_len = strlen(str);
++
++		desc->bLength = 2 + 2 * str_len;
++		desc->bDescriptorType = USB_DT_STRING;
++		for (j = 0; j < str_len; j++) {
++			desc->wData[j] = (u16) str[j];
++		}
++		if (i < 5)
++			usbtty.str_desc[i + 1] =
++				(struct usb_string_descriptor *)
++				((u8 *) desc + desc->bLength);
++	}
++
++	/*
++	 * start the device layer. The device layer assigns us
++	 * our endpoint addresses
++	 */
++	if ((ret = usbdev_init(&dev_desc, &config_desc, &if_desc, ep_desc,
++			       usbtty.str_desc, usbtty_callback, NULL))) {
++		err(__FUNCTION__ ": device-layer init failed");
++		goto out;
++	}
++	
++	/* initialize the devfs nodes for this device and let the user
++	   know what ports we are bound to */
++	for (i = 0; i < NUM_PORTS; ++i) {
++		struct usb_serial_port *port;
++		tty_register_devfs(&serial_tty_driver, 0, i);
++		info("usbdev serial attached to ttyUSBdev%d "
++		     "(or devfs usb/ttsdev/%d)", i, i);
++		port = &usbtty.port[i];
++		port->number = i;
++		port->in_desc = &ep_desc[NUM_PORTS*i];
++		port->out_desc = &ep_desc[NUM_PORTS*i + 1];
++		port->in_ep_addr = port->in_desc->bEndpointAddress & 0x0f;
++		port->out_ep_addr = port->out_desc->bEndpointAddress & 0x0f;
++		port->send_complete_tq.routine = port_send_complete;
++		port->send_complete_tq.data = port;
++		port->receive_complete_tq.routine = port_receive_complete;
++		port->receive_complete_tq.data = port;
++		spin_lock_init(&port->port_lock);
++	}
++
++ out:
++	if (ret)
++		usbfn_tty_exit();
++	return ret;
++}
++
++
++/* Module information */
++MODULE_AUTHOR("Steve Longerbeam, stevel@mvista.com, www.mvista.com");
++MODULE_DESCRIPTION("Au1x00 USB Device-Side Serial TTY Driver");
++MODULE_LICENSE("GPL");
++
++module_init(usbfn_tty_init);
++module_exit(usbfn_tty_exit);
+diff -Naur linux-2.6.17.orig/drivers/char/decserial.c linux-2.6.17/drivers/char/decserial.c
+--- linux-2.6.17.orig/drivers/char/decserial.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/drivers/char/decserial.c	2006-06-19 18:16:13.000000000 -0700
+@@ -14,87 +14,85 @@
+  *      device. Added support for PROM console in drivers/char/tty_io.c
+  *      instead. Although it may work to enable more than one 
+  *      console device I strongly recommend to use only one.
++ *
++ *	Copyright (C) 2004  Maciej W. Rozycki
+  */
+ 
+ #include <linux/config.h>
++#include <linux/errno.h>
+ #include <linux/init.h>
+-#include <asm/dec/machtype.h>
+-
+-#ifdef CONFIG_ZS
+-extern int zs_init(void);
+-#endif
+ 
+-#ifdef CONFIG_DZ
+-extern int dz_init(void);
+-#endif
++#include <asm/dec/machtype.h>
++#include <asm/dec/serial.h>
+ 
+-#ifdef CONFIG_SERIAL_CONSOLE
++extern int register_zs_hook(unsigned int channel,
++			    struct dec_serial_hook *hook);
++extern int unregister_zs_hook(unsigned int channel);
+ 
++int register_dec_serial_hook(unsigned int channel,
++			     struct dec_serial_hook *hook)
++{
+ #ifdef CONFIG_ZS
+-extern void zs_serial_console_init(void);
+-#endif
+-
+-#ifdef CONFIG_DZ
+-extern void dz_serial_console_init(void);
++	if (IOASIC)
++		return register_zs_hook(channel, hook);
+ #endif
++	return 0;
++}
+ 
++int unregister_dec_serial_hook(unsigned int channel)
++{
++#ifdef CONFIG_ZS
++	if (IOASIC)
++		return unregister_zs_hook(channel);
+ #endif
++	return 0;
++}
+ 
+-/* rs_init - starts up the serial interface -
+-   handle normal case of starting up the serial interface */
+ 
+-#ifdef CONFIG_SERIAL
++extern int zs_init(void);
++extern int dz_init(void);
+ 
++/*
++ * rs_init - starts up the serial interface -
++ * handle normal case of starting up the serial interface
++ */
+ int __init rs_init(void)
+ {
+-
+-#if defined(CONFIG_ZS) && defined(CONFIG_DZ)
+-    if (IOASIC)
+-	return zs_init();
+-    else
+-	return dz_init();
+-#else
+-
+ #ifdef CONFIG_ZS
+-    return zs_init();
++	if (IOASIC)
++		return zs_init();
+ #endif
+-
+ #ifdef CONFIG_DZ
+-    return dz_init();
+-#endif
+-
++	if (!IOASIC)
++		return dz_init();
+ #endif
++	return -ENXIO;
+ }
+ 
+ __initcall(rs_init);
+ 
+-#endif
+ 
+-#ifdef CONFIG_SERIAL_CONSOLE
++#ifdef CONFIG_SERIAL_DEC_CONSOLE
++
++extern void zs_serial_console_init(void);
++extern void dz_serial_console_init(void);
+ 
+-/* serial_console_init handles the special case of starting
+- *   up the console on the serial port
++/*
++ * dec_serial_console_init handles the special case of starting
++ * up the console on the serial port
+  */
+-static int __init decserial_console_init(void)
++static int __init dec_serial_console_init(void)
+ {
+-#if defined(CONFIG_ZS) && defined(CONFIG_DZ)
+-    if (IOASIC)
+-	zs_serial_console_init();
+-    else
+-	dz_serial_console_init();
+-#else
+-
+ #ifdef CONFIG_ZS
+-    zs_serial_console_init();
++	if (IOASIC)
++		zs_serial_console_init();
+ #endif
+-
+ #ifdef CONFIG_DZ
+-    dz_serial_console_init();
+-#endif
+-
++	if (!IOASIC)
++		dz_serial_console_init();
+ #endif
+     return 0;
+ }
+-console_initcall(decserial_console_init);
++console_initcall(dec_serial_console_init);
+ 
+ #endif
+diff -Naur linux-2.6.17.orig/drivers/char/ibm_workpad_keymap.map linux-2.6.17/drivers/char/ibm_workpad_keymap.map
+--- linux-2.6.17.orig/drivers/char/ibm_workpad_keymap.map	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/drivers/char/ibm_workpad_keymap.map	2006-06-19 18:16:13.000000000 -0700
+@@ -0,0 +1,343 @@
++# Keymap for IBM Workpad z50
++# US Mapping
++#
++# by Michael Klar <wyldfier@iname.com>
++#
++# This is a great big mess on account of how the Caps Lock key is handled as
++# LeftShift-RightShift.  Right shift key had to be broken out, so don't use
++# use this map file as a basis for other keyboards that don't do the same
++# thing with Caps Lock.
++#
++# This file is subject to the terms and conditions of the GNU General Public
++# License.  See the file "COPYING" in the main directory of this archive
++# for more details.
++
++keymaps 0-2,4-5,8,12,32-33,36-37
++strings as usual
++
++keycode 0 = F1 F11 Console_13
++	shiftr keycode 0 = F11
++	shift shiftr keycode 0 = F11
++	control keycode 0 = F1
++	alt keycode 0 = Console_1
++	control alt keycode 0 = Console_1
++keycode 1 = F3 F13 Console_15
++	shiftr keycode 1 = F13
++	shift shiftr keycode 1 = F13
++	control keycode 1 = F3
++	alt keycode 1 = Console_3
++	control alt keycode 1 = Console_3
++keycode 2 = F5 F15 Console_17
++	shiftr keycode 2 = F15
++	shift shiftr keycode 2 = F15
++	control keycode 2 = F5
++	alt keycode 2 = Console_5
++	control alt keycode 2 = Console_5
++keycode 3 = F7 F17 Console_19
++	shiftr keycode 3 = F17
++	shift shiftr keycode 3 = F17
++	control keycode 3 = F7
++	alt keycode 3 = Console_7
++	control alt keycode 3 = Console_7
++keycode 4 = F9 F19 Console_21
++	shiftr keycode 4 = F19
++	shift shiftr keycode 4 = F19
++	control keycode 4 = F9
++	alt keycode 4 = Console_9
++	control alt keycode 4 = Console_9
++#keycode 5 is contrast down
++#keycode 6 is contrast up
++keycode 7 = F11 F11 Console_23
++	shiftr keycode 7 = F11
++	shift shiftr keycode 7 = F11
++	control keycode 7 = F11
++	alt keycode 7 = Console_11
++	control alt keycode 7 = Console_11
++keycode 8 = F2 F12 Console_14
++	shiftr keycode 8 = F12
++	shift shiftr keycode 8 = F12
++	control keycode 8 = F2
++	alt keycode 8 = Console_2
++	control alt keycode 8 = Console_2
++keycode 9 = F4 F14 Console_16
++	shiftr keycode 9 = F14
++	shift shiftr keycode 9 = F14
++	control keycode 9 = F4
++	alt keycode 9 = Console_4
++	control alt keycode 9 = Console_4
++keycode 10 = F6 F16 Console_18
++	shiftr keycode 10 = F16
++	shift shiftr keycode 10 = F16
++	control keycode 10 = F6
++	alt keycode 10 = Console_6
++	control alt keycode 10 = Console_6
++keycode 11 = F8 F18 Console_20
++	shiftr keycode 11 = F18
++	shift shiftr keycode 11 = F18
++	control keycode 11 = F8
++	alt keycode 11 = Console_8
++	control alt keycode 11 = Console_8
++keycode 12 = F10 F20 Console_22
++	shiftr keycode 12 = F20
++	shift shiftr keycode 12 = F20
++	control keycode 12 = F10
++	alt keycode 12 = Console_10
++	control alt keycode 12 = Console_10
++#keycode 13 is brightness down
++#keycode 14 is brightness up
++keycode 15 = F12 F12 Console_24
++	shiftr keycode 15 = F12
++	shift shiftr keycode 15 = F12
++	control keycode 15 = F12
++	alt keycode 15 = Console_12
++	control alt keycode 15 = Console_12
++keycode 16 = apostrophe quotedbl
++	shiftr keycode 16 = quotedbl
++	shift shiftr keycode 16 = quotedbl
++	control keycode 16 = Control_g
++	alt keycode 16 = Meta_apostrophe
++keycode 17 = bracketleft braceleft
++	shiftr keycode 17 = braceleft
++	shift shiftr keycode 17 = braceleft
++	control keycode 17 = Escape
++	alt keycode 17 = Meta_bracketleft
++keycode 18 = minus underscore backslash       
++	shiftr keycode 18 = underscore
++	shift shiftr keycode 18 = underscore
++	control keycode 18 = Control_underscore
++	shift control keycode 18 = Control_underscore
++	shiftr control keycode 18 = Control_underscore
++	shift shiftr control keycode 18 = Control_underscore
++	alt keycode 18 = Meta_minus
++keycode 19 = zero parenright braceright
++	shiftr keycode 19 = parenright
++	shift shiftr keycode 19 = parenright
++	alt keycode 19 = Meta_zero
++keycode 20 = p
++	shiftr keycode 20 = +P
++	shift shiftr keycode 20 = +p
++keycode 21 = semicolon colon
++	shiftr keycode 21 = colon
++	shift shiftr keycode 21 = colon
++	alt keycode 21 = Meta_semicolon
++keycode 22 = Up Scroll_Backward
++	shiftr keycode 22 = Scroll_Backward
++	shift shiftr keycode 22 = Scroll_Backward
++	alt keycode 22 = Prior
++keycode 23 = slash question
++	shiftr keycode 23 = question
++	shift shiftr keycode 23 = question
++	control keycode 23 = Delete
++	alt keycode 23 = Meta_slash
++
++keycode 27 = nine parenleft bracketright
++	shiftr keycode 27 = parenleft
++	shift shiftr keycode 27 = parenleft
++	alt keycode 27 = Meta_nine
++keycode 28 = o
++	shiftr keycode 28 = +O
++	shift shiftr keycode 28 = +o
++keycode 29 = l
++	shiftr keycode 29 = +L
++	shift shiftr keycode 29 = +l
++keycode 30 = period greater
++	shiftr keycode 30 = greater
++	shift shiftr keycode 30 = greater
++	control keycode 30 = Compose
++	alt keycode 30 = Meta_period
++
++keycode 32 = Left Decr_Console
++	shiftr keycode 32 = Decr_Console
++	shift shiftr keycode 32 = Decr_Console
++	alt keycode 32 = Home
++keycode 33 = bracketright braceright asciitilde      
++	shiftr keycode 33 = braceright
++	shift shiftr keycode 33 = braceright
++	control keycode 33 = Control_bracketright
++	alt keycode 33 = Meta_bracketright
++keycode 34 = equal plus
++	shiftr keycode 34 = plus
++	shift shiftr keycode 34 = plus
++	alt keycode 34 = Meta_equal
++keycode 35 = eight asterisk bracketleft
++	shiftr keycode 35 = asterisk
++	shift shiftr keycode 35 = asterisk
++	control keycode 35 = Delete
++	alt keycode 35 = Meta_eight
++keycode 36 = i
++	shiftr keycode 36 = +I
++	shift shiftr keycode 36 = +i
++keycode 37 = k
++	shiftr keycode 37 = +K
++	shift shiftr keycode 37 = +k
++keycode 38 = comma less
++	shiftr keycode 38 = less
++	shift shiftr keycode 38 = less
++	alt keycode 38 = Meta_comma
++
++keycode 40 = h
++	shiftr keycode 40 = +H
++	shift shiftr keycode 40 = +h
++keycode 41 = y
++	shiftr keycode 41 = +Y
++	shift shiftr keycode 41 = +y
++keycode 42 = six asciicircum
++	shiftr keycode 42 = asciicircum
++	shift shiftr keycode 42 = asciicircum
++	control keycode 42 = Control_asciicircum
++	alt keycode 42 = Meta_six
++keycode 43 = seven ampersand braceleft
++	shiftr keycode 43 = ampersand
++	shift shiftr keycode 43 = ampersand
++	control keycode 43 = Control_underscore
++	alt keycode 43 = Meta_seven
++keycode 44 = u
++	shiftr keycode 44 = +U
++	shift shiftr keycode 44 = +u
++keycode 45 = j
++	shiftr keycode 45 = +J
++	shift shiftr keycode 45 = +j
++keycode 46 = m
++	shiftr keycode 46 = +M
++	shift shiftr keycode 46 = +m
++keycode 47 = n
++	shiftr keycode 47 = +N
++	shift shiftr keycode 47 = +n
++
++# This is the "Backspace" key:
++keycode 49 = Delete Delete
++	shiftr keycode 49 = Delete
++	shift shiftr keycode 49 = Delete
++	control keycode 49 = BackSpace
++	alt keycode 49 = Meta_Delete
++keycode 50 = Num_Lock
++	shift keycode 50 = Bare_Num_Lock
++	shiftr keycode 50 = Bare_Num_Lock
++	shift shiftr keycode 50 = Bare_Num_Lock
++# This is the "Delete" key:
++keycode 51 = Remove
++	control alt keycode 51 = Boot
++
++keycode 53 = backslash bar
++	shiftr keycode 53 = bar
++	shift shiftr keycode 53 = bar
++	control keycode 53 = Control_backslash
++	alt keycode 53 = Meta_backslash
++keycode 54 = Return
++	alt keycode 54 = Meta_Control_m
++keycode 55 = space space           
++	shiftr keycode 55 = space
++	shift shiftr keycode 55 = space
++	control keycode 55 = nul
++	alt keycode 55 = Meta_space
++keycode 56 = g
++	shiftr keycode 56 = +G
++	shift shiftr keycode 56 = +g
++keycode 57 = t
++	shiftr keycode 57 = +T
++	shift shiftr keycode 57 = +t
++keycode 58 = five percent
++	shiftr keycode 58 = percent
++	shift shiftr keycode 58 = percent
++	control keycode 58 = Control_bracketright
++	alt keycode 58 = Meta_five
++keycode 59 = four dollar dollar
++	shiftr keycode 59 = dollar
++	shift shiftr keycode 59 = dollar
++	control keycode 59 = Control_backslash
++	alt keycode 59 = Meta_four
++keycode 60 = r
++	shiftr keycode 60 = +R
++	shift shiftr keycode 60 = +r
++keycode 61 = f
++	shiftr keycode 61 = +F
++	shift shiftr keycode 61 = +f
++	altgr keycode 61 = Hex_F
++keycode 62 = v
++	shiftr keycode 62 = +V
++	shift shiftr keycode 62 = +v
++keycode 63 = b
++	shiftr keycode 63 = +B
++	shift shiftr keycode 63 = +b
++	altgr keycode 63 = Hex_B
++
++keycode 67 = three numbersign
++	shiftr keycode 67 = numbersign
++	shift shiftr keycode 67 = numbersign
++	control keycode 67 = Escape
++	alt keycode 67 = Meta_three
++keycode 68 = e
++	shiftr keycode 68 = +E
++	shift shiftr keycode 68 = +e
++	altgr keycode 68 = Hex_E
++keycode 69 = d
++	shiftr keycode 69 = +D
++	shift shiftr keycode 69 = +d
++	altgr keycode 69 = Hex_D
++keycode 70 = c
++	shiftr keycode 70 = +C
++	shift shiftr keycode 70 = +c
++	altgr keycode 70 = Hex_C
++keycode 71 = Right Incr_Console
++	shiftr keycode 71 = Incr_Console
++	shift shiftr keycode 71 = Incr_Console
++	alt keycode 71 = End
++
++keycode 75 = two at at
++	shiftr keycode 75 = at
++	shift shiftr keycode 75 = at
++	control keycode 75 = nul
++	shift control keycode 75 = nul
++	shiftr control keycode 75 = nul
++	shift shiftr control keycode 75 = nul
++	alt keycode 75 = Meta_two
++keycode 76 = w
++	shiftr keycode 76 = +W
++	shift shiftr keycode 76 = +w
++keycode 77 = s
++	shiftr keycode 77 = +S
++	shift shiftr keycode 77 = +s
++keycode 78 = x
++	shiftr keycode 78 = +X
++	shift shiftr keycode 78 = +x
++keycode 79 = Down Scroll_Forward
++	shiftr keycode 79 = Scroll_Forward
++	shift shiftr keycode 79 = Scroll_Forward
++	alt keycode 79 = Next
++keycode 80 = Escape Escape
++	shiftr keycode 80 = Escape
++	shift shiftr keycode 80 = Escape
++	alt keycode 80 = Meta_Escape
++keycode 81 = Tab Tab             
++	shiftr keycode 81 = Tab
++	shift shiftr keycode 81 = Tab
++	alt keycode 81 = Meta_Tab
++keycode 82 = grave asciitilde
++	shiftr keycode 82 = asciitilde
++	shift shiftr keycode 82 = asciitilde
++	control keycode 82 = nul
++	alt keycode 82 = Meta_grave
++keycode 83 = one exclam
++	shiftr keycode 83 = exclam
++	shift shiftr keycode 83 = exclam
++	alt keycode 83 = Meta_one
++keycode 84 = q
++	shiftr keycode 84 = +Q
++	shift shiftr keycode 84 = +q
++keycode 85 = a
++	shiftr keycode 85 = +A
++	shift shiftr keycode 85 = +a
++	altgr keycode 85 = Hex_A
++keycode 86 = z
++	shiftr keycode 86 = +Z
++	shift shiftr keycode 86 = +z
++
++# This is the windows key:
++keycode 88 = Decr_Console
++keycode 89 = Shift
++keycode 90 = Control
++keycode 91 = Control
++keycode 92 = Alt
++keycode 93 = AltGr
++keycode 94 = ShiftR
++	shift keycode 94 = Caps_Lock
+diff -Naur linux-2.6.17.orig/drivers/char/Kconfig linux-2.6.17/drivers/char/Kconfig
+--- linux-2.6.17.orig/drivers/char/Kconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/drivers/char/Kconfig	2006-06-19 18:16:13.000000000 -0700
+@@ -340,23 +340,68 @@
+ 	  To compile this driver as a module, choose M here: the
+ 	  module will be called istallion.
+ 
+-config AU1000_UART
+-	bool "Enable Au1000 UART Support"
+-	depends on SERIAL_NONSTANDARD && MIPS
+-	help
+-	  If you have an Alchemy AU1000 processor (MIPS based) and you want
+-	  to use serial ports, say Y.  Otherwise, say N.
+-
+-config AU1000_SERIAL_CONSOLE
+-	bool "Enable Au1000 serial console"
+-	depends on AU1000_UART
++config AU1X00_GPIO
++	tristate "Alchemy Au1000 GPIO device support"
++	depends on MIPS && SOC_AU1X00
++
++config TS_AU1X00_ADS7846
++	tristate "Au1000/ADS7846 touchscreen support"
++	depends on MIPS && SOC_AU1X00
++
++config AU1X00_USB_TTY
++	tristate "Au1000 USB TTY Device support"
++	depends on MIPS && MIPS_AU1000 && AU1000_USB_DEVICE=y && AU1000_USB_DEVICE
++
++config AU1X00_USB_RAW
++	tristate "Au1000 USB Raw Device support"
++	depends on MIPS && MIPS_AU1000 && AU1000_USB_DEVICE=y && AU1000_USB_TTY!=y && AU1X00_USB_DEVICE
++
++config SIBYTE_SB1250_DUART
++	bool "Support for BCM1xxx onchip DUART"
++	depends on MIPS && SIBYTE_SB1xxx_SOC=y
++
++config SIBYTE_SB1250_DUART_CONSOLE
++	bool "Console on BCM1xxx DUART"
++	depends on SIBYTE_SB1250_DUART
++
++config SERIAL_DEC
++	bool "DECstation serial support"
++	depends on MACH_DECSTATION
++	default y
+ 	help
+-	  If you have an Alchemy AU1000 processor (MIPS based) and you want
+-	  to use a console on a serial port, say Y.  Otherwise, say N.
++	  This selects whether you want to be asked about drivers for
++	  DECstation serial ports.
++
++	  Note that the answer to this question won't directly affect the
++	  kernel: saying N will just cause the configurator to skip all
++	  the questions about DECstation serial ports.
++
++	  If unsure, say Y.
++
++config SERIAL_DEC_CONSOLE
++	bool "Support for console on a DECstation serial port"
++	depends on SERIAL_DEC
++	default y
++	help
++	  If you say Y here, it will be possible to use a serial port as the
++	  system console (the system console is the device which receives all
++	  kernel messages and warnings and which allows logins in single user
++	  mode).  Note that the firmware uses ttyS0 as the serial console on
++	  the Maxine and ttyS2 on the others.
++
++	  If unsure, say Y.
++
++config ZS
++	bool "Z85C30 Serial Support"
++	depends on SERIAL_DEC
++	default y
++	help
++	  Documentation on the Zilog 85C350 serial communications controller
++	  is downloadable at <http://www.zilog.com/pdfs/serial/z85c30.pdf>.
+ 
+ config QTRONIX_KEYBOARD
+ 	bool "Enable Qtronix 990P Keyboard Support"
+-	depends on IT8712
++	depends on MIPS && (MIPS_ITE8172 || MIPS_IVR)
+ 	help
+ 	  Images of Qtronix keyboards are at
+ 	  <http://www.qtronix.com/keyboard.html>.
+@@ -368,7 +413,7 @@
+ 
+ config IT8172_SCR0
+ 	bool "Enable Smart Card Reader 0 Support "
+-	depends on IT8712
++	depends on MIPS && (MIPS_ITE8172 || MIPS_IVR)
+ 	help
+ 	  Say Y here to support smart-card reader 0 (SCR0) on the Integrated
+ 	  Technology Express, Inc. ITE8172 SBC.  Vendor page at
+@@ -377,13 +422,17 @@
+ 
+ config IT8172_SCR1
+ 	bool "Enable Smart Card Reader 1 Support "
+-	depends on IT8712
++	depends on MIPS && (MIPS_ITE8172 || MIPS_IVR)
+ 	help
+ 	  Say Y here to support smart-card reader 1 (SCR1) on the Integrated
+ 	  Technology Express, Inc. ITE8172 SBC.  Vendor page at
+ 	  <http://www.ite.com.tw/ia/brief_it8172bsp.htm>; picture of the
+ 	  board at <http://www.mvista.com/partners/semiconductor/ite.html>.
+ 
++config ITE_GPIO
++	tristate "ITE GPIO"
++	depends on MIPS && MIPS_ITE8172
++
+ config A2232
+ 	tristate "Commodore A2232 serial support (EXPERIMENTAL)"
+ 	depends on EXPERIMENTAL && ZORRO && BROKEN_ON_SMP
+diff -Naur linux-2.6.17.orig/drivers/char/Makefile linux-2.6.17/drivers/char/Makefile
+--- linux-2.6.17.orig/drivers/char/Makefile	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/drivers/char/Makefile	2006-06-19 18:16:13.000000000 -0700
+@@ -31,6 +31,7 @@
+ obj-$(CONFIG_A2232)		+= ser_a2232.o generic_serial.o
+ obj-$(CONFIG_ATARI_DSP56K)	+= dsp56k.o
+ obj-$(CONFIG_MOXA_SMARTIO)	+= mxser.o
++obj-$(CONFIG_SIBYTE_SB1250_DUART) += sb1250_duart.o
+ obj-$(CONFIG_COMPUTONE)		+= ip2/
+ obj-$(CONFIG_RISCOM8)		+= riscom8.o
+ obj-$(CONFIG_ISI)		+= isicom.o
+@@ -51,6 +52,7 @@
+ obj-$(CONFIG_VIOTAPE)		+= viotape.o
+ obj-$(CONFIG_HVCS)		+= hvcs.o
+ obj-$(CONFIG_SGI_MBCS)		+= mbcs.o
++obj-$(CONFIG_SERIAL_DEC)	+= decserial.o
+ 
+ obj-$(CONFIG_PRINTER)		+= lp.o
+ obj-$(CONFIG_TIPAR)		+= tipar.o
+@@ -78,6 +80,10 @@
+ obj-$(CONFIG_HW_RANDOM)		+= hw_random.o
+ obj-$(CONFIG_FTAPE)		+= ftape/
+ obj-$(CONFIG_COBALT_LCD)	+= lcd.o
++obj-$(CONFIG_ITE_GPIO)		+= ite_gpio.o
++obj-$(CONFIG_AU1000_GPIO)	+= au1000_gpio.o
++obj-$(CONFIG_AU1000_USB_TTY)	+= au1000_usbtty.o
++obj-$(CONFIG_AU1000_USB_RAW)	+= au1000_usbraw.o
+ obj-$(CONFIG_PPDEV)		+= ppdev.o
+ obj-$(CONFIG_NWBUTTON)		+= nwbutton.o
+ obj-$(CONFIG_NWFLASH)		+= nwflash.o
+diff -Naur linux-2.6.17.orig/drivers/char/qtronix.c linux-2.6.17/drivers/char/qtronix.c
+--- linux-2.6.17.orig/drivers/char/qtronix.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/drivers/char/qtronix.c	2006-06-19 18:16:13.000000000 -0700
+@@ -535,8 +535,7 @@
+ 		i--;
+ 	}
+ 	if (count-i) {
+-		struct inode *inode = file->f_dentry->d_inode;
+-		inode->i_atime = current_fs_time(inode->i_sb);
++		file->f_dentry->d_inode->i_atime = get_seconds();
+ 		return count-i;
+ 	}
+ 	if (signal_pending(current))
+diff -Naur linux-2.6.17.orig/drivers/char/rtc.c linux-2.6.17/drivers/char/rtc.c
+--- linux-2.6.17.orig/drivers/char/rtc.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/drivers/char/rtc.c	2006-06-19 18:16:13.000000000 -0700
+@@ -35,23 +35,22 @@
+  *	1.09a	Pete Zaitcev: Sun SPARC
+  *	1.09b	Jeff Garzik: Modularize, init cleanup
+  *	1.09c	Jeff Garzik: SMP cleanup
+- *	1.10    Paul Barton-Davis: add support for async I/O
++ *	1.10	Paul Barton-Davis: add support for async I/O
+  *	1.10a	Andrea Arcangeli: Alpha updates
+  *	1.10b	Andrew Morton: SMP lock fix
+  *	1.10c	Cesar Barros: SMP locking fixes and cleanup
+  *	1.10d	Paul Gortmaker: delete paranoia check in rtc_exit
+  *	1.10e	Maciej W. Rozycki: Handle DECstation's year weirdness.
+- *      1.11    Takashi Iwai: Kernel access functions
++ *	1.11	Takashi Iwai: Kernel access functions
+  *			      rtc_register/rtc_unregister/rtc_control
+  *      1.11a   Daniele Bellucci: Audit create_proc_read_entry in rtc_init
+- *	1.12	Venkatesh Pallipadi: Hooks for emulating rtc on HPET base-timer
++ *	1.12    Venkatesh Pallipadi: Hooks for emulating rtc on HPET base-timer
+  *		CONFIG_HPET_EMULATE_RTC
++ *	1.12a	Maciej W. Rozycki: Handle memory-mapped chips properly.
+  *	1.12ac	Alan Cox: Allow read access to the day of week register
+  */
+ 
+-#define RTC_VERSION		"1.12ac"
+-
+-#define RTC_IO_EXTENT	0x8
++#define RTC_VERSION		"1.12a"
+ 
+ /*
+  *	Note that *all* calls to CMOS_READ and CMOS_WRITE are done with
+@@ -338,7 +337,15 @@
+ 	if (rtc_has_irq == 0)
+ 		return -EIO;
+ 
+-	if (count < sizeof(unsigned))
++	/*
++	 * Historically this function used to assume that sizeof(unsigned long)
++	 * is the same in userspace and kernelspace.  This lead to problems
++	 * for configurations with multiple ABIs such a the MIPS o32 and 64
++	 * ABIs supported on the same kernel.  So now we support read of both
++	 * 4 and 8 bytes and assume that's the sizeof(unsigned long) in the
++	 * userspace ABI.
++	 */
++	if (count != sizeof(unsigned int) && count !=  sizeof(unsigned long))
+ 		return -EINVAL;
+ 
+ 	add_wait_queue(&rtc_wait, &wait);
+@@ -369,10 +376,12 @@
+ 		schedule();
+ 	} while (1);
+ 
+-	if (count < sizeof(unsigned long))
+-		retval = put_user(data, (unsigned int __user *)buf) ?: sizeof(int); 
++	if (count == sizeof(unsigned int))
++		retval = put_user(data, (unsigned int __user *)buf) ?: sizeof(int);
+ 	else
+ 		retval = put_user(data, (unsigned long __user *)buf) ?: sizeof(long);
++	if (!retval)
++		retval = count;
+  out:
+ 	current->state = TASK_RUNNING;
+ 	remove_wait_queue(&rtc_wait, &wait);
+@@ -924,6 +933,9 @@
+ 	struct sparc_isa_device *isa_dev;
+ #endif
+ #endif
++#ifndef __sparc__
++	void *r;
++#endif
+ 
+ #ifdef __sparc__
+ 	for_each_ebus(ebus) {
+@@ -969,8 +981,13 @@
+ 	}
+ no_irq:
+ #else
+-	if (!request_region(RTC_PORT(0), RTC_IO_EXTENT, "rtc")) {
+-		printk(KERN_ERR "rtc: I/O port %d is not free.\n", RTC_PORT (0));
++	if (RTC_IOMAPPED)
++		r = request_region(RTC_PORT(0), RTC_IO_EXTENT, "rtc");
++	else
++		r = request_mem_region(RTC_PORT(0), RTC_IO_EXTENT, "rtc");
++	if (!r) {
++		printk(KERN_ERR "rtc: I/O resource %lx is not free.\n",
++		       (long)(RTC_PORT(0)));
+ 		return -EIO;
+ 	}
+ 
+@@ -984,7 +1001,10 @@
+ 	if(request_irq(RTC_IRQ, rtc_int_handler_ptr, SA_INTERRUPT, "rtc", NULL)) {
+ 		/* Yeah right, seeing as irq 8 doesn't even hit the bus. */
+ 		printk(KERN_ERR "rtc: IRQ %d is not free.\n", RTC_IRQ);
+-		release_region(RTC_PORT(0), RTC_IO_EXTENT);
++		if (RTC_IOMAPPED)
++			release_region(RTC_PORT(0), RTC_IO_EXTENT);
++		else
++			release_mem_region(RTC_PORT(0), RTC_IO_EXTENT);
+ 		return -EIO;
+ 	}
+ 	hpet_rtc_timer_init();
+@@ -1084,7 +1104,10 @@
+ 	if (rtc_has_irq)
+ 		free_irq (rtc_irq, &rtc_port);
+ #else
+-	release_region (RTC_PORT (0), RTC_IO_EXTENT);
++	if (RTC_IOMAPPED)
++		release_region(RTC_PORT(0), RTC_IO_EXTENT);
++	else
++		release_mem_region(RTC_PORT(0), RTC_IO_EXTENT);
+ #ifdef RTC_IRQ
+ 	if (rtc_has_irq)
+ 		free_irq (RTC_IRQ, NULL);
+diff -Naur linux-2.6.17.orig/drivers/char/sb1250_duart.c linux-2.6.17/drivers/char/sb1250_duart.c
+--- linux-2.6.17.orig/drivers/char/sb1250_duart.c	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/drivers/char/sb1250_duart.c	2006-06-19 18:16:13.000000000 -0700
+@@ -0,0 +1,911 @@
++/*
++ * Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ * 
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
++ */
++
++/* 
++ * Driver support for the on-chip sb1250 dual-channel serial port,
++ * running in asynchronous mode.  Also, support for doing a serial console
++ * on one of those ports 
++ */
++#include <linux/config.h>
++#include <linux/types.h>
++#include <linux/kernel.h>
++#include <linux/serial.h>
++#include <linux/interrupt.h>
++#include <linux/module.h>
++#include <linux/console.h>
++#include <linux/kdev_t.h>
++#include <linux/major.h>
++#include <linux/termios.h>
++#include <linux/spinlock.h>
++#include <linux/irq.h>
++#include <linux/errno.h>
++#include <linux/tty.h>
++#include <linux/sched.h>
++#include <linux/tty_flip.h>
++#include <linux/timer.h>
++#include <linux/init.h>
++#include <linux/mm.h>
++#include <asm/delay.h>
++#include <asm/io.h>
++#include <asm/uaccess.h>
++#include <asm/sibyte/swarm.h>
++#include <asm/sibyte/sb1250.h>
++#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
++#include <asm/sibyte/bcm1480_regs.h>
++#include <asm/sibyte/bcm1480_int.h>
++#elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
++#include <asm/sibyte/sb1250_regs.h>
++#include <asm/sibyte/sb1250_int.h>
++#else
++#error invalid SiByte UART configuation
++#endif
++#include <asm/sibyte/sb1250_uart.h>
++#include <asm/war.h>
++
++#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
++#define UNIT_CHANREG(n,reg)	A_BCM1480_DUART_CHANREG((n),(reg))
++#define UNIT_IMRREG(n)		A_BCM1480_DUART_IMRREG(n)
++#define UNIT_INT(n)		(K_BCM1480_INT_UART_0 + (n))
++#elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
++#define UNIT_CHANREG(n,reg)	A_DUART_CHANREG((n),(reg))
++#define UNIT_IMRREG(n)		A_DUART_IMRREG(n)
++#define UNIT_INT(n)		(K_INT_UART_0 + (n))
++#else
++#error invalid SiByte UART configuation
++#endif
++
++/* Toggle spewing of debugging output */
++#undef DEBUG
++
++#define DEFAULT_CFLAGS          (CS8 | B115200)
++
++#define TX_INTEN          1
++#define DUART_INITIALIZED 2
++
++#define DUART_MAX_LINE 4
++char sb1250_duart_present[DUART_MAX_LINE];
++EXPORT_SYMBOL(sb1250_duart_present);
++
++/*
++ * Still not sure what the termios structures set up here are for, 
++ *  but we have to supply pointers to them to register the tty driver
++ */
++static struct tty_driver *sb1250_duart_driver; //, sb1250_duart_callout_driver;
++
++/*
++ * This lock protects both the open flags for all the uart states as 
++ * well as the reference count for the module
++ */
++static DEFINE_SPINLOCK(open_lock);
++
++typedef struct { 
++	unsigned char       outp_buf[SERIAL_XMIT_SIZE];
++	unsigned int        outp_head;
++	unsigned int        outp_tail;
++	unsigned int        outp_count;
++	spinlock_t          outp_lock;
++	unsigned int        open;
++	unsigned int        line;
++	unsigned int        last_cflags;
++	unsigned long       flags;
++	struct tty_struct   *tty;
++	/* CSR addresses */
++	volatile u32	    *status;
++	volatile u32	    *imr;
++	volatile u32	    *tx_hold;
++	volatile u32	    *rx_hold;
++	volatile u32	    *mode_1;
++	volatile u32	    *mode_2;
++	volatile u32	    *clk_sel;
++	volatile u32	    *cmd;
++} uart_state_t;
++
++static uart_state_t uart_states[DUART_MAX_LINE];
++
++/*
++ * Inline functions local to this module 
++ */
++
++/*
++ * In bug 1956, we get glitches that can mess up uart registers.  This
++ * "write-mode-1 after any register access" is the accepted
++ * workaround.
++ */
++#if SIBYTE_1956_WAR
++static unsigned int last_mode1[DUART_MAX_LINE];
++#endif
++
++static inline u32 READ_SERCSR(volatile u32 *addr, int line)
++{
++	u32 val = csr_in32(addr);
++#if SIBYTE_1956_WAR
++	csr_out32(last_mode1[line], uart_states[line].mode_1);
++#endif
++	return val;
++}
++
++static inline void WRITE_SERCSR(u32 val, volatile u32 *addr, int line)
++{
++	csr_out32(val, addr);
++#if SIBYTE_1956_WAR
++	csr_out32(last_mode1[line], uart_states[line].mode_1);
++#endif
++}
++
++static void init_duart_port(uart_state_t *port, int line)
++{
++	if (!(port->flags & DUART_INITIALIZED)) {
++		port->line = line;
++		port->status = IOADDR(UNIT_CHANREG(line, R_DUART_STATUS));
++		port->imr = IOADDR(UNIT_IMRREG(line));
++		port->tx_hold = IOADDR(UNIT_CHANREG(line, R_DUART_TX_HOLD));
++		port->rx_hold = IOADDR(UNIT_CHANREG(line, R_DUART_RX_HOLD));
++		port->mode_1 = IOADDR(UNIT_CHANREG(line, R_DUART_MODE_REG_1));
++		port->mode_2 = IOADDR(UNIT_CHANREG(line, R_DUART_MODE_REG_2));
++		port->clk_sel = IOADDR(UNIT_CHANREG(line, R_DUART_CLK_SEL));
++		port->cmd = IOADDR(UNIT_CHANREG(line, R_DUART_CMD));
++		port->flags |= DUART_INITIALIZED;
++	}
++}
++
++/*
++ * Mask out the passed interrupt lines at the duart level.  This should be
++ * called while holding the associated outp_lock.
++ */
++static inline void duart_mask_ints(unsigned int line, unsigned int mask)
++{
++	uart_state_t *port = uart_states + line;
++	u64 tmp = READ_SERCSR(port->imr, line);
++	WRITE_SERCSR(tmp & ~mask, port->imr, line);
++}
++
++	
++/* Unmask the passed interrupt lines at the duart level */
++static inline void duart_unmask_ints(unsigned int line, unsigned int mask)
++{
++	uart_state_t *port = uart_states + line;
++	u64 tmp = READ_SERCSR(port->imr, line);
++	WRITE_SERCSR(tmp | mask, port->imr, line);
++}
++
++static inline void transmit_char_pio(uart_state_t *us)
++{
++	struct tty_struct *tty = us->tty;
++	int blocked = 0;
++
++	if (spin_trylock(&us->outp_lock)) {
++		for (;;) {
++			if (!(READ_SERCSR(us->status, us->line) & M_DUART_TX_RDY))
++				break;
++			if (us->outp_count <= 0 || tty->stopped || tty->hw_stopped) {
++				break;
++			} else {
++				WRITE_SERCSR(us->outp_buf[us->outp_head],
++					     us->tx_hold, us->line);
++				us->outp_head = (us->outp_head + 1) & (SERIAL_XMIT_SIZE-1);
++				if (--us->outp_count <= 0)
++					break;
++			}
++			udelay(10);
++		}
++		spin_unlock(&us->outp_lock);
++	} else {
++		blocked = 1;
++	}
++
++	if (!us->outp_count || tty->stopped ||
++	    tty->hw_stopped || blocked) {
++		us->flags &= ~TX_INTEN;
++		duart_mask_ints(us->line, M_DUART_IMR_TX);
++	}
++
++      	if (us->open &&
++	    (us->outp_count < (SERIAL_XMIT_SIZE/2))) {
++		/*
++		 * We told the discipline at one point that we had no
++		 * space, so it went to sleep.  Wake it up when we hit
++		 * half empty
++		 */
++		if ((tty->flags & (1 << TTY_DO_WRITE_WAKEUP)) &&
++		    tty->ldisc.write_wakeup)
++			tty->ldisc.write_wakeup(tty);
++		wake_up_interruptible(&tty->write_wait);
++	}
++}
++
++/* 
++ * Generic interrupt handler for both channels.  dev_id is a pointer
++ * to the proper uart_states structure, so from that we can derive 
++ * which port interrupted 
++ */
++
++static irqreturn_t duart_int(int irq, void *dev_id, struct pt_regs *regs)
++{
++	uart_state_t *us = (uart_state_t *)dev_id;
++	struct tty_struct *tty = us->tty;
++	unsigned int status = READ_SERCSR(us->status, us->line);
++
++	pr_debug("DUART INT\n");
++
++	if (status & M_DUART_RX_RDY) {
++		int counter = 2048;
++		unsigned int ch;
++
++		if (status & M_DUART_OVRUN_ERR)
++			tty_insert_flip_char(tty, 0, TTY_OVERRUN);
++		if (status & M_DUART_PARITY_ERR) {
++			printk("Parity error!\n");
++		} else if (status & M_DUART_FRM_ERR) {
++			printk("Frame error!\n");
++		}
++
++		while (counter > 0) {
++			if (!(READ_SERCSR(us->status, us->line) & M_DUART_RX_RDY))
++				break;
++			ch = READ_SERCSR(us->rx_hold, us->line);
++			tty_insert_flip_char(tty, ch, 0);
++			udelay(1);
++			counter--;
++		}
++		tty_flip_buffer_push(tty);
++	}
++
++	if (status & M_DUART_TX_RDY) {
++		transmit_char_pio(us);
++	}
++
++	return IRQ_HANDLED;
++}
++
++/*
++ *  Actual driver functions
++ */
++
++/* Return the number of characters we can accomodate in a write at this instant */
++static int duart_write_room(struct tty_struct *tty)
++{
++	uart_state_t *us = (uart_state_t *) tty->driver_data;
++	int retval;
++
++	retval = SERIAL_XMIT_SIZE - us->outp_count;
++
++	pr_debug("duart_write_room called, returning %i\n", retval);
++
++	return retval;
++}
++
++/* memcpy the data from src to destination, but take extra care if the
++   data is coming from user space */
++static inline int copy_buf(char *dest, const char *src, int size, int from_user) 
++{
++	if (from_user) {
++		(void) copy_from_user(dest, src, size); 
++	} else {
++		memcpy(dest, src, size);
++	}
++	return size;
++}
++
++/*
++ * Buffer up to count characters from buf to be written.  If we don't have
++ * other characters buffered, enable the tx interrupt to start sending
++ */
++static int duart_write(struct tty_struct *tty, const unsigned char *buf,
++		       int count)
++{
++	uart_state_t *us;
++	int c, t, total = 0;
++	unsigned long flags;
++
++	if (!tty) return 0;
++
++	us = tty->driver_data;
++	if (!us) return 0;
++
++	pr_debug("duart_write called for %i chars by %i (%s)\n", count, current->pid, current->comm);
++
++	spin_lock_irqsave(&us->outp_lock, flags);
++
++	for (;;) {
++		c = count;
++
++		t = SERIAL_XMIT_SIZE - us->outp_tail;
++		if (t < c) c = t;
++
++		t = SERIAL_XMIT_SIZE - 1 - us->outp_count;
++		if (t < c) c = t;
++
++		if (c <= 0) break;
++
++		memcpy(us->outp_buf + us->outp_tail, buf, c);
++
++		us->outp_count += c;
++		us->outp_tail = (us->outp_tail + c) & (SERIAL_XMIT_SIZE - 1);
++		buf += c;
++		count -= c;
++		total += c;
++	}
++
++	spin_unlock_irqrestore(&us->outp_lock, flags);
++
++	if (us->outp_count && !tty->stopped && 
++	    !tty->hw_stopped && !(us->flags & TX_INTEN)) {
++		us->flags |= TX_INTEN;
++		duart_unmask_ints(us->line, M_DUART_IMR_TX);
++	}
++
++	return total;
++}
++
++
++/* Buffer one character to be written.  If there's not room for it, just drop
++   it on the floor.  This is used for echo, among other things */
++static void duart_put_char(struct tty_struct *tty, u_char ch)
++{
++	uart_state_t *us = (uart_state_t *) tty->driver_data;
++	unsigned long flags;
++
++	pr_debug("duart_put_char called.  Char is %x (%c)\n", (int)ch, ch);
++
++	spin_lock_irqsave(&us->outp_lock, flags);
++
++	if (us->outp_count == SERIAL_XMIT_SIZE) {
++		spin_unlock_irqrestore(&us->outp_lock, flags);
++		return;
++	}
++
++	us->outp_buf[us->outp_tail] = ch;
++	us->outp_tail = (us->outp_tail + 1) &(SERIAL_XMIT_SIZE-1);
++	us->outp_count++;
++
++	spin_unlock_irqrestore(&us->outp_lock, flags);
++}
++
++static void duart_flush_chars(struct tty_struct * tty)
++{
++	uart_state_t *port;
++
++	if (!tty) return;
++
++	port = tty->driver_data;
++
++	if (!port) return;
++
++	if (port->outp_count <= 0 || tty->stopped || tty->hw_stopped) {
++		return;
++	}
++
++	port->flags |= TX_INTEN;
++	duart_unmask_ints(port->line, M_DUART_IMR_TX);
++}
++
++/* Return the number of characters in the output buffer that have yet to be 
++   written */
++static int duart_chars_in_buffer(struct tty_struct *tty)
++{
++	uart_state_t *us = (uart_state_t *) tty->driver_data;
++	int retval;
++
++	retval = us->outp_count;
++
++	pr_debug("duart_chars_in_buffer returning %i\n", retval);
++
++	return retval;
++}
++
++/* Kill everything we haven't yet shoved into the FIFO.  Turn off the
++   transmit interrupt since we've nothing more to transmit */
++static void duart_flush_buffer(struct tty_struct *tty)
++{
++	uart_state_t *us = (uart_state_t *) tty->driver_data;
++	unsigned long flags;
++
++	pr_debug("duart_flush_buffer called\n");
++	spin_lock_irqsave(&us->outp_lock, flags);
++	us->outp_head = us->outp_tail = us->outp_count = 0;
++	spin_unlock_irqrestore(&us->outp_lock, flags);
++
++	wake_up_interruptible(&us->tty->write_wait);
++	if ((tty->flags & (1 << TTY_DO_WRITE_WAKEUP)) &&
++	    tty->ldisc.write_wakeup)
++		tty->ldisc.write_wakeup(tty);
++}
++
++
++/* See sb1250 user manual for details on these registers */
++static inline void duart_set_cflag(unsigned int line, unsigned int cflag)
++{
++	unsigned int mode_reg1 = 0, mode_reg2 = 0;
++	unsigned int clk_divisor;
++	uart_state_t *port = uart_states + line;
++
++	switch (cflag & CSIZE) {
++	case CS7:
++		mode_reg1 |= V_DUART_BITS_PER_CHAR_7;
++		
++	default:
++		/* We don't handle CS5 or CS6...is there a way we're supposed to flag this? 
++		   right now we just force them to CS8 */
++		mode_reg1 |= 0x0;
++		break;
++	}
++	if (cflag & CSTOPB) {
++	        mode_reg2 |= M_DUART_STOP_BIT_LEN_2;
++	}
++	if (!(cflag & PARENB)) {
++	        mode_reg1 |= V_DUART_PARITY_MODE_NONE;
++	}
++	if (cflag & PARODD) {
++		mode_reg1 |= M_DUART_PARITY_TYPE_ODD;
++	}
++	
++	/* Formula for this is (5000000/baud)-1, but we saturate
++	   at 12 bits, which means we can't actually do anything less
++	   that 1200 baud */
++	switch (cflag & CBAUD) {
++	case B200:	
++	case B300:	
++	case B1200:	clk_divisor = 4095;		break;
++	case B1800:	clk_divisor = 2776;		break;
++	case B2400:	clk_divisor = 2082;		break;
++	case B4800:	clk_divisor = 1040;		break;
++	default:
++	case B9600:	clk_divisor = 519;		break;
++	case B19200:	clk_divisor = 259;		break;
++	case B38400:	clk_divisor = 129;		break;
++	case B57600:	clk_divisor = 85;		break;
++	case B115200:	clk_divisor = 42;		break;
++	}
++	WRITE_SERCSR(mode_reg1, port->mode_1, port->line);
++	WRITE_SERCSR(mode_reg2, port->mode_2, port->line);
++	WRITE_SERCSR(clk_divisor, port->clk_sel, port->line);
++	port->last_cflags = cflag;
++}
++
++
++/* Handle notification of a termios change.  */
++static void duart_set_termios(struct tty_struct *tty, struct termios *old)
++{
++	uart_state_t *us = (uart_state_t *) tty->driver_data;
++
++	pr_debug("duart_set_termios called by %i (%s)\n", current->pid, current->comm);
++	if (old && tty->termios->c_cflag == old->c_cflag)
++		return;
++	duart_set_cflag(us->line, tty->termios->c_cflag);
++}
++
++static int get_serial_info(uart_state_t *us, struct serial_struct * retinfo) {
++
++	struct serial_struct tmp;
++
++	memset(&tmp, 0, sizeof(tmp));
++
++	tmp.type=PORT_SB1250;
++	tmp.line=us->line;
++	tmp.port=UNIT_CHANREG(tmp.line,0);
++	tmp.irq=UNIT_INT(tmp.line);
++	tmp.xmit_fifo_size=16; /* fixed by hw */
++	tmp.baud_base=5000000;
++	tmp.io_type=SERIAL_IO_MEM;
++
++	if (copy_to_user(retinfo,&tmp,sizeof(*retinfo)))
++		return -EFAULT;
++
++	return 0;
++}
++
++static int duart_ioctl(struct tty_struct *tty, struct file * file,
++		       unsigned int cmd, unsigned long arg)
++{
++	uart_state_t *us = (uart_state_t *) tty->driver_data;
++
++/*	if (serial_paranoia_check(info, tty->device, "rs_ioctl"))
++	return -ENODEV;*/
++	switch (cmd) {
++	case TIOCMGET:
++		printk("Ignoring TIOCMGET\n");
++		break;
++	case TIOCMBIS:
++		printk("Ignoring TIOCMBIS\n");
++		break;
++	case TIOCMBIC:
++		printk("Ignoring TIOCMBIC\n");
++		break;
++	case TIOCMSET:
++		printk("Ignoring TIOCMSET\n");
++		break;
++	case TIOCGSERIAL:
++		return get_serial_info(us,(struct serial_struct *) arg);
++	case TIOCSSERIAL:
++		printk("Ignoring TIOCSSERIAL\n");
++		break;
++	case TIOCSERCONFIG:
++		printk("Ignoring TIOCSERCONFIG\n");
++		break;
++	case TIOCSERGETLSR: /* Get line status register */
++		printk("Ignoring TIOCSERGETLSR\n");
++		break;
++	case TIOCSERGSTRUCT:
++		printk("Ignoring TIOCSERGSTRUCT\n");
++		break;
++	case TIOCMIWAIT:
++		printk("Ignoring TIOCMIWAIT\n");
++		break;
++	case TIOCGICOUNT:
++		printk("Ignoring TIOCGICOUNT\n");
++		break;
++	case TIOCSERGWILD:
++		printk("Ignoring TIOCSERGWILD\n");
++		break;
++	case TIOCSERSWILD:
++		printk("Ignoring TIOCSERSWILD\n");
++		break;
++	default:
++		break;
++	}
++//	printk("Ignoring IOCTL %x from pid %i (%s)\n", cmd, current->pid, current->comm);
++	return -ENOIOCTLCMD;
++}
++
++/* XXXKW locking? */
++static void duart_start(struct tty_struct *tty)
++{
++	uart_state_t *us = (uart_state_t *) tty->driver_data;
++
++	pr_debug("duart_start called\n");
++
++	if (us->outp_count && !(us->flags & TX_INTEN)) {
++		us->flags |= TX_INTEN;
++		duart_unmask_ints(us->line, M_DUART_IMR_TX);
++	}
++}
++
++/* XXXKW locking? */
++static void duart_stop(struct tty_struct *tty)
++{
++	uart_state_t *us = (uart_state_t *) tty->driver_data;
++
++	pr_debug("duart_stop called\n");
++
++	if (us->outp_count && (us->flags & TX_INTEN)) {
++		us->flags &= ~TX_INTEN;
++		duart_mask_ints(us->line, M_DUART_IMR_TX);
++	}
++}
++
++/* Not sure on the semantics of this; are we supposed to wait until the stuff
++   already in the hardware FIFO drains, or are we supposed to wait until 
++   we've drained the output buffer, too?  I'm assuming the former, 'cause thats
++   what the other drivers seem to assume 
++*/
++
++static void duart_wait_until_sent(struct tty_struct *tty, int timeout)
++{
++	uart_state_t *us = (uart_state_t *) tty->driver_data;
++	unsigned long orig_jiffies;
++
++	orig_jiffies = jiffies;
++	pr_debug("duart_wait_until_sent(%d)+\n", timeout);
++	while (!(READ_SERCSR(us->status, us->line) & M_DUART_TX_EMT)) {
++		set_current_state(TASK_INTERRUPTIBLE);
++	 	schedule_timeout(1);
++		if (signal_pending(current))
++			break;
++		if (timeout && time_after(jiffies, orig_jiffies + timeout))
++			break;
++	}
++	pr_debug("duart_wait_until_sent()-\n");
++}
++
++/*
++ * duart_hangup() --- called by tty_hangup() when a hangup is signaled.
++ */
++static void duart_hangup(struct tty_struct *tty)
++{
++	uart_state_t *us = (uart_state_t *) tty->driver_data;
++
++	duart_flush_buffer(tty);
++	us->open = 0;
++	us->tty = 0;
++}
++
++/*
++ * Open a tty line.  Note that this can be called multiple times, so ->open can
++ * be >1.  Only set up the tty struct if this is a "new" open, e.g. ->open was
++ * zero
++ */
++static int duart_open(struct tty_struct *tty, struct file *filp)
++{
++	uart_state_t *us;
++	unsigned int line = tty->index;
++	unsigned long flags;
++
++	if ((line >= tty->driver->num) || !sb1250_duart_present[line])
++		return -ENODEV;
++
++	pr_debug("duart_open called by %i (%s), tty is %p, rw is %p, ww is %p\n",
++	       current->pid, current->comm, tty, tty->read_wait,
++	       tty->write_wait);
++
++	us = uart_states + line;
++	tty->driver_data = us;
++
++	spin_lock_irqsave(&open_lock, flags);
++	if (!us->open) {
++		us->tty = tty;
++		us->tty->termios->c_cflag = us->last_cflags;
++	}
++	us->open++;
++	us->flags &= ~TX_INTEN;
++	duart_unmask_ints(line, M_DUART_IMR_RX);
++	spin_unlock_irqrestore(&open_lock, flags);
++
++	return 0;
++}
++
++
++/*
++ * Close a reference count out.  If reference count hits zero, null the
++ * tty, kill the interrupts.  The tty_io driver is responsible for making
++ * sure we've cleared out our internal buffers before calling close()
++ */
++static void duart_close(struct tty_struct *tty, struct file *filp)
++{
++	uart_state_t *us = (uart_state_t *) tty->driver_data;
++	unsigned long flags;
++
++	pr_debug("duart_close called by %i (%s)\n", current->pid, current->comm);
++
++	if (!us || !us->open)
++		return;
++
++	spin_lock_irqsave(&open_lock, flags);
++	if (tty_hung_up_p(filp)) {
++		spin_unlock_irqrestore(&open_lock, flags);
++		return;
++	}
++
++	if (--us->open < 0) {
++		us->open = 0;
++		printk(KERN_ERR "duart: bad open count: %d\n", us->open);
++	}
++	if (us->open) {
++		spin_unlock_irqrestore(&open_lock, flags);
++		return;
++	}
++
++	spin_unlock_irqrestore(&open_lock, flags);
++
++	tty->closing = 1;
++
++	/* Stop accepting input */
++	duart_mask_ints(us->line, M_DUART_IMR_RX);
++	/* Wait for FIFO to drain */
++	while (!(READ_SERCSR(us->status, us->line) & M_DUART_TX_EMT))
++		;
++
++	if (tty->driver->flush_buffer)
++		tty->driver->flush_buffer(tty);
++	if (tty->ldisc.flush_buffer)
++		tty->ldisc.flush_buffer(tty);
++	tty->closing = 0;
++}
++
++
++static struct tty_operations duart_ops = {
++        .open   = duart_open,
++        .close = duart_close,
++        .write = duart_write,
++        .put_char = duart_put_char,
++        .flush_chars = duart_flush_chars,
++        .write_room = duart_write_room,
++        .chars_in_buffer = duart_chars_in_buffer,
++        .flush_buffer = duart_flush_buffer,
++        .ioctl = duart_ioctl,
++//        .throttle = duart_throttle,
++//        .unthrottle = duart_unthrottle,
++        .set_termios = duart_set_termios,
++        .stop = duart_stop,
++        .start = duart_start,
++        .hangup = duart_hangup,
++	.wait_until_sent = duart_wait_until_sent,
++};
++
++/* Initialize the sb1250_duart_present array based on SOC type.  */
++static void __init sb1250_duart_init_present_lines(void)
++{
++	int i, max_lines;
++
++	/* Set the number of available units based on the SOC type.  */
++	switch (soc_type) {
++	case K_SYS_SOC_TYPE_BCM1x55:
++	case K_SYS_SOC_TYPE_BCM1x80:
++		max_lines = 4;
++		break;
++	default:
++		/* Assume at least two serial ports at the normal address.  */
++		max_lines = 2;
++		break;
++	}
++	if (max_lines > DUART_MAX_LINE)
++		max_lines = DUART_MAX_LINE;
++
++	for (i = 0; i < max_lines; i++)
++		sb1250_duart_present[i] = 1;
++}
++
++/* Set up the driver and register it, register the UART interrupts.  This
++   is called from tty_init, or as a part of the module init */
++static int __init sb1250_duart_init(void) 
++{
++	int i;
++
++	sb1250_duart_init_present_lines();
++
++	sb1250_duart_driver = alloc_tty_driver(DUART_MAX_LINE);
++	if (!sb1250_duart_driver)
++		return -ENOMEM;
++
++	sb1250_duart_driver->owner = THIS_MODULE;
++	sb1250_duart_driver->name = "duart";
++	sb1250_duart_driver->devfs_name = "duart/";
++	sb1250_duart_driver->major = TTY_MAJOR;
++	sb1250_duart_driver->minor_start = SB1250_DUART_MINOR_BASE;
++	sb1250_duart_driver->type            = TTY_DRIVER_TYPE_SERIAL;
++	sb1250_duart_driver->subtype         = SERIAL_TYPE_NORMAL;
++	sb1250_duart_driver->init_termios    = tty_std_termios;
++	sb1250_duart_driver->flags           = TTY_DRIVER_REAL_RAW;
++	tty_set_operations(sb1250_duart_driver, &duart_ops);
++
++	for (i=0; i<DUART_MAX_LINE; i++) {
++		uart_state_t *port = uart_states + i;
++
++		if (!sb1250_duart_present[i])
++			continue;
++
++		init_duart_port(port, i);
++		spin_lock_init(&port->outp_lock);
++		duart_mask_ints(i, M_DUART_IMR_ALL);
++		if (request_irq(UNIT_INT(i), duart_int, 0, "uart", port)) {
++			panic("Couldn't get uart0 interrupt line");
++		}
++		__raw_writeq(M_DUART_RX_EN|M_DUART_TX_EN,
++			     IOADDR(UNIT_CHANREG(i, R_DUART_CMD)));
++		duart_set_cflag(i, DEFAULT_CFLAGS);
++	}
++
++	/* Interrupts are now active, our ISR can be called. */
++
++	if (tty_register_driver(sb1250_duart_driver)) {
++		printk(KERN_ERR "Couldn't register sb1250 duart serial driver\n");
++		put_tty_driver(sb1250_duart_driver);
++		return 1;
++	}
++	return 0;
++}
++
++/* Unload the driver.  Unregister stuff, get ready to go away */
++static void __exit sb1250_duart_fini(void)
++{
++	unsigned long flags;
++	int i;
++
++	local_irq_save(flags);
++	tty_unregister_driver(sb1250_duart_driver);
++	put_tty_driver(sb1250_duart_driver);
++
++	for (i=0; i<DUART_MAX_LINE; i++) {
++		if (!sb1250_duart_present[i])
++			continue;
++		free_irq(UNIT_INT(i), &uart_states[i]);
++		disable_irq(UNIT_INT(i));
++	}
++	local_irq_restore(flags);
++}
++
++module_init(sb1250_duart_init);
++module_exit(sb1250_duart_fini);
++MODULE_DESCRIPTION("SB1250 Duart serial driver");
++MODULE_AUTHOR("Broadcom Corp.");
++
++#ifdef CONFIG_SIBYTE_SB1250_DUART_CONSOLE
++
++/*
++ * Serial console stuff.  Very basic, polling driver for doing serial
++ * console output.  The console_sem is held by the caller, so we
++ * shouldn't be interrupted for more console activity.
++ * XXXKW What about getting interrupted by uart driver activity?
++ */
++
++void serial_outc(unsigned char c, int line)
++{
++	uart_state_t *port = uart_states + line;
++	while (!(READ_SERCSR(port->status, line) & M_DUART_TX_RDY)) ;
++	WRITE_SERCSR(c, port->tx_hold, line);
++	while (!(READ_SERCSR(port->status, port->line) & M_DUART_TX_EMT)) ;
++}
++
++static void ser_console_write(struct console *cons, const char *s,
++	unsigned int count)
++{
++	int line = cons->index;
++	uart_state_t *port = uart_states + line;
++	u32 imr;
++
++	imr = READ_SERCSR(port->imr, line);
++	WRITE_SERCSR(0, port->imr, line);
++	while (count--) {
++		if (*s == '\n')
++			serial_outc('\r', line);
++		serial_outc(*s++, line);
++    	}
++	WRITE_SERCSR(imr, port->imr, line);
++}
++
++static struct tty_driver *ser_console_device(struct console *c, int *index)
++{
++	*index = c->index;
++	return sb1250_duart_driver;
++}
++
++static int ser_console_setup(struct console *cons, char *str)
++{
++	int i;
++
++	sb1250_duart_init_present_lines();
++
++	for (i=0; i<DUART_MAX_LINE; i++) {
++		uart_state_t *port = uart_states + i;
++
++		if (!sb1250_duart_present[i])
++			continue;
++
++		init_duart_port(port, i);
++#if SIBYTE_1956_WAR
++		last_mode1[i] = V_DUART_PARITY_MODE_NONE|V_DUART_BITS_PER_CHAR_8;
++#endif
++		WRITE_SERCSR(V_DUART_PARITY_MODE_NONE|V_DUART_BITS_PER_CHAR_8,
++			     port->mode_1, i);
++		WRITE_SERCSR(M_DUART_STOP_BIT_LEN_1,
++			     port->mode_2, i);
++		WRITE_SERCSR(V_DUART_BAUD_RATE(115200),
++			     port->clk_sel, i);
++		WRITE_SERCSR(M_DUART_RX_EN|M_DUART_TX_EN,
++			     port->cmd, i);
++	}
++	return 0;
++}
++
++static struct console sb1250_ser_cons = {
++	.name		= "duart",
++	.write		= ser_console_write,
++	.device		= ser_console_device,
++	.setup		= ser_console_setup,
++	.flags		= CON_PRINTBUFFER,
++	.index		= -1,
++};
++
++static int __init sb1250_serial_console_init(void)
++{
++	register_console(&sb1250_ser_cons);
++	return 0;
++}
++
++console_initcall(sb1250_serial_console_init);
++
++#endif /* CONFIG_SIBYTE_SB1250_DUART_CONSOLE */
+diff -Naur linux-2.6.17.orig/drivers/ide/mips/Makefile linux-2.6.17/drivers/ide/mips/Makefile
+--- linux-2.6.17.orig/drivers/ide/mips/Makefile	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/drivers/ide/mips/Makefile	2006-06-19 18:16:13.000000000 -0700
+@@ -1,4 +1,4 @@
+ obj-$(CONFIG_BLK_DEV_IDE_SWARM)		+= swarm.o
+ obj-$(CONFIG_BLK_DEV_IDE_AU1XXX)	+= au1xxx-ide.o
+ 
+-EXTRA_CFLAGS    := -Idrivers/ide
++CFLAGS_au1xxx-ide.o := -Idrivers/ide
+diff -Naur linux-2.6.17.orig/drivers/mtd/devices/docprobe.c linux-2.6.17/drivers/mtd/devices/docprobe.c
+--- linux-2.6.17.orig/drivers/mtd/devices/docprobe.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/drivers/mtd/devices/docprobe.c	2006-06-19 18:16:13.000000000 -0700
+@@ -84,10 +84,10 @@
+ 	0xe4000000,
+ #elif defined(CONFIG_MOMENCO_OCELOT)
+ 	0x2f000000,
+-        0xff000000,
++	0xff000000,
+ #elif defined(CONFIG_MOMENCO_OCELOT_G) || defined (CONFIG_MOMENCO_OCELOT_C)
+-        0xff000000,
+-##else
++	0xff000000,
++#else
+ #warning Unknown architecture for DiskOnChip. No default probe locations defined
+ #endif
+ 	0xffffffff };
+diff -Naur linux-2.6.17.orig/drivers/mtd/devices/Kconfig linux-2.6.17/drivers/mtd/devices/Kconfig
+--- linux-2.6.17.orig/drivers/mtd/devices/Kconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/drivers/mtd/devices/Kconfig	2006-06-19 18:16:13.000000000 -0700
+@@ -47,6 +47,11 @@
+ 	  accelerator.  Say Y here if you have a DECstation 5000/2x0 or a
+ 	  DECsystem 5900 equipped with such a module.
+ 
++	  If you want to compile this driver as a module ( = code which can be
++	  inserted in and removed from the running kernel whenever you want),
++	  say M here and read <file:Documentation/modules.txt>.  The module will
++	  be called ms02-nv.o.
++
+ config MTD_DATAFLASH
+ 	tristate "Support for AT45xxx DataFlash"
+ 	depends on MTD && SPI_MASTER && EXPERIMENTAL
+diff -Naur linux-2.6.17.orig/drivers/mtd/maps/Kconfig linux-2.6.17/drivers/mtd/maps/Kconfig
+--- linux-2.6.17.orig/drivers/mtd/maps/Kconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/drivers/mtd/maps/Kconfig	2006-06-19 18:16:13.000000000 -0700
+@@ -200,8 +200,8 @@
+ 	  Support for the flash chip on Tsunami TIG bus.
+ 
+ config MTD_LASAT
+-	tristate "Flash chips on LASAT board"
+-	depends on LASAT
++	tristate "LASAT flash device"
++	depends on LASAT && MTD_CFI
+ 	help
+ 	  Support for the flash chips on the Lasat 100 and 200 boards.
+ 
+@@ -299,6 +299,18 @@
+ 	  Mapping for the Flaga digital module. If you don't have one, ignore
+ 	  this setting.
+ 
++config MTD_XXS1500
++	tristate "MyCable XXS1500 Flash device"
++	depends on MIPS && MIPS_XXS1500
++	help
++	  Flash memory access on MyCable XXS1500 Board
++
++config MTD_MTX1
++	tristate "4-G Systems MTX-1 Flash device"
++	depends on MIPS && MIPS_MTX1
++	help
++	  Flash memory access on 4-G Systems MTX-1 Board
++
+ config MTD_BEECH
+ 	tristate "CFI Flash device mapped on IBM 405LP Beech"
+ 	depends on MTD_CFI && BEECH
+diff -Naur linux-2.6.17.orig/drivers/mtd/maps/lasat.c linux-2.6.17/drivers/mtd/maps/lasat.c
+--- linux-2.6.17.orig/drivers/mtd/maps/lasat.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/drivers/mtd/maps/lasat.c	2006-06-19 18:16:13.000000000 -0700
+@@ -7,7 +7,7 @@
+  * modify it under the terms of the GNU General Public License version
+  * 2 as published by the Free Software Foundation.
+  *
+- * $Id: lasat.c,v 1.9 2004/11/04 13:24:15 gleixner Exp $
++ * $Id: lasat.c,v 1.7 2004/07/12 21:59:44 dwmw2 Exp $
+  *
+  */
+ 
+@@ -50,7 +50,7 @@
+ 	ENABLE_VPP((&lasat_map));
+ 
+ 	lasat_map.phys = lasat_flash_partition_start(LASAT_MTD_BOOTLOADER);
+-	lasat_map.virt = ioremap_nocache(
++	lasat_map.virt = (unsigned long)ioremap_nocache(
+ 		        lasat_map.phys, lasat_board_info.li_flash_size);
+ 	lasat_map.size = lasat_board_info.li_flash_size;
+ 
+diff -Naur linux-2.6.17.orig/drivers/net/big_sur_ge.c linux-2.6.17/drivers/net/big_sur_ge.c
+--- linux-2.6.17.orig/drivers/net/big_sur_ge.c	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/drivers/net/big_sur_ge.c	2006-06-19 18:16:13.000000000 -0700
+@@ -0,0 +1,2005 @@
++/*
++ * drivers/net/big_sur_ge.c - Driver for PMC-Sierra Big Sur ethernet ports
++ *
++ * Copyright (C) 2003 PMC-Sierra Inc.
++ * Author : Manish Lachwani (lachwani@pmc-sierra.com)
++ * Copyright (C) 2003 Ralf Baechle (ralf@linux-mips.org)
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
++ *
++ */
++
++/*************************************************************************
++ * Description :
++ *
++ * The driver has three modes of operation: FIFO non-DMA, Simple DMA
++ * and SG DMA. There is also a Polled mode and an Interrupt mode of
++ * operation. SG DMA should do zerocopy and check offload. Probably,
++ * zerocopy on the Rx might also work. Simple DMA is the non-zerocpy
++ * case on the Tx and the Rx.
++ *
++ * We turn on Simple DMA and interrupt mode. Although, support has been
++ * added for the SG mode also but not for the polled mode. This is a
++ * Fast Ethernet driver although there will be support for Gigabit soon.
++ *
++ * The driver is divided into two parts: Hardware dependent and a
++ * Hardware independent. There is currently no support for checksum offload
++ * zerocopy and Rx NAPI. There is support for Interrupt Mitigation.
++ ****************************************************************************/
++
++/*************************************************************
++ * Hardware Indepenent Part of the driver
++ *************************************************************/
++
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/netdevice.h>
++#include <linux/etherdevice.h>
++#include <linux/skbuff.h>
++#include <linux/mii.h>
++#include <asm/io.h>
++#include <asm/irq.h>
++
++#include "big_sur_ge.h"
++
++#define TX_TIMEOUT (60*HZ)	/* Transmission timeout is 60 seconds. */
++
++static struct net_device *dev_list = NULL;
++static DEFINE_SPINLOCK(dev_lock);
++
++typedef enum DUPLEX { UNKNOWN, HALF_DUPLEX, FULL_DUPLEX } DUPLEX;
++
++/* Big Sur Ethernet MAC structure */
++struct big_sur_ge_enet {
++	struct net_device_stats stats;	/* Statistics for this device */
++	struct net_device *next_dev;	/* The next device in dev_list */
++	struct timer_list phy_timer;	/* PHY monitoring timer */
++	u32 index;		/* Which interface is this */
++	u32 save_base_address;	/* Saved physical base address */
++	struct sk_buff *saved_skb;	/* skb being transmitted */
++	spinlock_t lock;	/* For atomic access to saved_skb */
++	u8 mii_addr;		/* The MII address of the PHY */
++	big_sur_ge emac;	/* GE driver structure */
++};
++
++/* Manish : For testing purposes only */
++static unsigned char big_sur_mac_addr_base[6] = "00:11:22:33:44:55";
++
++/*********************************************************************
++ * Function Prototypes (whole bunch of them)
++ *********************************************************************/
++unsigned long big_sur_ge_dma_control(xdma_channel *);
++void big_sur_ge_dma_reset(xdma_channel *);
++static void handle_fifo_intr(big_sur_ge *);
++void big_sur_ge_check_fifo_recv_error(big_sur_ge *);
++void big_sur_ge_check_fifo_send_error(big_sur_ge *);
++static int big_sur_ge_config_fifo(big_sur_ge *);
++big_sur_ge_config *big_sur_ge_lookup_config(unsigned int);
++static int big_sur_ge_config_dma(big_sur_ge *);
++void big_sur_ge_enet_reset(big_sur_ge *);
++void big_sur_ge_check_mac_error(big_sur_ge *, unsigned long);
++
++/*********************************************************************
++ * DMA Channel Initialization
++ **********************************************************************/
++static int big_sur_ge_dma_init(xdma_channel * dma, unsigned long base_address)
++{
++	dma->reg_base_address = base_address;
++	dma->get_ptr = NULL;
++	dma->put_ptr = NULL;
++	dma->commit_ptr = NULL;
++	dma->last_ptr = NULL;
++	dma->total_desc_count = (unsigned long) NULL;
++	dma->active_desc_count = (unsigned long) NULL;
++	dma->ready = 1;		/* DMA channel is ready */
++
++	big_sur_ge_dma_reset(dma);
++
++	return 0;
++}
++
++/*********************************************************************
++ * Is the DMA channel ready yet ?
++ **********************************************************************/
++static int big_sur_ge_dma_ready(xdma_channel * dma)
++{
++	return dma->ready == 1;
++}
++
++/*********************************************************************
++ * Perform the self test on the DMA channel
++ **********************************************************************/
++#define BIG_SUR_GE_CONTROL_REG_RESET_MASK	0x98000000
++
++static int big_sur_ge_dma_self_test(xdma_channel * dma)
++{
++	unsigned long reg_data;
++
++	big_sur_ge_dma_reset(dma);
++
++	reg_data = big_sur_ge_dma_control(dma);
++	if (reg_data != BIG_SUR_GE_CONTROL_REG_RESET_MASK) {
++		printk(KERN_ERR "DMA Channel Self Test Failed \n");
++		return -1;
++	}
++
++	return 0;
++}
++
++/*********************************************************************
++ * Reset the DMA channel
++ **********************************************************************/
++static void big_sur_ge_dma_reset(xdma_channel * dma)
++{
++	BIG_SUR_GE_WRITE(dma->reg_base_address + BIG_SUR_GE_RST_REG_OFFSET,
++			 BIG_SUR_GE_RESET_MASK);
++}
++
++/*********************************************************************
++ * Get control of the DMA channel
++ **********************************************************************/
++static unsigned long big_sur_ge_dma_control(xdma_channel * dma)
++{
++	return BIG_SUR_GE_READ(dma->reg_base_address +
++			       BIG_SUR_GE_DMAC_REG_OFFSET);
++}
++
++/*********************************************************************
++ * Set control of the DMA channel
++ **********************************************************************/
++static void big_sur_ge_set_dma_control(xdma_channel * dma, unsigned long control)
++{
++	BIG_SUR_GE_WRITE(dma->reg_base_address +
++			 BIG_SUR_GE_DMAC_REG_OFFSET, control);
++}
++
++/*********************************************************************
++ * Get the status of the DMA channel
++ *********************************************************************/
++static unsigned long big_sur_ge_dma_status(xdma_channel * dma)
++{
++	return BIG_SUR_GE_READ(dma->reg_base_address +
++			       BIG_SUR_GE_DMAS_REG_OFFSET);
++}
++
++/*********************************************************************
++ * Set the interrupt status of the DMA channel
++ *********************************************************************/
++static void big_sur_ge_set_intr_status(xdma_channel * dma, unsigned long status)
++{
++	BIG_SUR_GE_WRITE(dma->reg_base_address + BIG_SUR_GE_IS_REG_OFFSET,
++			 status);
++}
++
++/*********************************************************************
++ * Get the interrupt status of the DMA channel
++ *********************************************************************/
++static unsigned long big_sur_ge_get_intr_status(xdma_channel * dma)
++{
++	return BIG_SUR_GE_READ(dma->reg_base_address +
++			       BIG_SUR_GE_IS_REG_OFFSET);
++}
++
++/*********************************************************************
++ * Set the Interrupt Enable
++ *********************************************************************/
++static void big_sur_ge_set_intr_enable(xdma_channel * dma, unsigned long enable)
++{
++	BIG_SUR_GE_WRITE(dma->reg_base_address + BIG_SUR_GE_IE_REG_OFFSET,
++			 enable);
++}
++
++/*********************************************************************
++ * Get the Interrupt Enable field to make a check
++ *********************************************************************/
++static unsigned long big_sur_ge_get_intr_enable(xdma_channel * dma)
++{
++	return BIG_SUR_GE_READ(dma->reg_base_address +
++			       BIG_SUR_GE_IE_REG_OFFSET);
++}
++
++/*********************************************************************
++ * Transfer the data over the DMA channel
++ *********************************************************************/
++static void big_sur_ge_dma_transfer(xdma_channel * dma, unsigned long *source,
++			     unsigned long *dest, unsigned long length)
++{
++	BIG_SUR_GE_WRITE(dma->reg_base_address + BIG_SUR_GE_SA_REG_OFFSET,
++			 (unsigned long) source);
++
++	BIG_SUR_GE_WRITE(dma->reg_base_address + BIG_SUR_GE_DA_REG_OFFSET,
++			 (unsigned long) dest);
++
++	BIG_SUR_GE_WRITE(dma->reg_base_address + BIG_SUR_GE_LEN_REG_OFFSET,
++			 length);
++}
++
++/*********************************************************************
++ * Get the DMA descriptor
++ *********************************************************************/
++static int big_sur_ge_get_descriptor(xdma_channel * dma,
++			      xbuf_descriptor ** buffer_desc)
++{
++	unsigned long reg_data;
++
++	reg_data = xbuf_descriptor_GetControl(dma->get_ptr);
++	xbuf_descriptor_SetControl(dma->get_ptr, reg_data |
++				   BIG_SUR_GE_DMACR_SG_DISABLE_MASK);
++
++	*buffer_desc = dma->get_ptr;
++
++	dma->get_ptr = xbuf_descriptor_GetNextPtr(dma->get_ptr);
++	dma->active_desc_count--;
++
++	return 0;
++}
++
++/*********************************************************************
++ * Get the packet count
++ *********************************************************************/
++static int big_sur_ge_get_packet_count(xdma_channel * dma)
++{
++	return (BIG_SUR_GE_READ
++		(dma->reg_base_address + BIG_SUR_GE_UPC_REG_OFFSET));
++}
++
++/*********************************************************************
++ * Descrement the packet count
++ *********************************************************************/
++static void big_sur_ge_decr_packet_count(xdma_channel * dma)
++{
++	unsigned long reg_data;
++
++	reg_data =
++	    BIG_SUR_GE_READ(dma->base_address + BIG_SUR_GE_UPC_REG_OFFSET);
++	if (reg_data > 0)
++		BIG_SUR_GE_WRITE(dma->base_address +
++				 BIG_SUR_GE_UPC_REG_OFFSET, 1);
++}
++
++/****************************************************************************
++ * Start of the code that deals with the Packet Fifo
++ *****************************************************************************/
++
++/****************************************************************************
++ * Init the packet fifo
++ ****************************************************************************/
++static int packet_fifo_init(packet_fifo * fifo, u32 reg, u32 data)
++{
++	fifo->reg_base_addr = reg;
++	fifo->data_base_address = data;
++	fifo->ready_status = 1;
++
++	BIG_SUR_GE_FIFO_RESET(fifo);
++
++	return 0;
++}
++
++/****************************************************************************
++ * Packet fifo self test
++ ****************************************************************************/
++static int packet_fifo_self_test(packet_fifo * fifo, unsigned long type)
++{
++	unsigned long reg_data;
++
++	BIG_SUR_GE_FIFO_RESET(fifo);
++	reg_data =
++	    BIG_SUR_GE_READ(fifo->reg_base_addr +
++			    BIG_SUR_GE_COUNT_STATUS_REG_OFFSET);
++
++	if (type == BIG_SUR_GE_READ_FIFO_TYPE) {
++		if (reg_data != BIG_SUR_GE_EMPTY_FULL_MASK) {
++			printk(KERN_ERR "Read FIFO not empty \n");
++			return -1;
++		}
++	} else if (!(reg_data & BIG_SUR_GE_EMPTY_FULL_MASK)) {
++		printk(KERN_ERR "Write FIFO is full \n");
++		return -1;
++	}
++
++	return 0;
++}
++
++/****************************************************************************
++ * Packet FIFO read
++ ****************************************************************************/
++static int packet_fifo_read(packet_fifo * fifo, u8 * buffer, unsigned int len)
++{
++	unsigned long fifo_count, word_count, extra_byte;
++	unsigned long *buffer_data = (unsigned long *) buffer;
++
++	fifo_count =
++	    BIG_SUR_GE_READ(fifo->reg_base_addr +
++			    BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT);
++	fifo_count &= BIG_SUR_GE_COUNT_MASK;
++
++	if ((fifo_count * BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT) < len)
++		return -1;
++
++	word_count = len / BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT;
++	extra_byte = len % BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT;
++
++	for (fifo_count = 0; fifo_count < word_count; fifo_count++)
++		buffer_data[fifo_count] =
++		    BIG_SUR_GE_READ(fifo->reg_base_addr);
++
++	if (extra_byte > 0) {
++		unsigned long last_word;
++		int *extra_buffer_data =
++		    (int *) (buffer_data + word_count);
++
++		last_word = BIG_SUR_GE_READ(fifo->data_base_address);
++		if (extra_byte == 1)
++			extra_buffer_data[0] = (int) (last_word << 24);
++		else if (extra_byte == 2) {
++			extra_buffer_data[0] = (int) (last_word << 24);
++			extra_buffer_data[1] = (int) (last_word << 16);
++		} else if (extra_byte == 3) {
++			extra_buffer_data[0] = (int) (last_word << 24);
++			extra_buffer_data[1] = (int) (last_word << 16);
++			extra_buffer_data[2] = (int) (last_word << 8);
++		}
++	}
++
++	return 0;
++}
++
++/*****************************************************************************
++ * Write the data into the packet fifo
++ *****************************************************************************/
++static int packet_fifo_write(packet_fifo * fifo, int *buffer, int len)
++{
++	unsigned long fifo_count, word_count, extra_byte;
++	unsigned long *buffer_data = (unsigned long *) buffer;
++
++	fifo_count =
++	    BIG_SUR_GE_READ(fifo->reg_base_addr +
++			    BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT);
++	fifo_count &= BIG_SUR_GE_COUNT_MASK;
++
++	word_count = len / BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT;
++	extra_byte = len % BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT;
++
++	/* You should see what the ppc driver does here. It just slobbers */
++	if (extra_byte > 0)
++		if (fifo_count > (word_count + 1)) {
++			printk(KERN_ERR
++			       "No room in the packet send fifo \n");
++			return -1;
++		}
++
++	for (fifo_count = 0; fifo_count < word_count; fifo_count++)
++		BIG_SUR_GE_WRITE(fifo->data_base_address,
++				 buffer_data[fifo_count]);
++
++
++	if (extra_byte > 0) {
++		unsigned long last_word = 0;
++		int *extra_buffer_data =
++		    (int *) (buffer_data + word_count);
++
++		if (extra_byte == 1)
++			last_word = extra_buffer_data[0] << 24;
++		else if (extra_byte == 2)
++			last_word = (extra_buffer_data[0] << 24 |
++				     extra_buffer_data[1] << 16);
++
++		else if (extra_byte == 3)
++			last_word = (extra_buffer_data[0] << 24 |
++				     extra_buffer_data[1] << 16 |
++				     extra_buffer_data[2] << 8);
++
++
++		BIG_SUR_GE_WRITE(fifo->data_base_address, last_word);
++	}
++
++	return 0;
++}
++
++
++/*****************************************************************************
++ * Interrupt handlers: We handle any errors associated with the FIFO.
++ * FIFO is for simple dma case and we do want to handle the simple DMA
++ * case. We dont handle the Scatter Gather DMA for now since it is not working.
++ ******************************************************************************/
++
++/*********************************************************************************
++ * FIFO send for Simple DMA with Interrupts
++ **********************************************************************************/
++static int big_sur_ge_enet_fifo_send(big_sur_ge * emac, u8 * buffer,
++			      unsigned long byte_cnt)
++{
++	unsigned long int_status, reg_data;
++
++	/* Silly checks here that we really dont need */
++	if (!emac->started)
++		return -1;
++
++	if (emac->polled)
++		return -1;
++
++	if (emac->dma_sg)
++		return -1;
++
++	int_status =
++	    BIG_SUR_GE_READ(emac->base_address + XIIF_V123B_IISR_OFFSET);
++	if (int_status & BIG_SUR_GE_EIR_XMIT_LFIFO_FULL_MASK) {
++		printk(KERN_ERR "Tx FIFO error: Queue is Full \n");
++		return -1;
++	}
++
++	/*
++	 * Write the data to the FIFO in the hardware
++	 */
++	if ((BIG_SUR_GE_GET_COUNT(&emac->send_fifo) *
++	     sizeof(unsigned long)) < byte_cnt) {
++		printk(KERN_ERR "Send FIFO on chip is full \n");
++		return -1;
++	}
++
++	if (big_sur_ge_dma_status(&emac->send_channel) &
++	    BIG_SUR_GE_DMASR_BUSY_MASK) {
++		printk(KERN_ERR "Send channel FIFO engine busy \n");
++		return -1;
++	}
++
++	big_sur_ge_set_dma_control(&emac->send_channel,
++				   BIG_SUR_GE_DMACR_SOURCE_INCR_MASK |
++				   BIG_SUR_GE_DMACR_DEST_LOCAL_MASK |
++				   BIG_SUR_GE_DMACR_SG_DISABLE_MASK);
++
++	big_sur_ge_dma_transfer(&emac->send_channel,
++				(unsigned long *) buffer,
++				(unsigned long *) (emac->base_address +
++						   BIG_SUR_GE_PFIFO_TXDATA_OFFSET),
++				byte_cnt);
++
++	reg_data = big_sur_ge_dma_status(&emac->send_channel);
++	while (reg_data & BIG_SUR_GE_DMASR_BUSY_MASK) {
++		reg_data = big_sur_ge_dma_status(&emac->recv_channel);
++		if (!(reg_data & BIG_SUR_GE_DMASR_BUSY_MASK))
++			break;
++	}
++
++	if ((reg_data & BIG_SUR_GE_DMASR_BUS_ERROR_MASK) ||
++	    (reg_data & BIG_SUR_GE_DMASR_BUS_TIMEOUT_MASK)) {
++		printk(KERN_ERR "Send side DMA error \n");
++		return -1;
++	}
++
++	BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_TPLR_OFFSET,
++			 byte_cnt);
++
++	return 0;
++}
++
++/*************************************************************************
++ * FIFO receive for Simple DMA case
++ *************************************************************************/
++static int big_sur_ge_enet_fifo_recv(big_sur_ge * emac, u8 * buffer,
++			      unsigned long *byte_cnt)
++{
++	unsigned long int_status, reg_data;
++
++	/* Silly checks here that we really dont need */
++	if (!emac->started)
++		return -1;
++
++	if (emac->polled)
++		return -1;
++
++	if (emac->dma_sg)
++		return -1;
++
++	if (*byte_cnt < BIG_SUR_GE_MAX_FRAME_SIZE)
++		return -1;
++
++	int_status =
++	    BIG_SUR_GE_READ(emac->base_address + XIIF_V123B_IISR_OFFSET);
++	if (int_status & BIG_SUR_GE_EIR_RECV_LFIFO_EMPTY_MASK) {
++		BIG_SUR_GE_WRITE(emac->base_address +
++				 XIIF_V123B_IISR_OFFSET,
++				 BIG_SUR_GE_EIR_RECV_LFIFO_EMPTY_MASK);
++		return -1;
++	}
++
++	if (big_sur_ge_dma_status(&emac->recv_channel) &
++	    BIG_SUR_GE_DMASR_BUSY_MASK) {
++		printk(KERN_ERR "Rx side DMA Engine busy \n");
++		return -1;
++	}
++
++	if (BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_RPLR_OFFSET) ==
++	    0) {
++		printk(KERN_ERR "MAC has the FIFO packet length 0 \n");
++		return -1;
++	}
++
++	/* For the simple DMA case only */
++	big_sur_ge_set_dma_control(&emac->recv_channel,
++				   BIG_SUR_GE_DMACR_DEST_INCR_MASK |
++				   BIG_SUR_GE_DMACR_SOURCE_LOCAL_MASK |
++				   BIG_SUR_GE_DMACR_SG_DISABLE_MASK);
++
++	if (packet_fifo_read(&emac->recv_fifo, buffer,
++			     BIG_SUR_GE_READ(emac->base_address +
++					     BIG_SUR_GE_RPLR_OFFSET)) ==
++	    -1) {
++		printk(KERN_ERR "Not enough space in the FIFO \n");
++		return -1;
++	}
++
++	big_sur_ge_dma_transfer(&emac->recv_channel,
++				(unsigned long *) (emac->base_address +
++						   BIG_SUR_GE_PFIFO_RXDATA_OFFSET),
++				(unsigned long *)
++				buffer,
++				BIG_SUR_GE_READ(emac->base_address +
++						BIG_SUR_GE_RPLR_OFFSET));
++
++	reg_data = big_sur_ge_dma_status(&emac->recv_channel);
++	while (reg_data & BIG_SUR_GE_DMASR_BUSY_MASK) {
++		reg_data = big_sur_ge_dma_status(&emac->recv_channel);
++		if (!(reg_data & BIG_SUR_GE_DMASR_BUSY_MASK))
++			break;
++	}
++
++	if ((reg_data & BIG_SUR_GE_DMASR_BUS_ERROR_MASK) ||
++	    (reg_data & BIG_SUR_GE_DMASR_BUS_TIMEOUT_MASK)) {
++		printk(KERN_ERR "DMA Bus Error \n");
++		return -1;
++	}
++
++	*byte_cnt =
++	    BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_RPLR_OFFSET);
++
++	return 0;
++}
++
++static irqreturn_t big_sur_ge_int_handler(int irq, void *dev_id,
++				   struct pt_regs *regs)
++{
++	struct net_device *netdev = dev_id;
++	struct big_sur_ge_enet *lp = netdev->priv;
++	big_sur_ge *emac = (big_sur_ge *)emac_ptr;
++	void *emac_ptr = &lp->emac;
++	unsigned long int_status;
++
++	int_status =
++	    BIG_SUR_GE_READ(emac->base_address + XIIF_V123B_DIPR_OFFSET);
++	if (int_status & BIG_SUR_GE_IPIF_EMAC_MASK)
++		handle_fifo_intr(emac);
++
++	if (int_status & BIG_SUR_GE_IPIF_RECV_FIFO_MASK)
++		big_sur_ge_check_fifo_recv_error(emac);
++
++	if (int_status & BIG_SUR_GE_IPIF_SEND_FIFO_MASK)
++		big_sur_ge_check_fifo_send_error(emac);
++
++	if (int_status & XIIF_V123B_ERROR_MASK)
++		BIG_SUR_GE_WRITE(emac->base_address +
++				 XIIF_V123B_DISR_OFFSET,
++				 XIIF_V123B_ERROR_MASK);
++
++	return IRQ_HANDLED;
++}
++
++/****************************************************************************
++ * Set the FIFO send handler
++ ***************************************************************************/
++static void big_sur_ge_set_fifo_send_handler(big_sur_ge * emac, void *call_back,
++				      big_sur_fifo_handler function)
++{
++	emac->big_sur_ge_fifo_send_handler = function;
++	emac->fifo_send_ref = call_back;
++}
++
++/****************************************************************************
++ * Set the FIFO recv handler
++ ***************************************************************************/
++static void big_sur_ge_set_fifo_recv_handler(big_sur_ge * emac, void *call_back,
++				      big_sur_fifo_handler function)
++{
++	emac->big_sur_ge_fifo_recv_handler = function;
++	emac->fifo_recv_ref = call_back;
++}
++
++/****************************************************************************
++ * Main Fifo intr handler
++ ***************************************************************************/
++static void handle_fifo_intr(big_sur_ge * emac)
++{
++	unsigned long int_status;
++
++	/* Ack the interrupts asap */
++	int_status =
++	    BIG_SUR_GE_READ(emac->base_address + XIIF_V123B_IISR_OFFSET);
++	BIG_SUR_GE_WRITE(emac->base_address + XIIF_V123B_IISR_OFFSET,
++			 int_status);
++
++	/* Process the Rx side */
++	if (int_status & BIG_SUR_GE_EIR_RECV_DONE_MASK) {
++		emac->big_sur_ge_fifo_recv_handler(&emac->fifo_recv_ref);
++		BIG_SUR_GE_WRITE(emac->base_address +
++				 XIIF_V123B_IISR_OFFSET,
++				 BIG_SUR_GE_EIR_RECV_DONE_MASK);
++	}
++
++	if (int_status & BIG_SUR_GE_EIR_XMIT_DONE_MASK) {
++		/* We dont collect stats and hence we dont need to get status */
++
++		emac->big_sur_ge_fifo_send_handler(emac->fifo_recv_ref);
++		BIG_SUR_GE_WRITE(emac->base_address +
++				 XIIF_V123B_IISR_OFFSET,
++				 BIG_SUR_GE_EIR_XMIT_DONE_MASK);
++	}
++
++	big_sur_ge_check_mac_error(emac, int_status);
++}
++
++/******************************************************************
++ * Handle the Receive side DMA interrupts. The PPC driver has
++ * callbacks all over the place. This has been eliminated here by
++ * using the following approach:
++ *
++ * The ISR is set to the main interrrupt handler. This will handle
++ * all the interrupts including the ones for DMA. In this main isr,
++ * we determine if we need to call recv or send side intr functions.
++ * Pretty complex but thats the way it is now.
++ *******************************************************************/
++static void big_sur_ge_handle_recv_intr(big_sur_ge * emac)
++{
++	unsigned long int_status;
++
++	int_status = big_sur_ge_get_intr_status(&emac->recv_channel);
++	if (int_status & (BIG_SUR_GE_IXR_PKT_THRESHOLD_MASK |
++			  BIG_SUR_GE_IXR_PKT_WAIT_BOUND_MASK)) {
++		u32 num_packets;
++		u32 num_processed;
++		u32 num_buffers;
++		u32 num_bytes;
++		xbuf_descriptor *first_desc_ptr = NULL;
++		xbuf_descriptor *buffer_desc;
++		int is_last = 0;
++
++		/* The number of packets we need to process on the Rx */
++		num_packets =
++		    big_sur_ge_get_packet_count(&emac->recv_channel);
++
++		for (num_processed = 0; num_processed < num_packets;
++		     num_processed++) {
++			while (!is_last) {
++				if (big_sur_ge_get_descriptor
++				    (&emac->recv_channel,
++				     &buffer_desc) == -1)
++					break;
++
++				if (first_desc_ptr == NULL)
++					first_desc_ptr = buffer_desc;
++
++				num_bytes +=
++				    xbuf_descriptor_GetLength(buffer_desc);
++
++				if (xbuf_descriptor_IsLastStatus
++				    (buffer_desc)) {
++					is_last = 1;
++				}
++
++				num_buffers++;
++			}
++
++			/* Number of buffers is always 1 since we dont do SG */
++
++			/*
++			 * Only for SG DMA which is currently not supported. In the
++			 * future, as we have SG channel working, we will code this
++			 * receive side routine. For now, do nothing. This is never
++			 * called from FIFO mode - Manish
++			 */
++			big_sur_ge_decr_packet_count(&emac->recv_channel);
++		}
++	}
++
++	/* Ack the interrupts */
++	big_sur_ge_set_intr_status(&emac->recv_channel, int_status);
++
++	if (int_status & BIG_SUR_GE_IXR_DMA_ERROR_MASK) {
++		/* We need a reset here */
++	}
++
++	big_sur_ge_set_intr_status(&emac->recv_channel, int_status);
++}
++
++/****************************************************************
++ * Handle the send side DMA interrupt
++ ****************************************************************/
++static void big_sur_ge_handle_send_intr(big_sur_ge * emac)
++{
++	unsigned long int_status;
++
++	int_status = big_sur_ge_get_intr_status(&emac->send_channel);
++
++	if (int_status & (BIG_SUR_GE_IXR_PKT_THRESHOLD_MASK |
++			  BIG_SUR_GE_IXR_PKT_WAIT_BOUND_MASK)) {
++		unsigned long num_frames = 0;
++		unsigned long num_processed = 0;
++		unsigned long num_buffers = 0;
++		unsigned long num_bytes = 0;
++		unsigned long is_last = 0;
++		xbuf_descriptor *first_desc_ptr = NULL;
++		xbuf_descriptor *buffer_desc;
++
++		num_frames =
++		    big_sur_ge_get_packet_count(&emac->send_channel);
++
++		for (num_processed = 0; num_processed < num_frames;
++		     num_processed++) {
++			while (!is_last) {
++				if (big_sur_ge_get_descriptor
++				    (&emac->send_channel, &buffer_desc)
++				    == -1) {
++					break;
++				}
++
++				if (first_desc_ptr == NULL)
++					first_desc_ptr = buffer_desc;
++
++				num_bytes +=
++				    xbuf_descriptor_GetLength(buffer_desc);
++				if (xbuf_descriptor_IsLastControl
++				    (buffer_desc))
++					is_last = 1;
++
++				num_buffers++;
++			}
++
++			/*
++			 * Only for SG DMA which is currently not supported. In the
++			 * future, as we have SG channel working, we will code this
++			 * receive side routine. For now, do nothing. This is never
++			 * called from FIFO mode - Manish
++			 */
++			big_sur_ge_decr_packet_count(&emac->send_channel);
++		}
++	}
++
++	/* Ack the interrupts and reset DMA channel if necessary */
++	big_sur_ge_set_intr_status(&emac->send_channel, int_status);
++	if (int_status & BIG_SUR_GE_IXR_DMA_ERROR_MASK) {
++		/* Manish : need reset */
++	}
++
++	big_sur_ge_set_intr_status(&emac->send_channel, int_status);
++}
++
++/*****************************************************************
++ * For now, the MAC address errors dont trigger a update of the
++ * stats. There is no stats framework in place. Hence, we just
++ * check for the errors below and do a reset if needed.
++ *****************************************************************/
++static void big_sur_ge_check_mac_error(big_sur_ge * emac,
++				unsigned long int_status)
++{
++	if (int_status & (BIG_SUR_GE_EIR_RECV_DFIFO_OVER_MASK |
++			  BIG_SUR_GE_EIR_RECV_LFIFO_OVER_MASK |
++			  BIG_SUR_GE_EIR_RECV_LFIFO_UNDER_MASK |
++			  BIG_SUR_GE_EIR_RECV_ERROR_MASK |
++			  BIG_SUR_GE_EIR_RECV_MISSED_FRAME_MASK |
++			  BIG_SUR_GE_EIR_RECV_COLLISION_MASK |
++			  BIG_SUR_GE_EIR_RECV_FCS_ERROR_MASK |
++			  BIG_SUR_GE_EIR_RECV_LEN_ERROR_MASK |
++			  BIG_SUR_GE_EIR_RECV_SHORT_ERROR_MASK |
++			  BIG_SUR_GE_EIR_RECV_LONG_ERROR_MASK |
++			  BIG_SUR_GE_EIR_RECV_ALIGN_ERROR_MASK |
++			  BIG_SUR_GE_EIR_XMIT_SFIFO_OVER_MASK |
++			  BIG_SUR_GE_EIR_XMIT_LFIFO_OVER_MASK |
++			  BIG_SUR_GE_EIR_XMIT_SFIFO_UNDER_MASK |
++			  BIG_SUR_GE_EIR_XMIT_LFIFO_UNDER_MASK)) {
++
++		BIG_SUR_GE_WRITE(emac->base_address +
++				 XIIF_V123B_IIER_OFFSET, 0);
++		/*
++		 * Manish Reset the MAC here
++		 */
++	}
++}
++
++/*****************************************************************
++ * Check for FIFO Recv errors
++ *****************************************************************/
++static void big_sur_ge_check_fifo_recv_error(big_sur_ge * emac)
++{
++	if (BIG_SUR_GE_IS_DEADLOCKED(&emac->recv_fifo)) {
++		unsigned long intr_enable;
++
++		intr_enable =
++		    BIG_SUR_GE_READ(emac->base_address +
++				    XIIF_V123B_DIER_OFFSET);
++		BIG_SUR_GE_WRITE(emac->base_address +
++				 XIIF_V123B_DIER_OFFSET,
++				 intr_enable &
++				 ~(BIG_SUR_GE_IPIF_RECV_FIFO_MASK));
++
++	}
++}
++
++/*****************************************************************
++ * Check for FIFO Send errors
++ *****************************************************************/
++static void big_sur_ge_check_fifo_send_error(big_sur_ge * emac)
++{
++	if (BIG_SUR_GE_IS_DEADLOCKED(&emac->send_fifo)) {
++		unsigned long intr_enable;
++
++		intr_enable =
++		    BIG_SUR_GE_READ(emac->base_address +
++				    XIIF_V123B_DIER_OFFSET);
++		BIG_SUR_GE_WRITE(emac->base_address +
++				 XIIF_V123B_DIER_OFFSET,
++				 intr_enable &
++				 ~(BIG_SUR_GE_IPIF_SEND_FIFO_MASK));
++	}
++}
++
++/*****************************************************************
++ * GE unit init
++ ****************************************************************/
++static int big_sur_ge_enet_init(big_sur_ge * emac, unsigned int device_id)
++{
++	unsigned long reg_data;
++	big_sur_ge_config *config;
++	int err;
++
++	/* Assume that the device has been stopped */
++
++	config = big_sur_ge_lookup_config(device_id);
++	if (config == NULL)
++		return -1;
++
++	emac->ready = 0;
++	emac->started = 0;
++	emac->dma_sg = 0;	/* This MAC has no support for Scatter Gather DMA */
++	emac->has_mii = config->has_mii;
++	emac->has_mcast_hash_table = 0;
++	emac->dma_config = config->dma_config;
++
++	/*
++	 * Initialize the FIFO send and recv handlers to the stub handlers.
++	 * We only deal with the FIFO mode of operation since SG is not supported.
++	 * Also, there is no error handler. We try to handle as much of error as
++	 * possible and then return. No error codes also.
++	 */
++
++	emac->base_address = config->base_address;
++
++	if (big_sur_ge_config_dma(emac) == -1)
++		return -1;
++
++	err = big_sur_ge_config_fifo(emac);
++	if (err == -1)
++		return err;
++
++	/* Now, we know that the FIFO initialized successfully. So, set the ready flag */
++	emac->ready = 1;
++
++	/* Do we need a PHY reset here also. It did cause problems on some boards */
++	big_sur_ge_enet_reset(emac);
++
++	/* PHY reset code. Remove if causes a problem on the board */
++	reg_data =
++	    BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_ECR_OFFSET);
++	reg_data &= ~(BIG_SUR_GE_ECR_PHY_ENABLE_MASK);
++	BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_ECR_OFFSET,
++			 reg_data);
++	reg_data |= BIG_SUR_GE_ECR_PHY_ENABLE_MASK;
++	BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_ECR_OFFSET,
++			 reg_data);
++
++	return 0;
++}
++
++/*******************************************************************
++ * Start the GE unit for Tx, Rx and Interrupts
++ *******************************************************************/
++static int big_sur_ge_start(big_sur_ge * emac)
++{
++	unsigned long reg_data;
++
++	/*
++	 * Basic mode of operation is polled and interrupt mode. We disable the polled
++	 * mode for good. We may use the polled mode for Rx NAPI but that does not
++	 * require all the interrupts to be disabled
++	 */
++
++	emac->polled = 0;
++
++	/*
++	 * DMA: Three modes of operation - simple, FIFO, SG. SG is surely not working
++	 * and so is kept off using the dma_sg flag. Simple and FIFO work. But, we may
++	 * not use FIFO at all. So, we enable the interrupts below
++	 */
++
++	BIG_SUR_GE_WRITE(emac->base_address + XIIF_V123B_DIER_OFFSET,
++			 BIG_SUR_GE_IPIF_FIFO_DFT_MASK |
++			 XIIF_V123B_ERROR_MASK);
++
++	BIG_SUR_GE_WRITE(emac->base_address + XIIF_V123B_IIER_OFFSET,
++			 BIG_SUR_GE_EIR_DFT_FIFO_MASK);
++
++	/* Toggle the started flag */
++	emac->started = 1;
++
++	/* Start the Tx and Rx units respectively */
++	reg_data =
++	    BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_ECR_OFFSET);
++	reg_data &=
++	    ~(BIG_SUR_GE_ECR_XMIT_RESET_MASK |
++	      BIG_SUR_GE_ECR_RECV_RESET_MASK);
++	reg_data |=
++	    (BIG_SUR_GE_ECR_XMIT_ENABLE_MASK |
++	     BIG_SUR_GE_ECR_RECV_ENABLE_MASK);
++
++	BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_ECR_OFFSET,
++			 reg_data);
++
++	return 0;
++}
++
++/**************************************************************************
++ * Stop the GE unit
++ **************************************************************************/
++static int big_sur_ge_stop(big_sur_ge * emac)
++{
++	unsigned long reg_data;
++
++	/* We assume that the device is not already stopped */
++	if (!emac->started)
++		return 0;
++
++	/* Disable the Tx and Rx unit respectively */
++	reg_data =
++	    BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_ECR_OFFSET);
++	reg_data &=
++	    ~(BIG_SUR_GE_ECR_XMIT_ENABLE_MASK |
++	      BIG_SUR_GE_ECR_RECV_ENABLE_MASK);
++	BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_ECR_OFFSET,
++			 reg_data);
++
++	/* Disable the interrupts */
++	BIG_SUR_GE_WRITE(emac->base_address + XIIF_V123B_DGIER_OFFSET, 0);
++
++	/* Toggle the started flag */
++	emac->started = 0;
++
++	return 0;
++}
++
++/************************************************************************
++ * Reset the GE MAC unit
++ *************************************************************************/
++static void big_sur_ge_enet_reset(big_sur_ge * emac)
++{
++	unsigned long reg_data;
++
++	(void) big_sur_ge_stop(emac);
++
++	BIG_SUR_GE_WRITE(emac->base_address + XIIF_V123B_RESETR_OFFSET,
++			 XIIF_V123B_RESET_MASK);
++
++	/*
++	 * For now, configure the receiver to not strip off FCS and padding since
++	 * this is not currently supported. In the future, just take the default
++	 * and provide the option for the user to change this behavior.
++	 */
++	reg_data =
++	    BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_ECR_OFFSET);
++	reg_data &=
++	    ~(BIG_SUR_GE_ECR_RECV_PAD_ENABLE_MASK |
++	      BIG_SUR_GE_ECR_RECV_FCS_ENABLE_MASK);
++	reg_data &= ~(BIG_SUR_GE_ECR_RECV_STRIP_ENABLE_MASK);
++	BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_ECR_OFFSET,
++			 reg_data);
++}
++
++/*************************************************************************
++ * Set the MAC address of the GE mac unit
++ *************************************************************************/
++static int big_sur_ge_set_mac_address(big_sur_ge * emac, unsigned char *addr)
++{
++	unsigned long mac_addr = 0;
++
++	/* Device is started and so mac address must be set */
++	if (emac->started == 1)
++		return 0;
++
++	mac_addr = ((addr[0] << 8) | addr[1]);
++	BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_SAH_OFFSET,
++			 mac_addr);
++
++	mac_addr |= ((addr[2] << 24) | (addr[3] << 16) |
++		     (addr[4] << 8) | addr[5]);
++
++	BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_SAL_OFFSET,
++			 mac_addr);
++
++	return 0;
++}
++
++/****************************************************************************
++ * Get the MAC address of the GE MAC unit
++ ***************************************************************************/
++static void big_sur_ge_get_mac_unit(big_sur_ge * emac, unsigned int *addr)
++{
++	unsigned long mac_addr_hi, mac_addr_lo;
++
++	mac_addr_hi =
++	    BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_SAH_OFFSET);
++	mac_addr_lo =
++	    BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_SAL_OFFSET);
++
++	addr[0] = (mac_addr_hi >> 8);
++	addr[1] = mac_addr_hi;
++
++	addr[2] = (mac_addr_lo >> 24);
++	addr[3] = (mac_addr_lo >> 16);
++	addr[4] = (mac_addr_lo >> 8);
++	addr[5] = mac_addr_lo;
++}
++
++/*********************************************************************************
++ * Configure the GE MAC for DMA capabilities. Not for Scatter Gather, only Simple
++ *********************************************************************************/
++static int big_sur_ge_config_dma(big_sur_ge * emac)
++{
++	if (big_sur_ge_dma_init(&emac->recv_channel, emac->base_address +
++				BIG_SUR_GE_DMA_RECV_OFFSET) == -1) {
++		printk(KERN_ERR "Could not initialize the DMA unit  \n");
++		return -1;
++	}
++
++	if (big_sur_ge_dma_init(&emac->send_channel, emac->base_address +
++				BIG_SUR_GE_DMA_SEND_OFFSET) == -1) {
++		printk(KERN_ERR "Could not initialize the DMA unit  \n");
++		return -1;
++	}
++
++	return 0;
++}
++
++/******************************************************************************
++ * Configure the FIFO for simple DMA
++ ******************************************************************************/
++static int big_sur_ge_config_fifo(big_sur_ge * emac)
++{
++	int err = 0;
++
++	err = packet_fifo_init(&emac->recv_fifo, emac->base_address +
++			       BIG_SUR_GE_PFIFO_RXREG_OFFSET,
++			       emac->base_address +
++			       BIG_SUR_GE_PFIFO_RXDATA_OFFSET);
++
++	if (err == -1) {
++		printk(KERN_ERR
++		       "Could not initialize Rx packet FIFO for Simple DMA \n");
++		return err;
++	}
++
++	err = packet_fifo_init(&emac->send_fifo, emac->base_address +
++			       BIG_SUR_GE_PFIFO_TXREG_OFFSET,
++			       emac->base_address +
++			       BIG_SUR_GE_PFIFO_TXDATA_OFFSET);
++
++	if (err == -1) {
++		printk(KERN_ERR
++		       "Could not initialize Tx packet FIFO for Simple DMA \n");
++	}
++
++	return err;
++}
++
++#define BIG_SUR_GE_NUM_INSTANCES	2
++
++
++/**********************************************************************************
++ * Look up the config of the MAC
++ **********************************************************************************/
++static big_sur_ge_config *big_sur_ge_lookup_config(unsigned int device_id)
++{
++	big_sur_ge_config *config = NULL;
++	int i = 0;
++
++	for (i = 0; i < BIG_SUR_GE_NUM_INSTANCES; i++) {
++		/* Manish : Init the config here */
++		break;
++	}
++
++	return config;
++}
++
++typedef struct {
++	unsigned long option;
++	unsigned long mask;
++} option_map;
++
++static option_map option_table[] = {
++	{BIG_SUR_GE_UNICAST_OPTION, BIG_SUR_GE_ECR_UNICAST_ENABLE_MASK},
++	{BIG_SUR_GE_BROADCAST_OPTION, BIG_SUR_GE_ECR_BROAD_ENABLE_MASK},
++	{BIG_SUR_GE_PROMISC_OPTION, BIG_SUR_GE_ECR_PROMISC_ENABLE_MASK},
++	{BIG_SUR_GE_FDUPLEX_OPTION, BIG_SUR_GE_ECR_FULL_DUPLEX_MASK},
++	{BIG_SUR_GE_LOOPBACK_OPTION, BIG_SUR_GE_ECR_LOOPBACK_MASK},
++	{BIG_SUR_GE_MULTICAST_OPTION, BIG_SUR_GE_ECR_MULTI_ENABLE_MASK},
++	{BIG_SUR_GE_FLOW_CONTROL_OPTION, BIG_SUR_GE_ECR_PAUSE_FRAME_MASK},
++	{BIG_SUR_GE_INSERT_PAD_OPTION,
++	 BIG_SUR_GE_ECR_XMIT_PAD_ENABLE_MASK},
++	{BIG_SUR_GE_INSERT_FCS_OPTION,
++	 BIG_SUR_GE_ECR_XMIT_FCS_ENABLE_MASK},
++	{BIG_SUR_GE_INSERT_ADDR_OPTION,
++	 BIG_SUR_GE_ECR_XMIT_ADDR_INSERT_MASK},
++	{BIG_SUR_GE_OVWRT_ADDR_OPTION,
++	 BIG_SUR_GE_ECR_XMIT_ADDR_OVWRT_MASK},
++	{BIG_SUR_GE_STRIP_PAD_OPTION, BIG_SUR_GE_ECR_RECV_PAD_ENABLE_MASK},
++	{BIG_SUR_GE_STRIP_FCS_OPTION, BIG_SUR_GE_ECR_RECV_FCS_ENABLE_MASK},
++	{BIG_SUR_GE_STRIP_PAD_FCS_OPTION,
++	 BIG_SUR_GE_ECR_RECV_STRIP_ENABLE_MASK}
++};
++
++#define BIG_SUR_GE_NUM_OPTIONS		(sizeof(option_table) / sizeof(option_map))
++
++/**********************************************************************
++ * Set the options for the GE
++ **********************************************************************/
++static int big_sur_ge_set_options(big_sur_ge * emac, unsigned long option_flag)
++{
++	unsigned long reg_data;
++	unsigned int index;
++
++	/* Assume that the device is stopped before calling this function */
++
++	reg_data =
++	    BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_ECR_OFFSET);
++	for (index = 0; index < BIG_SUR_GE_NUM_OPTIONS; index++) {
++		if (option_flag & option_table[index].option)
++			reg_data |= option_table[index].mask;
++		else
++			reg_data &= ~(option_table[index].mask);
++
++	}
++
++	BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_ECR_OFFSET,
++			 reg_data);
++
++	/* No polled option */
++	emac->polled = 0;
++
++	return 0;
++}
++
++/*******************************************************
++ * Get the options from the GE
++ *******************************************************/
++static unsigned long big_sur_ge_get_options(big_sur_ge * emac)
++{
++	unsigned long option_flag = 0, reg_data;
++	unsigned int index;
++
++	reg_data =
++	    BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_ECR_OFFSET);
++
++	for (index = 0; index < BIG_SUR_GE_NUM_OPTIONS; index++) {
++		if (option_flag & option_table[index].option)
++			reg_data |= option_table[index].mask;
++	}
++
++	/* No polled mode */
++
++	return option_flag;
++}
++
++/********************************************************
++ * Set the Inter frame gap
++ ********************************************************/
++static int big_sur_ge_set_frame_gap(big_sur_ge * emac, int part1, int part2)
++{
++	unsigned long config;
++
++	/* Assume that the device is stopped before calling this */
++
++	config = ((part1 << BIG_SUR_GE_IFGP_PART1_SHIFT) |
++		  (part2 << BIG_SUR_GE_IFGP_PART2_SHIFT));
++
++	BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_IFGP_OFFSET,
++			 config);
++
++	return 0;
++}
++
++/********************************************************
++ * Get the Inter frame gap
++ ********************************************************/
++static void big_sur_ge_get_frame_gap(big_sur_ge * emac, int *part1, int *part2)
++{
++	unsigned long config;
++
++	config =
++	    BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_IFGP_OFFSET);
++	*part1 =
++	    ((config & BIG_SUR_GE_IFGP_PART1_SHIFT) >>
++	     BIG_SUR_GE_IFGP_PART1_SHIFT);
++	*part2 =
++	    ((config & BIG_SUR_GE_IFGP_PART2_SHIFT) >>
++	     BIG_SUR_GE_IFGP_PART2_SHIFT);
++}
++
++/*******************************************************************
++ * PHY specific functions for the MAC
++ *******************************************************************/
++#define BIG_SUR_GE_MAX_PHY_ADDR		32
++#define BIG_SUR_GE_MAX_PHY_REG		32
++
++/*******************************************************************
++ * Read the PHY reg
++ *******************************************************************/
++static int big_sur_ge_phy_read(big_sur_ge * emac, unsigned long addr,
++			unsigned long reg_num, unsigned int *data)
++{
++	unsigned long mii_control, mii_data;
++
++	if (!emac->has_mii)
++		return -1;
++
++	mii_control =
++	    BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_MGTCR_OFFSET);
++	if (mii_control & BIG_SUR_GE_MGTCR_START_MASK) {
++		printk(KERN_ERR "PHY busy \n");
++		return -1;
++	}
++
++	mii_control = (addr << BIG_SUR_GE_MGTCR_PHY_ADDR_SHIFT);
++	mii_control |= (reg_num << BIG_SUR_GE_MGTCR_REG_ADDR_SHIFT);
++	mii_control |=
++	    (BIG_SUR_GE_MGTCR_RW_NOT_MASK | BIG_SUR_GE_MGTCR_START_MASK |
++	     BIG_SUR_GE_MGTCR_MII_ENABLE_MASK);
++
++	BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_MGTCR_OFFSET,
++			 mii_control);
++
++	while (mii_control & BIG_SUR_GE_MGTCR_START_MASK)
++		if (!(mii_control & BIG_SUR_GE_MGTCR_START_MASK))
++			break;
++
++	mii_data =
++	    BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_MGTDR_OFFSET);
++	*data = (unsigned int) mii_data;
++
++	return 0;
++}
++
++/**********************************************************************
++ * Write to the PHY register
++ **********************************************************************/
++static int big_sur_ge_phy_write(big_sur_ge * emac, unsigned long addr,
++			 unsigned long reg_num, unsigned int data)
++{
++	unsigned long mii_control;
++
++	if (!emac->has_mii)
++		return -1;
++
++	mii_control =
++	    BIG_SUR_GE_READ(emac->base_address + BIG_SUR_GE_MGTCR_OFFSET);
++	if (mii_control & BIG_SUR_GE_MGTCR_START_MASK) {
++		printk(KERN_ERR "PHY busy \n");
++		return -1;
++	}
++
++	BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_MGTDR_OFFSET,
++			 (unsigned long) data);
++
++	mii_control = (addr << BIG_SUR_GE_MGTCR_PHY_ADDR_SHIFT);
++	mii_control |= (reg_num << BIG_SUR_GE_MGTCR_REG_ADDR_SHIFT);
++	mii_control |=
++	    (BIG_SUR_GE_MGTCR_START_MASK |
++	     BIG_SUR_GE_MGTCR_MII_ENABLE_MASK);
++
++	BIG_SUR_GE_WRITE(emac->base_address + BIG_SUR_GE_MGTCR_OFFSET,
++			 mii_control);
++
++	while (mii_control & BIG_SUR_GE_MGTCR_START_MASK)
++		if (!(mii_control & BIG_SUR_GE_MGTCR_START_MASK))
++			break;
++
++	return 0;
++}
++
++
++
++
++
++
++/********************************************************************
++ * The hardware dependent part of the driver begins here
++ ********************************************************************/
++
++
++/*******************************************************************
++ * Reset the GE system
++ *******************************************************************/
++static void big_sur_ge_reset(struct net_device *netdev, DUPLEX duplex)
++{
++	struct big_sur_ge_enet *lp = netdev->priv;
++	struct sk_buff *skb;
++	unsigned long options;
++	int ifcfg1, ifcfg2;
++
++	/* Stop the queue */
++	netif_stop_queue(netdev);
++
++	big_sur_ge_get_frame_gap(&lp->emac, &ifcfg1, &ifcfg2);
++	options = big_sur_ge_get_options(&lp->emac);
++	switch (duplex) {
++	case HALF_DUPLEX:
++		options &= ~(BIG_SUR_GE_FDUPLEX_OPTION);
++		break;
++
++	case FULL_DUPLEX:
++		options |= BIG_SUR_GE_FDUPLEX_OPTION;
++		break;
++
++	case UNKNOWN:
++		break;
++	}
++
++	/* There is no support for SG DMA in a 100 Mpbs NIC */
++
++	big_sur_ge_enet_reset(&lp->emac);
++
++	/* Set the necessary options for the MAC unit */
++	big_sur_ge_set_mac_address(&lp->emac, netdev->dev_addr);
++	big_sur_ge_set_frame_gap(&lp->emac, ifcfg1, ifcfg2);
++	big_sur_ge_set_options(&lp->emac, options);
++
++	(void) big_sur_ge_start(&lp->emac);
++
++	spin_lock_irq(&lp->lock);
++	skb = lp->saved_skb;
++	lp->saved_skb = NULL;
++	spin_unlock_irq(&lp->lock);
++
++	if (skb)
++		dev_kfree_skb(skb);
++
++	/* Wake the queue */
++	netif_wake_queue(netdev);
++}
++
++/********************************************************************
++ * Get the PHY status
++ *******************************************************************/
++static int big_sur_ge_get_phy_status(struct net_device *netdev,
++				     DUPLEX * duplex, int *linkup)
++{
++	struct big_sur_ge_enet *lp = netdev->priv;
++	unsigned int reg_data;
++	int err = 0;
++
++	err =
++	    big_sur_ge_phy_read(&lp->emac, lp->mii_addr, MII_BMCR,
++				&reg_data);
++	if (err == -1) {
++		printk(KERN_ERR "%s: Could not read PHY control register",
++		       netdev->name);
++		return err;
++	}
++
++	if (!(reg_data & BMCR_ANENABLE)) {
++		if (reg_data & BMCR_FULLDPLX)
++			*duplex = FULL_DUPLEX;
++		else
++			*duplex = HALF_DUPLEX;
++	} else {
++		unsigned int advertise, partner, neg;
++
++		err =
++		    big_sur_ge_phy_read(&lp->emac, lp->mii_addr,
++					MII_ADVERTISE, &advertise);
++		if (err == -1) {
++			printk(KERN_ERR
++			       "%s: Could not read PHY control register",
++			       netdev->name);
++			return err;
++		}
++
++		err =
++		    big_sur_ge_phy_read(&lp->emac, lp->mii_addr, MII_LPA,
++					&partner);
++		if (err == -1) {
++			printk(KERN_ERR
++			       "%s: Could not read PHY control register",
++			       netdev->name);
++			return err;
++		}
++
++		neg = advertise & partner & ADVERTISE_ALL;
++		if (neg & ADVERTISE_100FULL)
++			*duplex = FULL_DUPLEX;
++		else if (neg & ADVERTISE_100HALF)
++			*duplex = HALF_DUPLEX;
++		else if (neg & ADVERTISE_10FULL)
++			*duplex = FULL_DUPLEX;
++		else
++			*duplex = HALF_DUPLEX;
++
++		err =
++		    big_sur_ge_phy_read(&lp->emac, lp->mii_addr, MII_BMSR,
++					&reg_data);
++		if (err == -1) {
++			printk(KERN_ERR
++			       "%s: Could not read PHY control register",
++			       netdev->name);
++			return err;
++		}
++
++		*linkup = (reg_data & BMSR_LSTATUS) != 0;
++
++	}
++	return 0;
++}
++
++/************************************************************
++ * Poll the MII for duplex and link status
++ ***********************************************************/
++static void big_sur_ge_poll_mii(unsigned long data)
++{
++	struct net_device *netdev = (struct net_device *) data;
++	struct big_sur_ge_enet *lp = netdev->priv;
++	unsigned long options;
++	DUPLEX mac_duplex, phy_duplex;
++	int phy_carrier, netif_carrier;
++
++	if (big_sur_ge_get_phy_status(netdev, &phy_duplex, &phy_carrier) ==
++	    -1) {
++		printk(KERN_ERR "%s: Terminating link monitoring.\n",
++		       netdev->name);
++		return;
++	}
++
++	options = big_sur_ge_get_options(&lp->emac);
++	if (options & BIG_SUR_GE_FDUPLEX_OPTION)
++		mac_duplex = FULL_DUPLEX;
++	else
++		mac_duplex = HALF_DUPLEX;
++
++	if (mac_duplex != phy_duplex) {
++		disable_irq(netdev->irq);
++		big_sur_ge_reset(netdev, phy_duplex);
++		enable_irq(netdev->irq);
++	}
++
++	netif_carrier = netif_carrier_ok(netdev) != 0;
++
++	if (phy_carrier != netif_carrier) {
++		if (phy_carrier) {
++			printk(KERN_INFO "%s: Link carrier restored.\n",
++			       netdev->name);
++			netif_carrier_on(netdev);
++		} else {
++			printk(KERN_INFO "%s: Link carrier lost.\n",
++			       netdev->name);
++			netif_carrier_off(netdev);
++		}
++	}
++
++	/* Set up the timer so we'll get called again in 2 seconds. */
++	lp->phy_timer.expires = jiffies + 2 * HZ;
++	add_timer(&lp->phy_timer);
++}
++
++/**************************************************************
++ * Open the network interface
++ *************************************************************/
++static int big_sur_ge_open(struct net_device *netdev)
++{
++	struct big_sur_ge_enet *lp = netdev->priv;
++	unsigned long options;
++	DUPLEX phy_duplex, mac_duplex;
++	int phy_carrier, retval;
++
++	(void) big_sur_ge_stop(&lp->emac);
++
++	if (big_sur_ge_set_mac_address(&lp->emac, netdev->dev_addr) == -1) {
++		printk(KERN_ERR "%s: Could not set MAC address.\n",
++		       netdev->name);
++		return -EIO;
++	}
++
++	options = big_sur_ge_get_options(&lp->emac);
++
++	retval =
++	    request_irq(netdev->irq, &big_sur_ge_int_handler, 0,
++			netdev->name, netdev);
++	if (retval) {
++		printk(KERN_ERR
++		       "%s: Could not allocate interrupt %d.\n",
++		       netdev->name, netdev->irq);
++
++		return retval;
++	}
++
++	if (!
++	    (big_sur_ge_get_phy_status(netdev, &phy_duplex, &phy_carrier)))
++	{
++		if (options & BIG_SUR_GE_FDUPLEX_OPTION)
++			mac_duplex = FULL_DUPLEX;
++		else
++			mac_duplex = HALF_DUPLEX;
++
++		if (mac_duplex != phy_duplex) {
++			switch (phy_duplex) {
++			case HALF_DUPLEX:
++				options &= ~(BIG_SUR_GE_FDUPLEX_OPTION);
++				break;
++			case FULL_DUPLEX:
++				options |= BIG_SUR_GE_FDUPLEX_OPTION;
++				break;
++			case UNKNOWN:
++				break;
++			}
++
++			big_sur_ge_set_options(&lp->emac, options);
++		}
++	}
++
++	if (big_sur_ge_start(&lp->emac) == -1) {
++		printk(KERN_ERR "%s: Could not start device.\n",
++		       netdev->name);
++		free_irq(netdev->irq, netdev);
++		return -EBUSY;
++	}
++
++	netif_start_queue(netdev);
++
++	lp->phy_timer.expires = jiffies + 2 * HZ;
++	lp->phy_timer.data = (unsigned long) netdev;
++	lp->phy_timer.function = &big_sur_ge_poll_mii;
++	add_timer(&lp->phy_timer);
++
++	return 0;
++}
++
++/*********************************************************************
++ * Close the network device interface
++ *********************************************************************/
++static int big_sur_ge_close(struct net_device *netdev)
++{
++	struct big_sur_ge_enet *lp = netdev->priv;
++
++	del_timer_sync(&lp->phy_timer);
++	netif_stop_queue(netdev);
++
++	free_irq(netdev->irq, netdev);
++
++	if (big_sur_ge_stop(&lp->emac) == -1) {
++		printk(KERN_ERR "%s: Could not stop device.\n",
++		       netdev->name);
++		return -EBUSY;
++	}
++
++	return 0;
++}
++
++/*********************************************************************
++ * Get the network device stats. For now, do nothing
++ *********************************************************************/
++static struct net_device_stats *big_sur_ge_get_stats(struct net_device
++						     *netdev)
++{
++	/* Do nothing */
++	return (struct net_device_stats *) 0;
++}
++
++/********************************************************************
++ * FIFO send for a packet that needs to be transmitted
++ ********************************************************************/
++static int big_sur_ge_fifo_send(struct sk_buff *orig_skb,
++				struct net_device *netdev)
++{
++	struct big_sur_ge_enet *lp = netdev->priv;
++	struct sk_buff *new_skb;
++	unsigned int len, align;
++
++	netif_stop_queue(netdev);
++	len = orig_skb->len;
++
++	if (!(new_skb = dev_alloc_skb(len + 4))) {
++		dev_kfree_skb(orig_skb);
++		printk(KERN_ERR
++		       "%s: Could not allocate transmit buffer.\n",
++		       netdev->name);
++		netif_wake_queue(netdev);
++		return -EBUSY;
++	}
++
++	align = 4 - ((unsigned long) new_skb->data & 3);
++	if (align != 4)
++		skb_reserve(new_skb, align);
++
++	skb_put(new_skb, len);
++	memcpy(new_skb->data, orig_skb->data, len);
++
++	dev_kfree_skb(orig_skb);
++
++	lp->saved_skb = new_skb;
++	if (big_sur_ge_enet_fifo_send(&lp->emac, (u8 *) new_skb->data, len)
++	    == -1) {
++		spin_lock_irq(&lp->lock);
++		new_skb = lp->saved_skb;
++		lp->saved_skb = NULL;
++		spin_unlock_irq(&lp->lock);
++
++		dev_kfree_skb(new_skb);
++		printk(KERN_ERR "%s: Could not transmit buffer.\n",
++		       netdev->name);
++		netif_wake_queue(netdev);
++		return -EIO;
++	}
++	return 0;
++}
++
++/**********************************************************************
++ * Call the fifo send handler
++ **********************************************************************/
++static void big_sur_ge_fifo_send_handler(void *callback)
++{
++	struct net_device *netdev = (struct net_device *) callback;
++	struct big_sur_ge_enet *lp = netdev->priv;
++	struct sk_buff *skb;
++
++	spin_lock_irq(&lp->lock);
++	skb = lp->saved_skb;
++	lp->saved_skb = NULL;
++	spin_unlock_irq(&lp->lock);
++
++	if (skb)
++		dev_kfree_skb(skb);
++
++	netif_wake_queue(netdev);
++}
++
++/**********************************************************************
++ * Handle the timeout of the ethernet device
++ **********************************************************************/
++static void big_sur_ge_tx_timeout(struct net_device *netdev)
++{
++	printk
++	    ("%s: Exceeded transmit timeout of %lu ms.	Resetting mac.\n",
++	     netdev->name, TX_TIMEOUT * 1000UL / HZ);
++
++	disable_irq(netdev->irq);
++	big_sur_ge_reset(netdev, UNKNOWN);
++	enable_irq(netdev->irq);
++}
++
++/*********************************************************************
++ * When in FIFO mode, the callback function for packets received
++ *********************************************************************/
++static void big_sur_ge_fifo_recv_handler(void *callback)
++{
++	struct net_device *netdev = (struct net_device *) callback;
++	struct big_sur_ge_enet *lp = netdev->priv;
++	struct sk_buff *skb;
++	unsigned long len = BIG_SUR_GE_MAX_FRAME_SIZE;
++	unsigned int align;
++
++	if (!(skb = dev_alloc_skb(len + 4))) {
++		printk(KERN_ERR "%s: Could not allocate receive buffer.\n",
++		       netdev->name);
++		return;
++	}
++
++	align = 4 - ((unsigned long) skb->data & 3);
++	if (align != 4)
++		skb_reserve(skb, align);
++
++	if (big_sur_ge_enet_fifo_recv(&lp->emac, (u8 *) skb->data, &len) ==
++	    -1) {
++		dev_kfree_skb(skb);
++
++		printk(KERN_ERR "%s: Could not receive buffer \n",
++		       netdev->name);
++		netdev->tx_timeout = NULL;
++		big_sur_ge_reset(netdev, UNKNOWN);
++		netdev->tx_timeout = big_sur_ge_tx_timeout;
++	}
++
++	skb_put(skb, len);	/* Tell the skb how much data we got. */
++	skb->dev = netdev;	/* Fill out required meta-data. */
++	skb->protocol = eth_type_trans(skb, netdev);
++
++	netif_rx(skb);		/* Send the packet upstream. */
++}
++
++/*********************************************************************
++ * Set the Multicast Hash list
++ *********************************************************************/
++static void big_sur_ge_set_multicast_hash_list(struct net_device *netdev)
++{
++	struct big_sur_ge_enet *lp = netdev->priv;
++	unsigned long options;
++
++	disable_irq(netdev->irq);
++	local_bh_disable();
++
++	(void) big_sur_ge_stop(&lp->emac);
++	options = big_sur_ge_get_options(&lp->emac);
++	options &=
++	    ~(BIG_SUR_GE_PROMISC_OPTION | BIG_SUR_GE_MULTICAST_OPTION);
++
++	/* Do nothing for now */
++
++	(void) big_sur_ge_start(&lp->emac);
++	local_bh_enable();
++	enable_irq(netdev->irq);
++}
++
++/***********************************************************************
++ * IOCTL support
++ ***********************************************************************/
++static int big_sur_ge_ioctl(struct net_device *netdev, struct ifreq *rq,
++			    int cmd)
++{
++	struct big_sur_ge_enet *lp = netdev->priv;
++	struct mii_ioctl_data *data =
++	    (struct mii_ioctl_data *) &rq->ifr_data;
++
++	switch (cmd) {
++	case SIOCGMIIPHY:	/* Get address of MII PHY in use. */
++	case SIOCDEVPRIVATE:	/* for binary compat, remove in 2.5 */
++		data->phy_id = lp->mii_addr;
++
++	case SIOCGMIIREG:	/* Read MII PHY register. */
++	case SIOCDEVPRIVATE + 1:	/* for binary compat, remove in 2.5 */
++		if (data->phy_id > 31 || data->reg_num > 31)
++			return -ENXIO;
++
++		del_timer_sync(&lp->phy_timer);
++
++		if (big_sur_ge_phy_read(&lp->emac, data->phy_id,
++					data->reg_num,
++					&data->val_out) == -1) {
++			printk(KERN_ERR "%s: Could not read from PHY",
++			       netdev->name);
++			return -EBUSY;
++		}
++
++		lp->phy_timer.expires = jiffies + 2 * HZ;
++		add_timer(&lp->phy_timer);
++
++		return 0;
++
++	case SIOCSMIIREG:	/* Write MII PHY register. */
++	case SIOCDEVPRIVATE + 2:	/* for binary compat, remove in 2.5 */
++		if (data->phy_id > 31 || data->reg_num > 31)
++			return -ENXIO;
++
++		del_timer_sync(&lp->phy_timer);
++
++		if (big_sur_ge_phy_write
++		    (&lp->emac, data->phy_id, data->reg_num,
++		     data->val_in) == -1) {
++			printk(KERN_ERR "%s: Could not write to PHY",
++			       netdev->name);
++			return -EBUSY;
++		}
++
++		lp->phy_timer.expires = jiffies + 2 * HZ;
++		add_timer(&lp->phy_timer);
++
++		return 0;
++
++	default:
++		return -EOPNOTSUPP;
++	}
++}
++
++/*****************************************************************
++ * Get the config from the config table
++ *****************************************************************/
++static big_sur_ge_config *big_sur_ge_get_config(int index)
++{
++	/* Manish */
++	return (big_sur_ge_config *) 0;
++}
++
++/*****************************************************************
++ * Release the network device structure
++ *****************************************************************/
++static void big_sur_ge_remove_head(void)
++{
++	struct net_device *netdev;
++	struct big_sur_ge_enet *lp;
++	big_sur_ge_config *config;
++
++	spin_lock(&dev_lock);
++	netdev = dev_list;
++	lp = netdev->priv;
++
++	spin_unlock(&dev_lock);
++
++	config = big_sur_ge_get_config(lp->index);
++	iounmap((void *) config->base_address);
++	config->base_address = lp->save_base_address;
++
++	if (lp->saved_skb)
++		dev_kfree_skb(lp->saved_skb);
++	kfree(lp);
++
++	unregister_netdev(netdev);
++	kfree(netdev);
++}
++
++/*****************************************************************
++ * Initial Function to probe the network interface
++ *****************************************************************/
++static int __init big_sur_ge_probe(int index)
++{
++	static const unsigned long remap_size =
++	    BIG_SUR_GE_EMAC_0_HIGHADDR - BIG_SUR_GE_EMAC_0_BASEADDR + 1;
++	struct net_device *netdev;
++	struct big_sur_ge_enet *lp;
++	big_sur_ge_config *config;
++	unsigned int irq;
++	unsigned long maddr;
++	goto err;
++
++	switch (index) {
++	case 0:
++		irq = (31 - BIG_SUR_GE_INTC_0_EMAC_0_VEC_ID);
++		break;
++	case 1:
++		irq = (31 - BIG_SUR_GE_INTC_1_EMAC_1_VEC_ID);
++		break;
++	case 2:
++		irq = (31 - BIG_SUR_GE_INTC_2_EMAC_2_VEC_ID);
++		break;
++	default:
++		err = -ENODEV;
++		goto out;
++	}
++
++	config = big_sur_ge_get_config(index);
++	if (!config) {
++		err = -ENODEV;
++		goto out;
++	}
++
++	netdev = alloc_etherdev(sizeof(big_sur_ge_config));
++
++	if (!netdev) {
++		err = -ENOMEM;
++		goto out;
++	}
++
++	SET_MODULE_OWNER(netdev);
++
++	netdev->irq = irq;
++
++	lp = (struct big_sur_ge_enet *) netdev->priv;
++	memset(lp, 0, sizeof(struct big_sur_ge_enet));
++	spin_lock_init(&lp->lock);
++	spin_lock(&dev_lock);
++	lp->next_dev = dev_list;
++	dev_list = netdev;
++	spin_unlock(&dev_lock);
++
++	lp->save_base_address = config->base_address;
++	config->base_address =
++	    (unsigned long) ioremap(lp->save_base_address, remap_size);
++	if (!config->base_address) {
++		err = -ENOMEM;
++		goto out_unlock;
++	}
++
++	if (big_sur_ge_enet_init(&lp->emac, config->device_id) == -1) {
++		printk(KERN_ERR "%s: Could not initialize device.\n",
++		       netdev->name);
++		err = -ENODEV;
++		goto out_unmap;
++	}
++
++	/* Manish: dev_addr value */
++	memcpy(netdev->dev_addr, big_sur_mac_addr_base, 6);
++	if (big_sur_ge_set_mac_address(&lp->emac, netdev->dev_addr) == -1) {
++		printk(KERN_ERR "%s: Could not set MAC address.\n",
++		       netdev->name);
++		err = -EIO;
++		goto out_unmap;
++	}
++
++	/*
++	 * There is no Scatter Gather support but there is a Simple DMA support
++	 */
++	big_sur_ge_set_fifo_recv_handler(&lp->emac, netdev,
++					 big_sur_ge_fifo_recv_handler);
++	big_sur_ge_set_fifo_send_handler(&lp->emac, netdev,
++					 big_sur_ge_fifo_send_handler);
++	netdev->hard_start_xmit = big_sur_ge_fifo_send;
++
++	lp->mii_addr = 0xFF;
++
++	for (maddr = 0; maddr < 31; maddr++) {
++		unsigned int reg_data;
++
++		if (big_sur_ge_phy_read
++		    (&lp->emac, maddr, MII_BMCR, &reg_data) == 0) {
++			lp->mii_addr = maddr;
++			break;
++		}
++	}
++
++	if (lp->mii_addr == 0xFF) {
++		lp->mii_addr = 0;
++		printk(KERN_WARNING
++		       "%s: No PHY detected.  Assuming a PHY at address %d.\n",
++		       netdev->name, lp->mii_addr);
++	}
++
++	netdev->open = big_sur_ge_open;
++	netdev->stop = big_sur_ge_close;
++	netdev->get_stats = big_sur_ge_get_stats;	/* Does nothing */
++	netdev->do_ioctl = big_sur_ge_ioctl;
++	netdev->tx_timeout = big_sur_ge_tx_timeout;
++	netdev->watchdog_timeo = TX_TIMEOUT;
++
++	err = register_netdev(netdev))
++	if (!err)
++		goto out_unmap;
++
++	printk(KERN_INFO "%s: PMC-Sierra Big Sur Ethernet Device %d  at 0x%08X "
++	       "mapped to 0x%08X, irq=%d\n", netdev->name, index,
++	       lp->save_base_address, config->base_address, netdev->irq);
++
++	return ret;
++
++out_unmap:
++	iounmap(config->base_address);
++
++out_unlock:
++	big_sur_ge_remove_head();
++
++out:
++	return ret;
++}
++
++static int __init big_sur_ge_init(void)
++{
++	int index = 0;
++
++	while (big_sur_ge_probe(index++) == 0);
++
++	return (index > 1) ? 0 : -ENODEV;
++}
++
++static void __exit big_sur_ge_cleanup(void)
++{
++	while (dev_list)
++		big_sur_ge_remove_head();
++}
++
++module_init(big_sur_ge_init);
++module_exit(big_sur_ge_cleanup);
++
++MODULE_AUTHOR("Manish Lachwani <lachwani@pmc-sierra.com>");
++MODULE_DESCRIPTION("PMC-Sierra Big Sur Ethernet MAC Driver");
++MODULE_LICENSE("GPL");
+diff -Naur linux-2.6.17.orig/drivers/net/big_sur_ge.h linux-2.6.17/drivers/net/big_sur_ge.h
+--- linux-2.6.17.orig/drivers/net/big_sur_ge.h	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/drivers/net/big_sur_ge.h	2006-06-19 18:16:13.000000000 -0700
+@@ -0,0 +1,713 @@
++/*
++ * drivers/net/big_sur_ge.h - Driver for PMC-Sierra Big Sur
++ * ethernet ports
++ *
++ * Copyright (C) 2003 PMC-Sierra Inc.
++ * Author : Manish Lachwani (lachwani@pmc-sierra.com)
++ * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
++ *
++ */
++
++#ifndef	__BIG_SUR_GE_H__
++#define	__BIG_SUR_GE_H__
++
++#include <linux/version.h>
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/spinlock.h>
++#include <linux/types.h>
++
++#define	BIG_SUR_DEVICE_NAME	"big sur"
++#define	BIG_SUR_DEVICE_DESC	"Big Sur Ethernet 10/100 MAC"
++
++#define BIG_SUR_GE_BASE			0xbb000000
++
++#define	BIG_SUR_GE_WRITE(ofs,data)	*(volatile u32 *)(BIG_SUR_GE_BASE+(ofs)) = data
++
++#define	BIG_SUR_GE_READ(ofs)		*(volatile u32 *)(BIG_SUR_GE_BASE+(ofs))
++
++/* Manish : Need to fix these defines later */
++#define	BIG_SUR_GE_EMAC_0_HIGHADDR
++#define	BIG_SUR_GE_EMAC_0_BASEADDR
++#define	BIG_SUR_GE_INTC_0_EMAC_0_VEC_ID		1
++#define	BIG_SUR_GE_INTC_1_EMAC_1_VEC_ID		2
++#define	BIG_SUR_GE_INTC_2_EMAC_2_VEC_ID		3
++#define	BIG_SUR_GE_EMAC_0_ERR_COUNT_EXIST
++#define	BIG_SUR_GE_EMAC_0_DMA_PRESENT
++#define	BIG_SUR_GE_EMAC_0_MII_EXIST
++#define	BIG_SUR_GE_OPB_ETHERNET_0_BASEADDR
++#define	BIG_SUR_GE_EMAC_0_DEVICE_ID
++#define	BIG_SUR_GE_OPB_ETHERNET_0_ERR_COUNT_EXIST
++#define	BIG_SUR_GE_OPB_ETHERNET_0_DMA_PRESENT
++#define	BIG_SUR_GE_OPB_ETHERNET_0_MII_EXIST
++#define	BIG_SUR_GE_OPB_ETHERNET_0_DEVICE_ID
++
++#define	BIG_SUR_GE_FIFO_WIDTH_BYTE_COUNT	4UL
++/* IPIF specific defines */
++#define XIIF_V123B_DISR_OFFSET     0UL  /* device interrupt status register */
++#define XIIF_V123B_DIPR_OFFSET     4UL  /* device interrupt pending register */
++#define XIIF_V123B_DIER_OFFSET     8UL  /* device interrupt enable register */
++#define XIIF_V123B_DIIR_OFFSET     24UL /* device interrupt ID register */
++#define XIIF_V123B_DGIER_OFFSET    28UL /* device global interrupt enable reg */
++#define XIIF_V123B_IISR_OFFSET     32UL /* IP interrupt status register */
++#define XIIF_V123B_IIER_OFFSET     40UL /* IP interrupt enable register */
++#define XIIF_V123B_RESETR_OFFSET   64UL /* reset register */
++#define XIIF_V123B_RESET_MASK             0xAUL
++#define	XIIF_V123B_ERROR_MASK		0x1UL
++
++/* defines */
++#define BIG_SUR_GE_UNICAST_OPTION        	0x00000001
++#define BIG_SUR_GE_BROADCAST_OPTION      	0x00000002
++#define BIG_SUR_GE_PROMISC_OPTION        	0x00000004
++#define BIG_SUR_GE_FDUPLEX_OPTION        	0x00000008
++#define BIG_SUR_GE_POLLED_OPTION         	0x00000010
++#define BIG_SUR_GE_LOOPBACK_OPTION       	0x00000020
++#define BIG_SUR_GE_FLOW_CONTROL_OPTION   	0x00000080
++#define BIG_SUR_GE_INSERT_PAD_OPTION     	0x00000100
++#define BIG_SUR_GE_INSERT_FCS_OPTION     	0x00000200
++#define BIG_SUR_GE_INSERT_ADDR_OPTION    	0x00000400
++#define BIG_SUR_GE_OVWRT_ADDR_OPTION     	0x00000800
++#define BIG_SUR_GE_STRIP_PAD_FCS_OPTION  	0x00002000
++
++/* Not Supported */
++#define BIG_SUR_GE_MULTICAST_OPTION      	0x00000040
++#define BIG_SUR_GE_FLOW_CONTROL_OPTION   	0x00000080
++#define BIG_SUR_GE_INSERT_PAD_OPTION     	0x00000100
++#define BIG_SUR_GE_INSERT_FCS_OPTION     	0x00000200
++#define BIG_SUR_GE_INSERT_ADDR_OPTION    	0x00000400
++#define BIG_SUR_GE_OVWRT_ADDR_OPTION     	0x00000800
++#define BIG_SUR_GE_STRIP_PAD_OPTION      	0x00001000
++#define BIG_SUR_GE_STRIP_FCS_OPTION     	0x00002000
++
++
++/* Defaults for Interrupt Coalescing in the SG DMA Engine */
++#define BIG_SUR_GE_SGDMA_DFT_THRESHOLD     1   /* Default pkt threshold */
++#define BIG_SUR_GE_SGDMA_MAX_THRESHOLD     255 /* Maximum pkt theshold */
++#define BIG_SUR_GE_SGDMA_DFT_WAITBOUND     5   /* Default pkt wait bound (msec) */
++#define BIG_SUR_GE_SGDMA_MAX_WAITBOUND     1023        /* Maximum pkt wait bound (msec) */
++
++/* Direction */
++#define BIG_SUR_GE_SEND    1
++#define BIG_SUR_GE_RECV    2
++
++/* SG DMA */
++#define BIG_SUR_GE_SGDMA_NODELAY     0 /* start SG DMA immediately */
++#define BIG_SUR_GE_SGDMA_DELAY       1 /* do not start SG DMA */
++
++#define BIG_SUR_GE_CFG_NO_IPIF             0   /* Not supported by the driver */
++#define BIG_SUR_GE_CFG_NO_DMA              1   /* No DMA */
++#define BIG_SUR_GE_CFG_SIMPLE_DMA          2   /* Simple DMA */
++#define BIG_SUR_GE_CFG_DMA_SG              3   /* DMA scatter gather */
++
++#define BIG_SUR_GE_MAC_ADDR_SIZE   6   /* six-byte MAC address */
++#define BIG_SUR_GE_MTU             1500        /* max size of Ethernet frame */
++#define BIG_SUR_GE_HDR_SIZE        14  /* size of Ethernet header */
++#define BIG_SUR_GE_HDR_VLAN_SIZE   18  /* size of Ethernet header with VLAN */
++#define BIG_SUR_GE_TRL_SIZE        4   /* size of Ethernet trailer (FCS) */
++#define BIG_SUR_GE_MAX_FRAME_SIZE  \
++		(BIG_SUR_GE_MTU + BIG_SUR_GE_HDR_SIZE + BIG_SUR_GE_TRL_SIZE)
++
++#define BIG_SUR_GE_MAX_VLAN_FRAME_SIZE  \
++		(BIG_SUR_GE_MTU + BIG_SUR_GE_HDR_VLAN_SIZE + BIG_SUR_GE_TRL_SIZE)
++
++/* Send and Receive buffers */
++#define BIG_SUR_GE_MIN_RECV_BUFS   32  /* minimum # of recv buffers */
++#define BIG_SUR_GE_DFT_RECV_BUFS   64  /* default # of recv buffers */
++
++#define BIG_SUR_GE_MIN_SEND_BUFS   16  /* minimum # of send buffers */
++#define BIG_SUR_GE_DFT_SEND_BUFS   32  /* default # of send buffers */
++
++#define BIG_SUR_GE_MIN_BUFFERS     (BIG_SUR_GE_MIN_RECV_BUFS + BIG_SUR_GE_MIN_SEND_BUFS)
++#define BIG_SUR_GE_DFT_BUFFERS     (BIG_SUR_GE_DFT_RECV_BUFS + BIG_SUR_GE_DFT_SEND_BUFS)
++
++/* Send and Receive Descriptors */
++#define BIG_SUR_GE_MIN_RECV_DESC   16  /* minimum # of recv descriptors */
++#define BIG_SUR_GE_DFT_RECV_DESC   32  /* default # of recv descriptors */
++
++#define BIG_SUR_GE_MIN_SEND_DESC   8   /* minimum # of send descriptors */
++#define BIG_SUR_GE_DFT_SEND_DESC   16  /* default # of send descriptors */
++
++/* FIFO Specific Defines */
++#define BIG_SUR_GE_READ_FIFO_TYPE      0       /* a read FIFO */
++#define BIG_SUR_GE_WRITE_FIFO_TYPE     1       /* a write FIFO */
++#define BIG_SUR_GE_RESET_REG_OFFSET            0UL
++#define BIG_SUR_GE_MODULE_INFO_REG_OFFSET      0UL
++#define BIG_SUR_GE_COUNT_STATUS_REG_OFFSET     4UL
++#define BIG_SUR_GE_RESET_FIFO_MASK             0x0000000A
++#define BIG_SUR_GE_COUNT_MASK                  0x0000FFFF
++#define BIG_SUR_GE_DEADLOCK_MASK               0x20000000
++#define BIG_SUR_GE_ALMOST_EMPTY_FULL_MASK      0x40000000
++#define BIG_SUR_GE_EMPTY_FULL_MASK             0x80000000
++
++#define BIG_SUR_GE_FIFO_RESET(fifo)	\
++	BIG_SUR_GE_WRITE((fifo)->reg_base_addr + BIG_SUR_GE_RESET_REG_OFFSET, BIG_SUR_GE_RESET_FIFO_MASK)
++
++#define	BIG_SUR_GE_GET_COUNT(fifo)	\
++	(BIG_SUR_GE_READ((fifo)->reg_base_addr + BIG_SUR_GE_COUNT_STATUS_REG_OFFSET) & 	\
++							BIG_SUR_GE_COUNT_MASK)
++
++#define	BIG_SUR_GE_IS_ALMOST_EMPTY(fifo)	\
++		(BIG_SUR_GE_READ(fifo->reg_base_addr + BIG_SUR_GE_COUNT_STATUS_REG_OFFSET) &	\
++							BIG_SUR_GE_ALMOST_EMPTY_FULL_MASK)
++
++#define	BIG_SUR_GE_IS_ALMOST_FULL(fifo)  \
++		(BIG_SUR_GE_READ(fifo->reg_base_addr + BIG_SUR_GE_COUNT_STATUS_REG_OFFSET) &   \
++							BIG_SUR_GE_ALMOST_EMPTY_FULL_MASK)
++
++#define BIG_SUR_GE_IS_EMPTY(fifo)  \
++		(BIG_SUR_GE_READ(fifo->reg_base_addr + BIG_SUR_GE_COUNT_STATUS_REG_OFFSET) &   \
++							BIG_SUR_GE_EMPTY_FULL_MASK)
++
++#define BIG_SUR_GE_IS_FULL(fifo)  \
++	(BIG_SUR_GE_READ(fifo->reg_base_addr + BIG_SUR_GE_COUNT_STATUS_REG_OFFSET) &   \
++							BIG_SUR_GE_EMPTY_FULL_MASK)
++
++#define	BIG_SUR_GE_IS_DEADLOCKED(fifo)	\
++	(BIG_SUR_GE_READ((fifo)->reg_base_addr + BIG_SUR_GE_COUNT_STATUS_REG_OFFSET) &   \
++							BIG_SUR_GE_DEADLOCK_MASK)
++
++/* Device Config */
++typedef struct _big_sur_ge_config {
++	u16		device_id;
++	u32		base_address;
++	u32		has_counters;
++	u32		has_sg_dma;
++	u8		dma_config;
++	u32		has_mii;
++} big_sur_ge_config;
++
++#define BIG_SUR_GE_SIZE_IN_WORDS           10
++typedef unsigned long xbuf_descriptor[BIG_SUR_GE_SIZE_IN_WORDS];
++
++/* Callback Functions */
++typedef void (*big_sur_sg_handler) (void *callback, xbuf_descriptor *desc, u32 num_desc);
++typedef	void (*big_sur_fifo_handler) (void *callback);
++typedef void (*big_sur_irq_handler) (void *instance);
++
++typedef struct _xdma_channel_tag {
++	u32			reg_base_address;
++        u32                     base_address;
++        u32                     ready;
++        xbuf_descriptor         *put_ptr;
++        xbuf_descriptor         *get_ptr;
++        xbuf_descriptor         *commit_ptr;
++        xbuf_descriptor         *last_ptr;
++
++        u32                     total_desc_count;
++        u32                     active_desc_count;
++} xdma_channel;
++
++typedef struct _packet_fifo {
++        u32             reg_base_addr;
++        u32             ready_status;
++        u32             data_base_address;
++} packet_fifo;
++
++
++/* Big Sur GE driver structure */
++typedef struct _big_sur_ge {
++	u32		base_address;
++	u32		started;
++	u32		ready;
++	u32		polled;
++	u32		dma_sg;
++
++	u8		dma_config;
++	u32		has_mii;
++	u32		has_mcast_hash_table;
++
++	/* For the FIFO and simple DMA case only */
++	packet_fifo	recv_fifo;
++	packet_fifo	send_fifo;
++
++	big_sur_fifo_handler	big_sur_ge_fifo_recv_handler;
++	big_sur_fifo_handler	big_sur_ge_fifo_send_handler;
++
++	void	*fifo_send_ref;
++	void	*fifo_recv_ref;	
++
++	/* For SG DMA only */
++	xdma_channel	recv_channel;
++	xdma_channel	send_channel;
++} big_sur_ge;
++
++/* Offset of the MAC registers from the IPIF base address */
++#define BIG_SUR_GE_REG_OFFSET     0x1100UL
++
++/*
++ * Register offsets for the Ethernet MAC. Each register is 32 bits.
++ */
++#define BIG_SUR_GE_EMIR_OFFSET   (BIG_SUR_GE_REG_OFFSET + 0x0)        /* EMAC Module ID */
++#define BIG_SUR_GE_ECR_OFFSET    (BIG_SUR_GE_REG_OFFSET + 0x4)        /* MAC Control */
++#define BIG_SUR_GE_IFGP_OFFSET   (BIG_SUR_GE_REG_OFFSET + 0x8)        /* Interframe Gap */
++#define BIG_SUR_GE_SAH_OFFSET    (BIG_SUR_GE_REG_OFFSET + 0xC)        /* Station addr, high */
++#define BIG_SUR_GE_SAL_OFFSET    (BIG_SUR_GE_REG_OFFSET + 0x10)       /* Station addr, low */
++#define BIG_SUR_GE_MGTCR_OFFSET  (BIG_SUR_GE_REG_OFFSET + 0x14)       /* MII mgmt control */
++#define BIG_SUR_GE_MGTDR_OFFSET  (BIG_SUR_GE_REG_OFFSET + 0x18)       /* MII mgmt data */
++#define BIG_SUR_GE_RPLR_OFFSET   (BIG_SUR_GE_REG_OFFSET + 0x1C)       /* Rx packet length */
++#define BIG_SUR_GE_TPLR_OFFSET   (BIG_SUR_GE_REG_OFFSET + 0x20)       /* Tx packet length */
++#define BIG_SUR_GE_TSR_OFFSET    (BIG_SUR_GE_REG_OFFSET + 0x24)       /* Tx status */
++#define BIG_SUR_GE_RMFC_OFFSET   (BIG_SUR_GE_REG_OFFSET + 0x28)       /* Rx missed frames */
++#define BIG_SUR_GE_RCC_OFFSET    (BIG_SUR_GE_REG_OFFSET + 0x2C)       /* Rx collisions */
++#define BIG_SUR_GE_RFCSEC_OFFSET (BIG_SUR_GE_REG_OFFSET + 0x30)       /* Rx FCS errors */
++#define BIG_SUR_GE_RAEC_OFFSET   (BIG_SUR_GE_REG_OFFSET + 0x34)       /* Rx alignment errors */
++#define BIG_SUR_GE_TEDC_OFFSET   (BIG_SUR_GE_REG_OFFSET + 0x38)       /* Transmit excess
++                                                         * deferral cnt */
++/*
++ * Register offsets for the IPIF components
++ */
++#define BIG_SUR_GE_ISR_OFFSET           0x20UL /* Interrupt status */
++
++#define BIG_SUR_GE_DMA_OFFSET           0x2300UL
++#define BIG_SUR_GE_DMA_SEND_OFFSET      (BIG_SUR_GE_DMA_OFFSET + 0x0) /* DMA send channel */
++#define BIG_SUR_GE_DMA_RECV_OFFSET      (BIG_SUR_GE_DMA_OFFSET + 0x40)        /* DMA recv channel */
++
++#define BIG_SUR_GE_PFIFO_OFFSET         0x2000UL
++#define BIG_SUR_GE_PFIFO_TXREG_OFFSET   (BIG_SUR_GE_PFIFO_OFFSET + 0x0)       /* Tx registers */
++#define BIG_SUR_GE_PFIFO_RXREG_OFFSET   (BIG_SUR_GE_PFIFO_OFFSET + 0x10)      /* Rx registers */
++#define BIG_SUR_GE_PFIFO_TXDATA_OFFSET  (BIG_SUR_GE_PFIFO_OFFSET + 0x100)     /* Tx keyhole */
++#define BIG_SUR_GE_PFIFO_RXDATA_OFFSET  (BIG_SUR_GE_PFIFO_OFFSET + 0x200)     /* Rx keyhole */
++
++/*
++ * EMAC Module Identification Register (EMIR)
++ */
++#define BIG_SUR_GE_EMIR_VERSION_MASK    0xFFFF0000UL   /* Device version */
++#define BIG_SUR_GE_EMIR_TYPE_MASK       0x0000FF00UL   /* Device type */
++
++/*
++ * EMAC Control Register (ECR)
++ */
++#define BIG_SUR_GE_ECR_FULL_DUPLEX_MASK         0x80000000   /* Full duplex mode */
++#define BIG_SUR_GE_ECR_XMIT_RESET_MASK          0x40000000   /* Reset transmitter */
++#define BIG_SUR_GE_ECR_XMIT_ENABLE_MASK         0x20000000   /* Enable transmitter */
++#define BIG_SUR_GE_ECR_RECV_RESET_MASK          0x10000000   /* Reset receiver */
++#define BIG_SUR_GE_ECR_RECV_ENABLE_MASK         0x08000000   /* Enable receiver */
++#define BIG_SUR_GE_ECR_PHY_ENABLE_MASK          0x04000000   /* Enable PHY */
++#define BIG_SUR_GE_ECR_XMIT_PAD_ENABLE_MASK     0x02000000   /* Enable xmit pad insert */
++#define BIG_SUR_GE_ECR_XMIT_FCS_ENABLE_MASK     0x01000000   /* Enable xmit FCS insert */
++#define BIG_SUR_GE_ECR_XMIT_ADDR_INSERT_MASK    0x00800000   /* Enable xmit source addr insertion */
++#define BIG_SUR_GE_ECR_XMIT_ERROR_INSERT_MASK   0x00400000   /* Insert xmit error */
++#define BIG_SUR_GE_ECR_XMIT_ADDR_OVWRT_MASK     0x00200000   /* Enable xmit source addr overwrite */
++#define BIG_SUR_GE_ECR_LOOPBACK_MASK            0x00100000   /* Enable internal loopback */
++#define BIG_SUR_GE_ECR_RECV_PAD_ENABLE_MASK     0x00080000   /* Enable recv pad strip */
++#define BIG_SUR_GE_ECR_RECV_FCS_ENABLE_MASK     0x00040000   /* Enable recv FCS strip */
++#define BIG_SUR_GE_ECR_RECV_STRIP_ENABLE_MASK   0x00080000   /* Enable recv pad/fcs strip */
++#define BIG_SUR_GE_ECR_UNICAST_ENABLE_MASK      0x00020000   /* Enable unicast addr */
++#define BIG_SUR_GE_ECR_MULTI_ENABLE_MASK        0x00010000   /* Enable multicast addr */
++#define BIG_SUR_GE_ECR_BROAD_ENABLE_MASK        0x00008000   /* Enable broadcast addr */
++#define BIG_SUR_GE_ECR_PROMISC_ENABLE_MASK      0x00004000   /* Enable promiscuous mode */
++#define BIG_SUR_GE_ECR_RECV_ALL_MASK            0x00002000   /* Receive all frames */
++#define BIG_SUR_GE_ECR_RESERVED2_MASK           0x00001000   /* Reserved */
++#define BIG_SUR_GE_ECR_MULTI_HASH_ENABLE_MASK   0x00000800   /* Enable multicast hash */
++#define BIG_SUR_GE_ECR_PAUSE_FRAME_MASK         0x00000400   /* Interpret pause frames */
++#define BIG_SUR_GE_ECR_CLEAR_HASH_MASK          0x00000200   /* Clear hash table */
++#define BIG_SUR_GE_ECR_ADD_HASH_ADDR_MASK       0x00000100  /* Add hash table address */
++
++/*
++ * Interframe Gap Register (IFGR)
++ */
++#define BIG_SUR_GE_IFGP_PART1_MASK         0xF8000000        /* Interframe Gap Part1 */
++#define BIG_SUR_GE_IFGP_PART1_SHIFT        27
++#define BIG_SUR_GE_IFGP_PART2_MASK         0x07C00000        /* Interframe Gap Part2 */
++#define BIG_SUR_GE_IFGP_PART2_SHIFT        22
++
++/*
++ * Station Address High Register (SAH)
++ */
++#define BIG_SUR_GE_SAH_ADDR_MASK           0x0000FFFF        /* Station address high bytes */
++
++/*
++ * Station Address Low Register (SAL)
++ */
++#define BIG_SUR_GE_SAL_ADDR_MASK           0xFFFFFFFF        /* Station address low bytes */
++
++/*
++ * MII Management Control Register (MGTCR)
++ */
++#define BIG_SUR_GE_MGTCR_START_MASK        0x80000000        /* Start/Busy */
++#define BIG_SUR_GE_MGTCR_RW_NOT_MASK       0x40000000        /* Read/Write Not (direction) */
++#define BIG_SUR_GE_MGTCR_PHY_ADDR_MASK     0x3E000000        /* PHY address */
++#define BIG_SUR_GE_MGTCR_PHY_ADDR_SHIFT    25  /* PHY address shift */
++#define BIG_SUR_GE_MGTCR_REG_ADDR_MASK     0x01F00000        /* Register address */
++#define BIG_SUR_GE_MGTCR_REG_ADDR_SHIFT    20  /* Register addr shift */
++#define BIG_SUR_GE_MGTCR_MII_ENABLE_MASK   0x00080000        /* Enable MII from EMAC */
++#define BIG_SUR_GE_MGTCR_RD_ERROR_MASK     0x00040000        /* MII mgmt read error */
++
++/*
++ * MII Management Data Register (MGTDR)
++ */
++#define BIG_SUR_GE_MGTDR_DATA_MASK         0x0000FFFF        /* MII data */
++
++/*
++ * Receive Packet Length Register (RPLR)
++ */
++#define BIG_SUR_GE_RPLR_LENGTH_MASK        0x0000FFFF        /* Receive packet length */
++
++/*
++ * Transmit Packet Length Register (TPLR)
++ */
++#define BIG_SUR_GE_TPLR_LENGTH_MASK        0x0000FFFF       /* Transmit packet length */
++
++/*
++ * Transmit Status Register (TSR)
++ */
++#define BIG_SUR_GE_TSR_EXCESS_DEFERRAL_MASK 0x80000000       /* Transmit excess deferral */
++#define BIG_SUR_GE_TSR_FIFO_UNDERRUN_MASK   0x40000000       /* Packet FIFO underrun */
++#define BIG_SUR_GE_TSR_ATTEMPTS_MASK        0x3E000000      /* Transmission attempts */
++#define BIG_SUR_GE_TSR_LATE_COLLISION_MASK  0x01000000      /* Transmit late collision */
++
++/*
++ * Receive Missed Frame Count (RMFC)
++ */
++#define BIG_SUR_GE_RMFC_DATA_MASK          0x0000FFFF
++
++/*
++ * Receive Collision Count (RCC)
++ */
++#define BIG_SUR_GE_RCC_DATA_MASK           0x0000FFFF
++/*
++ * Receive FCS Error Count (RFCSEC)
++ */
++#define BIG_SUR_GE_RFCSEC_DATA_MASK        0x0000FFFF
++
++/*
++ * Receive Alignment Error Count (RALN)
++ */
++#define BIG_SUR_GE_RAEC_DATA_MASK          0x0000FFFF
++
++/*
++ * Transmit Excess Deferral Count (TEDC)
++ */
++#define BIG_SUR_GE_TEDC_DATA_MASK          0x0000FFFF
++
++/*
++ * EMAC Interrupt Registers (Status and Enable) masks. These registers are
++ * part of the IPIF IP Interrupt registers
++ */
++#define BIG_SUR_GE_EIR_XMIT_DONE_MASK         0x00000001     /* Xmit complete */
++#define BIG_SUR_GE_EIR_RECV_DONE_MASK         0x00000002     /* Recv complete */
++#define BIG_SUR_GE_EIR_XMIT_ERROR_MASK        0x00000004     /* Xmit error */
++#define BIG_SUR_GE_EIR_RECV_ERROR_MASK        0x00000008     /* Recv error */
++#define BIG_SUR_GE_EIR_XMIT_SFIFO_EMPTY_MASK  0x00000010     /* Xmit status fifo empty */
++#define BIG_SUR_GE_EIR_RECV_LFIFO_EMPTY_MASK  0x00000020     /* Recv length fifo empty */
++#define BIG_SUR_GE_EIR_XMIT_LFIFO_FULL_MASK   0x00000040     /* Xmit length fifo full */
++#define BIG_SUR_GE_EIR_RECV_LFIFO_OVER_MASK   0x00000080     /* Recv length fifo overrun */
++#define BIG_SUR_GE_EIR_RECV_LFIFO_UNDER_MASK  0x00000100     /* Recv length fifo underrun */
++#define BIG_SUR_GE_EIR_XMIT_SFIFO_OVER_MASK   0x00000200     /* Xmit status fifo overrun */
++#define BIG_SUR_GE_EIR_XMIT_SFIFO_UNDER_MASK  0x00000400     /* Transmit status fifo underrun */
++#define BIG_SUR_GE_EIR_XMIT_LFIFO_OVER_MASK   0x00000800     /* Transmit length fifo overrun */
++#define BIG_SUR_GE_EIR_XMIT_LFIFO_UNDER_MASK  0x00001000     /* Transmit length fifo underrun */
++#define BIG_SUR_GE_EIR_XMIT_PAUSE_MASK        0x00002000     /* Transmit pause pkt received */
++#define BIG_SUR_GE_EIR_RECV_DFIFO_OVER_MASK   0x00004000     /* Receive data fifo overrun */
++#define BIG_SUR_GE_EIR_RECV_MISSED_FRAME_MASK 0x00008000     /* Receive missed frame error */
++#define BIG_SUR_GE_EIR_RECV_COLLISION_MASK    0x00010000     /* Receive collision error */
++#define BIG_SUR_GE_EIR_RECV_FCS_ERROR_MASK    0x00020000     /* Receive FCS error */
++#define BIG_SUR_GE_EIR_RECV_LEN_ERROR_MASK    0x00040000     /* Receive length field error */
++#define BIG_SUR_GE_EIR_RECV_SHORT_ERROR_MASK  0x00080000     /* Receive short frame error */
++#define BIG_SUR_GE_EIR_RECV_LONG_ERROR_MASK   0x00100000     /* Receive long frame error */
++#define BIG_SUR_GE_EIR_RECV_ALIGN_ERROR_MASK  0x00200000     /* Receive alignment error */
++
++#define	BIG_SUR_GE_READ_REG(base_addr, reg_offset)	\
++		BIG_SUR_GE_READ(base_addr + reg_offset)
++
++#define	BIG_SUR_GE_WRITE_REG(base_addr, reg_offset, data)	\
++		 BIG_SUR_GE_WRITE(base_addr + reg_offset, data)
++
++#define BIG_SUR_GE_CONTROL_REG(base_addr, mask)		\
++		BIG_SUR_GE_WRITE(base_addr + BIG_SUR_GE_ECR_OFFSET, mask)
++
++/* Set the MAC Address */
++#define	big_sur_ge_set_mac(base_addr, address)					\
++{										\
++	u32	mac_addr;							\
++										\
++	mac_addr = ((address[0] << 8) | (address[1]);				\
++	BIG_SUR_GE_WRITE(base_address + BIG_SUR_GE_SAH_OFFSET, mac_address);		\
++										\
++	mac_addr = ((address[2] << 24) | (address[3] << 16) |			\
++			(address[4] << 8) | address[5]);			\
++										\
++	BIG_SUR_GE_WRITE(base_address + BIG_SUR_GE_SAL_OFFSET, mac_address);		\
++										\
++}										
++
++/* Enable the MAC unit */
++#define	big_sur_ge_mac_enable(base_address)					\
++{										\
++	u32	control;							\
++	control = BIG_SUR_GE_READ(base_address + BIG_SUR_GE_ECR_OFFSET);		\
++	control &= ~(BIG_SUR_GE_ECR_XMIT_RESET_MASK | BIG_SUR_GE_ECR_RECV_RESET_MASK);	\
++	control |= (BIG_SUR_GE_ECR_XMIT_ENABLE_MASK | BIG_SUR_GE_ECR_RECV_ENABLE_MASK);	\
++	BIG_SUR_GE_WRITE(base_address + BIG_SUR_GE_ECR_OFFSET, control);		\
++}
++
++/* Disable the MAC unit */
++#define	big_sur_ge_mac_disable(base_address)					\
++{										\
++	u32	control;							\
++	control = BIG_SUR_GE_READ(base_address + BIG_SUR_GE_ECR_OFFSET);		\
++	control &= ~(BIG_SUR_GE_ECR_XMIT_ENABLE_MASK | BIG_SUR_GE_ECR_RECV_ENABLE_MASK);	\
++	BIG_SUR_GE_WRITE(base_address + BIG_SUR_GE_ECR_OFFSET, control);		\
++}
++
++/* Check if the Tx is done */
++#define	big_sur_ge_tx_done(base_address)						\
++	(BIG_SUR_GE_READ(base_address + BIG_SUR_GE_ISR_OFFSET) & BIG_SUR_GE_EIR_XMIT_DONE_MASK)
++
++
++/* Check if Rx FIFO is empty */
++#define	big_sur_ge_rx_empty(base_address)						\
++	(!(BIG_SUR_GE_READ(base_address + BIG_SUR_GE_ISR_OFFSET) & BIG_SUR_GE_EIR_RECV_DONE_MASK))
++
++/* Reset the MAC PHY */
++#define	big_sur_ge_reset_phy(base_address)						\
++{											\
++	u32	control;								\
++	control = BIG_SUR_GE_READ(base_address + BIG_SUR_GE_ECR_OFFSET);			\
++	control &= ~(BIG_SUR_GE_ECR_PHY_ENABLE_MASK);						\
++	BIG_SUR_GE_WRITE(base_address + BIG_SUR_GE_ECR_OFFSET, control);			\
++	control |= BIG_SUR_GE_ECR_PHY_ENABLE_MASK;						\
++	BIG_SUR_GE_WRITE(base_address + BIG_SUR_GE_ECR_OFFSET, control);			\
++}
++
++/* DMA SG defines */
++#define BIG_SUR_GE_CONTROL_LAST_BD_MASK        0x02000000
++#define BIG_SUR_GE_STATUS_LAST_BD_MASK         0x10000000
++#define BIG_SUR_GE_RST_REG_OFFSET      0       /* reset register */
++#define BIG_SUR_GE_MI_REG_OFFSET       0       /* module information register */
++#define BIG_SUR_GE_DMAC_REG_OFFSET     4       /* DMA control register */
++#define BIG_SUR_GE_SA_REG_OFFSET       8       /* source address register */
++#define BIG_SUR_GE_DA_REG_OFFSET       12      /* destination address register */
++#define BIG_SUR_GE_LEN_REG_OFFSET      16      /* length register */
++#define BIG_SUR_GE_DMAS_REG_OFFSET     20      /* DMA status register */
++#define BIG_SUR_GE_BDA_REG_OFFSET      24      /* buffer descriptor address register */
++#define BIG_SUR_GE_SWCR_REG_OFFSET 28  /* software control register */
++#define BIG_SUR_GE_UPC_REG_OFFSET      32      /* unserviced packet count register */
++#define BIG_SUR_GE_PCT_REG_OFFSET      36      /* packet count threshold register */
++#define BIG_SUR_GE_PWB_REG_OFFSET      40      /* packet wait bound register */
++#define BIG_SUR_GE_IS_REG_OFFSET       44      /* interrupt status register */
++#define BIG_SUR_GE_IE_REG_OFFSET       48      /* interrupt enable register */
++
++#define BIG_SUR_GE_RESET_MASK                          0x0000000A
++
++/* Buffer Descriptor Control */
++
++#define BIG_SUR_GE_DEVICE_STATUS_OFFSET    0
++#define BIG_SUR_GE_CONTROL_OFFSET          1
++#define BIG_SUR_GE_SOURCE_OFFSET           2
++#define BIG_SUR_GE_DESTINATION_OFFSET      3
++#define BIG_SUR_GE_LENGTH_OFFSET           4
++#define BIG_SUR_GE_STATUS_OFFSET           5
++#define BIG_SUR_GE_NEXT_PTR_OFFSET         6
++#define BIG_SUR_GE_ID_OFFSET               7
++#define BIG_SUR_GE_FLAGS_OFFSET            8
++#define BIG_SUR_GE_RQSTED_LENGTH_OFFSET    9
++
++#define BIG_SUR_GE_FLAGS_LOCKED_MASK       1
++
++#define	xbuf_descriptor_init(base)				\
++{								\
++	(*((u32 *)base + BIG_SUR_GE_CONTROL_OFFSET) = 0);		\
++	(*((u32 *)base + BIG_SUR_GE_SOURCE_OFFSET) = 0);        \
++    	(*((u32 *)base + BIG_SUR_GE_DESTINATION_OFFSET) = 0);   \
++    	(*((u32 *)base + BIG_SUR_GE_LENGTH_OFFSET) = 0);        \
++    	(*((u32 *)base + BIG_SUR_GE_STATUS_OFFSET) = 0);        \
++    	(*((u32 *)base + BIG_SUR_GE_DEVICE_STATUS_OFFSET) = 0); \
++    	(*((u32 *)base + BIG_SUR_GE_NEXT_PTR_OFFSET) = 0);      \
++    	(*((u32 *)base + BIG_SUR_GE_ID_OFFSET) = 0);            \
++    	(*((u32 *)base + BIG_SUR_GE_FLAGS_OFFSET) = 0);         \
++    	(*((u32 *)base + BIG_SUR_GE_RQSTED_LENGTH_OFFSET) = 0); \
++}
++
++#define xbuf_descriptor_GetControl(base)   \
++    (u32)(*((u32 *)base + BIG_SUR_GE_CONTROL_OFFSET))
++
++#define xbuf_descriptor_SetControl(base, Control)  \
++    (*((u32 *)base + BIG_SUR_GE_CONTROL_OFFSET) = (u32)Control)
++
++#define xbuf_descriptor_IsLastControl(base) \
++    (u32)(*((u32 *)base + BIG_SUR_GE_CONTROL_OFFSET) & \
++               BIG_SUR_GE_CONTROL_LAST_BD_MASK)
++
++#define xbuf_descriptor_SetLast(base) \
++    (*((u32 *)base + BIG_SUR_GE_CONTROL_OFFSET) |= BIG_SUR_GECONTROL_LAST_BD_MASK)
++
++#define xbuf_descriptor_GetSrcAddress(base) \
++    ((u32 *)(*((u32 *)base + BIG_SUR_GE_SOURCE_OFFSET)))
++
++#define xbuf_descriptor_SetSrcAddress(base, Source) \
++    (*((u32 *)base + BIG_SUR_GE_SOURCE_OFFSET) = (u32)Source)
++
++#define xbuf_descriptor_GetDestAddress(base) \
++    ((u32 *)(*((u32 *)base + BIG_SUR_GE_DESTINATION_OFFSET)))
++
++#define xbuf_descriptor_SetDestAddress(base, Destination) \
++    (*((u32 *)base + BIG_SUR_GE_DESTINATION_OFFSET) = (u32)Destination)
++
++#define xbuf_descriptor_GetLength(base)                           \
++    (u32)(*((u32 *)base + BIG_SUR_GE_RQSTED_LENGTH_OFFSET) -    \
++              *((u32 *)base + BIG_SUR_GE_LENGTH_OFFSET))
++
++#define xbuf_descriptor_SetLength(base, Length)                       \
++{                                                                           \
++    (*((u32 *)base + BIG_SUR_GE_LENGTH_OFFSET) = (u32)(Length));    \
++    (*((u32 *)base + BIG_SUR_GE_RQSTED_LENGTH_OFFSET) = (u32)(Length));\
++}
++
++#define xbuf_descriptor_GetStatus(base)    \
++    (u32)(*((u32 *)base + BIG_SUR_GE_STATUS_OFFSET))
++
++#define xbuf_descriptor_SetStatus(base, Status)    \
++    (*((u32 *)base + BIG_SUR_GE_STATUS_OFFSET) = (u32)Status)
++
++#define xbuf_descriptor_IsLastStatus(base) \
++    (u32)(*((u32 *)base + BIG_SUR_GE_STATUS_OFFSET) & \
++               BIG_SUR_GE_STATUS_LAST_BD_MASK)
++
++#define xbuf_descriptor_GetDeviceStatus(base) \
++    ((u32)(*((u32 *)base + BIG_SUR_GE_DEVICE_STATUS_OFFSET)))
++
++#define xbuf_descriptor_SetDeviceStatus(base, Status) \
++    (*((u32 *)base + BIG_SUR_GE_DEVICE_STATUS_OFFSET) = (u32)Status)
++
++#define xbuf_descriptor_GetNextPtr(base) \
++    (xbuf_descriptor *)(*((u32 *)base + BIG_SUR_GE_NEXT_PTR_OFFSET))
++
++#define xbuf_descriptor_SetNextPtr(base, NextPtr) \
++    (*((u32 *)base + BIG_SUR_GE_NEXT_PTR_OFFSET) = (u32)NextPtr)
++
++#define xbuf_descriptor_GetId(base) \
++    (u32)(*((u32 *)base + BIG_SUR_GE_ID_OFFSET))
++
++#define xbuf_descriptor_SetId(base, Id) \
++    (*((u32 *)base + BIG_SUR_GE_ID_OFFSET) = (u32)Id)
++
++#define xbuf_descriptor_GetFlags(base) \
++    (u32)(*((u32 *)base + BIG_SUR_GE_FLAGS_OFFSET))
++
++#define xbuf_descriptor_SetFlags(base, Flags) \
++    (*((u32 *)base + BIG_SUR_GE_FLAGS_OFFSET) = (u32)Flags)
++
++#define xbuf_descriptor_Lock(base) \
++    (*((u32 *)base + BIG_SUR_GE_FLAGS_OFFSET) |= BIG_SUR_GE_FLAGS_LOCKED_MASK)
++
++#define xbuf_descriptor_Unlock(base) \
++    (*((u32 *)base + BIG_SUR_GE_FLAGS_OFFSET) &= ~BIG_SUR_GE_FLAGS_LOCKED_MASK)
++
++#define xbuf_descriptor_IsLocked(base) \
++	(*((u32 *)base + BIG_SUR_GE_FLAGS_OFFSET) & BIG_SUR_GE_FLAGS_LOCKED_MASK)
++
++#define BIG_SUR_GE_DMACR_SOURCE_INCR_MASK      0x80000000UL    /* increment source address */
++#define BIG_SUR_GE_DMACR_DEST_INCR_MASK        0x40000000UL    /* increment dest address */
++#define BIG_SUR_GE_DMACR_SOURCE_LOCAL_MASK 0x20000000UL        /* local source address */
++#define BIG_SUR_GE_DMACR_DEST_LOCAL_MASK       0x10000000UL    /* local dest address */
++#define BIG_SUR_GE_DMACR_SG_DISABLE_MASK       0x08000000UL    /* scatter gather disable */
++#define BIG_SUR_GE_DMACR_GEN_BD_INTR_MASK      0x04000000UL    /* descriptor interrupt */
++#define BIG_SUR_GE_DMACR_LAST_BD_MASK          BIG_SUR_GE_CONTROL_LAST_BD_MASK        /* last buffer */
++#define BIG_SUR_GE_DMASR_BUSY_MASK                     0x80000000UL    /* channel is busy */
++#define BIG_SUR_GE_DMASR_BUS_ERROR_MASK        0x40000000UL    /* bus error occurred */
++#define BIG_SUR_GE_DMASR_BUS_TIMEOUT_MASK      0x20000000UL    /* bus timeout occurred */
++#define BIG_SUR_GE_DMASR_LAST_BD_MASK          BIG_SUR_GE_STATUS_LAST_BD_MASK /* last buffer */
++#define BIG_SUR_GE_DMASR_SG_BUSY_MASK          0x08000000UL    /* scatter gather is busy */
++#define BIG_SUR_GE_IXR_DMA_DONE_MASK           0x1UL   /* dma operation done */
++#define BIG_SUR_GE_IXR_DMA_ERROR_MASK      0x2UL       /* dma operation error */
++#define BIG_SUR_GE_IXR_PKT_DONE_MASK       0x4UL       /* packet done */
++#define BIG_SUR_GE_IXR_PKT_THRESHOLD_MASK      0x8UL   /* packet count threshold */
++#define BIG_SUR_GE_IXR_PKT_WAIT_BOUND_MASK 0x10UL      /* packet wait bound reached */
++#define BIG_SUR_GE_IXR_SG_DISABLE_ACK_MASK 0x20UL      /* scatter gather disable
++                                                   acknowledge occurred */
++#define BIG_SUR_GEIXR_SG_END_MASK                     0x40UL  /* last buffer descriptor
++                                                           disabled scatter gather */
++#define BIG_SUR_GEIXR_BD_MASK                         0x80UL  /* buffer descriptor done */
++
++/* BD control */
++#define BIG_SUR_GE_DFT_SEND_BD_MASK    (BIG_SUR_GEDMACR_SOURCE_INCR_MASK | \
++                                 BIG_SUR_GEDMACR_DEST_LOCAL_MASK)
++#define BIG_SUR_GE_DFT_RECV_BD_MASK    (BIG_SUR_GEDMACR_DEST_INCR_MASK |  \
++                                 BIG_SUR_GEDMACR_SOURCE_LOCAL_MASK)
++
++/* Interrupts */
++#define BIG_SUR_GE_IPIF_EMAC_MASK      0x00000004UL    /* MAC interrupt */
++#define BIG_SUR_GE_IPIF_SEND_DMA_MASK  0x00000008UL    /* Send DMA interrupt */
++#define BIG_SUR_GE_IPIF_RECV_DMA_MASK  0x00000010UL    /* Receive DMA interrupt */
++#define BIG_SUR_GE_IPIF_RECV_FIFO_MASK 0x00000020UL    /* Receive FIFO interrupt */
++#define BIG_SUR_GE_IPIF_SEND_FIFO_MASK 0x00000040UL    /* Send FIFO interrupt */
++
++#define BIG_SUR_GE_IPIF_DMA_DFT_MASK   (BIG_SUR_GE_IPIF_SEND_DMA_MASK |   \
++                                 BIG_SUR_GE_IPIF_RECV_DMA_MASK |   \
++                                 BIG_SUR_GE_IPIF_EMAC_MASK |       \
++                                 BIG_SUR_GE_IPIF_SEND_FIFO_MASK |  \
++                                 BIG_SUR_GE_IPIF_RECV_FIFO_MASK)
++
++#define BIG_SUR_GE_IPIF_FIFO_DFT_MASK  (BIG_SUR_GE_IPIF_EMAC_MASK |       \
++                                 BIG_SUR_GE_IPIF_SEND_FIFO_MASK |  \
++                                 BIG_SUR_GE_IPIF_RECV_FIFO_MASK)
++
++#define BIG_SUR_GE_IPIF_DMA_DEV_INTR_COUNT   7 /* Number of interrupt sources */
++#define BIG_SUR_GE_IPIF_FIFO_DEV_INTR_COUNT  5 /* Number of interrupt sources */
++#define BIG_SUR_GE_IPIF_DEVICE_INTR_COUNT  7   /* Number of interrupt sources */
++#define BIG_SUR_GE_IPIF_IP_INTR_COUNT      22  /* Number of MAC interrupts */
++
++/* a mask for all transmit interrupts, used in polled mode */
++#define BIG_SUR_GE_EIR_XMIT_ALL_MASK   (BIG_SUR_GE_EIR_XMIT_DONE_MASK |           \
++                                 BIG_SUR_GE_EIR_XMIT_ERROR_MASK |          \
++                                 BIG_SUR_GE_EIR_XMIT_SFIFO_EMPTY_MASK |    \
++                                 BIG_SUR_GE_EIR_XMIT_LFIFO_FULL_MASK)
++
++/* a mask for all receive interrupts, used in polled mode */
++#define BIG_SUR_GE_EIR_RECV_ALL_MASK   (BIG_SUR_GE_EIR_RECV_DONE_MASK |           \
++                                 BIG_SUR_GE_EIR_RECV_ERROR_MASK |          \
++                                 BIG_SUR_GE_EIR_RECV_LFIFO_EMPTY_MASK |    \
++                                 BIG_SUR_GE_EIR_RECV_LFIFO_OVER_MASK |     \
++                                 BIG_SUR_GE_EIR_RECV_LFIFO_UNDER_MASK |    \
++                                 BIG_SUR_GE_EIR_RECV_DFIFO_OVER_MASK |     \
++                                 BIG_SUR_GE_EIR_RECV_MISSED_FRAME_MASK |   \
++                                 BIG_SUR_GE_EIR_RECV_COLLISION_MASK |      \
++                                 BIG_SUR_GE_EIR_RECV_FCS_ERROR_MASK |      \
++                                 BIG_SUR_GE_EIR_RECV_LEN_ERROR_MASK |      \
++                                 BIG_SUR_GE_EIR_RECV_SHORT_ERROR_MASK |    \
++                                 BIG_SUR_GE_EIR_RECV_LONG_ERROR_MASK |     \
++                                 BIG_SUR_GE_EIR_RECV_ALIGN_ERROR_MASK)
++
++/* a default interrupt mask for scatter-gather DMA operation */
++#define BIG_SUR_GE_EIR_DFT_SG_MASK    (BIG_SUR_GE_EIR_RECV_ERROR_MASK |           \
++                                BIG_SUR_GE_EIR_RECV_LFIFO_OVER_MASK |      \
++                                BIG_SUR_GE_EIR_RECV_LFIFO_UNDER_MASK |     \
++                                BIG_SUR_GE_EIR_XMIT_SFIFO_OVER_MASK |      \
++                                BIG_SUR_GE_EIR_XMIT_SFIFO_UNDER_MASK |     \
++                                BIG_SUR_GE_EIR_XMIT_LFIFO_OVER_MASK |      \
++                                BIG_SUR_GE_EIR_XMIT_LFIFO_UNDER_MASK |     \
++                                BIG_SUR_GE_EIR_RECV_DFIFO_OVER_MASK |      \
++                                BIG_SUR_GE_EIR_RECV_MISSED_FRAME_MASK |    \
++                                BIG_SUR_GE_EIR_RECV_COLLISION_MASK |       \
++                                BIG_SUR_GE_EIR_RECV_FCS_ERROR_MASK |       \
++                                BIG_SUR_GE_EIR_RECV_LEN_ERROR_MASK |       \
++                                BIG_SUR_GE_EIR_RECV_SHORT_ERROR_MASK |     \
++                                BIG_SUR_GE_EIR_RECV_LONG_ERROR_MASK |      \
++                                BIG_SUR_GE_EIR_RECV_ALIGN_ERROR_MASK)
++
++/* a default interrupt mask for non-DMA operation (direct FIFOs) */
++#define BIG_SUR_GE_EIR_DFT_FIFO_MASK  (BIG_SUR_GE_EIR_XMIT_DONE_MASK |            \
++                                BIG_SUR_GE_EIR_RECV_DONE_MASK |            \
++                                BIG_SUR_GE_EIR_DFT_SG_MASK)
++
++#define BIG_SUR_GE_DMA_SG_INTR_MASK    (BIG_SUR_GEIXR_DMA_ERROR_MASK  |      \
++                                 BIG_SUR_GEIXR_PKT_THRESHOLD_MASK |   \
++                                 BIG_SUR_GEIXR_PKT_WAIT_BOUND_MASK |  \
++                                 BIG_SUR_GEIXR_SG_END_MASK)
++
++#endif
+diff -Naur linux-2.6.17.orig/drivers/net/declance.c linux-2.6.17/drivers/net/declance.c
+--- linux-2.6.17.orig/drivers/net/declance.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/drivers/net/declance.c	2006-06-19 18:16:13.000000000 -0700
+@@ -704,8 +704,8 @@
+ 	return IRQ_HANDLED;
+ }
+ 
+-static irqreturn_t
+-lance_interrupt(const int irq, void *dev_id, struct pt_regs *regs)
++static irqreturn_t lance_interrupt(const int irq, void *dev_id,
++				   struct pt_regs *regs)
+ {
+ 	struct net_device *dev = (struct net_device *) dev_id;
+ 	struct lance_private *lp = netdev_priv(dev);
+@@ -1255,7 +1255,7 @@
+ 	return 0;
+ 
+ err_out_free_dev:
+-	kfree(dev);
++	free_netdev(dev);
+ 
+ err_out:
+ 	return ret;
+@@ -1301,6 +1301,7 @@
+ 	while (root_lance_dev) {
+ 		struct net_device *dev = root_lance_dev;
+ 		struct lance_private *lp = netdev_priv(dev);
++
+ 		unregister_netdev(dev);
+ #ifdef CONFIG_TC
+ 		if (lp->slot >= 0)
+diff -Naur linux-2.6.17.orig/drivers/net/gt64240eth.c linux-2.6.17/drivers/net/gt64240eth.c
+--- linux-2.6.17.orig/drivers/net/gt64240eth.c	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/drivers/net/gt64240eth.c	2006-06-19 18:16:13.000000000 -0700
+@@ -0,0 +1,1672 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2001 Patton Electronics Company
++ * Copyright (C) 2002 Momentum Computer
++ *
++ * Copyright 2000 MontaVista Software Inc.
++ * Author: MontaVista Software, Inc.
++ *         	stevel@mvista.com or support@mvista.com
++ *
++ *  This program is free software; you can distribute it and/or modify it
++ *  under the terms of the GNU General Public License (Version 2) as
++ *  published by the Free Software Foundation.
++ *
++ *  This program is distributed in the hope it will be useful, but WITHOUT
++ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
++ *  for more details.
++ *
++ *  You should have received a copy of the GNU General Public License along
++ *  with this program; if not, write to the Free Software Foundation, Inc.,
++ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
++ *
++ * Ethernet driver for the MIPS GT96100 Advanced Communication Controller.
++ * 
++ * Modified for the Gallileo/Marvell GT-64240 Communication Controller.
++ *
++ * Support for Rx NAPI, Rx checksum offload, IOCTL and ETHTOOL added
++ * Manish Lachwani (lachwani@pmc-sierra.com) - 09/16/2003
++ *
++ * Modified for later version of Linux 2.4 kernel
++ * Manish Lachwani (lachwani@pmc-sierra.com) - 04/29/2004
++ */
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/sched.h>
++#include <linux/string.h>
++#include <linux/timer.h>
++#include <linux/errno.h>
++#include <linux/in.h>
++#include <linux/ioport.h>
++#include <linux/slab.h>
++#include <linux/interrupt.h>
++#include <linux/pci.h>
++#include <linux/init.h>
++#include <linux/netdevice.h>
++#include <linux/etherdevice.h>
++#include <linux/ethtool.h>
++#include <linux/skbuff.h>
++#include <linux/delay.h>
++#include <linux/ctype.h>
++#include <linux/mii.h>
++
++#include <asm/irq.h>
++#include <asm/bitops.h>
++#include <asm/io.h>
++#include <asm/uaccess.h>
++
++#define DESC_DATA_BE 1
++
++#include "gt64240eth.h"
++
++// enable this port (set hash size to 1/2K)
++//- #define PORT_CONFIG pcrHS
++#define PORT_CONFIG (pcrHS | pcrHD)
++//- #define PORT_CONFIG pcrHS |pcrPM |pcrPBF|pcrHDM
++//- GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG, pcrEN | pcrHS);
++//- GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG, pcrEN | pcrHS | pcrPM);
++//- GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG, pcrEN | pcrHS | pcrPM | 1<<pcrLPBKBit);
++
++// clear all the MIB ctr regs
++#define EXT_CONFIG_CLEAR (pcxrFCTL | pcxrFCTLen | pcxrFLP | pcxrDPLXen | pcxrPRIOrxOverride | pcxrRMIIen)
++
++/*
++ * _debug level:
++ * <= 2	none.
++ *  > 2	some warnings such as queue full, .....
++ *  > 3	lots of change-of-state messages.
++ *  > 4	EXTENSIVE data/descriptor dumps.
++ */
++
++#ifdef GT64240_DEBUG
++static int gt64240_debug = GT64240_DEBUG;
++#else
++static int gt64240_debug = 0;
++#endif
++
++static int debug = -1;
++
++#define GT64240_MSG_ENABLE	(NETIF_MSG_DRV          | \
++				NETIF_MSG_PROBE        | \
++				NETIF_MSG_LINK)
++
++
++/********************************************************/
++
++// prototypes
++static void gt64240_delay(int msec);
++static int gt64240_add_hash_entry(struct net_device *dev,
++				  unsigned char *addr);
++static void read_mib_counters(struct gt64240_private *gp);
++static void dump_MII(struct net_device *dev);
++static void dump_tx_desc(struct net_device *dev, int i);
++static void dump_rx_desc(struct net_device *dev, int i);
++static void dump_hw_addr(unsigned char *addr_str);
++static void update_stats(struct gt64240_private *gp);
++static void abort(struct net_device *dev, u32 abort_bits);
++static void hard_stop(struct net_device *dev);
++static void enable_ether_irq(struct net_device *dev);
++static void disable_ether_irq(struct net_device *dev);
++static int __init gt64240_probe1(unsigned long ioaddr, int irq, int port_num);
++static void reset_tx(struct net_device *dev);
++static void reset_rx(struct net_device *dev);
++static int gt64240_init(struct net_device *dev);
++static int gt64240_open(struct net_device *dev);
++static int gt64240_close(struct net_device *dev);
++static int gt64240_tx(struct sk_buff *skb, struct net_device *dev);
++#ifdef GT64240_NAPI
++static int gt64240_poll(struct net_device *dev, int *budget);
++static int gt64240_rx(struct net_device *dev, u32 status, int budget);
++#else
++static int gt64240_rx(struct net_device *dev, u32 status);
++#endif
++static void gt64240_tx_timeout(struct net_device *dev);
++static void gt64240_set_rx_mode(struct net_device *dev);
++static struct net_device_stats *gt64240_get_stats(struct net_device *dev);
++
++extern char *__init prom_getcmdline(void);
++extern int prom_get_mac_addrs(unsigned char
++			      station_addr[NUM_INTERFACES][6]);
++
++static char version[] __devinitdata =
++	"gt64240eth.o: version 0.1, <www.patton.com>\n";
++
++// PHY device addresses
++static u32 gt64240_phy_addr[NUM_INTERFACES] __devinitdata = { 0x8, 0x1, 0xa };
++
++// Need real Ethernet addresses -- in parse_mac_addr_options(),
++// these will be replaced by prom_get_mac_addrs() and/or prom_getcmdline().
++static unsigned char gt64240_station_addr[NUM_INTERFACES][6] = {
++	{0x00, 0x01, 0x02, 0x03, 0x04, 0x05},
++	{0x01, 0x02, 0x03, 0x04, 0x05, 0x06},
++	{0x02, 0x03, 0x04, 0x05, 0x06, 0x07}
++};
++
++static int max_interrupt_work = 32;
++
++/*
++ * Base address and interupt of the GT64240 ethernet controllers
++ */
++static struct {
++	unsigned int port;
++	int irq;
++} gt64240_iflist[NUM_INTERFACES] = {
++	{
++	GT64240_ETH0_BASE, 8}, {
++	GT64240_ETH1_BASE, 8}, {
++	GT64240_ETH2_BASE, 8}
++};
++
++static void gt64240_delay(int ms)
++{
++	if (in_interrupt())
++		return;
++	else {
++		current->state = TASK_INTERRUPTIBLE;
++		schedule_timeout(ms * HZ / 1000);
++	}
++}
++
++unsigned char prom_mac_addr_base[6];
++
++int prom_get_mac_addrs(unsigned char station_addr[NUM_INTERFACES][6])
++{
++	memcpy(station_addr[0], prom_mac_addr_base, 6);
++	memcpy(station_addr[1], prom_mac_addr_base, 6);
++	memcpy(station_addr[2], prom_mac_addr_base, 6);
++
++	station_addr[1][5] += 1;
++	station_addr[2][5] += 2;
++
++	return 0;
++}
++
++void parse_mac_addr_options(void)
++{
++	prom_get_mac_addrs(gt64240_station_addr);
++}
++
++static int read_MII(struct net_device *dev, int phy, int reg)
++{
++	int timedout = 20;
++	u32 smir = smirOpCode | (phy << smirPhyAdBit) |
++	    (reg << smirRegAdBit);
++
++	// wait for last operation to complete
++	while ((GT64240_READ(GT64240_ETH_SMI_REG)) & smirBusy) {
++		// snooze for 1 msec and check again
++		gt64240_delay(1);
++
++		if (--timedout == 0) {
++			printk("%s: read_MII busy timeout!!\n", dev->name);
++			return -1;
++		}
++	}
++
++	GT64240_WRITE(GT64240_ETH_SMI_REG, smir);
++
++	timedout = 20;
++	// wait for read to complete
++	while (!
++	       ((smir =
++		 GT64240_READ(GT64240_ETH_SMI_REG)) & smirReadValid)) {
++		// snooze for 1 msec and check again
++		gt64240_delay(1);
++
++		if (--timedout == 0) {
++			printk("%s: read_MII timeout!!\n", dev->name);
++			return -1;
++		}
++	}
++
++	return (int) (smir & smirDataMask);
++}
++
++static void gp_get_drvinfo (struct net_device *dev, 
++				struct ethtool_drvinfo *info)
++{
++	strcpy(info->driver, "gt64260");
++	strcpy(info->version, version);
++}
++
++static int gp_get_settings(struct net_device *dev, 
++				struct ethtool_cmd *cmd)
++{
++	struct gt64240_private *gp = netdev_priv(dev);
++	int rc;
++
++	spin_lock_irq(&gp->lock);
++	rc = mii_ethtool_gset(&gp->mii_if, cmd);
++	spin_unlock_irq(&gp->lock);
++	return rc;
++}
++
++static int gp_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
++{
++	struct gt64240_private *gp = netdev_priv(dev);
++	int rc;
++
++	spin_lock_irq(&gp->lock);
++	rc = mii_ethtool_sset(&gp->mii_if, cmd);
++	spin_unlock_irq(&gp->lock);
++	return rc;
++}
++
++static int gp_nway_reset(struct net_device *dev)
++{
++	struct gt64240_private *gp = netdev_priv(dev);
++	return mii_nway_restart(&gp->mii_if);
++}
++
++static u32 gp_get_link(struct net_device *dev)
++{
++	struct gt64240_private *gp = netdev_priv(dev);
++	return mii_link_ok(&gp->mii_if);
++}
++
++static u32 gp_get_msglevel(struct net_device *dev)
++{
++	struct gt64240_private *gp = netdev_priv(dev);
++	return gp->msg_enable;
++}
++
++static void gp_set_msglevel(struct net_device *dev, u32 value)
++{
++	struct gt64240_private *gp = netdev_priv(dev);
++	gp->msg_enable = value;
++}
++
++static struct ethtool_ops gp_ethtool_ops = {
++	.get_drvinfo		= gp_get_drvinfo,
++	.get_settings		= gp_get_settings,
++	.set_settings		= gp_set_settings,
++	.nway_reset		= gp_nway_reset,
++	.get_link		= gp_get_link,
++	.get_msglevel		= gp_get_msglevel,
++	.set_msglevel		= gp_set_msglevel,
++};
++
++static int gt64240_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
++{
++	struct gt64240_private *gp = netdev_priv(dev);
++	struct mii_ioctl_data *data =
++	    (struct mii_ioctl_data *) &rq->ifr_data;
++	int retval;
++
++	if (!netif_running(dev))
++		return -EINVAL;
++
++	spin_lock_irq(&gp->lock);
++	retval = generic_mii_ioctl(&gp->mii_if, data, cmd, NULL);
++	spin_unlock_irq(&gp->lock);
++
++	return retval;
++}
++
++static void dump_tx_desc(struct net_device *dev, int i)
++{
++	struct gt64240_private *gp = netdev_priv(dev);
++	gt64240_td_t *td = &gp->tx_ring[i];
++
++	printk("%s:tx[%d]: self=%p cmd=%08x, cnt=%4d. bufp=%08x, next=%08x\n",
++	       dev->name, i, td, td->cmdstat, td->byte_cnt, td->buff_ptr,
++	       td->next);
++}
++
++static void dump_rx_desc(struct net_device *dev, int i)
++{
++	struct gt64240_private *gp = netdev_priv(dev);
++	gt64240_rd_t *rd = &gp->rx_ring[i];
++
++	printk("%s:rx_dsc[%d]: self=%p cst=%08x,size=%4d. cnt=%4d. "
++	       "bufp=%08x, next=%08x\n",
++	       dev->name, i, rd, rd->cmdstat, rd->buff_sz, rd->byte_cnt,
++	       rd->buff_ptr, rd->next);
++}
++
++// These routines work, just disabled to avoid compile warnings
++static void write_MII(struct net_device *dev, int phy, int reg, int data)
++{
++	u32 smir = (phy << smirPhyAdBit) | (reg << smirRegAdBit) | data;
++	int timedout = 20;
++
++	// wait for last operation to complete
++	while (GT64240_READ(GT64240_ETH_SMI_REG) & smirBusy) {
++		// snooze for 1 msec and check again
++		gt64240_delay(1);
++
++		if (--timedout == 0) {
++			printk("%s: write_MII busy timeout!!\n",
++			       dev->name);
++			return;
++		}
++	}
++
++	GT64240_WRITE(GT64240_ETH_SMI_REG, smir);
++}
++
++static void dump_MII(struct net_device *dev)
++{
++	struct gt64240_private *gp = netdev_priv(dev);
++	int i, val;
++
++	for (i = 0; i < 7; i++) {
++		if ((val = read_MII(dev, gp->phy_addr, i)) >= 0)
++			printk("%s: MII Reg %d=%x\n", dev->name, i, val);
++	}
++	for (i = 16; i < 21; i++) {
++		if ((val = read_MII(dev, gp->phy_addr, i)) >= 0)
++			printk("%s: MII Reg %d=%x\n", dev->name, i, val);
++	}
++}
++
++
++static void dump_hw_addr(unsigned char *addr_str)
++{
++	int i;
++	for (i = 0; i < 6; i++) {
++		printk("%2.2x", addr_str[i]);
++		printk(i < 5 ? ":" : "\n");
++	}
++}
++
++static int gt64240_add_hash_entry(struct net_device *dev,
++				  unsigned char *addr)
++{
++	static unsigned char swapped[256];
++	struct gt64240_private *gp;
++	u32 value1, value0, *entry;
++	unsigned char hash_ea[6];
++	static int flag = 0;
++	u16 hashResult;
++	int i;
++
++	if (flag == 0) {	/* Create table to swap bits in a byte  */
++		flag = 1;
++		for (i = 0; i < 256; i++) {
++			swapped[i] = (i & 0x01) << 7;
++			swapped[i] |= (i & 0x02) << 5;
++			swapped[i] |= (i & 0x04) << 3;
++			swapped[i] |= (i & 0x08) << 1;
++			swapped[i] |= (i & 0x10) >> 1;
++			swapped[i] |= (i & 0x20) >> 3;
++			swapped[i] |= (i & 0x40) >> 5;
++			swapped[i] |= (i & 0x80) >> 7;
++		}
++	}
++
++	for (i = 0; i < 6; i++) {	/* swap bits from mac to create hash mac */
++		hash_ea[i] = swapped[addr[i]];
++	}
++
++	gp = netdev_priv(dev);
++
++	/* create hash entry address    */
++	hashResult = (((hash_ea[5] >> 2) & 0x3F) << 9) & 0x7E00;
++	hashResult |= ((hash_ea[4] & 0x7F) << 2) | (hash_ea[5] & 0x03);
++	hashResult ^=
++	    ((hash_ea[3] & 0xFF) << 1) | ((hash_ea[4] >> 7) & 0x01);
++	hashResult ^= ((hash_ea[1] & 0x01) << 8) | (hash_ea[2] & 0xFF);
++
++	value0 = hteValid | hteRD;	/* Create hash table entry value */
++	value0 |= (u32) addr[0] << 3;
++	value0 |= (u32) addr[1] << 11;
++	value0 |= (u32) addr[2] << 19;
++	value0 |= ((u32) addr[3] & 0x1f) << 27;
++
++	value1 = ((u32) addr[3] >> 5) & 0x07;
++	value1 |= (u32) addr[4] << 3;
++	value1 |= (u32) addr[5] << 11;
++
++	/* Inset entry value into hash table */
++	for (i = 0; i < HASH_HOP_NUMBER; i++) {
++		entry = (u32 *) ((u32) gp->hash_table +
++				 (((u32) hashResult & 0x07ff) << 3));
++		if ((*entry & hteValid) && !(*entry & hteSkip)) {
++			hashResult += 2;	/* oops, occupied, go to next entry */
++		} else {
++#ifdef __LITTLE_ENDIAN
++			entry[1] = value1;
++			entry[0] = value0;
++#else
++			entry[0] = value1;
++			entry[1] = value0;
++#endif
++			break;
++		}
++	}
++	if (i >= HASH_HOP_NUMBER) {
++		printk("%s: gt64240_add_hash_entry expired!\n", dev->name);
++		return (-1);
++	}
++	return (0);
++}
++
++
++static void read_mib_counters(struct gt64240_private *gp)
++{
++	u32 *mib_regs = (u32 *) & gp->mib;
++	int i;
++
++	for (i = 0; i < sizeof(mib_counters_t) / sizeof(u32); i++)
++		mib_regs[i] =
++		    GT64240ETH_READ(gp,
++				    GT64240_ETH_MIB_COUNT_BASE +
++				    i * sizeof(u32));
++}
++
++
++static void update_stats(struct gt64240_private *gp)
++{
++	mib_counters_t *mib = &gp->mib;
++	struct net_device_stats *stats = &gp->stats;
++
++	read_mib_counters(gp);
++
++	stats->rx_packets = mib->totalFramesReceived;
++	stats->tx_packets = mib->framesSent;
++	stats->rx_bytes = mib->totalByteReceived;
++	stats->tx_bytes = mib->byteSent;
++	stats->rx_errors = mib->totalFramesReceived - mib->framesReceived;
++	//the tx error counters are incremented by the ISR
++	//rx_dropped incremented by gt64240_rx
++	//tx_dropped incremented by gt64240_tx
++	stats->multicast = mib->multicastFramesReceived;
++	// collisions incremented by gt64240_tx_complete
++	stats->rx_length_errors = mib->oversizeFrames + mib->fragments;
++	// The RxError condition means the Rx DMA encountered a
++	// CPU owned descriptor, which, if things are working as
++	// they should, means the Rx ring has overflowed.
++	stats->rx_over_errors = mib->macRxError;
++	stats->rx_crc_errors = mib->cRCError;
++}
++
++static void abort(struct net_device *dev, u32 abort_bits)
++{
++	struct gt64240_private *gp = netdev_priv(dev);
++	int timedout = 100;	// wait up to 100 msec for hard stop to complete
++
++	if (gt64240_debug > 3)
++		printk("%s: abort\n", dev->name);
++
++	// Return if neither Rx or Tx abort bits are set
++	if (!(abort_bits & (sdcmrAR | sdcmrAT)))
++		return;
++
++	// make sure only the Rx/Tx abort bits are set
++	abort_bits &= (sdcmrAR | sdcmrAT);
++
++	spin_lock(&gp->lock);
++
++	// abort any Rx/Tx DMA immediately
++	GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_COMM, abort_bits);
++
++	if (gt64240_debug > 3)
++		printk("%s: abort: SDMA cmd  = %x/%x\n",
++		       dev->name, abort_bits, GT64240ETH_READ(gp,
++							      GT64240_ETH_SDMA_COMM));
++
++	// wait for abort to complete
++	while ((GT64240ETH_READ(gp, GT64240_ETH_SDMA_COMM)) & abort_bits) {
++		// snooze for 20 msec and check again
++		gt64240_delay(1);
++
++		if (--timedout == 0) {
++			printk("%s: abort timeout!!\n", dev->name);
++			break;
++		}
++	}
++
++	spin_unlock(&gp->lock);
++}
++
++
++static void hard_stop(struct net_device *dev)
++{
++	struct gt64240_private *gp = netdev_priv(dev);
++
++	if (gt64240_debug > 3)
++		printk("%s: hard stop\n", dev->name);
++
++	disable_ether_irq(dev);
++
++	abort(dev, sdcmrAR | sdcmrAT);
++
++	// disable port
++	GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG, 0);
++	if (gt64240_debug > 3)
++		printk("%s: gt64240_hard_stop: Port Config=%x\n",
++		       dev->name, GT64240ETH_READ(gp,
++						  GT64240_ETH_PORT_CONFIG));
++
++}
++
++static void gt64240_tx_complete(struct net_device *dev, u32 status)
++{
++	struct gt64240_private *gp = netdev_priv(dev);
++	int nextOut, cdp;
++	gt64240_td_t *td;
++	u32 cmdstat;
++
++	cdp = (GT64240ETH_READ(gp, GT64240_ETH_CURR_TX_DESC_PTR0)
++	       - gp->tx_ring_dma) / sizeof(gt64240_td_t);
++
++	if (gt64240_debug > 3) {	/*+prk17aug01 */
++		nextOut = gp->tx_next_out;
++		printk
++		    ("%s: tx_complete: TX_PTR0=0x%08x, cdp=%d. nextOut=%d.\n",
++		     dev->name, GT64240ETH_READ(gp,
++						GT64240_ETH_CURR_TX_DESC_PTR0),
++		     cdp, nextOut);
++		td = &gp->tx_ring[nextOut];
++	}
++
++/*** NEED to check and CLEAR these errors every time thru here: ***/
++	if (gt64240_debug > 2) {
++		if (GT64240_READ(COMM_UNIT_INTERRUPT_CAUSE))
++			printk
++			    ("%s: gt64240_tx_complete: CIU Cause=%08x, Mask=%08x, EAddr=%08x\n",
++			     dev->name,
++			     GT64240_READ(COMM_UNIT_INTERRUPT_CAUSE),
++			     GT64240_READ(COMM_UNIT_INTERRUPT_MASK),
++			     GT64240_READ(COMM_UNIT_ERROR_ADDRESS));
++		GT64240_WRITE(COMM_UNIT_INTERRUPT_CAUSE, 0);
++	}
++	// Continue until we reach the current descriptor pointer
++	for (nextOut = gp->tx_next_out; nextOut != cdp;
++	     nextOut = (nextOut + 1) % TX_RING_SIZE) {
++
++		if (--gp->intr_work_done == 0)
++			break;
++
++		td = &gp->tx_ring[nextOut];
++		cmdstat = td->cmdstat;
++
++		if (cmdstat & (u32) txOwn) {
++			// DMA is not finished writing descriptor???
++			// Leave and come back later to pick-up where we left off.
++			break;
++		}
++		// increment Tx error stats
++		if (cmdstat & (u32) txErrorSummary) {
++			if (gt64240_debug > 2)
++				printk
++				    ("%s: tx_complete: Tx error, cmdstat = %x\n",
++				     dev->name, cmdstat);
++			gp->stats.tx_errors++;
++			if (cmdstat & (u32) txReTxLimit)
++				gp->stats.tx_aborted_errors++;
++			if (cmdstat & (u32) txUnderrun)
++				gp->stats.tx_fifo_errors++;
++			if (cmdstat & (u32) txLateCollision)
++				gp->stats.tx_window_errors++;
++		}
++
++		if (cmdstat & (u32) txCollision)
++			gp->stats.collisions +=
++			    (unsigned long) ((cmdstat & txReTxCntMask) >>
++					     txReTxCntBit);
++
++		// Wake the queue if the ring was full
++		if (gp->tx_full) {
++			gp->tx_full = 0;
++			if (gp->last_psr & psrLink) {
++				netif_wake_queue(dev);
++			}
++		}
++		// decrement tx ring buffer count
++		if (gp->tx_count)
++			gp->tx_count--;
++
++		// free the skb
++		if (gp->tx_skbuff[nextOut]) {
++			if (gt64240_debug > 3)
++				printk
++				    ("%s: tx_complete: good Tx, skb=%p\n",
++				     dev->name, gp->tx_skbuff[nextOut]);
++			dev_kfree_skb_irq(gp->tx_skbuff[nextOut]);
++			gp->tx_skbuff[nextOut] = NULL;
++		} else {
++			printk("%s: tx_complete: no skb!\n", dev->name);
++		}
++	}
++
++	gp->tx_next_out = nextOut;
++
++	if ((status & icrTxEndLow) && gp->tx_count != 0) {
++		// we must restart the DMA
++		GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_COMM,
++				 sdcmrERD | sdcmrTXDL);
++	}
++}
++
++static irqreturn_t gt64240_interrupt(int irq, void *dev_id,
++	struct pt_regs *regs)
++{
++	struct net_device *dev = (struct net_device *) dev_id;
++	struct gt64240_private *gp = netdev_priv(dev);
++	u32 status;
++
++	if (dev == NULL) {
++		printk("%s: isr: null dev ptr\n", dev->name);
++		return IRQ_NONE;
++	}
++
++	spin_lock(&gp->lock);
++
++	if (gt64240_debug > 3)
++		printk("%s: isr: entry\n", dev->name);
++
++	gp->intr_work_done = max_interrupt_work;
++
++	while (gp->intr_work_done > 0) {
++
++		status = GT64240ETH_READ(gp, GT64240_ETH_INT_CAUSE);
++#ifdef GT64240_NAPI
++		/* dont ack Rx interrupts */
++		if (!(status & icrRxBuffer))
++			GT64240ETH_WRITE(gp, GT64240_ETH_INT_CAUSE, 0);
++#else
++		// ACK interrupts
++		GT64240ETH_WRITE(gp, GT64240_ETH_INT_CAUSE, 0);
++#endif
++
++		if (gt64240_debug > 3)
++			printk("%s: isr: work=%d., icr=%x\n", dev->name,
++			       gp->intr_work_done, status);
++
++		if ((status & icrEtherIntSum) == 0) {
++			if (!(status &
++			      (icrTxBufferLow | icrTxBufferHigh |
++			       icrRxBuffer))) {
++				/* exit from the while() loop */
++				break;
++			}
++		}
++
++		if (status & icrMIIPhySTC) {
++			u32 psr =
++			    GT64240ETH_READ(gp, GT64240_ETH_PORT_STATUS);
++			if (gp->last_psr != psr) {
++				printk("%s: port status: 0x%08x\n",
++				       dev->name, psr);
++				printk
++				    ("%s:    %s MBit/s, %s-duplex, flow-control %s, link is %s,\n",
++				     dev->name,
++				     psr & psrSpeed ? "100" : "10",
++				     psr & psrDuplex ? "full" : "half",
++				     psr & psrFctl ? "disabled" :
++				     "enabled",
++				     psr & psrLink ? "up" : "down");
++				printk
++				    ("%s:    TxLowQ is %s, TxHighQ is %s, Transmitter is %s\n",
++				     dev->name,
++				     psr & psrTxLow ? "running" :
++				     "stopped",
++				     psr & psrTxHigh ? "running" :
++				     "stopped",
++				     psr & psrTxInProg ? "on" : "off");
++
++				if ((psr & psrLink) && !gp->tx_full &&
++				    netif_queue_stopped(dev)) {
++					printk
++					    ("%s: isr: Link up, waking queue.\n",
++					     dev->name);
++					netif_wake_queue(dev);
++				} else if (!(psr & psrLink)
++					   && !netif_queue_stopped(dev)) {
++					printk
++					    ("%s: isr: Link down, stopping queue.\n",
++					     dev->name);
++					netif_stop_queue(dev);
++				}
++
++				gp->last_psr = psr;
++			}
++		}
++
++		if (status & (icrTxBufferLow | icrTxEndLow))
++			gt64240_tx_complete(dev, status);
++
++		if (status & icrRxBuffer) {
++#ifdef GT64240_NAPI
++			if (netif_rx_schedule_prep(dev)) {
++				disable_ether_irq(dev);
++				__netif_rx_schedule(dev);
++			}
++#else
++			gt64240_rx(dev, status);
++#endif
++		}
++		// Now check TX errors (RX errors were handled in gt64240_rx)
++		if (status & icrTxErrorLow) {
++			printk("%s: isr: Tx resource error\n", dev->name);
++		}
++
++		if (status & icrTxUdr) {
++			printk("%s: isr: Tx underrun error\n", dev->name);
++		}
++	}
++
++	if (gp->intr_work_done == 0) {
++		// ACK any remaining pending interrupts
++		GT64240ETH_WRITE(gp, GT64240_ETH_INT_CAUSE, 0);
++		if (gt64240_debug > 3)
++			printk("%s: isr: hit max work\n", dev->name);
++	}
++
++	if (gt64240_debug > 3)
++		printk("%s: isr: exit, icr=%x\n",
++		       dev->name, GT64240ETH_READ(gp,
++						  GT64240_ETH_INT_CAUSE));
++
++	spin_unlock(&gp->lock);
++
++	return IRQ_HANDLED;
++}
++
++static void enable_ether_irq(struct net_device *dev)
++{
++	struct gt64240_private *gp = netdev_priv(dev);
++	u32 intMask;
++
++	intMask =
++	    icrTxBufferLow | icrTxEndLow | icrTxErrorLow |
++	    icrTxBufferHigh | icrTxEndHigh | icrTxErrorHigh | icrTxUdr |
++	    icrRxBuffer | icrRxOVR | icrRxError | icrMIIPhySTC |
++	    icrEtherIntSum;
++
++
++//- GT64240ETH_WRITE(gp, GT64240_ETH_INT_CAUSE, 0); /* CLEAR existing ints */
++	// unmask device interrupts:
++	GT64240ETH_WRITE(gp, GT64240_ETH_INT_MASK, intMask);
++
++	// now route ethernet interrupts to GT PCI1 (eth0 and eth1 will be
++	// sharing it).
++	intMask = MV_READ(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH);
++	intMask |= 1 << gp->port_num;
++	MV_WRITE(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, intMask);
++}
++
++static void disable_ether_irq(struct net_device *dev)
++{
++	struct gt64240_private *gp = netdev_priv(dev);
++	u32 intMask;
++
++	intMask = MV_READ(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH);
++	intMask &= ~(1 << gp->port_num);
++	MV_WRITE(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, intMask);
++
++	// mask all device interrupts: 
++	GT64240ETH_WRITE(gp, GT64240_ETH_INT_MASK, 0);
++}
++
++/*
++ * Probe for a GT64240 ethernet controller.
++ */
++static int __init gt64240_probe(void)
++{
++	int found = 0;
++	int i;
++
++	parse_mac_addr_options();
++
++	for (i = 0; i < NUM_INTERFACES; i++) {
++		unsigned long base_addr = gt64240_iflist[i].port;
++
++		if (check_region(base_addr, GT64240_ETH_IO_SIZE)) {
++			printk("gt64240_probe: ioaddr 0x%lx taken?\n",
++			       base_addr);
++			continue;
++		}
++
++		if (gt64240_probe1(base_addr, gt64240_iflist[i].irq, i) == 0) {
++			/*
++			 * Does not seem to be the "traditional" way folks do
++			 * this, but I want to init both eth ports if at all
++			 * possible!
++			 *
++			 * So, until I find out the "correct" way to do this:
++			 */
++			if (++found == NUM_INTERFACES)	/* That's all of them */
++				return 0;
++		}
++	}
++
++	if (found)
++		return 0;	/* as long as we found at least one! */
++
++	return -ENODEV;
++}
++
++module_init(gt64240_probe);
++
++static int __init gt64240_probe1(unsigned long ioaddr, int irq, int port_num)
++{
++	struct net_device *dev = NULL;
++	static unsigned version_printed = 0;
++	struct gt64240_private *gp = NULL;
++	int retval;
++	u32 cpuConfig;
++
++	dev = alloc_etherdev(sizeof(struct gt64240_private));
++	if (!dev)
++		return -ENOMEM;
++
++	if (irq < 0) {
++		printk
++		    ("gt64240_probe1: irq unknown - probing not supported\n");
++		return -ENODEV;
++	}
++#if 1				/* KLUDGE Alert: no check on return value: */
++	if (!request_region(ioaddr, GT64240_ETH_IO_SIZE, "gt64240eth"))
++		printk("*** request_region() failed!\n");
++#endif
++
++	cpuConfig = GT64240_READ(CPU_CONFIGURATION);
++	printk("gt64240_probe1: cpu in %s-endian mode\n",
++	       (cpuConfig & (1 << 12)) ? "little" : "big");
++
++	printk("%s: GT64240 found at ioaddr 0x%lx, irq %d.\n",
++	       dev->name, ioaddr, irq);
++
++	if (gt64240_debug && version_printed++ == 0)
++		printk("%s: %s", dev->name, version);
++
++	/* private struct aligned and zeroed by init_etherdev */
++	/* Fill in the 'dev' fields. */
++	dev->base_addr = ioaddr;
++	dev->irq = irq;
++	memcpy(dev->dev_addr, gt64240_station_addr[port_num],
++	       sizeof(dev->dev_addr));
++
++	printk("%s: HW Address ", dev->name);
++	dump_hw_addr(dev->dev_addr);
++
++	gp = dev->priv;
++
++	gp->msg_enable = (debug < 0 ? GT64240_MSG_ENABLE : debug);
++	gp->port_num = port_num;
++	gp->io_size = GT64240_ETH_IO_SIZE;
++	gp->port_offset = port_num * GT64240_ETH_IO_SIZE;
++	gp->phy_addr = gt64240_phy_addr[port_num];
++
++	printk("%s: GT64240 ethernet port %d\n", dev->name, gp->port_num);
++
++#ifdef GT64240_NAPI
++	printk("Rx NAPI supported \n");
++#endif
++
++/* MII Initialization */
++	gp->mii_if.dev = dev;
++	gp->mii_if.phy_id = dev->base_addr;
++	gp->mii_if.mdio_read = read_MII;
++	gp->mii_if.mdio_write = write_MII;
++	gp->mii_if.advertising = read_MII(dev, gp->phy_addr, MII_ADVERTISE);
++
++	// Allocate Rx and Tx descriptor rings
++	if (gp->rx_ring == NULL) {
++		// All descriptors in ring must be 16-byte aligned
++		gp->rx_ring = dma_alloc_noncoherent(NULL,
++					sizeof(gt64240_rd_t) * RX_RING_SIZE +
++					sizeof(gt64240_td_t) * TX_RING_SIZE,
++					&gp->rx_ring_dma, GFP_KERNEL);
++		if (gp->rx_ring == NULL) {
++			retval = -ENOMEM;
++			goto free_region;
++		}
++
++		gp->tx_ring = (gt64240_td_t *) (gp->rx_ring + RX_RING_SIZE);
++		gp->tx_ring_dma =
++			gp->rx_ring_dma + sizeof(gt64240_rd_t) * RX_RING_SIZE;
++	}
++	// Allocate the Rx Data Buffers
++	if (gp->rx_buff == NULL) {
++		gp->rx_buff = dma_alloc_coherent(NULL,
++				PKT_BUF_SZ * RX_RING_SIZE, &gp->rx_buff_dma,
++				GFP_KERNEL);
++		if (gp->rx_buff == NULL) {
++			dma_free_noncoherent(NULL,
++				sizeof(gt64240_rd_t) * RX_RING_SIZE +
++				sizeof(gt64240_td_t) * TX_RING_SIZE,
++				gp->rx_ring, gp->rx_ring_dma);
++			retval = -ENOMEM;
++			goto free_region;
++		}
++	}
++
++	if (gt64240_debug > 3)
++		printk("%s: gt64240_probe1, rx_ring=%p, tx_ring=%p\n",
++		       dev->name, gp->rx_ring, gp->tx_ring);
++
++	// Allocate Rx Hash Table
++	if (gp->hash_table == NULL) {
++		gp->hash_table = dma_alloc_coherent(NULL,
++				RX_HASH_TABLE_SIZE, &gp->hash_table_dma,
++				GFP_KERNEL);
++		if (gp->hash_table == NULL) {
++			dma_free_noncoherent(NULL,
++				sizeof(gt64240_rd_t) * RX_RING_SIZE +
++				sizeof(gt64240_td_t) * TX_RING_SIZE,
++				gp->rx_ring, gp->rx_ring_dma);
++			dma_free_noncoherent(NULL, PKT_BUF_SZ * RX_RING_SIZE,
++				gp->rx_buff, gp->rx_buff_dma);
++			retval = -ENOMEM;
++			goto free_region;
++		}
++	}
++
++	if (gt64240_debug > 3)
++		printk("%s: gt64240_probe1, hash=%p\n",
++		       dev->name, gp->hash_table);
++
++	spin_lock_init(&gp->lock);
++
++	dev->open = gt64240_open;
++	dev->hard_start_xmit = gt64240_tx;
++	dev->stop = gt64240_close;
++	dev->get_stats = gt64240_get_stats;
++	dev->do_ioctl = gt64240_ioctl;
++	dev->set_multicast_list = gt64240_set_rx_mode;
++	dev->tx_timeout = gt64240_tx_timeout;
++	dev->watchdog_timeo = GT64240ETH_TX_TIMEOUT;
++
++#ifdef GT64240_NAPI
++	dev->poll = gt64240_poll;
++	dev->weight = 64;
++#endif
++	dev->ethtool_ops = &gp_ethtool_ops;
++
++	/* Fill in the fields of the device structure with ethernet values. */
++	return 0;
++
++free_region:
++	release_region(ioaddr, gp->io_size);
++	unregister_netdev(dev);
++	free_netdev(dev);
++	printk("%s: gt64240_probe1 failed.  Returns %d\n",
++	       dev->name, retval);
++	return retval;
++}
++
++
++static void reset_tx(struct net_device *dev)
++{
++	struct gt64240_private *gp = netdev_priv(dev);
++	int i;
++
++	abort(dev, sdcmrAT);
++
++	for (i = 0; i < TX_RING_SIZE; i++) {
++		if (gp->tx_skbuff[i]) {
++			if (in_interrupt())
++				dev_kfree_skb_irq(gp->tx_skbuff[i]);
++			else
++				dev_kfree_skb(gp->tx_skbuff[i]);
++			gp->tx_skbuff[i] = NULL;
++		}
++//-     gp->tx_ring[i].cmdstat = 0; // CPU owns
++		gp->tx_ring[i].cmdstat =
++		    (u32) (txGenCRC | txEI | txPad | txFirst | txLast);
++		gp->tx_ring[i].byte_cnt = 0;
++		gp->tx_ring[i].buff_ptr = 0;
++		gp->tx_ring[i].next =
++		    gp->tx_ring_dma + sizeof(gt64240_td_t) * (i + 1);
++		if (gt64240_debug > 4)
++			dump_tx_desc(dev, i);
++	}
++	/* Wrap the ring. */
++	gp->tx_ring[i - 1].next = gp->tx_ring_dma;
++	if (gt64240_debug > 4)
++		dump_tx_desc(dev, i - 1);
++
++	// setup only the lowest priority TxCDP reg
++	GT64240ETH_WRITE(gp, GT64240_ETH_CURR_TX_DESC_PTR0,
++			 gp->tx_ring_dma);
++//- GT64240ETH_WRITE(gp, GT64240_ETH_CURR_TX_DESC_PTR0, 0);     /* ROLLINS */
++//- GT64240ETH_WRITE(gp, GT64240_ETH_CURR_TX_DESC_PTR0,virt_to_phys(&gp->tx_ring[0]));  /* ROLLINS */
++
++	GT64240ETH_WRITE(gp, GT64240_ETH_CURR_TX_DESC_PTR1, 0);
++
++	// init Tx indeces and pkt counter
++	gp->tx_next_in = gp->tx_next_out = 0;
++	gp->tx_count = 0;
++}
++
++static void reset_rx(struct net_device *dev)
++{
++	struct gt64240_private *gp = netdev_priv(dev);
++	int i;
++
++	abort(dev, sdcmrAR);
++
++	for (i = 0; i < RX_RING_SIZE; i++) {
++		gp->rx_ring[i].next =
++		    gp->rx_ring_dma + sizeof(gt64240_rd_t) * (i + 1);
++		gp->rx_ring[i].buff_ptr = gp->rx_buff_dma + i * PKT_BUF_SZ;
++		gp->rx_ring[i].buff_sz = PKT_BUF_SZ;
++		gp->rx_ring[i].byte_cnt = 0;	/* just for debug printk's */
++		// Give ownership to device, set first and last, enable interrupt
++		gp->rx_ring[i].cmdstat =
++		    (uint32_t) (rxFirst | rxLast | rxOwn | rxEI);
++		if (gt64240_debug > 4)
++			dump_rx_desc(dev, i);
++	}
++	/* Wrap the ring. */
++	gp->rx_ring[i - 1].next = gp->rx_ring_dma;
++	if (gt64240_debug > 4)
++		dump_rx_desc(dev, i - 1);
++
++	// Setup only the lowest priority RxFDP and RxCDP regs
++	for (i = 0; i < 4; i++) {
++		if (i == 0) {
++			GT64240ETH_WRITE(gp, GT64240_ETH_1ST_RX_DESC_PTR0,
++					 gp->rx_ring_dma);
++			GT64240ETH_WRITE(gp, GT64240_ETH_CURR_RX_DESC_PTR0,
++					 gp->rx_ring_dma);
++		} else {
++			GT64240ETH_WRITE(gp,
++					 GT64240_ETH_1ST_RX_DESC_PTR0 +
++					 i * 4, 0);
++			GT64240ETH_WRITE(gp,
++					 GT64240_ETH_CURR_RX_DESC_PTR0 +
++					 i * 4, 0);
++		}
++	}
++
++	// init Rx NextOut index
++	gp->rx_next_out = 0;
++}
++
++
++static int gt64240_init(struct net_device *dev)
++{
++	struct gt64240_private *gp = netdev_priv(dev);
++
++	if (gt64240_debug > 3) {
++		printk("%s: gt64240_init: dev=%p\n", dev->name, dev);
++		printk("%s: gt64240_init: scs0_lo=%04x, scs0_hi=%04x\n",
++		       dev->name, GT64240_READ(0x008),
++		       GT64240_READ(0x010));
++		printk("%s: gt64240_init: scs1_lo=%04x, scs1_hi=%04x\n",
++		       dev->name, GT64240_READ(0x208),
++		       GT64240_READ(0x210));
++		printk("%s: gt64240_init: scs2_lo=%04x, scs2_hi=%04x\n",
++		       dev->name, GT64240_READ(0x018),
++		       GT64240_READ(0x020));
++		printk("%s: gt64240_init: scs3_lo=%04x, scs3_hi=%04x\n",
++		       dev->name, GT64240_READ(0x218),
++		       GT64240_READ(0x220));
++	}
++	// Stop and disable Port
++	hard_stop(dev);
++
++	GT64240_WRITE(COMM_UNIT_INTERRUPT_MASK, 0x07070777);	/*+prk21aug01 */
++	if (gt64240_debug > 2)
++		printk
++		    ("%s: gt64240_init: CIU Cause=%08x, Mask=%08x, EAddr=%08x\n",
++		     dev->name, GT64240_READ(COMM_UNIT_INTERRUPT_CAUSE),
++		     GT64240_READ(COMM_UNIT_INTERRUPT_MASK),
++		     GT64240_READ(COMM_UNIT_ERROR_ADDRESS));
++
++	// Set-up hash table
++	memset(gp->hash_table, 0, RX_HASH_TABLE_SIZE);	// clear it
++	gp->hash_mode = 0;
++	// Add a single entry to hash table - our ethernet address
++	gt64240_add_hash_entry(dev, dev->dev_addr);
++	// Set-up DMA ptr to hash table
++	GT64240ETH_WRITE(gp, GT64240_ETH_HASH_TBL_PTR, gp->hash_table_dma);
++	if (gt64240_debug > 3)
++		printk("%s: gt64240_init: Hash Tbl Ptr=%x\n", dev->name,
++		       GT64240ETH_READ(gp, GT64240_ETH_HASH_TBL_PTR));
++
++	// Setup Tx
++	reset_tx(dev);
++
++	if (gt64240_debug > 3)
++		printk("%s: gt64240_init: Curr Tx Desc Ptr0=%x\n",
++		       dev->name, GT64240ETH_READ(gp,
++						  GT64240_ETH_CURR_TX_DESC_PTR0));
++
++	// Setup Rx
++	reset_rx(dev);
++
++	if (gt64240_debug > 3)
++		printk("%s: gt64240_init: 1st/Curr Rx Desc Ptr0=%x/%x\n",
++		       dev->name, GT64240ETH_READ(gp,
++						  GT64240_ETH_1ST_RX_DESC_PTR0),
++		       GT64240ETH_READ(gp, GT64240_ETH_CURR_RX_DESC_PTR0));
++
++	if (gt64240_debug > 3)
++		dump_MII(dev);
++
++	/* force a PHY reset -- self-clearing! */
++	write_MII(dev, gp->phy_addr, 0, 0x8000);
++
++	if (gt64240_debug > 3)
++		printk("%s: gt64240_init: PhyAD=%x\n", dev->name,
++		       GT64240_READ(GT64240_ETH_PHY_ADDR_REG));
++
++	// setup DMA
++	// We want the Rx/Tx DMA to write/read data to/from memory in
++	// Big Endian mode. Also set DMA Burst Size to 8 64Bit words.
++#ifdef DESC_DATA_BE
++	GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_CONFIG,
++			 (0xf << sdcrRCBit) | sdcrRIFB | (3 <<
++							  sdcrBSZBit));
++#else
++	GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_CONFIG, sdcrBLMR | sdcrBLMT |
++//-                  (0xf<<sdcrRCBit) | sdcrRIFB | (3<<sdcrBSZBit));
++			 (0xf << sdcrRCBit) | sdcrRIFB | (2 <<
++							  sdcrBSZBit));
++#endif
++
++	if (gt64240_debug > 3)
++		printk("%s: gt64240_init: SDMA Config=%x\n", dev->name,
++		       GT64240ETH_READ(gp, GT64240_ETH_SDMA_CONFIG));
++
++#if 0
++	// start Rx DMA
++	GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_COMM, sdcmrERD);
++#endif
++
++	if (gt64240_debug > 3)
++		printk("%s: gt64240_init: SDMA Cmd =%x\n", dev->name,
++		       GT64240ETH_READ(gp, GT64240_ETH_SDMA_COMM));
++
++#if 1
++	GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG, PORT_CONFIG);
++#endif
++
++	if (gt64240_debug > 3)
++		printk("%s: gt64240_init: Port Config=%x\n", dev->name,
++		       GT64240ETH_READ(gp, GT64240_ETH_PORT_CONFIG));
++
++	/*
++	 * Disable all Type-of-Service queueing. All Rx packets will be
++	 * treated normally and will be sent to the lowest priority
++	 * queue.
++	 *
++	 * Disable flow-control for now. FIX! support flow control?
++	 */
++
++#if 1
++	// clear all the MIB ctr regs
++	GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG_EXT,
++			 EXT_CONFIG_CLEAR);
++	read_mib_counters(gp);
++	GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG_EXT,
++			 EXT_CONFIG_CLEAR | pcxrMIBclrMode);
++
++#endif
++	if (gt64240_debug > 3)
++		printk("%s: gt64240_init: Port Config Ext=%x\n", dev->name,
++		       GT64240ETH_READ(gp, GT64240_ETH_PORT_CONFIG_EXT));
++
++	if (gt64240_debug > 3)
++		printk("%s: gt64240_init: Port Command=%x\n", dev->name,
++		       GT64240ETH_READ(gp, GT64240_ETH_PORT_COMMAND));
++	GT64240ETH_WRITE(gp, GT64240_ETH_PORT_COMMAND, 0x0);
++
++	netif_start_queue(dev);
++
++	/* enable the port */
++	GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG,
++			 (PORT_CONFIG | pcrEN));
++	if (gt64240_debug > 3)
++		printk("%s: gt64240_init: Port Config=%x\n", dev->name,
++		       GT64240ETH_READ(gp, GT64240_ETH_PORT_CONFIG));
++#if 1
++	// start Rx DMA
++	GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_COMM, sdcmrERD);
++#endif
++
++
++	// enable interrupts
++	enable_ether_irq(dev);
++
++//---    gp->last_psr |= psrLink;   /* KLUDGE ALERT */
++
++	// we should now be receiving frames
++	return 0;
++}
++
++
++static int gt64240_open(struct net_device *dev)
++{
++	int retval;
++
++	if (gt64240_debug > 3)
++		printk("%s: gt64240_open: dev=%p\n", dev->name, dev);
++
++	if ((retval = request_irq(dev->irq, &gt64240_interrupt,
++				  SA_SHIRQ, dev->name, dev))) {
++		printk("%s: unable to get IRQ %d\n", dev->name, dev->irq);
++
++		return retval;
++	}
++	// Initialize and startup the GT-64240 ethernet port
++	if ((retval = gt64240_init(dev))) {
++		printk("%s: error in gt64240_open\n", dev->name);
++		free_irq(dev->irq, dev);
++
++		return retval;
++	}
++
++	if (gt64240_debug > 3)
++		printk("%s: gt64240_open: Initialization done.\n",
++		       dev->name);
++
++	return 0;
++}
++
++static int gt64240_close(struct net_device *dev)
++{
++	if (gt64240_debug > 3)
++		printk("%s: gt64240_close: dev=%p\n", dev->name, dev);
++
++	// stop the device
++	if (netif_device_present(dev)) {
++		netif_stop_queue(dev);
++		hard_stop(dev);
++	}
++
++	free_irq(dev->irq, dev);
++
++	return 0;
++}
++
++#ifdef GT64240_NAPI
++/*
++ * Function will release Tx skbs which are now complete
++ */
++static void gt64240_tx_fill(struct net_device *dev, u32 status)
++{
++	struct gt64240_private *gp = netdev_priv(dev);
++	int nextOut, cdp;
++	gt64240_td_t *td;
++	u32 cmdstat;
++
++	cdp = (GT64240ETH_READ(gp, GT64240_ETH_CURR_TX_DESC_PTR0)
++	       - gp->tx_ring_dma) / sizeof(gt64240_td_t);
++
++	for (nextOut = gp->tx_next_out; nextOut != cdp;
++	     nextOut = (nextOut + 1) % TX_RING_SIZE) {
++		if (--gp->intr_work_done == 0)
++			break;
++
++		td = &gp->tx_ring[nextOut];
++		cmdstat = td->cmdstat;
++
++		if (cmdstat & (u32) txOwn)
++			break;
++
++		if (gp->tx_full) {
++			gp->tx_full = 0;
++			if (gp->last_psr & psrLink) {
++				netif_wake_queue(dev);
++			}
++		}
++		// decrement tx ring buffer count
++		if (gp->tx_count)
++			gp->tx_count--;
++
++		// free the skb
++		if (gp->tx_skbuff[nextOut]) {
++			dev_kfree_skb_irq(gp->tx_skbuff[nextOut]);
++			gp->tx_skbuff[nextOut] = NULL;
++		}
++	}
++
++	gp->tx_next_out = nextOut;
++
++	if ((status & icrTxEndLow) && gp->tx_count != 0)
++		// we must restart the DMA
++		GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_COMM,
++				 sdcmrERD | sdcmrTXDL);
++}
++
++/*
++ * Main function for NAPI
++ */
++static int gt64240_poll(struct net_device *dev, int *budget)
++{
++	struct gt64240_private *gp = netdev_priv(dev);
++	unsigned long flags;
++	int done = 1, orig_budget, work_done;
++	u32 status = GT64240ETH_READ(gp, GT64240_ETH_INT_CAUSE);
++
++	spin_lock_irqsave(&gp->lock, flags);
++	gt64240_tx_fill(dev, status);
++
++	if (GT64240ETH_READ(gp, GT64240_ETH_CURR_RX_DESC_PTR0) !=
++	    gp->rx_next_out) {
++		orig_budget = *budget;
++		if (orig_budget > dev->quota)
++			orig_budget = dev->quota;
++
++		work_done = gt64240_rx(dev, status, orig_budget);
++		*budget -= work_done;
++		dev->quota -= work_done;
++		if (work_done >= orig_budget)
++			done = 0;
++		if (done) {
++			__netif_rx_complete(dev);
++			enable_ether_irq(dev);
++		}
++	}
++
++	spin_unlock_irqrestore(&gp->lock, flags);
++
++	return (done ? 0 : 1);
++}
++#endif
++
++static int gt64240_tx(struct sk_buff *skb, struct net_device *dev)
++{
++	struct gt64240_private *gp = netdev_priv(dev);
++	unsigned long flags;
++	int nextIn;
++
++	spin_lock_irqsave(&gp->lock, flags);
++
++	nextIn = gp->tx_next_in;
++
++	if (gt64240_debug > 3) {
++		printk("%s: gt64240_tx: nextIn=%d.\n", dev->name, nextIn);
++	}
++
++	if (gp->tx_count >= TX_RING_SIZE) {
++		printk("%s: Tx Ring full, pkt dropped.\n", dev->name);
++		gp->stats.tx_dropped++;
++		spin_unlock_irqrestore(&gp->lock, flags);
++		return 1;
++	}
++
++	if (!(gp->last_psr & psrLink)) {
++		printk("%s: gt64240_tx: Link down, pkt dropped.\n",
++		       dev->name);
++		gp->stats.tx_dropped++;
++		spin_unlock_irqrestore(&gp->lock, flags);
++//---   dump_MII(dev);          /* KLUDGE ALERT !!! */
++		return 1;
++	}
++
++	if (gp->tx_ring[nextIn].cmdstat & txOwn) {
++		printk
++		    ("%s: gt64240_tx: device owns descriptor, pkt dropped.\n",
++		     dev->name);
++		gp->stats.tx_dropped++;
++		// stop the queue, so Tx timeout can fix it
++		netif_stop_queue(dev);
++		spin_unlock_irqrestore(&gp->lock, flags);
++		return 1;
++	}
++	// Prepare the Descriptor at tx_next_in
++	gp->tx_skbuff[nextIn] = skb;
++	gp->tx_ring[nextIn].byte_cnt = skb->len;
++	gp->tx_ring[nextIn].buff_ptr = virt_to_phys(skb->data);
++
++	// make sure packet gets written back to memory
++	dma_cache_wback_inv((unsigned long) (skb->data), skb->len);
++	mb();
++
++	// Give ownership to device, set first and last desc, enable interrupt
++	// Setting of ownership bit must be *last*!
++	gp->tx_ring[nextIn].cmdstat =
++	    txOwn | txGenCRC | txEI | txPad | txFirst | txLast;
++
++	if (gt64240_debug > 5) {
++		dump_tx_desc(dev, nextIn);
++	}
++	// increment tx_next_in with wrap
++	gp->tx_next_in = (nextIn + 1) % TX_RING_SIZE;
++
++//+prk20aug01:
++	if (0) {		/* ROLLINS */
++		GT64240ETH_WRITE(gp, GT64240_ETH_CURR_TX_DESC_PTR0,
++				 virt_to_phys(&gp->tx_ring[nextIn]));
++	}
++
++	if (gt64240_debug > 3) {	/*+prk17aug01 */
++		printk
++		    ("%s: gt64240_tx: TX_PTR0=0x%08x, EthPortStatus=0x%08x\n",
++		     dev->name, GT64240ETH_READ(gp,
++						GT64240_ETH_CURR_TX_DESC_PTR0),
++		     GT64240ETH_READ(gp, GT64240_ETH_PORT_STATUS));
++	}
++	// If DMA is stopped, restart
++	if (!((GT64240ETH_READ(gp, GT64240_ETH_PORT_STATUS)) & psrTxLow)) {
++		GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_COMM,
++				 sdcmrERD | sdcmrTXDL);
++	}
++
++	if (gt64240_debug > 3) {	/*+prk17aug01 */
++		printk
++		    ("%s: gt64240_tx: TX_PTR0=0x%08x, EthPortStatus=0x%08x\n",
++		     dev->name, GT64240ETH_READ(gp,
++						GT64240_ETH_CURR_TX_DESC_PTR0),
++		     GT64240ETH_READ(gp, GT64240_ETH_PORT_STATUS));
++	}
++	// increment count and stop queue if full
++	if (++gp->tx_count >= TX_RING_SIZE) {
++		gp->tx_full = 1;
++		netif_stop_queue(dev);
++	}
++
++	dev->trans_start = jiffies;
++	spin_unlock_irqrestore(&gp->lock, flags);
++
++	return 0;
++}
++
++
++static int
++#ifdef GT64240_NAPI
++gt64240_rx(struct net_device *dev, u32 status, int budget)
++#else
++gt64240_rx(struct net_device *dev, u32 status)
++#endif
++{
++	struct gt64240_private *gp = netdev_priv(dev);
++	struct sk_buff *skb;
++	int pkt_len, nextOut, cdp;
++	gt64240_rd_t *rd;
++	u32 cmdstat;
++
++	if (gt64240_debug > 3)
++		printk("%s: gt64240_rx: dev=%p, status=%x\n",
++		       dev->name, dev, status);
++
++	cdp = (GT64240ETH_READ(gp, GT64240_ETH_CURR_RX_DESC_PTR0)
++	       - gp->rx_ring_dma) / sizeof(gt64240_rd_t);
++
++	// Continue until we reach the current descriptor pointer
++	for (nextOut = gp->rx_next_out; nextOut != cdp;
++	     nextOut = (nextOut + 1) % RX_RING_SIZE) {
++
++#ifdef GT64240_NAPI
++		if (budget <= 0)
++			break;
++
++		budget--;
++#endif
++
++		if (--gp->intr_work_done == 0)
++			break;
++
++		if (gt64240_debug > 4)
++			dump_rx_desc(dev, nextOut);
++
++		rd = &gp->rx_ring[nextOut];
++		cmdstat = rd->cmdstat;
++
++		if (gt64240_debug > 3)
++			printk("%s: isr: Rx desc cmdstat=%x, nextOut=%d\n",
++			       dev->name, cmdstat, nextOut);
++
++		if (cmdstat & (u32) rxOwn) {
++			if (gt64240_debug > 2)
++				printk
++				    ("%s: gt64240_rx: device owns descriptor!\n",
++				     dev->name);
++			// DMA is not finished updating descriptor???
++			// Leave and come back later to pick-up where we left off.
++			break;
++		}
++		// must be first and last (ie only) buffer of packet
++		if (!(cmdstat & (u32) rxFirst)
++		    || !(cmdstat & (u32) rxLast)) {
++			printk
++			    ("%s: gt64240_rx: desc not first and last!\n",
++			     dev->name);
++			cmdstat |= (u32) rxOwn;
++			rd->cmdstat = cmdstat;
++			continue;
++		}
++		// Drop this received pkt if there were any errors
++		if ((cmdstat & (u32) rxErrorSummary)
++		    || (status & icrRxError)) {
++			// update the detailed rx error counters that are not covered
++			// by the MIB counters.
++			if (cmdstat & (u32) rxOverrun)
++				gp->stats.rx_fifo_errors++;
++			cmdstat |= (u32) rxOwn;
++			rd->cmdstat = cmdstat;
++			continue;
++		}
++
++		pkt_len = rd->byte_cnt;
++
++		/* Create new skb. */
++//      skb = dev_alloc_skb(pkt_len+2);
++		skb = dev_alloc_skb(1538);
++		if (skb == NULL) {
++			printk("%s: Memory squeeze, dropping packet.\n",
++			       dev->name);
++			gp->stats.rx_dropped++;
++			cmdstat |= (u32) rxOwn;
++			rd->cmdstat = cmdstat;
++			continue;
++		}
++		skb->dev = dev;
++		skb_reserve(skb, 2);	/* 16 byte IP header align */
++		memcpy(skb_put(skb, pkt_len),
++		       &gp->rx_buff[nextOut * PKT_BUF_SZ], pkt_len);
++		skb->protocol = eth_type_trans(skb, dev);
++
++		/* NIC performed some checksum computation */
++		skb->ip_summed = CHECKSUM_UNNECESSARY;
++#ifdef GT64240_NAPI
++		netif_receive_skb(skb);
++#else
++		netif_rx(skb);	/* pass the packet to upper layers */
++#endif
++
++		// now we can release ownership of this desc back to device
++		cmdstat |= (u32) rxOwn;
++		rd->cmdstat = cmdstat;
++
++		dev->last_rx = jiffies;
++	}
++
++	if (gt64240_debug > 3 && nextOut == gp->rx_next_out)
++		printk("%s: gt64240_rx: RxCDP did not increment?\n",
++		       dev->name);
++
++	gp->rx_next_out = nextOut;
++	return 0;
++}
++
++
++static void gt64240_tx_timeout(struct net_device *dev)
++{
++	struct gt64240_private *gp = netdev_priv(dev);
++	unsigned long flags;
++
++	spin_lock_irqsave(&gp->lock, flags);
++
++
++	if (!(gp->last_psr & psrLink)) {
++		spin_unlock_irqrestore(&gp->lock, flags);
++	} else {
++		printk("======------> gt64240_tx_timeout: %d jiffies \n",
++		       GT64240ETH_TX_TIMEOUT);
++
++		disable_ether_irq(dev);
++		spin_unlock_irqrestore(&gp->lock, flags);
++		reset_tx(dev);
++		enable_ether_irq(dev);
++
++		netif_wake_queue(dev);
++	}
++}
++
++
++static void gt64240_set_rx_mode(struct net_device *dev)
++{
++	struct gt64240_private *gp = netdev_priv(dev);
++	unsigned long flags;
++	struct dev_mc_list *mcptr;
++
++	if (gt64240_debug > 3)
++		printk("%s: gt64240_set_rx_mode: dev=%p, flags=%x\n",
++		       dev->name, dev, dev->flags);
++
++	// stop the Receiver DMA
++	abort(dev, sdcmrAR);
++
++	spin_lock_irqsave(&gp->lock, flags);
++
++	if (dev->flags & IFF_PROMISC)
++		GT64240ETH_SETBIT(gp, GT64240_ETH_PORT_CONFIG, pcrPM);
++	else
++		GT64240ETH_CLRBIT(gp, GT64240_ETH_PORT_CONFIG, pcrPM);
++/*
++	GT64240ETH_WRITE(gp, GT64240_ETH_PORT_CONFIG,
++		(PORT_CONFIG | pcrPM | pcrEN));
++*/
++
++	memset(gp->hash_table, 0, RX_HASH_TABLE_SIZE);	// clear hash table
++	// Add our ethernet address
++	gt64240_add_hash_entry(dev, dev->dev_addr);
++	if (dev->mc_count) {
++		for (mcptr = dev->mc_list; mcptr; mcptr = mcptr->next) {
++			if (gt64240_debug > 2) {
++				printk("%s: gt64240_set_rx_mode: addr=\n",
++				       dev->name);
++				dump_hw_addr(mcptr->dmi_addr);
++			}
++			gt64240_add_hash_entry(dev, mcptr->dmi_addr);
++		}
++	}
++
++	if (gt64240_debug > 3)
++		printk("%s: gt64240_set_rx: Port Config=%x\n", dev->name,
++		       GT64240ETH_READ(gp, GT64240_ETH_PORT_CONFIG));
++
++	// restart Rx DMA
++	GT64240ETH_WRITE(gp, GT64240_ETH_SDMA_COMM, sdcmrERD);
++
++	spin_unlock_irqrestore(&gp->lock, flags);
++}
++
++static struct net_device_stats *gt64240_get_stats(struct net_device *dev)
++{
++	struct gt64240_private *gp = netdev_priv(dev);
++	unsigned long flags;
++
++	if (gt64240_debug > 3)
++		printk("%s: gt64240_get_stats: dev=%p\n", dev->name, dev);
++
++	if (netif_device_present(dev)) {
++		spin_lock_irqsave(&gp->lock, flags);
++		update_stats(gp);
++		spin_unlock_irqrestore(&gp->lock, flags);
++	}
++
++	return &gp->stats;
++}
+diff -Naur linux-2.6.17.orig/drivers/net/gt64240eth.h linux-2.6.17/drivers/net/gt64240eth.h
+--- linux-2.6.17.orig/drivers/net/gt64240eth.h	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/drivers/net/gt64240eth.h	2006-06-19 18:16:13.000000000 -0700
+@@ -9,6 +9,7 @@
+  * Copyright 2000 MontaVista Software Inc.
+  * Author: MontaVista Software, Inc.
+  *         	stevel@mvista.com or support@mvista.com
++ * Copyright 2004, 05 Ralf Baechle (ralf@linux-mips.org)
+  *
+  *  This program is free software; you can distribute it and/or modify it
+  *  under the terms of the GNU General Public License (Version 2) as
+@@ -31,6 +32,7 @@
+ #ifndef _GT64240ETH_H
+ #define _GT64240ETH_H
+ 
++#include <linux/config.h>
+ #include <asm/gt64240.h>
+ 
+ #define ETHERNET_PORTS_DIFFERENCE_OFFSETS	0x400
+@@ -108,10 +110,10 @@
+ #define REV_GT64240A 0x10
+ 
+ #define GT64240ETH_READ(gp, offset)					\
+-	GT_READ((gp)->port_offset + (offset))
++	MV_READ((gp)->port_offset + (offset))
+ 
+ #define GT64240ETH_WRITE(gp, offset, data)				\
+-	GT_WRITE((gp)->port_offset + (offset), (data))
++	MV_WRITE((gp)->port_offset + (offset), (data))
+ 
+ #define GT64240ETH_SETBIT(gp, offset, bits)				\
+ 	GT64240ETH_WRITE((gp), (offset),				\
+@@ -121,8 +123,8 @@
+ 	GT64240ETH_WRITE((gp), (offset),				\
+ 	                 GT64240ETH_READ((gp), (offset)) & ~(bits))
+ 
+-#define GT64240_READ(ofs)		GT_READ(ofs)
+-#define GT64240_WRITE(ofs, data)	GT_WRITE((ofs), (data))
++#define GT64240_READ(ofs)		MV_READ(ofs)
++#define GT64240_WRITE(ofs, data)	MV_WRITE((ofs), (data))
+ 
+ /* Bit definitions of the SMI Reg */
+ enum {
+diff -Naur linux-2.6.17.orig/drivers/net/ioc3-eth.c linux-2.6.17/drivers/net/ioc3-eth.c
+--- linux-2.6.17.orig/drivers/net/ioc3-eth.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/drivers/net/ioc3-eth.c	2006-06-19 18:16:13.000000000 -0700
+@@ -5,7 +5,7 @@
+  *
+  * Driver for SGI's IOC3 based Ethernet cards as found in the PCI card.
+  *
+- * Copyright (C) 1999, 2000, 2001, 2003 Ralf Baechle
++ * Copyright (C) 1999, 2000, 01, 03, 06 Ralf Baechle
+  * Copyright (C) 1995, 1999, 2000, 2001 by Silicon Graphics, Inc.
+  *
+  * References:
+@@ -63,12 +63,7 @@
+ #include <asm/pgtable.h>
+ #include <asm/uaccess.h>
+ #include <asm/sn/types.h>
+-#include <asm/sn/sn0/addrs.h>
+-#include <asm/sn/sn0/hubni.h>
+-#include <asm/sn/sn0/hubio.h>
+-#include <asm/sn/klconfig.h>
+ #include <asm/sn/ioc3.h>
+-#include <asm/sn/sn0/ip27.h>
+ #include <asm/pci/bridge.h>
+ 
+ /*
+@@ -96,6 +91,9 @@
+ 	u32 emcr, ehar_h, ehar_l;
+ 	spinlock_t ioc3_lock;
+ 	struct mii_if_info mii;
++	unsigned long flags;
++#define IOC3_FLAG_RX_CHECKSUMS	1
++
+ 	struct pci_dev *pdev;
+ 
+ 	/* Members used by autonegotiation  */
+@@ -145,7 +143,7 @@
+ static inline unsigned long ioc3_map(void *ptr, unsigned long vdev)
+ {
+ #ifdef CONFIG_SGI_IP27
+-	vdev <<= 58;   /* Shift to PCI64_ATTR_VIRTUAL */
++	vdev <<= 57;   /* Shift to PCI64_ATTR_VIRTUAL */
+ 
+ 	return vdev | (0xaUL << PCI64_ATTR_TARG_SHFT) | PCI64_ATTR_PREF |
+ 	       ((unsigned long)ptr & TO_PHYS_MASK);
+@@ -523,8 +521,6 @@
+ 	return &ip->stats;
+ }
+ 
+-#ifdef CONFIG_SGI_IOC3_ETH_HW_RX_CSUM
+-
+ static void ioc3_tcpudp_checksum(struct sk_buff *skb, uint32_t hwsum, int len)
+ {
+ 	struct ethhdr *eh = eth_hdr(skb);
+@@ -592,7 +588,6 @@
+ 	if (csum == 0xffff)
+ 		skb->ip_summed = CHECKSUM_UNNECESSARY;
+ }
+-#endif /* CONFIG_SGI_IOC3_ETH_HW_RX_CSUM */
+ 
+ static inline void ioc3_rx(struct ioc3_private *ip)
+ {
+@@ -627,9 +622,9 @@
+ 				goto next;
+ 			}
+ 
+-#ifdef CONFIG_SGI_IOC3_ETH_HW_RX_CSUM
+-			ioc3_tcpudp_checksum(skb, w0 & ERXBUF_IPCKSUM_MASK,len);
+-#endif
++			if (likely(ip->flags & IOC3_FLAG_RX_CHECKSUMS))
++				ioc3_tcpudp_checksum(skb,
++					w0 & ERXBUF_IPCKSUM_MASK, len);
+ 
+ 			netif_rx(skb);
+ 
+@@ -1290,9 +1285,7 @@
+ 	dev->set_multicast_list	= ioc3_set_multicast_list;
+ 	dev->set_mac_address	= ioc3_set_mac_address;
+ 	dev->ethtool_ops	= &ioc3_ethtool_ops;
+-#ifdef CONFIG_SGI_IOC3_ETH_HW_TX_CSUM
+ 	dev->features		= NETIF_F_IP_CSUM;
+-#endif
+ 
+ 	sw_physid1 = ioc3_mdio_read(dev, ip->mii.phy_id, MII_PHYSID1);
+ 	sw_physid2 = ioc3_mdio_read(dev, ip->mii.phy_id, MII_PHYSID2);
+@@ -1379,7 +1372,6 @@
+ 	uint32_t w0 = 0;
+ 	int produce;
+ 
+-#ifdef CONFIG_SGI_IOC3_ETH_HW_TX_CSUM
+ 	/*
+ 	 * IOC3 has a fairly simple minded checksumming hardware which simply
+ 	 * adds up the 1's complement checksum for the entire packet and
+@@ -1427,7 +1419,6 @@
+ 
+ 		w0 = ETXD_DOCHECKSUM | (csoff << ETXD_CHKOFF_SHIFT);
+ 	}
+-#endif /* CONFIG_SGI_IOC3_ETH_HW_TX_CSUM */
+ 
+ 	spin_lock_irq(&ip->ioc3_lock);
+ 
+@@ -1581,12 +1572,37 @@
+ 	return rc;
+ }
+ 
++static u32 ioc3_get_rx_csum(struct net_device *dev)
++{
++	struct ioc3_private *ip = netdev_priv(dev);
++
++	return ip->flags & IOC3_FLAG_RX_CHECKSUMS;
++}
++
++static int ioc3_set_rx_csum(struct net_device *dev, u32 data)
++{
++	struct ioc3_private *ip = netdev_priv(dev);
++
++	spin_lock_bh(&ip->ioc3_lock);
++	if (data)
++		ip->flags |= IOC3_FLAG_RX_CHECKSUMS;
++	else
++		ip->flags &= ~IOC3_FLAG_RX_CHECKSUMS;
++	spin_unlock_bh(&ip->ioc3_lock);
++
++	return 0;
++}
++
+ static struct ethtool_ops ioc3_ethtool_ops = {
+ 	.get_drvinfo		= ioc3_get_drvinfo,
+ 	.get_settings		= ioc3_get_settings,
+ 	.set_settings		= ioc3_set_settings,
+ 	.nway_reset		= ioc3_nway_reset,
+ 	.get_link		= ioc3_get_link,
++	.get_rx_csum		= ioc3_get_rx_csum,
++	.set_rx_csum		= ioc3_set_rx_csum,
++	.get_tx_csum		= ethtool_op_get_tx_csum,
++	.set_tx_csum		= ethtool_op_set_tx_csum
+ };
+ 
+ static int ioc3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
+diff -Naur linux-2.6.17.orig/drivers/net/Kconfig linux-2.6.17/drivers/net/Kconfig
+--- linux-2.6.17.orig/drivers/net/Kconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/drivers/net/Kconfig	2006-06-19 18:16:13.000000000 -0700
+@@ -438,6 +438,14 @@
+ 	  This is the driver for the onboard card of MIPS Magnum 4000,
+ 	  Acer PICA, Olivetti M700-10 and a few other identical OEM systems.
+ 
++config GALILEO_64240_ETH
++	tristate "Galileo GT64240 Ethernet support"
++	depends on NET_ETHERNET && MOMENCO_OCELOT_G
++	select MII
++	help
++	  This is the driver for the ethernet interfaces integrated into
++	  the Galileo (now Marvell) GT64240 chipset.
++
+ config MIPS_GT96100ETH
+ 	bool "MIPS GT96100 Ethernet support"
+ 	depends on NET_ETHERNET && MIPS_GT96100
+@@ -452,10 +460,6 @@
+ 	  If you have an Alchemy Semi AU1X00 based system
+ 	  say Y.  Otherwise, say N.
+ 
+-config NET_SB1250_MAC
+-	tristate "SB1250 Ethernet support"
+-	depends on NET_ETHERNET && SIBYTE_SB1xxx_SOC
+-
+ config SGI_IOC3_ETH
+ 	bool "SGI IOC3 Ethernet"
+ 	depends on NET_ETHERNET && PCI && SGI_IP27
+@@ -466,25 +470,13 @@
+ 	  the Ethernet-HOWTO, available from
+ 	  <http://www.tldp.org/docs.html#howto>.
+ 
+-config SGI_IOC3_ETH_HW_RX_CSUM
+-	bool "Receive hardware checksums"
+-	depends on SGI_IOC3_ETH && INET
+-	default y
+-	help
+-	  The SGI IOC3 network adapter supports TCP and UDP checksums in
+-	  hardware to offload processing of these checksums from the CPU.  At
+-	  the moment only acceleration of IPv4 is supported.  This option
+-	  enables offloading for checksums on receive.  If unsure, say Y.
+-
+-config SGI_IOC3_ETH_HW_TX_CSUM
+-	bool "Transmit hardware checksums"
+-	depends on SGI_IOC3_ETH && INET
+-	default y
++config MIPS_SIM_NET
++	tristate "MIPS simulator Network device (EXPERIMENTAL)"
++	depends on NETDEVICES && MIPS_SIM && EXPERIMENTAL
+ 	help
+-	  The SGI IOC3 network adapter supports TCP and UDP checksums in
+-	  hardware to offload processing of these checksums from the CPU.  At
+-	  the moment only acceleration of IPv4 is supported.  This option
+-	  enables offloading for checksums on transmit.  If unsure, say Y.
++	  The MIPSNET device is a simple Ethernet network device which is
++	  emulated by the MIPS Simulator.
++	  If you are not using a MIPSsim or are unsure, say N.
+ 
+ config MIPS_SIM_NET
+ 	tristate "MIPS simulator Network device (EXPERIMENTAL)"
+@@ -1993,6 +1985,10 @@
+ 
+ 	  If in doubt, say N.
+ 
++config NET_SB1250_MAC
++	tristate "SB1250 Ethernet support"
++	depends on SIBYTE_SB1xxx_SOC
++
+ config R8169_VLAN
+ 	bool "VLAN support"
+ 	depends on R8169 && VLAN_8021Q
+@@ -2195,8 +2191,8 @@
+ 	select MII
+ 	help
+ 	  This driver supports the gigabit Ethernet on the Marvell MV643XX
+-	  chipset which is used in the Momenco Ocelot C and Jaguar ATX and
+-	  Pegasos II, amongst other PPC and MIPS boards.
++	  chipset which is used in the Momenco Ocelot C Ocelot, Jaguar ATX
++	  and Pegasos II, amongst other PPC and MIPS boards.
+ 
+ config MV643XX_ETH_0
+ 	bool "MV-643XX Port 0"
+@@ -2219,6 +2215,20 @@
+ 	  This enables support for Port 2 of the Marvell MV643XX Gigabit
+ 	  Ethernet.
+ 
++config BIG_SUR_FE
++	bool "PMC-Sierra TITAN Fast Ethernet Support"
++	depends on NET_ETHERNET && PMC_BIG_SUR
++	help
++	  This enables support for the the integrated ethernet of
++	  PMC-Sierra's Big Sur SoC.
++
++config TITAN_GE
++	bool "PMC-Sierra TITAN Gigabit Ethernet Support"
++	depends on PMC_YOSEMITE
++	help
++	  This enables support for the the integrated ethernet of
++	  PMC-Sierra's Titan SoC.
++
+ endmenu
+ 
+ #
+diff -Naur linux-2.6.17.orig/drivers/net/Makefile linux-2.6.17/drivers/net/Makefile
+--- linux-2.6.17.orig/drivers/net/Makefile	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/drivers/net/Makefile	2006-06-19 18:16:13.000000000 -0700
+@@ -111,6 +111,11 @@
+ 
+ obj-$(CONFIG_MV643XX_ETH) += mv643xx_eth.o
+ 
++obj-$(CONFIG_GALILEO_64240_ETH) += gt64240eth.o
++obj-$(CONFIG_MV64340_ETH) += mv64340_eth.o
++obj-$(CONFIG_BIG_SUR_FE) += big_sur_ge.o
++obj-$(CONFIG_TITAN_GE) += titan_mdio.o titan_ge.o
++
+ obj-$(CONFIG_PPP) += ppp_generic.o slhc.o
+ obj-$(CONFIG_PPP_ASYNC) += ppp_async.o
+ obj-$(CONFIG_PPP_SYNC_TTY) += ppp_synctty.o
+diff -Naur linux-2.6.17.orig/drivers/net/sb1250-mac.c linux-2.6.17/drivers/net/sb1250-mac.c
+--- linux-2.6.17.orig/drivers/net/sb1250-mac.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/drivers/net/sb1250-mac.c	2006-06-19 18:16:13.000000000 -0700
+@@ -156,6 +156,10 @@
+ 
+ #define NUMCACHEBLKS(x) (((x)+SMP_CACHE_BYTES-1)/SMP_CACHE_BYTES)
+ 
++#define SBMAC_READCSR(t)	__raw_readq((unsigned long)t)
++#define SBMAC_WRITECSR(t,v)	__raw_writeq(v, (unsigned long)t)
++
++
+ #define SBMAC_MAX_TXDESCR	32
+ #define SBMAC_MAX_RXDESCR	32
+ 
+@@ -2416,6 +2420,11 @@
+ 			sc->sbm_dev->name);
+ 	}
+ 
++	if (periph_rev >= 2) {
++		printk(KERN_INFO "%s: enabling TCP rcv checksum\n",
++			sc->sbm_dev->name);
++	}
++
+ 	/*
+ 	 * Display Ethernet address (this is called during the config
+ 	 * process so we need to finish off the config message that
+diff -Naur linux-2.6.17.orig/drivers/net/titan_ge.c linux-2.6.17/drivers/net/titan_ge.c
+--- linux-2.6.17.orig/drivers/net/titan_ge.c	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/drivers/net/titan_ge.c	2006-06-19 18:16:13.000000000 -0700
+@@ -0,0 +1,2071 @@
++/*
++ * drivers/net/titan_ge.c - Driver for Titan ethernet ports
++ *
++ * Copyright (C) 2003 PMC-Sierra Inc.
++ * Author : Manish Lachwani (lachwani@pmc-sierra.com)
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
++ */
++
++/*
++ * The MAC unit of the Titan consists of the following:
++ *
++ * -> XDMA Engine to move data to from the memory to the MAC packet FIFO
++ * -> FIFO is where the incoming and outgoing data is placed
++ * -> TRTG is the unit that pulls the data from the FIFO for Tx and pushes
++ *    the data into the FIFO for Rx
++ * -> TMAC is the outgoing MAC interface and RMAC is the incoming.
++ * -> AFX is the address filtering block
++ * -> GMII block to communicate with the PHY
++ *
++ * Rx will look like the following:
++ * GMII --> RMAC --> AFX --> TRTG --> Rx FIFO --> XDMA --> CPU memory
++ *
++ * Tx will look like the following:
++ * CPU memory --> XDMA --> Tx FIFO --> TRTG --> TMAC --> GMII
++ *
++ * The Titan driver has support for the following performance features:
++ * -> Rx side checksumming
++ * -> Jumbo Frames
++ * -> Interrupt Coalscing
++ * -> Rx NAPI
++ * -> SKB Recycling
++ * -> Transmit/Receive descriptors in SRAM
++ * -> Fast routing for IP forwarding
++ */
++
++#include <linux/config.h>
++#include <linux/dma-mapping.h>
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/sched.h>
++#include <linux/ioport.h>
++#include <linux/interrupt.h>
++#include <linux/slab.h>
++#include <linux/string.h>
++#include <linux/errno.h>
++#include <linux/ip.h>
++#include <linux/init.h>
++#include <linux/in.h>
++#include <linux/platform_device.h>
++#include <linux/netdevice.h>
++#include <linux/etherdevice.h>
++#include <linux/skbuff.h>
++#include <linux/mii.h>
++#include <linux/delay.h>
++#include <linux/skbuff.h>
++#include <linux/prefetch.h>
++
++/* For MII specifc registers, titan_mdio.h should be included */
++#include <net/ip.h>
++
++#include <asm/bitops.h>
++#include <asm/io.h>
++#include <asm/types.h>
++#include <asm/pgtable.h>
++#include <asm/system.h>
++#include <asm/titan_dep.h>
++
++#include "titan_ge.h"
++#include "titan_mdio.h"
++
++/* Static Function Declarations	 */
++static int titan_ge_eth_open(struct net_device *);
++static void titan_ge_eth_stop(struct net_device *);
++static struct net_device_stats *titan_ge_get_stats(struct net_device *);
++static int titan_ge_init_rx_desc_ring(titan_ge_port_info *, int, int,
++				      unsigned long, unsigned long,
++				      unsigned long);
++static int titan_ge_init_tx_desc_ring(titan_ge_port_info *, int,
++				      unsigned long, unsigned long);
++
++static int titan_ge_open(struct net_device *);
++static int titan_ge_start_xmit(struct sk_buff *, struct net_device *);
++static int titan_ge_stop(struct net_device *);
++
++static unsigned long titan_ge_tx_coal(unsigned long, int);
++
++static void titan_ge_port_reset(unsigned int);
++static int titan_ge_free_tx_queue(titan_ge_port_info *);
++static int titan_ge_rx_task(struct net_device *, titan_ge_port_info *);
++static int titan_ge_port_start(struct net_device *, titan_ge_port_info *);
++
++static int titan_ge_return_tx_desc(titan_ge_port_info *, int);
++
++/*
++ * Some configuration for the FIFO and the XDMA channel needs
++ * to be done only once for all the ports. This flag controls
++ * that
++ */
++static unsigned long config_done;
++
++/*
++ * One time out of memory flag
++ */
++static unsigned int oom_flag;
++
++static int titan_ge_poll(struct net_device *netdev, int *budget);
++
++static int titan_ge_receive_queue(struct net_device *, unsigned int);
++
++static struct platform_device *titan_ge_device[3];
++
++/* MAC Address */
++extern unsigned char titan_ge_mac_addr_base[6];
++
++unsigned long titan_ge_base;
++static unsigned long titan_ge_sram;
++
++static char titan_string[] = "titan";
++
++/*
++ * The Titan GE has two alignment requirements:
++ * -> skb->data to be cacheline aligned (32 byte)
++ * -> IP header alignment to 16 bytes
++ *
++ * The latter is not implemented. So, that results in an extra copy on
++ * the Rx. This is a big performance hog. For the former case, the
++ * dev_alloc_skb() has been replaced with titan_ge_alloc_skb(). The size
++ * requested is calculated:
++ *
++ * Ethernet Frame Size : 1518
++ * Ethernet Header     : 14
++ * Future Titan change for IP header alignment : 2
++ *
++ * Hence, we allocate (1518 + 14 + 2+ 64) = 1580 bytes.  For IP header
++ * alignment, we use skb_reserve().
++ */
++
++#define ALIGNED_RX_SKB_ADDR(addr) \
++	((((unsigned long)(addr) + (64UL - 1UL)) \
++	& ~(64UL - 1UL)) - (unsigned long)(addr))
++
++#define titan_ge_alloc_skb(__length, __gfp_flags) \
++({      struct sk_buff *__skb; \
++	__skb = alloc_skb((__length) + 64, (__gfp_flags)); \
++	if(__skb) { \
++		int __offset = (int) ALIGNED_RX_SKB_ADDR(__skb->data); \
++		if(__offset) \
++			skb_reserve(__skb, __offset); \
++	} \
++	__skb; \
++})
++
++/*
++ * Configure the GMII block of the Titan based on what the PHY tells us
++ */
++static void titan_ge_gmii_config(int port_num)
++{
++	unsigned int reg_data = 0, phy_reg;
++	int err;
++
++	err = titan_ge_mdio_read(port_num, TITAN_GE_MDIO_PHY_STATUS, &phy_reg);
++
++	if (err == TITAN_GE_MDIO_ERROR) {
++		printk(KERN_ERR
++		       "Could not read PHY control register 0x11 \n");
++		printk(KERN_ERR
++			"Setting speed to 1000 Mbps and Duplex to Full \n");
++
++		return;
++	}
++
++	err = titan_ge_mdio_write(port_num, TITAN_GE_MDIO_PHY_IE, 0);
++
++	if (phy_reg & 0x8000) {
++		if (phy_reg & 0x2000) {
++			/* Full Duplex and 1000 Mbps */
++			TITAN_GE_WRITE((TITAN_GE_GMII_CONFIG_MODE +
++					(port_num << 12)), 0x201);
++		}  else {
++			/* Half Duplex and 1000 Mbps */
++			TITAN_GE_WRITE((TITAN_GE_GMII_CONFIG_MODE +
++					(port_num << 12)), 0x2201);
++			}
++	}
++	if (phy_reg & 0x4000) {
++		if (phy_reg & 0x2000) {
++			/* Full Duplex and 100 Mbps */
++			TITAN_GE_WRITE((TITAN_GE_GMII_CONFIG_MODE +
++					(port_num << 12)), 0x100);
++		} else {
++			/* Half Duplex and 100 Mbps */
++			TITAN_GE_WRITE((TITAN_GE_GMII_CONFIG_MODE +
++					(port_num << 12)), 0x2100);
++		}
++	}
++	reg_data = TITAN_GE_READ(TITAN_GE_GMII_CONFIG_GENERAL +
++				(port_num << 12));
++	reg_data |= 0x3;
++	TITAN_GE_WRITE((TITAN_GE_GMII_CONFIG_GENERAL +
++			(port_num << 12)), reg_data);
++}
++
++/*
++ * Enable the TMAC if it is not
++ */
++static void titan_ge_enable_tx(unsigned int port_num)
++{
++	unsigned long reg_data;
++
++	reg_data = TITAN_GE_READ(TITAN_GE_TMAC_CONFIG_1 + (port_num << 12));
++	if (!(reg_data & 0x8000)) {
++		printk("TMAC disabled for port %d!! \n", port_num);
++
++		reg_data |= 0x0001;	/* Enable TMAC */
++		reg_data |= 0x4000;	/* CRC Check Enable */
++		reg_data |= 0x2000;	/* Padding enable */
++		reg_data |= 0x0800;	/* CRC Add enable */
++		reg_data |= 0x0080;	/* PAUSE frame */
++
++		TITAN_GE_WRITE((TITAN_GE_TMAC_CONFIG_1 +
++				(port_num << 12)), reg_data);
++	}
++}
++
++/*
++ * Tx Timeout function
++ */
++static void titan_ge_tx_timeout(struct net_device *netdev)
++{
++	titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
++
++	printk(KERN_INFO "%s: TX timeout  ", netdev->name);
++	printk(KERN_INFO "Resetting card \n");
++
++	/* Do the reset outside of interrupt context */
++	schedule_work(&titan_ge_eth->tx_timeout_task);
++}
++
++/*
++ * Update the AFX tables for UC and MC for slice 0 only
++ */
++static void titan_ge_update_afx(titan_ge_port_info * titan_ge_eth)
++{
++	int port = titan_ge_eth->port_num;
++	unsigned int i;
++	volatile unsigned long reg_data = 0;
++	u8 p_addr[6];
++
++	memcpy(p_addr, titan_ge_eth->port_mac_addr, 6);
++
++	/* Set the MAC address here for TMAC and RMAC */
++	TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_HI + (port << 12)),
++		       ((p_addr[5] << 8) | p_addr[4]));
++	TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_MID + (port << 12)),
++		       ((p_addr[3] << 8) | p_addr[2]));
++	TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_LOW + (port << 12)),
++		       ((p_addr[1] << 8) | p_addr[0]));
++
++	TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_HI + (port << 12)),
++		       ((p_addr[5] << 8) | p_addr[4]));
++	TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_MID + (port << 12)),
++		       ((p_addr[3] << 8) | p_addr[2]));
++	TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_LOW + (port << 12)),
++		       ((p_addr[1] << 8) | p_addr[0]));
++
++	TITAN_GE_WRITE((0x112c | (port << 12)), 0x1);
++	/* Configure the eight address filters */
++	for (i = 0; i < 8; i++) {
++		/* Select each of the eight filters */
++		TITAN_GE_WRITE((TITAN_GE_AFX_ADDRS_FILTER_CTRL_2 +
++				(port << 12)), i);
++
++		/* Configure the match */
++		reg_data = 0x9;	/* Forward Enable Bit */
++		TITAN_GE_WRITE((TITAN_GE_AFX_ADDRS_FILTER_CTRL_0 +
++				(port << 12)), reg_data);
++
++		/* Finally, AFX Exact Match Address Registers */
++		TITAN_GE_WRITE((TITAN_GE_AFX_EXACT_MATCH_LOW + (port << 12)),
++			       ((p_addr[1] << 8) | p_addr[0]));
++		TITAN_GE_WRITE((TITAN_GE_AFX_EXACT_MATCH_MID + (port << 12)),
++			       ((p_addr[3] << 8) | p_addr[2]));
++		TITAN_GE_WRITE((TITAN_GE_AFX_EXACT_MATCH_HIGH + (port << 12)),
++			       ((p_addr[5] << 8) | p_addr[4]));
++
++		/* VLAN id set to 0 */
++		TITAN_GE_WRITE((TITAN_GE_AFX_EXACT_MATCH_VID +
++				(port << 12)), 0);
++	}
++}
++
++/*
++ * Actual Routine to reset the adapter when the timeout occurred
++ */
++static void titan_ge_tx_timeout_task(struct net_device *netdev)
++{
++	titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
++	int port = titan_ge_eth->port_num;
++
++	printk("Titan GE: Transmit timed out. Resetting ... \n");
++
++	/* Dump debug info */
++	printk(KERN_ERR "TRTG cause : %x \n",
++			TITAN_GE_READ(0x100c + (port << 12)));
++
++	/* Fix this for the other ports */
++	printk(KERN_ERR "FIFO cause : %x \n", TITAN_GE_READ(0x482c));
++	printk(KERN_ERR "IE cause : %x \n", TITAN_GE_READ(0x0040));
++	printk(KERN_ERR "XDMA GDI ERROR : %x \n",
++			TITAN_GE_READ(0x5008 + (port << 8)));
++	printk(KERN_ERR "CHANNEL ERROR: %x \n",
++			TITAN_GE_READ(TITAN_GE_CHANNEL0_INTERRUPT
++						+ (port << 8)));
++
++	netif_device_detach(netdev);
++	titan_ge_port_reset(titan_ge_eth->port_num);
++	titan_ge_port_start(netdev, titan_ge_eth);
++	netif_device_attach(netdev);
++}
++
++/*
++ * Change the MTU of the Ethernet Device
++ */
++static int titan_ge_change_mtu(struct net_device *netdev, int new_mtu)
++{
++	titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
++	unsigned long flags;
++
++	if ((new_mtu > 9500) || (new_mtu < 64))
++		return -EINVAL;
++
++	spin_lock_irqsave(&titan_ge_eth->lock, flags);
++
++	netdev->mtu = new_mtu;
++
++	/* Now we have to reopen the interface so that SKBs with the new
++	 * size will be allocated */
++
++	if (netif_running(netdev)) {
++		titan_ge_eth_stop(netdev);
++
++		if (titan_ge_eth_open(netdev) != TITAN_OK) {
++			printk(KERN_ERR
++			       "%s: Fatal error on opening device\n",
++			       netdev->name);
++			spin_unlock_irqrestore(&titan_ge_eth->lock, flags);
++			return -1;
++		}
++	}
++
++	spin_unlock_irqrestore(&titan_ge_eth->lock, flags);
++	return 0;
++}
++
++/*
++ * Titan Gbe Interrupt Handler. All the three ports send interrupt to one line
++ * only. Once an interrupt is triggered, figure out the port and then check
++ * the channel.
++ */
++static irqreturn_t titan_ge_int_handler(int irq, void *dev_id,
++	struct pt_regs *regs)
++{
++	struct net_device *netdev = (struct net_device *) dev_id;
++	titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
++	unsigned int port_num = titan_ge_eth->port_num;
++	unsigned int reg_data;
++	unsigned int eth_int_cause_error = 0, is;
++	unsigned long eth_int_cause1;
++	int err = 0;
++#ifdef CONFIG_SMP
++	unsigned long eth_int_cause2;
++#endif
++
++	/* Ack the CPU interrupt */
++	switch (port_num) {
++	case 0:
++		is = OCD_READ(RM9000x2_OCD_INTP0STATUS1);
++		OCD_WRITE(RM9000x2_OCD_INTP0CLEAR1, is);
++
++#ifdef CONFIG_SMP
++		is = OCD_READ(RM9000x2_OCD_INTP1STATUS1);
++		OCD_WRITE(RM9000x2_OCD_INTP1CLEAR1, is);
++#endif
++		break;
++
++	case 1:
++		is = OCD_READ(RM9000x2_OCD_INTP0STATUS0);
++		OCD_WRITE(RM9000x2_OCD_INTP0CLEAR0, is);
++
++#ifdef CONFIG_SMP
++		is = OCD_READ(RM9000x2_OCD_INTP1STATUS0);
++		OCD_WRITE(RM9000x2_OCD_INTP1CLEAR0, is);
++#endif
++		break;
++
++	case 2:
++		is = OCD_READ(RM9000x2_OCD_INTP0STATUS4);
++		OCD_WRITE(RM9000x2_OCD_INTP0CLEAR4, is);
++
++#ifdef CONFIG_SMP
++		is = OCD_READ(RM9000x2_OCD_INTP1STATUS4);
++		OCD_WRITE(RM9000x2_OCD_INTP1CLEAR4, is);
++#endif
++	}
++
++	eth_int_cause1 = TITAN_GE_READ(TITAN_GE_INTR_XDMA_CORE_A);
++#ifdef CONFIG_SMP
++	eth_int_cause2 = TITAN_GE_READ(TITAN_GE_INTR_XDMA_CORE_B);
++#endif
++
++	/* Spurious interrupt */
++#ifdef CONFIG_SMP
++	if ( (eth_int_cause1 == 0) && (eth_int_cause2 == 0)) {
++#else
++	if (eth_int_cause1 == 0) {
++#endif
++		eth_int_cause_error = TITAN_GE_READ(TITAN_GE_CHANNEL0_INTERRUPT +
++					(port_num << 8));
++
++		if (eth_int_cause_error == 0)
++			return IRQ_NONE;
++	}
++
++	/* Handle Tx first. No need to ack interrupts */
++#ifdef CONFIG_SMP
++	if ( (eth_int_cause1 & 0x20202) ||
++		(eth_int_cause2 & 0x20202) )
++#else
++	if (eth_int_cause1 & 0x20202)
++#endif
++		titan_ge_free_tx_queue(titan_ge_eth);
++
++	/* Handle the Rx next */
++#ifdef CONFIG_SMP
++	if ( (eth_int_cause1 & 0x10101) ||
++		(eth_int_cause2 & 0x10101)) {
++#else
++	if (eth_int_cause1 & 0x10101) {
++#endif
++		if (netif_rx_schedule_prep(netdev)) {
++			unsigned int ack;
++
++			ack = TITAN_GE_READ(TITAN_GE_INTR_XDMA_IE);
++			/* Disable Tx and Rx both */
++			if (port_num == 0)
++				ack &= ~(0x3);
++			if (port_num == 1)
++				ack &= ~(0x300);
++
++			if (port_num == 2)
++				ack &= ~(0x30000);
++
++			/* Interrupts have been disabled */
++			TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_IE, ack);
++
++			__netif_rx_schedule(netdev);
++		}
++	}
++
++	/* Handle error interrupts */
++	if (eth_int_cause_error && (eth_int_cause_error != 0x2)) {
++		printk(KERN_ERR
++			"XDMA Channel Error : %x  on port %d\n",
++			eth_int_cause_error, port_num);
++
++		printk(KERN_ERR
++			"XDMA GDI Hardware error : %x  on port %d\n",
++			TITAN_GE_READ(0x5008 + (port_num << 8)), port_num);
++
++		printk(KERN_ERR
++			"XDMA currently has %d Rx descriptors \n",
++			TITAN_GE_READ(0x5048 + (port_num << 8)));
++
++		printk(KERN_ERR
++			"XDMA currently has prefetcted %d Rx descriptors \n",
++			TITAN_GE_READ(0x505c + (port_num << 8)));
++
++		TITAN_GE_WRITE((TITAN_GE_CHANNEL0_INTERRUPT +
++			       (port_num << 8)), eth_int_cause_error);
++	}
++
++	/*
++	 * PHY interrupt to inform abt the changes. Reading the
++	 * PHY Status register will clear the interrupt
++	 */
++	if ((!(eth_int_cause1 & 0x30303)) &&
++		(eth_int_cause_error == 0)) {
++		err =
++		    titan_ge_mdio_read(port_num,
++			       TITAN_GE_MDIO_PHY_IS, &reg_data);
++
++		if (reg_data & 0x0400) {
++			/* Link status change */
++			titan_ge_mdio_read(port_num,
++				   TITAN_GE_MDIO_PHY_STATUS, &reg_data);
++			if (!(reg_data & 0x0400)) {
++				/* Link is down */
++				netif_carrier_off(netdev);
++				netif_stop_queue(netdev);
++			} else {
++				/* Link is up */
++				netif_carrier_on(netdev);
++				netif_wake_queue(netdev);
++
++				/* Enable the queue */
++				titan_ge_enable_tx(port_num);
++			}
++		}
++	}
++
++	return IRQ_HANDLED;
++}
++
++/*
++ * Multicast and Promiscuous mode set. The
++ * set_multi entry point is called whenever the
++ * multicast address list or the network interface
++ * flags are updated.
++ */
++static void titan_ge_set_multi(struct net_device *netdev)
++{
++	titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
++	unsigned int port_num = titan_ge_eth->port_num;
++	unsigned long reg_data;
++
++	reg_data = TITAN_GE_READ(TITAN_GE_AFX_ADDRS_FILTER_CTRL_1 +
++				(port_num << 12));
++
++	if (netdev->flags & IFF_PROMISC) {
++		reg_data |= 0x2;
++	}
++	else if (netdev->flags & IFF_ALLMULTI) {
++		reg_data |= 0x01;
++		reg_data |= 0x400; /* Use the 64-bit Multicast Hash bin */
++	}
++	else {
++		reg_data = 0x2;
++	}
++
++	TITAN_GE_WRITE((TITAN_GE_AFX_ADDRS_FILTER_CTRL_1 +
++			(port_num << 12)), reg_data);
++	if (reg_data & 0x01) {
++		TITAN_GE_WRITE((TITAN_GE_AFX_MULTICAST_HASH_LOW +
++				(port_num << 12)), 0xffff);
++		TITAN_GE_WRITE((TITAN_GE_AFX_MULTICAST_HASH_MIDLOW +
++				(port_num << 12)), 0xffff);
++		TITAN_GE_WRITE((TITAN_GE_AFX_MULTICAST_HASH_MIDHI +
++				(port_num << 12)), 0xffff);
++		TITAN_GE_WRITE((TITAN_GE_AFX_MULTICAST_HASH_HI +
++				(port_num << 12)), 0xffff);
++	}
++}
++
++/*
++ * Open the network device
++ */
++static int titan_ge_open(struct net_device *netdev)
++{
++	titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
++	unsigned int port_num = titan_ge_eth->port_num;
++	unsigned int irq = TITAN_ETH_PORT_IRQ - port_num;
++	int retval;
++
++	retval = request_irq(irq, titan_ge_int_handler,
++		     SA_INTERRUPT | SA_SAMPLE_RANDOM , netdev->name, netdev);
++
++	if (retval != 0) {
++		printk(KERN_ERR "Cannot assign IRQ number to TITAN GE \n");
++		return -1;
++	}
++
++	netdev->irq = irq;
++	printk(KERN_INFO "Assigned IRQ %d to port %d\n", irq, port_num);
++
++	spin_lock_irq(&(titan_ge_eth->lock));
++
++	if (titan_ge_eth_open(netdev) != TITAN_OK) {
++		spin_unlock_irq(&(titan_ge_eth->lock));
++		printk("%s: Error opening interface \n", netdev->name);
++		free_irq(netdev->irq, netdev);
++		return -EBUSY;
++	}
++
++	spin_unlock_irq(&(titan_ge_eth->lock));
++
++	return 0;
++}
++
++/*
++ * Allocate the SKBs for the Rx ring. Also used
++ * for refilling the queue
++ */
++static int titan_ge_rx_task(struct net_device *netdev,
++				titan_ge_port_info *titan_ge_port)
++{
++	struct device *device = &titan_ge_device[titan_ge_port->port_num]->dev;
++	volatile titan_ge_rx_desc *rx_desc;
++	struct sk_buff *skb;
++	int rx_used_desc;
++	int count = 0;
++
++	while (titan_ge_port->rx_ring_skbs < titan_ge_port->rx_ring_size) {
++
++	/* First try to get the skb from the recycler */
++#ifdef TITAN_GE_JUMBO_FRAMES
++		skb = titan_ge_alloc_skb(TITAN_GE_JUMBO_BUFSIZE, GFP_ATOMIC);
++#else
++		skb = titan_ge_alloc_skb(TITAN_GE_STD_BUFSIZE, GFP_ATOMIC);
++#endif
++		if (unlikely(!skb)) {
++			/* OOM, set the flag */
++			printk("OOM \n");
++			oom_flag = 1;
++			break;
++		}
++		count++;
++		skb->dev = netdev;
++
++		titan_ge_port->rx_ring_skbs++;
++
++		rx_used_desc = titan_ge_port->rx_used_desc_q;
++		rx_desc = &(titan_ge_port->rx_desc_area[rx_used_desc]);
++
++#ifdef TITAN_GE_JUMBO_FRAMES
++		rx_desc->buffer_addr = dma_map_single(device, skb->data,
++				TITAN_GE_JUMBO_BUFSIZE - 2, DMA_FROM_DEVICE);
++#else
++		rx_desc->buffer_addr = dma_map_single(device, skb->data,
++				TITAN_GE_STD_BUFSIZE - 2, DMA_FROM_DEVICE);
++#endif
++
++		titan_ge_port->rx_skb[rx_used_desc] = skb;
++		rx_desc->cmd_sts = TITAN_GE_RX_BUFFER_OWNED;
++
++		titan_ge_port->rx_used_desc_q =
++			(rx_used_desc + 1) % TITAN_GE_RX_QUEUE;
++	}
++
++	return count;
++}
++
++/*
++ * Actual init of the Tital GE port. There is one register for
++ * the channel configuration
++ */
++static void titan_port_init(struct net_device *netdev,
++			    titan_ge_port_info * titan_ge_eth)
++{
++	unsigned long reg_data;
++
++	titan_ge_port_reset(titan_ge_eth->port_num);
++
++	/* First reset the TMAC */
++	reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG);
++	reg_data |= 0x80000000;
++	TITAN_GE_WRITE(TITAN_GE_CHANNEL0_CONFIG, reg_data);
++
++	udelay(30);
++
++	reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG);
++	reg_data &= ~(0xc0000000);
++	TITAN_GE_WRITE(TITAN_GE_CHANNEL0_CONFIG, reg_data);
++
++	/* Now reset the RMAC */
++	reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG);
++	reg_data |= 0x00080000;
++	TITAN_GE_WRITE(TITAN_GE_CHANNEL0_CONFIG, reg_data);
++
++	udelay(30);
++
++	reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG);
++	reg_data &= ~(0x000c0000);
++	TITAN_GE_WRITE(TITAN_GE_CHANNEL0_CONFIG, reg_data);
++}
++
++/*
++ * Start the port. All the hardware specific configuration
++ * for the XDMA, Tx FIFO, Rx FIFO, TMAC, RMAC, TRTG and AFX
++ * go here
++ */
++static int titan_ge_port_start(struct net_device *netdev,
++				titan_ge_port_info * titan_port)
++{
++	volatile unsigned long reg_data, reg_data1;
++	int port_num = titan_port->port_num;
++	int count = 0;
++	unsigned long reg_data_1;
++
++	if (config_done == 0) {
++		reg_data = TITAN_GE_READ(0x0004);
++		reg_data |= 0x100;
++		TITAN_GE_WRITE(0x0004, reg_data);
++
++		reg_data &= ~(0x100);
++		TITAN_GE_WRITE(0x0004, reg_data);
++
++		/* Turn on GMII/MII mode and turn off TBI mode */
++		reg_data = TITAN_GE_READ(TITAN_GE_TSB_CTRL_1);
++		reg_data |= 0x00000700;
++		reg_data &= ~(0x00800000); /* Fencing */
++
++		TITAN_GE_WRITE(0x000c, 0x00001100);
++
++		TITAN_GE_WRITE(TITAN_GE_TSB_CTRL_1, reg_data);
++
++		/* Set the CPU Resource Limit register */
++		TITAN_GE_WRITE(0x00f8, 0x8);
++
++		/* Be conservative when using the BIU buffers */
++		TITAN_GE_WRITE(0x0068, 0x4);
++	}
++
++	titan_port->tx_threshold = 0;
++	titan_port->rx_threshold = 0;
++
++	/* We need to write the descriptors for Tx and Rx */
++	TITAN_GE_WRITE((TITAN_GE_CHANNEL0_TX_DESC + (port_num << 8)),
++		       (unsigned long) titan_port->tx_dma);
++	TITAN_GE_WRITE((TITAN_GE_CHANNEL0_RX_DESC + (port_num << 8)),
++		       (unsigned long) titan_port->rx_dma);
++
++	if (config_done == 0) {
++		/* Step 1:  XDMA config	*/
++		reg_data = TITAN_GE_READ(TITAN_GE_XDMA_CONFIG);
++		reg_data &= ~(0x80000000);      /* clear reset */
++		reg_data |= 0x1 << 29;	/* sparse tx descriptor spacing */
++		reg_data |= 0x1 << 28;	/* sparse rx descriptor spacing */
++		reg_data |= (0x1 << 23) | (0x1 << 24);  /* Descriptor Coherency */
++		reg_data |= (0x1 << 21) | (0x1 << 22);  /* Data Coherency */
++		TITAN_GE_WRITE(TITAN_GE_XDMA_CONFIG, reg_data);
++	}
++
++	/* IR register for the XDMA */
++	reg_data = TITAN_GE_READ(TITAN_GE_GDI_INTERRUPT_ENABLE + (port_num << 8));
++	reg_data |= 0x80068000; /* No Rx_OOD */
++	TITAN_GE_WRITE((TITAN_GE_GDI_INTERRUPT_ENABLE + (port_num << 8)), reg_data);
++
++	/* Start the Tx and Rx XDMA controller */
++	reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG + (port_num << 8));
++	reg_data &= 0x4fffffff;     /* Clear tx reset */
++	reg_data &= 0xfff4ffff;     /* Clear rx reset */
++
++#ifdef TITAN_GE_JUMBO_FRAMES
++	reg_data |= 0xa0 | 0x30030000;
++#else
++	reg_data |= 0x40 | 0x20030000;
++#endif
++
++#ifndef CONFIG_SMP
++	reg_data &= ~(0x10);
++	reg_data |= 0x0f; /* All of the packet */
++#endif
++
++	TITAN_GE_WRITE((TITAN_GE_CHANNEL0_CONFIG + (port_num << 8)), reg_data);
++
++	/* Rx desc count */
++	count = titan_ge_rx_task(netdev, titan_port);
++	TITAN_GE_WRITE((0x5048 + (port_num << 8)), count);
++	count = TITAN_GE_READ(0x5048 + (port_num << 8));
++
++	udelay(30);
++
++	/*
++	 * Step 2:  Configure the SDQPF, i.e. FIFO
++	 */
++	if (config_done == 0) {
++		reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_RXFIFO_CTL);
++		reg_data = 0x1;
++		TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_CTL, reg_data);
++		reg_data &= ~(0x1);
++		TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_CTL, reg_data);
++		reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_RXFIFO_CTL);
++		TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_CTL, reg_data);
++
++		reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_TXFIFO_CTL);
++		reg_data = 0x1;
++		TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_CTL, reg_data);
++		reg_data &= ~(0x1);
++		TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_CTL, reg_data);
++		reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_TXFIFO_CTL);
++		TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_CTL, reg_data);
++	}
++	/*
++	 * Enable RX FIFO 0, 4 and 8
++	 */
++	if (port_num == 0) {
++		reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_RXFIFO_0);
++
++		reg_data |= 0x100000;
++		reg_data |= (0xff << 10);
++
++		TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_0, reg_data);
++		/*
++		 * BAV2,BAV and DAV settings for the Rx FIFO
++		 */
++		reg_data1 = TITAN_GE_READ(0x4844);
++		reg_data1 |= ( (0x10 << 20) | (0x10 << 10) | 0x1);
++		TITAN_GE_WRITE(0x4844, reg_data1);
++
++		reg_data &= ~(0x00100000);
++		reg_data |= 0x200000;
++
++		TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_0, reg_data);
++
++		reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_TXFIFO_0);
++		reg_data |= 0x100000;
++
++		TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_0, reg_data);
++
++		reg_data |= (0xff << 10);
++
++		TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_0, reg_data);
++
++		/*
++		 * BAV2, BAV and DAV settings for the Tx FIFO
++		 */
++		reg_data1 = TITAN_GE_READ(0x4944);
++		reg_data1 = ( (0x1 << 20) | (0x1 << 10) | 0x10);
++
++		TITAN_GE_WRITE(0x4944, reg_data1);
++
++		reg_data &= ~(0x00100000);
++		reg_data |= 0x200000;
++
++		TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_0, reg_data);
++
++	}
++
++	if (port_num == 1) {
++		reg_data = TITAN_GE_READ(0x4870);
++
++		reg_data |= 0x100000;
++		reg_data |= (0xff << 10) | (0xff + 1);
++
++		TITAN_GE_WRITE(0x4870, reg_data);
++		/*
++		 * BAV2,BAV and DAV settings for the Rx FIFO
++		 */
++		reg_data1 = TITAN_GE_READ(0x4874);
++		reg_data1 |= ( (0x10 << 20) | (0x10 << 10) | 0x1);
++		TITAN_GE_WRITE(0x4874, reg_data1);
++
++		reg_data &= ~(0x00100000);
++		reg_data |= 0x200000;
++
++		TITAN_GE_WRITE(0x4870, reg_data);
++
++		reg_data = TITAN_GE_READ(0x494c);
++		reg_data |= 0x100000;
++
++		TITAN_GE_WRITE(0x494c, reg_data);
++		reg_data |= (0xff << 10) | (0xff + 1);
++		TITAN_GE_WRITE(0x494c, reg_data);
++
++		/*
++		 * BAV2, BAV and DAV settings for the Tx FIFO
++		 */
++		reg_data1 = TITAN_GE_READ(0x4950);
++		reg_data1 = ( (0x1 << 20) | (0x1 << 10) | 0x10);
++
++		TITAN_GE_WRITE(0x4950, reg_data1);
++
++		reg_data &= ~(0x00100000);
++		reg_data |= 0x200000;
++
++		TITAN_GE_WRITE(0x494c, reg_data);
++	}
++
++	/*
++	 * Titan 1.2 revision does support port #2
++	 */
++	if (port_num == 2) {
++		/*
++		 * Put the descriptors in the SRAM
++		 */
++		reg_data = TITAN_GE_READ(0x48a0);
++
++		reg_data |= 0x100000;
++		reg_data |= (0xff << 10) | (2*(0xff + 1));
++
++		TITAN_GE_WRITE(0x48a0, reg_data);
++		/*
++		 * BAV2,BAV and DAV settings for the Rx FIFO
++		 */
++		reg_data1 = TITAN_GE_READ(0x48a4);
++		reg_data1 |= ( (0x10 << 20) | (0x10 << 10) | 0x1);
++		TITAN_GE_WRITE(0x48a4, reg_data1);
++
++		reg_data &= ~(0x00100000);
++		reg_data |= 0x200000;
++
++		TITAN_GE_WRITE(0x48a0, reg_data);
++		
++		reg_data = TITAN_GE_READ(0x4958);
++		reg_data |= 0x100000;
++
++		TITAN_GE_WRITE(0x4958, reg_data);
++		reg_data |= (0xff << 10) | (2*(0xff + 1));
++		TITAN_GE_WRITE(0x4958, reg_data);
++
++		/*
++		 * BAV2, BAV and DAV settings for the Tx FIFO
++		 */
++		reg_data1 = TITAN_GE_READ(0x495c);
++		reg_data1 = ( (0x1 << 20) | (0x1 << 10) | 0x10);
++
++		TITAN_GE_WRITE(0x495c, reg_data1);
++
++		reg_data &= ~(0x00100000);
++		reg_data |= 0x200000;
++
++		TITAN_GE_WRITE(0x4958, reg_data);
++	}
++
++	if (port_num == 2) {
++		reg_data = TITAN_GE_READ(0x48a0);
++
++		reg_data |= 0x100000;
++		reg_data |= (0xff << 10) | (2*(0xff + 1));
++
++		TITAN_GE_WRITE(0x48a0, reg_data);
++		/*
++		 * BAV2,BAV and DAV settings for the Rx FIFO
++		 */
++		reg_data1 = TITAN_GE_READ(0x48a4);
++		reg_data1 |= ( (0x10 << 20) | (0x10 << 10) | 0x1);
++		TITAN_GE_WRITE(0x48a4, reg_data1);
++
++		reg_data &= ~(0x00100000);
++		reg_data |= 0x200000;
++
++		TITAN_GE_WRITE(0x48a0, reg_data);
++
++		reg_data = TITAN_GE_READ(0x4958);
++		reg_data |= 0x100000;
++
++		TITAN_GE_WRITE(0x4958, reg_data);
++		reg_data |= (0xff << 10) | (2*(0xff + 1));
++		TITAN_GE_WRITE(0x4958, reg_data);
++
++		/*
++		 * BAV2, BAV and DAV settings for the Tx FIFO
++		 */
++		reg_data1 = TITAN_GE_READ(0x495c);
++		reg_data1 = ( (0x1 << 20) | (0x1 << 10) | 0x10);
++
++		TITAN_GE_WRITE(0x495c, reg_data1);
++
++		reg_data &= ~(0x00100000);
++		reg_data |= 0x200000;
++
++		TITAN_GE_WRITE(0x4958, reg_data);
++	}
++
++	/*
++	 * Step 3:  TRTG block enable
++	 */
++	reg_data = TITAN_GE_READ(TITAN_GE_TRTG_CONFIG + (port_num << 12));
++
++	/*
++	 * This is the 1.2 revision of the chip. It has fix for the
++	 * IP header alignment. Now, the IP header begins at an
++	 * aligned address and this wont need an extra copy in the
++	 * driver. This performance drawback existed in the previous
++	 * versions of the silicon
++	 */
++	reg_data_1 = TITAN_GE_READ(0x103c + (port_num << 12));
++	reg_data_1 |= 0x40000000;
++	TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1);
++
++	reg_data_1 |= 0x04000000;
++	TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1);
++
++	mdelay(5);
++
++	reg_data_1 &= ~(0x04000000);
++	TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1);
++
++	mdelay(5);
++
++	reg_data |= 0x0001;
++	TITAN_GE_WRITE((TITAN_GE_TRTG_CONFIG + (port_num << 12)), reg_data);
++
++	/*
++	 * Step 4:  Start the Tx activity
++	 */
++	TITAN_GE_WRITE((TITAN_GE_TMAC_CONFIG_2 + (port_num << 12)), 0xe197);
++#ifdef TITAN_GE_JUMBO_FRAMES
++	TITAN_GE_WRITE((0x1258 + (port_num << 12)), 0x4000);
++#endif
++	reg_data = TITAN_GE_READ(TITAN_GE_TMAC_CONFIG_1 + (port_num << 12));
++	reg_data |= 0x0001;	/* Enable TMAC */
++	reg_data |= 0x6c70;	/* PAUSE also set */
++
++	TITAN_GE_WRITE((TITAN_GE_TMAC_CONFIG_1 + (port_num << 12)), reg_data);
++
++	udelay(30);
++
++	/* Destination Address drop bit */
++	reg_data = TITAN_GE_READ(TITAN_GE_RMAC_CONFIG_2 + (port_num << 12));
++	reg_data |= 0x218;        /* DA_DROP bit and pause */
++	TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_2 + (port_num << 12)), reg_data);
++
++	TITAN_GE_WRITE((0x1218 + (port_num << 12)), 0x3);
++
++#ifdef TITAN_GE_JUMBO_FRAMES
++	TITAN_GE_WRITE((0x1208 + (port_num << 12)), 0x4000);
++#endif
++	/* Start the Rx activity */
++	reg_data = TITAN_GE_READ(TITAN_GE_RMAC_CONFIG_1 + (port_num << 12));
++	reg_data |= 0x0001;	/* RMAC Enable */
++	reg_data |= 0x0010;	/* CRC Check enable */
++	reg_data |= 0x0040;	/* Min Frame check enable */
++	reg_data |= 0x4400;	/* Max Frame check enable */
++
++	TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_1 + (port_num << 12)), reg_data);
++
++	udelay(30);
++
++	/*
++	 * Enable the Interrupts for Tx and Rx
++	 */
++	reg_data1 = TITAN_GE_READ(TITAN_GE_INTR_XDMA_IE);
++
++	if (port_num == 0) {
++		reg_data1 |= 0x3;
++#ifdef CONFIG_SMP
++		TITAN_GE_WRITE(0x0038, 0x003);
++#else
++		TITAN_GE_WRITE(0x0038, 0x303);
++#endif
++	}
++
++	if (port_num == 1) {
++		reg_data1 |= 0x300;
++	}
++
++	if (port_num == 2)
++		reg_data1 |= 0x30000;
++
++	TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_IE, reg_data1);
++	TITAN_GE_WRITE(0x003c, 0x300);
++
++	if (config_done == 0) {
++		TITAN_GE_WRITE(0x0024, 0x04000024);	/* IRQ vector */
++		TITAN_GE_WRITE(0x0020, 0x000fb000);	/* INTMSG base */
++	}
++
++	/* Priority */
++	reg_data = TITAN_GE_READ(0x1038 + (port_num << 12));
++	reg_data &= ~(0x00f00000);
++	TITAN_GE_WRITE((0x1038 + (port_num << 12)), reg_data);
++
++	/* Step 5:  GMII config */
++	titan_ge_gmii_config(port_num);
++
++	if (config_done == 0) {
++		TITAN_GE_WRITE(0x1a80, 0);
++		config_done = 1;
++	}
++
++	return TITAN_OK;
++}
++
++/*
++ * Function to queue the packet for the Ethernet device
++ */
++static void titan_ge_tx_queue(titan_ge_port_info * titan_ge_eth,
++				struct sk_buff * skb)
++{
++	struct device *device = &titan_ge_device[titan_ge_eth->port_num]->dev;
++	unsigned int curr_desc = titan_ge_eth->tx_curr_desc_q;
++	volatile titan_ge_tx_desc *tx_curr;
++	int port_num = titan_ge_eth->port_num;
++
++	tx_curr = &(titan_ge_eth->tx_desc_area[curr_desc]);
++	tx_curr->buffer_addr =
++		dma_map_single(device, skb->data, skb_headlen(skb),
++			       DMA_TO_DEVICE);
++
++	titan_ge_eth->tx_skb[curr_desc] = (struct sk_buff *) skb;
++	tx_curr->buffer_len = skb_headlen(skb);
++
++	/* Last descriptor enables interrupt and changes ownership */
++	tx_curr->cmd_sts = 0x1 | (1 << 15) | (1 << 5);
++
++	/* Kick the XDMA to start the transfer from memory to the FIFO */
++	TITAN_GE_WRITE((0x5044 + (port_num << 8)), 0x1);
++
++	/* Current descriptor updated */
++	titan_ge_eth->tx_curr_desc_q = (curr_desc + 1) % TITAN_GE_TX_QUEUE;
++
++	/* Prefetch the next descriptor */
++	prefetch((const void *)
++		 &titan_ge_eth->tx_desc_area[titan_ge_eth->tx_curr_desc_q]);
++}
++
++/*
++ * Actually does the open of the Ethernet device
++ */
++static int titan_ge_eth_open(struct net_device *netdev)
++{
++	titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
++	unsigned int port_num = titan_ge_eth->port_num;
++	struct device *device = &titan_ge_device[port_num]->dev;
++	unsigned long reg_data;
++	unsigned int phy_reg;
++	int err = 0;
++
++	/* Stop the Rx activity */
++	reg_data = TITAN_GE_READ(TITAN_GE_RMAC_CONFIG_1 + (port_num << 12));
++	reg_data &= ~(0x00000001);
++	TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_1 + (port_num << 12)), reg_data);
++
++	/* Clear the port interrupts */
++	TITAN_GE_WRITE((TITAN_GE_CHANNEL0_INTERRUPT + (port_num << 8)), 0x0);
++
++	if (config_done == 0) {
++		TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_CORE_A, 0);
++		TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_CORE_B, 0);
++	}
++
++	/* Set the MAC Address */
++	memcpy(titan_ge_eth->port_mac_addr, netdev->dev_addr, 6);
++
++	if (config_done == 0)
++		titan_port_init(netdev, titan_ge_eth);
++
++	titan_ge_update_afx(titan_ge_eth);
++
++	/* Allocate the Tx ring now */
++	titan_ge_eth->tx_ring_skbs = 0;
++	titan_ge_eth->tx_ring_size = TITAN_GE_TX_QUEUE;
++
++	/* Allocate space in the SRAM for the descriptors */
++	titan_ge_eth->tx_desc_area = (titan_ge_tx_desc *)
++		(titan_ge_sram + TITAN_TX_RING_BYTES * port_num);
++	titan_ge_eth->tx_dma = TITAN_SRAM_BASE + TITAN_TX_RING_BYTES * port_num;
++
++	if (!titan_ge_eth->tx_desc_area) {
++		printk(KERN_ERR
++		       "%s: Cannot allocate Tx Ring (size %d bytes) for port %d\n",
++		       netdev->name, TITAN_TX_RING_BYTES, port_num);
++		return -ENOMEM;
++	}
++
++	memset(titan_ge_eth->tx_desc_area, 0, titan_ge_eth->tx_desc_area_size);
++
++	/* Now initialize the Tx descriptor ring */
++	titan_ge_init_tx_desc_ring(titan_ge_eth,
++				   titan_ge_eth->tx_ring_size,
++				   (unsigned long) titan_ge_eth->tx_desc_area,
++				   (unsigned long) titan_ge_eth->tx_dma);
++
++	/* Allocate the Rx ring now */
++	titan_ge_eth->rx_ring_size = TITAN_GE_RX_QUEUE;
++	titan_ge_eth->rx_ring_skbs = 0;
++
++	titan_ge_eth->rx_desc_area =
++		(titan_ge_rx_desc *)(titan_ge_sram + 0x1000 + TITAN_RX_RING_BYTES * port_num);
++
++	titan_ge_eth->rx_dma = TITAN_SRAM_BASE + 0x1000 + TITAN_RX_RING_BYTES * port_num;
++
++	if (!titan_ge_eth->rx_desc_area) {
++		printk(KERN_ERR "%s: Cannot allocate Rx Ring (size %d bytes)\n",
++		       netdev->name, TITAN_RX_RING_BYTES);
++
++		printk(KERN_ERR "%s: Freeing previously allocated TX queues...",
++		       netdev->name);
++
++		dma_free_coherent(device, titan_ge_eth->tx_desc_area_size,
++				    (void *) titan_ge_eth->tx_desc_area,
++				    titan_ge_eth->tx_dma);
++
++		return -ENOMEM;
++	}
++
++	memset(titan_ge_eth->rx_desc_area, 0, titan_ge_eth->rx_desc_area_size);
++
++	/* Now initialize the Rx ring */
++#ifdef TITAN_GE_JUMBO_FRAMES
++	if ((titan_ge_init_rx_desc_ring
++	    (titan_ge_eth, titan_ge_eth->rx_ring_size, TITAN_GE_JUMBO_BUFSIZE,
++	     (unsigned long) titan_ge_eth->rx_desc_area, 0,
++	      (unsigned long) titan_ge_eth->rx_dma)) == 0)
++#else
++	if ((titan_ge_init_rx_desc_ring
++	     (titan_ge_eth, titan_ge_eth->rx_ring_size, TITAN_GE_STD_BUFSIZE,
++	      (unsigned long) titan_ge_eth->rx_desc_area, 0,
++	      (unsigned long) titan_ge_eth->rx_dma)) == 0)
++#endif
++		panic("%s: Error initializing RX Ring\n", netdev->name);
++
++	/* Fill the Rx ring with the SKBs */
++	titan_ge_port_start(netdev, titan_ge_eth);
++
++	/*
++	 * Check if Interrupt Coalscing needs to be turned on. The
++	 * values specified in the register is multiplied by
++	 * (8 x 64 nanoseconds) to determine when an interrupt should
++	 * be sent to the CPU.
++	 */
++
++	if (TITAN_GE_TX_COAL) {
++		titan_ge_eth->tx_int_coal =
++		    titan_ge_tx_coal(TITAN_GE_TX_COAL, port_num);
++	}
++
++	err = titan_ge_mdio_read(port_num, TITAN_GE_MDIO_PHY_STATUS, &phy_reg);
++	if (err == TITAN_GE_MDIO_ERROR) {
++		printk(KERN_ERR
++		       "Could not read PHY control register 0x11 \n");
++		return TITAN_ERROR;
++	}
++	if (!(phy_reg & 0x0400)) {
++		netif_carrier_off(netdev);
++		netif_stop_queue(netdev);
++		return TITAN_ERROR;
++	} else {
++		netif_carrier_on(netdev);
++		netif_start_queue(netdev);
++	}
++
++	return TITAN_OK;
++}
++
++/*
++ * Queue the packet for Tx. Currently no support for zero copy,
++ * checksum offload and Scatter Gather. The chip does support
++ * Scatter Gather only. But, that wont help here since zero copy
++ * requires support for Tx checksumming also.
++ */
++int titan_ge_start_xmit(struct sk_buff *skb, struct net_device *netdev)
++{
++	titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
++	unsigned long flags;
++	struct net_device_stats *stats;
++//printk("titan_ge_start_xmit\n");
++
++	stats = &titan_ge_eth->stats;
++	spin_lock_irqsave(&titan_ge_eth->lock, flags);
++
++	if ((TITAN_GE_TX_QUEUE - titan_ge_eth->tx_ring_skbs) <=
++	    (skb_shinfo(skb)->nr_frags + 1)) {
++		netif_stop_queue(netdev);
++		spin_unlock_irqrestore(&titan_ge_eth->lock, flags);
++		printk(KERN_ERR "Tx OOD \n");
++		return 1;
++	}
++
++	titan_ge_tx_queue(titan_ge_eth, skb);
++	titan_ge_eth->tx_ring_skbs++;
++
++	if (TITAN_GE_TX_QUEUE <= (titan_ge_eth->tx_ring_skbs + 4)) {
++		spin_unlock_irqrestore(&titan_ge_eth->lock, flags);
++		titan_ge_free_tx_queue(titan_ge_eth);
++		spin_lock_irqsave(&titan_ge_eth->lock, flags);
++	}
++
++	stats->tx_bytes += skb->len;
++	stats->tx_packets++;
++
++	spin_unlock_irqrestore(&titan_ge_eth->lock, flags);
++
++	netdev->trans_start = jiffies;
++
++	return 0;
++}
++
++/*
++ * Actually does the Rx. Rx side checksumming supported.
++ */
++static int titan_ge_rx(struct net_device *netdev, int port_num,
++			titan_ge_port_info * titan_ge_port,
++		       titan_ge_packet * packet)
++{
++	int rx_curr_desc, rx_used_desc;
++	volatile titan_ge_rx_desc *rx_desc;
++
++	rx_curr_desc = titan_ge_port->rx_curr_desc_q;
++	rx_used_desc = titan_ge_port->rx_used_desc_q;
++
++	if (((rx_curr_desc + 1) % TITAN_GE_RX_QUEUE) == rx_used_desc)
++		return TITAN_ERROR;
++
++	rx_desc = &(titan_ge_port->rx_desc_area[rx_curr_desc]);
++
++	if (rx_desc->cmd_sts & TITAN_GE_RX_BUFFER_OWNED)
++		return TITAN_ERROR;
++
++	packet->skb = titan_ge_port->rx_skb[rx_curr_desc];
++	packet->len = (rx_desc->cmd_sts & 0x7fff);
++
++	/*
++	 * At this point, we dont know if the checksumming
++	 * actually helps relieve CPU. So, keep it for
++	 * port 0 only
++	 */
++	packet->checksum = ntohs((rx_desc->buffer & 0xffff0000) >> 16);
++	packet->cmd_sts = rx_desc->cmd_sts;
++
++	titan_ge_port->rx_curr_desc_q = (rx_curr_desc + 1) % TITAN_GE_RX_QUEUE;
++
++	/* Prefetch the next descriptor */
++	prefetch((const void *)
++	       &titan_ge_port->rx_desc_area[titan_ge_port->rx_curr_desc_q + 1]);
++
++	return TITAN_OK;
++}
++
++/*
++ * Free the Tx queue of the used SKBs
++ */
++static int titan_ge_free_tx_queue(titan_ge_port_info *titan_ge_eth)
++{
++	unsigned long flags;
++
++	/* Take the lock */
++	spin_lock_irqsave(&(titan_ge_eth->lock), flags);
++
++	while (titan_ge_return_tx_desc(titan_ge_eth, titan_ge_eth->port_num) == 0)
++		if (titan_ge_eth->tx_ring_skbs != 1)
++			titan_ge_eth->tx_ring_skbs--;
++
++	spin_unlock_irqrestore(&titan_ge_eth->lock, flags);
++
++	return TITAN_OK;
++}
++
++/*
++ * Threshold beyond which we do the cleaning of
++ * Tx queue and new allocation for the Rx
++ * queue
++ */
++#define	TX_THRESHOLD	4
++#define	RX_THRESHOLD	10
++
++/*
++ * Receive the packets and send it to the kernel.
++ */
++static int titan_ge_receive_queue(struct net_device *netdev, unsigned int max)
++{
++	titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
++	unsigned int port_num = titan_ge_eth->port_num;
++	titan_ge_packet packet;
++	struct net_device_stats *stats;
++	struct sk_buff *skb;
++	unsigned long received_packets = 0;
++	unsigned int ack;
++
++	stats = &titan_ge_eth->stats;
++
++	while ((--max)
++	       && (titan_ge_rx(netdev, port_num, titan_ge_eth, &packet) == TITAN_OK)) {
++		skb = (struct sk_buff *) packet.skb;
++
++		titan_ge_eth->rx_ring_skbs--;
++
++		if (--titan_ge_eth->rx_work_limit < 0)
++			break;
++		received_packets++;
++
++		stats->rx_packets++;
++		stats->rx_bytes += packet.len;
++
++		if ((packet.cmd_sts & TITAN_GE_RX_PERR) ||
++			(packet.cmd_sts & TITAN_GE_RX_OVERFLOW_ERROR) ||
++			(packet.cmd_sts & TITAN_GE_RX_TRUNC) ||
++			(packet.cmd_sts & TITAN_GE_RX_CRC_ERROR)) {
++				stats->rx_dropped++;
++				dev_kfree_skb_any(skb);
++
++				continue;
++		}
++		/*
++		 * Either support fast path or slow path. Decision
++		 * making can really slow down the performance. The
++		 * idea is to cut down the number of checks and improve
++		 * the fastpath.
++		 */
++
++		skb_put(skb, packet.len - 2);
++
++		/*
++		 * Increment data pointer by two since thats where
++		 * the MAC starts
++		 */
++		skb_reserve(skb, 2);
++		skb->protocol = eth_type_trans(skb, netdev);
++		netif_receive_skb(skb);
++
++		if (titan_ge_eth->rx_threshold > RX_THRESHOLD) {
++			ack = titan_ge_rx_task(netdev, titan_ge_eth);
++			TITAN_GE_WRITE((0x5048 + (port_num << 8)), ack);
++			titan_ge_eth->rx_threshold = 0;
++		} else
++			titan_ge_eth->rx_threshold++;
++
++		if (titan_ge_eth->tx_threshold > TX_THRESHOLD) {
++			titan_ge_eth->tx_threshold = 0;
++			titan_ge_free_tx_queue(titan_ge_eth);
++		}
++		else
++			titan_ge_eth->tx_threshold++;
++
++	}
++	return received_packets;
++}
++
++
++/*
++ * Enable the Rx side interrupts
++ */
++static void titan_ge_enable_int(unsigned int port_num,
++			titan_ge_port_info *titan_ge_eth,
++			struct net_device *netdev)
++{
++	unsigned long reg_data = TITAN_GE_READ(TITAN_GE_INTR_XDMA_IE);
++
++	if (port_num == 0)
++		reg_data |= 0x3;
++	if (port_num == 1)
++		reg_data |= 0x300;
++	if (port_num == 2)
++		reg_data |= 0x30000;
++
++	/* Re-enable interrupts */
++	TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_IE, reg_data);
++}
++
++/*
++ * Main function to handle the polling for Rx side NAPI.
++ * Receive interrupts have been disabled at this point.
++ * The poll schedules the transmit followed by receive.
++ */
++static int titan_ge_poll(struct net_device *netdev, int *budget)
++{
++	titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
++	int port_num = titan_ge_eth->port_num;
++	int work_done = 0;
++	unsigned long flags, status;
++
++	titan_ge_eth->rx_work_limit = *budget;
++	if (titan_ge_eth->rx_work_limit > netdev->quota)
++		titan_ge_eth->rx_work_limit = netdev->quota;
++
++	do {
++		/* Do the transmit cleaning work here */
++		titan_ge_free_tx_queue(titan_ge_eth);
++
++		/* Ack the Rx interrupts */
++		if (port_num == 0)
++			TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_CORE_A, 0x3);
++		if (port_num == 1)
++			TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_CORE_A, 0x300);
++		if (port_num == 2)
++			TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_CORE_A, 0x30000);
++
++		work_done += titan_ge_receive_queue(netdev, 0);
++
++		/* Out of quota and there is work to be done */
++		if (titan_ge_eth->rx_work_limit < 0)
++			goto not_done;
++
++		/* Receive alloc_skb could lead to OOM */
++		if (oom_flag == 1) {
++			oom_flag = 0;
++			goto oom;
++		}
++
++		status = TITAN_GE_READ(TITAN_GE_INTR_XDMA_CORE_A);
++	} while (status & 0x30300);
++
++	/* If we are here, then no more interrupts to process */
++	goto done;
++
++not_done:
++	*budget -= work_done;
++	netdev->quota -= work_done;
++	return 1;
++
++oom:
++	printk(KERN_ERR "OOM \n");
++	netif_rx_complete(netdev);
++	return 0;
++
++done:
++	/*
++	 * No more packets on the poll list. Turn the interrupts
++	 * back on and we should be able to catch the new
++	 * packets in the interrupt handler
++	 */
++	if (!work_done)
++		work_done = 1;
++
++	*budget -= work_done;
++	netdev->quota -= work_done;
++
++	spin_lock_irqsave(&titan_ge_eth->lock, flags);
++
++	/* Remove us from the poll list */
++	netif_rx_complete(netdev);
++
++	/* Re-enable interrupts */
++	titan_ge_enable_int(port_num, titan_ge_eth, netdev);
++
++	spin_unlock_irqrestore(&titan_ge_eth->lock, flags);
++
++	return 0;
++}
++
++/*
++ * Close the network device
++ */
++int titan_ge_stop(struct net_device *netdev)
++{
++	titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
++
++	spin_lock_irq(&(titan_ge_eth->lock));
++	titan_ge_eth_stop(netdev);
++	free_irq(netdev->irq, netdev);
++	spin_unlock_irq(&titan_ge_eth->lock);
++
++	return TITAN_OK;
++}
++
++/*
++ * Free the Tx ring
++ */
++static void titan_ge_free_tx_rings(struct net_device *netdev)
++{
++	titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
++	unsigned int port_num = titan_ge_eth->port_num;
++	unsigned int curr;
++	unsigned long reg_data;
++
++	/* Stop the Tx DMA */
++	reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG +
++				(port_num << 8));
++	reg_data |= 0xc0000000;
++	TITAN_GE_WRITE((TITAN_GE_CHANNEL0_CONFIG +
++			(port_num << 8)), reg_data);
++
++	/* Disable the TMAC */
++	reg_data = TITAN_GE_READ(TITAN_GE_TMAC_CONFIG_1 +
++				(port_num << 12));
++	reg_data &= ~(0x00000001);
++	TITAN_GE_WRITE((TITAN_GE_TMAC_CONFIG_1 +
++			(port_num << 12)), reg_data);
++
++	for (curr = 0;
++	     (titan_ge_eth->tx_ring_skbs) && (curr < TITAN_GE_TX_QUEUE);
++	     curr++) {
++		if (titan_ge_eth->tx_skb[curr]) {
++			dev_kfree_skb(titan_ge_eth->tx_skb[curr]);
++			titan_ge_eth->tx_ring_skbs--;
++		}
++	}
++
++	if (titan_ge_eth->tx_ring_skbs != 0)
++		printk
++		    ("%s: Error on Tx descriptor free - could not free %d"
++		     " descriptors\n", netdev->name,
++		     titan_ge_eth->tx_ring_skbs);
++
++#ifndef TITAN_RX_RING_IN_SRAM
++	dma_free_coherent(&titan_ge_device[port_num]->dev,
++			  titan_ge_eth->tx_desc_area_size,
++			  (void *) titan_ge_eth->tx_desc_area,
++			  titan_ge_eth->tx_dma);
++#endif
++}
++
++/*
++ * Free the Rx ring
++ */
++static void titan_ge_free_rx_rings(struct net_device *netdev)
++{
++	titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
++	unsigned int port_num = titan_ge_eth->port_num;
++	unsigned int curr;
++	unsigned long reg_data;
++
++	/* Stop the Rx DMA */
++	reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG +
++				(port_num << 8));
++	reg_data |= 0x000c0000;
++	TITAN_GE_WRITE((TITAN_GE_CHANNEL0_CONFIG +
++			(port_num << 8)), reg_data);
++
++	/* Disable the RMAC */
++	reg_data = TITAN_GE_READ(TITAN_GE_RMAC_CONFIG_1 +
++				(port_num << 12));
++	reg_data &= ~(0x00000001);
++	TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_1 +
++			(port_num << 12)), reg_data);
++
++	for (curr = 0;
++	     titan_ge_eth->rx_ring_skbs && (curr < TITAN_GE_RX_QUEUE);
++	     curr++) {
++		if (titan_ge_eth->rx_skb[curr]) {
++			dev_kfree_skb(titan_ge_eth->rx_skb[curr]);
++			titan_ge_eth->rx_ring_skbs--;
++		}
++	}
++
++	if (titan_ge_eth->rx_ring_skbs != 0)
++		printk(KERN_ERR
++		       "%s: Error in freeing Rx Ring. %d skb's still"
++		       " stuck in RX Ring - ignoring them\n", netdev->name,
++		       titan_ge_eth->rx_ring_skbs);
++
++#ifndef TITAN_RX_RING_IN_SRAM
++	dma_free_coherent(&titan_ge_device[port_num]->dev,
++			  titan_ge_eth->rx_desc_area_size,
++			  (void *) titan_ge_eth->rx_desc_area,
++			  titan_ge_eth->rx_dma);
++#endif
++}
++
++/*
++ * Actually does the stop of the Ethernet device
++ */
++static void titan_ge_eth_stop(struct net_device *netdev)
++{
++	titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
++
++	netif_stop_queue(netdev);
++
++	titan_ge_port_reset(titan_ge_eth->port_num);
++
++	titan_ge_free_tx_rings(netdev);
++	titan_ge_free_rx_rings(netdev);
++
++	/* Disable the Tx and Rx Interrupts for all channels */
++	TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_IE, 0x0);
++}
++
++/*
++ * Update the MAC address. Note that we have to write the
++ * address in three station registers, 16 bits each. And this
++ * has to be done for TMAC and RMAC
++ */
++static void titan_ge_update_mac_address(struct net_device *netdev)
++{
++	titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
++	unsigned int port_num = titan_ge_eth->port_num;
++	u8 p_addr[6];
++
++	memcpy(titan_ge_eth->port_mac_addr, netdev->dev_addr, 6);
++	memcpy(p_addr, netdev->dev_addr, 6);
++
++	/* Update the Address Filtering Match tables */
++	titan_ge_update_afx(titan_ge_eth);
++
++	printk("Station MAC : %d %d %d %d %d %d  \n",
++		p_addr[5], p_addr[4], p_addr[3],
++		p_addr[2], p_addr[1], p_addr[0]);
++
++	/* Set the MAC address here for TMAC and RMAC */
++	TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_HI + (port_num << 12)),
++		       ((p_addr[5] << 8) | p_addr[4]));
++	TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_MID + (port_num << 12)),
++		       ((p_addr[3] << 8) | p_addr[2]));
++	TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_LOW + (port_num << 12)),
++		       ((p_addr[1] << 8) | p_addr[0]));
++
++	TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_HI + (port_num << 12)),
++		       ((p_addr[5] << 8) | p_addr[4]));
++	TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_MID + (port_num << 12)),
++		       ((p_addr[3] << 8) | p_addr[2]));
++	TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_LOW + (port_num << 12)),
++		       ((p_addr[1] << 8) | p_addr[0]));
++}
++
++/*
++ * Set the MAC address of the Ethernet device
++ */
++static int titan_ge_set_mac_address(struct net_device *dev, void *addr)
++{
++	titan_ge_port_info *tp = netdev_priv(dev);
++	struct sockaddr *sa = addr;
++
++	memcpy(dev->dev_addr, sa->sa_data, dev->addr_len);
++
++	spin_lock_irq(&tp->lock);
++	titan_ge_update_mac_address(dev);
++	spin_unlock_irq(&tp->lock);
++
++	return 0;
++}
++
++/*
++ * Get the Ethernet device stats
++ */
++static struct net_device_stats *titan_ge_get_stats(struct net_device *netdev)
++{
++	titan_ge_port_info *titan_ge_eth = netdev_priv(netdev);
++
++	return &titan_ge_eth->stats;
++}
++
++/*
++ * Initialize the Rx descriptor ring for the Titan Ge
++ */
++static int titan_ge_init_rx_desc_ring(titan_ge_port_info * titan_eth_port,
++				      int rx_desc_num,
++				      int rx_buff_size,
++				      unsigned long rx_desc_base_addr,
++				      unsigned long rx_buff_base_addr,
++				      unsigned long rx_dma)
++{
++	volatile titan_ge_rx_desc *rx_desc;
++	unsigned long buffer_addr;
++	int index;
++	unsigned long titan_ge_rx_desc_bus = rx_dma;
++
++	buffer_addr = rx_buff_base_addr;
++	rx_desc = (titan_ge_rx_desc *) rx_desc_base_addr;
++
++	/* Check alignment */
++	if (rx_buff_base_addr & 0xF)
++		return 0;
++
++	/* Check Rx buffer size */
++	if ((rx_buff_size < 8) || (rx_buff_size > TITAN_GE_MAX_RX_BUFFER))
++		return 0;
++
++	/* 64-bit alignment
++	if ((rx_buff_base_addr + rx_buff_size) & 0x7)
++		return 0; */
++
++	/* Initialize the Rx desc ring */
++	for (index = 0; index < rx_desc_num; index++) {
++		titan_ge_rx_desc_bus += sizeof(titan_ge_rx_desc);
++		rx_desc[index].cmd_sts = 0;
++		rx_desc[index].buffer_addr = buffer_addr;
++		titan_eth_port->rx_skb[index] = NULL;
++		buffer_addr += rx_buff_size;
++	}
++
++	titan_eth_port->rx_curr_desc_q = 0;
++	titan_eth_port->rx_used_desc_q = 0;
++
++	titan_eth_port->rx_desc_area = (titan_ge_rx_desc *) rx_desc_base_addr;
++	titan_eth_port->rx_desc_area_size =
++	    rx_desc_num * sizeof(titan_ge_rx_desc);
++
++	titan_eth_port->rx_dma = rx_dma;
++
++	return TITAN_OK;
++}
++
++/*
++ * Initialize the Tx descriptor ring. Descriptors in the SRAM
++ */
++static int titan_ge_init_tx_desc_ring(titan_ge_port_info * titan_ge_port,
++				      int tx_desc_num,
++				      unsigned long tx_desc_base_addr,
++				      unsigned long tx_dma)
++{
++	titan_ge_tx_desc *tx_desc;
++	int index;
++	unsigned long titan_ge_tx_desc_bus = tx_dma;
++
++	if (tx_desc_base_addr & 0xF)
++		return 0;
++
++	tx_desc = (titan_ge_tx_desc *) tx_desc_base_addr;
++
++	for (index = 0; index < tx_desc_num; index++) {
++		titan_ge_port->tx_dma_array[index] =
++		    (dma_addr_t) titan_ge_tx_desc_bus;
++		titan_ge_tx_desc_bus += sizeof(titan_ge_tx_desc);
++		tx_desc[index].cmd_sts = 0x0000;
++		tx_desc[index].buffer_len = 0;
++		tx_desc[index].buffer_addr = 0x00000000;
++		titan_ge_port->tx_skb[index] = NULL;
++	}
++
++	titan_ge_port->tx_curr_desc_q = 0;
++	titan_ge_port->tx_used_desc_q = 0;
++
++	titan_ge_port->tx_desc_area = (titan_ge_tx_desc *) tx_desc_base_addr;
++	titan_ge_port->tx_desc_area_size =
++	    tx_desc_num * sizeof(titan_ge_tx_desc);
++
++	titan_ge_port->tx_dma = tx_dma;
++	return TITAN_OK;
++}
++
++/*
++ * Initialize the device as an Ethernet device
++ */
++static int __init titan_ge_probe(struct device *device)
++{
++	titan_ge_port_info *titan_ge_eth;
++	struct net_device *netdev;
++	int port = to_platform_device(device)->id;
++	int err;
++
++	netdev = alloc_etherdev(sizeof(titan_ge_port_info));
++	if (!netdev) {
++		err = -ENODEV;
++		goto out;
++	}
++
++	netdev->open = titan_ge_open;
++	netdev->stop = titan_ge_stop;
++	netdev->hard_start_xmit = titan_ge_start_xmit;
++	netdev->get_stats = titan_ge_get_stats;
++	netdev->set_multicast_list = titan_ge_set_multi;
++	netdev->set_mac_address = titan_ge_set_mac_address;
++
++	/* Tx timeout */
++	netdev->tx_timeout = titan_ge_tx_timeout;
++	netdev->watchdog_timeo = 2 * HZ;
++
++	/* Set these to very high values */
++	netdev->poll = titan_ge_poll;
++	netdev->weight = 64;
++
++	netdev->tx_queue_len = TITAN_GE_TX_QUEUE;
++	netif_carrier_off(netdev);
++	netdev->base_addr = 0;
++
++	netdev->change_mtu = titan_ge_change_mtu;
++
++	titan_ge_eth = netdev_priv(netdev);
++	/* Allocation of memory for the driver structures */
++
++	titan_ge_eth->port_num = port;
++
++	/* Configure the Tx timeout handler */
++	INIT_WORK(&titan_ge_eth->tx_timeout_task,
++		  (void (*)(void *)) titan_ge_tx_timeout_task, netdev);
++
++	spin_lock_init(&titan_ge_eth->lock);
++
++	/* set MAC addresses */
++	memcpy(netdev->dev_addr, titan_ge_mac_addr_base, 6);
++	netdev->dev_addr[5] += port;
++
++	err = register_netdev(netdev);
++
++	if (err)
++		goto out_free_netdev;
++
++	printk(KERN_NOTICE
++	       "%s: port %d with MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
++	       netdev->name, port, netdev->dev_addr[0],
++	       netdev->dev_addr[1], netdev->dev_addr[2],
++	       netdev->dev_addr[3], netdev->dev_addr[4],
++	       netdev->dev_addr[5]);
++
++	printk(KERN_NOTICE "Rx NAPI supported, Tx Coalescing ON \n");
++
++	return 0;
++
++out_free_netdev:
++	kfree(netdev);
++
++out:
++	return err;
++}
++
++static void __devexit titan_device_remove(struct device *device)
++{
++}
++
++/*
++ * Reset the Ethernet port
++ */
++static void titan_ge_port_reset(unsigned int port_num)
++{
++	unsigned int reg_data;
++
++	/* Stop the Tx port activity */
++	reg_data = TITAN_GE_READ(TITAN_GE_TMAC_CONFIG_1 +
++				(port_num << 12));
++	reg_data &= ~(0x0001);
++	TITAN_GE_WRITE((TITAN_GE_TMAC_CONFIG_1 +
++			(port_num << 12)), reg_data);
++
++	/* Stop the Rx port activity */
++	reg_data = TITAN_GE_READ(TITAN_GE_RMAC_CONFIG_1 +
++				(port_num << 12));
++	reg_data &= ~(0x0001);
++	TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_1 +
++			(port_num << 12)), reg_data);
++
++	return;
++}
++
++/*
++ * Return the Tx desc after use by the XDMA
++ */
++static int titan_ge_return_tx_desc(titan_ge_port_info * titan_ge_eth, int port)
++{
++	int tx_desc_used;
++	struct sk_buff *skb;
++
++	tx_desc_used = titan_ge_eth->tx_used_desc_q;
++
++	/* return right away */
++	if (tx_desc_used == titan_ge_eth->tx_curr_desc_q)
++		return TITAN_ERROR;
++
++	/* Now the critical stuff */
++	skb = titan_ge_eth->tx_skb[tx_desc_used];
++
++	dev_kfree_skb_any(skb);
++
++	titan_ge_eth->tx_skb[tx_desc_used] = NULL;
++	titan_ge_eth->tx_used_desc_q =
++	    (tx_desc_used + 1) % TITAN_GE_TX_QUEUE;
++
++	return 0;
++}
++
++/*
++ * Coalescing for the Tx path
++ */
++static unsigned long titan_ge_tx_coal(unsigned long delay, int port)
++{
++	unsigned long rx_delay;
++
++	rx_delay = TITAN_GE_READ(TITAN_GE_INT_COALESCING);
++	delay = (delay << 16) | rx_delay;
++
++	TITAN_GE_WRITE(TITAN_GE_INT_COALESCING, delay);
++	TITAN_GE_WRITE(0x5038, delay);
++
++	return delay;
++}
++
++static struct device_driver titan_soc_driver = {
++	.name   = titan_string,
++	.bus    = &platform_bus_type,
++	.probe  = titan_ge_probe,
++	.remove = __devexit_p(titan_device_remove),
++};
++
++static void titan_platform_release (struct device *device)
++{
++	struct platform_device *pldev;
++
++	/* free device */
++	pldev = to_platform_device (device);
++	kfree (pldev);
++}
++
++/*
++ * Register the Titan GE with the kernel
++ */
++static int __init titan_ge_init_module(void)
++{
++	struct platform_device *pldev;
++	unsigned int version, device;
++	int i;
++
++	printk(KERN_NOTICE
++	       "PMC-Sierra TITAN 10/100/1000 Ethernet Driver \n");
++
++	titan_ge_base = (unsigned long) ioremap(TITAN_GE_BASE, TITAN_GE_SIZE);
++	if (!titan_ge_base) {
++		printk("Mapping Titan GE failed\n");
++		goto out;
++	}
++
++	device = TITAN_GE_READ(TITAN_GE_DEVICE_ID);
++	version = (device & 0x000f0000) >> 16;
++	device &= 0x0000ffff;
++
++	printk(KERN_NOTICE "Device Id : %x,  Version : %x \n", device, version);
++
++#ifdef TITAN_RX_RING_IN_SRAM
++	titan_ge_sram = (unsigned long) ioremap(TITAN_SRAM_BASE,
++						TITAN_SRAM_SIZE);
++	if (!titan_ge_sram) {
++		printk("Mapping Titan SRAM failed\n");
++		goto out_unmap_ge;
++	}
++#endif
++
++	if (driver_register(&titan_soc_driver)) {
++		printk(KERN_ERR "Driver registration failed\n");
++		goto out_unmap_sram;
++	}
++
++	for (i = 0; i < 3; i++) {
++		titan_ge_device[i] = NULL;
++
++	        if (!(pldev = kmalloc (sizeof (*pldev), GFP_KERNEL)))
++	                continue;
++
++                memset (pldev, 0, sizeof (*pldev));
++                pldev->name		= titan_string;
++                pldev->id		= i;
++                pldev->dev.release	= titan_platform_release;
++                titan_ge_device[i]	= pldev;
++
++                if (platform_device_register (pldev)) {
++                        kfree (pldev);
++                        titan_ge_device[i] = NULL;
++                        continue;
++                }
++                                                                                
++                if (!pldev->dev.driver) {
++	                /*
++			 * The driver was not bound to this device, there was
++	                 * no hardware at this address. Unregister it, as the
++	                 * release fuction will take care of freeing the
++	                 * allocated structure
++			 */
++                        titan_ge_device[i] = NULL;
++                        platform_device_unregister (pldev);
++                }
++        }
++
++	return 0;
++
++out_unmap_sram:
++	iounmap((void *)titan_ge_sram);
++
++out_unmap_ge:
++	iounmap((void *)titan_ge_base);
++
++out:
++	return -ENOMEM;
++}
++
++/*
++ * Unregister the Titan GE from the kernel
++ */
++static void __exit titan_ge_cleanup_module(void)
++{
++	int i;
++
++	driver_unregister(&titan_soc_driver);
++
++	for (i = 0; i < 3; i++) {
++		if (titan_ge_device[i]) {
++			platform_device_unregister (titan_ge_device[i]);
++			titan_ge_device[i] = NULL;
++		}
++	}
++
++	iounmap((void *)titan_ge_sram);
++	iounmap((void *)titan_ge_base);
++}
++
++MODULE_AUTHOR("Manish Lachwani <lachwani@pmc-sierra.com>");
++MODULE_DESCRIPTION("Titan GE Ethernet driver");
++MODULE_LICENSE("GPL");
++
++module_init(titan_ge_init_module);
++module_exit(titan_ge_cleanup_module);
+diff -Naur linux-2.6.17.orig/drivers/net/titan_ge.h linux-2.6.17/drivers/net/titan_ge.h
+--- linux-2.6.17.orig/drivers/net/titan_ge.h	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/drivers/net/titan_ge.h	2006-06-19 18:16:13.000000000 -0700
+@@ -0,0 +1,417 @@
++#ifndef _TITAN_GE_H_
++#define _TITAN_GE_H_
++
++#include <linux/config.h>
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/config.h>
++#include <linux/spinlock.h>
++#include <asm/byteorder.h>
++
++/*
++ * These functions should be later moved to a more generic location since there
++ * will be others accessing it also
++ */
++
++/*
++ * This is the way it works: LKB5 Base is at 0x0128. TITAN_BASE is defined in
++ * include/asm/titan_dep.h. TITAN_GE_BASE is the value in the TITAN_GE_LKB5
++ * register.
++ */
++
++#define	TITAN_GE_BASE	0xfe000000UL
++#define	TITAN_GE_SIZE	0x10000UL
++
++extern unsigned long titan_ge_base;
++
++#define	TITAN_GE_WRITE(offset, data) \
++		*(volatile u32 *)(titan_ge_base + (offset)) = (data)
++
++#define TITAN_GE_READ(offset) *(volatile u32 *)(titan_ge_base + (offset))
++
++#ifndef msec_delay
++#define msec_delay(x)   do { if(in_interrupt()) { \
++				/* Don't mdelay in interrupt context! */ \
++				BUG(); \
++			} else { \
++				set_current_state(TASK_UNINTERRUPTIBLE); \
++				schedule_timeout((x * HZ)/1000); \
++			} } while(0)
++#endif
++
++#define TITAN_GE_PORT_0
++
++#define	TITAN_SRAM_BASE		((OCD_READ(RM9000x2_OCD_LKB13) & ~1) << 4)
++#define	TITAN_SRAM_SIZE		0x2000UL
++
++/*
++ * We may need these constants
++ */
++#define TITAN_BIT0    0x00000001
++#define TITAN_BIT1    0x00000002
++#define TITAN_BIT2    0x00000004
++#define TITAN_BIT3    0x00000008
++#define TITAN_BIT4    0x00000010
++#define TITAN_BIT5    0x00000020
++#define TITAN_BIT6    0x00000040
++#define TITAN_BIT7    0x00000080
++#define TITAN_BIT8    0x00000100
++#define TITAN_BIT9    0x00000200
++#define TITAN_BIT10   0x00000400
++#define TITAN_BIT11   0x00000800
++#define TITAN_BIT12   0x00001000
++#define TITAN_BIT13   0x00002000
++#define TITAN_BIT14   0x00004000
++#define TITAN_BIT15   0x00008000
++#define TITAN_BIT16   0x00010000
++#define TITAN_BIT17   0x00020000
++#define TITAN_BIT18   0x00040000
++#define TITAN_BIT19   0x00080000
++#define TITAN_BIT20   0x00100000
++#define TITAN_BIT21   0x00200000
++#define TITAN_BIT22   0x00400000
++#define TITAN_BIT23   0x00800000
++#define TITAN_BIT24   0x01000000
++#define TITAN_BIT25   0x02000000
++#define TITAN_BIT26   0x04000000
++#define TITAN_BIT27   0x08000000
++#define TITAN_BIT28   0x10000000
++#define TITAN_BIT29   0x20000000
++#define TITAN_BIT30   0x40000000
++#define TITAN_BIT31   0x80000000
++
++/* Flow Control */
++#define	TITAN_GE_FC_NONE	0x0
++#define	TITAN_GE_FC_FULL	0x1
++#define	TITAN_GE_FC_TX_PAUSE	0x2
++#define	TITAN_GE_FC_RX_PAUSE	0x3
++
++/* Duplex Settings */
++#define	TITAN_GE_FULL_DUPLEX	0x1
++#define	TITAN_GE_HALF_DUPLEX	0x2
++
++/* Speed settings */
++#define	TITAN_GE_SPEED_1000	0x1
++#define	TITAN_GE_SPEED_100	0x2
++#define	TITAN_GE_SPEED_10	0x3
++
++/* Debugging info only */
++#undef TITAN_DEBUG
++
++/* Keep the rings in the Titan's SSRAM */
++#define TITAN_RX_RING_IN_SRAM
++
++#ifdef CONFIG_64BIT
++#define	TITAN_GE_IE_MASK	0xfffffffffb001b64
++#define	TITAN_GE_IE_STATUS	0xfffffffffb001b60
++#else
++#define	TITAN_GE_IE_MASK	0xfb001b64
++#define	TITAN_GE_IE_STATUS	0xfb001b60
++#endif
++
++/* Support for Jumbo Frames */
++#undef TITAN_GE_JUMBO_FRAMES
++
++/* Rx buffer size */
++#ifdef TITAN_GE_JUMBO_FRAMES
++#define	TITAN_GE_JUMBO_BUFSIZE	9080
++#else
++#define	TITAN_GE_STD_BUFSIZE	1580
++#endif
++
++/*
++ * Tx and Rx Interrupt Coalescing parameter. These values are
++ * for 1 Ghz processor. Rx coalescing can be taken care of
++ * by NAPI. NAPI is adaptive and hence useful. Tx coalescing
++ * is not adaptive. Hence, these values need to be adjusted
++ * based on load, CPU speed etc.
++ */
++#define	TITAN_GE_RX_COAL	150
++#define	TITAN_GE_TX_COAL	300
++
++#if defined(__BIG_ENDIAN)
++
++/* Define the Rx descriptor */
++typedef struct eth_rx_desc {
++	u32     reserved;	/* Unused 		*/
++	u32     buffer_addr;	/* CPU buffer address 	*/
++	u32	cmd_sts;	/* Command and Status	*/
++	u32	buffer;		/* XDMA buffer address	*/
++} titan_ge_rx_desc;
++
++/* Define the Tx descriptor */
++typedef struct eth_tx_desc {
++	u16     cmd_sts;	/* Command, Status and Buffer count */
++	u16	buffer_len;	/* Length of the buffer	*/
++	u32     buffer_addr;	/* Physical address of the buffer */
++} titan_ge_tx_desc;
++
++#elif defined(__LITTLE_ENDIAN)
++
++/* Define the Rx descriptor */
++typedef struct eth_rx_desc {
++	u32	buffer_addr;	/* CPU buffer address   */
++	u32	reserved;	/* Unused               */
++	u32	buffer;		/* XDMA buffer address  */
++	u32	cmd_sts;	/* Command and Status   */
++} titan_ge_rx_desc;
++
++/* Define the Tx descriptor */
++typedef struct eth_tx_desc {
++	u32     buffer_addr;	/* Physical address of the buffer */
++	u16     buffer_len;     /* Length of the buffer */
++	u16     cmd_sts;        /* Command, Status and Buffer count */
++} titan_ge_tx_desc;
++#endif
++
++/* Default Tx Queue Size */
++#define	TITAN_GE_TX_QUEUE	128
++#define TITAN_TX_RING_BYTES	(TITAN_GE_TX_QUEUE * sizeof(struct eth_tx_desc))
++
++/* Default Rx Queue Size */
++#define	TITAN_GE_RX_QUEUE	64
++#define TITAN_RX_RING_BYTES	(TITAN_GE_RX_QUEUE * sizeof(struct eth_rx_desc))
++
++/* Packet Structure */
++typedef struct _pkt_info {
++	unsigned int           len;
++	unsigned int            cmd_sts;
++	unsigned int            buffer;
++	struct sk_buff          *skb;
++	unsigned int		checksum;
++} titan_ge_packet;
++
++
++#define	PHYS_CNT	3
++
++/* Titan Port specific data structure */
++typedef struct _eth_port_ctrl {
++	unsigned int		port_num;
++	u8			port_mac_addr[6];
++
++	/* Rx descriptor pointers */
++	int 			rx_curr_desc_q, rx_used_desc_q;
++
++	/* Tx descriptor pointers */
++	int 			tx_curr_desc_q, tx_used_desc_q;
++
++	/* Rx descriptor area */
++	volatile titan_ge_rx_desc	*rx_desc_area;
++	unsigned int			rx_desc_area_size;
++	struct sk_buff*			rx_skb[TITAN_GE_RX_QUEUE];
++
++	/* Tx Descriptor area */
++	volatile titan_ge_tx_desc	*tx_desc_area;
++	unsigned int                    tx_desc_area_size;
++	struct sk_buff*                 tx_skb[TITAN_GE_TX_QUEUE];
++
++	/* Timeout task */
++	struct work_struct		tx_timeout_task;
++
++	/* DMA structures and handles */
++	dma_addr_t			tx_dma;
++	dma_addr_t			rx_dma;
++	dma_addr_t			tx_dma_array[TITAN_GE_TX_QUEUE];
++
++	/* Device lock */
++	spinlock_t			lock;
++
++	unsigned int			tx_ring_skbs;
++	unsigned int			rx_ring_size;
++	unsigned int			tx_ring_size;
++	unsigned int			rx_ring_skbs;
++
++	struct net_device_stats		stats;
++
++	/* Tx and Rx coalescing */
++	unsigned long			rx_int_coal;
++	unsigned long			tx_int_coal;
++
++	/* Threshold for replenishing the Rx and Tx rings */
++	unsigned int			tx_threshold;
++	unsigned int			rx_threshold;
++
++	/* NAPI work limit */
++	unsigned int			rx_work_limit;
++} titan_ge_port_info;
++
++/* Titan specific constants */
++#define	TITAN_ETH_PORT_IRQ		3
++
++/* Max Rx buffer */
++#define	TITAN_GE_MAX_RX_BUFFER		65536
++
++/* Tx and Rx Error */
++#define	TITAN_GE_ERROR
++
++/* Rx Descriptor Command and Status */
++
++#define	TITAN_GE_RX_CRC_ERROR		TITAN_BIT27	/* crc error */
++#define	TITAN_GE_RX_OVERFLOW_ERROR	TITAN_BIT15	/* overflow */
++#define TITAN_GE_RX_BUFFER_OWNED	TITAN_BIT21	/* buffer ownership */
++#define	TITAN_GE_RX_STP			TITAN_BIT31	/* start of packet */
++#define	TITAN_GE_RX_BAM			TITAN_BIT30	/* broadcast address match */
++#define TITAN_GE_RX_PAM			TITAN_BIT28	/* physical address match */
++#define TITAN_GE_RX_LAFM		TITAN_BIT29	/* logical address filter match */
++#define TITAN_GE_RX_VLAN		TITAN_BIT26	/* virtual lans */
++#define TITAN_GE_RX_PERR		TITAN_BIT19	/* packet error */
++#define TITAN_GE_RX_TRUNC		TITAN_BIT20	/* packet size greater than 32 buffers */
++
++/* Tx Descriptor Command */
++#define	TITAN_GE_TX_BUFFER_OWNED	TITAN_BIT5	/* buffer ownership */
++#define	TITAN_GE_TX_ENABLE_INTERRUPT	TITAN_BIT15	/* Interrupt Enable */
++
++/* Return Status */
++#define	TITAN_OK	0x1	/* Good Status */
++#define	TITAN_ERROR	0x2	/* Error Status */
++
++/* MIB specific register offset */
++#define TITAN_GE_MSTATX_STATS_BASE_LOW       0x0800  /* MSTATX COUNTL[15:0] */
++#define TITAN_GE_MSTATX_STATS_BASE_MID       0x0804  /* MSTATX COUNTM[15:0] */
++#define TITAN_GE_MSTATX_STATS_BASE_HI        0x0808  /* MSTATX COUNTH[7:0] */
++#define TITAN_GE_MSTATX_CONTROL              0x0828  /* MSTATX Control */
++#define TITAN_GE_MSTATX_VARIABLE_SELECT      0x082C  /* MSTATX Variable Select */
++
++/* MIB counter offsets, add to the TITAN_GE_MSTATX_STATS_BASE_XXX */
++#define TITAN_GE_MSTATX_RXFRAMESOK                   0x0040
++#define TITAN_GE_MSTATX_RXOCTETSOK                   0x0050
++#define TITAN_GE_MSTATX_RXFRAMES                     0x0060
++#define TITAN_GE_MSTATX_RXOCTETS                     0x0070
++#define TITAN_GE_MSTATX_RXUNICASTFRAMESOK            0x0080
++#define TITAN_GE_MSTATX_RXBROADCASTFRAMESOK          0x0090
++#define TITAN_GE_MSTATX_RXMULTICASTFRAMESOK          0x00A0
++#define TITAN_GE_MSTATX_RXTAGGEDFRAMESOK             0x00B0
++#define TITAN_GE_MSTATX_RXMACPAUSECONTROLFRAMESOK    0x00C0
++#define TITAN_GE_MSTATX_RXMACCONTROLFRAMESOK         0x00D0
++#define TITAN_GE_MSTATX_RXFCSERROR                   0x00E0
++#define TITAN_GE_MSTATX_RXALIGNMENTERROR             0x00F0
++#define TITAN_GE_MSTATX_RXSYMBOLERROR                0x0100
++#define TITAN_GE_MSTATX_RXLAYER1ERROR                0x0110
++#define TITAN_GE_MSTATX_RXINRANGELENGTHERROR         0x0120
++#define TITAN_GE_MSTATX_RXLONGLENGTHERROR            0x0130
++#define TITAN_GE_MSTATX_RXLONGLENGTHCRCERROR         0x0140
++#define TITAN_GE_MSTATX_RXSHORTLENGTHERROR           0x0150
++#define TITAN_GE_MSTATX_RXSHORTLLENGTHCRCERROR       0x0160
++#define TITAN_GE_MSTATX_RXFRAMES64OCTETS             0x0170
++#define TITAN_GE_MSTATX_RXFRAMES65TO127OCTETS        0x0180
++#define TITAN_GE_MSTATX_RXFRAMES128TO255OCTETS       0x0190
++#define TITAN_GE_MSTATX_RXFRAMES256TO511OCTETS       0x01A0
++#define TITAN_GE_MSTATX_RXFRAMES512TO1023OCTETS      0x01B0
++#define TITAN_GE_MSTATX_RXFRAMES1024TO1518OCTETS     0x01C0
++#define TITAN_GE_MSTATX_RXFRAMES1519TOMAXSIZE        0x01D0
++#define TITAN_GE_MSTATX_RXSTATIONADDRESSFILTERED     0x01E0
++#define TITAN_GE_MSTATX_RXVARIABLE                   0x01F0
++#define TITAN_GE_MSTATX_GENERICADDRESSFILTERED       0x0200
++#define TITAN_GE_MSTATX_UNICASTFILTERED              0x0210
++#define TITAN_GE_MSTATX_MULTICASTFILTERED            0x0220
++#define TITAN_GE_MSTATX_BROADCASTFILTERED            0x0230
++#define TITAN_GE_MSTATX_HASHFILTERED                 0x0240
++#define TITAN_GE_MSTATX_TXFRAMESOK                   0x0250
++#define TITAN_GE_MSTATX_TXOCTETSOK                   0x0260
++#define TITAN_GE_MSTATX_TXOCTETS                     0x0270
++#define TITAN_GE_MSTATX_TXTAGGEDFRAMESOK             0x0280
++#define TITAN_GE_MSTATX_TXMACPAUSECONTROLFRAMESOK    0x0290
++#define TITAN_GE_MSTATX_TXFCSERROR                   0x02A0
++#define TITAN_GE_MSTATX_TXSHORTLENGTHERROR           0x02B0
++#define TITAN_GE_MSTATX_TXLONGLENGTHERROR            0x02C0
++#define TITAN_GE_MSTATX_TXSYSTEMERROR                0x02D0
++#define TITAN_GE_MSTATX_TXMACERROR                   0x02E0
++#define TITAN_GE_MSTATX_TXCARRIERSENSEERROR          0x02F0
++#define TITAN_GE_MSTATX_TXSQETESTERROR               0x0300
++#define TITAN_GE_MSTATX_TXUNICASTFRAMESOK            0x0310
++#define TITAN_GE_MSTATX_TXBROADCASTFRAMESOK          0x0320
++#define TITAN_GE_MSTATX_TXMULTICASTFRAMESOK          0x0330
++#define TITAN_GE_MSTATX_TXUNICASTFRAMESATTEMPTED     0x0340
++#define TITAN_GE_MSTATX_TXBROADCASTFRAMESATTEMPTED   0x0350
++#define TITAN_GE_MSTATX_TXMULTICASTFRAMESATTEMPTED   0x0360
++#define TITAN_GE_MSTATX_TXFRAMES64OCTETS             0x0370
++#define TITAN_GE_MSTATX_TXFRAMES65TO127OCTETS        0x0380
++#define TITAN_GE_MSTATX_TXFRAMES128TO255OCTETS       0x0390
++#define TITAN_GE_MSTATX_TXFRAMES256TO511OCTETS       0x03A0
++#define TITAN_GE_MSTATX_TXFRAMES512TO1023OCTETS      0x03B0
++#define TITAN_GE_MSTATX_TXFRAMES1024TO1518OCTETS     0x03C0
++#define TITAN_GE_MSTATX_TXFRAMES1519TOMAXSIZE        0x03D0
++#define TITAN_GE_MSTATX_TXVARIABLE                   0x03E0
++#define TITAN_GE_MSTATX_RXSYSTEMERROR                0x03F0
++#define TITAN_GE_MSTATX_SINGLECOLLISION              0x0400
++#define TITAN_GE_MSTATX_MULTIPLECOLLISION            0x0410
++#define TITAN_GE_MSTATX_DEFERREDXMISSIONS            0x0420
++#define TITAN_GE_MSTATX_LATECOLLISIONS               0x0430
++#define TITAN_GE_MSTATX_ABORTEDDUETOXSCOLLS          0x0440
++
++/* Interrupt specific defines */
++#define TITAN_GE_DEVICE_ID         0x0000  /* Device ID */
++#define TITAN_GE_RESET             0x0004  /* Reset reg */
++#define TITAN_GE_TSB_CTRL_0        0x000C  /* TSB Control reg 0 */
++#define TITAN_GE_TSB_CTRL_1        0x0010  /* TSB Control reg 1 */
++#define TITAN_GE_INTR_GRP0_STATUS  0x0040  /* General Interrupt Group 0 Status */
++#define TITAN_GE_INTR_XDMA_CORE_A  0x0048  /* XDMA Channel Interrupt Status, Core A*/
++#define TITAN_GE_INTR_XDMA_CORE_B  0x004C  /* XDMA Channel Interrupt Status, Core B*/
++#define	TITAN_GE_INTR_XDMA_IE	   0x0058  /* XDMA Channel Interrupt Enable */
++#define TITAN_GE_SDQPF_ECC_INTR    0x480C  /* SDQPF ECC Interrupt Status */
++#define TITAN_GE_SDQPF_RXFIFO_CTL  0x4828  /* SDQPF RxFifo Control and Interrupt Enb*/
++#define TITAN_GE_SDQPF_RXFIFO_INTR 0x482C  /* SDQPF RxFifo Interrupt Status */
++#define TITAN_GE_SDQPF_TXFIFO_CTL  0x4928  /* SDQPF TxFifo Control and Interrupt Enb*/
++#define TITAN_GE_SDQPF_TXFIFO_INTR 0x492C  /* SDQPF TxFifo Interrupt Status */
++#define	TITAN_GE_SDQPF_RXFIFO_0	   0x4840  /* SDQPF RxFIFO Enable */
++#define	TITAN_GE_SDQPF_TXFIFO_0	   0x4940  /* SDQPF TxFIFO Enable */
++#define TITAN_GE_XDMA_CONFIG       0x5000  /* XDMA Global Configuration */
++#define TITAN_GE_XDMA_INTR_SUMMARY 0x5010  /* XDMA Interrupt Summary */
++#define TITAN_GE_XDMA_BUFADDRPRE   0x5018  /* XDMA Buffer Address Prefix */
++#define TITAN_GE_XDMA_DESCADDRPRE  0x501C  /* XDMA Descriptor Address Prefix */
++#define TITAN_GE_XDMA_PORTWEIGHT   0x502C  /* XDMA Port Weight Configuration */
++
++/* Rx MAC defines */
++#define TITAN_GE_RMAC_CONFIG_1               0x1200  /* RMAC Configuration 1 */
++#define TITAN_GE_RMAC_CONFIG_2               0x1204  /* RMAC Configuration 2 */
++#define TITAN_GE_RMAC_MAX_FRAME_LEN          0x1208  /* RMAC Max Frame Length */
++#define TITAN_GE_RMAC_STATION_HI             0x120C  /* Rx Station Address High */
++#define TITAN_GE_RMAC_STATION_MID            0x1210  /* Rx Station Address Middle */
++#define TITAN_GE_RMAC_STATION_LOW            0x1214  /* Rx Station Address Low */
++#define TITAN_GE_RMAC_LINK_CONFIG            0x1218  /* RMAC Link Configuration */
++
++/* Tx MAC defines */
++#define TITAN_GE_TMAC_CONFIG_1               0x1240  /* TMAC Configuration 1 */
++#define TITAN_GE_TMAC_CONFIG_2               0x1244  /* TMAC Configuration 2 */
++#define TITAN_GE_TMAC_IPG                    0x1248  /* TMAC Inter-Packet Gap */
++#define TITAN_GE_TMAC_STATION_HI             0x124C  /* Tx Station Address High */
++#define TITAN_GE_TMAC_STATION_MID            0x1250  /* Tx Station Address Middle */
++#define TITAN_GE_TMAC_STATION_LOW            0x1254  /* Tx Station Address Low */
++#define TITAN_GE_TMAC_MAX_FRAME_LEN          0x1258  /* TMAC Max Frame Length */
++#define TITAN_GE_TMAC_MIN_FRAME_LEN          0x125C  /* TMAC Min Frame Length */
++#define TITAN_GE_TMAC_PAUSE_FRAME_TIME       0x1260  /* TMAC Pause Frame Time */
++#define TITAN_GE_TMAC_PAUSE_FRAME_INTERVAL   0x1264  /* TMAC Pause Frame Interval */
++
++/* GMII register */
++#define TITAN_GE_GMII_INTERRUPT_STATUS       0x1348  /* GMII Interrupt Status */
++#define TITAN_GE_GMII_CONFIG_GENERAL         0x134C  /* GMII Configuration General */
++#define TITAN_GE_GMII_CONFIG_MODE            0x1350  /* GMII Configuration Mode */
++
++/* Tx and Rx XDMA defines */
++#define	TITAN_GE_INT_COALESCING		     0x5030 /* Interrupt Coalescing */
++#define	TITAN_GE_CHANNEL0_CONFIG	     0x5040 /* Channel 0 XDMA config */
++#define	TITAN_GE_CHANNEL0_INTERRUPT	     0x504c /* Channel 0 Interrupt Status */
++#define	TITAN_GE_GDI_INTERRUPT_ENABLE        0x5050 /* IE for the GDI Errors */
++#define	TITAN_GE_CHANNEL0_PACKET	     0x5060 /* Channel 0 Packet count */
++#define	TITAN_GE_CHANNEL0_BYTE		     0x5064 /* Channel 0 Byte count */
++#define	TITAN_GE_CHANNEL0_TX_DESC	     0x5054 /* Channel 0 Tx first desc */
++#define	TITAN_GE_CHANNEL0_RX_DESC	     0x5058 /* Channel 0 Rx first desc */
++
++/* AFX (Address Filter Exact) register offsets for Slice 0 */
++#define TITAN_GE_AFX_EXACT_MATCH_LOW         0x1100  /* AFX Exact Match Address Low*/
++#define TITAN_GE_AFX_EXACT_MATCH_MID         0x1104  /* AFX Exact Match Address Mid*/
++#define TITAN_GE_AFX_EXACT_MATCH_HIGH        0x1108  /* AFX Exact Match Address Hi */
++#define TITAN_GE_AFX_EXACT_MATCH_VID         0x110C  /* AFX Exact Match VID */
++#define TITAN_GE_AFX_MULTICAST_HASH_LOW      0x1110  /* AFX Multicast HASH Low */
++#define TITAN_GE_AFX_MULTICAST_HASH_MIDLOW   0x1114  /* AFX Multicast HASH MidLow */
++#define TITAN_GE_AFX_MULTICAST_HASH_MIDHI    0x1118  /* AFX Multicast HASH MidHi */
++#define TITAN_GE_AFX_MULTICAST_HASH_HI       0x111C  /* AFX Multicast HASH Hi */
++#define TITAN_GE_AFX_ADDRS_FILTER_CTRL_0     0x1120  /* AFX Address Filter Ctrl 0 */
++#define TITAN_GE_AFX_ADDRS_FILTER_CTRL_1     0x1124  /* AFX Address Filter Ctrl 1 */
++#define TITAN_GE_AFX_ADDRS_FILTER_CTRL_2     0x1128  /* AFX Address Filter Ctrl 2 */
++
++/* Traffic Groomer block */
++#define        TITAN_GE_TRTG_CONFIG	     0x1000  /* TRTG Config */
++
++#endif 				/* _TITAN_GE_H_ */
++
+diff -Naur linux-2.6.17.orig/drivers/net/titan_mdio.c linux-2.6.17/drivers/net/titan_mdio.c
+--- linux-2.6.17.orig/drivers/net/titan_mdio.c	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/drivers/net/titan_mdio.c	2006-06-19 18:16:13.000000000 -0700
+@@ -0,0 +1,217 @@
++/*
++ * drivers/net/titan_mdio.c - Driver for Titan ethernet ports
++ *
++ * Copyright (C) 2003 PMC-Sierra Inc.
++ * Author : Manish Lachwani (lachwani@pmc-sierra.com)
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
++ *
++ * Management Data IO (MDIO) driver for the Titan GMII. Interacts with the Marvel PHY
++ * on the Titan. No support for the TBI as yet.
++ *
++ */
++
++#include	"titan_mdio.h"
++
++#define MDIO_DEBUG
++
++/*
++ * Local constants
++ */
++#define MAX_CLKA            1023
++#define MAX_PHY_DEV         31
++#define MAX_PHY_REG         31
++#define WRITEADDRS_OPCODE   0x0
++#define	READ_OPCODE	    0x2
++#define WRITE_OPCODE        0x1
++#define MAX_MDIO_POLL       100
++
++/*
++ * Titan MDIO and SCMB registers
++ */
++#define TITAN_GE_SCMB_CONTROL                0x01c0  /* SCMB Control */
++#define TITAN_GE_SCMB_CLKA	             0x01c4  /* SCMB Clock A */
++#define TITAN_GE_MDIO_COMMAND                0x01d0  /* MDIO Command */
++#define TITAN_GE_MDIO_DEVICE_PORT_ADDRESS    0x01d4  /* MDIO Device and Port addrs */
++#define TITAN_GE_MDIO_DATA                   0x01d8  /* MDIO Data */
++#define TITAN_GE_MDIO_INTERRUPTS             0x01dC  /* MDIO Interrupts */
++
++/*
++ * Function to poll the MDIO
++ */
++static int titan_ge_mdio_poll(void)
++{
++	int	i, val;
++
++	for (i = 0; i < MAX_MDIO_POLL; i++) {
++		val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_COMMAND);
++
++		if (!(val & 0x8000))
++			return TITAN_GE_MDIO_GOOD;
++	}
++
++	return TITAN_GE_MDIO_ERROR;
++}
++
++
++/*
++ * Initialize and configure the MDIO
++ */
++int titan_ge_mdio_setup(titan_ge_mdio_config *titan_mdio)
++{
++	unsigned long	val;
++
++	/* Reset the SCMB and program into MDIO mode*/
++	TITAN_GE_MDIO_WRITE(TITAN_GE_SCMB_CONTROL, 0x9000);
++	TITAN_GE_MDIO_WRITE(TITAN_GE_SCMB_CONTROL, 0x1000);
++
++	/* CLK A */
++	val = TITAN_GE_MDIO_READ(TITAN_GE_SCMB_CLKA);
++	val = ( (val & ~(0x03ff)) | (titan_mdio->clka & 0x03ff));
++	TITAN_GE_MDIO_WRITE(TITAN_GE_SCMB_CLKA, val);
++
++	/* Preamble Suppresion */
++	val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_COMMAND);
++	val = ( (val & ~(0x0001)) | (titan_mdio->mdio_spre & 0x0001));
++	TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_COMMAND, val);
++
++	/* MDIO mode */
++	val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS);
++	val = ( (val & ~(0x4000)) | (titan_mdio->mdio_mode & 0x4000));
++	TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS, val);
++
++	return TITAN_GE_MDIO_GOOD;
++}
++
++/*
++ * Set the PHY address in indirect mode
++ */
++int titan_ge_mdio_inaddrs(int dev_addr, int reg_addr)
++{
++	volatile unsigned long	val;
++
++	/* Setup the PHY device */
++	val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS);
++	val = ( (val & ~(0x1f00)) | ( (dev_addr << 8) & 0x1f00));
++	val = ( (val & ~(0x001f)) | ( reg_addr & 0x001f));
++	TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS, val);
++
++	/* Write the new address */
++	val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_COMMAND);
++	val = ( (val & ~(0x0300)) | ( (WRITEADDRS_OPCODE << 8) & 0x0300));
++	TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_COMMAND, val);
++
++	return TITAN_GE_MDIO_GOOD;
++}
++
++/*
++ * Read the MDIO register. This is what the individual parametes mean:
++ *
++ * dev_addr : PHY ID
++ * reg_addr : register offset
++ *
++ * See the spec for the Titan MAC. We operate in the Direct Mode.
++ */
++
++#define MAX_RETRIES	2
++
++int titan_ge_mdio_read(int dev_addr, int reg_addr, unsigned int *pdata)
++{
++	volatile unsigned long	val;
++	int retries = 0;
++
++	/* Setup the PHY device */
++
++again:
++	val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS);
++	val = ( (val & ~(0x1f00)) | ( (dev_addr << 8) & 0x1f00));
++	val = ( (val & ~(0x001f)) | ( reg_addr & 0x001f));
++	val |= 0x4000;
++	TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS, val);
++
++	udelay(30);
++
++	/* Issue the read command */
++	val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_COMMAND);
++	val = ( (val & ~(0x0300)) | ( (READ_OPCODE << 8) & 0x0300));
++	TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_COMMAND, val);
++
++	udelay(30);
++
++	if (titan_ge_mdio_poll() != TITAN_GE_MDIO_GOOD)
++		return TITAN_GE_MDIO_ERROR;
++
++	*pdata = (unsigned int)TITAN_GE_MDIO_READ(TITAN_GE_MDIO_DATA);
++	val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_INTERRUPTS);
++
++	udelay(30);
++
++	if (val & 0x2) {
++		if (retries == MAX_RETRIES)
++			return TITAN_GE_MDIO_ERROR;
++		else {
++			retries++;
++			goto again;
++		}
++	}
++
++	return TITAN_GE_MDIO_GOOD;
++}
++
++/*
++ * Write to the MDIO register
++ *
++ * dev_addr : PHY ID
++ * reg_addr : register that needs to be written to
++ *
++ */
++int titan_ge_mdio_write(int dev_addr, int reg_addr, unsigned int data)
++{
++	volatile unsigned long	val;
++
++	if (titan_ge_mdio_poll() != TITAN_GE_MDIO_GOOD)
++		return TITAN_GE_MDIO_ERROR;
++
++	/* Setup the PHY device */
++	val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS);
++	val = ( (val & ~(0x1f00)) | ( (dev_addr << 8) & 0x1f00));
++	val = ( (val & ~(0x001f)) | ( reg_addr & 0x001f));
++	val |= 0x4000;
++	TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_DEVICE_PORT_ADDRESS, val);
++
++	udelay(30);
++
++	/* Setup the data to write */
++	TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_DATA, data);
++
++	udelay(30);
++
++	/* Issue the write command */
++	val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_COMMAND);
++	val = ( (val & ~(0x0300)) | ( (WRITE_OPCODE << 8) & 0x0300));
++	TITAN_GE_MDIO_WRITE(TITAN_GE_MDIO_COMMAND, val);
++
++	udelay(30);
++
++	if (titan_ge_mdio_poll() != TITAN_GE_MDIO_GOOD)
++		return TITAN_GE_MDIO_ERROR;
++
++	val = TITAN_GE_MDIO_READ(TITAN_GE_MDIO_INTERRUPTS);
++	if (val & 0x2)
++		return TITAN_GE_MDIO_ERROR;
++
++	return TITAN_GE_MDIO_GOOD;
++}
++
+diff -Naur linux-2.6.17.orig/drivers/net/titan_mdio.h linux-2.6.17/drivers/net/titan_mdio.h
+--- linux-2.6.17.orig/drivers/net/titan_mdio.h	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/drivers/net/titan_mdio.h	2006-06-19 18:16:13.000000000 -0700
+@@ -0,0 +1,56 @@
++/*
++ * MDIO used to interact with the PHY when using GMII/MII
++ */
++#ifndef _TITAN_MDIO_H
++#define _TITAN_MDIO_H
++
++#include <linux/netdevice.h>
++#include <linux/workqueue.h>
++#include <linux/delay.h>
++#include "titan_ge.h"
++
++
++#define	TITAN_GE_MDIO_ERROR	(-9000)
++#define	TITAN_GE_MDIO_GOOD	0
++
++#define	TITAN_GE_MDIO_BASE		titan_ge_base
++
++#define	TITAN_GE_MDIO_READ(offset)	\
++	*(volatile u32 *)(titan_ge_base + (offset))
++
++#define	TITAN_GE_MDIO_WRITE(offset, data)	\
++	*(volatile u32 *)(titan_ge_base + (offset)) = (data)
++
++
++/* GMII specific registers */
++#define	TITAN_GE_MARVEL_PHY_ID		0x00
++#define	TITAN_PHY_AUTONEG_ADV		0x04
++#define	TITAN_PHY_LP_ABILITY		0x05
++#define	TITAN_GE_MDIO_MII_CTRL		0x09
++#define	TITAN_GE_MDIO_MII_EXTENDED	0x0f
++#define	TITAN_GE_MDIO_PHY_CTRL		0x10
++#define	TITAN_GE_MDIO_PHY_STATUS	0x11
++#define	TITAN_GE_MDIO_PHY_IE		0x12
++#define	TITAN_GE_MDIO_PHY_IS		0x13
++#define	TITAN_GE_MDIO_PHY_LED		0x18
++#define	TITAN_GE_MDIO_PHY_LED_OVER	0x19
++#define	PHY_ANEG_TIME_WAIT		45	/* 45 seconds wait time */
++
++/*
++ * MDIO Config Structure
++ */
++typedef struct {
++	unsigned int		clka;
++	int			mdio_spre;
++	int			mdio_mode;
++} titan_ge_mdio_config;
++
++/*
++ * Function Prototypes
++ */
++int titan_ge_mdio_setup(titan_ge_mdio_config *);
++int titan_ge_mdio_inaddrs(int, int);
++int titan_ge_mdio_read(int, int, unsigned int *);
++int titan_ge_mdio_write(int, int, unsigned int);
++
++#endif /* _TITAN_MDIO_H */
+diff -Naur linux-2.6.17.orig/drivers/net/tulip/tulip_core.c linux-2.6.17/drivers/net/tulip/tulip_core.c
+--- linux-2.6.17.orig/drivers/net/tulip/tulip_core.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/drivers/net/tulip/tulip_core.c	2006-06-19 18:16:13.000000000 -0700
+@@ -1483,14 +1483,6 @@
+ 			sa_offset = 2;		/* Grrr, damn Matrox boards. */
+ 			multiport_cnt = 4;
+ 		}
+-#ifdef CONFIG_DDB5476
+-		if ((pdev->bus->number == 0) && (PCI_SLOT(pdev->devfn) == 6)) {
+-			/* DDB5476 MAC address in first EEPROM locations. */
+-                       sa_offset = 0;
+-                       /* No media table either */
+-                       tp->flags &= ~HAS_MEDIA_TABLE;
+-               }
+-#endif
+ #ifdef CONFIG_DDB5477
+                if ((pdev->bus->number == 0) && (PCI_SLOT(pdev->devfn) == 4)) {
+                        /* DDB5477 MAC address in first EEPROM locations. */
+diff -Naur linux-2.6.17.orig/drivers/scsi/dec_esp.c linux-2.6.17/drivers/scsi/dec_esp.c
+--- linux-2.6.17.orig/drivers/scsi/dec_esp.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/drivers/scsi/dec_esp.c	2006-06-19 18:16:13.000000000 -0700
+@@ -55,7 +55,7 @@
+ 
+ static int  dma_bytes_sent(struct NCR_ESP *esp, int fifo_count);
+ static void dma_drain(struct NCR_ESP *esp);
+-static int  dma_can_transfer(struct NCR_ESP *esp, struct scsi_cmnd *sp);
++static int  dma_can_transfer(struct NCR_ESP *esp, struct scsi_cmnd * sp);
+ static void dma_dump_state(struct NCR_ESP *esp);
+ static void dma_init_read(struct NCR_ESP *esp, u32 vaddress, int length);
+ static void dma_init_write(struct NCR_ESP *esp, u32 vaddress, int length);
+@@ -230,7 +230,7 @@
+ 			mem_start = get_tc_base_addr(slot);
+ 
+ 			/* Store base addr into esp struct */
+-			esp->slot = CPHYSADDR(mem_start);
++			esp->slot = mem_start;
+ 
+ 			esp->dregs = 0;
+ 			esp->eregs = (void *)CKSEG1ADDR(mem_start +
+diff -Naur linux-2.6.17.orig/drivers/scsi/NCR53C9x.h linux-2.6.17/drivers/scsi/NCR53C9x.h
+--- linux-2.6.17.orig/drivers/scsi/NCR53C9x.h	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/drivers/scsi/NCR53C9x.h	2006-06-19 18:16:13.000000000 -0700
+@@ -145,12 +145,7 @@
+ 
+ #ifndef MULTIPLE_PAD_SIZES
+ 
+-#ifdef CONFIG_CPU_HAS_WB
+-#include <asm/wbflush.h>
+-#define esp_write(__reg, __val) do{(__reg) = (__val); wbflush();} while(0)
+-#else
+-#define esp_write(__reg, __val) ((__reg) = (__val))
+-#endif
++#define esp_write(__reg, __val) do{(__reg) = (__val); iob();} while(0)
+ #define esp_read(__reg) (__reg)
+ 
+ struct ESP_regs {
+diff -Naur linux-2.6.17.orig/drivers/scsi/sgiwd93.c linux-2.6.17/drivers/scsi/sgiwd93.c
+--- linux-2.6.17.orig/drivers/scsi/sgiwd93.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/drivers/scsi/sgiwd93.c	2006-06-19 18:16:13.000000000 -0700
+@@ -14,6 +14,7 @@
+ #include <linux/interrupt.h>
+ #include <linux/types.h>
+ #include <linux/mm.h>
++#include <linux/module.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <linux/dma-mapping.h>
+@@ -197,6 +198,7 @@
+ 	udelay(50);
+ 	hregs->ctrl = 0;
+ }
++EXPORT_SYMBOL_GPL(sgiwd93_reset);
+ 
+ static inline void init_hpc_chain(struct hpc_data *hd)
+ {
+diff -Naur linux-2.6.17.orig/drivers/serial/ip22zilog.c linux-2.6.17/drivers/serial/ip22zilog.c
+--- linux-2.6.17.orig/drivers/serial/ip22zilog.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/drivers/serial/ip22zilog.c	2006-06-19 18:16:13.000000000 -0700
+@@ -866,6 +866,7 @@
+ 	up->cflag = termios->c_cflag;
+ 
+ 	ip22zilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port));
++	uart_update_timeout(port, termios->c_cflag, baud);
+ 
+ 	spin_unlock_irqrestore(&up->port.lock, flags);
+ }
+@@ -1027,6 +1028,8 @@
+ 	}
+ 
+ 	con->cflag = cflag | CS8;			/* 8N1 */
++
++	uart_update_timeout(&ip22zilog_port_table[con->index].port, cflag, baud);
+ }
+ 
+ static int __init ip22zilog_console_setup(struct console *con, char *options)
+diff -Naur linux-2.6.17.orig/drivers/serial/ip3106_uart.c linux-2.6.17/drivers/serial/ip3106_uart.c
+--- linux-2.6.17.orig/drivers/serial/ip3106_uart.c	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/drivers/serial/ip3106_uart.c	2006-06-19 18:16:13.000000000 -0700
+@@ -0,0 +1,912 @@
++/*
++ * Initially based on linux-2.4.20_mvl31-pnx8xx0/drivers/char/serial_pnx8550.c
++ *
++ * Complete rewrite to drivers/serial/pnx8550_uart.c by
++ * Embedded Alley Solutions, source@embeddedalley.com as part of the
++ * PNX8550 2.6 port, and then drivers/serial/ip3106_uart.c to work
++ * with other Philips SoCs.
++ *
++ * Existing copyrights from files used to write this driver:
++ * Author: Per Hallsmark per.hallsmark@mvista.com
++ *
++ * and
++ *
++ * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
++ * Copyright (C) 2000 Deep Blue Solutions Ltd.
++ *
++ */
++
++#include <linux/config.h>
++
++#if defined(CONFIG_SERIAL_IP3106_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
++#define SUPPORT_SYSRQ
++#endif
++
++#include <linux/module.h>
++#include <linux/ioport.h>
++#include <linux/init.h>
++#include <linux/console.h>
++#include <linux/sysrq.h>
++#include <linux/device.h>
++#include <linux/tty.h>
++#include <linux/tty_flip.h>
++#include <linux/serial_core.h>
++#include <linux/serial.h>
++#include <linux/serial_ip3106.h>
++
++#include <asm/io.h>
++#include <asm/irq.h>
++
++#include <uart.h>
++
++/* We've been assigned a range on the "Low-density serial ports" major */
++#define SERIAL_IP3106_MAJOR	204
++#define MINOR_START		5
++
++#define NR_PORTS		2
++
++#define IP3106_ISR_PASS_LIMIT	256
++
++/*
++ * Convert from ignore_status_mask or read_status_mask to FIFO
++ * and interrupt status bits
++ */
++#define SM_TO_FIFO(x)	((x) >> 10)
++#define SM_TO_ISTAT(x)	((x) & 0x000001ff)
++#define FIFO_TO_SM(x)	((x) << 10)
++#define ISTAT_TO_SM(x)	((x) & 0x000001ff)
++
++/*
++ * This is the size of our serial port register set.
++ */
++#define UART_PORT_SIZE	0x1000
++
++/*
++ * This determines how often we check the modem status signals
++ * for any change.  They generally aren't connected to an IRQ
++ * so we have to poll them.  We also check immediately before
++ * filling the TX fifo incase CTS has been dropped.
++ */
++#define MCTRL_TIMEOUT	(250*HZ/1000)
++
++
++extern struct ip3106_port ip3106_ports[];
++
++static inline int serial_in(struct ip3106_port *sport, int offset)
++{
++	return (__raw_readl(sport->port.membase + offset));
++}
++
++static inline void serial_out(struct ip3106_port *sport, int offset, int value)
++{
++	__raw_writel(value, sport->port.membase + offset);
++}
++
++/*
++ * Handle any change of modem status signal since we were last called.
++ */
++static void ip3106_mctrl_check(struct ip3106_port *sport)
++{
++	unsigned int status, changed;
++
++	status = sport->port.ops->get_mctrl(&sport->port);
++	changed = status ^ sport->old_status;
++
++	if (changed == 0)
++		return;
++
++	sport->old_status = status;
++
++	if (changed & TIOCM_RI)
++		sport->port.icount.rng++;
++	if (changed & TIOCM_DSR)
++		sport->port.icount.dsr++;
++	if (changed & TIOCM_CAR)
++		uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
++	if (changed & TIOCM_CTS)
++		uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
++
++	wake_up_interruptible(&sport->port.info->delta_msr_wait);
++}
++
++/*
++ * This is our per-port timeout handler, for checking the
++ * modem status signals.
++ */
++static void ip3106_timeout(unsigned long data)
++{
++	struct ip3106_port *sport = (struct ip3106_port *)data;
++	unsigned long flags;
++
++	if (sport->port.info) {
++		spin_lock_irqsave(&sport->port.lock, flags);
++		ip3106_mctrl_check(sport);
++		spin_unlock_irqrestore(&sport->port.lock, flags);
++
++		mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
++	}
++}
++
++/*
++ * interrupts disabled on entry
++ */
++static void ip3106_stop_tx(struct uart_port *port, unsigned int tty_stop)
++{
++	struct ip3106_port *sport = (struct ip3106_port *)port;
++	u32 ien;
++
++	/* Disable TX intr */
++	ien = serial_in(sport, IP3106_IEN);
++	serial_out(sport, IP3106_IEN, ien & ~IP3106_UART_INT_ALLTX);
++
++	/* Clear all pending TX intr */
++	serial_out(sport, IP3106_ICLR, IP3106_UART_INT_ALLTX);
++}
++
++/*
++ * interrupts may not be disabled on entry
++ */
++static void ip3106_start_tx(struct uart_port *port, unsigned int tty_start)
++{
++	struct ip3106_port *sport = (struct ip3106_port *)port;
++	unsigned long flags;
++	u32 ien;
++
++	spin_lock_irqsave(&sport->port.lock, flags);
++
++	/* Clear all pending TX intr */
++	serial_out(sport, IP3106_ICLR, IP3106_UART_INT_ALLTX);
++
++	/* Enable TX intr */
++	ien = serial_in(sport, IP3106_IEN);
++	serial_out(sport, IP3106_IEN, ien | IP3106_UART_INT_ALLTX);
++
++	spin_unlock_irqrestore(&sport->port.lock, flags);
++}
++
++/*
++ * Interrupts enabled
++ */
++static void ip3106_stop_rx(struct uart_port *port)
++{
++	struct ip3106_port *sport = (struct ip3106_port *)port;
++	u32 ien;
++
++	/* Disable RX intr */
++	ien = serial_in(sport, IP3106_IEN);
++	serial_out(sport, IP3106_IEN, ien & ~IP3106_UART_INT_ALLRX);
++
++	/* Clear all pending RX intr */
++	serial_out(sport, IP3106_ICLR, IP3106_UART_INT_ALLRX);
++}
++
++/*
++ * Set the modem control timer to fire immediately.
++ */
++static void ip3106_enable_ms(struct uart_port *port)
++{
++	struct ip3106_port *sport = (struct ip3106_port *)port;
++
++	mod_timer(&sport->timer, jiffies);
++}
++
++static void
++ip3106_rx_chars(struct ip3106_port *sport, struct pt_regs *regs)
++{
++	struct tty_struct *tty = sport->port.info->tty;
++	unsigned int status, ch, flg, ignored = 0;
++
++	status = FIFO_TO_SM(serial_in(sport, IP3106_FIFO)) |
++		 ISTAT_TO_SM(serial_in(sport, IP3106_ISTAT));
++	while (status & FIFO_TO_SM(IP3106_UART_FIFO_RXFIFO)) {
++		ch = serial_in(sport, IP3106_FIFO);
++
++		if (tty->flip.count >= TTY_FLIPBUF_SIZE)
++			goto ignore_char;
++		sport->port.icount.rx++;
++
++		flg = TTY_NORMAL;
++
++		/*
++		 * note that the error handling code is
++		 * out of the main execution path
++		 */
++		if (status & FIFO_TO_SM(IP3106_UART_FIFO_RXFE |
++					IP3106_UART_FIFO_RXPAR))
++			goto handle_error;
++
++		if (uart_handle_sysrq_char(&sport->port, ch, regs))
++			goto ignore_char;
++
++	error_return:
++		tty_insert_flip_char(tty, ch, flg);
++	ignore_char:
++		serial_out(sport, IP3106_LCR, serial_in(sport, IP3106_LCR) |
++				IP3106_UART_LCR_RX_NEXT);
++		status = FIFO_TO_SM(serial_in(sport, IP3106_FIFO)) |
++			 ISTAT_TO_SM(serial_in(sport, IP3106_ISTAT));
++	}
++ out:
++	tty_flip_buffer_push(tty);
++	return;
++
++ handle_error:
++	if (status & FIFO_TO_SM(IP3106_UART_FIFO_RXPAR))
++		sport->port.icount.parity++;
++	else if (status & FIFO_TO_SM(IP3106_UART_FIFO_RXFE))
++		sport->port.icount.frame++;
++	if (status & ISTAT_TO_SM(IP3106_UART_INT_RXOVRN))
++		sport->port.icount.overrun++;
++
++	if (status & sport->port.ignore_status_mask) {
++		if (++ignored > 100)
++			goto out;
++		goto ignore_char;
++	}
++
++//	status &= sport->port.read_status_mask;
++
++	if (status & FIFO_TO_SM(IP3106_UART_FIFO_RXPAR))
++		flg = TTY_PARITY;
++	else if (status & FIFO_TO_SM(IP3106_UART_FIFO_RXFE))
++		flg = TTY_FRAME;
++
++	if (status & ISTAT_TO_SM(IP3106_UART_INT_RXOVRN)) {
++		/*
++		 * overrun does *not* affect the character
++		 * we read from the FIFO
++		 */
++		tty_insert_flip_char(tty, ch, flg);
++		ch = 0;
++		flg = TTY_OVERRUN;
++	}
++#ifdef SUPPORT_SYSRQ
++	sport->port.sysrq = 0;
++#endif
++	goto error_return;
++}
++
++static void ip3106_tx_chars(struct ip3106_port *sport)
++{
++	struct circ_buf *xmit = &sport->port.info->xmit;
++
++	if (sport->port.x_char) {
++		serial_out(sport, IP3106_FIFO, sport->port.x_char);
++		sport->port.icount.tx++;
++		sport->port.x_char = 0;
++		return;
++	}
++
++	/*
++	 * Check the modem control lines before
++	 * transmitting anything.
++	 */
++	ip3106_mctrl_check(sport);
++
++	if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
++		ip3106_stop_tx(&sport->port, 0);
++		return;
++	}
++
++	/*
++	 * TX while bytes available
++	 */
++	while (((serial_in(sport, IP3106_FIFO) &
++					IP3106_UART_FIFO_TXFIFO) >> 16) < 16) {
++		serial_out(sport, IP3106_FIFO, xmit->buf[xmit->tail]);
++		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
++		sport->port.icount.tx++;
++		if (uart_circ_empty(xmit))
++			break;
++	}
++
++	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
++		uart_write_wakeup(&sport->port);
++
++	if (uart_circ_empty(xmit))
++		ip3106_stop_tx(&sport->port, 0);
++}
++
++static irqreturn_t ip3106_int(int irq, void *dev_id, struct pt_regs *regs)
++{
++	struct ip3106_port *sport = dev_id;
++	unsigned int status;
++
++	spin_lock(&sport->port.lock);
++	/* Get the interrupts */
++	status  = serial_in(sport, IP3106_ISTAT) & serial_in(sport, IP3106_IEN);
++
++	/* RX Receiver Holding Register Overrun */
++	if (status & IP3106_UART_INT_RXOVRN) {
++		sport->port.icount.overrun++;
++		serial_out(sport, IP3106_ICLR, IP3106_UART_INT_RXOVRN);
++	}
++
++	/* RX Frame Error */
++	if (status & IP3106_UART_INT_FRERR) {
++		sport->port.icount.frame++;
++		serial_out(sport, IP3106_ICLR, IP3106_UART_INT_FRERR);
++	}
++
++	/* Break signal received */
++	if (status & IP3106_UART_INT_BREAK) {
++		sport->port.icount.brk++;
++		serial_out(sport, IP3106_ICLR, IP3106_UART_INT_BREAK);
++	}
++
++	/* RX Parity Error */
++	if (status & IP3106_UART_INT_PARITY) {
++		sport->port.icount.parity++;
++		serial_out(sport, IP3106_ICLR, IP3106_UART_INT_PARITY);
++	}
++
++	/* Byte received */
++	if (status & IP3106_UART_INT_RX) {
++		ip3106_rx_chars(sport, regs);
++		serial_out(sport, IP3106_ICLR, IP3106_UART_INT_RX);
++	}
++
++	/* TX holding register empty - transmit a byte */
++	if (status & IP3106_UART_INT_TX) {
++		ip3106_tx_chars(sport);
++		serial_out(sport, IP3106_ICLR, IP3106_UART_INT_TX);
++	}
++
++	/* TX shift register and holding register empty  */
++	if (status & IP3106_UART_INT_EMPTY) {
++		serial_out(sport, IP3106_ICLR, IP3106_UART_INT_EMPTY);
++	}
++
++	/* Receiver time out */
++	if (status & IP3106_UART_INT_RCVTO) {
++		serial_out(sport, IP3106_ICLR, IP3106_UART_INT_RCVTO);
++	}
++	spin_unlock(&sport->port.lock);
++	return IRQ_HANDLED;
++}
++
++/*
++ * Return TIOCSER_TEMT when transmitter is not busy.
++ */
++static unsigned int ip3106_tx_empty(struct uart_port *port)
++{
++	struct ip3106_port *sport = (struct ip3106_port *)port;
++
++	return serial_in(sport, IP3106_FIFO) & IP3106_UART_FIFO_TXFIFO_STA ? 0 : TIOCSER_TEMT;
++}
++
++static unsigned int ip3106_get_mctrl(struct uart_port *port)
++{
++	struct ip3106_port *sport = (struct ip3106_port *)port;
++	unsigned int mctrl = TIOCM_DSR;
++	unsigned int msr;
++
++	/* REVISIT */
++
++	msr = serial_in(sport, IP3106_MCR);
++
++	mctrl |= msr & IP3106_UART_MCR_CTS ? TIOCM_CTS : 0;
++	mctrl |= msr & IP3106_UART_MCR_DCD ? TIOCM_CAR : 0;
++
++	return mctrl;
++}
++
++static void ip3106_set_mctrl(struct uart_port *port, unsigned int mctrl)
++{
++#if	0	/* FIXME */
++	struct ip3106_port *sport = (struct ip3106_port *)port;
++	unsigned int msr;
++#endif
++}
++
++/*
++ * Interrupts always disabled.
++ */
++static void ip3106_break_ctl(struct uart_port *port, int break_state)
++{
++	struct ip3106_port *sport = (struct ip3106_port *)port;
++	unsigned long flags;
++	unsigned int lcr;
++
++	spin_lock_irqsave(&sport->port.lock, flags);
++	lcr = serial_in(sport, IP3106_LCR);
++	if (break_state == -1)
++		lcr |= IP3106_UART_LCR_TXBREAK;
++	else
++		lcr &= ~IP3106_UART_LCR_TXBREAK;
++	serial_out(sport, IP3106_LCR, lcr);
++	spin_unlock_irqrestore(&sport->port.lock, flags);
++}
++
++static int ip3106_startup(struct uart_port *port)
++{
++	struct ip3106_port *sport = (struct ip3106_port *)port;
++	int retval;
++
++	/*
++	 * Allocate the IRQ
++	 */
++	retval = request_irq(sport->port.irq, ip3106_int, 0,
++			     "ip3106-uart", sport);
++	if (retval)
++		return retval;
++
++	/*
++	 * Finally, clear and enable interrupts
++	 */
++
++	serial_out(sport, IP3106_ICLR, IP3106_UART_INT_ALLRX |
++			     IP3106_UART_INT_ALLTX);
++
++	serial_out(sport, IP3106_IEN, serial_in(sport, IP3106_IEN) |
++			    IP3106_UART_INT_ALLRX |
++			    IP3106_UART_INT_ALLTX);
++
++	/*
++	 * Enable modem status interrupts
++	 */
++	spin_lock_irq(&sport->port.lock);
++	ip3106_enable_ms(&sport->port);
++	spin_unlock_irq(&sport->port.lock);
++
++	return 0;
++}
++
++static void ip3106_shutdown(struct uart_port *port)
++{
++	struct ip3106_port *sport = (struct ip3106_port *)port;
++
++	/*
++	 * Stop our timer.
++	 */
++	del_timer_sync(&sport->timer);
++
++	/*
++	 * Disable all interrupts, port and break condition.
++	 */
++	serial_out(sport, IP3106_IEN, 0);
++
++	/*
++	 * Reset the Tx and Rx FIFOS
++	 */
++	serial_out(sport, IP3106_LCR, serial_in(sport, IP3106_LCR) |
++			    IP3106_UART_LCR_TX_RST |
++			    IP3106_UART_LCR_RX_RST);
++
++	/*
++	 * Clear all interrupts
++	 */
++	serial_out(sport, IP3106_ICLR, IP3106_UART_INT_ALLRX |
++			     IP3106_UART_INT_ALLTX);
++
++	/*
++	 * Free the interrupt
++	 */
++	free_irq(sport->port.irq, sport);
++}
++
++static void
++ip3106_set_termios(struct uart_port *port, struct termios *termios,
++		   struct termios *old)
++{
++	struct ip3106_port *sport = (struct ip3106_port *)port;
++	unsigned long flags;
++	unsigned int lcr_fcr, old_ien, baud, quot;
++	unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
++
++	/*
++	 * We only support CS7 and CS8.
++	 */
++	while ((termios->c_cflag & CSIZE) != CS7 &&
++	       (termios->c_cflag & CSIZE) != CS8) {
++		termios->c_cflag &= ~CSIZE;
++		termios->c_cflag |= old_csize;
++		old_csize = CS8;
++	}
++
++	if ((termios->c_cflag & CSIZE) == CS8)
++		lcr_fcr = IP3106_UART_LCR_8BIT;
++	else
++		lcr_fcr = 0;
++
++	if (termios->c_cflag & CSTOPB)
++		lcr_fcr |= IP3106_UART_LCR_2STOPB;
++	if (termios->c_cflag & PARENB) {
++		lcr_fcr |= IP3106_UART_LCR_PAREN;
++		if (!(termios->c_cflag & PARODD))
++			lcr_fcr |= IP3106_UART_LCR_PAREVN;
++	}
++
++	/*
++	 * Ask the core to calculate the divisor for us.
++	 */
++	baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
++	quot = uart_get_divisor(port, baud);
++
++	spin_lock_irqsave(&sport->port.lock, flags);
++
++#if	0	/* REVISIT */
++	sport->port.read_status_mask &= UTSR0_TO_SM(UTSR0_TFS);
++	sport->port.read_status_mask |= UTSR1_TO_SM(UTSR1_ROR);
++	if (termios->c_iflag & INPCK)
++		sport->port.read_status_mask |=
++				UTSR1_TO_SM(UTSR1_FRE | UTSR1_PRE);
++	if (termios->c_iflag & (BRKINT | PARMRK))
++		sport->port.read_status_mask |=
++				UTSR0_TO_SM(UTSR0_RBB | UTSR0_REB);
++
++	/*
++	 * Characters to ignore
++	 */
++	sport->port.ignore_status_mask = 0;
++	if (termios->c_iflag & IGNPAR)
++		sport->port.ignore_status_mask |=
++				UTSR1_TO_SM(UTSR1_FRE | UTSR1_PRE);
++	if (termios->c_iflag & IGNBRK) {
++		sport->port.ignore_status_mask |=
++				UTSR0_TO_SM(UTSR0_RBB | UTSR0_REB);
++		/*
++		 * If we're ignoring parity and break indicators,
++		 * ignore overruns too (for real raw support).
++		 */
++		if (termios->c_iflag & IGNPAR)
++			sport->port.ignore_status_mask |=
++				UTSR1_TO_SM(UTSR1_ROR);
++	}
++#endif
++
++	del_timer_sync(&sport->timer);
++
++	/*
++	 * Update the per-port timeout.
++	 */
++	uart_update_timeout(port, termios->c_cflag, baud);
++
++	/*
++	 * disable interrupts and drain transmitter
++	 */
++	old_ien = serial_in(sport, IP3106_IEN);
++	serial_out(sport, IP3106_IEN, old_ien & ~(IP3106_UART_INT_ALLTX |
++					IP3106_UART_INT_ALLRX));
++
++	while (serial_in(sport, IP3106_FIFO) & IP3106_UART_FIFO_TXFIFO_STA)
++		barrier();
++
++	/* then, disable everything */
++	serial_out(sport, IP3106_IEN, 0);
++
++	/* Reset the Rx and Tx FIFOs too */
++	lcr_fcr |= IP3106_UART_LCR_TX_RST;
++	lcr_fcr |= IP3106_UART_LCR_RX_RST;
++
++	/* set the parity, stop bits and data size */
++	serial_out(sport, IP3106_LCR, lcr_fcr);
++
++	/* set the baud rate */
++	quot -= 1;
++	serial_out(sport, IP3106_BAUD, quot);
++
++	serial_out(sport, IP3106_ICLR, -1);
++
++	serial_out(sport, IP3106_IEN, old_ien);
++
++	if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
++		ip3106_enable_ms(&sport->port);
++
++	spin_unlock_irqrestore(&sport->port.lock, flags);
++}
++
++static const char *ip3106_type(struct uart_port *port)
++{
++	struct ip3106_port *sport = (struct ip3106_port *)port;
++
++	return sport->port.type == PORT_IP3106 ? "IP3106" : NULL;
++}
++
++/*
++ * Release the memory region(s) being used by 'port'.
++ */
++static void ip3106_release_port(struct uart_port *port)
++{
++	struct ip3106_port *sport = (struct ip3106_port *)port;
++
++	release_mem_region(sport->port.mapbase, UART_PORT_SIZE);
++}
++
++/*
++ * Request the memory region(s) being used by 'port'.
++ */
++static int ip3106_request_port(struct uart_port *port)
++{
++	struct ip3106_port *sport = (struct ip3106_port *)port;
++
++	return request_mem_region(sport->port.mapbase, UART_PORT_SIZE,
++			"ip3106-uart") != NULL ? 0 : -EBUSY;
++}
++
++/*
++ * Configure/autoconfigure the port.
++ */
++static void ip3106_config_port(struct uart_port *port, int flags)
++{
++	struct ip3106_port *sport = (struct ip3106_port *)port;
++
++	if (flags & UART_CONFIG_TYPE &&
++	    ip3106_request_port(&sport->port) == 0)
++		sport->port.type = PORT_IP3106;
++}
++
++/*
++ * Verify the new serial_struct (for TIOCSSERIAL).
++ * The only change we allow are to the flags and type, and
++ * even then only between PORT_IP3106 and PORT_UNKNOWN
++ */
++static int
++ip3106_verify_port(struct uart_port *port, struct serial_struct *ser)
++{
++	struct ip3106_port *sport = (struct ip3106_port *)port;
++	int ret = 0;
++
++	if (ser->type != PORT_UNKNOWN && ser->type != PORT_IP3106)
++		ret = -EINVAL;
++	if (sport->port.irq != ser->irq)
++		ret = -EINVAL;
++	if (ser->io_type != SERIAL_IO_MEM)
++		ret = -EINVAL;
++	if (sport->port.uartclk / 16 != ser->baud_base)
++		ret = -EINVAL;
++	if ((void *)sport->port.mapbase != ser->iomem_base)
++		ret = -EINVAL;
++	if (sport->port.iobase != ser->port)
++		ret = -EINVAL;
++	if (ser->hub6 != 0)
++		ret = -EINVAL;
++	return ret;
++}
++
++struct uart_ops ip3106_pops = {
++	.tx_empty	= ip3106_tx_empty,
++	.set_mctrl	= ip3106_set_mctrl,
++	.get_mctrl	= ip3106_get_mctrl,
++	.stop_tx	= ip3106_stop_tx,
++	.start_tx	= ip3106_start_tx,
++	.stop_rx	= ip3106_stop_rx,
++	.enable_ms	= ip3106_enable_ms,
++	.break_ctl	= ip3106_break_ctl,
++	.startup	= ip3106_startup,
++	.shutdown	= ip3106_shutdown,
++	.set_termios	= ip3106_set_termios,
++	.type		= ip3106_type,
++	.release_port	= ip3106_release_port,
++	.request_port	= ip3106_request_port,
++	.config_port	= ip3106_config_port,
++	.verify_port	= ip3106_verify_port,
++};
++
++
++/*
++ * Setup the IP3106 serial ports.
++ *
++ * Note also that we support "console=ttySx" where "x" is either 0 or 1.
++ */
++static void __init ip3106_init_ports(void)
++{
++	static int first = 1;
++	int i;
++
++	if (!first)
++		return;
++	first = 0;
++
++	for (i = 0; i < NR_PORTS; i++) {
++		init_timer(&ip3106_ports[i].timer);
++		ip3106_ports[i].timer.function = ip3106_timeout;
++		ip3106_ports[i].timer.data     = (unsigned long)&ip3106_ports[i];
++	}
++}
++
++#ifdef CONFIG_SERIAL_IP3106_CONSOLE
++
++/*
++ * Interrupts are disabled on entering
++ */
++static void
++ip3106_console_write(struct console *co, const char *s, unsigned int count)
++{
++	struct ip3106_port *sport = &ip3106_ports[co->index];
++	unsigned int old_ien, status, i;
++
++	/*
++	 *	First, save IEN and then disable interrupts
++	 */
++	old_ien = serial_in(sport, IP3106_IEN);
++	serial_out(sport, IP3106_IEN, old_ien & ~(IP3106_UART_INT_ALLTX |
++					IP3106_UART_INT_ALLRX));
++
++	/*
++	 *	Now, do each character
++	 */
++	for (i = 0; i < count; i++) {
++		do {
++			/* Wait for UART_TX register to empty */
++			status = serial_in(sport, IP3106_FIFO);
++		} while (status & IP3106_UART_FIFO_TXFIFO);
++		serial_out(sport, IP3106_FIFO, s[i]);
++		if (s[i] == '\n') {
++			do {
++				status = serial_in(sport, IP3106_FIFO);
++			} while (status & IP3106_UART_FIFO_TXFIFO);
++			serial_out(sport, IP3106_FIFO, '\r');
++		}
++	}
++
++	/*
++	 *	Finally, wait for transmitter to become empty
++	 *	and restore IEN
++	 */
++	do {
++		/* Wait for UART_TX register to empty */
++		status = serial_in(sport, IP3106_FIFO);
++	} while (status & IP3106_UART_FIFO_TXFIFO);
++
++	/* Clear TX and EMPTY interrupt */
++	serial_out(sport, IP3106_ICLR, IP3106_UART_INT_TX |
++			     IP3106_UART_INT_EMPTY);
++
++	serial_out(sport, IP3106_IEN, old_ien);
++}
++
++static int __init
++ip3106_console_setup(struct console *co, char *options)
++{
++	struct ip3106_port *sport;
++	int baud = 38400;
++	int bits = 8;
++	int parity = 'n';
++	int flow = 'n';
++
++	/*
++	 * Check whether an invalid uart number has been specified, and
++	 * if so, search for the first available port that does have
++	 * console support.
++	 */
++	if (co->index == -1 || co->index >= NR_PORTS)
++		co->index = 0;
++	sport = &ip3106_ports[co->index];
++
++	if (options)
++		uart_parse_options(options, &baud, &parity, &bits, &flow);
++
++	return uart_set_options(&sport->port, co, baud, parity, bits, flow);
++}
++
++extern struct uart_driver ip3106_reg;
++static struct console ip3106_console = {
++	.name		= "ttyS",
++	.write		= ip3106_console_write,
++	.device		= uart_console_device,
++	.setup		= ip3106_console_setup,
++	.flags		= CON_PRINTBUFFER,
++	.index		= -1,
++	.data		= &ip3106_reg,
++};
++
++static int __init ip3106_rs_console_init(void)
++{
++	ip3106_init_ports();
++	register_console(&ip3106_console);
++	return 0;
++}
++console_initcall(ip3106_rs_console_init);
++
++#define IP3106_CONSOLE	&ip3106_console
++#else
++#define IP3106_CONSOLE	NULL
++#endif
++
++static struct uart_driver ip3106_reg = {
++	.owner			= THIS_MODULE,
++	.driver_name		= "ttyS",
++	.dev_name		= "ttyS",
++	.devfs_name		= "tts/",
++	.major			= SERIAL_IP3106_MAJOR,
++	.minor			= MINOR_START,
++	.nr			= NR_PORTS,
++	.cons			= IP3106_CONSOLE,
++};
++
++static int ip3106_serial_suspend(struct device *_dev, u32 state, u32 level)
++{
++	struct ip3106_port *sport = dev_get_drvdata(_dev);
++
++	if (sport && level == SUSPEND_DISABLE)
++		uart_suspend_port(&ip3106_reg, &sport->port);
++
++	return 0;
++}
++
++static int ip3106_serial_resume(struct device *_dev, u32 level)
++{
++	struct ip3106_port *sport = dev_get_drvdata(_dev);
++
++	if (sport && level == RESUME_ENABLE)
++		uart_resume_port(&ip3106_reg, &sport->port);
++
++	return 0;
++}
++
++static int ip3106_serial_probe(struct device *_dev)
++{
++	struct platform_device *dev = to_platform_device(_dev);
++	struct resource *res = dev->resource;
++	int i;
++
++	for (i = 0; i < dev->num_resources; i++, res++) {
++		if (!(res->flags & IORESOURCE_MEM))
++			continue;
++
++		for (i = 0; i < NR_PORTS; i++) {
++			if (ip3106_ports[i].port.mapbase != res->start)
++				continue;
++
++			ip3106_ports[i].port.dev = _dev;
++			uart_add_one_port(&ip3106_reg, &ip3106_ports[i].port);
++			dev_set_drvdata(_dev, &ip3106_ports[i]);
++			break;
++		}
++	}
++
++	return 0;
++}
++
++static int ip3106_serial_remove(struct device *_dev)
++{
++	struct ip3106_port *sport = dev_get_drvdata(_dev);
++
++	dev_set_drvdata(_dev, NULL);
++
++	if (sport)
++		uart_remove_one_port(&ip3106_reg, &sport->port);
++
++	return 0;
++}
++
++static struct device_driver ip3106_serial_driver = {
++	.name		= "ip3106-uart",
++	.bus		= &platform_bus_type,
++	.probe		= ip3106_serial_probe,
++	.remove		= ip3106_serial_remove,
++	.suspend	= ip3106_serial_suspend,
++	.resume		= ip3106_serial_resume,
++};
++
++static int __init ip3106_serial_init(void)
++{
++	int ret;
++
++	printk(KERN_INFO "Serial: IP3106 driver $Revision: 1.2 $\n");
++
++	ip3106_init_ports();
++
++	ret = uart_register_driver(&ip3106_reg);
++	if (ret == 0) {
++		ret = driver_register(&ip3106_serial_driver);
++		if (ret)
++			uart_unregister_driver(&ip3106_reg);
++	}
++	return ret;
++}
++
++static void __exit ip3106_serial_exit(void)
++{
++	driver_unregister(&ip3106_serial_driver);
++	uart_unregister_driver(&ip3106_reg);
++}
++
++module_init(ip3106_serial_init);
++module_exit(ip3106_serial_exit);
++
++MODULE_AUTHOR("Embedded Alley Solutions, Inc.");
++MODULE_DESCRIPTION("IP3106 generic serial port driver");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS_CHARDEV_MAJOR(SERIAL_IP3106_MAJOR);
+diff -Naur linux-2.6.17.orig/drivers/serial/Kconfig linux-2.6.17/drivers/serial/Kconfig
+--- linux-2.6.17.orig/drivers/serial/Kconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/drivers/serial/Kconfig	2006-06-19 18:16:13.000000000 -0700
+@@ -647,6 +647,25 @@
+ 	depends on SERIAL_SH_SCI=y
+ 	select SERIAL_CORE_CONSOLE
+ 
++config SERIAL_IP3106
++	bool "Enable IP3106 UART Support (Philips PNX 8xx0 SoCs)"
++	depends on MIPS && (SOC_PNX8550 || SOC_PNX8330)
++	select SERIAL_CORE
++	help
++	  If you have a Philips SoC with an IP 3106 UART in it, such as
++	  the PNX8550 or PNX8330 (MIPS based) and you want to use
++	  serial ports, say Y.  Otherwise, say N.
++
++config SERIAL_IP3106_CONSOLE
++	bool "Enable PNX8XX0 serial console"
++	depends on SERIAL_IP3106
++	select SERIAL_CORE_CONSOLE
++	help
++	  If you have a Philips SoC with an IP 3106 UART in it, such as
++	  the PNX8550 or PNX8330 (MIPS based) and you want to use
++	  a serial console, say Y.
++	  Otherwise, say N.
++
+ config SERIAL_CORE
+ 	tristate
+ 
+diff -Naur linux-2.6.17.orig/drivers/serial/Makefile linux-2.6.17/drivers/serial/Makefile
+--- linux-2.6.17.orig/drivers/serial/Makefile	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/drivers/serial/Makefile	2006-06-19 18:16:13.000000000 -0700
+@@ -39,6 +39,7 @@
+ obj-$(CONFIG_V850E_UART) += v850e_uart.o
+ obj-$(CONFIG_SERIAL_PMACZILOG) += pmac_zilog.o
+ obj-$(CONFIG_SERIAL_LH7A40X) += serial_lh7a40x.o
++obj-$(CONFIG_SERIAL_IP3106) += ip3106_uart.o
+ obj-$(CONFIG_SERIAL_DZ) += dz.o
+ obj-$(CONFIG_SERIAL_SH_SCI) += sh-sci.o
+ obj-$(CONFIG_SERIAL_SGI_L1_CONSOLE) += sn_console.o
+diff -Naur linux-2.6.17.orig/drivers/usb/gadget/net2280.c linux-2.6.17/drivers/usb/gadget/net2280.c
+--- linux-2.6.17.orig/drivers/usb/gadget/net2280.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/drivers/usb/gadget/net2280.c	2006-06-19 18:16:13.000000000 -0700
+@@ -468,7 +468,8 @@
+ #elif	defined(CONFIG_PPC) && !defined(CONFIG_NOT_COHERENT_CACHE)
+ #define USE_KMALLOC
+ 
+-#elif	defined(CONFIG_MIPS) && !defined(CONFIG_DMA_NONCOHERENT)
++#elif	defined(CONFIG_MIPS) && \
++	(defined(CONFIG_DMA_COHERENT) || defined(CONFIG_DMA_IP27))
+ #define USE_KMALLOC
+ 
+ /* FIXME there are other cases, including an x86-64 one ...  */
+diff -Naur linux-2.6.17.orig/drivers/usb/host/ohci-hcd.c linux-2.6.17/drivers/usb/host/ohci-hcd.c
+--- linux-2.6.17.orig/drivers/usb/host/ohci-hcd.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/drivers/usb/host/ohci-hcd.c	2006-06-19 18:16:13.000000000 -0700
+@@ -906,6 +906,10 @@
+ #include "ohci-au1xxx.c"
+ #endif
+ 
++#ifdef CONFIG_PNX8550
++#include "ohci-pnx8550.c"
++#endif
++
+ #ifdef CONFIG_USB_OHCI_HCD_PPC_SOC
+ #include "ohci-ppc-soc.c"
+ #endif
+diff -Naur linux-2.6.17.orig/drivers/usb/host/ohci-pnx8550.c linux-2.6.17/drivers/usb/host/ohci-pnx8550.c
+--- linux-2.6.17.orig/drivers/usb/host/ohci-pnx8550.c	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/drivers/usb/host/ohci-pnx8550.c	2006-06-19 18:16:13.000000000 -0700
+@@ -0,0 +1,277 @@
++/*
++ * OHCI HCD (Host Controller Driver) for USB.
++ *
++ * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
++ * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
++ * (C) Copyright 2002 Hewlett-Packard Company
++ * (C) Copyright 2005 Embedded Alley Solutions, Inc.
++ *
++ * Bus Glue for PNX8550
++ *
++ * Written by Christopher Hoover <ch@hpl.hp.com>
++ * Based on fragments of previous driver by Russell King et al.
++ *
++ * Modified for LH7A404 from ohci-sa1111.c
++ *  by Durgesh Pattamatta <pattamattad@sharpsec.com>
++ *
++ * Modified for pxa27x from ohci-lh7a404.c
++ *  by Nick Bane <nick@cecomputing.co.uk> 26-8-2004
++ *
++ * Modified for PNX8550 from ohci-pxa27x.c
++ *  by Embedded Alley Solutions, Inc. 
++ *
++ * This file is licenced under the GPL.
++ */
++
++#include <linux/device.h>
++#include <asm/mach-pnx8550/usb.h>
++#include <asm/mach-pnx8550/int.h>
++#include <asm/mach-pnx8550/pci.h>
++
++#ifndef CONFIG_PNX8550
++#error "This file is PNX8550 bus glue.  CONFIG_PNX8550 must be defined."
++#endif
++
++extern int usb_disabled(void);
++
++/*-------------------------------------------------------------------------*/
++
++static void pnx8550_start_hc(struct platform_device *dev)
++{
++	/*
++	 * Set register CLK48CTL to enable and 48MHz
++	 */
++	outl(0x00000003, PCI_BASE | 0x0004770c);
++
++	/*
++	 * Set register CLK12CTL to enable and 48MHz
++	 */
++	outl(0x00000003, PCI_BASE | 0x00047710);
++
++	udelay(100);
++}
++
++static void pnx8550_stop_hc(struct platform_device *dev)
++{
++	udelay(10);
++}
++
++
++/*-------------------------------------------------------------------------*/
++
++/* configure so an HC device and id are always provided */
++/* always called with process context; sleeping is OK */
++
++
++/**
++ * usb_hcd_pnx8550_probe - initialize pnx8550-based HCDs
++ * Context: !in_interrupt()
++ *
++ * Allocates basic resources for this USB host controller, and
++ * then invokes the start() method for the HCD associated with it
++ * through the hotplug entry's driver_data.
++ *
++ */
++int usb_hcd_pnx8550_probe (const struct hc_driver *driver,
++			  struct platform_device *dev)
++{
++	int retval;
++	struct usb_hcd *hcd;
++
++	if (dev->resource[1].flags != IORESOURCE_IRQ) {
++		pr_debug ("resource[1] is not IORESOURCE_IRQ");
++		return -ENOMEM;
++	}
++
++	hcd = usb_create_hcd (driver, &dev->dev, "pnx8550");
++	if (!hcd)
++		return -ENOMEM;
++	hcd->rsrc_start = dev->resource[0].start;
++	hcd->rsrc_len = dev->resource[0].end - dev->resource[0].start + 1;
++
++	if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) {
++		pr_debug("request_mem_region failed");
++		retval = -EBUSY;
++		goto err1;
++	}
++
++	hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
++	if (!hcd->regs) {
++		pr_debug("ioremap failed");
++		retval = -ENOMEM;
++		goto err2;
++	}
++
++	pnx8550_start_hc(dev);
++
++	ohci_hcd_init(hcd_to_ohci(hcd));
++
++	retval = usb_add_hcd(hcd, dev->resource[1].start, SA_INTERRUPT);
++	if (retval == 0)
++		return retval;
++
++	pnx8550_stop_hc(dev);
++	iounmap(hcd->regs);
++ err2:
++	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
++ err1:
++	usb_put_hcd(hcd);
++	return retval;
++}
++
++
++/* may be called without controller electrically present */
++/* may be called with controller, bus, and devices active */
++
++/**
++ * usb_hcd_pnx8550_remove - shutdown processing for pnx8550-based HCDs
++ * @dev: USB Host Controller being removed
++ * Context: !in_interrupt()
++ *
++ * Reverses the effect of usb_hcd_pnx8550_probe(), first invoking
++ * the HCD's stop() method.  It is always called from a thread
++ * context, normally "rmmod", "apmd", or something similar.
++ *
++ */
++void usb_hcd_pnx8550_remove (struct usb_hcd *hcd, struct platform_device *dev)
++{
++	usb_remove_hcd(hcd);
++	pnx8550_stop_hc(dev);
++	iounmap(hcd->regs);
++	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
++	usb_put_hcd(hcd);
++}
++
++/*-------------------------------------------------------------------------*/
++
++static int __devinit
++ohci_pnx8550_start (struct usb_hcd *hcd)
++{
++	struct ohci_hcd	*ohci = hcd_to_ohci (hcd);
++	int		ret;
++
++	ohci_dbg (ohci, "ohci_pnx8550_start, ohci:%p", ohci);
++
++	if ((ret = ohci_init(ohci)) < 0)
++		return ret;
++
++	if ((ret = ohci_run (ohci)) < 0) {
++		err ("can't start %s", hcd->self.bus_name);
++		ohci_stop (hcd);
++		return ret;
++	}
++
++	return 0;
++}
++
++/*-------------------------------------------------------------------------*/
++
++static const struct hc_driver ohci_pnx8550_hc_driver = {
++	.description =		hcd_name,
++	.product_desc =		"PNX8550 OHCI",
++	.hcd_priv_size =	sizeof(struct ohci_hcd),
++
++	/*
++	 * generic hardware linkage
++	 */
++	.irq =			ohci_irq,
++	.flags =		HCD_USB11 | HCD_MEMORY,
++
++	/*
++	 * basic lifecycle operations
++	 */
++	.start =		ohci_pnx8550_start,
++	.stop =			ohci_stop,
++
++	/*
++	 * managing i/o requests and associated device resources
++	 */
++	.urb_enqueue =		ohci_urb_enqueue,
++	.urb_dequeue =		ohci_urb_dequeue,
++	.endpoint_disable =	ohci_endpoint_disable,
++
++	/*
++	 * scheduling support
++	 */
++	.get_frame_number =	ohci_get_frame,
++
++	/*
++	 * root hub support
++	 */
++	.hub_status_data =	ohci_hub_status_data,
++	.hub_control =		ohci_hub_control,
++#ifdef  CONFIG_USB_SUSPEND
++	.hub_suspend =		ohci_hub_suspend,
++	.hub_resume =		ohci_hub_resume,
++#endif
++};
++
++/*-------------------------------------------------------------------------*/
++
++static int ohci_hcd_pnx8550_drv_probe(struct device *dev)
++{
++	struct platform_device *pdev = to_platform_device(dev);
++	int ret;
++
++	pr_debug ("In ohci_hcd_pnx8550_drv_probe");
++
++	if (usb_disabled())
++		return -ENODEV;
++
++	ret = usb_hcd_pnx8550_probe(&ohci_pnx8550_hc_driver, pdev);
++	return ret;
++}
++
++static int ohci_hcd_pnx8550_drv_remove(struct device *dev)
++{
++	struct platform_device *pdev = to_platform_device(dev);
++	struct usb_hcd *hcd = dev_get_drvdata(dev);
++
++	usb_hcd_pnx8550_remove(hcd, pdev);
++	return 0;
++}
++
++static int ohci_hcd_pnx8550_drv_suspend(struct device *dev, u32 state, u32 level)
++{
++//	struct platform_device *pdev = to_platform_device(dev);
++//	struct usb_hcd *hcd = dev_get_drvdata(dev);
++	printk("%s: not implemented yet\n", __FUNCTION__);
++
++	return 0;
++}
++
++static int ohci_hcd_pnx8550_drv_resume(struct device *dev, u32 state)
++{
++//	struct platform_device *pdev = to_platform_device(dev);
++//	struct usb_hcd *hcd = dev_get_drvdata(dev);
++	printk("%s: not implemented yet\n", __FUNCTION__);
++
++	return 0;
++}
++
++
++static struct device_driver ohci_hcd_pnx8550_driver = {
++	.name		= "pnx8550-ohci",
++	.bus		= &platform_bus_type,
++	.probe		= ohci_hcd_pnx8550_drv_probe,
++	.remove		= ohci_hcd_pnx8550_drv_remove,
++	.suspend	= ohci_hcd_pnx8550_drv_suspend, 
++	.resume		= ohci_hcd_pnx8550_drv_resume, 
++};
++
++static int __init ohci_hcd_pnx8550_init (void)
++{
++	pr_debug (DRIVER_INFO " (pnx8550)");
++	pr_debug ("block sizes: ed %d td %d\n",
++		sizeof (struct ed), sizeof (struct td));
++
++	return driver_register(&ohci_hcd_pnx8550_driver);
++}
++
++static void __exit ohci_hcd_pnx8550_cleanup (void)
++{
++	driver_unregister(&ohci_hcd_pnx8550_driver);
++}
++
++module_init (ohci_hcd_pnx8550_init);
++module_exit (ohci_hcd_pnx8550_cleanup);
+diff -Naur linux-2.6.17.orig/drivers/video/au1100fb.c linux-2.6.17/drivers/video/au1100fb.c
+--- linux-2.6.17.orig/drivers/video/au1100fb.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/drivers/video/au1100fb.c	2006-06-19 18:16:13.000000000 -0700
+@@ -38,6 +38,7 @@
+  *  with this program; if not, write  to the Free Software Foundation, Inc.,
+  *  675 Mass Ave, Cambridge, MA 02139, USA.
+  */
++
+ #include <linux/config.h>
+ #include <linux/module.h>
+ #include <linux/kernel.h>
+diff -Naur linux-2.6.17.orig/drivers/video/Kconfig linux-2.6.17/drivers/video/Kconfig
+--- linux-2.6.17.orig/drivers/video/Kconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/drivers/video/Kconfig	2006-06-19 18:16:13.000000000 -0700
+@@ -1142,6 +1142,17 @@
+ 	  Please read the <file:Documentation/fb/README-sstfb.txt> for supported
+ 	  options and other important info  support.
+ 
++config FB_SMIVGX
++	tristate "Silicon Motion VoyagerGX support"
++	depends on FB && PCI && (MIPS || EXPERIMENTAL)
++	select FB_CFB_FILLRECT
++	select FB_CFB_COPYAREA
++	select FB_CFB_IMAGEBLIT
++	---help---
++	  This drivers supports SMI VoyagerGX 501 based PCI boards
++	  The default settings drive both a CRT and LCD.  The CRT
++	  can be turned off by passing in the no_crt option
++
+ config FB_CYBLA
+ 	tristate "Cyberblade/i1 support"
+ 	depends on FB && PCI && X86_32 && !64BIT
+@@ -1206,7 +1217,25 @@
+ 
+ config FB_AU1100
+ 	bool "Au1100 LCD Driver"
+-	depends on (FB = y) && EXPERIMENTAL && PCI && MIPS && MIPS_PB1100=y
++	depends on FB && MIPS && SOC_AU1100
++	select FB_CFB_FILLRECT
++	select FB_CFB_COPYAREA
++	select FB_CFB_IMAGEBLIT
++	help
++	  This is the framebuffer driver for the AMD Au1100 SOC.  It can drive
++	  various panels and CRTs by passing in kernel cmd line option
++	  au1100fb:panel=<name>.
++
++config FB_AU1200
++	bool "Au1200 LCD Driver"
++	depends on FB && MIPS && SOC_AU1200
++	select FB_CFB_FILLRECT
++	select FB_CFB_COPYAREA
++	select FB_CFB_IMAGEBLIT
++	help
++	  This is the framebuffer driver for the AMD Au1200 SOC.  It can drive
++	  various panels and CRTs by passing in kernel cmd line option
++	  au1200fb:panel=<name>.
+ 
+ config FB_AU1200
+ 	bool "Au1200 LCD Driver"
+@@ -1322,8 +1351,8 @@
+  	select FB_CFB_IMAGEBLIT
+ 	help
+ 	  Support for the PMAGB-B TURBOchannel framebuffer card used mainly
+-	  in the MIPS-based DECstation series. The card is currently only
+-	  supported in 1280x1024x8 mode.
++	  in the MIPS-based DECstation series. The card is currently only 
++	  supported in 1280x1024x8 mode.  
+ 
+ config FB_MAXINE
+ 	bool "Maxine (Personal DECstation) onboard framebuffer support"
+diff -Naur linux-2.6.17.orig/drivers/video/Makefile linux-2.6.17/drivers/video/Makefile
+--- linux-2.6.17.orig/drivers/video/Makefile	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/drivers/video/Makefile	2006-06-19 18:16:13.000000000 -0700
+@@ -93,6 +93,7 @@
+ obj-$(CONFIG_FB_TX3912)		  += tx3912fb.o
+ obj-$(CONFIG_FB_S1D13XXX)	  += s1d13xxxfb.o
+ obj-$(CONFIG_FB_IMX)              += imxfb.o
++obj-$(CONFIG_FB_SMIVGX)		  += smivgxfb.o
+ obj-$(CONFIG_FB_S3C2410)	  += s3c2410fb.o
+ 
+ # Platform or fallback drivers go here
+diff -Naur linux-2.6.17.orig/drivers/video/smivgxfb.c linux-2.6.17/drivers/video/smivgxfb.c
+--- linux-2.6.17.orig/drivers/video/smivgxfb.c	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/drivers/video/smivgxfb.c	2006-06-19 18:16:13.000000000 -0700
+@@ -0,0 +1,387 @@
++/***************************************************************************
++ *  Silicon Motion VoyagerGX framebuffer driver
++ *
++ * 	ported to 2.6 by Embedded Alley Solutions, Inc
++ * 	Copyright (C) 2005 Embedded Alley Solutions, Inc
++ *
++ * 		based on
++    copyright            : (C) 2001 by Szu-Tao Huang
++    email                : johuang@siliconmotion.com
++    Updated to SM501 by Eric.Devolder@amd.com and dan@embeddededge.com
++    for the AMD Mirage Portable Tablet.  20 Oct 2003
++ ***************************************************************************/
++
++/***************************************************************************
++ *                                                                         *
++ *   This program is free software; you can redistribute it and/or modify  *
++ *   it under the terms of the GNU General Public License as published by  *
++ *   the Free Software Foundation; either version 2 of the License, or     *
++ *   (at your option) any later version.                                   *
++ *                                                                         *
++ ***************************************************************************/
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/errno.h>
++#include <linux/string.h>
++#include <linux/mm.h>
++#include <linux/tty.h>
++#include <linux/slab.h>
++#include <linux/delay.h>
++#include <linux/fb.h>
++#include <linux/pci.h>
++#include <linux/init.h>
++
++#include <asm/io.h>
++#include <asm/irq.h>
++#include <asm/pgtable.h>
++#include <asm/system.h>
++#include <asm/uaccess.h>
++
++static char __iomem *SMIRegs;	// point to virtual Memory Map IO starting address
++static char __iomem *SMILFB;	// point to virtual video memory starting address
++
++static struct fb_fix_screeninfo smifb_fix __devinitdata = {
++	.id =		"smivgx",
++	.type =		FB_TYPE_PACKED_PIXELS,
++	.visual =	FB_VISUAL_TRUECOLOR,
++	.ywrapstep = 	0,
++	.line_length	= 1024 * 2, /* (bbp * xres)/8 */
++	.accel =	FB_ACCEL_NONE,
++};
++
++static struct fb_var_screeninfo smifb_var __devinitdata = {
++	.xres           = 1024,
++	.yres           = 768,
++	.xres_virtual   = 1024,
++	.yres_virtual   = 768,
++	.bits_per_pixel = 16,
++	.red            = { 11, 5, 0 },
++	.green          = {  5, 6, 0 },
++	.blue           = {  0, 5, 0 },
++	.activate       = FB_ACTIVATE_NOW,
++	.height         = -1,
++	.width          = -1,
++	.vmode          = FB_VMODE_NONINTERLACED,
++};
++
++
++static struct fb_info info;
++
++#define smi_mmiowb(dat,reg)	writeb(dat, (SMIRegs + reg))
++#define smi_mmioww(dat,reg)	writew(dat, (SMIRegs + reg))
++#define smi_mmiowl(dat,reg)	writel(dat, (SMIRegs + reg))
++
++#define smi_mmiorb(reg)	        readb(SMIRegs + reg)
++#define smi_mmiorw(reg)	        readw(SMIRegs + reg)
++#define smi_mmiorl(reg)	        readl(SMIRegs + reg)
++
++/* Address space offsets for various control/status registers.
++*/
++#define MISC_CTRL			0x000004
++#define GPIO_LO_CTRL			0x000008
++#define GPIO_HI_CTRL			0x00000c
++#define DRAM_CTRL			0x000010
++#define CURRENT_POWER_GATE		0x000038
++#define CURRENT_POWER_CLOCK		0x00003C
++#define POWER_MODE1_GATE                0x000048
++#define POWER_MODE1_CLOCK               0x00004C
++#define POWER_MODE_CTRL			0x000054
++
++#define GPIO_DATA_LO			0x010000
++#define GPIO_DATA_HI			0x010004
++#define GPIO_DATA_DIR_LO		0x010008
++#define GPIO_DATA_DIR_HI		0x01000c
++#define I2C_BYTE_COUNT			0x010040
++#define I2C_CONTROL			0x010041
++#define I2C_STATUS_RESET		0x010042
++#define I2C_SLAVE_ADDRESS		0x010043
++#define I2C_DATA			0x010044
++
++#define DE_COLOR_COMPARE		0x100020
++#define DE_COLOR_COMPARE_MASK		0x100024
++#define DE_MASKS			0x100028
++#define DE_WRAP				0x10004C
++
++#define PANEL_DISPLAY_CTRL              0x080000
++#define PANEL_PAN_CTRL                  0x080004
++#define PANEL_COLOR_KEY                 0x080008
++#define PANEL_FB_ADDRESS                0x08000C
++#define PANEL_FB_WIDTH                  0x080010
++#define PANEL_WINDOW_WIDTH              0x080014
++#define PANEL_WINDOW_HEIGHT             0x080018
++#define PANEL_PLANE_TL                  0x08001C
++#define PANEL_PLANE_BR                  0x080020
++#define PANEL_HORIZONTAL_TOTAL          0x080024
++#define PANEL_HORIZONTAL_SYNC           0x080028
++#define PANEL_VERTICAL_TOTAL            0x08002C
++#define PANEL_VERTICAL_SYNC             0x080030
++#define PANEL_CURRENT_LINE              0x080034
++#define VIDEO_DISPLAY_CTRL		0x080040
++#define VIDEO_DISPLAY_FB0		0x080044
++#define VIDEO_DISPLAY_FBWIDTH		0x080048
++#define VIDEO_DISPLAY_FB0LAST		0x08004C
++#define VIDEO_DISPLAY_TL		0x080050
++#define VIDEO_DISPLAY_BR		0x080054
++#define VIDEO_SCALE			0x080058
++#define VIDEO_INITIAL_SCALE		0x08005C
++#define VIDEO_YUV_CONSTANTS		0x080060
++#define VIDEO_DISPLAY_FB1		0x080064
++#define VIDEO_DISPLAY_FB1LAST		0x080068
++#define VIDEO_ALPHA_CTRL		0x080080
++#define PANEL_HWC_ADDRESS		0x0800F0
++#define CRT_DISPLAY_CTRL		0x080200
++#define CRT_FB_ADDRESS			0x080204
++#define CRT_FB_WIDTH			0x080208
++#define CRT_HORIZONTAL_TOTAL		0x08020c
++#define CRT_HORIZONTAL_SYNC		0x080210
++#define CRT_VERTICAL_TOTAL		0x080214
++#define CRT_VERTICAL_SYNC		0x080218
++#define CRT_HWC_ADDRESS			0x080230
++#define CRT_HWC_LOCATION		0x080234
++
++#define ZV_CAPTURE_CTRL			0x090000
++#define ZV_CAPTURE_CLIP			0x090004
++#define ZV_CAPTURE_SIZE			0x090008
++#define ZV_CAPTURE_BUF0			0x09000c
++#define ZV_CAPTURE_BUF1			0x090010
++#define ZV_CAPTURE_OFFSET		0x090014
++#define ZV_FIFO_CTRL			0x090018
++
++#define waitforvsync() udelay(400)
++
++static int initdone = 0;
++static int crt_out = 1;
++
++
++static int
++smi_setcolreg(unsigned regno, unsigned red, unsigned green,
++	unsigned blue, unsigned transp,
++	struct fb_info *info)
++{
++	if (regno > 255)
++		return 1;
++
++	((u32 *)(info->pseudo_palette))[regno] =
++		    ((red & 0xf800) >> 0) |
++		    ((green & 0xfc00) >> 5) |
++		    ((blue & 0xf800) >> 11);
++
++	return 0;
++}
++
++/* This function still needs lots of work to generically support
++ * different output devices (CRT or LCD) and resolutions.
++ * Currently hard-coded for 1024x768 LCD panel.
++ */
++static void smi_setmode(void)
++{
++	if (initdone)
++		return;
++
++	initdone = 1;
++
++	/* Just blast in some control values based upon the chip
++	 * documentation.  We use the internal memory, I don't know
++	 * how to determine the amount available yet.
++	 */
++	smi_mmiowl(0x07F127C2, DRAM_CTRL);
++	smi_mmiowl(0x02000020, PANEL_HWC_ADDRESS);
++	smi_mmiowl(0x007FF800, PANEL_HWC_ADDRESS);
++	smi_mmiowl(0x00021827, POWER_MODE1_GATE);
++	smi_mmiowl(0x011A0A09, POWER_MODE1_CLOCK);
++	smi_mmiowl(0x00000001, POWER_MODE_CTRL);
++	smi_mmiowl(0x80000000, PANEL_FB_ADDRESS);
++	smi_mmiowl(0x08000800, PANEL_FB_WIDTH);
++	smi_mmiowl(0x04000000, PANEL_WINDOW_WIDTH);
++	smi_mmiowl(0x03000000, PANEL_WINDOW_HEIGHT);
++	smi_mmiowl(0x00000000, PANEL_PLANE_TL);
++	smi_mmiowl(0x02FF03FF, PANEL_PLANE_BR);
++	smi_mmiowl(0x05D003FF, PANEL_HORIZONTAL_TOTAL);
++	smi_mmiowl(0x00C80424, PANEL_HORIZONTAL_SYNC);
++	smi_mmiowl(0x032502FF, PANEL_VERTICAL_TOTAL);
++	smi_mmiowl(0x00060302, PANEL_VERTICAL_SYNC);
++	smi_mmiowl(0x00013905, PANEL_DISPLAY_CTRL);
++	smi_mmiowl(0x01013105, PANEL_DISPLAY_CTRL);
++	waitforvsync();
++	smi_mmiowl(0x03013905, PANEL_DISPLAY_CTRL);
++	waitforvsync();
++	smi_mmiowl(0x07013905, PANEL_DISPLAY_CTRL);
++	waitforvsync();
++	smi_mmiowl(0x0F013905, PANEL_DISPLAY_CTRL);
++	smi_mmiowl(0x0002187F, POWER_MODE1_GATE);
++	smi_mmiowl(0x01011801, POWER_MODE1_CLOCK);
++	smi_mmiowl(0x00000001, POWER_MODE_CTRL);
++
++	smi_mmiowl(0x80000000, PANEL_FB_ADDRESS);
++	smi_mmiowl(0x00000000, PANEL_PAN_CTRL);
++	smi_mmiowl(0x00000000, PANEL_COLOR_KEY);
++
++	if (crt_out) {
++		/* Just sent the panel out to the CRT for now.
++		*/
++		smi_mmiowl(0x80000000, CRT_FB_ADDRESS);
++		smi_mmiowl(0x08000800, CRT_FB_WIDTH);
++		smi_mmiowl(0x05D003FF, CRT_HORIZONTAL_TOTAL);
++		smi_mmiowl(0x00C80424, CRT_HORIZONTAL_SYNC);
++		smi_mmiowl(0x032502FF, CRT_VERTICAL_TOTAL);
++		smi_mmiowl(0x00060302, CRT_VERTICAL_SYNC);
++		smi_mmiowl(0x007FF800, CRT_HWC_ADDRESS);
++		smi_mmiowl(0x00010305, CRT_DISPLAY_CTRL);
++		smi_mmiowl(0x00000001, MISC_CTRL);
++	}
++}
++
++/*
++ * Unmap in the memory mapped IO registers
++ *
++ */
++
++static void __devinit smi_unmap_mmio(void)
++{
++	if (SMIRegs) {
++		iounmap(SMIRegs);
++		SMIRegs = NULL;
++	}
++}
++
++
++/*
++ * Unmap in the screen memory
++ *
++ */
++static void __devinit smi_unmap_smem(void)
++{
++	if (SMILFB) {
++		iounmap(SMILFB);
++		SMILFB = NULL;
++	}
++}
++
++static void vgxfb_setup(char *options)
++{
++
++	if (!options || !*options)
++		return;
++
++	/* The only thing I'm looking for right now is to disable a
++	 * CRT output that mirrors the panel display.
++	 */
++	if (strcmp(options, "no_crt") == 0)
++		crt_out = 0;
++
++	return;
++}
++
++static struct fb_ops smifb_ops = {
++	.owner =		THIS_MODULE,
++	.fb_setcolreg =		smi_setcolreg,
++	.fb_fillrect =		cfb_fillrect,
++	.fb_copyarea =		cfb_copyarea,
++	.fb_imageblit =		cfb_imageblit,
++};
++
++static int __devinit vgx_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
++{
++	int err;
++
++	/* Enable the chip.
++	*/
++	err = pci_enable_device(dev);
++	if (err)
++		return err;
++
++
++	/* Set up MMIO space.
++	*/
++	smifb_fix.mmio_start = pci_resource_start(dev,1);
++	smifb_fix.mmio_len = 0x00200000;
++	SMIRegs = ioremap(smifb_fix.mmio_start, smifb_fix.mmio_len);
++
++	/* Set up framebuffer.  It's a 64M space, various amount of
++	 * internal memory.  I don't know how to determine the real
++	 * amount of memory (yet).
++	 */
++	smifb_fix.smem_start = pci_resource_start(dev,0);
++	smifb_fix.smem_len = 0x00800000;
++	SMILFB = ioremap(smifb_fix.smem_start, smifb_fix.smem_len);
++
++	memset_io(SMILFB, 0, smifb_fix.smem_len);
++
++	info.screen_base = SMILFB;
++	info.fbops = &smifb_ops;
++	info.fix = smifb_fix;
++
++	info.flags = FBINFO_FLAG_DEFAULT;
++
++	info.pseudo_palette = kmalloc(sizeof(u32) * 16, GFP_KERNEL);
++	if (!info.pseudo_palette) {
++		return -ENOMEM;
++	}
++	memset(info.pseudo_palette, 0, sizeof(u32) *16);
++
++	fb_alloc_cmap(&info.cmap,256,0);
++
++	smi_setmode();
++
++	info.var = smifb_var;
++
++	if (register_framebuffer(&info) < 0)
++		goto failed;
++
++	return 0;
++
++failed:
++	smi_unmap_smem();
++	smi_unmap_mmio();
++
++	return err;
++}
++
++static void __devexit vgx_pci_remove(struct pci_dev *dev)
++{
++	unregister_framebuffer(&info);
++	smi_unmap_smem();
++	smi_unmap_mmio();
++}
++
++static struct pci_device_id vgx_devices[] = {
++	{PCI_VENDOR_ID_SILICON_MOTION, PCI_DEVICE_ID_SM501_VOYAGER_GX_REV_AA,
++	 PCI_ANY_ID, PCI_ANY_ID},
++	{PCI_VENDOR_ID_SILICON_MOTION, PCI_DEVICE_ID_SM501_VOYAGER_GX_REV_B,
++	 PCI_ANY_ID, PCI_ANY_ID},
++	{0}
++};
++
++MODULE_DEVICE_TABLE(pci, vgx_devices);
++
++static struct pci_driver vgxfb_pci_driver = {
++	.name	= "vgxfb",
++	.id_table= vgx_devices,
++	.probe	= vgx_pci_probe,
++	.remove	= __devexit_p(vgx_pci_remove),
++};
++
++static int __init vgxfb_init(void)
++{
++	char *option = NULL;
++
++	if (fb_get_options("vgxfb", &option))
++		return -ENODEV;
++	vgxfb_setup(option);
++
++	printk("Silicon Motion Inc. VOYAGER Init complete.\n");
++	return pci_module_init(&vgxfb_pci_driver);
++}
++
++static void __exit vgxfb_exit(void)
++{
++	pci_unregister_driver(&vgxfb_pci_driver);
++}
++
++module_init(vgxfb_init);
++module_exit(vgxfb_exit);
++
++MODULE_AUTHOR("");
++MODULE_DESCRIPTION("Framebuffer driver for SMI Voyager");
++MODULE_LICENSE("GPL");
+diff -Naur linux-2.6.17.orig/include/asm-mips/addrspace.h linux-2.6.17/include/asm-mips/addrspace.h
+--- linux-2.6.17.orig/include/asm-mips/addrspace.h	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/include/asm-mips/addrspace.h	2006-06-19 18:16:14.000000000 -0700
+@@ -133,57 +133,22 @@
+     || defined (CONFIG_CPU_NEVADA)					\
+     || defined (CONFIG_CPU_TX49XX)					\
+     || defined (CONFIG_CPU_MIPS64)
+-#define KUSIZE		_LLCONST_(0x0000010000000000)	/* 2^^40 */
+-#define KUSIZE_64	_LLCONST_(0x0000010000000000)	/* 2^^40 */
+-#define K0SIZE		_LLCONST_(0x0000001000000000)	/* 2^^36 */
+-#define K1SIZE		_LLCONST_(0x0000001000000000)	/* 2^^36 */
+-#define K2SIZE		_LLCONST_(0x000000ff80000000)
+-#define KSEGSIZE	_LLCONST_(0x000000ff80000000)	/* max syssegsz */
+ #define TO_PHYS_MASK	_LLCONST_(0x0000000fffffffff)	/* 2^^36 - 1 */
+ #endif
+ 
+ #if defined (CONFIG_CPU_R8000)
+ /* We keep KUSIZE consistent with R4000 for now (2^^40) instead of (2^^48) */
+-#define KUSIZE		_LLCONST_(0x0000010000000000)	/* 2^^40 */
+-#define KUSIZE_64	_LLCONST_(0x0000010000000000)	/* 2^^40 */
+-#define K0SIZE		_LLCONST_(0x0000010000000000)	/* 2^^40 */
+-#define K1SIZE		_LLCONST_(0x0000010000000000)	/* 2^^40 */
+-#define K2SIZE		_LLCONST_(0x0001000000000000)
+-#define KSEGSIZE	_LLCONST_(0x0000010000000000)	/* max syssegsz */
+ #define TO_PHYS_MASK	_LLCONST_(0x000000ffffffffff)	/* 2^^40 - 1 */
+ #endif
+ 
+ #if defined (CONFIG_CPU_R10000)
+-#define KUSIZE		_LLCONST_(0x0000010000000000)	/* 2^^40 */
+-#define KUSIZE_64	_LLCONST_(0x0000010000000000)	/* 2^^40 */
+-#define K0SIZE		_LLCONST_(0x0000010000000000)	/* 2^^40 */
+-#define K1SIZE		_LLCONST_(0x0000010000000000)	/* 2^^40 */
+-#define K2SIZE		_LLCONST_(0x00000fff80000000)
+-#define KSEGSIZE	_LLCONST_(0x00000fff80000000)	/* max syssegsz */
+ #define TO_PHYS_MASK	_LLCONST_(0x000000ffffffffff)	/* 2^^40 - 1 */
+ #endif
+ 
+ #if defined(CONFIG_CPU_SB1) || defined(CONFIG_CPU_SB1A)
+-#define KUSIZE		_LLCONST_(0x0000100000000000)	/* 2^^44 */
+-#define KUSIZE_64	_LLCONST_(0x0000100000000000)	/* 2^^44 */
+-#define K0SIZE		_LLCONST_(0x0000100000000000)	/* 2^^44 */
+-#define K1SIZE		_LLCONST_(0x0000100000000000)	/* 2^^44 */
+-#define K2SIZE		_LLCONST_(0x0000ffff80000000)
+-#define KSEGSIZE	_LLCONST_(0x0000ffff80000000)	/* max syssegsz */
+ #define TO_PHYS_MASK	_LLCONST_(0x00000fffffffffff)	/* 2^^44 - 1 */
+ #endif
+ 
+-/*
+- * Further names for SGI source compatibility.  These are stolen from
+- * IRIX's <sys/mips_addrspace.h>.
+- */
+-#define KUBASE		_LLCONST_(0)
+-#define KUSIZE_32	_LLCONST_(0x0000000080000000)	/* KUSIZE
+-							   for a 32 bit proc */
+-#define K0BASE_EXL_WR	_LLCONST_(0xa800000000000000)	/* exclusive on write */
+-#define K0BASE_NONCOH	_LLCONST_(0x9800000000000000)	/* noncoherent */
+-#define K0BASE_EXL	_LLCONST_(0xa000000000000000)	/* exclusive */
+-
+ #ifndef CONFIG_CPU_R8000
+ 
+ /*
+diff -Naur linux-2.6.17.orig/include/asm-mips/apm.h linux-2.6.17/include/asm-mips/apm.h
+--- linux-2.6.17.orig/include/asm-mips/apm.h	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/include/asm-mips/apm.h	2006-06-19 18:16:14.000000000 -0700
+@@ -0,0 +1,65 @@
++/* -*- linux-c -*-
++ *
++ * (C) 2003 zecke@handhelds.org
++ *
++ * GPL version 2
++ *
++ * based on arch/arm/kernel/apm.c
++ * factor out the information needed by architectures to provide
++ * apm status
++ *
++ *
++ */
++#ifndef MIPS_ASM_SA1100_APM_H
++#define MIPS_ASM_SA1100_APM_H
++
++#include <linux/config.h>
++#include <linux/apm_bios.h>
++
++/*
++ * This structure gets filled in by the machine specific 'get_power_status'
++ * implementation.  Any fields which are not set default to a safe value.
++ */
++struct apm_power_info {
++	unsigned char	ac_line_status;
++#define APM_AC_OFFLINE			0
++#define APM_AC_ONLINE			1
++#define APM_AC_BACKUP			2
++#define APM_AC_UNKNOWN			0xff
++
++	unsigned char	battery_status;
++#define APM_BATTERY_STATUS_HIGH		0
++#define APM_BATTERY_STATUS_LOW		1
++#define APM_BATTERY_STATUS_CRITICAL	2
++#define APM_BATTERY_STATUS_CHARGING	3
++#define APM_BATTERY_STATUS_NOT_PRESENT	4
++#define APM_BATTERY_STATUS_UNKNOWN	0xff
++
++	unsigned char	battery_flag;
++#define APM_BATTERY_FLAG_HIGH		(1 << 0)
++#define APM_BATTERY_FLAG_LOW		(1 << 1)
++#define APM_BATTERY_FLAG_CRITICAL	(1 << 2)
++#define APM_BATTERY_FLAG_CHARGING	(1 << 3)
++#define APM_BATTERY_FLAG_NOT_PRESENT	(1 << 7)
++#define APM_BATTERY_FLAG_UNKNOWN	0xff
++
++	int		battery_life;
++	int		time;
++	int		units;
++#define APM_UNITS_MINS			0
++#define APM_UNITS_SECS			1
++#define APM_UNITS_UNKNOWN		-1
++
++};
++
++/*
++ * This allows machines to provide their own "apm get power status" function.
++ */
++extern void (*apm_get_power_status)(struct apm_power_info *);
++
++/*
++ * Queue an event (APM_SYS_SUSPEND or APM_CRITICAL_SUSPEND)
++ */
++void apm_queue_event(apm_event_t event);
++
++#endif
+diff -Naur linux-2.6.17.orig/include/asm-mips/asmmacro-32.h linux-2.6.17/include/asm-mips/asmmacro-32.h
+--- linux-2.6.17.orig/include/asm-mips/asmmacro-32.h	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/include/asm-mips/asmmacro-32.h	2006-06-19 18:16:14.000000000 -0700
+@@ -12,7 +12,7 @@
+ #include <asm/fpregdef.h>
+ #include <asm/mipsregs.h>
+ 
+-	.macro	fpu_save_double thread status tmp1=t0 tmp2
++	.macro	fpu_save_double thread status tmp1=t0
+ 	cfc1	\tmp1,  fcr31
+ 	sdc1	$f0,  THREAD_FPR0(\thread)
+ 	sdc1	$f2,  THREAD_FPR2(\thread)
+@@ -70,7 +70,7 @@
+ 	sw	\tmp, THREAD_FCR31(\thread)
+ 	.endm
+ 
+-	.macro	fpu_restore_double thread tmp=t0
++	.macro	fpu_restore_double thread status tmp=t0
+ 	lw	\tmp, THREAD_FCR31(\thread)
+ 	ldc1	$f0,  THREAD_FPR0(\thread)
+ 	ldc1	$f2,  THREAD_FPR2(\thread)
+diff -Naur linux-2.6.17.orig/include/asm-mips/asmmacro-64.h linux-2.6.17/include/asm-mips/asmmacro-64.h
+--- linux-2.6.17.orig/include/asm-mips/asmmacro-64.h	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/include/asm-mips/asmmacro-64.h	2006-06-19 18:16:14.000000000 -0700
+@@ -53,12 +53,12 @@
+ 	sdc1	$f31, THREAD_FPR31(\thread)
+ 	.endm
+ 
+-	.macro	fpu_save_double thread status tmp1 tmp2
+-	sll	\tmp2, \tmp1, 5
+-	bgez	\tmp2, 2f
++	.macro	fpu_save_double thread status tmp
++	sll	\tmp, \status, 5
++	bgez	\tmp, 2f
+ 	fpu_save_16odd \thread
+ 2:
+-	fpu_save_16even \thread \tmp1			# clobbers t1
++	fpu_save_16even \thread \tmp
+ 	.endm
+ 
+ 	.macro	fpu_restore_16even thread tmp=t0
+@@ -101,13 +101,12 @@
+ 	ldc1	$f31, THREAD_FPR31(\thread)
+ 	.endm
+ 
+-	.macro	fpu_restore_double thread tmp
+-	mfc0	t0, CP0_STATUS
+-	sll	t1, t0, 5
+-	bgez	t1, 1f				# 16 register mode?
++	.macro	fpu_restore_double thread status tmp
++	sll	\tmp, \status, 5
++	bgez	\tmp, 1f				# 16 register mode?
+ 
+-	fpu_restore_16odd a0
+-1:	fpu_restore_16even a0, t0		# clobbers t0
++	fpu_restore_16odd \thread
++1:	fpu_restore_16even \thread \tmp
+ 	.endm
+ 
+ 	.macro	cpu_save_nonscratch thread
+diff -Naur linux-2.6.17.orig/include/asm-mips/asmmacro.h linux-2.6.17/include/asm-mips/asmmacro.h
+--- linux-2.6.17.orig/include/asm-mips/asmmacro.h	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/include/asm-mips/asmmacro.h	2006-06-19 18:16:14.000000000 -0700
+@@ -27,14 +27,14 @@
+ 	ori	\reg, \reg, TCSTATUS_IXMT
+ 	xori	\reg, \reg, TCSTATUS_IXMT
+ 	mtc0	\reg, CP0_TCSTATUS
+-	ehb
++	_ehb
+ 	.endm
+ 
+ 	.macro	local_irq_disable reg=t0
+ 	mfc0	\reg, CP0_TCSTATUS
+ 	ori	\reg, \reg, TCSTATUS_IXMT
+ 	mtc0	\reg, CP0_TCSTATUS
+-	ehb
++	_ehb
+ 	.endm
+ #else
+ 	.macro	local_irq_enable reg=t0
+diff -Naur linux-2.6.17.orig/include/asm-mips/bootinfo.h linux-2.6.17/include/asm-mips/bootinfo.h
+--- linux-2.6.17.orig/include/asm-mips/bootinfo.h	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/include/asm-mips/bootinfo.h	2006-06-19 18:16:14.000000000 -0700
+@@ -217,6 +217,13 @@
+  */
+ #define MACH_GROUP_TITAN       22	/* PMC-Sierra Titan		*/
+ #define  MACH_TITAN_YOSEMITE	1	/* PMC-Sierra Yosemite		*/
++#define  MACH_TITAN_EXCITE	2	/* Basler eXcite		*/
++
++/*
++ * Valid machtype for group NEC EMMA2RH
++ */
++#define MACH_GROUP_NEC_EMMA2RH 25	/* NEC EMMA2RH (was 23)		*/
++#define  MACH_NEC_MARKEINS	0	/* NEC EMMA2RH Mark-eins	*/
+ 
+ #define CL_SIZE			COMMAND_LINE_SIZE
+ 
+@@ -258,4 +265,10 @@
+  * Registers a0, a1, a3 and a4 as passed to the kenrel entry by firmware
+  */
+ extern unsigned long fw_arg0, fw_arg1, fw_arg2, fw_arg3;
++
++/*
++ * Platform memory detection hook called by setup_arch
++ */
++extern void plat_mem_setup(void);
++
+ #endif /* _ASM_BOOTINFO_H */
+diff -Naur linux-2.6.17.orig/include/asm-mips/cpu-features.h linux-2.6.17/include/asm-mips/cpu-features.h
+--- linux-2.6.17.orig/include/asm-mips/cpu-features.h	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/include/asm-mips/cpu-features.h	2006-06-19 18:16:14.000000000 -0700
+@@ -188,19 +188,15 @@
+ # endif
+ #endif
+ 
+-#ifdef CONFIG_CPU_MIPSR2
+-# if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
+-#  define cpu_has_vint		(cpu_data[0].options & MIPS_CPU_VINT)
+-# else
+-#  define cpu_has_vint			0
+-# endif
+-# if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
+-#  define cpu_has_veic		(cpu_data[0].options & MIPS_CPU_VEIC)
+-# else
+-#  define cpu_has_veic			0
+-# endif
+-#else
++#if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
++# define cpu_has_vint		(cpu_data[0].options & MIPS_CPU_VINT)
++#elif !defined(cpu_has_vint)
+ # define cpu_has_vint			0
++#endif
++
++#if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
++# define cpu_has_veic		(cpu_data[0].options & MIPS_CPU_VEIC)
++#elif !defined(cpu_has_veic)
+ # define cpu_has_veic			0
+ #endif
+ 
+diff -Naur linux-2.6.17.orig/include/asm-mips/ddb5074.h linux-2.6.17/include/asm-mips/ddb5074.h
+--- linux-2.6.17.orig/include/asm-mips/ddb5074.h	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/include/asm-mips/ddb5074.h	1969-12-31 16:00:00.000000000 -0800
+@@ -1,11 +0,0 @@
+-/*
+- *  include/asm-mips/ddb5074.h -- NEC DDB Vrc-5074 definitions
+- *
+- *  Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
+- *                     Sony Software Development Center Europe (SDCE), Brussels
+- */
+-
+-extern void ddb5074_led_hex(int hex);
+-extern void ddb5074_led_d2(int on);
+-extern void ddb5074_led_d3(int on);
+-
+diff -Naur linux-2.6.17.orig/include/asm-mips/ddb5xxx/ddb5074.h linux-2.6.17/include/asm-mips/ddb5xxx/ddb5074.h
+--- linux-2.6.17.orig/include/asm-mips/ddb5xxx/ddb5074.h	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/include/asm-mips/ddb5xxx/ddb5074.h	1969-12-31 16:00:00.000000000 -0800
+@@ -1,38 +0,0 @@
+-/*
+- *  include/asm-mips/ddb5074.h -- NEC DDB Vrc-5074 definitions
+- *
+- *  Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
+- *                     Sony Software Development Center Europe (SDCE), Brussels
+- */
+-
+-#ifndef _ASM_DDB5XXX_DDB5074_H
+-#define _ASM_DDB5XXX_DDB5074_H
+-
+-#include <asm/nile4.h>
+-
+-#define DDB_SDRAM_SIZE      0x04000000      /* 64MB */
+-
+-#define DDB_PCI_IO_BASE     0x06000000
+-#define DDB_PCI_IO_SIZE     0x02000000      /* 32 MB */
+-
+-#define DDB_PCI_MEM_BASE    0x08000000
+-#define DDB_PCI_MEM_SIZE    0x08000000  /* 128 MB */
+-
+-#define DDB_PCI_CONFIG_BASE DDB_PCI_MEM_BASE
+-#define DDB_PCI_CONFIG_SIZE DDB_PCI_MEM_SIZE
+-
+-#define NILE4_PCI_IO_BASE   0xa6000000
+-#define NILE4_PCI_MEM_BASE  0xa8000000
+-#define NILE4_PCI_CFG_BASE  NILE4_PCI_MEM_BASE
+-#define DDB_PCI_IACK_BASE NILE4_PCI_IO_BASE
+-
+-#define NILE4_IRQ_BASE NUM_I8259_INTERRUPTS
+-#define CPU_IRQ_BASE (NUM_NILE4_INTERRUPTS + NILE4_IRQ_BASE)
+-#define CPU_NILE4_CASCADE 2
+-
+-extern void ddb5074_led_hex(int hex);
+-extern void ddb5074_led_d2(int on);
+-extern void ddb5074_led_d3(int on);
+-
+-extern void nile4_irq_setup(u32 base);
+-#endif
+diff -Naur linux-2.6.17.orig/include/asm-mips/ddb5xxx/ddb5476.h linux-2.6.17/include/asm-mips/ddb5xxx/ddb5476.h
+--- linux-2.6.17.orig/include/asm-mips/ddb5xxx/ddb5476.h	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/include/asm-mips/ddb5xxx/ddb5476.h	1969-12-31 16:00:00.000000000 -0800
+@@ -1,157 +0,0 @@
+-/*
+- * header file specific for ddb5476
+- *
+- * Copyright (C) 2001 MontaVista Software Inc.
+- * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
+- *
+- * This program is free software; you can redistribute  it and/or modify it
+- * under  the terms of  the GNU General  Public License as published by the
+- * Free Software Foundation;  either version 2 of the  License, or (at your
+- * option) any later version.
+- *
+- */
+-
+-/*
+- *  Memory map (physical address)
+- *
+- *  Note most of the following address must be properly aligned by the
+- *  corresponding size.  For example, if PCI_IO_SIZE is 16MB, then
+- *  PCI_IO_BASE must be aligned along 16MB boundary.
+- */
+-#define DDB_SDRAM_BASE		0x00000000
+-#define DDB_SDRAM_SIZE		0x04000000      /* 64MB */
+-
+-#define	DDB_DCS3_BASE		0x04000000	/* flash 1 */
+-#define	DDB_DCS3_SIZE		0x01000000	/* 16MB */
+-
+-#define	DDB_DCS2_BASE		0x05000000	/* flash 2 */
+-#define	DDB_DCS2_SIZE		0x01000000	/* 16MB */
+-
+-#define DDB_PCI_IO_BASE		0x06000000
+-#define DDB_PCI_IO_SIZE		0x02000000      /* 32 MB */
+-
+-#define	DDB_PCI_MEM_BASE	0x08000000
+-#define	DDB_PCI_MEM_SIZE	0x08000000	/* 128 MB */
+-
+-#define	DDB_DCS5_BASE		0x13000000	/* DDB status regs */
+-#define	DDB_DCS5_SIZE		0x00200000	/* 2MB, 8-bit */
+-
+-#define	DDB_DCS4_BASE		0x14000000	/* DDB control regs */
+-#define	DDB_DCS4_SIZE		0x00200000	/* 2MB, 8-bit */
+-
+-#define DDB_INTCS_BASE		0x1fa00000      /* VRC5476 control regs */
+-#define DDB_INTCS_SIZE		0x00200000      /* 2MB */
+-
+-#define DDB_BOOTCS_BASE         0x1fc00000      /* Boot ROM / EPROM /Flash */
+-#define DDB_BOOTCS_SIZE         0x00200000      /* 2 MB - doc says 4MB */
+-
+-
+-/* aliases */
+-#define	DDB_PCI_CONFIG_BASE	DDB_PCI_MEM_BASE
+-#define	DDB_PCI_CONFIG_SIZE	DDB_PCI_MEM_SIZE
+-
+-/* PCI intr ack share PCIW0 with PCI IO */
+-#define	DDB_PCI_IACK_BASE	DDB_PCI_IO_BASE
+-
+-/*
+- * Interrupt mapping
+- *
+- * We have three interrupt controllers:
+- *
+- *   . CPU itself - 8 sources
+- *   . i8259 - 16 sources
+- *   . vrc5476 - 16 sources
+- *
+- *  They connected as follows:
+- *    all vrc5476 interrupts are routed to cpu IP2 (by software setting)
+- *    all i2869 are routed to INTC in vrc5476 (by hardware connection)
+- *
+- *  All VRC5476 PCI interrupts are level-triggered (no ack needed).
+- *  All PCI irq but INTC are active low.
+- */
+-
+-/*
+- * irq number block assignment
+- */
+-
+-#define	NUM_CPU_IRQ		8
+-#define	NUM_I8259_IRQ		16
+-#define	NUM_VRC5476_IRQ		16
+-
+-#define	DDB_IRQ_BASE		0
+-
+-#define	I8259_IRQ_BASE		DDB_IRQ_BASE
+-#define	VRC5476_IRQ_BASE	(I8259_IRQ_BASE + NUM_I8259_IRQ)
+-#define	CPU_IRQ_BASE		(VRC5476_IRQ_BASE + NUM_VRC5476_IRQ)
+-
+-/*
+- * vrc5476 irq defs, see page 52-64 of Vrc5074 system controller manual
+- */
+-
+-#define VRC5476_IRQ_CPCE	0	/* cpu parity error */
+-#define VRC5476_IRQ_CNTD	1	/* cpu no target */
+-#define VRC5476_IRQ_MCE		2	/* memory check error */
+-#define VRC5476_IRQ_DMA		3	/* DMA */
+-#define VRC5476_IRQ_UART	4	/* vrc5476 builtin UART, not used */
+-#define VRC5476_IRQ_WDOG	5	/* watchdog timer */
+-#define VRC5476_IRQ_GPT		6	/* general purpose timer */
+-#define VRC5476_IRQ_LBRT	7	/* local bus read timeout */
+-#define VRC5476_IRQ_INTA	8	/* PCI INT #A */
+-#define VRC5476_IRQ_INTB	9	/* PCI INT #B */
+-#define VRC5476_IRQ_INTC	10	/* PCI INT #C */
+-#define VRC5476_IRQ_INTD	11	/* PCI INT #D */
+-#define VRC5476_IRQ_INTE	12	/* PCI INT #E */
+-#define VRC5476_IRQ_RESERVED_13	13	/* reserved  */
+-#define VRC5476_IRQ_PCIS	14	/* PCI SERR #  */
+-#define VRC5476_IRQ_PCI		15	/* PCI internal error */
+-
+-/*
+- * i2859 irq assignment
+- */
+-#define I8259_IRQ_RESERVED_0	0
+-#define I8259_IRQ_KEYBOARD	1	/* M1543 default */
+-#define I8259_IRQ_CASCADE	2
+-#define I8259_IRQ_UART_B	3	/* M1543 default, may conflict with RTC according to schematic diagram  */
+-#define I8259_IRQ_UART_A	4	/* M1543 default */
+-#define I8259_IRQ_PARALLEL	5	/* M1543 default */
+-#define I8259_IRQ_RESERVED_6	6
+-#define I8259_IRQ_RESERVED_7	7
+-#define I8259_IRQ_RTC		8	/* who set this? */
+-#define I8259_IRQ_USB		9	/* ddb_setup */
+-#define I8259_IRQ_PMU		10	/* ddb_setup */
+-#define I8259_IRQ_RESERVED_11	11
+-#define I8259_IRQ_RESERVED_12	12	/* m1543_irq_setup */
+-#define I8259_IRQ_RESERVED_13	13
+-#define I8259_IRQ_HDC1		14	/* default and ddb_setup */
+-#define I8259_IRQ_HDC2		15	/* default */
+-
+-
+-/*
+- * misc
+- */
+-#define	VRC5476_I8259_CASCADE	VRC5476_IRQ_INTC
+-#define	CPU_VRC5476_CASCADE	2
+-
+-#define is_i8259_irq(irq)       ((irq) < NUM_I8259_IRQ)
+-#define nile4_to_irq(n)         ((n)+NUM_I8259_IRQ)
+-#define irq_to_nile4(n)         ((n)-NUM_I8259_IRQ)
+-
+-/*
+- * low-level irq functions
+- */
+-#ifndef __ASSEMBLY__
+-extern void nile4_map_irq(int nile4_irq, int cpu_irq);
+-extern void nile4_map_irq_all(int cpu_irq);
+-extern void nile4_enable_irq(int nile4_irq);
+-extern void nile4_disable_irq(int nile4_irq);
+-extern void nile4_disable_irq_all(void);
+-extern u16 nile4_get_irq_stat(int cpu_irq);
+-extern void nile4_enable_irq_output(int cpu_irq);
+-extern void nile4_disable_irq_output(int cpu_irq);
+-extern void nile4_set_pci_irq_polarity(int pci_irq, int high);
+-extern void nile4_set_pci_irq_level_or_edge(int pci_irq, int level);
+-extern void nile4_clear_irq(int nile4_irq);
+-extern void nile4_clear_irq_mask(u32 mask);
+-extern u8 nile4_i8259_iack(void);
+-extern void nile4_dump_irq_status(void);        /* Debug */
+-#endif /* !__ASSEMBLY__ */
+diff -Naur linux-2.6.17.orig/include/asm-mips/ddb5xxx/ddb5xxx.h linux-2.6.17/include/asm-mips/ddb5xxx/ddb5xxx.h
+--- linux-2.6.17.orig/include/asm-mips/ddb5xxx/ddb5xxx.h	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/include/asm-mips/ddb5xxx/ddb5xxx.h	2006-06-19 18:16:14.000000000 -0700
+@@ -174,13 +174,8 @@
+ 
+ static inline void ddb_sync(void)
+ {
+-/* The DDB5074 doesn't seem to like these accesses. They kill the board on
+- * interrupt load
+- */
+-#ifndef CONFIG_DDB5074
+     volatile u32 *p = (volatile u32 *)0xbfc00000;
+     (void)(*p);
+-#endif
+ }
+ 
+ static inline void ddb_out32(u32 offset, u32 val)
+@@ -260,11 +255,7 @@
+ /*
+  * include the board dependent part
+  */
+-#if defined(CONFIG_DDB5074)
+-#include <asm/ddb5xxx/ddb5074.h>
+-#elif defined(CONFIG_DDB5476)
+-#include <asm/ddb5xxx/ddb5476.h>
+-#elif defined(CONFIG_DDB5477)
++#if defined(CONFIG_DDB5477)
+ #include <asm/ddb5xxx/ddb5477.h>
+ #else
+ #error "Unknown DDB board!"
+diff -Naur linux-2.6.17.orig/include/asm-mips/emma2rh/emma2rh.h linux-2.6.17/include/asm-mips/emma2rh/emma2rh.h
+--- linux-2.6.17.orig/include/asm-mips/emma2rh/emma2rh.h	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/include/asm-mips/emma2rh/emma2rh.h	2006-06-19 18:16:14.000000000 -0700
+@@ -0,0 +1,330 @@
++/*
++ *  include/asm-mips/emma2rh/emma2rh.h
++ *      This file is EMMA2RH common header.
++ *
++ *  Copyright (C) NEC Electronics Corporation 2005-2006
++ *
++ *  This file based on include/asm-mips/ddb5xxx/ddb5xxx.h
++ *          Copyright 2001 MontaVista Software Inc.
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License as published by
++ *  the Free Software Foundation; either version 2 of the License, or
++ *  (at your option) any later version.
++ *
++ *  This program is distributed in the hope that it will be useful,
++ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *  GNU General Public License for more details.
++ *
++ *  You should have received a copy of the GNU General Public License
++ *  along with this program; if not, write to the Free Software
++ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
++ */
++#ifndef __ASM_EMMA2RH_EMMA2RH_H
++#define __ASM_EMMA2RH_EMMA2RH_H
++
++/*
++ * EMMA2RH registers
++ */
++#define REGBASE 0x10000000
++
++#define EMMA2RH_BHIF_STRAP_0	(0x000010+REGBASE)
++#define EMMA2RH_BHIF_INT_ST_0	(0x000030+REGBASE)
++#define EMMA2RH_BHIF_INT_ST_1	(0x000034+REGBASE)
++#define EMMA2RH_BHIF_INT_ST_2	(0x000038+REGBASE)
++#define EMMA2RH_BHIF_INT_EN_0	(0x000040+REGBASE)
++#define EMMA2RH_BHIF_INT_EN_1	(0x000044+REGBASE)
++#define EMMA2RH_BHIF_INT_EN_2	(0x000048+REGBASE)
++#define EMMA2RH_BHIF_INT1_EN_0	(0x000050+REGBASE)
++#define EMMA2RH_BHIF_INT1_EN_1	(0x000054+REGBASE)
++#define EMMA2RH_BHIF_INT1_EN_2	(0x000058+REGBASE)
++#define EMMA2RH_BHIF_SW_INT	(0x000070+REGBASE)
++#define EMMA2RH_BHIF_SW_INT_EN	(0x000080+REGBASE)
++#define EMMA2RH_BHIF_SW_INT_CLR	(0x000090+REGBASE)
++#define EMMA2RH_BHIF_MAIN_CTRL	(0x0000b4+REGBASE)
++#define EMMA2RH_BHIF_EXCEPT_VECT_BASE_ADDRESS	(0x0000c0+REGBASE)
++#define EMMA2RH_GPIO_DIR	(0x110d20+REGBASE)
++#define EMMA2RH_GPIO_INT_ST	(0x110d30+REGBASE)
++#define EMMA2RH_GPIO_INT_MASK	(0x110d3c+REGBASE)
++#define EMMA2RH_GPIO_INT_MODE	(0x110d48+REGBASE)
++#define EMMA2RH_GPIO_INT_CND_A	(0x110d54+REGBASE)
++#define EMMA2RH_GPIO_INT_CND_B	(0x110d60+REGBASE)
++#define EMMA2RH_PBRD_INT_EN	(0x100010+REGBASE)
++#define EMMA2RH_PBRD_CLKSEL	(0x100028+REGBASE)
++#define EMMA2RH_PFUR0_BASE	(0x101000+REGBASE)
++#define EMMA2RH_PFUR1_BASE	(0x102000+REGBASE)
++#define EMMA2RH_PFUR2_BASE	(0x103000+REGBASE)
++#define EMMA2RH_PIIC0_BASE	(0x107000+REGBASE)
++#define EMMA2RH_PIIC1_BASE	(0x108000+REGBASE)
++#define EMMA2RH_PIIC2_BASE	(0x109000+REGBASE)
++#define EMMA2RH_PCI_CONTROL	(0x200000+REGBASE)
++#define EMMA2RH_PCI_ARBIT_CTR	(0x200004+REGBASE)
++#define EMMA2RH_PCI_IWIN0_CTR	(0x200010+REGBASE)
++#define EMMA2RH_PCI_IWIN1_CTR	(0x200014+REGBASE)
++#define EMMA2RH_PCI_INIT_ESWP	(0x200018+REGBASE)
++#define EMMA2RH_PCI_INT		(0x200020+REGBASE)
++#define EMMA2RH_PCI_INT_EN	(0x200024+REGBASE)
++#define EMMA2RH_PCI_TWIN_CTR	(0x200030+REGBASE)
++#define EMMA2RH_PCI_TWIN_BADR	(0x200034+REGBASE)
++#define EMMA2RH_PCI_TWIN0_DADR	(0x200038+REGBASE)
++#define EMMA2RH_PCI_TWIN1_DADR	(0x20003c+REGBASE)
++
++/*
++ *  Memory map (physical address)
++ *
++ *  Note most of the following address must be properly aligned by the
++ *  corresponding size.  For example, if PCI_IO_SIZE is 16MB, then
++ *  PCI_IO_BASE must be aligned along 16MB boundary.
++ */
++
++/* the actual ram size is detected at run-time */
++#define EMMA2RH_RAM_BASE	0x00000000
++#define EMMA2RH_RAM_SIZE	0x10000000	/* less than 256MB */
++
++#define EMMA2RH_IO_BASE		0x10000000
++#define EMMA2RH_IO_SIZE		0x01000000	/* 16 MB */
++
++#define EMMA2RH_GENERALIO_BASE	0x11000000
++#define EMMA2RH_GENERALIO_SIZE	0x01000000	/* 16 MB */
++
++#define EMMA2RH_PCI_IO_BASE	0x12000000
++#define EMMA2RH_PCI_IO_SIZE	0x02000000	/* 32 MB */
++
++#define EMMA2RH_PCI_MEM_BASE	0x14000000
++#define EMMA2RH_PCI_MEM_SIZE	0x08000000	/* 128 MB */
++
++#define EMMA2RH_ROM_BASE	0x1c000000
++#define EMMA2RH_ROM_SIZE	0x04000000	/* 64 MB */
++
++#define EMMA2RH_PCI_CONFIG_BASE	EMMA2RH_PCI_IO_BASE
++#define EMMA2RH_PCI_CONFIG_SIZE	EMMA2RH_PCI_IO_SIZE
++
++#define NUM_CPU_IRQ		8
++#define NUM_EMMA2RH_IRQ		96
++
++#define CPU_EMMA2RH_CASCADE	2
++#define EMMA2RH_IRQ_BASE	0
++
++/*
++ * emma2rh irq defs
++ */
++
++#define EMMA2RH_IRQ_INT0	(0 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT1	(1 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT2	(2 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT3	(3 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT4	(4 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT5	(5 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT6	(6 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT7	(7 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT8	(8 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT9	(9 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT10	(10 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT11	(11 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT12	(12 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT13	(13 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT14	(14 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT15	(15 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT16	(16 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT17	(17 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT18	(18 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT19	(19 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT20	(20 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT21	(21 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT22	(22 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT23	(23 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT24	(24 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT25	(25 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT26	(26 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT27	(27 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT28	(28 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT29	(29 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT30	(30 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT31	(31 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT32	(32 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT33	(33 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT34	(34 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT35	(35 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT36	(36 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT37	(37 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT38	(38 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT39	(39 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT40	(40 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT41	(41 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT42	(42 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT43	(43 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT44	(44 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT45	(45 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT46	(46 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT47	(47 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT48	(48 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT49	(49 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT50	(50 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT51	(51 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT52	(52 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT53	(53 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT54	(54 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT55	(55 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT56	(56 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT57	(57 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT58	(58 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT59	(59 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT60	(60 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT61	(61 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT62	(62 + EMMA2RH_IRQ_BASE)
++#define EMMA2RH_IRQ_INT63	(63 + EMMA2RH_IRQ_BASE)
++
++#define EMMA2RH_IRQ_PFUR0	EMMA2RH_IRQ_INT49
++#define EMMA2RH_IRQ_PFUR1	EMMA2RH_IRQ_INT50
++#define EMMA2RH_IRQ_PFUR2	EMMA2RH_IRQ_INT51
++#define EMMA2RH_IRQ_PIIC0	EMMA2RH_IRQ_INT56
++#define EMMA2RH_IRQ_PIIC1	EMMA2RH_IRQ_INT57
++#define EMMA2RH_IRQ_PIIC2	EMMA2RH_IRQ_INT58
++
++/*
++ *  EMMA2RH Register Access
++ */
++
++#define EMMA2RH_BASE (0xa0000000)
++
++static inline void emma2rh_sync(void)
++{
++	volatile u32 *p = (volatile u32 *)0xbfc00000;
++	(void)(*p);
++}
++
++static inline void emma2rh_out32(u32 offset, u32 val)
++{
++	*(volatile u32 *)(EMMA2RH_BASE | offset) = val;
++	emma2rh_sync();
++}
++
++static inline u32 emma2rh_in32(u32 offset)
++{
++	u32 val = *(volatile u32 *)(EMMA2RH_BASE | offset);
++	emma2rh_sync();
++	return val;
++}
++
++static inline void emma2rh_out16(u32 offset, u16 val)
++{
++	*(volatile u16 *)(EMMA2RH_BASE | offset) = val;
++	emma2rh_sync();
++}
++
++static inline u16 emma2rh_in16(u32 offset)
++{
++	u16 val = *(volatile u16 *)(EMMA2RH_BASE | offset);
++	emma2rh_sync();
++	return val;
++}
++
++static inline void emma2rh_out8(u32 offset, u8 val)
++{
++	*(volatile u8 *)(EMMA2RH_BASE | offset) = val;
++	emma2rh_sync();
++}
++
++static inline u8 emma2rh_in8(u32 offset)
++{
++	u8 val = *(volatile u8 *)(EMMA2RH_BASE | offset);
++	emma2rh_sync();
++	return val;
++}
++
++/**
++ * IIC registers map
++ **/
++
++/*---------------------------------------------------------------------------*/
++/* CNT - Control register (00H R/W)                                          */
++/*---------------------------------------------------------------------------*/
++#define SPT         0x00000001
++#define STT         0x00000002
++#define ACKE        0x00000004
++#define WTIM        0x00000008
++#define SPIE        0x00000010
++#define WREL        0x00000020
++#define LREL        0x00000040
++#define IICE        0x00000080
++#define CNT_RESERVED    0x000000ff	/* reserved bit 0 */
++
++#define I2C_EMMA_START      (IICE | STT)
++#define I2C_EMMA_STOP       (IICE | SPT)
++#define I2C_EMMA_REPSTART   I2C_EMMA_START
++
++/*---------------------------------------------------------------------------*/
++/* STA - Status register (10H Read)                                          */
++/*---------------------------------------------------------------------------*/
++#define MSTS        0x00000080
++#define ALD         0x00000040
++#define EXC         0x00000020
++#define COI         0x00000010
++#define TRC         0x00000008
++#define ACKD        0x00000004
++#define STD         0x00000002
++#define SPD         0x00000001
++
++/*---------------------------------------------------------------------------*/
++/* CSEL - Clock select register (20H R/W)                                    */
++/*---------------------------------------------------------------------------*/
++#define FCL         0x00000080
++#define ND50        0x00000040
++#define CLD         0x00000020
++#define DAD         0x00000010
++#define SMC         0x00000008
++#define DFC         0x00000004
++#define CL          0x00000003
++#define CSEL_RESERVED   0x000000ff	/* reserved bit 0 */
++
++#define FAST397     0x0000008b
++#define FAST297     0x0000008a
++#define FAST347     0x0000000b
++#define FAST260     0x0000000a
++#define FAST130     0x00000008
++#define STANDARD108 0x00000083
++#define STANDARD83  0x00000082
++#define STANDARD95  0x00000003
++#define STANDARD73  0x00000002
++#define STANDARD36  0x00000001
++#define STANDARD71  0x00000000
++
++/*---------------------------------------------------------------------------*/
++/* SVA - Slave address register (30H R/W)                                    */
++/*---------------------------------------------------------------------------*/
++#define SVA         0x000000fe
++
++/*---------------------------------------------------------------------------*/
++/* SHR - Shift register (40H R/W)                                            */
++/*---------------------------------------------------------------------------*/
++#define SR          0x000000ff
++
++/*---------------------------------------------------------------------------*/
++/* INT - Interrupt register (50H R/W)                                        */
++/* INTM - Interrupt mask register (60H R/W)                                  */
++/*---------------------------------------------------------------------------*/
++#define INTE0       0x00000001
++
++/***********************************************************************
++ * I2C registers
++ ***********************************************************************
++ */
++#define I2C_EMMA_CNT            0x00
++#define I2C_EMMA_STA            0x10
++#define I2C_EMMA_CSEL           0x20
++#define I2C_EMMA_SVA            0x30
++#define I2C_EMMA_SHR            0x40
++#define I2C_EMMA_INT            0x50
++#define I2C_EMMA_INTM           0x60
++
++/*
++ * include the board dependent part
++ */
++#if defined(CONFIG_MARKEINS)
++#include <asm/emma2rh/markeins.h>
++#else
++#error "Unknown EMMA2RH board!"
++#endif
++
++#endif /* __ASM_EMMA2RH_EMMA2RH_H */
+diff -Naur linux-2.6.17.orig/include/asm-mips/emma2rh/markeins.h linux-2.6.17/include/asm-mips/emma2rh/markeins.h
+--- linux-2.6.17.orig/include/asm-mips/emma2rh/markeins.h	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/include/asm-mips/emma2rh/markeins.h	2006-06-19 18:16:14.000000000 -0700
+@@ -0,0 +1,76 @@
++/*
++ *  include/asm-mips/emma2rh/markeins.h
++ *      This file is EMMA2RH board depended header.
++ *
++ *  Copyright (C) NEC Electronics Corporation 2005-2006
++ *
++ *  This file based on include/asm-mips/ddb5xxx/ddb5xxx.h
++ *          Copyright 2001 MontaVista Software Inc.
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License as published by
++ *  the Free Software Foundation; either version 2 of the License, or
++ *  (at your option) any later version.
++ *
++ *  This program is distributed in the hope that it will be useful,
++ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *  GNU General Public License for more details.
++ *
++ *  You should have received a copy of the GNU General Public License
++ *  along with this program; if not, write to the Free Software
++ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
++ */
++
++#ifndef MARKEINS_H
++#define MARKEINS_H
++
++#define NUM_EMMA2RH_IRQ_SW	32
++#define NUM_EMMA2RH_IRQ_GPIO	32
++
++#define EMMA2RH_SW_CASCADE	(EMMA2RH_IRQ_INT7 - EMMA2RH_IRQ_INT0)
++#define EMMA2RH_GPIO_CASCADE	(EMMA2RH_IRQ_INT46 - EMMA2RH_IRQ_INT0)
++
++#define EMMA2RH_SW_IRQ_BASE	(EMMA2RH_IRQ_BASE + NUM_EMMA2RH_IRQ)
++#define EMMA2RH_GPIO_IRQ_BASE	(EMMA2RH_SW_IRQ_BASE + NUM_EMMA2RH_IRQ_SW)
++#define CPU_IRQ_BASE		(EMMA2RH_GPIO_IRQ_BASE + NUM_EMMA2RH_IRQ_GPIO)
++
++#define EMMA2RH_SW_IRQ_INT0	(0+EMMA2RH_SW_IRQ_BASE)
++#define EMMA2RH_SW_IRQ_INT1	(1+EMMA2RH_SW_IRQ_BASE)
++#define EMMA2RH_SW_IRQ_INT2	(2+EMMA2RH_SW_IRQ_BASE)
++#define EMMA2RH_SW_IRQ_INT3	(3+EMMA2RH_SW_IRQ_BASE)
++#define EMMA2RH_SW_IRQ_INT4	(4+EMMA2RH_SW_IRQ_BASE)
++#define EMMA2RH_SW_IRQ_INT5	(5+EMMA2RH_SW_IRQ_BASE)
++#define EMMA2RH_SW_IRQ_INT6	(6+EMMA2RH_SW_IRQ_BASE)
++#define EMMA2RH_SW_IRQ_INT7	(7+EMMA2RH_SW_IRQ_BASE)
++#define EMMA2RH_SW_IRQ_INT8	(8+EMMA2RH_SW_IRQ_BASE)
++#define EMMA2RH_SW_IRQ_INT9	(9+EMMA2RH_SW_IRQ_BASE)
++#define EMMA2RH_SW_IRQ_INT10	(10+EMMA2RH_SW_IRQ_BASE)
++#define EMMA2RH_SW_IRQ_INT11	(11+EMMA2RH_SW_IRQ_BASE)
++#define EMMA2RH_SW_IRQ_INT12	(12+EMMA2RH_SW_IRQ_BASE)
++#define EMMA2RH_SW_IRQ_INT13	(13+EMMA2RH_SW_IRQ_BASE)
++#define EMMA2RH_SW_IRQ_INT14	(14+EMMA2RH_SW_IRQ_BASE)
++#define EMMA2RH_SW_IRQ_INT15	(15+EMMA2RH_SW_IRQ_BASE)
++#define EMMA2RH_SW_IRQ_INT16	(16+EMMA2RH_SW_IRQ_BASE)
++#define EMMA2RH_SW_IRQ_INT17	(17+EMMA2RH_SW_IRQ_BASE)
++#define EMMA2RH_SW_IRQ_INT18	(18+EMMA2RH_SW_IRQ_BASE)
++#define EMMA2RH_SW_IRQ_INT19	(19+EMMA2RH_SW_IRQ_BASE)
++#define EMMA2RH_SW_IRQ_INT20	(20+EMMA2RH_SW_IRQ_BASE)
++#define EMMA2RH_SW_IRQ_INT21	(21+EMMA2RH_SW_IRQ_BASE)
++#define EMMA2RH_SW_IRQ_INT22	(22+EMMA2RH_SW_IRQ_BASE)
++#define EMMA2RH_SW_IRQ_INT23	(23+EMMA2RH_SW_IRQ_BASE)
++#define EMMA2RH_SW_IRQ_INT24	(24+EMMA2RH_SW_IRQ_BASE)
++#define EMMA2RH_SW_IRQ_INT25	(25+EMMA2RH_SW_IRQ_BASE)
++#define EMMA2RH_SW_IRQ_INT26	(26+EMMA2RH_SW_IRQ_BASE)
++#define EMMA2RH_SW_IRQ_INT27	(27+EMMA2RH_SW_IRQ_BASE)
++#define EMMA2RH_SW_IRQ_INT28	(28+EMMA2RH_SW_IRQ_BASE)
++#define EMMA2RH_SW_IRQ_INT29	(29+EMMA2RH_SW_IRQ_BASE)
++#define EMMA2RH_SW_IRQ_INT30	(30+EMMA2RH_SW_IRQ_BASE)
++#define EMMA2RH_SW_IRQ_INT31	(31+EMMA2RH_SW_IRQ_BASE)
++
++#define MARKEINS_PCI_IRQ_INTA	EMMA2RH_GPIO_IRQ_BASE+15
++#define MARKEINS_PCI_IRQ_INTB	EMMA2RH_GPIO_IRQ_BASE+16
++#define MARKEINS_PCI_IRQ_INTC	EMMA2RH_GPIO_IRQ_BASE+17
++#define MARKEINS_PCI_IRQ_INTD	EMMA2RH_GPIO_IRQ_BASE+18
++
++#endif /* CONFIG_MARKEINS */
+diff -Naur linux-2.6.17.orig/include/asm-mips/fpu_emulator.h linux-2.6.17/include/asm-mips/fpu_emulator.h
+--- linux-2.6.17.orig/include/asm-mips/fpu_emulator.h	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/include/asm-mips/fpu_emulator.h	2006-06-19 18:16:14.000000000 -0700
+@@ -12,8 +12,8 @@
+  *  with this program; if not, write to the Free Software Foundation, Inc.,
+  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+  *
+- * Further private data for which no space exists in mips_fpu_soft_struct.
+- * This should be subsumed into the mips_fpu_soft_struct structure as
++ * Further private data for which no space exists in mips_fpu_struct.
++ * This should be subsumed into the mips_fpu_struct structure as
+  * defined in processor.h as soon as the absurd wired absolute assembler
+  * offsets become dynamic at compile time.
+  *
+diff -Naur linux-2.6.17.orig/include/asm-mips/fpu.h linux-2.6.17/include/asm-mips/fpu.h
+--- linux-2.6.17.orig/include/asm-mips/fpu.h	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/include/asm-mips/fpu.h	2006-06-19 18:16:14.000000000 -0700
+@@ -138,10 +138,9 @@
+ 	if (cpu_has_fpu) {
+ 		if ((tsk == current) && __is_fpu_owner())
+ 			_save_fp(current);
+-		return tsk->thread.fpu.hard.fpr;
+ 	}
+ 
+-	return tsk->thread.fpu.soft.fpr;
++	return tsk->thread.fpu.fpr;
+ }
+ 
+ #endif /* _ASM_FPU_H */
+diff -Naur linux-2.6.17.orig/include/asm-mips/futex.h linux-2.6.17/include/asm-mips/futex.h
+--- linux-2.6.17.orig/include/asm-mips/futex.h	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/include/asm-mips/futex.h	2006-06-19 18:16:14.000000000 -0700
+@@ -22,51 +22,53 @@
+ 		"	.set	push				\n"	\
+ 		"	.set	noat				\n"	\
+ 		"	.set	mips3				\n"	\
+-		"1:	ll	%1, (%3)	# __futex_atomic_op	\n" \
++		"1:	ll	%1, %4	# __futex_atomic_op	\n"	\
+ 		"	.set	mips0				\n"	\
+ 		"	" insn	"				\n"	\
+ 		"	.set	mips3				\n"	\
+-		"2:	sc	$1, (%3)			\n"	\
++		"2:	sc	$1, %2				\n"	\
+ 		"	beqzl	$1, 1b				\n"	\
+ 		__FUTEX_SMP_SYNC					\
+ 		"3:						\n"	\
+ 		"	.set	pop				\n"	\
+ 		"	.set	mips0				\n"	\
+ 		"	.section .fixup,\"ax\"			\n"	\
+-		"4:	li	%0, %5				\n"	\
++		"4:	li	%0, %6				\n"	\
+ 		"	j	2b				\n"	\
+ 		"	.previous				\n"	\
+ 		"	.section __ex_table,\"a\"		\n"	\
+ 		"	"__UA_ADDR "\t1b, 4b			\n"	\
+ 		"	"__UA_ADDR "\t2b, 4b			\n"	\
+ 		"	.previous				\n"	\
+-		: "=r" (ret), "=r" (oldval)				\
+-		: "0" (0), "r" (uaddr), "Jr" (oparg), "i" (-EFAULT));	\
++		: "=r" (ret), "=&r" (oldval), "=R" (*uaddr)		\
++		: "0" (0), "R" (*uaddr), "Jr" (oparg), "i" (-EFAULT)	\
++		: "memory");						\
+ 	} else if (cpu_has_llsc) {					\
+ 		__asm__ __volatile__(					\
+ 		"	.set	push				\n"	\
+ 		"	.set	noat				\n"	\
+ 		"	.set	mips3				\n"	\
+-		"1:	ll	%1, (%3)	# __futex_atomic_op	\n" \
++		"1:	ll	%1, %4	# __futex_atomic_op	\n"	\
+ 		"	.set	mips0				\n"	\
+ 		"	" insn	"				\n"	\
+ 		"	.set	mips3				\n"	\
+-		"2:	sc	$1, (%3)			\n"	\
++		"2:	sc	$1, %2				\n"	\
+ 		"	beqz	$1, 1b				\n"	\
+ 		__FUTEX_SMP_SYNC					\
+ 		"3:						\n"	\
+ 		"	.set	pop				\n"	\
+ 		"	.set	mips0				\n"	\
+ 		"	.section .fixup,\"ax\"			\n"	\
+-		"4:	li	%0, %5				\n"	\
++		"4:	li	%0, %6				\n"	\
+ 		"	j	2b				\n"	\
+ 		"	.previous				\n"	\
+ 		"	.section __ex_table,\"a\"		\n"	\
+ 		"	"__UA_ADDR "\t1b, 4b			\n"	\
+ 		"	"__UA_ADDR "\t2b, 4b			\n"	\
+ 		"	.previous				\n"	\
+-		: "=r" (ret), "=r" (oldval)				\
+-		: "0" (0), "r" (uaddr), "Jr" (oparg), "i" (-EFAULT));	\
++		: "=r" (ret), "=&r" (oldval), "=R" (*uaddr)		\
++		: "0" (0), "R" (*uaddr), "Jr" (oparg), "i" (-EFAULT)	\
++		: "memory");						\
+ 	} else								\
+ 		ret = -ENOSYS;						\
+ }
+@@ -89,23 +91,23 @@
+ 
+ 	switch (op) {
+ 	case FUTEX_OP_SET:
+-		__futex_atomic_op("move	$1, %z4", ret, oldval, uaddr, oparg);
++		__futex_atomic_op("move	$1, %z5", ret, oldval, uaddr, oparg);
+ 		break;
+ 
+ 	case FUTEX_OP_ADD:
+-		__futex_atomic_op("addu	$1, %1, %z4",
++		__futex_atomic_op("addu	$1, %1, %z5",
+ 		                  ret, oldval, uaddr, oparg);
+ 		break;
+ 	case FUTEX_OP_OR:
+-		__futex_atomic_op("or	$1, %1, %z4",
++		__futex_atomic_op("or	$1, %1, %z5",
+ 		                  ret, oldval, uaddr, oparg);
+ 		break;
+ 	case FUTEX_OP_ANDN:
+-		__futex_atomic_op("and	$1, %1, %z4",
++		__futex_atomic_op("and	$1, %1, %z5",
+ 		                  ret, oldval, uaddr, ~oparg);
+ 		break;
+ 	case FUTEX_OP_XOR:
+-		__futex_atomic_op("xor	$1, %1, %z4",
++		__futex_atomic_op("xor	$1, %1, %z5",
+ 		                  ret, oldval, uaddr, oparg);
+ 		break;
+ 	default:
+diff -Naur linux-2.6.17.orig/include/asm-mips/io.h linux-2.6.17/include/asm-mips/io.h
+--- linux-2.6.17.orig/include/asm-mips/io.h	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/include/asm-mips/io.h	2006-06-19 18:16:14.000000000 -0700
+@@ -519,34 +519,6 @@
+ }
+ 
+ /*
+- * Memory Mapped I/O
+- */
+-#define ioread8(addr)		readb(addr)
+-#define ioread16(addr)		readw(addr)
+-#define ioread32(addr)		readl(addr)
+-
+-#define iowrite8(b,addr)	writeb(b,addr)
+-#define iowrite16(w,addr)	writew(w,addr)
+-#define iowrite32(l,addr)	writel(l,addr)
+-
+-#define ioread8_rep(a,b,c)	readsb(a,b,c)
+-#define ioread16_rep(a,b,c)	readsw(a,b,c)
+-#define ioread32_rep(a,b,c)	readsl(a,b,c)
+-
+-#define iowrite8_rep(a,b,c)	writesb(a,b,c)
+-#define iowrite16_rep(a,b,c)	writesw(a,b,c)
+-#define iowrite32_rep(a,b,c)	writesl(a,b,c)
+-
+-/* Create a virtual mapping cookie for an IO port range */
+-extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
+-extern void ioport_unmap(void __iomem *);
+-
+-/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
+-struct pci_dev;
+-extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
+-extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
+-
+-/*
+  * ISA space is 'always mapped' on currently supported MIPS systems, no need
+  * to explicitly ioremap() it. The fact that the ISA IO space is mapped
+  * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
+diff -Naur linux-2.6.17.orig/include/asm-mips/irq.h linux-2.6.17/include/asm-mips/irq.h
+--- linux-2.6.17.orig/include/asm-mips/irq.h	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/include/asm-mips/irq.h	2006-06-19 18:16:14.000000000 -0700
+@@ -77,4 +77,8 @@
+                           unsigned long hwmask);
+ #endif /* CONFIG_MIPS_MT_SMTC */
+ 
++#ifdef CONFIG_SMP
++#define ARCH_HAS_IRQ_PER_CPU
++#endif
++
+ #endif /* _ASM_IRQ_H */
+diff -Naur linux-2.6.17.orig/include/asm-mips/mach-au1x00/au1xxx_ide.h linux-2.6.17/include/asm-mips/mach-au1x00/au1xxx_ide.h
+--- linux-2.6.17.orig/include/asm-mips/mach-au1x00/au1xxx_ide.h	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/include/asm-mips/mach-au1x00/au1xxx_ide.h	2006-06-19 18:16:14.000000000 -0700
+@@ -84,6 +84,7 @@
+ } _auide_hwif;
+ 
+ #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
++
+ /* HD white list */
+ static const struct drive_list_entry dma_white_list [] = {
+ /*
+diff -Naur linux-2.6.17.orig/include/asm-mips/mach-ddb5074/mc146818rtc.h linux-2.6.17/include/asm-mips/mach-ddb5074/mc146818rtc.h
+--- linux-2.6.17.orig/include/asm-mips/mach-ddb5074/mc146818rtc.h	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/include/asm-mips/mach-ddb5074/mc146818rtc.h	1969-12-31 16:00:00.000000000 -0800
+@@ -1,31 +0,0 @@
+-/*
+- * This file is subject to the terms and conditions of the GNU General Public
+- * License.  See the file "COPYING" in the main directory of this archive
+- * for more details.
+- *
+- * Copyright (C) 1998, 2001, 03 by Ralf Baechle
+- *
+- * RTC routines for PC style attached Dallas chip.
+- */
+-#ifndef __ASM_MACH_DDB5074_MC146818RTC_H
+-#define __ASM_MACH_DDB5074_MC146818RTC_H
+-
+-#include <asm/ddb5xxx/ddb5074.h>
+-#include <asm/ddb5xxx/ddb5xxx.h>
+-
+-#define RTC_PORT(x)	(0x70 + (x))
+-#define RTC_IRQ		8
+-
+-static inline unsigned char CMOS_READ(unsigned long addr)
+-{
+-	return *(volatile unsigned char *)(KSEG1ADDR(DDB_PCI_MEM_BASE)+addr);
+-}
+-
+-static inline void CMOS_WRITE(unsigned char data, unsigned long addr)
+-{
+-	*(volatile unsigned char *)(KSEG1ADDR(DDB_PCI_MEM_BASE)+addr) = data;
+-}
+-
+-#define RTC_ALWAYS_BCD	1
+-
+-#endif /* __ASM_MACH_DDB5074_MC146818RTC_H */
+diff -Naur linux-2.6.17.orig/include/asm-mips/mach-emma2rh/irq.h linux-2.6.17/include/asm-mips/mach-emma2rh/irq.h
+--- linux-2.6.17.orig/include/asm-mips/mach-emma2rh/irq.h	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/include/asm-mips/mach-emma2rh/irq.h	2006-06-19 18:16:14.000000000 -0700
+@@ -0,0 +1,13 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2003 by Ralf Baechle
++ */
++#ifndef __ASM_MACH_EMMA2RH_IRQ_H
++#define __ASM_MACH_EMMA2RH_IRQ_H
++
++#define NR_IRQS	256
++
++#endif /* __ASM_MACH_EMMA2RH_IRQ_H */
+diff -Naur linux-2.6.17.orig/include/asm-mips/mach-excite/cpu-feature-overrides.h linux-2.6.17/include/asm-mips/mach-excite/cpu-feature-overrides.h
+--- linux-2.6.17.orig/include/asm-mips/mach-excite/cpu-feature-overrides.h	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/include/asm-mips/mach-excite/cpu-feature-overrides.h	2006-06-19 18:16:14.000000000 -0700
+@@ -0,0 +1,40 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2004 Thomas Koeller <thomas.koeller@baslerweb.com>
++ */
++#ifndef __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H
++#define __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H
++
++/*
++ * Basler eXcite has an RM9122 processor.
++ */
++#define cpu_has_watch		1
++#define cpu_has_mips16		0
++#define cpu_has_divec		0
++#define cpu_has_vce		0
++#define cpu_has_cache_cdex_p	0
++#define cpu_has_cache_cdex_s	0
++#define cpu_has_prefetch	1
++#define cpu_has_mcheck		0
++#define cpu_has_ejtag		0
++
++#define cpu_has_llsc		1
++#define cpu_has_vtag_icache	0
++#define cpu_has_dc_aliases	0
++#define cpu_has_ic_fills_f_dc	0
++#define cpu_has_dsp		0
++#define cpu_icache_snoops_remote_store	0
++
++#define cpu_has_nofpuex		0
++#define cpu_has_64bits		1
++
++#define cpu_has_subset_pcaches	0
++
++#define cpu_dcache_line_size()	32
++#define cpu_icache_line_size()	32
++#define cpu_scache_line_size()	32
++
++#endif /* __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H */
+diff -Naur linux-2.6.17.orig/include/asm-mips/mach-excite/excite.h linux-2.6.17/include/asm-mips/mach-excite/excite.h
+--- linux-2.6.17.orig/include/asm-mips/mach-excite/excite.h	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/include/asm-mips/mach-excite/excite.h	2006-06-19 18:16:14.000000000 -0700
+@@ -0,0 +1,155 @@
++#ifndef __EXCITE_H__
++#define __EXCITE_H__
++
++#include <linux/config.h>
++#include <linux/init.h>
++#include <asm/addrspace.h>
++#include <asm/types.h>
++
++#define EXCITE_CPU_EXT_CLOCK 100000000
++
++#if !defined(__ASSEMBLER__)
++void __init excite_kgdb_init(void);
++void excite_procfs_init(void);
++extern unsigned long memsize;
++extern char modetty[];
++extern u32 unit_id;
++#endif
++
++/* Base name for XICAP devices */
++#define XICAP_NAME	"xicap_gpi"
++
++/* OCD register offsets */
++#define LKB0		0x0038
++#define LKB5		0x0128
++#define LKM5		0x012C
++#define LKB7		0x0138
++#define LKM7		0x013c
++#define LKB8		0x0140
++#define LKM8		0x0144
++#define LKB9		0x0148
++#define LKM9		0x014c
++#define LKB10		0x0150
++#define LKM10		0x0154
++#define LKB11		0x0158
++#define LKM11		0x015c
++#define LKB12		0x0160
++#define LKM12		0x0164
++#define LKB13		0x0168
++#define LKM13		0x016c
++#define LDP0		0x0200
++#define LDP1		0x0210
++#define LDP2		0x0220
++#define LDP3		0x0230
++#define INTPIN0		0x0A40
++#define INTPIN1		0x0A44
++#define INTPIN2		0x0A48
++#define INTPIN3		0x0A4C
++#define INTPIN4		0x0A50
++#define INTPIN5		0x0A54
++#define INTPIN6		0x0A58
++#define INTPIN7		0x0A5C
++
++
++
++
++/* TITAN register offsets */
++#define CPRR		0x0004
++#define CPDSR		0x0008
++#define CPTC0R		0x000c
++#define CPTC1R		0x0010
++#define CPCFG0		0x0020
++#define CPCFG1		0x0024
++#define CPDST0A		0x0028
++#define CPDST0B		0x002c
++#define CPDST1A		0x0030
++#define CPDST1B		0x0034
++#define CPXDSTA		0x0038
++#define CPXDSTB		0x003c
++#define CPXCISRA	0x0048
++#define CPXCISRB	0x004c
++#define CPGIG0ER	0x0050
++#define CPGIG1ER	0x0054
++#define CPGRWL		0x0068
++#define CPURSLMT	0x00f8
++#define UACFG		0x0200
++#define UAINTS		0x0204
++#define SDRXFCIE	0x4828
++#define SDTXFCIE	0x4928
++#define INTP0Status0	0x1B00
++#define INTP0Mask0	0x1B04
++#define INTP0Set0	0x1B08
++#define INTP0Clear0	0x1B0C
++#define GXCFG		0x5000
++#define GXDMADRPFX	0x5018
++#define GXDMA_DESCADR	0x501c
++#define GXCH0TDESSTRT	0x5054
++
++/* IRQ definitions */
++#define NMICONFIG		0xac0
++#define TITAN_MSGINT	0xc4
++#define TITAN_IRQ	((TITAN_MSGINT / 0x20) + 2)
++#define FPGA0_MSGINT	0x5a
++#define FPGA0_IRQ	((FPGA0_MSGINT / 0x20) + 2)
++#define FPGA1_MSGINT	0x7b
++#define FPGA1_IRQ	((FPGA1_MSGINT / 0x20) + 2)
++#define PHY_MSGINT	0x9c
++#define PHY_IRQ		((PHY_MSGINT   / 0x20) + 2)
++
++#if defined(CONFIG_BASLER_EXCITE_PROTOTYPE)
++/* Pre-release units used interrupt pin #9 */
++#define USB_IRQ		11
++#else
++/* Re-designed units use interrupt pin #1 */
++#define USB_MSGINT	0x39
++#define USB_IRQ		((USB_MSGINT / 0x20) + 2)
++#endif
++#define TIMER_IRQ	12
++
++
++/* Device address ranges */
++#define EXCITE_OFFS_OCD		0x1fffc000
++#define	EXCITE_SIZE_OCD		(16 * 1024)
++#define EXCITE_PHYS_OCD		CPHYSADDR(EXCITE_OFFS_OCD)
++#define EXCITE_ADDR_OCD		CKSEG1ADDR(EXCITE_OFFS_OCD)
++
++#define EXCITE_OFFS_SCRAM 	0x1fffa000
++#define	EXCITE_SIZE_SCRAM	(8 << 10)
++#define EXCITE_PHYS_SCRAM 	CPHYSADDR(EXCITE_OFFS_SCRAM)
++#define EXCITE_ADDR_SCRAM 	CKSEG1ADDR(EXCITE_OFFS_SCRAM)
++
++#define EXCITE_OFFS_PCI_IO	0x1fff8000
++#define	EXCITE_SIZE_PCI_IO	(8 << 10)
++#define EXCITE_PHYS_PCI_IO	CPHYSADDR(EXCITE_OFFS_PCI_IO)
++#define EXCITE_ADDR_PCI_IO 	CKSEG1ADDR(EXCITE_OFFS_PCI_IO)
++
++#define EXCITE_OFFS_TITAN	0x1fff0000
++#define EXCITE_SIZE_TITAN	(32 << 10)
++#define EXCITE_PHYS_TITAN	CPHYSADDR(EXCITE_OFFS_TITAN)
++#define EXCITE_ADDR_TITAN	CKSEG1ADDR(EXCITE_OFFS_TITAN)
++
++#define EXCITE_OFFS_PCI_MEM	0x1ffe0000
++#define EXCITE_SIZE_PCI_MEM	(64 << 10)
++#define EXCITE_PHYS_PCI_MEM	CPHYSADDR(EXCITE_OFFS_PCI_MEM)
++#define EXCITE_ADDR_PCI_MEM	CKSEG1ADDR(EXCITE_OFFS_PCI_MEM)
++
++#define EXCITE_OFFS_FPGA	0x1ffdc000
++#define EXCITE_SIZE_FPGA	(16 << 10)
++#define EXCITE_PHYS_FPGA	CPHYSADDR(EXCITE_OFFS_FPGA)
++#define EXCITE_ADDR_FPGA	CKSEG1ADDR(EXCITE_OFFS_FPGA)
++
++#define EXCITE_OFFS_NAND	0x1ffd8000
++#define EXCITE_SIZE_NAND	(16 << 10)
++#define EXCITE_PHYS_NAND	CPHYSADDR(EXCITE_OFFS_NAND)
++#define EXCITE_ADDR_NAND	CKSEG1ADDR(EXCITE_OFFS_NAND)
++
++#define EXCITE_OFFS_BOOTROM	0x1f000000
++#define EXCITE_SIZE_BOOTROM	(8 << 20)
++#define EXCITE_PHYS_BOOTROM	CPHYSADDR(EXCITE_OFFS_BOOTROM)
++#define EXCITE_ADDR_BOOTROM	CKSEG1ADDR(EXCITE_OFFS_BOOTROM)
++
++/* FPGA address offsets */
++#define EXCITE_FPGA_DPR		0x0104	/* dual-ported ram */
++#define EXCITE_FPGA_SYSCTL	0x0200	/* system control register block */
++
++#endif /* __EXCITE_H__ */
+diff -Naur linux-2.6.17.orig/include/asm-mips/mach-excite/excite_nandflash.h linux-2.6.17/include/asm-mips/mach-excite/excite_nandflash.h
+--- linux-2.6.17.orig/include/asm-mips/mach-excite/excite_nandflash.h	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/include/asm-mips/mach-excite/excite_nandflash.h	2006-06-19 18:16:14.000000000 -0700
+@@ -0,0 +1,7 @@
++#ifndef __EXCITE_NANDFLASH_H__
++#define __EXCITE_NANDFLASH_H__
++
++/* Resource names */
++#define EXCITE_NANDFLASH_RESOURCE_REGS	"excite_nandflash_regs"
++
++#endif /* __EXCITE_NANDFLASH_H__ */
+diff -Naur linux-2.6.17.orig/include/asm-mips/mach-excite/rm9k_eth.h linux-2.6.17/include/asm-mips/mach-excite/rm9k_eth.h
+--- linux-2.6.17.orig/include/asm-mips/mach-excite/rm9k_eth.h	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/include/asm-mips/mach-excite/rm9k_eth.h	2006-06-19 18:16:14.000000000 -0700
+@@ -0,0 +1,23 @@
++#if !defined(__RM9K_ETH_H__)
++#define __RM9K_ETH_H__
++
++#define RM9K_GE_NAME			"rm9k_ge"
++
++/* Resource names */
++#define RM9K_GE_RESOURCE_MAC      	"rm9k_ge_mac"
++#define RM9K_GE_RESOURCE_MSTAT      	"rm9k_ge_mstat"
++#define RM9K_GE_RESOURCE_PKTPROC	"rm9k_ge_pktproc"
++#define RM9K_GE_RESOURCE_XDMA		"rm9k_ge_xdma"
++#define RM9K_GE_RESOURCE_FIFO_RX  	"rm9k_ge_fifo_rx"
++#define RM9K_GE_RESOURCE_FIFO_TX  	"rm9k_ge_fifo_tx"
++#define RM9K_GE_RESOURCE_FIFOMEM_RX  	"rm9k_ge_fifo_memory_rx"
++#define RM9K_GE_RESOURCE_FIFOMEM_TX  	"rm9k_ge_fifo_memory_tx"
++#define RM9K_GE_RESOURCE_PHY      	"rm9k_ge_phy"
++#define RM9K_GE_RESOURCE_DMADESC_RX  	"rm9k_ge_dmadesc_rx"
++#define RM9K_GE_RESOURCE_DMADESC_TX  	"rm9k_ge_dmadesc_tx"
++#define RM9K_GE_RESOURCE_IRQ_MAIN	"rm9k_ge_irq_main"
++#define RM9K_GE_RESOURCE_IRQ_PHY	"rm9k_ge_irq_phy"
++#define RM9K_GE_RESOURCE_GPI_SLICE	"rm9k_ge_gpi_slice"
++#define RM9K_GE_RESOURCE_MDIO_CHANNEL	"rm9k_ge_mdio_channel"
++
++#endif /* !defined(__RM9K_ETH_H__) */
+diff -Naur linux-2.6.17.orig/include/asm-mips/mach-excite/rm9k_wdt.h linux-2.6.17/include/asm-mips/mach-excite/rm9k_wdt.h
+--- linux-2.6.17.orig/include/asm-mips/mach-excite/rm9k_wdt.h	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/include/asm-mips/mach-excite/rm9k_wdt.h	2006-06-19 18:16:14.000000000 -0700
+@@ -0,0 +1,12 @@
++#ifndef __RM9K_WDT_H__
++#define __RM9K_WDT_H__
++
++/* Device name */
++#define WDT_NAME		"wdt_gpi"
++
++/* Resource names */
++#define WDT_RESOURCE_REGS	"excite_watchdog_regs"
++#define WDT_RESOURCE_IRQ	"excite_watchdog_irq"
++#define WDT_RESOURCE_COUNTER	"excite_watchdog_counter"
++
++#endif /* __RM9K_WDT_H__ */
+diff -Naur linux-2.6.17.orig/include/asm-mips/mach-excite/rm9k_xicap.h linux-2.6.17/include/asm-mips/mach-excite/rm9k_xicap.h
+--- linux-2.6.17.orig/include/asm-mips/mach-excite/rm9k_xicap.h	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/include/asm-mips/mach-excite/rm9k_xicap.h	2006-06-19 18:16:14.000000000 -0700
+@@ -0,0 +1,16 @@
++#ifndef __EXCITE_XICAP_H__
++#define __EXCITE_XICAP_H__
++
++
++/* Resource names */
++#define XICAP_RESOURCE_FIFO_RX		"xicap_fifo_rx"
++#define XICAP_RESOURCE_FIFO_TX		"xicap_fifo_tx"
++#define XICAP_RESOURCE_XDMA 		"xicap_xdma"
++#define XICAP_RESOURCE_DMADESC		"xicap_dmadesc"
++#define XICAP_RESOURCE_PKTPROC  	"xicap_pktproc"
++#define XICAP_RESOURCE_IRQ		"xicap_irq"
++#define XICAP_RESOURCE_GPI_SLICE	"xicap_gpi_slice"
++#define XICAP_RESOURCE_FIFO_BLK		"xicap_fifo_blocks"
++#define XICAP_RESOURCE_PKT_STREAM	"xicap_pkt_stream"
++
++#endif /* __EXCITE_XICAP_H__ */
+diff -Naur linux-2.6.17.orig/include/asm-mips/mach-mips/irq.h linux-2.6.17/include/asm-mips/mach-mips/irq.h
+--- linux-2.6.17.orig/include/asm-mips/mach-mips/irq.h	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/include/asm-mips/mach-mips/irq.h	2006-06-19 18:16:14.000000000 -0700
+@@ -5,10 +5,4 @@
+ 
+ #define NR_IRQS	256
+ 
+-#ifdef CONFIG_SMP
+-
+-#define ARCH_HAS_IRQ_PER_CPU
+-
+-#endif
+-
+ #endif /* __ASM_MACH_MIPS_IRQ_H */
+diff -Naur linux-2.6.17.orig/include/asm-mips/mach-rm200/cpu-feature-overrides.h linux-2.6.17/include/asm-mips/mach-rm200/cpu-feature-overrides.h
+--- linux-2.6.17.orig/include/asm-mips/mach-rm200/cpu-feature-overrides.h	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/include/asm-mips/mach-rm200/cpu-feature-overrides.h	2006-06-19 18:16:14.000000000 -0700
+@@ -35,10 +35,8 @@
+ #define cpu_has_nofpuex		0
+ #define cpu_has_64bits		1
+ 
+-#define cpu_has_subset_pcaches	0	/* No S-cache on R5000 I think ...  */
+ #define cpu_dcache_line_size()	32
+ #define cpu_icache_line_size()	32
+-#define cpu_scache_line_size()	0	/* No S-cache on R5000 I think ...  */
+ 
+ #define cpu_has_mips32r1	0
+ #define cpu_has_mips32r2	0
+diff -Naur linux-2.6.17.orig/include/asm-mips/mach-vr41xx/timex.h linux-2.6.17/include/asm-mips/mach-vr41xx/timex.h
+--- linux-2.6.17.orig/include/asm-mips/mach-vr41xx/timex.h	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/include/asm-mips/mach-vr41xx/timex.h	2006-06-19 18:16:14.000000000 -0700
+@@ -0,0 +1,18 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2003 by Ralf Baechle
++ */
++/*
++ * Changes:
++ *  Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
++ *  - CLOCK_TICK_RATE is changed into 32768 from 6144000.
++ */
++#ifndef __ASM_MACH_VR41XX_TIMEX_H
++#define __ASM_MACH_VR41XX_TIMEX_H
++
++#define CLOCK_TICK_RATE		32768
++
++#endif /* __ASM_MACH_VR41XX_TIMEX_H */
+diff -Naur linux-2.6.17.orig/include/asm-mips/mach-wrppmc/mach-gt64120.h linux-2.6.17/include/asm-mips/mach-wrppmc/mach-gt64120.h
+--- linux-2.6.17.orig/include/asm-mips/mach-wrppmc/mach-gt64120.h	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/include/asm-mips/mach-wrppmc/mach-gt64120.h	2006-06-19 18:16:14.000000000 -0700
+@@ -0,0 +1,84 @@
++/*
++ * This is a direct copy of the ev96100.h file, with a global
++ * search and replace.  The numbers are the same.
++ *
++ * The reason I'm duplicating this is so that the 64120/96100
++ * defines won't be confusing in the source code.
++ */
++#ifndef __ASM_MIPS_GT64120_H
++#define __ASM_MIPS_GT64120_H
++
++/*
++ * This is the CPU physical memory map of PPMC Board:
++ *
++ *    0x00000000-0x03FFFFFF      - 64MB SDRAM (SCS[0]#)
++ *    0x1C000000-0x1C000000      - LED (CS0)
++ *    0x1C800000-0x1C800007      - UART 16550 port (CS1)
++ *    0x1F000000-0x1F000000      - MailBox (CS3)
++ *    0x1FC00000-0x20000000      - 4MB Flash (BOOT CS)
++ */
++
++#define WRPPMC_SDRAM_SCS0_BASE	0x00000000
++#define WRPPMC_SDRAM_SCS0_SIZE	0x04000000
++
++#define WRPPMC_UART16550_BASE	0x1C800000
++#define WRPPMC_UART16550_CLOCK	3686400 /* 3.68MHZ */
++
++#define WRPPMC_LED_BASE		0x1C000000
++#define WRPPMC_MBOX_BASE	0x1F000000
++
++#define WRPPMC_BOOTROM_BASE	0x1FC00000
++#define WRPPMC_BOOTROM_SIZE	0x00400000 /* 4M Flash */
++
++#define WRPPMC_MIPS_TIMER_IRQ	7 /* MIPS compare/count timer interrupt */
++#define WRPPMC_UART16550_IRQ	6
++#define WRPPMC_PCI_INTA_IRQ	3
++
++/*
++ * PCI Bus I/O and Memory resources allocation
++ *
++ * NOTE: We only have PCI_0 hose interface
++ */
++#define GT_PCI_MEM_BASE	0x13000000UL
++#define GT_PCI_MEM_SIZE	0x02000000UL
++#define GT_PCI_IO_BASE	0x11000000UL
++#define GT_PCI_IO_SIZE	0x02000000UL
++#define GT_ISA_IO_BASE	PCI_IO_BASE
++
++/*
++ * PCI interrupts will come in on either the INTA or INTD interrups lines,
++ * which are mapped to the #2 and #5 interrupt pins of the MIPS.  On our
++ * boards, they all either come in on IntD or they all come in on IntA, they
++ * aren't mixed. There can be numerous PCI interrupts, so we keep a list of the
++ * "requested" interrupt numbers and go through the list whenever we get an
++ * IntA/D.
++ *
++ * Interrupts < 8 are directly wired to the processor; PCI INTA is 8 and
++ * INTD is 11.
++ */
++#define GT_TIMER	4
++#define GT_INTA		2
++#define GT_INTD		5
++
++#ifndef __ASSEMBLY__
++
++/*
++ * GT64120 internal register space base address
++ */
++extern unsigned long gt64120_base;
++
++#define GT64120_BASE	(gt64120_base)
++
++/* define WRPPMC_EARLY_DEBUG to enable early output something to UART */
++#undef WRPPMC_EARLY_DEBUG
++
++#ifdef WRPPMC_EARLY_DEBUG
++extern void wrppmc_led_on(int mask);
++extern void wrppmc_led_off(int mask);
++extern void wrppmc_early_printk(const char *fmt, ...);
++#else
++#define wrppmc_early_printk(fmt, ...) do {} while (0)
++#endif /* WRPPMC_EARLY_DEBUG */
++
++#endif /* __ASSEMBLY__ */
++#endif /* __ASM_MIPS_GT64120_H */
+diff -Naur linux-2.6.17.orig/include/asm-mips/mipsregs.h linux-2.6.17/include/asm-mips/mipsregs.h
+--- linux-2.6.17.orig/include/asm-mips/mipsregs.h	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/include/asm-mips/mipsregs.h	2006-06-19 18:16:14.000000000 -0700
+@@ -1451,18 +1451,17 @@
+ {
+ 	if ((previous & __EMT_ENABLE))
+ 		__asm__ __volatile__(
+-		"	.set	noreorder				\n"
+ 		"	.set	mips32r2				\n"
+ 		"	.word	0x41600be1		# emt		\n"
+ 		"	ehb						\n"
+-		"	.set	mips0					\n"
+-		"	.set	reorder					\n");
++		"	.set	mips0					\n");
+ }
+ 
+ static inline void __ehb(void)
+ {
+ 	__asm__ __volatile__(
+-	"	ehb							\n");
++	"	.set	mips32r2					\n"
++	"	ehb							\n"		"	.set	mips0						\n");
+ }
+ 
+ /*
+diff -Naur linux-2.6.17.orig/include/asm-mips/mmzone.h linux-2.6.17/include/asm-mips/mmzone.h
+--- linux-2.6.17.orig/include/asm-mips/mmzone.h	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/include/asm-mips/mmzone.h	2006-06-19 18:16:14.000000000 -0700
+@@ -14,17 +14,6 @@
+ #define kvaddr_to_nid(kvaddr)	pa_to_nid(__pa(kvaddr))
+ #define pfn_to_nid(pfn)		pa_to_nid((pfn) << PAGE_SHIFT)
+ 
+-#define pfn_valid(pfn)						\
+-({								\
+- 	unsigned long __pfn = (pfn);				\
+- 	int __n = pfn_to_nid(__pfn);				\
+-	((__n >= 0) ? (__pfn < NODE_DATA(__n)->node_start_pfn +	\
+-		       NODE_DATA(__n)->node_spanned_pages) : 0);\
+-})
+-
+-/* XXX: FIXME -- wli */
+-#define kern_addr_valid(addr)	(0)
+-
+ #endif /* CONFIG_DISCONTIGMEM */
+ 
+ #endif /* _ASM_MMZONE_H_ */
+diff -Naur linux-2.6.17.orig/include/asm-mips/page.h linux-2.6.17/include/asm-mips/page.h
+--- linux-2.6.17.orig/include/asm-mips/page.h	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/include/asm-mips/page.h	2006-06-19 18:16:14.000000000 -0700
+@@ -145,6 +145,25 @@
+ #endif
+ #endif
+ 
++#ifdef CONFIG_FLATMEM
++
++#define pfn_valid(pfn)		((pfn) < max_mapnr)
++
++#elif defined(CONFIG_NEED_MULTIPLE_NODES)
++
++#define pfn_valid(pfn)							\
++({									\
++	unsigned long __pfn = (pfn);					\
++	int __n = pfn_to_nid(__pfn);					\
++	((__n >= 0) ? (__pfn < NODE_DATA(__n)->node_start_pfn +		\
++	                       NODE_DATA(__n)->node_spanned_pages)	\
++	            : 0);						\
++})
++
++#else
++#error Provide a definition of pfn_valid
++#endif
++
+ #define virt_to_page(kaddr)	pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
+ #define virt_addr_valid(kaddr)	pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
+ 
+diff -Naur linux-2.6.17.orig/include/asm-mips/pci/bridge.h linux-2.6.17/include/asm-mips/pci/bridge.h
+--- linux-2.6.17.orig/include/asm-mips/pci/bridge.h	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/include/asm-mips/pci/bridge.h	2006-06-19 18:16:14.000000000 -0700
+@@ -15,6 +15,7 @@
+ #include <linux/types.h>
+ #include <linux/pci.h>
+ #include <asm/xtalk/xwidget.h>		/* generic widget header */
++#include <asm/sn/types.h>
+ 
+ /* I/O page size */
+ 
+@@ -848,4 +849,6 @@
+ extern void register_bridge_irq(unsigned int irq);
+ extern int request_bridge_irq(struct bridge_controller *bc);
+ 
++extern struct pci_ops bridge_pci_ops;
++
+ #endif /* _ASM_PCI_BRIDGE_H */
+diff -Naur linux-2.6.17.orig/include/asm-mips/pgtable.h linux-2.6.17/include/asm-mips/pgtable.h
+--- linux-2.6.17.orig/include/asm-mips/pgtable.h	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/include/asm-mips/pgtable.h	2006-06-19 18:16:14.000000000 -0700
+@@ -379,9 +379,7 @@
+ 	__update_cache(vma, address, pte);
+ }
+ 
+-#ifndef CONFIG_NEED_MULTIPLE_NODES
+ #define kern_addr_valid(addr)	(1)
+-#endif
+ 
+ #ifdef CONFIG_64BIT_PHYS_ADDR
+ extern int remap_pfn_range(struct vm_area_struct *vma, unsigned long from, unsigned long pfn, unsigned long size, pgprot_t prot);
+diff -Naur linux-2.6.17.orig/include/asm-mips/processor.h linux-2.6.17/include/asm-mips/processor.h
+--- linux-2.6.17.orig/include/asm-mips/processor.h	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/include/asm-mips/processor.h	2006-06-19 18:16:14.000000000 -0700
+@@ -71,11 +71,6 @@
+ 
+ typedef __u64 fpureg_t;
+ 
+-struct mips_fpu_hard_struct {
+-	fpureg_t	fpr[NUM_FPU_REGS];
+-	unsigned int	fcr31;
+-};
+-
+ /*
+  * It would be nice to add some more fields for emulator statistics, but there
+  * are a number of fixed offsets in offset.h and elsewhere that would have to
+@@ -83,18 +78,13 @@
+  * the FPU emulator for now.  See asm-mips/fpu_emulator.h.
+  */
+ 
+-struct mips_fpu_soft_struct {
++struct mips_fpu_struct {
+ 	fpureg_t	fpr[NUM_FPU_REGS];
+ 	unsigned int	fcr31;
+ };
+ 
+-union mips_fpu_union {
+-        struct mips_fpu_hard_struct hard;
+-        struct mips_fpu_soft_struct soft;
+-};
+-
+ #define INIT_FPU { \
+-	{{0,},} \
++	{0,} \
+ }
+ 
+ #define NUM_DSP_REGS   6
+@@ -133,7 +123,7 @@
+ 	unsigned long cp0_status;
+ 
+ 	/* Saved fpu/fpu emulator stuff. */
+-	union mips_fpu_union fpu;
++	struct mips_fpu_struct fpu;
+ #ifdef CONFIG_MIPS_MT_FPAFF
+ 	/* Emulated instruction count */
+ 	unsigned long emulated_fp;
+diff -Naur linux-2.6.17.orig/include/asm-mips/qemu.h linux-2.6.17/include/asm-mips/qemu.h
+--- linux-2.6.17.orig/include/asm-mips/qemu.h	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/include/asm-mips/qemu.h	2006-06-19 18:16:14.000000000 -0700
+@@ -21,4 +21,10 @@
+  */
+ #define QEMU_C0_COUNTER_CLOCK	100000000
+ 
++/*
++ * Magic qemu system control location.
++ */
++#define QEMU_RESTART_REG	0xBFBF0000
++#define QEMU_HALT_REG		0xBFBF0004
++
+ #endif /* __ASM_QEMU_H */
+diff -Naur linux-2.6.17.orig/include/asm-mips/rm9k-ocd.h linux-2.6.17/include/asm-mips/rm9k-ocd.h
+--- linux-2.6.17.orig/include/asm-mips/rm9k-ocd.h	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/include/asm-mips/rm9k-ocd.h	2006-06-19 18:16:14.000000000 -0700
+@@ -0,0 +1,56 @@
++/*
++ *  Copyright (C) 2004 by Basler Vision Technologies AG
++ *  Author: Thomas Koeller <thomas.koeller@baslerweb.com>
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License as published by
++ *  the Free Software Foundation; either version 2 of the License, or
++ *  (at your option) any later version.
++ *
++ *  This program is distributed in the hope that it will be useful,
++ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *  GNU General Public License for more details.
++ *
++ *  You should have received a copy of the GNU General Public License
++ *  along with this program; if not, write to the Free Software
++ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
++ */
++
++#if !defined(_ASM_RM9K_OCD_H)
++#define _ASM_RM9K_OCD_H
++
++#include <linux/types.h>
++#include <linux/spinlock.h>
++#include <asm/io.h>
++
++extern volatile void __iomem * const ocd_base;
++extern volatile void __iomem * const titan_base;
++
++#define ocd_addr(__x__)		(ocd_base + (__x__))
++#define titan_addr(__x__)	(titan_base + (__x__))
++#define scram_addr(__x__)	(scram_base + (__x__))
++
++/* OCD register access */
++#define ocd_readl(__offs__) __raw_readl(ocd_addr(__offs__))
++#define ocd_readw(__offs__) __raw_readw(ocd_addr(__offs__))
++#define ocd_readb(__offs__) __raw_readb(ocd_addr(__offs__))
++#define ocd_writel(__val__, __offs__) \
++	__raw_writel((__val__), ocd_addr(__offs__))
++#define ocd_writew(__val__, __offs__) \
++	__raw_writew((__val__), ocd_addr(__offs__))
++#define ocd_writeb(__val__, __offs__) \
++	__raw_writeb((__val__), ocd_addr(__offs__))
++
++/* TITAN register access - 32 bit-wide only */
++#define titan_readl(__offs__) __raw_readl(titan_addr(__offs__))
++#define titan_writel(__val__, __offs__) \
++	__raw_writel((__val__), titan_addr(__offs__))
++
++/* Protect access to shared TITAN registers */
++extern spinlock_t titan_lock;
++extern int titan_irqflags;
++#define lock_titan_regs() spin_lock_irqsave(&titan_lock, titan_irqflags)
++#define unlock_titan_regs() spin_unlock_irqrestore(&titan_lock, titan_irqflags)
++
++#endif	/* !defined(_ASM_RM9K_OCD_H) */
+diff -Naur linux-2.6.17.orig/include/asm-mips/sn/addrs.h linux-2.6.17/include/asm-mips/sn/addrs.h
+--- linux-2.6.17.orig/include/asm-mips/sn/addrs.h	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/include/asm-mips/sn/addrs.h	2006-06-19 18:16:14.000000000 -0700
+@@ -27,13 +27,8 @@
+ 
+ #ifndef __ASSEMBLY__
+ 
+-#if defined(CONFIG_SGI_IO)	/* FIXME */
+-#define PS_UINT_CAST		(__psunsigned_t)
+-#define UINT64_CAST		(__uint64_t)
+-#else	/* CONFIG_SGI_IO */
+ #define PS_UINT_CAST		(unsigned long)
+ #define UINT64_CAST		(unsigned long)
+-#endif	/* CONFIG_SGI_IO */
+ 
+ #define HUBREG_CAST		(volatile hubreg_t *)
+ 
+@@ -253,14 +248,6 @@
+  * for _x.
+  */
+ 
+-#ifdef _STANDALONE
+-
+-/* DO NOT USE THESE DIRECTLY IN THE KERNEL. SEE BELOW. */
+-#define LOCAL_HUB(_x)		(HUBREG_CAST (IALIAS_BASE + (_x)))
+-#define REMOTE_HUB(_n, _x)	(HUBREG_CAST (NODE_SWIN_BASE(_n, 1) +	\
+-					      0x800000 + (_x)))
+-#endif /* _STANDALONE */
+-
+ /*
+  * WARNING:
+  *	When certain Hub chip workaround are defined, it's not sufficient
+@@ -327,20 +314,6 @@
+ 	PHYS_TO_K0(NODE_OFFSET(nasid) | ARCS_SPB_OFFSET)
+ #define ARCS_SPB_SIZE		0x0400
+ 
+-#ifdef _STANDALONE
+-
+-#define ARCS_TVECTOR_OFFSET	0x2800
+-#define ARCS_PVECTOR_OFFSET	0x2c00
+-
+-/*
+- * These addresses are used by the master CPU to install the transfer
+- * and private vectors.  All others use the SPB to find them.
+- */
+-#define TVADDR	(NODE_CAC_BASE(get_nasid()) + ARCS_TVECTOR_OFFSET)
+-#define PVADDR	(NODE_CAC_BASE(get_nasid()) + ARCS_PVECTOR_OFFSET)
+-
+-#endif /* _STANDALONE */
+-
+ #define KLDIR_OFFSET		0x2000
+ #define KLDIR_ADDR(nasid)						\
+ 	TO_NODE_UNCAC((nasid), KLDIR_OFFSET)
+diff -Naur linux-2.6.17.orig/include/asm-mips/sn/fru.h linux-2.6.17/include/asm-mips/sn/fru.h
+--- linux-2.6.17.orig/include/asm-mips/sn/fru.h	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/include/asm-mips/sn/fru.h	2006-06-19 18:16:14.000000000 -0700
+@@ -0,0 +1,44 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Derived from IRIX <sys/SN/SN0/sn0_fru.h>
++ *
++ * Copyright (C) 1992 - 1997, 1999 Silcon Graphics, Inc.
++ * Copyright (C) 1999, 2006 Ralf Baechle (ralf@linux-mips)
++ */
++#ifndef __ASM_SN_FRU_H
++#define __ASM_SN_FRU_H
++
++#define MAX_DIMMS			8	 /* max # of dimm banks */
++#define MAX_PCIDEV			8	 /* max # of pci devices on a pci bus */
++
++typedef unsigned char confidence_t;
++
++typedef struct kf_mem_s {
++	confidence_t km_confidence; /* confidence level that the memory is bad
++				     * is this necessary ?
++				     */
++	confidence_t km_dimm[MAX_DIMMS];
++	                            /* confidence level that dimm[i] is bad
++				     *I think this is the right number
++				     */
++
++} kf_mem_t;
++
++typedef struct kf_cpu_s {
++	confidence_t  	kc_confidence; /* confidence level that cpu is bad */
++	confidence_t  	kc_icache; /* confidence level that instr. cache is bad */
++	confidence_t  	kc_dcache; /* confidence level that data   cache is bad */
++	confidence_t  	kc_scache; /* confidence level that sec.   cache is bad */
++	confidence_t	kc_sysbus; /* confidence level that sysad/cmd/state bus is bad */
++} kf_cpu_t;
++
++typedef struct kf_pci_bus_s {
++	confidence_t	kpb_belief;	/* confidence level  that the  pci bus is bad */
++	confidence_t	kpb_pcidev_belief[MAX_PCIDEV];
++	                                /* confidence level that the pci dev is bad */
++} kf_pci_bus_t;
++
++#endif /* __ASM_SN_FRU_H */
+diff -Naur linux-2.6.17.orig/include/asm-mips/sn/klconfig.h linux-2.6.17/include/asm-mips/sn/klconfig.h
+--- linux-2.6.17.orig/include/asm-mips/sn/klconfig.h	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/include/asm-mips/sn/klconfig.h	2006-06-19 18:16:14.000000000 -0700
+@@ -37,7 +37,7 @@
+ //#include <sys/SN/router.h>
+ // XXX Stolen from <sys/SN/router.h>:
+ #define MAX_ROUTER_PORTS (6)    /* Max. number of ports on a router */
+-#include <asm/sn/sn0/sn0_fru.h>
++#include <asm/sn/fru.h>
+ //#include <sys/graph.h>
+ //#include <sys/xtalk/xbow.h>
+ 
+@@ -54,32 +54,21 @@
+ #include <asm/sn/agent.h>
+ #include <asm/arc/types.h>
+ #include <asm/arc/hinv.h>
+-#if defined(CONFIG_SGI_IO) || defined(CONFIG_SGI_IP35)
++#if defined(CONFIG_SGI_IP35)
+ // The hack file has to be before vector and after sn0_fru....
+ #include <asm/hack.h>
+ #include <asm/sn/vector.h>
+ #include <asm/xtalk/xtalk.h>
+-#endif /* CONFIG_SGI_IO || CONFIG_SGI_IP35 */
++#endif /* CONFIG_SGI_IP35 */
+ #endif /* CONFIG_SGI_IP27 || CONFIG_SGI_IP35 */
+ 
+ #define KLCFGINFO_MAGIC	0xbeedbabe
+ 
+-#ifdef FRUTEST
+-typedef u64 klconf_off_t;
+-#else
+ typedef s32 klconf_off_t;
+-#endif
+ 
+ /*
+  * Some IMPORTANT OFFSETS. These are the offsets on all NODES.
+  */
+-#if 0
+-#define RAMBASE                 0
+-#define ARCSSPB_OFF             0x1000 /* shift it to sys/arcs/spb.h */
+-
+-#define OFF_HWGRAPH 		0
+-#endif
+-
+ #define	MAX_MODULE_ID		255
+ #define SIZE_PAD		4096 /* 4k padding for structures */
+ /*
+@@ -134,15 +123,9 @@
+ 
+ 
+ typedef struct console_s {
+-#if defined(CONFIG_SGI_IO)	/* FIXME */
+-	__psunsigned_t 	uart_base;
+-	__psunsigned_t 	config_base;
+-	__psunsigned_t 	memory_base;
+-#else
+ 	unsigned long 	uart_base;
+ 	unsigned long 	config_base;
+ 	unsigned long 	memory_base;
+-#endif
+ 	short		baud;
+ 	short		flag;
+ 	int		type;
+@@ -174,10 +157,6 @@
+ 
+ 
+ #define KL_CONFIG_HDR(_nasid) 	((kl_config_hdr_t *)(KLCONFIG_ADDR(_nasid)))
+-#if 0
+-#define KL_CONFIG_MALLOC_HDR(_nasid) \
+-                                (KL_CONFIG_HDR(_nasid)->ch_malloc_hdr)
+-#endif
+ #define KL_CONFIG_INFO_OFFSET(_nasid)					\
+         (KL_CONFIG_HDR(_nasid)->ch_board_info)
+ #define KL_CONFIG_INFO_SET_OFFSET(_nasid, _off)				\
+@@ -197,23 +176,13 @@
+ 
+ /* --- New Macros for the changed kl_config_hdr_t structure --- */
+ 
+-#if defined(CONFIG_SGI_IO)
+-#define PTR_CH_MALLOC_HDR(_k)   ((klc_malloc_hdr_t *)\
+-			((__psunsigned_t)_k + (_k->ch_malloc_hdr_off)))
+-#else
+ #define PTR_CH_MALLOC_HDR(_k)   ((klc_malloc_hdr_t *)\
+ 			(unsigned long)_k + (_k->ch_malloc_hdr_off)))
+-#endif
+ 
+ #define KL_CONFIG_CH_MALLOC_HDR(_n)   PTR_CH_MALLOC_HDR(KL_CONFIG_HDR(_n))
+ 
+-#if defined(CONFIG_SGI_IO)
+-#define PTR_CH_CONS_INFO(_k)	((console_t *)\
+-			((__psunsigned_t)_k + (_k->ch_cons_off)))
+-#else
+ #define PTR_CH_CONS_INFO(_k)	((console_t *)\
+ 			((unsigned long)_k + (_k->ch_cons_off)))
+-#endif
+ 
+ #define KL_CONFIG_CH_CONS_INFO(_n)   PTR_CH_CONS_INFO(KL_CONFIG_HDR(_n))
+ 
+@@ -490,14 +459,6 @@
+ #define KLCF_NUM_COMPS(_brd)	((_brd)->brd_numcompts)
+ #define KLCF_MODULE_ID(_brd)	((_brd)->brd_module)
+ 
+-#ifdef FRUTEST
+-
+-#define KLCF_NEXT(_brd) 		((_brd)->brd_next ? (lboard_t *)((_brd)->brd_next):  NULL)
+-#define KLCF_COMP(_brd, _ndx)   	(klinfo_t *)((_brd)->brd_compts[(_ndx)])
+-#define KLCF_COMP_ERROR(_brd, _comp)   	(_brd = _brd , (_comp)->errinfo)
+-
+-#else
+-
+ #define KLCF_NEXT(_brd) 	\
+         ((_brd)->brd_next ? 	\
+ 	 (lboard_t *)(NODE_OFFSET_TO_K1(NASID_GET(_brd), (_brd)->brd_next)):\
+@@ -509,8 +470,6 @@
+ #define KLCF_COMP_ERROR(_brd, _comp)	\
+                (NODE_OFFSET_TO_K1(NASID_GET(_brd), (_comp)->errinfo))
+ 
+-#endif
+-
+ #define KLCF_COMP_TYPE(_comp)	((_comp)->struct_type)
+ #define KLCF_BRIDGE_W_ID(_comp)	((_comp)->physid)	/* Widget ID */
+ 
+@@ -631,18 +590,6 @@
+ 	klconf_off_t	port_offset;
+ } klport_t;
+ 
+-#if 0
+-/*
+- * This is very similar to the klport_s but instead of having a componant
+- * offset it has a board offset.
+- */
+-typedef struct klxbow_port_s {
+-	nasid_t		port_nasid;
+-	unsigned char	port_flag;
+-	klconf_off_t	board_offset;
+-} klxbow_port_t;
+-#endif
+-
+ typedef struct klcpu_s {                          /* CPU */
+ 	klinfo_t 	cpu_info;
+ 	unsigned short 	cpu_prid;	/* Processor PRID value */
+@@ -945,36 +892,6 @@
+ extern lboard_t *find_lboard_class(lboard_t *start, unsigned char brd_class);
+ 
+ 
+-#if defined(CONFIG_SGI_IO)
+-extern xwidgetnum_t nodevertex_widgetnum_get(vertex_hdl_t node_vtx);
+-extern vertex_hdl_t nodevertex_xbow_peer_get(vertex_hdl_t node_vtx);
+-extern lboard_t *find_gfxpipe(int pipenum);
+-extern void setup_gfxpipe_link(vertex_hdl_t vhdl,int pipenum);
+-extern lboard_t *find_lboard_module_class(lboard_t *start, moduleid_t mod,
+-                                               unsigned char brd_class);
+-extern lboard_t *find_nic_lboard(lboard_t *, nic_t);
+-extern lboard_t *find_nic_type_lboard(nasid_t, unsigned char, nic_t);
+-extern lboard_t *find_lboard_modslot(lboard_t *start, moduleid_t mod, slotid_t slot);
+-extern lboard_t *find_lboard_module(lboard_t *start, moduleid_t mod);
+-extern lboard_t *get_board_name(nasid_t nasid, moduleid_t mod, slotid_t slot, char *name);
+-extern int	config_find_nic_router(nasid_t, nic_t, lboard_t **, klrou_t**);
+-extern int	config_find_nic_hub(nasid_t, nic_t, lboard_t **, klhub_t**);
+-extern int	config_find_xbow(nasid_t, lboard_t **, klxbow_t**);
+-extern klcpu_t *get_cpuinfo(cpuid_t cpu);
+-extern int 	update_klcfg_cpuinfo(nasid_t, int);
+-extern void 	board_to_path(lboard_t *brd, char *path);
+-extern moduleid_t get_module_id(nasid_t nasid);
+-extern void 	nic_name_convert(char *old_name, char *new_name);
+-extern int 	module_brds(nasid_t nasid, lboard_t **module_brds, int n);
+-extern lboard_t *brd_from_key(ulong_t key);
+-extern void 	device_component_canonical_name_get(lboard_t *,klinfo_t *,
+-						    char *);
+-extern int	board_serial_number_get(lboard_t *,char *);
+-extern int	is_master_baseio(nasid_t,moduleid_t,slotid_t);
+-extern nasid_t	get_actual_nasid(lboard_t *brd) ;
+-extern net_vec_t klcfg_discover_route(lboard_t *, lboard_t *, int);
+-#else	/* CONFIG_SGI_IO */
+ extern klcpu_t *sn_get_cpuinfo(cpuid_t cpu);
+-#endif	/* CONFIG_SGI_IO */
+ 
+ #endif /* _ASM_SN_KLCONFIG_H */
+diff -Naur linux-2.6.17.orig/include/asm-mips/sn/kldir.h linux-2.6.17/include/asm-mips/sn/kldir.h
+--- linux-2.6.17.orig/include/asm-mips/sn/kldir.h	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/include/asm-mips/sn/kldir.h	2006-06-19 18:16:14.000000000 -0700
+@@ -13,10 +13,6 @@
+ 
+ #include <linux/config.h>
+ 
+-#if defined(CONFIG_SGI_IO)
+-#include <asm/hack.h>
+-#endif
+-
+ /*
+  * The kldir memory area resides at a fixed place in each node's memory and
+  * provides pointers to most other IP27 memory areas.  This allows us to
+@@ -136,8 +132,6 @@
+ #define KLDIR_OFF_STRIDE		0x28
+ #endif /* __ASSEMBLY__ */
+ 
+-#if !defined(CONFIG_SGI_IO)
+-
+ /*
+  * This is defined here because IP27_SYMMON_STK_SIZE must be at least what
+  * we define here.  Since it's set up in the prom.  We can't redefine it later
+@@ -147,7 +141,7 @@
+  */
+ #define SYMMON_STACK_SIZE		0x8000
+ 
+-#if defined (PROM) || defined (SABLE)
++#if defined (PROM)
+ 
+ /*
+  * These defines are prom version dependent.  No code other than the IP27
+@@ -184,7 +178,7 @@
+ #define IP27_FREEMEM_COUNT		1
+ #define IP27_FREEMEM_STRIDE		0
+ 
+-#endif /* PROM || SABLE*/
++#endif /* PROM */
+ /*
+  * There will be only one of these in a partition so the IO6 must set it up.
+  */
+@@ -207,17 +201,11 @@
+ #define KLDIR_ENT_SIZE			0x40
+ #define KLDIR_MAX_ENTRIES		(0x400 / 0x40)
+ 
+-#endif	/* !CONFIG_SGI_IO */
+-
+ #ifndef __ASSEMBLY__
+ typedef struct kldir_ent_s {
+ 	u64		magic;		/* Indicates validity of entry      */
+ 	off_t		offset;		/* Offset from start of node space  */
+-#if defined(CONFIG_SGI_IO)	/* FIXME */
+-	__psunsigned_t	pointer;	/* Pointer to area in some cases    */
+-#else
+ 	unsigned long	pointer;	/* Pointer to area in some cases    */
+-#endif
+ 	size_t		size;		/* Size in bytes 		    */
+ 	u64		count;		/* Repeat count if array, 1 if not  */
+ 	size_t		stride;		/* Stride if array, 0 if not        */
+@@ -227,22 +215,4 @@
+ } kldir_ent_t;
+ #endif /* !__ASSEMBLY__ */
+ 
+-#if defined(CONFIG_SGI_IO)
+-
+-#define KLDIR_ENT_SIZE			0x40
+-#define KLDIR_MAX_ENTRIES		(0x400 / 0x40)
+-
+-/*
+- * The actual offsets of each memory area are machine-dependent
+- */
+-#ifdef CONFIG_SGI_IP27
+-// Not yet #include <asm/sn/sn0/kldir.h>
+-#elif defined(CONFIG_SGI_IP35)
+-#include <asm/sn/sn1/kldir.h>
+-#else
+-#error "kldir.h is currently defined for IP27 and IP35 platforms only"
+-#endif
+-
+-#endif	/* CONFIG_SGI_IO */
+-
+ #endif /* _ASM_SN_KLDIR_H */
+diff -Naur linux-2.6.17.orig/include/asm-mips/sn/sn0/addrs.h linux-2.6.17/include/asm-mips/sn/sn0/addrs.h
+--- linux-2.6.17.orig/include/asm-mips/sn/sn0/addrs.h	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/include/asm-mips/sn/sn0/addrs.h	2006-06-19 18:16:14.000000000 -0700
+@@ -49,7 +49,7 @@
+  * so for now we just use defines bracketed by an ifdef.
+  */
+ 
+-#ifdef CONFIG_SGI_SN0_N_MODE
++#ifdef CONFIG_SGI_SN_N_MODE
+ 
+ #define NODE_SIZE_BITS		31
+ #define BWIN_SIZE_BITS		28
+@@ -63,7 +63,7 @@
+ #define BDDIR_UPPER_MASK	(UINT64_CAST 0x7ffff << 10)
+ #define BDECC_UPPER_MASK	(UINT64_CAST 0x3ffffff << 3)
+ 
+-#else /* !defined(CONFIG_SGI_SN0_N_MODE), assume that M-mode is desired */
++#else /* !defined(CONFIG_SGI_SN_N_MODE), assume that M-mode is desired */
+ 
+ #define NODE_SIZE_BITS		32
+ #define BWIN_SIZE_BITS		29
+@@ -77,7 +77,7 @@
+ #define BDDIR_UPPER_MASK	(UINT64_CAST 0xfffff << 10)
+ #define BDECC_UPPER_MASK	(UINT64_CAST 0x7ffffff << 3)
+ 
+-#endif /* !defined(CONFIG_SGI_SN0_N_MODE) */
++#endif /* !defined(CONFIG_SGI_SN_N_MODE) */
+ 
+ #define NODE_ADDRSPACE_SIZE	(UINT64_CAST 1 << NODE_SIZE_BITS)
+ 
+@@ -85,15 +85,15 @@
+ #define NASID_GET(_pa)		(int) ((UINT64_CAST (_pa) >>		\
+ 					NASID_SHFT) & NASID_BITMASK)
+ 
+-#if !defined(__ASSEMBLY__) && !defined(_STANDALONE)
++#if !defined(__ASSEMBLY__)
+ 
+ #define NODE_SWIN_BASE(nasid, widget)					\
+ 	((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN)		\
+ 	: RAW_NODE_SWIN_BASE(nasid, widget))
+-#else /* __ASSEMBLY__ || _STANDALONE */
++#else /* __ASSEMBLY__ */
+ #define NODE_SWIN_BASE(nasid, widget) \
+      (NODE_IO_BASE(nasid) + (UINT64_CAST (widget) << SWIN_SIZE_BITS))
+-#endif /* __ASSEMBLY__ || _STANDALONE */
++#endif /* __ASSEMBLY__ */
+ 
+ /*
+  * The following definitions pertain to the IO special address
+@@ -143,12 +143,7 @@
+ #define SN0_WIDGET_BASE(_nasid, _wid)	(NODE_SWIN_BASE((_nasid), (_wid)))
+ 
+ /* Turn on sable logging for the processors whose bits are set. */
+-#ifdef SABLE
+-#define SABLE_LOG_TRIGGER(_map)	\
+-		*((volatile hubreg_t *)(IO_BASE + 0x17ffff0)) = (_map)
+-#else
+ #define SABLE_LOG_TRIGGER(_map)
+-#endif /* SABLE */
+ 
+ #ifndef __ASSEMBLY__
+ #define KERN_NMI_ADDR(nasid, slice)					\
+@@ -281,76 +276,6 @@
+ 
+ #define _ARCSPROM
+ 
+-#ifdef _STANDALONE
+-
+-/*
+- * The PROM needs to pass the device base address and the
+- * device pci cfg space address to the device drivers during
+- * install. The COMPONENT->Key field is used for this purpose.
+- * Macros needed by SN0 device drivers to convert the
+- * COMPONENT->Key field to the respective base address.
+- * Key field looks as follows:
+- *
+- *  +----------------------------------------------------+
+- *  |devnasid | widget  |pciid |hubwidid|hstnasid | adap |
+- *  |   2     |   1     |  1   |   1    |    2    |   1  |
+- *  +----------------------------------------------------+
+- *  |         |         |      |        |         |      |
+- *  64        48        40     32       24        8      0
+- *
+- * These are used by standalone drivers till the io infrastructure
+- * is in place.
+- */
+-
+-#ifndef __ASSEMBLY__
+-
+-#define uchar unsigned char
+-
+-#define KEY_DEVNASID_SHFT  48
+-#define KEY_WIDID_SHFT	   40
+-#define KEY_PCIID_SHFT	   32
+-#define KEY_HUBWID_SHFT	   24
+-#define KEY_HSTNASID_SHFT  8
+-
+-#define MK_SN0_KEY(nasid, widid, pciid) \
+-			((((__psunsigned_t)nasid)<< KEY_DEVNASID_SHFT |\
+-				((__psunsigned_t)widid) << KEY_WIDID_SHFT) |\
+-				((__psunsigned_t)pciid) << KEY_PCIID_SHFT)
+-
+-#define ADD_HUBWID_KEY(key,hubwid)\
+-			(key|=((__psunsigned_t)hubwid << KEY_HUBWID_SHFT))
+-
+-#define ADD_HSTNASID_KEY(key,hstnasid)\
+-			(key|=((__psunsigned_t)hstnasid << KEY_HSTNASID_SHFT))
+-
+-#define GET_DEVNASID_FROM_KEY(key)	((short)(key >> KEY_DEVNASID_SHFT))
+-#define GET_WIDID_FROM_KEY(key)		((uchar)(key >> KEY_WIDID_SHFT))
+-#define GET_PCIID_FROM_KEY(key)		((uchar)(key >> KEY_PCIID_SHFT))
+-#define GET_HUBWID_FROM_KEY(key)	((uchar)(key >> KEY_HUBWID_SHFT))
+-#define GET_HSTNASID_FROM_KEY(key)	((short)(key >> KEY_HSTNASID_SHFT))
+-
+-#define PCI_64_TARGID_SHFT		60
+-
+-#define GET_PCIBASE_FROM_KEY(key)  (NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\
+-					GET_WIDID_FROM_KEY(key))\
+-					| BRIDGE_DEVIO(GET_PCIID_FROM_KEY(key)))
+-
+-#define GET_PCICFGBASE_FROM_KEY(key) \
+-			(NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\
+-			      GET_WIDID_FROM_KEY(key))\
+-			| BRIDGE_TYPE0_CFG_DEV(GET_PCIID_FROM_KEY(key)))
+-
+-#define GET_WIDBASE_FROM_KEY(key) \
+-                        (NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\
+-                              GET_WIDID_FROM_KEY(key)))
+-
+-#define PUT_INSTALL_STATUS(c,s)		c->Revision = s
+-#define GET_INSTALL_STATUS(c)		c->Revision
+-
+-#endif /* !__ASSEMBLY__ */
+-
+-#endif /* _STANDALONE */
+-
+ #if defined (HUB_ERR_STS_WAR)
+ 
+ #define ERR_STS_WAR_REGISTER	IIO_IIBUSERR
+diff -Naur linux-2.6.17.orig/include/asm-mips/sn/sn0/arch.h linux-2.6.17/include/asm-mips/sn/sn0/arch.h
+--- linux-2.6.17.orig/include/asm-mips/sn/sn0/arch.h	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/include/asm-mips/sn/sn0/arch.h	2006-06-19 18:16:14.000000000 -0700
+@@ -13,8 +13,6 @@
+ 
+ #include <linux/config.h>
+ 
+-#ifndef SABLE
+-
+ #ifndef SN0XXL  /* 128 cpu SMP max */
+ /*
+  * This is the maximum number of nodes that can be part of a kernel.
+@@ -54,25 +52,16 @@
+  */
+ #define MAX_PARTITIONS		MAX_REGIONS
+ 
+-
+-#else
+-
+-#define MAX_COMPACT_NODES	4
+-#define MAX_NASIDS		4
+-#define MAXCPUS			8
+-
+-#endif
+-
+ #define NASID_MASK_BYTES	((MAX_NASIDS + 7) / 8)
+ 
+ /*
+  * Slot constants for SN0
+  */
+-#ifdef CONFIG_SGI_SN0_N_MODE
++#ifdef CONFIG_SGI_SN_N_MODE
+ #define MAX_MEM_SLOTS   16                      /* max slots per node */
+-#else /* !CONFIG_SGI_SN0_N_MODE, assume M_MODE */
++#else /* !CONFIG_SGI_SN_N_MODE, assume CONFIG_SGI_SN_M_MODE */
+ #define MAX_MEM_SLOTS   32                      /* max slots per node */
+-#endif /* defined(N_MODE) */
++#endif /* CONFIG_SGI_SN_M_MODE */
+ 
+ #define SLOT_SHIFT      	(27)
+ #define SLOT_MIN_MEM_SIZE	(32*1024*1024)
+diff -Naur linux-2.6.17.orig/include/asm-mips/sn/sn0/hub.h linux-2.6.17/include/asm-mips/sn/sn0/hub.h
+--- linux-2.6.17.orig/include/asm-mips/sn/sn0/hub.h	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/include/asm-mips/sn/sn0/hub.h	2006-06-19 18:16:14.000000000 -0700
+@@ -31,10 +31,6 @@
+ #include <asm/sn/sn0/hubni.h>
+ //#include <asm/sn/sn0/hubcore.h>
+ 
+-#ifdef SABLE
+-#define IP27_NO_HUBUART_INT	1
+-#endif
+-
+ /* Translation of uncached attributes */
+ #define	UATTR_HSPEC	0
+ #define	UATTR_IO	1
+diff -Naur linux-2.6.17.orig/include/asm-mips/sn/sn0/hubio.h linux-2.6.17/include/asm-mips/sn/sn0/hubio.h
+--- linux-2.6.17.orig/include/asm-mips/sn/sn0/hubio.h	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/include/asm-mips/sn/sn0/hubio.h	2006-06-19 18:16:14.000000000 -0700
+@@ -486,22 +486,6 @@
+ #define ICRBN_A_CERR_SHFT	54
+ #define ICRBN_A_ERR_MASK	0x3ff
+ 
+-#if 0	/* Disabled, this causes namespace polution and break allmodconfig */
+-/*
+- * Easy access macros.
+- */
+-#define	a_error		icrba_fields_s.error
+-#define	a_ecode		icrba_fields_s.ecode
+-#define	a_lnetuce	icrba_fields_s.lnetuce
+-#define	a_mark		icrba_fields_s.mark
+-#define	a_xerr		icrba_fields_s.xerr
+-#define	a_sidn		icrba_fields_s.sidn
+-#define	a_tnum		icrba_fields_s.tnum
+-#define	a_addr		icrba_fields_s.addr
+-#define	a_valid		icrba_fields_s.valid
+-#define	a_iow		icrba_fields_s.iow
+-#endif
+-
+ #endif /* !__ASSEMBLY__ */
+ 
+ #define	IIO_ICRB_ADDR_SHFT	2	/* Shift to get proper address */
+diff -Naur linux-2.6.17.orig/include/asm-mips/sn/sn0/hubmd.h linux-2.6.17/include/asm-mips/sn/sn0/hubmd.h
+--- linux-2.6.17.orig/include/asm-mips/sn/sn0/hubmd.h	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/include/asm-mips/sn/sn0/hubmd.h	2006-06-19 18:16:14.000000000 -0700
+@@ -92,7 +92,7 @@
+ #define MD_UREG1_14		0x2200f0 /* uController/UART 1 register     */
+ #define MD_UREG1_15		0x2200f8 /* uController/UART 1 register     */
+ 
+-#ifdef CONFIG_SGI_SN0_N_MODE
++#ifdef CONFIG_SGI_SN_N_MODE
+ #define MD_MEM_BANKS		4	 /* 4 banks of memory max in N mode */
+ #else
+ #define MD_MEM_BANKS		8	 /* 8 banks of memory max in M mode */
+diff -Naur linux-2.6.17.orig/include/asm-mips/sn/sn0/hubpi.h linux-2.6.17/include/asm-mips/sn/sn0/hubpi.h
+--- linux-2.6.17.orig/include/asm-mips/sn/sn0/hubpi.h	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/include/asm-mips/sn/sn0/hubpi.h	2006-06-19 18:16:14.000000000 -0700
+@@ -398,24 +398,6 @@
+ 
+ /* PI_RT_FILTER_CTRL mask and shift definitions */
+ 
+-#if 0
+-/*
+- * XXX - This register's definition has changed, but it's only implemented
+- * in Hub 2.
+- */
+-#define PRFC_DROP_COUNT_SHFT	27
+-#define PRFC_DROP_COUNT_MASK	(UINT64_CAST 0x3ff << 27)
+-#define PRFC_DROP_CTR_SHFT	18
+-#define PRFC_DROP_CTR_MASK	(UINT64_CAST 0x1ff << 18)
+-#define PRFC_MASK_ENABLE_SHFT	10
+-#define PRFC_MASK_ENABLE_MASK	(UINT64_CAST 0x7f << 10)
+-#define PRFC_MASK_CTR_SHFT	2
+-#define PRFC_MASK_CTR_MASK	(UINT64_CAST 0xff << 2)
+-#define PRFC_OFFSET_SHFT	0
+-#define PRFC_OFFSET_MASK	(UINT64_CAST 3)
+-#endif /* 0 */
+-
+-
+ /*
+  * Bits for NACK_CNT_A/B and NACK_CMP
+  */
+diff -Naur linux-2.6.17.orig/include/asm-mips/sn/sn0/ip27.h linux-2.6.17/include/asm-mips/sn/sn0/ip27.h
+--- linux-2.6.17.orig/include/asm-mips/sn/sn0/ip27.h	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/include/asm-mips/sn/sn0/ip27.h	2006-06-19 18:16:14.000000000 -0700
+@@ -6,7 +6,7 @@
+  * Derived from IRIX <sys/SN/SN0/IP27.h>.
+  *
+  * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
+- * Copyright (C) 1999 by Ralf Baechle
++ * Copyright (C) 1999, 2006 by Ralf Baechle
+  */
+ #ifndef _ASM_SN_SN0_IP27_H
+ #define _ASM_SN_SN0_IP27_H
+@@ -82,11 +82,4 @@
+ #define SEND_NMI(_nasid, _slice)	\
+           REMOTE_HUB_S((_nasid),  (PI_NMI_A + ((_slice) * PI_NMI_OFFSET)), 1)
+ 
+-/* Sanity hazzard ...  Below all the Origin hacks are following.  */
+-
+-#define SN00_BRIDGE		0x9200000008000000
+-#define SN00I_BRIDGE0		0x920000000b000000
+-#define SN00I_BRIDGE1		0x920000000e000000
+-#define SN00I_BRIDGE2		0x920000000f000000
+-
+ #endif /* _ASM_SN_SN0_IP27_H */
+diff -Naur linux-2.6.17.orig/include/asm-mips/sn/sn0/sn0_fru.h linux-2.6.17/include/asm-mips/sn/sn0/sn0_fru.h
+--- linux-2.6.17.orig/include/asm-mips/sn/sn0/sn0_fru.h	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/include/asm-mips/sn/sn0/sn0_fru.h	1969-12-31 16:00:00.000000000 -0800
+@@ -1,44 +0,0 @@
+-/*
+- * This file is subject to the terms and conditions of the GNU General Public
+- * License.  See the file "COPYING" in the main directory of this archive
+- * for more details.
+- *
+- * Derived from IRIX <sys/SN/SN0/sn0_fru.h>
+- *
+- * Copyright (C) 1992 - 1997, 1999 Silcon Graphics, Inc.
+- * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
+- */
+-#ifndef _ASM_SN_SN0_SN0_FRU_H
+-#define _ASM_SN_SN0_SN0_FRU_H
+-
+-#define MAX_DIMMS			8	 /* max # of dimm banks */
+-#define MAX_PCIDEV			8	 /* max # of pci devices on a pci bus */
+-
+-typedef unsigned char confidence_t;
+-
+-typedef struct kf_mem_s {
+-	confidence_t km_confidence; /* confidence level that the memory is bad
+-				     * is this necessary ?
+-				     */
+-	confidence_t km_dimm[MAX_DIMMS];
+-	                            /* confidence level that dimm[i] is bad
+-				     *I think this is the right number
+-				     */
+-
+-} kf_mem_t;
+-
+-typedef struct kf_cpu_s {
+-	confidence_t  	kc_confidence; /* confidence level that cpu is bad */
+-	confidence_t  	kc_icache; /* confidence level that instr. cache is bad */
+-	confidence_t  	kc_dcache; /* confidence level that data   cache is bad */
+-	confidence_t  	kc_scache; /* confidence level that sec.   cache is bad */
+-	confidence_t	kc_sysbus; /* confidence level that sysad/cmd/state bus is bad */
+-} kf_cpu_t;
+-
+-typedef struct kf_pci_bus_s {
+-	confidence_t	kpb_belief;	/* confidence level  that the  pci bus is bad */
+-	confidence_t	kpb_pcidev_belief[MAX_PCIDEV];
+-	                                /* confidence level that the pci dev is bad */
+-} kf_pci_bus_t;
+-
+-#endif /* _ASM_SN_SN0_SN0_FRU_H */
+diff -Naur linux-2.6.17.orig/include/asm-mips/sni.h linux-2.6.17/include/asm-mips/sni.h
+--- linux-2.6.17.orig/include/asm-mips/sni.h	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/include/asm-mips/sni.h	2006-06-19 18:16:14.000000000 -0700
+@@ -15,9 +15,6 @@
+ /*
+  * ASIC PCI registers for little endian configuration.
+  */
+-#ifndef __MIPSEL__
+-#error "Fix me for big endian"
+-#endif
+ #define PCIMT_UCONF		0xbfff0000
+ #define PCIMT_IOADTIMEOUT2	0xbfff0008
+ #define PCIMT_IOMEMCONF		0xbfff0010
+@@ -51,9 +48,9 @@
+ #define PCIMT_PCI_CONF		0xbfff0100
+ 
+ /*
+- * Data port for the PCI bus.
++ * Data port for the PCI bus in IO space
+  */
+-#define PCIMT_CONFIG_DATA	0xb4000cfc
++#define PCIMT_CONFIG_DATA	0x0cfc
+ 
+ /*
+  * Board specific registers
+diff -Naur linux-2.6.17.orig/include/asm-mips/stackframe.h linux-2.6.17/include/asm-mips/stackframe.h
+--- linux-2.6.17.orig/include/asm-mips/stackframe.h	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/include/asm-mips/stackframe.h	2006-06-19 18:16:14.000000000 -0700
+@@ -305,7 +305,7 @@
+ 		mfc0	v0, CP0_TCSTATUS
+ 		ori	v0, TCSTATUS_IXMT
+ 		mtc0	v0, CP0_TCSTATUS
+-		ehb
++		_ehb
+ 		DMT	5				# dmt a1
+ 		jal	mips_ihb
+ #endif /* CONFIG_MIPS_MT_SMTC */
+@@ -326,14 +326,14 @@
+  * restore TCStatus.IXMT.
+  */
+ 		LONG_L	v1, PT_TCSTATUS(sp)
+-		ehb
++		_ehb
+ 		mfc0	v0, CP0_TCSTATUS
+ 		andi	v1, TCSTATUS_IXMT
+ 		/* We know that TCStatua.IXMT should be set from above */
+ 		xori	v0, v0, TCSTATUS_IXMT
+ 		or	v0, v0, v1
+ 		mtc0	v0, CP0_TCSTATUS
+-		ehb
++		_ehb
+ 		andi	a1, a1, VPECONTROL_TE
+ 		beqz	a1, 1f
+ 		emt
+@@ -412,7 +412,7 @@
+ 		/* Clear TKSU, leave IXMT */
+ 		xori	t0, 0x00001800
+ 		mtc0	t0, CP0_TCSTATUS
+-		ehb
++		_ehb
+ 		/* We need to leave the global IE bit set, but clear EXL...*/
+ 		mfc0	t0, CP0_STATUS
+ 		ori	t0, ST0_EXL | ST0_ERL
+@@ -439,7 +439,7 @@
+ 		 * and enable interrupts only for the
+ 		 * current TC, using the TCStatus register.
+ 		 */
+-		ehb
++		_ehb
+ 		mfc0	t0,CP0_TCSTATUS
+ 		/* Fortunately CU 0 is in the same place in both registers */
+ 		/* Set TCU0, TKSU (for later inversion) and IXMT */
+@@ -448,7 +448,7 @@
+ 		/* Clear TKSU *and* IXMT */
+ 		xori	t0, 0x00001c00
+ 		mtc0	t0, CP0_TCSTATUS
+-		ehb
++		_ehb
+ 		/* We need to leave the global IE bit set, but clear EXL...*/
+ 		mfc0	t0, CP0_STATUS
+ 		ori	t0, ST0_EXL
+@@ -480,7 +480,7 @@
+ 		andi	v1, v0, TCSTATUS_IXMT
+ 		ori	v0, TCSTATUS_IXMT
+ 		mtc0	v0, CP0_TCSTATUS
+-		ehb
++		_ehb
+ 		DMT	2				# dmt	v0
+ 		/*
+ 		 * We don't know a priori if ra is "live"
+@@ -496,7 +496,7 @@
+ 		xori	t0, 0x1e
+ 		mtc0	t0, CP0_STATUS
+ #ifdef CONFIG_MIPS_MT_SMTC
+-		ehb
++		_ehb
+ 		andi	v0, v0, VPECONTROL_TE
+ 		beqz	v0, 2f
+ 		nop	/* delay slot */
+diff -Naur linux-2.6.17.orig/include/asm-mips/unistd.h linux-2.6.17/include/asm-mips/unistd.h
+--- linux-2.6.17.orig/include/asm-mips/unistd.h	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/include/asm-mips/unistd.h	2006-06-19 18:16:14.000000000 -0700
+@@ -326,16 +326,17 @@
+ #define __NR_unshare			(__NR_Linux + 303)
+ #define __NR_splice			(__NR_Linux + 304)
+ #define __NR_sync_file_range		(__NR_Linux + 305)
++#define __NR_tee			(__NR_Linux + 306)
+ 
+ /*
+  * Offset of the last Linux o32 flavoured syscall
+  */
+-#define __NR_Linux_syscalls		305
++#define __NR_Linux_syscalls		306
+ 
+ #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
+ 
+ #define __NR_O32_Linux			4000
+-#define __NR_O32_Linux_syscalls		305
++#define __NR_O32_Linux_syscalls		306
+ 
+ #if _MIPS_SIM == _MIPS_SIM_ABI64
+ 
+@@ -608,16 +609,17 @@
+ #define __NR_unshare			(__NR_Linux + 262)
+ #define __NR_splice			(__NR_Linux + 263)
+ #define __NR_sync_file_range		(__NR_Linux + 264)
++#define __NR_tee			(__NR_Linux + 265)
+ 
+ /*
+  * Offset of the last Linux 64-bit flavoured syscall
+  */
+-#define __NR_Linux_syscalls		264
++#define __NR_Linux_syscalls		265
+ 
+ #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
+ 
+ #define __NR_64_Linux			5000
+-#define __NR_64_Linux_syscalls		264
++#define __NR_64_Linux_syscalls		265
+ 
+ #if _MIPS_SIM == _MIPS_SIM_NABI32
+ 
+@@ -894,16 +896,17 @@
+ #define __NR_unshare			(__NR_Linux + 266)
+ #define __NR_splice			(__NR_Linux + 267)
+ #define __NR_sync_file_range		(__NR_Linux + 268)
++#define __NR_tee			(__NR_Linux + 269)
+ 
+ /*
+  * Offset of the last N32 flavoured syscall
+  */
+-#define __NR_Linux_syscalls		268
++#define __NR_Linux_syscalls		269
+ 
+ #endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
+ 
+ #define __NR_N32_Linux			6000
+-#define __NR_N32_Linux_syscalls		268
++#define __NR_N32_Linux_syscalls		269
+ 
+ #ifndef __ASSEMBLY__
+ 
+diff -Naur linux-2.6.17.orig/include/asm-mips/war.h linux-2.6.17/include/asm-mips/war.h
+--- linux-2.6.17.orig/include/asm-mips/war.h	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/include/asm-mips/war.h	2006-06-19 18:16:14.000000000 -0700
+@@ -172,7 +172,8 @@
+  * On the RM9000 there is a problem which makes the CreateDirtyExclusive
+  * cache operation unusable on SMP systems.
+  */
+-#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_PMC_YOSEMITE)
++#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_PMC_YOSEMITE) || \
++    defined(CONFIG_BASLER_EXCITE)
+ #define  RM9000_CDEX_SMP_WAR		1
+ #endif
+ 
+@@ -182,7 +183,7 @@
+  * being fetched may case spurious exceptions.
+  */
+ #if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_MOMENCO_OCELOT_3) || \
+-    defined(CONFIG_PMC_YOSEMITE)
++    defined(CONFIG_PMC_YOSEMITE) || defined(CONFIG_BASLER_EXCITE)
+ #define ICACHE_REFILLS_WORKAROUND_WAR	1
+ #endif
+ 
+diff -Naur linux-2.6.17.orig/include/linux/elf.h linux-2.6.17/include/linux/elf.h
+--- linux-2.6.17.orig/include/linux/elf.h	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/include/linux/elf.h	2006-06-19 18:16:14.000000000 -0700
+@@ -67,7 +67,7 @@
+ 
+ #define EM_MIPS		8	/* MIPS R3000 (officially, big-endian only) */
+ 
+-#define EM_MIPS_RS4_BE 10	/* MIPS R4000 big-endian */
++#define EM_MIPS_RS3_LE 10	/* MIPS R3000 little-endian */
+ 
+ #define EM_PARISC      15	/* HPPA */
+ 
+diff -Naur linux-2.6.17.orig/include/linux/mc146818rtc.h linux-2.6.17/include/linux/mc146818rtc.h
+--- linux-2.6.17.orig/include/linux/mc146818rtc.h	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/include/linux/mc146818rtc.h	2006-06-19 18:16:14.000000000 -0700
+@@ -89,4 +89,12 @@
+ # define RTC_VRT 0x80		/* valid RAM and time */
+ /**********************************************************************/
+ 
++#ifndef RTC_IO_EXTENT
++#define RTC_IO_EXTENT	0x8
++#endif
++
++#ifndef RTC_IOMAPPED
++#define RTC_IOMAPPED	1	/* Default to I/O mapping. */
++#endif
++
+ #endif /* _MC146818RTC_H */
+diff -Naur linux-2.6.17.orig/include/linux/pci_ids.h linux-2.6.17/include/linux/pci_ids.h
+--- linux-2.6.17.orig/include/linux/pci_ids.h	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/include/linux/pci_ids.h	2006-06-19 18:16:14.000000000 -0700
+@@ -1569,6 +1569,9 @@
+ #define PCI_VENDOR_ID_SATSAGEM		0x1267
+ #define PCI_DEVICE_ID_SATSAGEM_NICCY	0x1016
+ 
++#define PCI_VENDOR_ID_SILICON_MOTION		0x126f
++#define PCI_DEVICE_ID_SM501_VOYAGER_GX_REV_AA	0x0501
++#define PCI_DEVICE_ID_SM501_VOYAGER_GX_REV_B	0x0510
+ 
+ #define PCI_VENDOR_ID_ENSONIQ		0x1274
+ #define PCI_DEVICE_ID_ENSONIQ_CT5880	0x5880
+diff -Naur linux-2.6.17.orig/include/linux/serial.h linux-2.6.17/include/linux/serial.h
+--- linux-2.6.17.orig/include/linux/serial.h	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/include/linux/serial.h	2006-06-19 18:16:14.000000000 -0700
+@@ -76,7 +76,8 @@
+ #define PORT_16654	11
+ #define PORT_16850	12
+ #define PORT_RSA	13	/* RSA-DV II/S card */
+-#define PORT_MAX	13
++#define PORT_SB1250	14
++#define PORT_MAX	14
+ 
+ #define SERIAL_IO_PORT	0
+ #define SERIAL_IO_HUB6	1
+diff -Naur linux-2.6.17.orig/include/linux/serial_ip3106.h linux-2.6.17/include/linux/serial_ip3106.h
+--- linux-2.6.17.orig/include/linux/serial_ip3106.h	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/include/linux/serial_ip3106.h	2006-06-19 18:16:14.000000000 -0700
+@@ -78,4 +78,16 @@
+ #define IP3106_UART_FIFO_RXFIFO		0x00001F00
+ #define IP3106_UART_FIFO_RBRTHR		0x000000FF
+ 
++#define ip3106_lcr(base,port)    *(volatile u32 *)(base+(port*0x1000) + 0x000)
++#define ip3106_mcr(base, port)   *(volatile u32 *)(base+(port*0x1000) + 0x004)
++#define ip3106_baud(base, port)  *(volatile u32 *)(base+(port*0x1000) + 0x008)
++#define ip3106_cfg(base, port)   *(volatile u32 *)(base+(port*0x1000) + 0x00C)
++#define ip3106_fifo(base, port)	 *(volatile u32 *)(base+(port*0x1000) + 0x028)
++#define ip3106_istat(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFE0)
++#define ip3106_ien(base, port)   *(volatile u32 *)(base+(port*0x1000) + 0xFE4)
++#define ip3106_iclr(base, port)  *(volatile u32 *)(base+(port*0x1000) + 0xFE8)
++#define ip3106_iset(base, port)  *(volatile u32 *)(base+(port*0x1000) + 0xFEC)
++#define ip3106_pd(base, port)    *(volatile u32 *)(base+(port*0x1000) + 0xFF4)
++#define ip3106_mid(base, port)   *(volatile u32 *)(base+(port*0x1000) + 0xFFC)
++
+ #endif
+diff -Naur linux-2.6.17.orig/sound/oss/au1550_ac97.c linux-2.6.17/sound/oss/au1550_ac97.c
+--- linux-2.6.17.orig/sound/oss/au1550_ac97.c	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/sound/oss/au1550_ac97.c	2006-06-19 18:16:14.000000000 -0700
+@@ -60,6 +60,7 @@
+ #include <asm/mach-au1x00/au1000.h>
+ #include <asm/mach-au1x00/au1xxx_psc.h>
+ #include <asm/mach-au1x00/au1xxx_dbdma.h>
++#include <asm/mach-pb1x00/pb1550.h>
+ 
+ #undef OSS_DOCUMENTED_MIXER_SEMANTICS
+ 
+diff -Naur linux-2.6.17.orig/sound/oss/au1550_i2s.c linux-2.6.17/sound/oss/au1550_i2s.c
+--- linux-2.6.17.orig/sound/oss/au1550_i2s.c	1969-12-31 16:00:00.000000000 -0800
++++ linux-2.6.17/sound/oss/au1550_i2s.c	2006-06-19 18:16:14.000000000 -0700
+@@ -0,0 +1,2029 @@
++/*
++ *      au1550_i2s.c  --  Sound driver for Alchemy Au1550 MIPS
++ *			Internet Edge Processor.
++ *
++ * Copyright 2004 Embedded Edge, LLC
++ *	dan@embeddededge.com
++ * Copyright 2005 Matt Porter <mporter@kernel.crashing.org>
++ *
++ * Mostly copied from the au1550_psc.c driver and some from the
++ * PowerMac dbdma driver.
++ * We assume the processor can do memory coherent DMA.
++ *
++ * WM8731 mixer support, codec framework, cleanup, and 2.6 port
++ * Matt Porter <mporter@kernel.crashing.org>
++ *
++ * The SMBus (I2C) is required for the control of the
++ * appears at I2C address 0x36 (I2C binary 0011011).  The Pb1550
++ * uses the Wolfson WM8731 codec, which is controlled over the I2C.
++ * It's connected to a 12MHz clock, so we can only reliably support
++ * 96KHz, 48KHz, 32KHz, and 8KHz data rates.  Variable rate audio is
++ * unsupported, we currently force it to 48KHz.
++ *
++ *  This program is free software; you can redistribute  it and/or modify it
++ *  under  the terms of  the GNU General  Public License as published by the
++ *  Free Software Foundation;  either version 2 of the  License, or (at your
++ *  option) any later version.
++ *
++ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
++ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
++ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
++ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
++ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
++ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
++ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
++ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
++ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
++ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ *  You should have received a copy of the  GNU General Public License along
++ *  with this program; if not, write  to the Free Software Foundation, Inc.,
++ *  675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++#include <linux/module.h>
++#include <linux/string.h>
++#include <linux/ioport.h>
++#include <linux/sched.h>
++#include <linux/delay.h>
++#include <linux/fs.h>
++#include <linux/hardirq.h>
++#include <linux/sound.h>
++#include <linux/slab.h>
++#include <linux/soundcard.h>
++#include <linux/init.h>
++#include <linux/poll.h>
++#include <linux/pci.h>
++#include <linux/bitops.h>
++#include <linux/proc_fs.h>
++#include <linux/spinlock.h>
++#include <linux/smp_lock.h>
++
++#include <asm/io.h>
++#include <asm/uaccess.h>
++#include <asm/hardirq.h>
++
++#include <asm/mach-au1x00/au1000.h>
++#include <asm/mach-au1x00/au1xxx_psc.h>
++#include <asm/mach-au1x00/au1xxx_dbdma.h>
++#include <asm/mach-pb1x00/pb1550.h>
++
++#undef OSS_DOCUMENTED_MIXER_SEMANTICS
++
++#define AU1550_MODULE_NAME "Au1550 I2S Audio"
++#define PFX AU1550_MODULE_NAME
++
++/* Define this if you want to try running at the 44.1 KHz rate.
++ * It's just a little off, I think it's actually 44117 or something.
++ * I did this for debugging, since many programs, including this
++ * driver, will try to upsample from 44.1 to 48 KHz.
++ * Seems to work well, we'll just leave it this way.
++ */
++#define TRY_441KHz
++
++#ifdef TRY_441KHz
++#define SAMP_RATE	44100
++#else
++#define SAMP_RATE	48000
++#endif
++
++/* The number of DBDMA ring descriptors to allocate.  No sense making
++ * this too large....if you can't keep up with a few you aren't likely
++ * to be able to with lots of them, either.
++ */
++#define NUM_DBDMA_DESCRIPTORS 4
++
++#define pr_error(format, arg...) printk(KERN_ERR PFX ": " format "\n" , ## arg)
++
++static void
++au1550_delay(int msec)
++{
++	unsigned long   tmo;
++	signed long     tmo2;
++
++	if (in_interrupt())
++		return;
++
++	tmo = jiffies + (msec * HZ) / 1000;
++	for (;;) {
++		tmo2 = tmo - jiffies;
++		if (tmo2 <= 0)
++			break;
++		schedule_timeout(tmo2);
++	}
++}
++
++/*
++ * Codec framework. If somebody supports another codec, they
++ * should hopefully be able to define another struct i2s_codec
++ * definition, and #ifdef the support for it and the WM8731 so
++ * they can be selected via a CONFIG option. For now, we just
++ * hardcode WM8731_CODEC.
++ */
++#define i2s_supported_mixer(CODEC,FOO) ((FOO >= 0) && \
++                                    (FOO < SOUND_MIXER_NRDEVICES) && \
++                                    (CODEC)->supported_mixers & (1<<FOO) )
++
++struct i2s_codec {
++	int			modcnt;
++	int			supported_mixers;
++	int			stereo_mixers;
++	int			record_sources;
++	unsigned int		mixer_state[SOUND_MIXER_NRDEVICES];
++	void			*data;
++	int			(*set_mixer) (struct i2s_codec *codec, unsigned int oss_mixer, unsigned int val);
++	void			(*init_codec) (struct i2s_codec *codec);
++};
++
++#define WM8731_CODEC
++#ifdef WM8731_CODEC
++/*
++ * WM8731 codec support
++ */
++#define WM8731_SUPPORTED_MASK (WM8731_STEREO_MASK|WM8731_RECORD_MASK)
++#define WM8731_STEREO_MASK (SOUND_MASK_VOLUME|SOUND_MASK_LINE)
++#define WM8731_RECORD_MASK (SOUND_MASK_MIC|SOUND_MASK_LINE)
++
++static struct codec_data {
++	u16			audio_path;
++} wm8731_data;
++
++static void
++wm8731_wrcodec(u8 ctlreg, u8 val)
++{
++	int	rcnt;
++	extern int pb1550_wm_codec_write(u8 addr, u8 reg, u8 val);
++
++	/* The codec is a write only device, with a 16-bit control/data
++	 * word.  Although it is written as two bytes on the I2C, the
++	 * format is actually 7 bits of register and 9 bits of data.
++	 * The ls bit of the first byte is the ms bit of the data.
++	 */
++	rcnt = 0;
++	while ((pb1550_wm_codec_write((0x36 >> 1), ctlreg, val) != 1)
++							&& (rcnt < 50)) {
++		rcnt++;
++	}
++}
++
++static int
++wm8731_set_mixer(struct i2s_codec *codec, unsigned int oss_mixer, unsigned int val)
++{
++	unsigned int lvol, rvol;
++	struct codec_data *cdata = (struct codec_data *)codec->data;
++
++	switch (oss_mixer) {
++		case SOUND_MIXER_VOLUME:
++			/* normalize OSS range to fit codec volume control */
++			lvol = ((((val & 0x7f00) >> 8) * 0x60) / 0x64) + 0x1f;
++			rvol = (((val & 0x7f) * 0x60) / 0x64) + 0x1f;
++			lvol |= 0x80;
++			rvol |= 0x80;
++			wm8731_wrcodec(0x04, lvol);
++			au1550_delay(10);
++			wm8731_wrcodec(0x06, rvol);
++			au1550_delay(10);
++			codec->mixer_state[oss_mixer] = val;
++			break;
++		case SOUND_MIXER_LINE:
++			/* normalize OSS range to fit codec line control */
++			lvol = ((((val & 0x7f00) >> 8) * 0x1f) / 0x64);
++			rvol = (((val & 0x7f) * 0x1f) / 0x64);
++			if (!(val & 0x1f00))
++				lvol |= 0x80;
++			else
++				lvol &= ~0x80;
++			if (!(val & 0x001f))
++				rvol |= 0x80;
++			else
++				rvol &= ~0x80;
++			wm8731_wrcodec(0x00, lvol);
++			au1550_delay(10);
++			wm8731_wrcodec(0x02, rvol);
++			au1550_delay(10);
++			codec->mixer_state[oss_mixer] = val;
++			break;
++		case SOUND_MIXER_MIC:
++			if (!val)
++				cdata->audio_path |= 0x02;
++			else {
++				if (val >= 0x32)
++					cdata->audio_path |= 0x01;
++				else
++					cdata->audio_path &= ~0x01;
++				cdata->audio_path &= ~0x02;
++			}
++			wm8731_wrcodec(0x08, cdata->audio_path);
++			au1550_delay(10);
++			codec->mixer_state[oss_mixer] = val;
++			break;
++		case SOUND_MIXER_RECSRC:
++			if (val & SOUND_MASK_LINE)
++				cdata->audio_path &= ~0x04;
++			else
++				cdata->audio_path |= 0x04;
++			wm8731_wrcodec(0x08, cdata->audio_path);
++			au1550_delay(10);
++			codec->mixer_state[oss_mixer] = val;
++			break;
++		default:
++			return -EINVAL;
++	}
++
++	return 0;
++}
++
++void
++wm8731_init_codec(struct i2s_codec *codec)
++{
++	struct codec_data *cdata = (struct codec_data *)codec->data;
++
++	wm8731_wrcodec(0x1e, 0x00);	/* Reset */
++	au1550_delay(200);
++	wm8731_wrcodec(0x0c, 0x00);	/* Power up everything */
++	au1550_delay(10);
++	wm8731_wrcodec(0x12, 0x00);	/* Deactivate codec */
++	au1550_delay(10);
++	cdata->audio_path = 0x10;
++	/* Select DAC outputs to line out */
++	wm8731_wrcodec(0x08, cdata->audio_path);
++	au1550_delay(10);
++	wm8731_wrcodec(0x0a, 0x00);	/* Disable output mute */
++	au1550_delay(10);
++	wm8731_wrcodec(0x0e, 0x02);	/* Set slave, 16-bit, I2S modes */
++	au1550_delay(10);
++	wm8731_wrcodec(0x10, 0x01);	/* 12MHz (USB), 250fs */
++	au1550_delay(10);
++	wm8731_wrcodec(0x12, 0x01);	/* Activate codec */
++	au1550_delay(10);
++
++	codec->set_mixer(codec, SOUND_MIXER_VOLUME, 0x5050);
++	codec->set_mixer(codec, SOUND_MIXER_LINE, 0x0000);
++	codec->set_mixer(codec, SOUND_MIXER_MIC, 0x00);
++	codec->mixer_state[SOUND_MIXER_RECSRC] = SOUND_MIXER_LINE;
++}
++
++static struct i2s_codec au1550_i2s_codec = {
++	.supported_mixers	= WM8731_SUPPORTED_MASK,
++	.stereo_mixers		= WM8731_STEREO_MASK,
++	.record_sources		= WM8731_RECORD_MASK,
++	.init_codec		= &wm8731_init_codec,
++	.set_mixer		= &wm8731_set_mixer,
++	.data			= &wm8731_data,
++};
++#endif /* WM8731_CODEC */
++
++static struct au1550_state {
++	/* soundcore stuff */
++	int             dev_audio;
++	int		dev_mixer;
++
++	spinlock_t		lock;
++	struct semaphore	open_sem;
++	struct semaphore	sem;
++	mode_t			open_mode;
++	wait_queue_head_t	open_wait;
++	volatile psc_i2s_t	*psc_addr;
++	struct i2s_codec	*codec;
++
++	struct dmabuf {
++		u32		dmanr;
++		unsigned        sample_rate;
++		unsigned	src_factor;
++		unsigned        sample_size;
++		int             num_channels;
++		int		dma_bytes_per_sample;
++		int		user_bytes_per_sample;
++		int		cnt_factor;
++
++		void		*rawbuf;
++		unsigned        buforder;
++		unsigned	numfrag;
++		unsigned        fragshift;
++		void		*nextIn;
++		void		*nextOut;
++		int		count;
++		unsigned        total_bytes;
++		unsigned        error;
++		wait_queue_head_t wait;
++
++		/* redundant, but makes calculations easier */
++		unsigned	fragsize;
++		unsigned	dma_fragsize;
++		unsigned	dmasize;
++		unsigned	dma_qcount;
++
++		/* OSS stuff */
++		unsigned        mapped:1;
++		unsigned        ready:1;
++		unsigned        stopped:1;
++		unsigned        ossfragshift;
++		int             ossmaxfrags;
++		unsigned        subdivision;
++
++		/* Mixer stuff */
++		int		dev_mixer;
++	} dma_dac, dma_adc;
++} au1550_state;
++
++static unsigned
++ld2(unsigned int x)
++{
++	unsigned        r = 0;
++
++	if (x >= 0x10000) {
++		x >>= 16;
++		r += 16;
++	}
++	if (x >= 0x100) {
++		x >>= 8;
++		r += 8;
++	}
++	if (x >= 0x10) {
++		x >>= 4;
++		r += 4;
++	}
++	if (x >= 4) {
++		x >>= 2;
++		r += 2;
++	}
++	if (x >= 2)
++		r++;
++	return r;
++}
++
++/* stop the ADC before calling */
++static void
++set_adc_rate(struct au1550_state *s, unsigned rate)
++{
++	struct dmabuf  *adc = &s->dma_adc;
++
++	/* calc SRC factor */
++	adc->src_factor = (((SAMP_RATE*2) / rate) + 1) >> 1;
++	adc->sample_rate = SAMP_RATE / adc->src_factor;
++	return;
++
++	adc->src_factor = 1;
++}
++
++/* stop the DAC before calling */
++static void
++set_dac_rate(struct au1550_state *s, unsigned rate)
++{
++	struct dmabuf  *dac = &s->dma_dac;
++
++	/* calc SRC factor */
++	dac->src_factor = (((SAMP_RATE*2) / rate) + 1) >> 1;
++	dac->sample_rate = SAMP_RATE / dac->src_factor;
++	return;
++
++	dac->src_factor = 1;
++}
++
++static void
++stop_dac(struct au1550_state *s)
++{
++	struct dmabuf  *db = &s->dma_dac;
++	unsigned long   flags;
++	uint	stat;
++	volatile psc_i2s_t *ip;
++
++	if (db->stopped)
++		return;
++
++	ip = s->psc_addr;
++	spin_lock_irqsave(&s->lock, flags);
++
++	ip->psc_i2spcr = PSC_I2SPCR_TP;
++	au_sync();
++
++	/* Wait for Transmit Busy to show disabled.
++	*/
++	do {
++		stat = ip->psc_i2sstat;
++		au_sync();
++	} while ((stat & PSC_I2SSTAT_TB) != 0);
++
++	au1xxx_dbdma_reset(db->dmanr);
++
++	db->stopped = 1;
++
++	spin_unlock_irqrestore(&s->lock, flags);
++}
++
++static void
++stop_adc(struct au1550_state *s)
++{
++	struct dmabuf  *db = &s->dma_adc;
++	unsigned long   flags;
++	uint	stat;
++	volatile psc_i2s_t *ip;
++
++	if (db->stopped)
++		return;
++
++	ip = s->psc_addr;
++	spin_lock_irqsave(&s->lock, flags);
++
++	ip->psc_i2spcr = PSC_I2SPCR_RP;
++	au_sync();
++
++	/* Wait for Receive Busy to show disabled.
++	*/
++	do {
++		stat = ip->psc_i2sstat;
++		au_sync();
++	} while ((stat & PSC_I2SSTAT_RB) != 0);
++
++	au1xxx_dbdma_reset(db->dmanr);
++
++	db->stopped = 1;
++
++	spin_unlock_irqrestore(&s->lock, flags);
++}
++
++static void
++set_xmit_slots(int num_channels)
++{
++	/* This is here just as a place holder.  The WM8731 only
++	 * supports two fixed channels.
++	 */
++}
++
++static void
++set_recv_slots(int num_channels)
++{
++	/* This is here just as a place holder.  The WM8731 only
++	 * supports two fixed channels.
++	 */
++}
++
++static void
++start_dac(struct au1550_state *s)
++{
++	struct dmabuf  *db = &s->dma_dac;
++	unsigned long   flags;
++	volatile psc_i2s_t *ip;
++
++	if (!db->stopped)
++		return;
++
++	spin_lock_irqsave(&s->lock, flags);
++
++	ip = s->psc_addr;
++	set_xmit_slots(db->num_channels);
++	ip->psc_i2spcr = PSC_I2SPCR_TC;
++	au_sync();
++	ip->psc_i2spcr = PSC_I2SPCR_TS;
++	au_sync();
++
++	au1xxx_dbdma_start(db->dmanr);
++
++	db->stopped = 0;
++
++	spin_unlock_irqrestore(&s->lock, flags);
++}
++
++static void
++start_adc(struct au1550_state *s)
++{
++	struct dmabuf  *db = &s->dma_adc;
++	int	i;
++	volatile psc_i2s_t *ip;
++
++	if (!db->stopped)
++		return;
++
++	/* Put two buffers on the ring to get things started.
++	*/
++	for (i=0; i<2; i++) {
++		au1xxx_dbdma_put_dest(db->dmanr, db->nextIn, db->dma_fragsize);
++
++		db->nextIn += db->dma_fragsize;
++		if (db->nextIn >= db->rawbuf + db->dmasize)
++			db->nextIn -= db->dmasize;
++	}
++
++	ip = s->psc_addr;
++	set_recv_slots(db->num_channels);
++	au1xxx_dbdma_start(db->dmanr);
++	ip->psc_i2spcr = PSC_I2SPCR_RC;
++	au_sync();
++	ip->psc_i2spcr = PSC_I2SPCR_RS;
++	au_sync();
++
++	db->stopped = 0;
++}
++
++static int
++prog_dmabuf(struct au1550_state *s, struct dmabuf *db)
++{
++	unsigned user_bytes_per_sec;
++	unsigned        bufs;
++	unsigned        rate = db->sample_rate;
++
++	if (!db->rawbuf) {
++		db->ready = db->mapped = 0;
++		db->buforder = 5;	/* 32 * PAGE_SIZE */
++		db->rawbuf = kmalloc((PAGE_SIZE << db->buforder), GFP_KERNEL);
++		if (!db->rawbuf)
++			return -ENOMEM;
++	}
++
++	db->cnt_factor = 1;
++	if (db->sample_size == 8)
++		db->cnt_factor *= 2;
++	if (db->num_channels == 1)
++		db->cnt_factor *= 2;
++	db->cnt_factor *= db->src_factor;
++
++	db->count = 0;
++	db->dma_qcount = 0;
++	db->nextIn = db->nextOut = db->rawbuf;
++
++	db->user_bytes_per_sample = (db->sample_size>>3) * db->num_channels;
++	db->dma_bytes_per_sample = 2 * ((db->num_channels == 1) ?
++					2 : db->num_channels);
++
++	user_bytes_per_sec = rate * db->user_bytes_per_sample;
++	bufs = PAGE_SIZE << db->buforder;
++	if (db->ossfragshift) {
++		if ((1000 << db->ossfragshift) < user_bytes_per_sec)
++			db->fragshift = ld2(user_bytes_per_sec/1000);
++		else
++			db->fragshift = db->ossfragshift;
++	} else {
++		db->fragshift = ld2(user_bytes_per_sec / 100 /
++				    (db->subdivision ? db->subdivision : 1));
++		if (db->fragshift < 3)
++			db->fragshift = 3;
++	}
++
++	db->fragsize = 1 << db->fragshift;
++	db->dma_fragsize = db->fragsize * db->cnt_factor;
++	db->numfrag = bufs / db->dma_fragsize;
++
++	while (db->numfrag < 4 && db->fragshift > 3) {
++		db->fragshift--;
++		db->fragsize = 1 << db->fragshift;
++		db->dma_fragsize = db->fragsize * db->cnt_factor;
++		db->numfrag = bufs / db->dma_fragsize;
++	}
++
++	if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
++		db->numfrag = db->ossmaxfrags;
++
++	db->dmasize = db->dma_fragsize * db->numfrag;
++	memset(db->rawbuf, 0, bufs);
++
++#ifdef AU1000_VERBOSE_DEBUG
++	dbg("rate=%d, samplesize=%d, channels=%d",
++	    rate, db->sample_size, db->num_channels);
++	dbg("fragsize=%d, cnt_factor=%d, dma_fragsize=%d",
++	    db->fragsize, db->cnt_factor, db->dma_fragsize);
++	dbg("numfrag=%d, dmasize=%d", db->numfrag, db->dmasize);
++#endif
++
++	db->ready = 1;
++	return 0;
++}
++
++static int
++prog_dmabuf_adc(struct au1550_state *s)
++{
++	stop_adc(s);
++	return prog_dmabuf(s, &s->dma_adc);
++
++}
++
++static int
++prog_dmabuf_dac(struct au1550_state *s)
++{
++	stop_dac(s);
++	return prog_dmabuf(s, &s->dma_dac);
++}
++
++
++/* hold spinlock for the following */
++static void
++dac_dma_interrupt(int irq, void *dev_id, struct pt_regs *regs)
++{
++	struct au1550_state *s = (struct au1550_state *) dev_id;
++	struct dmabuf  *db = &s->dma_dac;
++	u32	i2s_stat;
++	volatile psc_i2s_t *ip;
++
++	ip = s->psc_addr;
++	i2s_stat = ip->psc_i2sstat;
++#ifdef AU1000_VERBOSE_DEBUG
++	if (i2s_stat & (PSC_I2SSTAT_TF | PSC_I2SSTAT_TR | PSC_I2SSTAT_TF))
++		dbg("I2S status = 0x%08x", i2s_stat);
++#endif
++	db->dma_qcount--;
++
++	if (db->count >= db->fragsize) {
++		if (au1xxx_dbdma_put_source(db->dmanr, db->nextOut,
++							db->fragsize) == 0) {
++			pr_error("qcount < 2 and no ring room!");
++		}
++		db->nextOut += db->fragsize;
++		if (db->nextOut >= db->rawbuf + db->dmasize)
++			db->nextOut -= db->dmasize;
++		db->count -= db->fragsize;
++		db->total_bytes += db->dma_fragsize;
++		db->dma_qcount++;
++	}
++
++	/* wake up anybody listening */
++	if (waitqueue_active(&db->wait))
++		wake_up(&db->wait);
++}
++
++
++static void
++adc_dma_interrupt(int irq, void *dev_id, struct pt_regs *regs)
++{
++	struct	au1550_state *s = (struct au1550_state *)dev_id;
++	struct	dmabuf  *dp = &s->dma_adc;
++	u32	obytes;
++	char	*obuf;
++
++	/* Pull the buffer from the dma queue.
++	*/
++	au1xxx_dbdma_get_dest(dp->dmanr, (void *)(&obuf), &obytes);
++
++	if ((dp->count + obytes) > dp->dmasize) {
++		/* Overrun. Stop ADC and log the error
++		*/
++		stop_adc(s);
++		dp->error++;
++		pr_error("adc overrun");
++		return;
++	}
++
++	/* Put a new empty buffer on the destination DMA.
++	*/
++	au1xxx_dbdma_put_dest(dp->dmanr, dp->nextIn, dp->dma_fragsize);
++
++	dp->nextIn += dp->dma_fragsize;
++	if (dp->nextIn >= dp->rawbuf + dp->dmasize)
++		dp->nextIn -= dp->dmasize;
++
++	dp->count += obytes;
++	dp->total_bytes += obytes;
++
++	/* wake up anybody listening
++	*/
++	if (waitqueue_active(&dp->wait))
++		wake_up(&dp->wait);
++
++}
++
++static loff_t
++au1550_llseek(struct file *file, loff_t offset, int origin)
++{
++	return -ESPIPE;
++}
++
++static int
++au1550_open_mixdev(struct inode *inode, struct file *file)
++{
++	file->private_data = &au1550_state;
++	return 0;
++}
++
++static int
++au1550_release_mixdev(struct inode *inode, struct file *file)
++{
++	return 0;
++}
++
++#define I2S_CODEC	"Wolfson WM8731"
++
++static int
++au1550_ioctl_mixdev(struct inode *inode, struct file *file,
++			       unsigned int cmd, unsigned long arg)
++{
++	struct au1550_state *s = (struct au1550_state *)file->private_data;
++	struct i2s_codec *codec = s->codec;
++	int i, val = 0;
++
++	if (cmd == SOUND_MIXER_INFO) {
++		mixer_info info;
++		memset(&info, 0, sizeof(info));
++		strlcpy(info.id, I2S_CODEC, sizeof(info.id));
++		strlcpy(info.name, I2S_CODEC, sizeof(info.name));
++		info.modify_counter = codec->modcnt;
++		if (copy_to_user((void __user *)arg, &info, sizeof(info)))
++			return -EFAULT;
++		return 0;
++	}
++	if (cmd == SOUND_OLD_MIXER_INFO) {
++		_old_mixer_info info;
++		memset(&info, 0, sizeof(info));
++		strlcpy(info.id, I2S_CODEC, sizeof(info.id));
++		strlcpy(info.name, I2S_CODEC, sizeof(info.name));
++		if (copy_to_user((void __user *)arg, &info, sizeof(info)))
++			return -EFAULT;
++		return 0;
++	}
++
++	if (_IOC_TYPE(cmd) != 'M' || _SIOC_SIZE(cmd) != sizeof(int))
++		return -EINVAL;
++
++	if (cmd == OSS_GETVERSION)
++		return put_user(SOUND_VERSION, (int __user *)arg);
++
++	if (_SIOC_DIR(cmd) == _SIOC_READ) {
++		switch (_IOC_NR(cmd)) {
++		case SOUND_MIXER_RECSRC: /* give them the current record source */
++			val = codec->mixer_state[SOUND_MIXER_RECSRC];
++			break;
++
++		case SOUND_MIXER_DEVMASK: /* give them the supported mixers */
++			val = codec->supported_mixers;
++			break;
++
++		case SOUND_MIXER_RECMASK: /* Arg contains a bit for each supported recording source */
++			val = codec->record_sources;
++			break;
++
++		case SOUND_MIXER_STEREODEVS: /* Mixer channels supporting stereo */
++			val = codec->stereo_mixers;
++			break;
++
++		case SOUND_MIXER_CAPS:
++			val = SOUND_CAP_EXCL_INPUT;
++			break;
++
++		default: /* read a specific mixer */
++			i = _IOC_NR(cmd);
++
++			if (!i2s_supported_mixer(codec, i))
++				return -EINVAL;
++
++			val = codec->mixer_state[i];
++ 			break;
++		}
++		return put_user(val, (int __user *)arg);
++	}
++
++	if (_SIOC_DIR(cmd) == (_SIOC_WRITE|_SIOC_READ)) {
++		codec->modcnt++;
++		if (get_user(val, (int __user *)arg))
++			return -EFAULT;
++
++		switch (_IOC_NR(cmd)) {
++		case SOUND_MIXER_RECSRC: /* Arg contains a bit for each recording source */
++			if (!val) return 0;
++			if (!(val &= codec->record_sources)) return -EINVAL;
++
++			codec->set_mixer(codec, SOUND_MIXER_RECSRC, val);
++
++			return 0;
++		default: /* write a specific mixer */
++			i = _IOC_NR(cmd);
++
++			if (!i2s_supported_mixer(codec, i))
++				return -EINVAL;
++
++			codec->set_mixer(codec, i, val);
++
++			return 0;
++		}
++	}
++	return -EINVAL;
++}
++
++static struct file_operations au1550_mixer_fops = {
++	owner:THIS_MODULE,
++	llseek:au1550_llseek,
++	ioctl:au1550_ioctl_mixdev,
++	open:au1550_open_mixdev,
++	release:au1550_release_mixdev,
++};
++
++static int
++drain_dac(struct au1550_state *s, int nonblock)
++{
++	unsigned long   flags;
++	int             count, tmo;
++
++	if (s->dma_dac.mapped || !s->dma_dac.ready || s->dma_dac.stopped)
++		return 0;
++
++	for (;;) {
++		spin_lock_irqsave(&s->lock, flags);
++		count = s->dma_dac.count;
++		spin_unlock_irqrestore(&s->lock, flags);
++		if (count <= 0)
++			break;
++		if (signal_pending(current))
++			break;
++		if (nonblock)
++			return -EBUSY;
++		tmo = 1000 * count / SAMP_RATE;
++		tmo /= s->dma_dac.dma_bytes_per_sample;
++		au1550_delay(tmo);
++	}
++	if (signal_pending(current))
++		return -ERESTARTSYS;
++	return 0;
++}
++
++static inline u8 S16_TO_U8(s16 ch)
++{
++	return (u8) (ch >> 8) + 0x80;
++}
++static inline s16 U8_TO_S16(u8 ch)
++{
++	return (s16) (ch - 0x80) << 8;
++}
++
++/*
++ * Translates user samples to dma buffer suitable for audio DAC data:
++ *     If mono, copy left channel to right channel in dma buffer.
++ *     If 8 bit samples, cvt to 16-bit before writing to dma buffer.
++ *     If interpolating (no VRA), duplicate every audio frame src_factor times.
++ */
++static int
++translate_from_user(struct dmabuf *db, char* dmabuf, char* userbuf,
++							       int dmacount)
++{
++	int             sample, i;
++	int             interp_bytes_per_sample;
++	int             num_samples;
++	int             mono = (db->num_channels == 1);
++	char            usersample[12];
++	s16             ch, dmasample[6];
++
++	if (db->sample_size == 16 && !mono && db->src_factor == 1) {
++		/* no translation necessary, just copy
++		*/
++		if (copy_from_user(dmabuf, userbuf, dmacount))
++			return -EFAULT;
++		return dmacount;
++	}
++
++	interp_bytes_per_sample = db->dma_bytes_per_sample * db->src_factor;
++	num_samples = dmacount / interp_bytes_per_sample;
++
++	for (sample = 0; sample < num_samples; sample++) {
++		if (copy_from_user(usersample, userbuf,
++				   db->user_bytes_per_sample)) {
++			return -EFAULT;
++		}
++
++		for (i = 0; i < db->num_channels; i++) {
++			if (db->sample_size == 8)
++				ch = U8_TO_S16(usersample[i]);
++			else
++				ch = *((s16 *) (&usersample[i * 2]));
++			dmasample[i] = ch;
++			if (mono)
++				dmasample[i + 1] = ch;	/* right channel */
++		}
++
++		/* duplicate every audio frame src_factor times
++		*/
++		for (i = 0; i < db->src_factor; i++)
++			memcpy(dmabuf, dmasample, db->dma_bytes_per_sample);
++
++		userbuf += db->user_bytes_per_sample;
++		dmabuf += interp_bytes_per_sample;
++	}
++
++	return num_samples * interp_bytes_per_sample;
++}
++
++/*
++ * Translates audio ADC samples to user buffer:
++ *     If mono, send only left channel to user buffer.
++ *     If 8 bit samples, cvt from 16 to 8 bit before writing to user buffer.
++ *     If decimating (no VRA), skip over src_factor audio frames.
++ */
++static int
++translate_to_user(struct dmabuf *db, char* userbuf, char* dmabuf,
++							     int dmacount)
++{
++	int             sample, i;
++	int             interp_bytes_per_sample;
++	int             num_samples;
++	int             mono = (db->num_channels == 1);
++	char            usersample[12];
++
++	if (db->sample_size == 16 && !mono && db->src_factor == 1) {
++		/* no translation necessary, just copy
++		*/
++		if (copy_to_user(userbuf, dmabuf, dmacount))
++			return -EFAULT;
++		return dmacount;
++	}
++
++	interp_bytes_per_sample = db->dma_bytes_per_sample * db->src_factor;
++	num_samples = dmacount / interp_bytes_per_sample;
++
++	for (sample = 0; sample < num_samples; sample++) {
++		for (i = 0; i < db->num_channels; i++) {
++			if (db->sample_size == 8)
++				usersample[i] =
++					S16_TO_U8(*((s16 *) (&dmabuf[i * 2])));
++			else
++				*((s16 *) (&usersample[i * 2])) =
++					*((s16 *) (&dmabuf[i * 2]));
++		}
++
++		if (copy_to_user(userbuf, usersample,
++				 db->user_bytes_per_sample)) {
++			return -EFAULT;
++		}
++
++		userbuf += db->user_bytes_per_sample;
++		dmabuf += interp_bytes_per_sample;
++	}
++
++	return num_samples * interp_bytes_per_sample;
++}
++
++/*
++ * Copy audio data to/from user buffer from/to dma buffer, taking care
++ * that we wrap when reading/writing the dma buffer. Returns actual byte
++ * count written to or read from the dma buffer.
++ */
++static int
++copy_dmabuf_user(struct dmabuf *db, char* userbuf, int count, int to_user)
++{
++	char           *bufptr = to_user ? db->nextOut : db->nextIn;
++	char           *bufend = db->rawbuf + db->dmasize;
++	int             cnt, ret;
++
++	if (bufptr + count > bufend) {
++		int             partial = (int) (bufend - bufptr);
++		if (to_user) {
++			if ((cnt = translate_to_user(db, userbuf,
++						     bufptr, partial)) < 0)
++				return cnt;
++			ret = cnt;
++			if ((cnt = translate_to_user(db, userbuf + partial,
++						     db->rawbuf,
++						     count - partial)) < 0)
++				return cnt;
++			ret += cnt;
++		} else {
++			if ((cnt = translate_from_user(db, bufptr, userbuf,
++						       partial)) < 0)
++				return cnt;
++			ret = cnt;
++			if ((cnt = translate_from_user(db, db->rawbuf,
++						       userbuf + partial,
++						       count - partial)) < 0)
++				return cnt;
++			ret += cnt;
++		}
++	} else {
++		if (to_user)
++			ret = translate_to_user(db, userbuf, bufptr, count);
++		else
++			ret = translate_from_user(db, bufptr, userbuf, count);
++	}
++
++	return ret;
++}
++
++static ssize_t
++au1550_read(struct file *file, char *buffer, size_t count, loff_t *ppos)
++{
++	struct au1550_state *s = (struct au1550_state *)file->private_data;
++	struct dmabuf  *db = &s->dma_adc;
++	DECLARE_WAITQUEUE(wait, current);
++	ssize_t         ret;
++	unsigned long   flags;
++	int             cnt, usercnt, avail;
++
++	if (db->mapped)
++		return -ENXIO;
++	if (!access_ok(VERIFY_WRITE, buffer, count))
++		return -EFAULT;
++	ret = 0;
++
++	count *= db->cnt_factor;
++
++	down(&s->sem);
++	add_wait_queue(&db->wait, &wait);
++
++	while (count > 0) {
++		/* wait for samples in ADC dma buffer
++		*/
++		do {
++			if (db->stopped)
++				start_adc(s);
++			spin_lock_irqsave(&s->lock, flags);
++			avail = db->count;
++			if (avail <= 0)
++				__set_current_state(TASK_INTERRUPTIBLE);
++			spin_unlock_irqrestore(&s->lock, flags);
++			if (avail <= 0) {
++				if (file->f_flags & O_NONBLOCK) {
++					if (!ret)
++						ret = -EAGAIN;
++					goto out;
++				}
++				up(&s->sem);
++				schedule();
++				if (signal_pending(current)) {
++					if (!ret)
++						ret = -ERESTARTSYS;
++					goto out2;
++				}
++				down(&s->sem);
++			}
++		} while (avail <= 0);
++
++		/* copy from nextOut to user
++		*/
++		if ((cnt = copy_dmabuf_user(db, buffer,
++					    count > avail ?
++					    avail : count, 1)) < 0) {
++			if (!ret)
++				ret = -EFAULT;
++			goto out;
++		}
++
++		spin_lock_irqsave(&s->lock, flags);
++		db->count -= cnt;
++		db->nextOut += cnt;
++		if (db->nextOut >= db->rawbuf + db->dmasize)
++			db->nextOut -= db->dmasize;
++		spin_unlock_irqrestore(&s->lock, flags);
++
++		count -= cnt;
++		usercnt = cnt / db->cnt_factor;
++		buffer += usercnt;
++		ret += usercnt;
++	}			/* while (count > 0) */
++
++out:
++	up(&s->sem);
++out2:
++	remove_wait_queue(&db->wait, &wait);
++	set_current_state(TASK_RUNNING);
++	return ret;
++}
++
++static ssize_t
++au1550_write(struct file *file, const char *buffer, size_t count, loff_t * ppos)
++{
++	struct au1550_state *s = (struct au1550_state *)file->private_data;
++	struct dmabuf  *db = &s->dma_dac;
++	DECLARE_WAITQUEUE(wait, current);
++	ssize_t         ret = 0;
++	unsigned long   flags;
++	int             cnt, usercnt, avail;
++
++#ifdef AU1000_VERBOSE_DEBUG
++	dbg("write: count=%d", count);
++#endif
++
++	if (db->mapped)
++		return -ENXIO;
++	if (!access_ok(VERIFY_READ, buffer, count))
++		return -EFAULT;
++
++	count *= db->cnt_factor;
++
++	down(&s->sem);
++	add_wait_queue(&db->wait, &wait);
++
++	while (count > 0) {
++		/* wait for space in playback buffer
++		*/
++		do {
++			spin_lock_irqsave(&s->lock, flags);
++			avail = (int) db->dmasize - db->count;
++			if (avail <= 0)
++				__set_current_state(TASK_INTERRUPTIBLE);
++			spin_unlock_irqrestore(&s->lock, flags);
++			if (avail <= 0) {
++				if (file->f_flags & O_NONBLOCK) {
++					if (!ret)
++						ret = -EAGAIN;
++					goto out;
++				}
++				up(&s->sem);
++				schedule();
++				if (signal_pending(current)) {
++					if (!ret)
++						ret = -ERESTARTSYS;
++					goto out2;
++				}
++				down(&s->sem);
++			}
++		} while (avail <= 0);
++
++		/* copy from user to nextIn
++		*/
++		if ((cnt = copy_dmabuf_user(db, (char *) buffer,
++					    count > avail ?
++					    avail : count, 0)) < 0) {
++			if (!ret)
++				ret = -EFAULT;
++			goto out;
++		}
++
++		spin_lock_irqsave(&s->lock, flags);
++		db->count += cnt;
++		db->nextIn += cnt;
++		if (db->nextIn >= db->rawbuf + db->dmasize)
++			db->nextIn -= db->dmasize;
++
++		/* If the data is available, we want to keep two buffers
++		 * on the dma queue.  If the queue count reaches zero,
++		 * we know the dma has stopped.
++		 */
++		while ((db->dma_qcount < 2) && (db->count >= db->fragsize)) {
++			if (au1xxx_dbdma_put_source(db->dmanr, db->nextOut,
++							db->fragsize) == 0) {
++				pr_error("qcount < 2 and no ring room!");
++			}
++			db->nextOut += db->fragsize;
++			if (db->nextOut >= db->rawbuf + db->dmasize)
++				db->nextOut -= db->dmasize;
++			db->count -= db->fragsize;
++			db->total_bytes += db->dma_fragsize;
++			if (db->dma_qcount == 0)
++				start_dac(s);
++			db->dma_qcount++;
++		}
++		spin_unlock_irqrestore(&s->lock, flags);
++
++		count -= cnt;
++		usercnt = cnt / db->cnt_factor;
++		buffer += usercnt;
++		ret += usercnt;
++	}			/* while (count > 0) */
++
++out:
++	up(&s->sem);
++out2:
++	remove_wait_queue(&db->wait, &wait);
++	set_current_state(TASK_RUNNING);
++	return ret;
++}
++
++
++/* No kernel lock - we have our own spinlock */
++static unsigned int
++au1550_poll(struct file *file, struct poll_table_struct *wait)
++{
++	struct au1550_state *s = (struct au1550_state *)file->private_data;
++	unsigned long   flags;
++	unsigned int    mask = 0;
++
++	if (file->f_mode & FMODE_WRITE) {
++		if (!s->dma_dac.ready)
++			return 0;
++		poll_wait(file, &s->dma_dac.wait, wait);
++	}
++	if (file->f_mode & FMODE_READ) {
++		if (!s->dma_adc.ready)
++			return 0;
++		poll_wait(file, &s->dma_adc.wait, wait);
++	}
++
++	spin_lock_irqsave(&s->lock, flags);
++
++	if (file->f_mode & FMODE_READ) {
++		if (s->dma_adc.count >= (signed)s->dma_adc.dma_fragsize)
++			mask |= POLLIN | POLLRDNORM;
++	}
++	if (file->f_mode & FMODE_WRITE) {
++		if (s->dma_dac.mapped) {
++			if (s->dma_dac.count >=
++			    (signed)s->dma_dac.dma_fragsize)
++				mask |= POLLOUT | POLLWRNORM;
++		} else {
++			if ((signed) s->dma_dac.dmasize >=
++			    s->dma_dac.count + (signed)s->dma_dac.dma_fragsize)
++				mask |= POLLOUT | POLLWRNORM;
++		}
++	}
++	spin_unlock_irqrestore(&s->lock, flags);
++	return mask;
++}
++
++static int
++au1550_mmap(struct file *file, struct vm_area_struct *vma)
++{
++	struct au1550_state *s = (struct au1550_state *)file->private_data;
++	struct dmabuf  *db;
++	unsigned long   size;
++	int ret = 0;
++
++	lock_kernel();
++	down(&s->sem);
++	if (vma->vm_flags & VM_WRITE)
++		db = &s->dma_dac;
++	else if (vma->vm_flags & VM_READ)
++		db = &s->dma_adc;
++	else {
++		ret = -EINVAL;
++		goto out;
++	}
++	if (vma->vm_pgoff != 0) {
++		ret = -EINVAL;
++		goto out;
++	}
++	size = vma->vm_end - vma->vm_start;
++	if (size > (PAGE_SIZE << db->buforder)) {
++		ret = -EINVAL;
++		goto out;
++	}
++	if (remap_pfn_range(vma, vma->vm_start,
++			     page_to_pfn(virt_to_page(db->rawbuf)),
++			     size, vma->vm_page_prot)) {
++		ret = -EAGAIN;
++		goto out;
++	}
++	vma->vm_flags &= ~VM_IO;
++	db->mapped = 1;
++out:
++	up(&s->sem);
++	unlock_kernel();
++	return ret;
++}
++
++
++#ifdef AU1000_VERBOSE_DEBUG
++static struct ioctl_str_t {
++	unsigned int    cmd;
++	const char     *str;
++} ioctl_str[] = {
++	{SNDCTL_DSP_RESET, "SNDCTL_DSP_RESET"},
++	{SNDCTL_DSP_SYNC, "SNDCTL_DSP_SYNC"},
++	{SNDCTL_DSP_SPEED, "SNDCTL_DSP_SPEED"},
++	{SNDCTL_DSP_STEREO, "SNDCTL_DSP_STEREO"},
++	{SNDCTL_DSP_GETBLKSIZE, "SNDCTL_DSP_GETBLKSIZE"},
++	{SNDCTL_DSP_SAMPLESIZE, "SNDCTL_DSP_SAMPLESIZE"},
++	{SNDCTL_DSP_CHANNELS, "SNDCTL_DSP_CHANNELS"},
++	{SOUND_PCM_WRITE_CHANNELS, "SOUND_PCM_WRITE_CHANNELS"},
++	{SOUND_PCM_WRITE_FILTER, "SOUND_PCM_WRITE_FILTER"},
++	{SNDCTL_DSP_POST, "SNDCTL_DSP_POST"},
++	{SNDCTL_DSP_SUBDIVIDE, "SNDCTL_DSP_SUBDIVIDE"},
++	{SNDCTL_DSP_SETFRAGMENT, "SNDCTL_DSP_SETFRAGMENT"},
++	{SNDCTL_DSP_GETFMTS, "SNDCTL_DSP_GETFMTS"},
++	{SNDCTL_DSP_SETFMT, "SNDCTL_DSP_SETFMT"},
++	{SNDCTL_DSP_GETOSPACE, "SNDCTL_DSP_GETOSPACE"},
++	{SNDCTL_DSP_GETISPACE, "SNDCTL_DSP_GETISPACE"},
++	{SNDCTL_DSP_NONBLOCK, "SNDCTL_DSP_NONBLOCK"},
++	{SNDCTL_DSP_GETCAPS, "SNDCTL_DSP_GETCAPS"},
++	{SNDCTL_DSP_GETTRIGGER, "SNDCTL_DSP_GETTRIGGER"},
++	{SNDCTL_DSP_SETTRIGGER, "SNDCTL_DSP_SETTRIGGER"},
++	{SNDCTL_DSP_GETIPTR, "SNDCTL_DSP_GETIPTR"},
++	{SNDCTL_DSP_GETOPTR, "SNDCTL_DSP_GETOPTR"},
++	{SNDCTL_DSP_MAPINBUF, "SNDCTL_DSP_MAPINBUF"},
++	{SNDCTL_DSP_MAPOUTBUF, "SNDCTL_DSP_MAPOUTBUF"},
++	{SNDCTL_DSP_SETSYNCRO, "SNDCTL_DSP_SETSYNCRO"},
++	{SNDCTL_DSP_SETDUPLEX, "SNDCTL_DSP_SETDUPLEX"},
++	{SNDCTL_DSP_GETODELAY, "SNDCTL_DSP_GETODELAY"},
++	{SNDCTL_DSP_GETCHANNELMASK, "SNDCTL_DSP_GETCHANNELMASK"},
++	{SNDCTL_DSP_BIND_CHANNEL, "SNDCTL_DSP_BIND_CHANNEL"},
++	{OSS_GETVERSION, "OSS_GETVERSION"},
++	{SOUND_PCM_READ_RATE, "SOUND_PCM_READ_RATE"},
++	{SOUND_PCM_READ_CHANNELS, "SOUND_PCM_READ_CHANNELS"},
++	{SOUND_PCM_READ_BITS, "SOUND_PCM_READ_BITS"},
++	{SOUND_PCM_READ_FILTER, "SOUND_PCM_READ_FILTER"}
++};
++#endif
++
++static int
++dma_count_done(struct dmabuf *db)
++{
++	if (db->stopped)
++		return 0;
++
++	return db->dma_fragsize - au1xxx_get_dma_residue(db->dmanr);
++}
++
++
++static int
++au1550_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
++							unsigned long arg)
++{
++	struct au1550_state *s = (struct au1550_state *)file->private_data;
++	unsigned long   flags;
++	audio_buf_info  abinfo;
++	count_info      cinfo;
++	int             count;
++	int             val, mapped, ret, diff;
++
++	mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
++		((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
++
++#ifdef AU1000_VERBOSE_DEBUG
++	for (count=0; count<sizeof(ioctl_str)/sizeof(ioctl_str[0]); count++) {
++		if (ioctl_str[count].cmd == cmd)
++			break;
++	}
++	if (count < sizeof(ioctl_str) / sizeof(ioctl_str[0]))
++		dbg("ioctl %s, arg=0x%lx", ioctl_str[count].str, arg);
++	else
++		dbg("ioctl 0x%x unknown, arg=0x%lx", cmd, arg);
++#endif
++
++	switch (cmd) {
++	case OSS_GETVERSION:
++		return put_user(SOUND_VERSION, (int *) arg);
++
++	case SNDCTL_DSP_SYNC:
++		if (file->f_mode & FMODE_WRITE)
++			return drain_dac(s, file->f_flags & O_NONBLOCK);
++		return 0;
++
++	case SNDCTL_DSP_SETDUPLEX:
++		return 0;
++
++	case SNDCTL_DSP_GETCAPS:
++		return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME |
++				DSP_CAP_TRIGGER | DSP_CAP_MMAP, (int *)arg);
++
++	case SNDCTL_DSP_RESET:
++		if (file->f_mode & FMODE_WRITE) {
++			stop_dac(s);
++			synchronize_irq();
++			s->dma_dac.count = s->dma_dac.total_bytes = 0;
++			s->dma_dac.nextIn = s->dma_dac.nextOut =
++				s->dma_dac.rawbuf;
++		}
++		if (file->f_mode & FMODE_READ) {
++			stop_adc(s);
++			synchronize_irq();
++			s->dma_adc.count = s->dma_adc.total_bytes = 0;
++			s->dma_adc.nextIn = s->dma_adc.nextOut =
++				s->dma_adc.rawbuf;
++		}
++		return 0;
++
++	case SNDCTL_DSP_SPEED:
++		if (get_user(val, (int *) arg))
++			return -EFAULT;
++		if (val >= 0) {
++			if (file->f_mode & FMODE_READ) {
++				stop_adc(s);
++				set_adc_rate(s, val);
++			}
++			if (file->f_mode & FMODE_WRITE) {
++				stop_dac(s);
++				set_dac_rate(s, val);
++			}
++			if (s->open_mode & FMODE_READ)
++				if ((ret = prog_dmabuf_adc(s)))
++					return ret;
++			if (s->open_mode & FMODE_WRITE)
++				if ((ret = prog_dmabuf_dac(s)))
++					return ret;
++		}
++		return put_user((file->f_mode & FMODE_READ) ?
++				s->dma_adc.sample_rate :
++				s->dma_dac.sample_rate,
++				(int *)arg);
++
++	case SNDCTL_DSP_STEREO:
++		if (get_user(val, (int *) arg))
++			return -EFAULT;
++		if (file->f_mode & FMODE_READ) {
++			stop_adc(s);
++			s->dma_adc.num_channels = val ? 2 : 1;
++			if ((ret = prog_dmabuf_adc(s)))
++				return ret;
++		}
++		if (file->f_mode & FMODE_WRITE) {
++			stop_dac(s);
++			s->dma_dac.num_channels = val ? 2 : 1;
++			if ((ret = prog_dmabuf_dac(s)))
++				return ret;
++		}
++		return 0;
++
++	case SNDCTL_DSP_CHANNELS:
++		if (get_user(val, (int *) arg))
++			return -EFAULT;
++		if (val != 0) {
++			if (file->f_mode & FMODE_READ) {
++				if (val < 0 || val > 2)
++					return -EINVAL;
++				stop_adc(s);
++				s->dma_adc.num_channels = val;
++				if ((ret = prog_dmabuf_adc(s)))
++					return ret;
++			}
++			if (file->f_mode & FMODE_WRITE) {
++				switch (val) {
++				case 1:
++				case 2:
++					break;
++				default:
++					return -EINVAL;
++				}
++
++				stop_dac(s);
++				s->dma_dac.num_channels = val;
++				if ((ret = prog_dmabuf_dac(s)))
++					return ret;
++			}
++		}
++		return put_user(val, (int *) arg);
++
++	case SNDCTL_DSP_GETFMTS:	/* Returns a mask */
++		return put_user(AFMT_S16_LE | AFMT_U8, (int *) arg);
++
++	case SNDCTL_DSP_SETFMT:	/* Selects ONE fmt */
++		if (get_user(val, (int *) arg))
++			return -EFAULT;
++		if (val != AFMT_QUERY) {
++			if (file->f_mode & FMODE_READ) {
++				stop_adc(s);
++				if (val == AFMT_S16_LE)
++					s->dma_adc.sample_size = 16;
++				else {
++					val = AFMT_U8;
++					s->dma_adc.sample_size = 8;
++				}
++				if ((ret = prog_dmabuf_adc(s)))
++					return ret;
++			}
++			if (file->f_mode & FMODE_WRITE) {
++				stop_dac(s);
++				if (val == AFMT_S16_LE)
++					s->dma_dac.sample_size = 16;
++				else {
++					val = AFMT_U8;
++					s->dma_dac.sample_size = 8;
++				}
++				if ((ret = prog_dmabuf_dac(s)))
++					return ret;
++			}
++		} else {
++			if (file->f_mode & FMODE_READ)
++				val = (s->dma_adc.sample_size == 16) ?
++					AFMT_S16_LE : AFMT_U8;
++			else
++				val = (s->dma_dac.sample_size == 16) ?
++					AFMT_S16_LE : AFMT_U8;
++		}
++		return put_user(val, (int *) arg);
++
++	case SNDCTL_DSP_POST:
++		return 0;
++
++	case SNDCTL_DSP_GETTRIGGER:
++		val = 0;
++		spin_lock_irqsave(&s->lock, flags);
++		if (file->f_mode & FMODE_READ && !s->dma_adc.stopped)
++			val |= PCM_ENABLE_INPUT;
++		if (file->f_mode & FMODE_WRITE && !s->dma_dac.stopped)
++			val |= PCM_ENABLE_OUTPUT;
++		spin_unlock_irqrestore(&s->lock, flags);
++		return put_user(val, (int *) arg);
++
++	case SNDCTL_DSP_SETTRIGGER:
++		if (get_user(val, (int *) arg))
++			return -EFAULT;
++		if (file->f_mode & FMODE_READ) {
++			if (val & PCM_ENABLE_INPUT)
++				start_adc(s);
++			else
++				stop_adc(s);
++		}
++		if (file->f_mode & FMODE_WRITE) {
++			if (val & PCM_ENABLE_OUTPUT)
++				start_dac(s);
++			else
++				stop_dac(s);
++		}
++		return 0;
++
++	case SNDCTL_DSP_GETOSPACE:
++		if (!(file->f_mode & FMODE_WRITE))
++			return -EINVAL;
++		abinfo.fragsize = s->dma_dac.fragsize;
++		spin_lock_irqsave(&s->lock, flags);
++		count = s->dma_dac.count;
++		count -= dma_count_done(&s->dma_dac);
++		spin_unlock_irqrestore(&s->lock, flags);
++		if (count < 0)
++			count = 0;
++		abinfo.bytes = (s->dma_dac.dmasize - count) /
++			s->dma_dac.cnt_factor;
++		abinfo.fragstotal = s->dma_dac.numfrag;
++		abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
++#ifdef AU1000_VERBOSE_DEBUG
++		dbg("bytes=%d, fragments=%d", abinfo.bytes, abinfo.fragments);
++#endif
++		return copy_to_user((void *) arg, &abinfo,
++				    sizeof(abinfo)) ? -EFAULT : 0;
++
++	case SNDCTL_DSP_GETISPACE:
++		if (!(file->f_mode & FMODE_READ))
++			return -EINVAL;
++		abinfo.fragsize = s->dma_adc.fragsize;
++		spin_lock_irqsave(&s->lock, flags);
++		count = s->dma_adc.count;
++		count += dma_count_done(&s->dma_adc);
++		spin_unlock_irqrestore(&s->lock, flags);
++		if (count < 0)
++			count = 0;
++		abinfo.bytes = count / s->dma_adc.cnt_factor;
++		abinfo.fragstotal = s->dma_adc.numfrag;
++		abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
++		return copy_to_user((void *) arg, &abinfo,
++				    sizeof(abinfo)) ? -EFAULT : 0;
++
++	case SNDCTL_DSP_NONBLOCK:
++		file->f_flags |= O_NONBLOCK;
++		return 0;
++
++	case SNDCTL_DSP_GETODELAY:
++		if (!(file->f_mode & FMODE_WRITE))
++			return -EINVAL;
++		spin_lock_irqsave(&s->lock, flags);
++		count = s->dma_dac.count;
++		count -= dma_count_done(&s->dma_dac);
++		spin_unlock_irqrestore(&s->lock, flags);
++		if (count < 0)
++			count = 0;
++		count /= s->dma_dac.cnt_factor;
++		return put_user(count, (int *) arg);
++
++	case SNDCTL_DSP_GETIPTR:
++		if (!(file->f_mode & FMODE_READ))
++			return -EINVAL;
++		spin_lock_irqsave(&s->lock, flags);
++		cinfo.bytes = s->dma_adc.total_bytes;
++		count = s->dma_adc.count;
++		if (!s->dma_adc.stopped) {
++			diff = dma_count_done(&s->dma_adc);
++			count += diff;
++			cinfo.bytes += diff;
++			cinfo.ptr =  virt_to_phys(s->dma_adc.nextIn) + diff -
++				virt_to_phys(s->dma_adc.rawbuf);
++		} else
++			cinfo.ptr = virt_to_phys(s->dma_adc.nextIn) -
++				virt_to_phys(s->dma_adc.rawbuf);
++		if (s->dma_adc.mapped)
++			s->dma_adc.count &= (s->dma_adc.dma_fragsize-1);
++		spin_unlock_irqrestore(&s->lock, flags);
++		if (count < 0)
++			count = 0;
++		cinfo.blocks = count >> s->dma_adc.fragshift;
++		return copy_to_user((void *) arg, &cinfo, sizeof(cinfo));
++
++	case SNDCTL_DSP_GETOPTR:
++		if (!(file->f_mode & FMODE_READ))
++			return -EINVAL;
++		spin_lock_irqsave(&s->lock, flags);
++		cinfo.bytes = s->dma_dac.total_bytes;
++		count = s->dma_dac.count;
++		if (!s->dma_dac.stopped) {
++			diff = dma_count_done(&s->dma_dac);
++			count -= diff;
++			cinfo.bytes += diff;
++			cinfo.ptr = virt_to_phys(s->dma_dac.nextOut) + diff -
++				virt_to_phys(s->dma_dac.rawbuf);
++		} else
++			cinfo.ptr = virt_to_phys(s->dma_dac.nextOut) -
++				virt_to_phys(s->dma_dac.rawbuf);
++		if (s->dma_dac.mapped)
++			s->dma_dac.count &= (s->dma_dac.dma_fragsize-1);
++		spin_unlock_irqrestore(&s->lock, flags);
++		if (count < 0)
++			count = 0;
++		cinfo.blocks = count >> s->dma_dac.fragshift;
++		return copy_to_user((void *) arg, &cinfo, sizeof(cinfo));
++
++	case SNDCTL_DSP_GETBLKSIZE:
++		if (file->f_mode & FMODE_WRITE)
++			return put_user(s->dma_dac.fragsize, (int *) arg);
++		else
++			return put_user(s->dma_adc.fragsize, (int *) arg);
++
++	case SNDCTL_DSP_SETFRAGMENT:
++		if (get_user(val, (int *) arg))
++			return -EFAULT;
++		if (file->f_mode & FMODE_READ) {
++			stop_adc(s);
++			s->dma_adc.ossfragshift = val & 0xffff;
++			s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
++			if (s->dma_adc.ossfragshift < 4)
++				s->dma_adc.ossfragshift = 4;
++			if (s->dma_adc.ossfragshift > 15)
++				s->dma_adc.ossfragshift = 15;
++			if (s->dma_adc.ossmaxfrags < 4)
++				s->dma_adc.ossmaxfrags = 4;
++			if ((ret = prog_dmabuf_adc(s)))
++				return ret;
++		}
++		if (file->f_mode & FMODE_WRITE) {
++			stop_dac(s);
++			s->dma_dac.ossfragshift = val & 0xffff;
++			s->dma_dac.ossmaxfrags = (val >> 16) & 0xffff;
++			if (s->dma_dac.ossfragshift < 4)
++				s->dma_dac.ossfragshift = 4;
++			if (s->dma_dac.ossfragshift > 15)
++				s->dma_dac.ossfragshift = 15;
++			if (s->dma_dac.ossmaxfrags < 4)
++				s->dma_dac.ossmaxfrags = 4;
++			if ((ret = prog_dmabuf_dac(s)))
++				return ret;
++		}
++		return 0;
++
++	case SNDCTL_DSP_SUBDIVIDE:
++		if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
++		    (file->f_mode & FMODE_WRITE && s->dma_dac.subdivision))
++			return -EINVAL;
++		if (get_user(val, (int *) arg))
++			return -EFAULT;
++		if (val != 1 && val != 2 && val != 4)
++			return -EINVAL;
++		if (file->f_mode & FMODE_READ) {
++			stop_adc(s);
++			s->dma_adc.subdivision = val;
++			if ((ret = prog_dmabuf_adc(s)))
++				return ret;
++		}
++		if (file->f_mode & FMODE_WRITE) {
++			stop_dac(s);
++			s->dma_dac.subdivision = val;
++			if ((ret = prog_dmabuf_dac(s)))
++				return ret;
++		}
++		return 0;
++
++	case SOUND_PCM_READ_RATE:
++		return put_user((file->f_mode & FMODE_READ) ?
++				s->dma_adc.sample_rate :
++				s->dma_dac.sample_rate,
++				(int *)arg);
++
++	case SOUND_PCM_READ_CHANNELS:
++		if (file->f_mode & FMODE_READ)
++			return put_user(s->dma_adc.num_channels, (int *)arg);
++		else
++			return put_user(s->dma_dac.num_channels, (int *)arg);
++
++	case SOUND_PCM_READ_BITS:
++		if (file->f_mode & FMODE_READ)
++			return put_user(s->dma_adc.sample_size, (int *)arg);
++		else
++			return put_user(s->dma_dac.sample_size, (int *)arg);
++
++	case SOUND_PCM_WRITE_FILTER:
++	case SNDCTL_DSP_SETSYNCRO:
++	case SOUND_PCM_READ_FILTER:
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++
++static int
++au1550_open(struct inode *inode, struct file *file)
++{
++	int             minor = MINOR(inode->i_rdev);
++	DECLARE_WAITQUEUE(wait, current);
++	struct au1550_state *s = &au1550_state;
++	int             ret;
++
++#ifdef AU1000_VERBOSE_DEBUG
++	if (file->f_flags & O_NONBLOCK)
++		dbg(__FUNCTION__ ": non-blocking");
++	else
++		dbg(__FUNCTION__ ": blocking");
++#endif
++
++	file->private_data = s;
++	/* wait for device to become free */
++	down(&s->open_sem);
++	while (s->open_mode & file->f_mode) {
++		if (file->f_flags & O_NONBLOCK) {
++			up(&s->open_sem);
++			return -EBUSY;
++		}
++		add_wait_queue(&s->open_wait, &wait);
++		__set_current_state(TASK_INTERRUPTIBLE);
++		up(&s->open_sem);
++		schedule();
++		remove_wait_queue(&s->open_wait, &wait);
++		set_current_state(TASK_RUNNING);
++		if (signal_pending(current))
++			return -ERESTARTSYS;
++		down(&s->open_sem);
++	}
++
++	stop_dac(s);
++	stop_adc(s);
++
++	if (file->f_mode & FMODE_READ) {
++		s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags =
++			s->dma_adc.subdivision = s->dma_adc.total_bytes = 0;
++		s->dma_adc.num_channels = 1;
++		s->dma_adc.sample_size = 8;
++		set_adc_rate(s, 8000);
++		if ((minor & 0xf) == SND_DEV_DSP16)
++			s->dma_adc.sample_size = 16;
++	}
++
++	if (file->f_mode & FMODE_WRITE) {
++		s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags =
++			s->dma_dac.subdivision = s->dma_dac.total_bytes = 0;
++		s->dma_dac.num_channels = 1;
++		s->dma_dac.sample_size = 8;
++		set_dac_rate(s, 8000);
++		if ((minor & 0xf) == SND_DEV_DSP16)
++			s->dma_dac.sample_size = 16;
++	}
++
++	if (file->f_mode & FMODE_READ) {
++		if ((ret = prog_dmabuf_adc(s)))
++			return ret;
++	}
++	if (file->f_mode & FMODE_WRITE) {
++		if ((ret = prog_dmabuf_dac(s)))
++			return ret;
++	}
++
++	s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
++	up(&s->open_sem);
++	init_MUTEX(&s->sem);
++	return 0;
++}
++
++static int
++au1550_release(struct inode *inode, struct file *file)
++{
++	struct au1550_state *s = (struct au1550_state *)file->private_data;
++
++	lock_kernel();
++
++	if (file->f_mode & FMODE_WRITE) {
++		unlock_kernel();
++		drain_dac(s, file->f_flags & O_NONBLOCK);
++		lock_kernel();
++	}
++
++	down(&s->open_sem);
++	if (file->f_mode & FMODE_WRITE) {
++		stop_dac(s);
++		kfree(s->dma_dac.rawbuf);
++		s->dma_dac.rawbuf = NULL;
++	}
++	if (file->f_mode & FMODE_READ) {
++		stop_adc(s);
++		kfree(s->dma_adc.rawbuf);
++		s->dma_adc.rawbuf = NULL;
++	}
++	s->open_mode &= ((~file->f_mode) & (FMODE_READ|FMODE_WRITE));
++	up(&s->open_sem);
++	wake_up(&s->open_wait);
++	unlock_kernel();
++	return 0;
++}
++
++static struct file_operations au1550_audio_fops = {
++	owner:		THIS_MODULE,
++	llseek:		au1550_llseek,
++	read:		au1550_read,
++	write:		au1550_write,
++	poll:		au1550_poll,
++	ioctl:		au1550_ioctl,
++	mmap:		au1550_mmap,
++	open:		au1550_open,
++	release:	au1550_release,
++};
++
++/* Set up an internal clock for the PSC3.  This will then get
++ * driven out of the Au1550 as the master.
++ */
++static void
++intclk_setup(void)
++{
++	uint clk, rate;
++
++	/* Wire up Freq4 as a clock for the PSC3.
++	 * We know SMBus uses Freq3.
++	 * By making changes to this rate, plus the word strobe
++	 * size, we can make fine adjustments to the actual data rate.
++	 */
++	rate = get_au1x00_speed();
++#ifdef TRY_441KHz
++	rate /= (11 * 1000000);
++#else
++	rate /= (12 * 1000000);
++#endif
++
++	/* The FRDIV in the frequency control is (FRDIV + 1) * 2
++	*/
++	rate /=2;
++	rate--;
++	clk = au_readl(SYS_FREQCTRL1);
++	au_sync();
++	clk &= ~(SYS_FC_FRDIV4_MASK | SYS_FC_FS4);;
++	clk |= (rate << SYS_FC_FRDIV4_BIT);
++	clk |= SYS_FC_FE4;
++	au_writel(clk, SYS_FREQCTRL1);
++	au_sync();
++
++	/* Set up the clock source routing to get Freq4 to PSC3_intclk.
++	*/
++	clk = au_readl(SYS_CLKSRC);
++	au_sync();
++	clk &= ~0x01f00000;
++	clk |= (6 << 22);
++	au_writel(clk, SYS_CLKSRC);
++	au_sync();
++}
++
++static int __devinit
++au1550_probe(void)
++{
++	struct au1550_state *s = &au1550_state;
++	int val;
++	volatile psc_i2s_t *ip;
++#ifdef AU1550_DEBUG
++	char proc_str[80];
++#endif
++
++	memset(s, 0, sizeof(struct au1550_state));
++
++	init_waitqueue_head(&s->dma_adc.wait);
++	init_waitqueue_head(&s->dma_dac.wait);
++	init_waitqueue_head(&s->open_wait);
++	init_MUTEX(&s->open_sem);
++	spin_lock_init(&s->lock);
++
++	s->codec = &au1550_i2s_codec;
++	s->psc_addr = (volatile psc_i2s_t *)I2S_PSC_BASE;
++	ip = s->psc_addr;
++
++	if (!request_region(CPHYSADDR(ip),
++			    0x30, AU1550_MODULE_NAME)) {
++		pr_error("I2S Audio ports in use");
++	}
++
++	/* Allocate the DMA Channels
++	*/
++	if ((s->dma_dac.dmanr = au1xxx_dbdma_chan_alloc(DBDMA_MEM_CHAN,
++	    DBDMA_I2S_TX_CHAN, dac_dma_interrupt, (void *)s)) == 0) {
++		pr_error("Can't get DAC DMA");
++		goto err_dma1;
++	}
++	au1xxx_dbdma_set_devwidth(s->dma_dac.dmanr, 16);
++	if (au1xxx_dbdma_ring_alloc(s->dma_dac.dmanr,
++					NUM_DBDMA_DESCRIPTORS) == 0) {
++		pr_error("Can't get DAC DMA descriptors");
++		goto err_dma1;
++	}
++
++	if ((s->dma_adc.dmanr = au1xxx_dbdma_chan_alloc(DBDMA_I2S_RX_CHAN,
++	    DBDMA_MEM_CHAN, adc_dma_interrupt, (void *)s)) == 0) {
++		pr_error("Can't get ADC DMA");
++		goto err_dma2;
++	}
++	au1xxx_dbdma_set_devwidth(s->dma_adc.dmanr, 16);
++	if (au1xxx_dbdma_ring_alloc(s->dma_adc.dmanr,
++					NUM_DBDMA_DESCRIPTORS) == 0) {
++		pr_error("Can't get ADC DMA descriptors");
++		goto err_dma2;
++	}
++
++	pr_info("DAC: DMA%d, ADC: DMA%d", DBDMA_I2S_TX_CHAN, DBDMA_I2S_RX_CHAN);
++
++	/* register devices */
++
++	if ((s->dev_audio = register_sound_dsp(&au1550_audio_fops, -1)) < 0)
++		goto err_dev1;
++
++	if ((s->dev_mixer = register_sound_mixer(&au1550_mixer_fops, -1)) < 0)
++		goto err_dev2;
++
++#ifdef AU1550_DEBUG
++	/* intialize the debug proc device */
++	s->ps = create_proc_read_entry(AU1000_MODULE_NAME, 0, NULL,
++				       proc_au1550_dump, NULL);
++#endif /* AU1550_DEBUG */
++
++	intclk_setup();
++
++	/* The GPIO for the appropriate PSC was configured by the
++	 * board specific start up.
++	 *
++	 * configure PSC for I2S Audio
++	 */
++	ip->psc_ctrl = PSC_CTRL_DISABLE;	/* Disable PSC */
++	au_sync();
++	ip->psc_sel = (PSC_SEL_CLK_INTCLK | PSC_SEL_PS_I2SMODE);
++	au_sync();
++
++	/* Enable PSC
++	*/
++	ip->psc_ctrl = PSC_CTRL_ENABLE;
++	au_sync();
++
++	/* Wait for PSC ready.
++	*/
++	do {
++		val = ip->psc_i2sstat;
++		au_sync();
++	} while ((val & PSC_I2SSTAT_SR) == 0);
++
++	/* Configure I2S controller.
++	 * Deep FIFO, 16-bit sample, DMA, make sure DMA matches fifo size.
++	 * Actual I2S mode (first bit delayed by one clock).
++	 * Master mode (We provide the clock from the PSC).
++	 */
++	val = PSC_I2SCFG_SET_LEN(16);
++#ifdef TRY_441KHz
++	/* This really should be 250, but it appears that all of the
++	 * PLLs, dividers and so on in the chain shift it.  That's the
++	 * problem with sourceing the clock instead of letting the very
++	 * stable codec provide it.  But, the PSC doesn't appear to want
++	 * to work in slave mode, so this is what we get.  It's  not
++	 * studio quality timing, but it's good enough for listening
++	 * to mp3s.
++	 */
++	val |= PSC_I2SCFG_SET_WS(252);
++#else
++	val |= PSC_I2SCFG_SET_WS(250);
++#endif
++	val |= PSC_I2SCFG_RT_FIFO8 | PSC_I2SCFG_TT_FIFO8 | \
++					PSC_I2SCFG_BI | PSC_I2SCFG_XM;
++
++	ip->psc_i2scfg = val;
++	au_sync();
++	val |= PSC_I2SCFG_DE_ENABLE;
++	ip->psc_i2scfg = val;
++	au_sync();
++
++	/* Wait for Device ready.
++	*/
++	do {
++		val = ip->psc_i2sstat;
++		au_sync();
++	} while ((val & PSC_I2SSTAT_DR) == 0);
++
++	val = ip->psc_i2scfg;
++	au_sync();
++
++	s->codec->init_codec(s->codec);
++
++	return 0;
++
++ err_dev2:
++	unregister_sound_dsp(s->dev_audio);
++ err_dev1:
++	au1xxx_dbdma_chan_free(s->dma_adc.dmanr);
++ err_dma2:
++	au1xxx_dbdma_chan_free(s->dma_dac.dmanr);
++ err_dma1:
++	release_region(CPHYSADDR(I2S_PSC_BASE), 0x30);
++
++	return -1;
++}
++
++static void __devinit
++au1550_remove(void)
++{
++	struct au1550_state *s = &au1550_state;
++
++	if (!s)
++		return;
++#ifdef AU1550_DEBUG
++	if (s->ps)
++		remove_proc_entry(AU1000_MODULE_NAME, NULL);
++#endif /* AU1000_DEBUG */
++	synchronize_irq();
++	au1xxx_dbdma_chan_free(s->dma_adc.dmanr);
++	au1xxx_dbdma_chan_free(s->dma_dac.dmanr);
++	release_region(CPHYSADDR(I2S_PSC_BASE), 0x30);
++	unregister_sound_dsp(s->dev_audio);
++	unregister_sound_mixer(s->dev_mixer);
++}
++
++static int __init
++init_au1550(void)
++{
++	return au1550_probe();
++}
++
++static void __exit
++cleanup_au1550(void)
++{
++	au1550_remove();
++}
++
++module_init(init_au1550);
++module_exit(cleanup_au1550);
++
++MODULE_AUTHOR("Advanced Micro Devices (AMD), dan@embeddededge.com");
++MODULE_DESCRIPTION("Au1550 I2S Audio Driver");
+diff -Naur linux-2.6.17.orig/sound/oss/Kconfig linux-2.6.17/sound/oss/Kconfig
+--- linux-2.6.17.orig/sound/oss/Kconfig	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/sound/oss/Kconfig	2006-06-19 18:16:14.000000000 -0700
+@@ -117,6 +117,10 @@
+ 	tristate "Au1550 AC97 Sound"
+ 	depends on SOUND_PRIME && SOC_AU1550
+ 
++config SOUND_AU1550_I2S
++	tristate "Au1550 I2S Sound"
++	depends on SOUND_PRIME && SOC_AU1550
++
+ config SOUND_TRIDENT
+ 	tristate "Trident 4DWave DX/NX, SiS 7018 or ALi 5451 PCI Audio Core"
+ 	depends on SOUND_PRIME && PCI
+diff -Naur linux-2.6.17.orig/sound/oss/Makefile linux-2.6.17/sound/oss/Makefile
+--- linux-2.6.17.orig/sound/oss/Makefile	2006-06-17 18:49:35.000000000 -0700
++++ linux-2.6.17/sound/oss/Makefile	2006-06-19 18:16:14.000000000 -0700
+@@ -66,6 +66,7 @@
+ obj-$(CONFIG_SOUND_VRC5477)	+= nec_vrc5477.o ac97_codec.o
+ obj-$(CONFIG_SOUND_AU1000)	+= au1000.o ac97_codec.o
+ obj-$(CONFIG_SOUND_AU1550_AC97)	+= au1550_ac97.o ac97_codec.o
++obj-$(CONFIG_SOUND_AU1550_I2S)	+= au1550_i2s.o
+ obj-$(CONFIG_SOUND_ESSSOLO1)	+= esssolo1.o
+ obj-$(CONFIG_SOUND_FUSION)	+= cs46xx.o ac97_codec.o
+ obj-$(CONFIG_SOUND_MAESTRO)	+= maestro.o
