source:
scripts/fetch/eglibc/2.10.1/10-ppc-atomic.patch@
d38577a
| Last change on this file since d38577a was 5dc2016, checked in by , 15 years ago | |
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| File size: 16.2 KB | |
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sysdeps/powerpc/bits/atomic.h
RCS file: /cvs/glibc/libc/sysdeps/powerpc/bits/atomic.h,v retrieving revision 1.17 diff -u -a -p -r1.17 atomic.h
typedef uintmax_t uatomic_max_t; 85 85 __typeof (*(mem)) __tmp; \ 86 86 __typeof (mem) __memp = (mem); \ 87 87 __asm __volatile ( \ 88 "1: lwarx %0, 0,%1" MUTEX_HINT_ACQ "\n" \88 "1: lwarx %0,%y1" MUTEX_HINT_ACQ "\n" \ 89 89 " cmpw %0,%2\n" \ 90 90 " bne 2f\n" \ 91 " stwcx. %3, 0,%1\n" \91 " stwcx. %3,%y1\n" \ 92 92 " bne- 1b\n" \ 93 93 "2: " __ARCH_ACQ_INSTR \ 94 : "=&r" (__tmp) 95 : " b" (__memp), "r" (oldval), "r" (newval)\94 : "=&r" (__tmp), "+Z" (*__memp) \ 95 : "r" (oldval), "r" (newval) \ 96 96 : "cr0", "memory"); \ 97 97 __tmp; \ 98 98 }) … … typedef uintmax_t uatomic_max_t; 102 102 __typeof (*(mem)) __tmp; \ 103 103 __typeof (mem) __memp = (mem); \ 104 104 __asm __volatile (__ARCH_REL_INSTR "\n" \ 105 "1: lwarx %0, 0,%1" MUTEX_HINT_REL "\n" \105 "1: lwarx %0,%y1" MUTEX_HINT_REL "\n" \ 106 106 " cmpw %0,%2\n" \ 107 107 " bne 2f\n" \ 108 " stwcx. %3, 0,%1\n" \108 " stwcx. %3,%y1\n" \ 109 109 " bne- 1b\n" \ 110 110 "2: " \ 111 : "=&r" (__tmp) 112 : " b" (__memp), "r" (oldval), "r" (newval)\111 : "=&r" (__tmp), "+Z" (__memp) \ 112 : "r" (oldval), "r" (newval) \ 113 113 : "cr0", "memory"); \ 114 114 __tmp; \ 115 115 }) … … typedef uintmax_t uatomic_max_t; 118 118 ({ \ 119 119 __typeof (*mem) __val; \ 120 120 __asm __volatile ( \ 121 "1: lwarx %0, 0,%2" MUTEX_HINT_ACQ "\n" \122 " stwcx. % 3,0,%2\n" \121 "1: lwarx %0,%y1" MUTEX_HINT_ACQ "\n" \ 122 " stwcx. %2,%y1\n" \ 123 123 " bne- 1b\n" \ 124 124 " " __ARCH_ACQ_INSTR \ 125 : "=&r" (__val), " =m" (*mem) \126 : " b" (mem), "r" (value), "m" (*mem)\125 : "=&r" (__val), "+Z" (*mem) \ 126 : "r" (value) \ 127 127 : "cr0", "memory"); \ 128 128 __val; \ 129 129 }) … … typedef uintmax_t uatomic_max_t; 132 132 ({ \ 133 133 __typeof (*mem) __val; \ 134 134 __asm __volatile (__ARCH_REL_INSTR "\n" \ 135 "1: lwarx %0, 0,%2" MUTEX_HINT_REL "\n" \136 " stwcx. % 3,0,%2\n" \135 "1: lwarx %0,%y1" MUTEX_HINT_REL "\n" \ 136 " stwcx. %2,%y1\n" \ 137 137 " bne- 1b" \ 138 : "=&r" (__val), " =m" (*mem) \139 : " b" (mem), "r" (value), "m" (*mem)\138 : "=&r" (__val), "+Z" (*mem) \ 139 : "r" (value) \ 140 140 : "cr0", "memory"); \ 141 141 __val; \ 142 142 }) … … typedef uintmax_t uatomic_max_t; 144 144 #define __arch_atomic_exchange_and_add_32(mem, value) \ 145 145 ({ \ 146 146 __typeof (*mem) __val, __tmp; \ 147 __asm __volatile ("1: lwarx %0, 0,%3\n" \148 " add %1,%0,% 4\n" \149 " stwcx. %1, 0,%3\n" \147 __asm __volatile ("1: lwarx %0,%y2\n" \ 148 " add %1,%0,%3\n" \ 149 " stwcx. %1,%y2\n" \ 150 150 " bne- 1b" \ 151 : "=&b" (__val), "=&r" (__tmp), " =m" (*mem) \152 : " b" (mem), "r" (value), "m" (*mem)\151 : "=&b" (__val), "=&r" (__tmp), "+Z" (*mem) \ 152 : "r" (value) \ 153 153 : "cr0", "memory"); \ 154 154 __val; \ 155 155 }) … … typedef uintmax_t uatomic_max_t; 157 157 #define __arch_atomic_increment_val_32(mem) \ 158 158 ({ \ 159 159 __typeof (*(mem)) __val; \ 160 __asm __volatile ("1: lwarx %0, 0,%2\n" \160 __asm __volatile ("1: lwarx %0,%y1\n" \ 161 161 " addi %0,%0,1\n" \ 162 " stwcx. %0, 0,%2\n" \162 " stwcx. %0,%y1\n" \ 163 163 " bne- 1b" \ 164 : "=&b" (__val), " =m" (*mem) \165 : "b" (mem), "m" (*mem)\164 : "=&b" (__val), "+Z" (*mem) \ 165 : \ 166 166 : "cr0", "memory"); \ 167 167 __val; \ 168 168 }) … … typedef uintmax_t uatomic_max_t; 170 170 #define __arch_atomic_decrement_val_32(mem) \ 171 171 ({ \ 172 172 __typeof (*(mem)) __val; \ 173 __asm __volatile ("1: lwarx %0, 0,%2\n" \173 __asm __volatile ("1: lwarx %0,%y1\n" \ 174 174 " subi %0,%0,1\n" \ 175 " stwcx. %0, 0,%2\n" \175 " stwcx. %0,%y1\n" \ 176 176 " bne- 1b" \ 177 : "=&b" (__val), " =m" (*mem) \178 : "b" (mem), "m" (*mem)\177 : "=&b" (__val), "+Z" (*mem) \ 178 : \ 179 179 : "cr0", "memory"); \ 180 180 __val; \ 181 181 }) 182 182 183 183 #define __arch_atomic_decrement_if_positive_32(mem) \ 184 184 ({ int __val, __tmp; \ 185 __asm __volatile ("1: lwarx %0, 0,%3\n" \185 __asm __volatile ("1: lwarx %0,%y2\n" \ 186 186 " cmpwi 0,%0,0\n" \ 187 187 " addi %1,%0,-1\n" \ 188 188 " ble 2f\n" \ 189 " stwcx. %1, 0,%3\n" \189 " stwcx. %1,%y2\n" \ 190 190 " bne- 1b\n" \ 191 191 "2: " __ARCH_ACQ_INSTR \ 192 : "=&b" (__val), "=&r" (__tmp), " =m" (*mem) \193 : "b" (mem), "m" (*mem)\192 : "=&b" (__val), "=&r" (__tmp), "+Z" (*mem) \ 193 : \ 194 194 : "cr0", "memory"); \ 195 195 __val; \ 196 196 }) -
sysdeps/powerpc/powerpc32/bits/atomic.h
RCS file: /cvs/glibc/libc/sysdeps/powerpc/powerpc32/bits/atomic.h,v retrieving revision 1.6 diff -u -a -p -r1.6 atomic.h
44 44 ({ \ 45 45 unsigned int __tmp; \ 46 46 __asm __volatile ( \ 47 "1: lwarx %0, 0,%1" MUTEX_HINT_ACQ "\n" \47 "1: lwarx %0,%y1" MUTEX_HINT_ACQ "\n" \ 48 48 " subf. %0,%2,%0\n" \ 49 49 " bne 2f\n" \ 50 " stwcx. %3, 0,%1\n" \50 " stwcx. %3,%y1\n" \ 51 51 " bne- 1b\n" \ 52 52 "2: " __ARCH_ACQ_INSTR \ 53 : "=&r" (__tmp) 54 : " b" (mem), "r" (oldval), "r" (newval)\53 : "=&r" (__tmp), "+Z" (*(mem)) \ 54 : "r" (oldval), "r" (newval) \ 55 55 : "cr0", "memory"); \ 56 56 __tmp != 0; \ 57 57 }) … … 60 60 ({ \ 61 61 unsigned int __tmp; \ 62 62 __asm __volatile (__ARCH_REL_INSTR "\n" \ 63 "1: lwarx %0, 0,%1" MUTEX_HINT_REL "\n" \63 "1: lwarx %0,%y1" MUTEX_HINT_REL "\n" \ 64 64 " subf. %0,%2,%0\n" \ 65 65 " bne 2f\n" \ 66 " stwcx. %3, 0,%1\n" \66 " stwcx. %3,%y1\n" \ 67 67 " bne- 1b\n" \ 68 68 "2: " \ 69 : "=&r" (__tmp) 70 : " b" (mem), "r" (oldval), "r" (newval)\69 : "=&r" (__tmp), "+Z" (*(mem)) \ 70 : "r" (oldval), "r" (newval) \ 71 71 : "cr0", "memory"); \ 72 72 __tmp != 0; \ 73 73 }) -
sysdeps/powerpc/powerpc64/bits/atomic.h
RCS file: /cvs/glibc/libc/sysdeps/powerpc/powerpc64/bits/atomic.h,v retrieving revision 1.8 diff -u -a -p -r1.8 atomic.h
44 44 ({ \ 45 45 unsigned int __tmp, __tmp2; \ 46 46 __asm __volatile (" clrldi %1,%1,32\n" \ 47 "1: lwarx %0, 0,%2" MUTEX_HINT_ACQ "\n" \47 "1: lwarx %0,%y2" MUTEX_HINT_ACQ "\n" \ 48 48 " subf. %0,%1,%0\n" \ 49 49 " bne 2f\n" \ 50 " stwcx. %4, 0,%2\n" \50 " stwcx. %4,%y2\n" \ 51 51 " bne- 1b\n" \ 52 52 "2: " __ARCH_ACQ_INSTR \ 53 : "=&r" (__tmp), "=r" (__tmp2) 54 : " b" (mem), "1" (oldval), "r" (newval)\53 : "=&r" (__tmp), "=r" (__tmp2), "+Z" (*(mem)) \ 54 : "1" (oldval), "r" (newval) \ 55 55 : "cr0", "memory"); \ 56 56 __tmp != 0; \ 57 57 }) … … 61 61 unsigned int __tmp, __tmp2; \ 62 62 __asm __volatile (__ARCH_REL_INSTR "\n" \ 63 63 " clrldi %1,%1,32\n" \ 64 "1: lwarx %0, 0,%2" MUTEX_HINT_REL "\n" \64 "1: lwarx %0,%y2" MUTEX_HINT_REL "\n" \ 65 65 " subf. %0,%1,%0\n" \ 66 66 " bne 2f\n" \ 67 " stwcx. %4, 0,%2\n" \67 " stwcx. %4,%y2\n" \ 68 68 " bne- 1b\n" \ 69 69 "2: " \ 70 : "=&r" (__tmp), "=r" (__tmp2) 71 : " b" (mem), "1" (oldval), "r" (newval)\70 : "=&r" (__tmp), "=r" (__tmp2), "+Z" (*(mem)) \ 71 : "1" (oldval), "r" (newval) \ 72 72 : "cr0", "memory"); \ 73 73 __tmp != 0; \ 74 74 }) … … 82 82 ({ \ 83 83 unsigned long __tmp; \ 84 84 __asm __volatile ( \ 85 "1: ldarx %0, 0,%1" MUTEX_HINT_ACQ "\n" \85 "1: ldarx %0,%y1" MUTEX_HINT_ACQ "\n" \ 86 86 " subf. %0,%2,%0\n" \ 87 87 " bne 2f\n" \ 88 " stdcx. %3, 0,%1\n" \88 " stdcx. %3,%y1\n" \ 89 89 " bne- 1b\n" \ 90 90 "2: " __ARCH_ACQ_INSTR \ 91 : "=&r" (__tmp) 92 : " b" (mem), "r" (oldval), "r" (newval)\91 : "=&r" (__tmp), "+Z" (*(mem)) \ 92 : "r" (oldval), "r" (newval) \ 93 93 : "cr0", "memory"); \ 94 94 __tmp != 0; \ 95 95 }) … … 98 98 ({ \ 99 99 unsigned long __tmp; \ 100 100 __asm __volatile (__ARCH_REL_INSTR "\n" \ 101 "1: ldarx %0, 0,%2" MUTEX_HINT_REL "\n" \101 "1: ldarx %0,%y1" MUTEX_HINT_REL "\n" \ 102 102 " subf. %0,%2,%0\n" \ 103 103 " bne 2f\n" \ 104 " stdcx. %3, 0,%1\n" \104 " stdcx. %3,%y1\n" \ 105 105 " bne- 1b\n" \ 106 106 "2: " \ 107 : "=&r" (__tmp) 108 : " b" (mem), "r" (oldval), "r" (newval)\107 : "=&r" (__tmp), "+Z" (*(mem)) \ 108 : "r" (oldval), "r" (newval) \ 109 109 : "cr0", "memory"); \ 110 110 __tmp != 0; \ 111 111 }) … … 115 115 __typeof (*(mem)) __tmp; \ 116 116 __typeof (mem) __memp = (mem); \ 117 117 __asm __volatile ( \ 118 "1: ldarx %0, 0,%1" MUTEX_HINT_ACQ "\n" \118 "1: ldarx %0,%y1" MUTEX_HINT_ACQ "\n" \ 119 119 " cmpd %0,%2\n" \ 120 120 " bne 2f\n" \ 121 " stdcx. %3, 0,%1\n" \121 " stdcx. %3,%y1\n" \ 122 122 " bne- 1b\n" \ 123 123 "2: " __ARCH_ACQ_INSTR \ 124 : "=&r" (__tmp) 125 : " b" (__memp), "r" (oldval), "r" (newval)\124 : "=&r" (__tmp), "+Z" (*__memp) \ 125 : "r" (oldval), "r" (newval) \ 126 126 : "cr0", "memory"); \ 127 127 __tmp; \ 128 128 }) … … 132 132 __typeof (*(mem)) __tmp; \ 133 133 __typeof (mem) __memp = (mem); \ 134 134 __asm __volatile (__ARCH_REL_INSTR "\n" \ 135 "1: ldarx %0, 0,%1" MUTEX_HINT_REL "\n" \135 "1: ldarx %0,%y1" MUTEX_HINT_REL "\n" \ 136 136 " cmpd %0,%2\n" \ 137 137 " bne 2f\n" \ 138 " stdcx. %3, 0,%1\n" \138 " stdcx. %3,%y1\n" \ 139 139 " bne- 1b\n" \ 140 140 "2: " \ 141 : "=&r" (__tmp) 142 : " b" (__memp), "r" (oldval), "r" (newval)\141 : "=&r" (__tmp), "+Z" (*__memp) \ 142 : "r" (oldval), "r" (newval) \ 143 143 : "cr0", "memory"); \ 144 144 __tmp; \ 145 145 }) … … 148 148 ({ \ 149 149 __typeof (*mem) __val; \ 150 150 __asm __volatile (__ARCH_REL_INSTR "\n" \ 151 "1: ldarx %0, 0,%2" MUTEX_HINT_ACQ "\n" \152 " stdcx. % 3,0,%2\n" \151 "1: ldarx %0,%y1" MUTEX_HINT_ACQ "\n" \ 152 " stdcx. %2,%y1\n" \ 153 153 " bne- 1b\n" \ 154 154 " " __ARCH_ACQ_INSTR \ 155 : "=&r" (__val), " =m" (*mem) \156 : " b" (mem), "r" (value), "m" (*mem)\155 : "=&r" (__val), "+Z" (*(mem)) \ 156 : "r" (value) \ 157 157 : "cr0", "memory"); \ 158 158 __val; \ 159 159 }) … … 162 162 ({ \ 163 163 __typeof (*mem) __val; \ 164 164 __asm __volatile (__ARCH_REL_INSTR "\n" \ 165 "1: ldarx %0, 0,%2" MUTEX_HINT_REL "\n" \166 " stdcx. % 3,0,%2\n" \165 "1: ldarx %0,%y1" MUTEX_HINT_REL "\n" \ 166 " stdcx. %2,%y1\n" \ 167 167 " bne- 1b" \ 168 : "=&r" (__val), " =m" (*mem) \169 : " b" (mem), "r" (value), "m" (*mem)\168 : "=&r" (__val), "+Z" (*(mem)) \ 169 : "r" (value) \ 170 170 : "cr0", "memory"); \ 171 171 __val; \ 172 172 }) … … 174 174 #define __arch_atomic_exchange_and_add_64(mem, value) \ 175 175 ({ \ 176 176 __typeof (*mem) __val, __tmp; \ 177 __asm __volatile ("1: ldarx %0, 0,%3\n" \178 " add %1,%0,% 4\n" \179 " stdcx. %1, 0,%3\n" \177 __asm __volatile ("1: ldarx %0,%y2\n" \ 178 " add %1,%0,%3\n" \ 179 " stdcx. %1,%y2\n" \ 180 180 " bne- 1b" \ 181 : "=&b" (__val), "=&r" (__tmp), " =m" (*mem) \182 : " b" (mem), "r" (value), "m" (*mem)\181 : "=&b" (__val), "=&r" (__tmp), "+Z" (*(mem)) \ 182 : "r" (value) \ 183 183 : "cr0", "memory"); \ 184 184 __val; \ 185 185 }) … … 187 187 #define __arch_atomic_increment_val_64(mem) \ 188 188 ({ \ 189 189 __typeof (*(mem)) __val; \ 190 __asm __volatile ("1: ldarx %0, 0,%2\n" \190 __asm __volatile ("1: ldarx %0,%y1\n" \ 191 191 " addi %0,%0,1\n" \ 192 " stdcx. %0, 0,%2\n" \192 " stdcx. %0,%y1\n" \ 193 193 " bne- 1b" \ 194 : "=&b" (__val), " =m" (*mem) \195 : "b" (mem), "m" (*mem)\194 : "=&b" (__val), "+Z" (*(mem)) \ 195 : \ 196 196 : "cr0", "memory"); \ 197 197 __val; \ 198 198 }) … … 200 200 #define __arch_atomic_decrement_val_64(mem) \ 201 201 ({ \ 202 202 __typeof (*(mem)) __val; \ 203 __asm __volatile ("1: ldarx %0, 0,%2\n" \203 __asm __volatile ("1: ldarx %0,%y1\n" \ 204 204 " subi %0,%0,1\n" \ 205 " stdcx. %0, 0,%2\n" \205 " stdcx. %0,%y1\n" \ 206 206 " bne- 1b" \ 207 : "=&b" (__val), " =m" (*mem) \208 : "b" (mem), "m" (*mem)\207 : "=&b" (__val), "+Z" (*(mem)) \ 208 : \ 209 209 : "cr0", "memory"); \ 210 210 __val; \ 211 211 }) 212 212 213 213 #define __arch_atomic_decrement_if_positive_64(mem) \ 214 214 ({ int __val, __tmp; \ 215 __asm __volatile ("1: ldarx %0, 0,%3\n" \215 __asm __volatile ("1: ldarx %0,%y2\n" \ 216 216 " cmpdi 0,%0,0\n" \ 217 217 " addi %1,%0,-1\n" \ 218 218 " ble 2f\n" \ 219 " stdcx. %1, 0,%3\n" \219 " stdcx. %1,%y2\n" \ 220 220 " bne- 1b\n" \ 221 221 "2: " __ARCH_ACQ_INSTR \ 222 : "=&b" (__val), "=&r" (__tmp), " =m" (*mem) \223 : "b" (mem), "m" (*mem)\222 : "=&b" (__val), "=&r" (__tmp), "+Z" (*(mem)) \ 223 : \ 224 224 : "cr0", "memory"); \ 225 225 __val; \ 226 226 })
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