source: scripts/fetch/eglibc/2.10.1/10-ppc-atomic.patch@ 728b4b2

clfs-2.1 clfs-3.0.0-systemd clfs-3.0.0-sysvinit systemd sysvinit
Last change on this file since 728b4b2 was 5dc2016, checked in by Jim Gifford <clfs@…>, 15 years ago

Changed extension from diff to patch
  • Property mode set to 100644
File size: 16.2 KB
RevLine 
[b17b911f]1Index: sysdeps/powerpc/bits/atomic.h
2===================================================================
3RCS file: /cvs/glibc/libc/sysdeps/powerpc/bits/atomic.h,v
4retrieving revision 1.17
5diff -u -a -p -r1.17 atomic.h
6--- sysdeps/powerpc/bits/atomic.h 26 Mar 2007 20:15:28 -0000 1.17
7+++ sysdeps/powerpc/bits/atomic.h 31 May 2008 08:50:56 -0000
8@@ -85,14 +85,14 @@ typedef uintmax_t uatomic_max_t;
9 __typeof (*(mem)) __tmp; \
10 __typeof (mem) __memp = (mem); \
11 __asm __volatile ( \
12- "1: lwarx %0,0,%1" MUTEX_HINT_ACQ "\n" \
13+ "1: lwarx %0,%y1" MUTEX_HINT_ACQ "\n" \
14 " cmpw %0,%2\n" \
15 " bne 2f\n" \
16- " stwcx. %3,0,%1\n" \
17+ " stwcx. %3,%y1\n" \
18 " bne- 1b\n" \
19 "2: " __ARCH_ACQ_INSTR \
20- : "=&r" (__tmp) \
21- : "b" (__memp), "r" (oldval), "r" (newval) \
22+ : "=&r" (__tmp), "+Z" (*__memp) \
23+ : "r" (oldval), "r" (newval) \
24 : "cr0", "memory"); \
25 __tmp; \
26 })
27@@ -102,14 +102,14 @@ typedef uintmax_t uatomic_max_t;
28 __typeof (*(mem)) __tmp; \
29 __typeof (mem) __memp = (mem); \
30 __asm __volatile (__ARCH_REL_INSTR "\n" \
31- "1: lwarx %0,0,%1" MUTEX_HINT_REL "\n" \
32+ "1: lwarx %0,%y1" MUTEX_HINT_REL "\n" \
33 " cmpw %0,%2\n" \
34 " bne 2f\n" \
35- " stwcx. %3,0,%1\n" \
36+ " stwcx. %3,%y1\n" \
37 " bne- 1b\n" \
38 "2: " \
39- : "=&r" (__tmp) \
40- : "b" (__memp), "r" (oldval), "r" (newval) \
41+ : "=&r" (__tmp), "+Z" (__memp) \
42+ : "r" (oldval), "r" (newval) \
43 : "cr0", "memory"); \
44 __tmp; \
45 })
46@@ -118,12 +118,12 @@ typedef uintmax_t uatomic_max_t;
47 ({ \
48 __typeof (*mem) __val; \
49 __asm __volatile ( \
50- "1: lwarx %0,0,%2" MUTEX_HINT_ACQ "\n" \
51- " stwcx. %3,0,%2\n" \
52+ "1: lwarx %0,%y1" MUTEX_HINT_ACQ "\n" \
53+ " stwcx. %2,%y1\n" \
54 " bne- 1b\n" \
55 " " __ARCH_ACQ_INSTR \
56- : "=&r" (__val), "=m" (*mem) \
57- : "b" (mem), "r" (value), "m" (*mem) \
58+ : "=&r" (__val), "+Z" (*mem) \
59+ : "r" (value) \
60 : "cr0", "memory"); \
61 __val; \
62 })
63@@ -132,11 +132,11 @@ typedef uintmax_t uatomic_max_t;
64 ({ \
65 __typeof (*mem) __val; \
66 __asm __volatile (__ARCH_REL_INSTR "\n" \
67- "1: lwarx %0,0,%2" MUTEX_HINT_REL "\n" \
68- " stwcx. %3,0,%2\n" \
69+ "1: lwarx %0,%y1" MUTEX_HINT_REL "\n" \
70+ " stwcx. %2,%y1\n" \
71 " bne- 1b" \
72- : "=&r" (__val), "=m" (*mem) \
73- : "b" (mem), "r" (value), "m" (*mem) \
74+ : "=&r" (__val), "+Z" (*mem) \
75+ : "r" (value) \
76 : "cr0", "memory"); \
77 __val; \
78 })
79@@ -144,12 +144,12 @@ typedef uintmax_t uatomic_max_t;
80 #define __arch_atomic_exchange_and_add_32(mem, value) \
81 ({ \
82 __typeof (*mem) __val, __tmp; \
83- __asm __volatile ("1: lwarx %0,0,%3\n" \
84- " add %1,%0,%4\n" \
85- " stwcx. %1,0,%3\n" \
86+ __asm __volatile ("1: lwarx %0,%y2\n" \
87+ " add %1,%0,%3\n" \
88+ " stwcx. %1,%y2\n" \
89 " bne- 1b" \
90- : "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \
91- : "b" (mem), "r" (value), "m" (*mem) \
92+ : "=&b" (__val), "=&r" (__tmp), "+Z" (*mem) \
93+ : "r" (value) \
94 : "cr0", "memory"); \
95 __val; \
96 })
97@@ -157,12 +157,12 @@ typedef uintmax_t uatomic_max_t;
98 #define __arch_atomic_increment_val_32(mem) \
99 ({ \
100 __typeof (*(mem)) __val; \
101- __asm __volatile ("1: lwarx %0,0,%2\n" \
102+ __asm __volatile ("1: lwarx %0,%y1\n" \
103 " addi %0,%0,1\n" \
104- " stwcx. %0,0,%2\n" \
105+ " stwcx. %0,%y1\n" \
106 " bne- 1b" \
107- : "=&b" (__val), "=m" (*mem) \
108- : "b" (mem), "m" (*mem) \
109+ : "=&b" (__val), "+Z" (*mem) \
110+ : \
111 : "cr0", "memory"); \
112 __val; \
113 })
114@@ -170,27 +170,27 @@ typedef uintmax_t uatomic_max_t;
115 #define __arch_atomic_decrement_val_32(mem) \
116 ({ \
117 __typeof (*(mem)) __val; \
118- __asm __volatile ("1: lwarx %0,0,%2\n" \
119+ __asm __volatile ("1: lwarx %0,%y1\n" \
120 " subi %0,%0,1\n" \
121- " stwcx. %0,0,%2\n" \
122+ " stwcx. %0,%y1\n" \
123 " bne- 1b" \
124- : "=&b" (__val), "=m" (*mem) \
125- : "b" (mem), "m" (*mem) \
126+ : "=&b" (__val), "+Z" (*mem) \
127+ : \
128 : "cr0", "memory"); \
129 __val; \
130 })
131
132 #define __arch_atomic_decrement_if_positive_32(mem) \
133 ({ int __val, __tmp; \
134- __asm __volatile ("1: lwarx %0,0,%3\n" \
135+ __asm __volatile ("1: lwarx %0,%y2\n" \
136 " cmpwi 0,%0,0\n" \
137 " addi %1,%0,-1\n" \
138 " ble 2f\n" \
139- " stwcx. %1,0,%3\n" \
140+ " stwcx. %1,%y2\n" \
141 " bne- 1b\n" \
142 "2: " __ARCH_ACQ_INSTR \
143- : "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \
144- : "b" (mem), "m" (*mem) \
145+ : "=&b" (__val), "=&r" (__tmp), "+Z" (*mem) \
146+ : \
147 : "cr0", "memory"); \
148 __val; \
149 })
150Index: sysdeps/powerpc/powerpc32/bits/atomic.h
151===================================================================
152RCS file: /cvs/glibc/libc/sysdeps/powerpc/powerpc32/bits/atomic.h,v
153retrieving revision 1.6
154diff -u -a -p -r1.6 atomic.h
155--- sysdeps/powerpc/powerpc32/bits/atomic.h 26 Mar 2007 20:15:45 -0000 1.6
156+++ sysdeps/powerpc/powerpc32/bits/atomic.h 31 May 2008 08:50:56 -0000
157@@ -44,14 +44,14 @@
158 ({ \
159 unsigned int __tmp; \
160 __asm __volatile ( \
161- "1: lwarx %0,0,%1" MUTEX_HINT_ACQ "\n" \
162+ "1: lwarx %0,%y1" MUTEX_HINT_ACQ "\n" \
163 " subf. %0,%2,%0\n" \
164 " bne 2f\n" \
165- " stwcx. %3,0,%1\n" \
166+ " stwcx. %3,%y1\n" \
167 " bne- 1b\n" \
168 "2: " __ARCH_ACQ_INSTR \
169- : "=&r" (__tmp) \
170- : "b" (mem), "r" (oldval), "r" (newval) \
171+ : "=&r" (__tmp), "+Z" (*(mem)) \
172+ : "r" (oldval), "r" (newval) \
173 : "cr0", "memory"); \
174 __tmp != 0; \
175 })
176@@ -60,14 +60,14 @@
177 ({ \
178 unsigned int __tmp; \
179 __asm __volatile (__ARCH_REL_INSTR "\n" \
180- "1: lwarx %0,0,%1" MUTEX_HINT_REL "\n" \
181+ "1: lwarx %0,%y1" MUTEX_HINT_REL "\n" \
182 " subf. %0,%2,%0\n" \
183 " bne 2f\n" \
184- " stwcx. %3,0,%1\n" \
185+ " stwcx. %3,%y1\n" \
186 " bne- 1b\n" \
187 "2: " \
188- : "=&r" (__tmp) \
189- : "b" (mem), "r" (oldval), "r" (newval) \
190+ : "=&r" (__tmp), "+Z" (*(mem)) \
191+ : "r" (oldval), "r" (newval) \
192 : "cr0", "memory"); \
193 __tmp != 0; \
194 })
195Index: sysdeps/powerpc/powerpc64/bits/atomic.h
196===================================================================
197RCS file: /cvs/glibc/libc/sysdeps/powerpc/powerpc64/bits/atomic.h,v
198retrieving revision 1.8
199diff -u -a -p -r1.8 atomic.h
200--- sysdeps/powerpc/powerpc64/bits/atomic.h 26 Mar 2007 20:16:03 -0000 1.8
201+++ sysdeps/powerpc/powerpc64/bits/atomic.h 31 May 2008 08:50:56 -0000
202@@ -44,14 +44,14 @@
203 ({ \
204 unsigned int __tmp, __tmp2; \
205 __asm __volatile (" clrldi %1,%1,32\n" \
206- "1: lwarx %0,0,%2" MUTEX_HINT_ACQ "\n" \
207+ "1: lwarx %0,%y2" MUTEX_HINT_ACQ "\n" \
208 " subf. %0,%1,%0\n" \
209 " bne 2f\n" \
210- " stwcx. %4,0,%2\n" \
211+ " stwcx. %4,%y2\n" \
212 " bne- 1b\n" \
213 "2: " __ARCH_ACQ_INSTR \
214- : "=&r" (__tmp), "=r" (__tmp2) \
215- : "b" (mem), "1" (oldval), "r" (newval) \
216+ : "=&r" (__tmp), "=r" (__tmp2), "+Z" (*(mem)) \
217+ : "1" (oldval), "r" (newval) \
218 : "cr0", "memory"); \
219 __tmp != 0; \
220 })
221@@ -61,14 +61,14 @@
222 unsigned int __tmp, __tmp2; \
223 __asm __volatile (__ARCH_REL_INSTR "\n" \
224 " clrldi %1,%1,32\n" \
225- "1: lwarx %0,0,%2" MUTEX_HINT_REL "\n" \
226+ "1: lwarx %0,%y2" MUTEX_HINT_REL "\n" \
227 " subf. %0,%1,%0\n" \
228 " bne 2f\n" \
229- " stwcx. %4,0,%2\n" \
230+ " stwcx. %4,%y2\n" \
231 " bne- 1b\n" \
232 "2: " \
233- : "=&r" (__tmp), "=r" (__tmp2) \
234- : "b" (mem), "1" (oldval), "r" (newval) \
235+ : "=&r" (__tmp), "=r" (__tmp2), "+Z" (*(mem)) \
236+ : "1" (oldval), "r" (newval) \
237 : "cr0", "memory"); \
238 __tmp != 0; \
239 })
240@@ -82,14 +82,14 @@
241 ({ \
242 unsigned long __tmp; \
243 __asm __volatile ( \
244- "1: ldarx %0,0,%1" MUTEX_HINT_ACQ "\n" \
245+ "1: ldarx %0,%y1" MUTEX_HINT_ACQ "\n" \
246 " subf. %0,%2,%0\n" \
247 " bne 2f\n" \
248- " stdcx. %3,0,%1\n" \
249+ " stdcx. %3,%y1\n" \
250 " bne- 1b\n" \
251 "2: " __ARCH_ACQ_INSTR \
252- : "=&r" (__tmp) \
253- : "b" (mem), "r" (oldval), "r" (newval) \
254+ : "=&r" (__tmp), "+Z" (*(mem)) \
255+ : "r" (oldval), "r" (newval) \
256 : "cr0", "memory"); \
257 __tmp != 0; \
258 })
259@@ -98,14 +98,14 @@
260 ({ \
261 unsigned long __tmp; \
262 __asm __volatile (__ARCH_REL_INSTR "\n" \
263- "1: ldarx %0,0,%2" MUTEX_HINT_REL "\n" \
264+ "1: ldarx %0,%y1" MUTEX_HINT_REL "\n" \
265 " subf. %0,%2,%0\n" \
266 " bne 2f\n" \
267- " stdcx. %3,0,%1\n" \
268+ " stdcx. %3,%y1\n" \
269 " bne- 1b\n" \
270 "2: " \
271- : "=&r" (__tmp) \
272- : "b" (mem), "r" (oldval), "r" (newval) \
273+ : "=&r" (__tmp), "+Z" (*(mem)) \
274+ : "r" (oldval), "r" (newval) \
275 : "cr0", "memory"); \
276 __tmp != 0; \
277 })
278@@ -115,14 +115,14 @@
279 __typeof (*(mem)) __tmp; \
280 __typeof (mem) __memp = (mem); \
281 __asm __volatile ( \
282- "1: ldarx %0,0,%1" MUTEX_HINT_ACQ "\n" \
283+ "1: ldarx %0,%y1" MUTEX_HINT_ACQ "\n" \
284 " cmpd %0,%2\n" \
285 " bne 2f\n" \
286- " stdcx. %3,0,%1\n" \
287+ " stdcx. %3,%y1\n" \
288 " bne- 1b\n" \
289 "2: " __ARCH_ACQ_INSTR \
290- : "=&r" (__tmp) \
291- : "b" (__memp), "r" (oldval), "r" (newval) \
292+ : "=&r" (__tmp), "+Z" (*__memp) \
293+ : "r" (oldval), "r" (newval) \
294 : "cr0", "memory"); \
295 __tmp; \
296 })
297@@ -132,14 +132,14 @@
298 __typeof (*(mem)) __tmp; \
299 __typeof (mem) __memp = (mem); \
300 __asm __volatile (__ARCH_REL_INSTR "\n" \
301- "1: ldarx %0,0,%1" MUTEX_HINT_REL "\n" \
302+ "1: ldarx %0,%y1" MUTEX_HINT_REL "\n" \
303 " cmpd %0,%2\n" \
304 " bne 2f\n" \
305- " stdcx. %3,0,%1\n" \
306+ " stdcx. %3,%y1\n" \
307 " bne- 1b\n" \
308 "2: " \
309- : "=&r" (__tmp) \
310- : "b" (__memp), "r" (oldval), "r" (newval) \
311+ : "=&r" (__tmp), "+Z" (*__memp) \
312+ : "r" (oldval), "r" (newval) \
313 : "cr0", "memory"); \
314 __tmp; \
315 })
316@@ -148,12 +148,12 @@
317 ({ \
318 __typeof (*mem) __val; \
319 __asm __volatile (__ARCH_REL_INSTR "\n" \
320- "1: ldarx %0,0,%2" MUTEX_HINT_ACQ "\n" \
321- " stdcx. %3,0,%2\n" \
322+ "1: ldarx %0,%y1" MUTEX_HINT_ACQ "\n" \
323+ " stdcx. %2,%y1\n" \
324 " bne- 1b\n" \
325 " " __ARCH_ACQ_INSTR \
326- : "=&r" (__val), "=m" (*mem) \
327- : "b" (mem), "r" (value), "m" (*mem) \
328+ : "=&r" (__val), "+Z" (*(mem)) \
329+ : "r" (value) \
330 : "cr0", "memory"); \
331 __val; \
332 })
333@@ -162,11 +162,11 @@
334 ({ \
335 __typeof (*mem) __val; \
336 __asm __volatile (__ARCH_REL_INSTR "\n" \
337- "1: ldarx %0,0,%2" MUTEX_HINT_REL "\n" \
338- " stdcx. %3,0,%2\n" \
339+ "1: ldarx %0,%y1" MUTEX_HINT_REL "\n" \
340+ " stdcx. %2,%y1\n" \
341 " bne- 1b" \
342- : "=&r" (__val), "=m" (*mem) \
343- : "b" (mem), "r" (value), "m" (*mem) \
344+ : "=&r" (__val), "+Z" (*(mem)) \
345+ : "r" (value) \
346 : "cr0", "memory"); \
347 __val; \
348 })
349@@ -174,12 +174,12 @@
350 #define __arch_atomic_exchange_and_add_64(mem, value) \
351 ({ \
352 __typeof (*mem) __val, __tmp; \
353- __asm __volatile ("1: ldarx %0,0,%3\n" \
354- " add %1,%0,%4\n" \
355- " stdcx. %1,0,%3\n" \
356+ __asm __volatile ("1: ldarx %0,%y2\n" \
357+ " add %1,%0,%3\n" \
358+ " stdcx. %1,%y2\n" \
359 " bne- 1b" \
360- : "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \
361- : "b" (mem), "r" (value), "m" (*mem) \
362+ : "=&b" (__val), "=&r" (__tmp), "+Z" (*(mem)) \
363+ : "r" (value) \
364 : "cr0", "memory"); \
365 __val; \
366 })
367@@ -187,12 +187,12 @@
368 #define __arch_atomic_increment_val_64(mem) \
369 ({ \
370 __typeof (*(mem)) __val; \
371- __asm __volatile ("1: ldarx %0,0,%2\n" \
372+ __asm __volatile ("1: ldarx %0,%y1\n" \
373 " addi %0,%0,1\n" \
374- " stdcx. %0,0,%2\n" \
375+ " stdcx. %0,%y1\n" \
376 " bne- 1b" \
377- : "=&b" (__val), "=m" (*mem) \
378- : "b" (mem), "m" (*mem) \
379+ : "=&b" (__val), "+Z" (*(mem)) \
380+ : \
381 : "cr0", "memory"); \
382 __val; \
383 })
384@@ -200,27 +200,27 @@
385 #define __arch_atomic_decrement_val_64(mem) \
386 ({ \
387 __typeof (*(mem)) __val; \
388- __asm __volatile ("1: ldarx %0,0,%2\n" \
389+ __asm __volatile ("1: ldarx %0,%y1\n" \
390 " subi %0,%0,1\n" \
391- " stdcx. %0,0,%2\n" \
392+ " stdcx. %0,%y1\n" \
393 " bne- 1b" \
394- : "=&b" (__val), "=m" (*mem) \
395- : "b" (mem), "m" (*mem) \
396+ : "=&b" (__val), "+Z" (*(mem)) \
397+ : \
398 : "cr0", "memory"); \
399 __val; \
400 })
401
402 #define __arch_atomic_decrement_if_positive_64(mem) \
403 ({ int __val, __tmp; \
404- __asm __volatile ("1: ldarx %0,0,%3\n" \
405+ __asm __volatile ("1: ldarx %0,%y2\n" \
406 " cmpdi 0,%0,0\n" \
407 " addi %1,%0,-1\n" \
408 " ble 2f\n" \
409- " stdcx. %1,0,%3\n" \
410+ " stdcx. %1,%y2\n" \
411 " bne- 1b\n" \
412 "2: " __ARCH_ACQ_INSTR \
413- : "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \
414- : "b" (mem), "m" (*mem) \
415+ : "=&b" (__val), "=&r" (__tmp), "+Z" (*(mem)) \
416+ : \
417 : "cr0", "memory"); \
418 __val; \
419 })
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