source:
patches/linux-2.6.17.6-mips-1.patch@
448817bb
| Last change on this file since 448817bb was d75f6d0, checked in by , 18 years ago | |
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| File size: 124.9 KB | |
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arch/mips/cobalt/console.c
Submitted By: Jim Gifford (patches at jg555 dot com) Date: 2006-07-08 Initial Package Version: 2.6.17.4 Origin: Linux-MIPS Upstream Status: http://www.linux-mips.org/pub/linux/mips/kernel/v2.6/ Description: Merges Linux-MIPS and Kernel.org Tree's diff -Naur linux-2.6.17.4-kernel/arch/mips/cobalt/console.c linux-2.6.17.4-mips/arch/mips/cobalt/console.c
old new 41 41 42 42 printk("Cobalt: early console registered\n"); 43 43 } 44 45 void __init disable_early_printk(void) 46 { 47 unregister_console(&cons_info); 48 } -
arch/mips/configs/atlas_defconfig
diff -Naur linux-2.6.17.4-kernel/arch/mips/configs/atlas_defconfig linux-2.6.17.4-mips/arch/mips/configs/atlas_defconfig
old new 67 67 CONFIG_GENERIC_FIND_NEXT_BIT=y 68 68 CONFIG_GENERIC_HWEIGHT=y 69 69 CONFIG_GENERIC_CALIBRATE_DELAY=y 70 CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 70 71 CONFIG_DMA_NONCOHERENT=y 71 72 CONFIG_DMA_NEED_PCI_MAP_STATE=y 72 73 CONFIG_MIPS_BONITO64=y -
arch/mips/configs/bigsur_defconfig
diff -Naur linux-2.6.17.4-kernel/arch/mips/configs/bigsur_defconfig linux-2.6.17.4-mips/arch/mips/configs/bigsur_defconfig
old new 83 83 CONFIG_GENERIC_FIND_NEXT_BIT=y 84 84 CONFIG_GENERIC_HWEIGHT=y 85 85 CONFIG_GENERIC_CALIBRATE_DELAY=y 86 CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 86 87 CONFIG_DMA_COHERENT=y 87 88 CONFIG_CPU_BIG_ENDIAN=y 88 89 # CONFIG_CPU_LITTLE_ENDIAN is not set -
arch/mips/configs/capcella_defconfig
diff -Naur linux-2.6.17.4-kernel/arch/mips/configs/capcella_defconfig linux-2.6.17.4-mips/arch/mips/configs/capcella_defconfig
old new 75 75 CONFIG_GENERIC_FIND_NEXT_BIT=y 76 76 CONFIG_GENERIC_HWEIGHT=y 77 77 CONFIG_GENERIC_CALIBRATE_DELAY=y 78 CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 78 79 CONFIG_DMA_NONCOHERENT=y 79 80 CONFIG_DMA_NEED_PCI_MAP_STATE=y 80 81 # CONFIG_CPU_BIG_ENDIAN is not set -
arch/mips/configs/cobalt_defconfig
diff -Naur linux-2.6.17.4-kernel/arch/mips/configs/cobalt_defconfig linux-2.6.17.4-mips/arch/mips/configs/cobalt_defconfig
old new 68 68 CONFIG_GENERIC_FIND_NEXT_BIT=y 69 69 CONFIG_GENERIC_HWEIGHT=y 70 70 CONFIG_GENERIC_CALIBRATE_DELAY=y 71 CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 71 72 CONFIG_DMA_NONCOHERENT=y 72 73 CONFIG_DMA_NEED_PCI_MAP_STATE=y 73 74 CONFIG_I8259=y -
arch/mips/configs/db1000_defconfig
diff -Naur linux-2.6.17.4-kernel/arch/mips/configs/db1000_defconfig linux-2.6.17.4-mips/arch/mips/configs/db1000_defconfig
old new 67 67 CONFIG_GENERIC_FIND_NEXT_BIT=y 68 68 CONFIG_GENERIC_HWEIGHT=y 69 69 CONFIG_GENERIC_CALIBRATE_DELAY=y 70 CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 70 71 CONFIG_DMA_NONCOHERENT=y 71 72 CONFIG_DMA_NEED_PCI_MAP_STATE=y 72 73 # CONFIG_CPU_BIG_ENDIAN is not set -
arch/mips/configs/db1100_defconfig
diff -Naur linux-2.6.17.4-kernel/arch/mips/configs/db1100_defconfig linux-2.6.17.4-mips/arch/mips/configs/db1100_defconfig
old new 67 67 CONFIG_GENERIC_FIND_NEXT_BIT=y 68 68 CONFIG_GENERIC_HWEIGHT=y 69 69 CONFIG_GENERIC_CALIBRATE_DELAY=y 70 CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 70 71 CONFIG_DMA_NONCOHERENT=y 71 72 CONFIG_DMA_NEED_PCI_MAP_STATE=y 72 73 # CONFIG_CPU_BIG_ENDIAN is not set -
arch/mips/configs/db1200_defconfig
diff -Naur linux-2.6.17.4-kernel/arch/mips/configs/db1200_defconfig linux-2.6.17.4-mips/arch/mips/configs/db1200_defconfig
old new 67 67 CONFIG_GENERIC_FIND_NEXT_BIT=y 68 68 CONFIG_GENERIC_HWEIGHT=y 69 69 CONFIG_GENERIC_CALIBRATE_DELAY=y 70 CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 70 71 CONFIG_DMA_COHERENT=y 71 72 CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y 72 73 # CONFIG_CPU_BIG_ENDIAN is not set -
arch/mips/configs/db1500_defconfig
diff -Naur linux-2.6.17.4-kernel/arch/mips/configs/db1500_defconfig linux-2.6.17.4-mips/arch/mips/configs/db1500_defconfig
old new 67 67 CONFIG_GENERIC_FIND_NEXT_BIT=y 68 68 CONFIG_GENERIC_HWEIGHT=y 69 69 CONFIG_GENERIC_CALIBRATE_DELAY=y 70 CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 70 71 CONFIG_DMA_NONCOHERENT=y 71 72 CONFIG_DMA_NEED_PCI_MAP_STATE=y 72 73 CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y -
arch/mips/configs/db1550_defconfig
diff -Naur linux-2.6.17.4-kernel/arch/mips/configs/db1550_defconfig linux-2.6.17.4-mips/arch/mips/configs/db1550_defconfig
old new 67 67 CONFIG_GENERIC_FIND_NEXT_BIT=y 68 68 CONFIG_GENERIC_HWEIGHT=y 69 69 CONFIG_GENERIC_CALIBRATE_DELAY=y 70 CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 70 71 CONFIG_DMA_NONCOHERENT=y 71 72 CONFIG_DMA_NEED_PCI_MAP_STATE=y 72 73 CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y -
arch/mips/configs/ddb5476_defconfig
diff -Naur linux-2.6.17.4-kernel/arch/mips/configs/ddb5476_defconfig linux-2.6.17.4-mips/arch/mips/configs/ddb5476_defconfig
old new 67 67 CONFIG_GENERIC_FIND_NEXT_BIT=y 68 68 CONFIG_GENERIC_HWEIGHT=y 69 69 CONFIG_GENERIC_CALIBRATE_DELAY=y 70 CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 70 71 CONFIG_DMA_NONCOHERENT=y 71 72 CONFIG_DMA_NEED_PCI_MAP_STATE=y 72 73 CONFIG_I8259=y -
arch/mips/configs/ddb5477_defconfig
diff -Naur linux-2.6.17.4-kernel/arch/mips/configs/ddb5477_defconfig linux-2.6.17.4-mips/arch/mips/configs/ddb5477_defconfig
old new 68 68 CONFIG_GENERIC_FIND_NEXT_BIT=y 69 69 CONFIG_GENERIC_HWEIGHT=y 70 70 CONFIG_GENERIC_CALIBRATE_DELAY=y 71 CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 71 72 CONFIG_DMA_NONCOHERENT=y 72 73 CONFIG_DMA_NEED_PCI_MAP_STATE=y 73 74 CONFIG_I8259=y -
arch/mips/configs/decstation_defconfig
diff -Naur linux-2.6.17.4-kernel/arch/mips/configs/decstation_defconfig linux-2.6.17.4-mips/arch/mips/configs/decstation_defconfig
old new 68 68 CONFIG_GENERIC_FIND_NEXT_BIT=y 69 69 CONFIG_GENERIC_HWEIGHT=y 70 70 CONFIG_GENERIC_CALIBRATE_DELAY=y 71 CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 71 72 CONFIG_DMA_NONCOHERENT=y 72 73 CONFIG_DMA_NEED_PCI_MAP_STATE=y 73 74 # CONFIG_CPU_BIG_ENDIAN is not set -
arch/mips/configs/e55_defconfig
diff -Naur linux-2.6.17.4-kernel/arch/mips/configs/e55_defconfig linux-2.6.17.4-mips/arch/mips/configs/e55_defconfig
old new 73 73 CONFIG_GENERIC_FIND_NEXT_BIT=y 74 74 CONFIG_GENERIC_HWEIGHT=y 75 75 CONFIG_GENERIC_CALIBRATE_DELAY=y 76 CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 76 77 CONFIG_DMA_NONCOHERENT=y 77 78 CONFIG_DMA_NEED_PCI_MAP_STATE=y 78 79 # CONFIG_CPU_BIG_ENDIAN is not set -
arch/mips/configs/ev64120_defconfig
diff -Naur linux-2.6.17.4-kernel/arch/mips/configs/ev64120_defconfig linux-2.6.17.4-mips/arch/mips/configs/ev64120_defconfig
old new 68 68 CONFIG_GENERIC_FIND_NEXT_BIT=y 69 69 CONFIG_GENERIC_HWEIGHT=y 70 70 CONFIG_GENERIC_CALIBRATE_DELAY=y 71 CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 71 72 CONFIG_DMA_NONCOHERENT=y 72 73 CONFIG_DMA_NEED_PCI_MAP_STATE=y 73 74 CONFIG_CPU_BIG_ENDIAN=y -
arch/mips/configs/ev96100_defconfig
diff -Naur linux-2.6.17.4-kernel/arch/mips/configs/ev96100_defconfig linux-2.6.17.4-mips/arch/mips/configs/ev96100_defconfig
old new 67 67 CONFIG_GENERIC_FIND_NEXT_BIT=y 68 68 CONFIG_GENERIC_HWEIGHT=y 69 69 CONFIG_GENERIC_CALIBRATE_DELAY=y 70 CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 70 71 CONFIG_DMA_NONCOHERENT=y 71 72 CONFIG_DMA_NEED_PCI_MAP_STATE=y 72 73 CONFIG_CPU_BIG_ENDIAN=y -
arch/mips/configs/ip22_defconfig
diff -Naur linux-2.6.17.4-kernel/arch/mips/configs/ip22_defconfig linux-2.6.17.4-mips/arch/mips/configs/ip22_defconfig
old new 67 67 CONFIG_GENERIC_FIND_NEXT_BIT=y 68 68 CONFIG_GENERIC_HWEIGHT=y 69 69 CONFIG_GENERIC_CALIBRATE_DELAY=y 70 CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 70 71 CONFIG_ARC=y 71 72 CONFIG_DMA_NONCOHERENT=y 72 73 CONFIG_DMA_NEED_PCI_MAP_STATE=y -
arch/mips/configs/ip27_defconfig
diff -Naur linux-2.6.17.4-kernel/arch/mips/configs/ip27_defconfig linux-2.6.17.4-mips/arch/mips/configs/ip27_defconfig
old new 73 73 CONFIG_GENERIC_FIND_NEXT_BIT=y 74 74 CONFIG_GENERIC_HWEIGHT=y 75 75 CONFIG_GENERIC_CALIBRATE_DELAY=y 76 CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 76 77 CONFIG_ARC=y 77 78 CONFIG_DMA_IP27=y 78 79 CONFIG_CPU_BIG_ENDIAN=y -
arch/mips/configs/ip32_defconfig
diff -Naur linux-2.6.17.4-kernel/arch/mips/configs/ip32_defconfig linux-2.6.17.4-mips/arch/mips/configs/ip32_defconfig
old new 67 67 CONFIG_GENERIC_FIND_NEXT_BIT=y 68 68 CONFIG_GENERIC_HWEIGHT=y 69 69 CONFIG_GENERIC_CALIBRATE_DELAY=y 70 CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 70 71 CONFIG_ARC=y 71 72 CONFIG_DMA_IP32=y 72 73 CONFIG_DMA_NONCOHERENT=y -
arch/mips/configs/it8172_defconfig
diff -Naur linux-2.6.17.4-kernel/arch/mips/configs/it8172_defconfig linux-2.6.17.4-mips/arch/mips/configs/it8172_defconfig
old new 68 68 CONFIG_GENERIC_FIND_NEXT_BIT=y 69 69 CONFIG_GENERIC_HWEIGHT=y 70 70 CONFIG_GENERIC_CALIBRATE_DELAY=y 71 CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 71 72 CONFIG_DMA_NONCOHERENT=y 72 73 CONFIG_DMA_NEED_PCI_MAP_STATE=y 73 74 # CONFIG_CPU_BIG_ENDIAN is not set -
arch/mips/configs/ivr_defconfig
diff -Naur linux-2.6.17.4-kernel/arch/mips/configs/ivr_defconfig linux-2.6.17.4-mips/arch/mips/configs/ivr_defconfig
old new 67 67 CONFIG_GENERIC_FIND_NEXT_BIT=y 68 68 CONFIG_GENERIC_HWEIGHT=y 69 69 CONFIG_GENERIC_CALIBRATE_DELAY=y 70 CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 70 71 CONFIG_DMA_NONCOHERENT=y 71 72 CONFIG_DMA_NEED_PCI_MAP_STATE=y 72 73 # CONFIG_CPU_BIG_ENDIAN is not set -
arch/mips/configs/jaguar-atx_defconfig
diff -Naur linux-2.6.17.4-kernel/arch/mips/configs/jaguar-atx_defconfig linux-2.6.17.4-mips/arch/mips/configs/jaguar-atx_defconfig
old new 68 68 CONFIG_GENERIC_FIND_NEXT_BIT=y 69 69 CONFIG_GENERIC_HWEIGHT=y 70 70 CONFIG_GENERIC_CALIBRATE_DELAY=y 71 CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 71 72 CONFIG_DMA_NONCOHERENT=y 72 73 CONFIG_DMA_NEED_PCI_MAP_STATE=y 73 74 CONFIG_LIMITED_DMA=y -
arch/mips/configs/jmr3927_defconfig
diff -Naur linux-2.6.17.4-kernel/arch/mips/configs/jmr3927_defconfig linux-2.6.17.4-mips/arch/mips/configs/jmr3927_defconfig
old new 67 67 CONFIG_GENERIC_FIND_NEXT_BIT=y 68 68 CONFIG_GENERIC_HWEIGHT=y 69 69 CONFIG_GENERIC_CALIBRATE_DELAY=y 70 CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 70 71 CONFIG_DMA_NONCOHERENT=y 71 72 CONFIG_DMA_NEED_PCI_MAP_STATE=y 72 73 CONFIG_CPU_BIG_ENDIAN=y -
arch/mips/configs/lasat200_defconfig
diff -Naur linux-2.6.17.4-kernel/arch/mips/configs/lasat200_defconfig linux-2.6.17.4-mips/arch/mips/configs/lasat200_defconfig
old new 71 71 CONFIG_GENERIC_FIND_NEXT_BIT=y 72 72 CONFIG_GENERIC_HWEIGHT=y 73 73 CONFIG_GENERIC_CALIBRATE_DELAY=y 74 CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 74 75 CONFIG_DMA_NONCOHERENT=y 75 76 CONFIG_DMA_NEED_PCI_MAP_STATE=y 76 77 CONFIG_MIPS_NILE4=y -
arch/mips/configs/malta_defconfig
diff -Naur linux-2.6.17.4-kernel/arch/mips/configs/malta_defconfig linux-2.6.17.4-mips/arch/mips/configs/malta_defconfig
old new 67 67 CONFIG_GENERIC_FIND_NEXT_BIT=y 68 68 CONFIG_GENERIC_HWEIGHT=y 69 69 CONFIG_GENERIC_CALIBRATE_DELAY=y 70 CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 70 71 CONFIG_ARCH_MAY_HAVE_PC_FDC=y 71 72 CONFIG_DMA_NONCOHERENT=y 72 73 CONFIG_DMA_NEED_PCI_MAP_STATE=y -
arch/mips/configs/mipssim_defconfig
diff -Naur linux-2.6.17.4-kernel/arch/mips/configs/mipssim_defconfig linux-2.6.17.4-mips/arch/mips/configs/mipssim_defconfig
old new 67 67 CONFIG_GENERIC_FIND_NEXT_BIT=y 68 68 CONFIG_GENERIC_HWEIGHT=y 69 69 CONFIG_GENERIC_CALIBRATE_DELAY=y 70 CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 70 71 CONFIG_DMA_NONCOHERENT=y 71 72 CONFIG_DMA_NEED_PCI_MAP_STATE=y 72 73 # CONFIG_CPU_BIG_ENDIAN is not set -
arch/mips/configs/mpc30x_defconfig
diff -Naur linux-2.6.17.4-kernel/arch/mips/configs/mpc30x_defconfig linux-2.6.17.4-mips/arch/mips/configs/mpc30x_defconfig
old new 75 75 CONFIG_GENERIC_FIND_NEXT_BIT=y 76 76 CONFIG_GENERIC_HWEIGHT=y 77 77 CONFIG_GENERIC_CALIBRATE_DELAY=y 78 CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 78 79 CONFIG_DMA_NONCOHERENT=y 79 80 CONFIG_DMA_NEED_PCI_MAP_STATE=y 80 81 # CONFIG_CPU_BIG_ENDIAN is not set -
arch/mips/configs/ocelot_3_defconfig
diff -Naur linux-2.6.17.4-kernel/arch/mips/configs/ocelot_3_defconfig linux-2.6.17.4-mips/arch/mips/configs/ocelot_3_defconfig
old new 67 67 CONFIG_GENERIC_FIND_NEXT_BIT=y 68 68 CONFIG_GENERIC_HWEIGHT=y 69 69 CONFIG_GENERIC_CALIBRATE_DELAY=y 70 CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 70 71 CONFIG_DMA_NONCOHERENT=y 71 72 CONFIG_DMA_NEED_PCI_MAP_STATE=y 72 73 CONFIG_CPU_BIG_ENDIAN=y -
arch/mips/configs/ocelot_c_defconfig
diff -Naur linux-2.6.17.4-kernel/arch/mips/configs/ocelot_c_defconfig linux-2.6.17.4-mips/arch/mips/configs/ocelot_c_defconfig
old new 67 67 CONFIG_GENERIC_FIND_NEXT_BIT=y 68 68 CONFIG_GENERIC_HWEIGHT=y 69 69 CONFIG_GENERIC_CALIBRATE_DELAY=y 70 CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 70 71 CONFIG_DMA_NONCOHERENT=y 71 72 CONFIG_DMA_NEED_PCI_MAP_STATE=y 72 73 CONFIG_CPU_BIG_ENDIAN=y -
arch/mips/configs/ocelot_defconfig
diff -Naur linux-2.6.17.4-kernel/arch/mips/configs/ocelot_defconfig linux-2.6.17.4-mips/arch/mips/configs/ocelot_defconfig
old new 67 67 CONFIG_GENERIC_FIND_NEXT_BIT=y 68 68 CONFIG_GENERIC_HWEIGHT=y 69 69 CONFIG_GENERIC_CALIBRATE_DELAY=y 70 CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 70 71 CONFIG_DMA_NONCOHERENT=y 71 72 CONFIG_DMA_NEED_PCI_MAP_STATE=y 72 73 CONFIG_CPU_BIG_ENDIAN=y -
arch/mips/configs/ocelot_g_defconfig
diff -Naur linux-2.6.17.4-kernel/arch/mips/configs/ocelot_g_defconfig linux-2.6.17.4-mips/arch/mips/configs/ocelot_g_defconfig
old new 67 67 CONFIG_GENERIC_FIND_NEXT_BIT=y 68 68 CONFIG_GENERIC_HWEIGHT=y 69 69 CONFIG_GENERIC_CALIBRATE_DELAY=y 70 CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 70 71 CONFIG_DMA_NONCOHERENT=y 71 72 CONFIG_DMA_NEED_PCI_MAP_STATE=y 72 73 CONFIG_CPU_BIG_ENDIAN=y -
arch/mips/configs/pb1100_defconfig
diff -Naur linux-2.6.17.4-kernel/arch/mips/configs/pb1100_defconfig linux-2.6.17.4-mips/arch/mips/configs/pb1100_defconfig
old new 67 67 CONFIG_GENERIC_FIND_NEXT_BIT=y 68 68 CONFIG_GENERIC_HWEIGHT=y 69 69 CONFIG_GENERIC_CALIBRATE_DELAY=y 70 CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 70 71 CONFIG_DMA_NONCOHERENT=y 71 72 CONFIG_DMA_NEED_PCI_MAP_STATE=y 72 73 # CONFIG_CPU_BIG_ENDIAN is not set -
arch/mips/configs/pb1500_defconfig
diff -Naur linux-2.6.17.4-kernel/arch/mips/configs/pb1500_defconfig linux-2.6.17.4-mips/arch/mips/configs/pb1500_defconfig
old new 67 67 CONFIG_GENERIC_FIND_NEXT_BIT=y 68 68 CONFIG_GENERIC_HWEIGHT=y 69 69 CONFIG_GENERIC_CALIBRATE_DELAY=y 70 CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 70 71 CONFIG_DMA_NONCOHERENT=y 71 72 CONFIG_DMA_NEED_PCI_MAP_STATE=y 72 73 # CONFIG_CPU_BIG_ENDIAN is not set -
arch/mips/configs/pb1550_defconfig
diff -Naur linux-2.6.17.4-kernel/arch/mips/configs/pb1550_defconfig linux-2.6.17.4-mips/arch/mips/configs/pb1550_defconfig
old new 67 67 CONFIG_GENERIC_FIND_NEXT_BIT=y 68 68 CONFIG_GENERIC_HWEIGHT=y 69 69 CONFIG_GENERIC_CALIBRATE_DELAY=y 70 CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 70 71 CONFIG_DMA_NONCOHERENT=y 71 72 CONFIG_DMA_NEED_PCI_MAP_STATE=y 72 73 CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y -
arch/mips/configs/pnx8550-jbs_defconfig
diff -Naur linux-2.6.17.4-kernel/arch/mips/configs/pnx8550-jbs_defconfig linux-2.6.17.4-mips/arch/mips/configs/pnx8550-jbs_defconfig
old new 67 67 CONFIG_GENERIC_FIND_NEXT_BIT=y 68 68 CONFIG_GENERIC_HWEIGHT=y 69 69 CONFIG_GENERIC_CALIBRATE_DELAY=y 70 CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 70 71 CONFIG_DMA_NONCOHERENT=y 71 72 CONFIG_DMA_NEED_PCI_MAP_STATE=y 72 73 # CONFIG_CPU_BIG_ENDIAN is not set -
arch/mips/configs/pnx8550-v2pci_defconfig
diff -Naur linux-2.6.17.4-kernel/arch/mips/configs/pnx8550-v2pci_defconfig linux-2.6.17.4-mips/arch/mips/configs/pnx8550-v2pci_defconfig
old new 67 67 CONFIG_GENERIC_FIND_NEXT_BIT=y 68 68 CONFIG_GENERIC_HWEIGHT=y 69 69 CONFIG_GENERIC_CALIBRATE_DELAY=y 70 CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 70 71 CONFIG_DMA_NONCOHERENT=y 71 72 CONFIG_DMA_NEED_PCI_MAP_STATE=y 72 73 # CONFIG_CPU_BIG_ENDIAN is not set -
arch/mips/configs/qemu_defconfig
diff -Naur linux-2.6.17.4-kernel/arch/mips/configs/qemu_defconfig linux-2.6.17.4-mips/arch/mips/configs/qemu_defconfig
old new 67 67 CONFIG_GENERIC_FIND_NEXT_BIT=y 68 68 CONFIG_GENERIC_HWEIGHT=y 69 69 CONFIG_GENERIC_CALIBRATE_DELAY=y 70 CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 70 71 CONFIG_DMA_COHERENT=y 71 72 CONFIG_GENERIC_ISA_DMA=y 72 73 CONFIG_I8259=y -
arch/mips/configs/rbhma4500_defconfig
diff -Naur linux-2.6.17.4-kernel/arch/mips/configs/rbhma4500_defconfig linux-2.6.17.4-mips/arch/mips/configs/rbhma4500_defconfig
old new 74 74 CONFIG_GENERIC_FIND_NEXT_BIT=y 75 75 CONFIG_GENERIC_HWEIGHT=y 76 76 CONFIG_GENERIC_CALIBRATE_DELAY=y 77 CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 77 78 CONFIG_DMA_NONCOHERENT=y 78 79 CONFIG_DMA_NEED_PCI_MAP_STATE=y 79 80 CONFIG_GENERIC_ISA_DMA=y -
arch/mips/configs/rm200_defconfig
diff -Naur linux-2.6.17.4-kernel/arch/mips/configs/rm200_defconfig linux-2.6.17.4-mips/arch/mips/configs/rm200_defconfig
old new 67 67 CONFIG_GENERIC_FIND_NEXT_BIT=y 68 68 CONFIG_GENERIC_HWEIGHT=y 69 69 CONFIG_GENERIC_CALIBRATE_DELAY=y 70 CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 70 71 CONFIG_ARC=y 71 72 CONFIG_ARCH_MAY_HAVE_PC_FDC=y 72 73 CONFIG_DMA_NONCOHERENT=y -
arch/mips/configs/sb1250-swarm_defconfig
diff -Naur linux-2.6.17.4-kernel/arch/mips/configs/sb1250-swarm_defconfig linux-2.6.17.4-mips/arch/mips/configs/sb1250-swarm_defconfig
old new 84 84 CONFIG_GENERIC_FIND_NEXT_BIT=y 85 85 CONFIG_GENERIC_HWEIGHT=y 86 86 CONFIG_GENERIC_CALIBRATE_DELAY=y 87 CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 87 88 CONFIG_DMA_COHERENT=y 88 89 CONFIG_CPU_BIG_ENDIAN=y 89 90 # CONFIG_CPU_LITTLE_ENDIAN is not set -
arch/mips/configs/sead_defconfig
diff -Naur linux-2.6.17.4-kernel/arch/mips/configs/sead_defconfig linux-2.6.17.4-mips/arch/mips/configs/sead_defconfig
old new 67 67 CONFIG_GENERIC_FIND_NEXT_BIT=y 68 68 CONFIG_GENERIC_HWEIGHT=y 69 69 CONFIG_GENERIC_CALIBRATE_DELAY=y 70 CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 70 71 CONFIG_DMA_NONCOHERENT=y 71 72 CONFIG_DMA_NEED_PCI_MAP_STATE=y 72 73 # CONFIG_CPU_BIG_ENDIAN is not set -
arch/mips/configs/tb0226_defconfig
diff -Naur linux-2.6.17.4-kernel/arch/mips/configs/tb0226_defconfig linux-2.6.17.4-mips/arch/mips/configs/tb0226_defconfig
old new 77 77 CONFIG_GENERIC_FIND_NEXT_BIT=y 78 78 CONFIG_GENERIC_HWEIGHT=y 79 79 CONFIG_GENERIC_CALIBRATE_DELAY=y 80 CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 80 81 CONFIG_DMA_NONCOHERENT=y 81 82 CONFIG_DMA_NEED_PCI_MAP_STATE=y 82 83 # CONFIG_CPU_BIG_ENDIAN is not set -
arch/mips/configs/tb0229_defconfig
diff -Naur linux-2.6.17.4-kernel/arch/mips/configs/tb0229_defconfig linux-2.6.17.4-mips/arch/mips/configs/tb0229_defconfig
old new 77 77 CONFIG_GENERIC_FIND_NEXT_BIT=y 78 78 CONFIG_GENERIC_HWEIGHT=y 79 79 CONFIG_GENERIC_CALIBRATE_DELAY=y 80 CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 80 81 CONFIG_DMA_NONCOHERENT=y 81 82 CONFIG_DMA_NEED_PCI_MAP_STATE=y 82 83 # CONFIG_CPU_BIG_ENDIAN is not set -
arch/mips/configs/workpad_defconfig
diff -Naur linux-2.6.17.4-kernel/arch/mips/configs/workpad_defconfig linux-2.6.17.4-mips/arch/mips/configs/workpad_defconfig
old new 73 73 CONFIG_GENERIC_FIND_NEXT_BIT=y 74 74 CONFIG_GENERIC_HWEIGHT=y 75 75 CONFIG_GENERIC_CALIBRATE_DELAY=y 76 CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 76 77 CONFIG_DMA_NONCOHERENT=y 77 78 CONFIG_DMA_NEED_PCI_MAP_STATE=y 78 79 # CONFIG_CPU_BIG_ENDIAN is not set -
arch/mips/configs/yosemite_defconfig
diff -Naur linux-2.6.17.4-kernel/arch/mips/configs/yosemite_defconfig linux-2.6.17.4-mips/arch/mips/configs/yosemite_defconfig
old new 68 68 CONFIG_GENERIC_FIND_NEXT_BIT=y 69 69 CONFIG_GENERIC_HWEIGHT=y 70 70 CONFIG_GENERIC_CALIBRATE_DELAY=y 71 CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 71 72 CONFIG_DMA_COHERENT=y 72 73 CONFIG_CPU_BIG_ENDIAN=y 73 74 # CONFIG_CPU_LITTLE_ENDIAN is not set -
arch/mips/defconfig
diff -Naur linux-2.6.17.4-kernel/arch/mips/defconfig linux-2.6.17.4-mips/arch/mips/defconfig
old new 67 67 CONFIG_GENERIC_FIND_NEXT_BIT=y 68 68 CONFIG_GENERIC_HWEIGHT=y 69 69 CONFIG_GENERIC_CALIBRATE_DELAY=y 70 CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 70 71 CONFIG_ARC=y 71 72 CONFIG_DMA_NONCOHERENT=y 72 73 CONFIG_DMA_NEED_PCI_MAP_STATE=y -
arch/mips/Kconfig
diff -Naur linux-2.6.17.4-kernel/arch/mips/Kconfig linux-2.6.17.4-mips/arch/mips/Kconfig
old new 278 278 select SYS_SUPPORTS_64BIT_KERNEL 279 279 select SYS_SUPPORTS_BIG_ENDIAN 280 280 select SYS_SUPPORTS_LITTLE_ENDIAN 281 select SYS_SUPPORTS_MULTITHREADING if EXPERIMENTAL 281 282 help 282 283 This enables support for the MIPS Technologies Atlas evaluation 283 284 board. … … 294 295 select I8259 295 296 select MIPS_BOARDS_GEN 296 297 select MIPS_BONITO64 298 select MIPS_CPU_SCACHE 297 299 select MIPS_GT64120 298 300 select MIPS_MSC 299 301 select SWAP_IO_SPACE … … 306 308 select SYS_SUPPORTS_64BIT_KERNEL 307 309 select SYS_SUPPORTS_BIG_ENDIAN 308 310 select SYS_SUPPORTS_LITTLE_ENDIAN 311 select SYS_SUPPORTS_MULTITHREADING 309 312 help 310 313 This enables support for the MIPS Technologies Malta evaluation 311 314 board. … … 438 441 439 442 config PNX8550_V2PCI 440 443 bool "Philips PNX8550 based Viper2-PCI board" 444 depends on BROKEN 441 445 select PNX8550 442 446 select SYS_SUPPORTS_LITTLE_ENDIAN 443 447 444 448 config PNX8550_JBS 445 449 bool "Philips PNX8550 based JBS board" 450 depends on BROKEN 446 451 select PNX8550 447 452 select SYS_SUPPORTS_LITTLE_ENDIAN 448 453 … … 506 511 config MACH_VR41XX 507 512 bool "NEC VR41XX-based machines" 508 513 select SYS_HAS_CPU_VR41XX 509 select SYS_SUPPORTS_32BIT_KERNEL510 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL511 514 512 515 config PMC_YOSEMITE 513 516 bool "PMC-Sierra Yosemite eval board" … … 522 525 select SYS_SUPPORTS_64BIT_KERNEL 523 526 select SYS_SUPPORTS_BIG_ENDIAN 524 527 select SYS_SUPPORTS_HIGHMEM 528 select SYS_SUPPORTS_SMP 525 529 help 526 530 Yosemite is an evaluation board for the RM9000x2 processor 527 531 manufactured by PMC-Sierra. … … 555 559 select HW_HAS_EISA 556 560 select IP22_CPU_SCACHE 557 561 select IRQ_CPU 562 select NO_ISA if ISA 558 563 select SWAP_IO_SPACE 559 564 select SYS_HAS_CPU_R4X00 560 565 select SYS_HAS_CPU_R5000 … … 577 582 select SYS_HAS_CPU_R10000 578 583 select SYS_SUPPORTS_64BIT_KERNEL 579 584 select SYS_SUPPORTS_BIG_ENDIAN 585 select SYS_SUPPORTS_SMP 580 586 help 581 587 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics 582 588 workstations. To compile a Linux kernel that runs on these, say Y … … 1035 1041 config HAVE_STD_PC_SERIAL_PORT 1036 1042 bool 1037 1043 1044 config VR4181 1045 bool 1046 1038 1047 config ARC_CONSOLE 1039 1048 bool "ARC console support" 1040 1049 depends on SGI_IP22 || SNI_RM200_PCI … … 1155 1164 select CPU_SUPPORTS_32BIT_KERNEL 1156 1165 select CPU_SUPPORTS_64BIT_KERNEL 1157 1166 help 1158 The options selects support for the NEC VR41 00series of processors.1167 The options selects support for the NEC VR41xx series of processors. 1159 1168 Only choose this option if you have one of these processors as a 1160 1169 kernel built with this option will not run on any other type of 1161 1170 processor or vice versa. … … 1211 1220 select CPU_SUPPORTS_32BIT_KERNEL 1212 1221 help 1213 1222 MIPS Technologies R6000 and R6000A series processors. Note these 1214 processors are extrem ly rare and the support for them is incomplete.1223 processors are extremely rare and the support for them is incomplete. 1215 1224 1216 1225 config CPU_NEVADA 1217 1226 bool "RM52xx" … … 1332 1341 endmenu 1333 1342 1334 1343 # 1335 # These two indicate any level of the MIPS32 and MIPS64 architecture1344 # These two indicate any level of the MIPS32 and MIPS64 architecture 1336 1345 # 1337 1346 config CPU_MIPS32 1338 1347 bool … … 1343 1352 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 1344 1353 1345 1354 # 1346 # These two indicate the revision of the architecture, either 32 bot 64 bit.1355 # These two indicate the revision of the architecture, either Release 1 or Release 2 1347 1356 # 1348 1357 config CPU_MIPSR1 1349 1358 bool … … 1436 1445 bool 1437 1446 select BOARD_SCACHE 1438 1447 1448 # 1449 # Support for a MIPS32 / MIPS64 style S-caches 1450 # 1451 config MIPS_CPU_SCACHE 1452 bool 1453 select BOARD_SCACHE 1454 1439 1455 config R5000_CPU_SCACHE 1440 1456 bool 1441 1457 select BOARD_SCACHE … … 1455 1471 config CPU_HAS_PREFETCH 1456 1472 bool 1457 1473 1458 config MIPS_MT1459 bool "Enable MIPS MT"1460 1461 1474 choice 1462 1475 prompt "MIPS MT options" 1463 depends on MIPS_MT 1476 1477 config MIPS_MT_DISABLED 1478 bool "Disable multithreading support." 1479 help 1480 Use this option if your workload can't take advantage of 1481 MIPS hardware multithreading support. On systems that don't have 1482 the option of an MT-enabled processor this option will be the only 1483 option in this menu. 1464 1484 1465 1485 config MIPS_MT_SMTC 1466 1486 bool "SMTC: Use all TCs on all VPEs for SMP" 1487 depends on CPU_MIPS32_R2 1488 #depends on CPU_MIPS64_R2 # once there is hardware ... 1489 depends on SYS_SUPPORTS_MULTITHREADING 1467 1490 select CPU_MIPSR2_IRQ_VI 1468 1491 select CPU_MIPSR2_SRS 1492 select MIPS_MT 1469 1493 select SMP 1494 help 1495 This is a kernel model which is known a SMTC or lately has been 1496 marketesed into SMVP. 1470 1497 1471 1498 config MIPS_MT_SMP 1472 1499 bool "Use 1 TC on each available VPE for SMP" 1500 depends on SYS_SUPPORTS_MULTITHREADING 1501 select CPU_MIPSR2_IRQ_VI 1502 select CPU_MIPSR2_SRS 1503 select MIPS_MT 1473 1504 select SMP 1505 help 1506 This is a kernel model which is also known a VSMP or lately 1507 has been marketesed into SMVP. 1474 1508 1475 1509 config MIPS_VPE_LOADER 1476 1510 bool "VPE loader support." 1477 depends on MIPS_MT 1511 depends on SYS_SUPPORTS_MULTITHREADING 1512 select MIPS_MT 1478 1513 help 1479 1514 Includes a loader for loading an elf relocatable object 1480 1515 onto another VPE and running it. 1481 1516 1482 1517 endchoice 1483 1518 1519 config MIPS_MT 1520 bool 1521 1522 config SYS_SUPPORTS_MULTITHREADING 1523 bool 1524 1484 1525 config MIPS_MT_FPAFF 1485 1526 bool "Dynamic FPU affinity for FP-intensive threads" 1486 1527 depends on MIPS_MT … … 1537 1578 config CPU_HAS_WB 1538 1579 bool 1539 1580 1581 # 1582 # Vectored interrupt mode is an R2 feature 1583 # 1540 1584 config CPU_MIPSR2_IRQ_VI 1541 bool "Vectored interrupt mode" 1542 depends on CPU_MIPSR2 1543 help 1544 Vectored interrupt mode allowing faster dispatching of interrupts. 1545 The board support code needs to be written to take advantage of this 1546 mode. Compatibility code is included to allow the kernel to run on 1547 a CPU that does not support vectored interrupts. It's safe to 1548 say Y here. 1585 bool 1549 1586 1587 # 1588 # Extended interrupt mode is an R2 feature 1589 # 1550 1590 config CPU_MIPSR2_IRQ_EI 1551 bool "External interrupt controller mode" 1552 depends on CPU_MIPSR2 1553 help 1554 Extended interrupt mode takes advantage of an external interrupt 1555 controller to allow fast dispatching from many possible interrupt 1556 sources. Say N unless you know that external interrupt support is 1557 required. 1591 bool 1558 1592 1593 # 1594 # Shadow registers are an R2 feature 1595 # 1559 1596 config CPU_MIPSR2_SRS 1560 bool "Make shadow set registers available for interrupt handlers" 1561 depends on CPU_MIPSR2_IRQ_VI || CPU_MIPSR2_IRQ_EI 1562 help 1563 Allow the kernel to use shadow register sets for fast interrupts. 1564 Interrupt handlers must be specially written to use shadow sets. 1565 Say N unless you know that shadow register set upport is needed. 1597 bool 1566 1598 1567 1599 config CPU_HAS_SYNC 1568 1600 bool … … 1616 1648 1617 1649 config SMP 1618 1650 bool "Multi-Processing support" 1619 depends on CPU_RM9000 || ((SIBYTE_BCM1x80 || SIBYTE_BCM1x55 || SIBYTE_SB1250 || QEMU) && !SIBYTE_STANDALONE) || SGI_IP27 || MIPS_MT_SMP || MIPS_MT_SMTC1620 ---help---1651 depends on SYS_SUPPORTS_SMP 1652 help 1621 1653 This enables support for systems with more than one CPU. If you have 1622 1654 a system with only one CPU, like most personal computers, say N. If 1623 1655 you have a system with more than one CPU, say Y. … … 1636 1668 1637 1669 If you don't know what to do here, say N. 1638 1670 1671 config SYS_SUPPORTS_SMP 1672 bool 1673 1639 1674 config NR_CPUS 1640 1675 int "Maximum number of CPUs (2-64)" 1641 1676 range 2 64 … … 1710 1745 config ISA 1711 1746 bool 1712 1747 1748 config NO_ISA 1749 bool 1750 1713 1751 config EISA 1714 1752 bool "EISA support" 1715 1753 depends on HW_HAS_EISA -
arch/mips/kernel/cpu-probe.c
diff -Naur linux-2.6.17.4-kernel/arch/mips/kernel/cpu-probe.c linux-2.6.17.4-mips/arch/mips/kernel/cpu-probe.c
old new 111 111 case CPU_R5000: 112 112 case CPU_NEVADA: 113 113 case CPU_RM7000: 114 case CPU_RM9000:115 114 case CPU_TX49XX: 116 115 case CPU_4KC: 117 116 case CPU_4KEC: … … 137 136 } else 138 137 printk(" unavailable.\n"); 139 138 break; 139 case CPU_RM9000: 140 if ((c->processor_id & 0x00ff) >= 0x40) { 141 cpu_wait = r4k_wait; 142 printk(" available.\n"); 143 } else { 144 printk(" unavailable.\n"); 145 } 146 break; 140 147 default: 141 148 printk(" unavailable.\n"); 142 149 break; … … 243 250 break; 244 251 case PRID_IMP_VR41XX: 245 252 switch (c->processor_id & 0xf0) { 253 #ifndef CONFIG_VR4181 246 254 case PRID_REV_VR4111: 247 255 c->cputype = CPU_VR4111; 248 256 break; 257 #else 258 case PRID_REV_VR4181: 259 c->cputype = CPU_VR4181; 260 break; 261 #endif 249 262 case PRID_REV_VR4121: 250 263 c->cputype = CPU_VR4121; 251 264 break; … … 597 610 break; 598 611 case PRID_IMP_25KF: 599 612 c->cputype = CPU_25KF; 600 /* Probe for L2 cache */601 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;602 613 break; 603 614 case PRID_IMP_34K: 604 615 c->cputype = CPU_34K; -
arch/mips/kernel/entry.S
diff -Naur linux-2.6.17.4-kernel/arch/mips/kernel/entry.S linux-2.6.17.4-mips/arch/mips/kernel/entry.S
old new 87 87 ori v1, v0, TCSTATUS_IXMT 88 88 mtc0 v1, CP0_TCSTATUS 89 89 andi v0, TCSTATUS_IXMT 90 ehb90 _ehb 91 91 mfc0 t0, CP0_TCCONTEXT 92 92 DMT 9 # dmt t1 93 93 jal mips_ihb … … 95 95 andi t3, t0, 0xff00 96 96 or t2, t2, t3 97 97 mtc0 t2, CP0_STATUS 98 ehb98 _ehb 99 99 andi t1, t1, VPECONTROL_TE 100 100 beqz t1, 1f 101 101 EMT … … 105 105 xori v1, v1, TCSTATUS_IXMT 106 106 or v1, v0, v1 107 107 mtc0 v1, CP0_TCSTATUS 108 ehb108 _ehb 109 109 xor t0, t0, t3 110 110 mtc0 t0, CP0_TCCONTEXT 111 111 #endif /* CONFIG_MIPS_MT_SMTC */ -
arch/mips/kernel/gdb-low.S
diff -Naur linux-2.6.17.4-kernel/arch/mips/kernel/gdb-low.S linux-2.6.17.4-mips/arch/mips/kernel/gdb-low.S
old new 291 291 ori t1, t2, TCSTATUS_IXMT 292 292 mtc0 t1, CP0_TCSTATUS 293 293 andi t2, t2, TCSTATUS_IXMT 294 ehb294 _ehb 295 295 DMT 9 # dmt t1 296 296 jal mips_ihb 297 297 nop … … 310 310 xori t1, t1, TCSTATUS_IXMT 311 311 or t1, t1, t2 312 312 mtc0 t1, CP0_TCSTATUS 313 ehb313 _ehb 314 314 #endif /* CONFIG_MIPS_MT_SMTC */ 315 315 LONG_L v0, GDB_FR_STATUS(sp) 316 316 LONG_L v1, GDB_FR_EPC(sp) -
arch/mips/kernel/genex.S
diff -Naur linux-2.6.17.4-kernel/arch/mips/kernel/genex.S linux-2.6.17.4-mips/arch/mips/kernel/genex.S
old new 214 214 mtc0 t0, CP0_TCCONTEXT 215 215 xor t1, t1, t0 216 216 mtc0 t1, CP0_STATUS 217 ehb217 _ehb 218 218 #endif /* CONFIG_MIPS_MT_SMTC */ 219 219 CLI 220 220 move a0, sp -
arch/mips/kernel/head.S
diff -Naur linux-2.6.17.4-kernel/arch/mips/kernel/head.S linux-2.6.17.4-mips/arch/mips/kernel/head.S
old new 96 96 /* Clear TKSU, leave IXMT */ 97 97 xori t0, 0x00001800 98 98 mtc0 t0, CP0_TCSTATUS 99 ehb99 _ehb 100 100 /* We need to leave the global IE bit set, but clear EXL...*/ 101 101 mfc0 t0, CP0_STATUS 102 102 or t0, ST0_CU0 | ST0_EXL | ST0_ERL | \set | \clr -
arch/mips/kernel/ptrace.c
diff -Naur linux-2.6.17.4-kernel/arch/mips/kernel/ptrace.c linux-2.6.17.4-mips/arch/mips/kernel/ptrace.c
old new 21 21 #include <linux/mm.h> 22 22 #include <linux/errno.h> 23 23 #include <linux/ptrace.h> 24 #include <linux/audit.h>25 24 #include <linux/smp.h> 26 25 #include <linux/smp_lock.h> 27 26 #include <linux/user.h> 28 27 #include <linux/security.h> 29 #include <linux/signal.h> 28 #include <linux/audit.h> 29 #include <linux/seccomp.h> 30 30 31 31 #include <asm/byteorder.h> 32 32 #include <asm/cpu.h> … … 482 482 */ 483 483 asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit) 484 484 { 485 /* do the secure computing check first */ 486 secure_computing(regs->orig_eax); 487 485 488 if (unlikely(current->audit_context) && entryexit) 486 489 audit_syscall_exit(AUDITSC_RESULT(regs->regs[2]), 487 490 regs->regs[2]); 488 491 489 492 if (!(current->ptrace & PT_PTRACED)) 490 493 goto out; 494 491 495 if (!test_thread_flag(TIF_SYSCALL_TRACE)) 492 496 goto out; 493 497 … … 505 509 send_sig(current->exit_code, current, 1); 506 510 current->exit_code = 0; 507 511 } 508 out: 512 513 out: 514 /* There is no ->orig_eax and that's quite intensional for now making 515 this work will require some work in various other place before it's 516 more than a placebo. */ 517 509 518 if (unlikely(current->audit_context) && !entryexit) 510 audit_syscall_entry(audit_arch(), regs-> regs[2],511 512 519 audit_syscall_entry(audit_arch(), regs->orig_eax, 520 regs->regs[4], regs->regs[5], 521 regs->regs[6], regs->regs[7]); 513 522 } -
arch/mips/kernel/r4k_switch.S
diff -Naur linux-2.6.17.4-kernel/arch/mips/kernel/r4k_switch.S linux-2.6.17.4-mips/arch/mips/kernel/r4k_switch.S
old new 75 75 and t0, t0, t1 76 76 LONG_S t0, ST_OFF(t3) 77 77 78 fpu_save_double a0 t 1 t0 t2 # c0_status passed in t179 # clobbers t 0 and t278 fpu_save_double a0 t0 t1 # c0_status passed in t0 79 # clobbers t1 80 80 1: 81 81 82 82 /* … … 94 94 ori t1, t2, TCSTATUS_IXMT 95 95 mtc0 t1, CP0_TCSTATUS 96 96 andi t2, t2, TCSTATUS_IXMT 97 ehb97 _ehb 98 98 DMT 8 # dmt t0 99 99 move t1,ra 100 100 jal mips_ihb … … 109 109 or a2, t1 110 110 mtc0 a2, CP0_STATUS 111 111 #ifdef CONFIG_MIPS_MT_SMTC 112 ehb112 _ehb 113 113 andi t0, t0, VPECONTROL_TE 114 114 beqz t0, 1f 115 115 emt … … 118 118 xori t1, t1, TCSTATUS_IXMT 119 119 or t1, t1, t2 120 120 mtc0 t1, CP0_TCSTATUS 121 ehb121 _ehb 122 122 #endif /* CONFIG_MIPS_MT_SMTC */ 123 123 move v0, a0 124 124 jr ra … … 129 129 */ 130 130 LEAF(_save_fp) 131 131 #ifdef CONFIG_64BIT 132 mfc0 t 1, CP0_STATUS132 mfc0 t0, CP0_STATUS 133 133 #endif 134 fpu_save_double a0 t 1 t0 t2# clobbers t1134 fpu_save_double a0 t0 t1 # clobbers t1 135 135 jr ra 136 136 END(_save_fp) 137 137 … … 139 139 * Restore a thread's fp context. 140 140 */ 141 141 LEAF(_restore_fp) 142 fpu_restore_double a0, t1 # clobbers t1 142 #ifdef CONFIG_64BIT 143 mfc0 t0, CP0_STATUS 144 #endif 145 fpu_restore_double a0 t0 t1 # clobbers t1 143 146 jr ra 144 147 END(_restore_fp) 145 148 -
arch/mips/kernel/scall32-o32.S
diff -Naur linux-2.6.17.4-kernel/arch/mips/kernel/scall32-o32.S linux-2.6.17.4-mips/arch/mips/kernel/scall32-o32.S
old new 497 497 sys sys_sched_get_priority_min 1 498 498 sys sys_sched_rr_get_interval 2 /* 4165 */ 499 499 sys sys_nanosleep, 2 500 sys sys_mremap, 4500 sys sys_mremap, 5 501 501 sys sys_accept 3 502 502 sys sys_bind 3 503 503 sys sys_connect 3 /* 4170 */ … … 647 647 sys sys_unshare 1 648 648 sys sys_splice 4 649 649 sys sys_sync_file_range 7 /* 4305 */ 650 sys sys_tee 4 650 651 .endm 651 652 652 653 /* We pre-compute the number of _instruction_ bytes needed to -
arch/mips/kernel/scall64-64.S
diff -Naur linux-2.6.17.4-kernel/arch/mips/kernel/scall64-64.S linux-2.6.17.4-mips/arch/mips/kernel/scall64-64.S
old new 462 462 PTR sys_unshare 463 463 PTR sys_splice 464 464 PTR sys_sync_file_range 465 PTR sys_tee /* 5265 */ -
arch/mips/kernel/scall64-n32.S
diff -Naur linux-2.6.17.4-kernel/arch/mips/kernel/scall64-n32.S linux-2.6.17.4-mips/arch/mips/kernel/scall64-n32.S
old new 388 388 PTR sys_unshare 389 389 PTR sys_splice 390 390 PTR sys_sync_file_range 391 PTR sys_tee -
arch/mips/kernel/scall64-o32.S
diff -Naur linux-2.6.17.4-kernel/arch/mips/kernel/scall64-o32.S linux-2.6.17.4-mips/arch/mips/kernel/scall64-o32.S
old new 510 510 PTR sys_unshare 511 511 PTR sys_splice 512 512 PTR sys32_sync_file_range /* 4305 */ 513 PTR sys_tee 513 514 .size sys_call_table,.-sys_call_table -
arch/mips/kernel/smp.c
diff -Naur linux-2.6.17.4-kernel/arch/mips/kernel/smp.c linux-2.6.17.4-mips/arch/mips/kernel/smp.c
old new 336 336 preempt_disable(); 337 337 338 338 if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) { 339 smp_call_function(flush_tlb_mm_ipi, (void *)mm, 1, 1);339 __on_other_cores(flush_tlb_mm_ipi, (void *)mm); 340 340 } else { 341 341 int i; 342 342 for (i = 0; i < num_online_cpus(); i++) … … 372 372 fd.vma = vma; 373 373 fd.addr1 = start; 374 374 fd.addr2 = end; 375 smp_call_function(flush_tlb_range_ipi, (void *)&fd, 1, 1);375 __on_other_cores(flush_tlb_range_ipi, (void *)&fd); 376 376 } else { 377 377 int i; 378 378 for (i = 0; i < num_online_cpus(); i++) … … 414 414 415 415 fd.vma = vma; 416 416 fd.addr1 = page; 417 smp_call_function(flush_tlb_page_ipi, (void *)&fd, 1, 1);417 __on_other_cores(flush_tlb_page_ipi, (void *)&fd); 418 418 } else { 419 419 int i; 420 420 for (i = 0; i < num_online_cpus(); i++) … … 434 434 435 435 void flush_tlb_one(unsigned long vaddr) 436 436 { 437 smp_call_function(flush_tlb_one_ipi, (void *) vaddr, 1, 1); 438 local_flush_tlb_one(vaddr); 437 __on_each_core(flush_tlb_one_ipi, (void *) vaddr); 439 438 } 440 439 441 440 static DEFINE_PER_CPU(struct cpu, cpu_devices); -
arch/mips/kernel/smtc-asm.S
diff -Naur linux-2.6.17.4-kernel/arch/mips/kernel/smtc-asm.S linux-2.6.17.4-mips/arch/mips/kernel/smtc-asm.S
old new 52 52 .set noat 53 53 /* Disable thread scheduling to make Status update atomic */ 54 54 DMT 27 # dmt k1 55 ehb55 _ehb 56 56 /* Set EXL */ 57 57 mfc0 k0,CP0_STATUS 58 58 ori k0,k0,ST0_EXL 59 59 mtc0 k0,CP0_STATUS 60 ehb60 _ehb 61 61 /* Thread scheduling now inhibited by EXL. Restore TE state. */ 62 62 andi k1,k1,VPECONTROL_TE 63 63 beqz k1,1f … … 82 82 li k1,ST0_CU0 83 83 or k1,k1,k0 84 84 mtc0 k1,CP0_STATUS 85 ehb85 _ehb 86 86 get_saved_sp 87 87 /* Interrupting TC will have pre-set values in slots in the new frame */ 88 88 2: subu k1,k1,PT_SIZE … … 90 90 lw k0,PT_TCSTATUS(k1) 91 91 /* Write it to TCStatus to restore CU/KSU/IXMT state */ 92 92 mtc0 k0,$2,1 93 ehb93 _ehb 94 94 lw k0,PT_EPC(k1) 95 95 mtc0 k0,CP0_EPC 96 96 /* Save all will redundantly recompute the SP, but use it for now */ … … 116 116 mfc0 t0,CP0_TCSTATUS 117 117 ori t1,t0,TCSTATUS_IXMT 118 118 mtc0 t1,CP0_TCSTATUS 119 ehb119 _ehb 120 120 /* We know we're in kernel mode, so prepare stack frame */ 121 121 subu t1,sp,PT_SIZE 122 122 sw ra,PT_EPC(t1) -
arch/mips/kernel/traps.c
diff -Naur linux-2.6.17.4-kernel/arch/mips/kernel/traps.c linux-2.6.17.4-mips/arch/mips/kernel/traps.c
old new 1051 1051 return (void *)old_handler; 1052 1052 } 1053 1053 1054 #ifdef CONFIG_CPU_MIPSR2 1054 #ifdef CONFIG_CPU_MIPSR2_SRS 1055 1055 /* 1056 1056 * MIPSR2 shadow register set allocation 1057 1057 * FIXME: SMP... … … 1070 1070 1071 1071 static void mips_srs_init(void) 1072 1072 { 1073 #ifdef CONFIG_CPU_MIPSR2_SRS1074 1073 shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1; 1075 1074 printk(KERN_INFO "%d MIPSR2 register sets available\n", 1076 1075 shadow_registers.sr_supported); 1077 #endif1078 1076 shadow_registers.sr_allocated = 1; /* Set 0 used by kernel */ 1079 1077 } 1080 1078 … … 1199 1197 { 1200 1198 return set_vi_srs_handler(n, addr, 0); 1201 1199 } 1202 #endif 1200 1201 #else 1202 1203 static inline void mips_srs_init(void) 1204 { 1205 } 1206 1207 #endif /* CONFIG_CPU_MIPSR2_SRS */ 1203 1208 1204 1209 /* 1205 1210 * This is used by native signal handling … … 1389 1394 else 1390 1395 ebase = CAC_BASE; 1391 1396 1392 #ifdef CONFIG_CPU_MIPSR21393 1397 mips_srs_init(); 1394 #endif1395 1398 1396 1399 per_cpu_trap_init(); 1397 1400 -
arch/mips/lib/iomap.c
diff -Naur linux-2.6.17.4-kernel/arch/mips/lib/iomap.c linux-2.6.17.4-mips/arch/mips/lib/iomap.c
old new 1 /*2 * iomap.c, Memory Mapped I/O routines for MIPS architecture.3 *4 * This code is based on lib/iomap.c, by Linus Torvalds.5 *6 * Copyright (C) 2004-2005 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>7 *8 * This program is free software; you can redistribute it and/or modify9 * it under the terms of the GNU General Public License as published by10 * the Free Software Foundation; either version 2 of the License, or11 * (at your option) any later version.12 *13 * This program is distributed in the hope that it will be useful,14 * but WITHOUT ANY WARRANTY; without even the implied warranty of15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the16 * GNU General Public License for more details.17 *18 * You should have received a copy of the GNU General Public License19 * along with this program; if not, write to the Free Software20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA21 */22 #include <linux/ioport.h>23 #include <linux/module.h>24 #include <linux/pci.h>25 26 #include <asm/io.h>27 28 void __iomem *ioport_map(unsigned long port, unsigned int nr)29 {30 unsigned long end;31 32 end = port + nr - 1UL;33 if (ioport_resource.start > port ||34 ioport_resource.end < end || port > end)35 return NULL;36 37 return (void __iomem *)(mips_io_port_base + port);38 }39 40 void ioport_unmap(void __iomem *addr)41 {42 }43 EXPORT_SYMBOL(ioport_map);44 EXPORT_SYMBOL(ioport_unmap);45 46 void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)47 {48 unsigned long start, len, flags;49 50 if (dev == NULL)51 return NULL;52 53 start = pci_resource_start(dev, bar);54 len = pci_resource_len(dev, bar);55 if (!start || !len)56 return NULL;57 58 if (maxlen != 0 && len > maxlen)59 len = maxlen;60 61 flags = pci_resource_flags(dev, bar);62 if (flags & IORESOURCE_IO)63 return ioport_map(start, len);64 if (flags & IORESOURCE_MEM) {65 if (flags & IORESOURCE_CACHEABLE)66 return ioremap_cachable(start, len);67 return ioremap_nocache(start, len);68 }69 70 return NULL;71 }72 73 void pci_iounmap(struct pci_dev *dev, void __iomem *addr)74 {75 iounmap(addr);76 }77 EXPORT_SYMBOL(pci_iomap);78 EXPORT_SYMBOL(pci_iounmap); -
arch/mips/lib/Makefile
diff -Naur linux-2.6.17.4-kernel/arch/mips/lib/Makefile linux-2.6.17.4-mips/arch/mips/lib/Makefile
old new 5 5 lib-y += csum_partial_copy.o memcpy.o promlib.o strlen_user.o strncpy_user.o \ 6 6 strnlen_user.o uncached.o 7 7 8 obj-y += iomap.o 8 # libgcc-style stuff needed in the kernel 9 lib-y += ashldi3.o ashrdi3.o lshrdi3.o 9 10 10 11 EXTRA_AFLAGS := $(CFLAGS) -
arch/mips/lib-32/dump_tlb.c
diff -Naur linux-2.6.17.4-kernel/arch/mips/lib-32/dump_tlb.c linux-2.6.17.4-mips/arch/mips/lib-32/dump_tlb.c
old new 41 41 return "256Mb"; 42 42 #endif 43 43 } 44 45 return "unknown";46 44 } 47 45 48 46 #define BARRIER() \ -
arch/mips/lib-64/dump_tlb.c
diff -Naur linux-2.6.17.4-kernel/arch/mips/lib-64/dump_tlb.c linux-2.6.17.4-mips/arch/mips/lib-64/dump_tlb.c
old new 32 32 case PM_256M: return "256Mb"; 33 33 #endif 34 34 } 35 36 return "unknown";37 35 } 38 36 39 37 #define BARRIER() \ -
arch/mips/Makefile
diff -Naur linux-2.6.17.4-kernel/arch/mips/Makefile linux-2.6.17.4-mips/arch/mips/Makefile
old new 83 83 LDFLAGS_vmlinux += -G 0 -static -n -nostdlib 84 84 MODFLAGS += -mlong-calls 85 85 86 cflags-y += -ffreestanding 87 86 88 # 87 89 # We explicitly add the endianness specifier if needed, this allows 88 90 # to compile kernels with a toolchain for the other endianness. We … … 365 367 cflags-$(CONFIG_PMC_YOSEMITE) += -Iinclude/asm-mips/mach-yosemite 366 368 load-$(CONFIG_PMC_YOSEMITE) += 0xffffffff80100000 367 369 370 # 368 371 # Qemu simulating MIPS32 4Kc 369 372 # 370 373 core-$(CONFIG_QEMU) += arch/mips/qemu/ -
arch/mips/mips-boards/generic/memory.c
diff -Naur linux-2.6.17.4-kernel/arch/mips/mips-boards/generic/memory.c linux-2.6.17.4-mips/arch/mips/mips-boards/generic/memory.c
old new 48 48 }; 49 49 #endif 50 50 51 /* determined physical memory size, not overridden by command line args */ 52 unsigned long physical_memsize = 0L; 53 51 54 struct prom_pmemblock * __init prom_getmdesc(void) 52 55 { 53 56 char *memsize_str; 54 57 unsigned int memsize; 55 58 char cmdline[CL_SIZE], *ptr; 56 59 57 /* Check the command line first for a memsize directive */ 60 /* otherwise look in the environment */ 61 memsize_str = prom_getenv("memsize"); 62 if (!memsize_str) { 63 prom_printf("memsize not set in boot prom, set to default (32Mb)\n"); 64 physical_memsize = 0x02000000; 65 } else { 66 #ifdef DEBUG 67 prom_printf("prom_memsize = %s\n", memsize_str); 68 #endif 69 physical_memsize = simple_strtol(memsize_str, NULL, 0); 70 } 71 72 #ifdef CONFIG_CPU_BIG_ENDIAN 73 /* SOC-it swaps, or perhaps doesn't swap, when DMA'ing the last 74 word of physical memory */ 75 physical_memsize -= PAGE_SIZE; 76 #endif 77 78 /* Check the command line for a memsize directive that overrides 79 the physical/default amount */ 58 80 strcpy(cmdline, arcs_cmdline); 59 81 ptr = strstr(cmdline, "memsize="); 60 82 if (ptr && (ptr != cmdline) && (*(ptr - 1) != ' ')) 61 83 ptr = strstr(ptr, " memsize="); 62 84 63 if (ptr) {85 if (ptr) 64 86 memsize = memparse(ptr + 8, &ptr); 65 } 66 else { 67 /* otherwise look in the environment */ 68 memsize_str = prom_getenv("memsize"); 69 if (!memsize_str) { 70 prom_printf("memsize not set in boot prom, set to default (32Mb)\n"); 71 memsize = 0x02000000; 72 } else { 73 #ifdef DEBUG 74 prom_printf("prom_memsize = %s\n", memsize_str); 75 #endif 76 memsize = simple_strtol(memsize_str, NULL, 0); 77 } 78 } 87 else 88 memsize = physical_memsize; 89 79 90 memset(mdesc, 0, sizeof(mdesc)); 80 91 81 92 mdesc[0].type = yamon_dontuse; -
arch/mips/mips-boards/malta/malta_int.c
diff -Naur linux-2.6.17.4-kernel/arch/mips/mips-boards/malta/malta_int.c linux-2.6.17.4-mips/arch/mips/mips-boards/malta/malta_int.c
old new 208 208 unsigned int a0 = 7; 209 209 unsigned int t0; 210 210 211 t0 = s0& 0xf000;211 t0 = pending & 0xf000; 212 212 t0 = t0 < 1; 213 213 t0 = t0 << 2; 214 214 a0 = a0 - t0; 215 s0 = s0<< t0;215 pending = pending << t0; 216 216 217 t0 = s0& 0xc000;217 t0 = pending & 0xc000; 218 218 t0 = t0 < 1; 219 219 t0 = t0 << 1; 220 220 a0 = a0 - t0; 221 s0 = s0<< t0;221 pending = pending << t0; 222 222 223 t0 = s0& 0x8000;223 t0 = pending & 0x8000; 224 224 t0 = t0 < 1; 225 225 //t0 = t0 << 2; 226 226 a0 = a0 - t0; 227 // s0 = s0<< t0;227 //pending = pending << t0; 228 228 229 229 return a0; 230 230 #endif -
arch/mips/mm/c-r4k.c
diff -Naur linux-2.6.17.4-kernel/arch/mips/mm/c-r4k.c linux-2.6.17.4-mips/arch/mips/mm/c-r4k.c
old new 24 24 #include <asm/page.h> 25 25 #include <asm/pgtable.h> 26 26 #include <asm/r4kcache.h> 27 #include <asm/smp.h> 27 28 #include <asm/system.h> 28 29 #include <asm/mmu_context.h> 29 30 #include <asm/war.h> 30 31 #include <asm/cacheflush.h> /* for run_uncached() */ 31 32 32 33 /*34 * Special Variant of smp_call_function for use by cache functions:35 *36 * o No return value37 * o collapses to normal function call on UP kernels38 * o collapses to normal function call on systems with a single shared39 * primary cache.40 */41 static inline void r4k_on_each_cpu(void (*func) (void *info), void *info,42 int retry, int wait)43 {44 preempt_disable();45 46 #if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)47 smp_call_function(func, info, retry, wait);48 #endif49 func(info);50 preempt_enable();51 }52 53 33 /* 54 34 * Must die. 55 35 */ … … 60 40 /* 61 41 * Dummy cache handling routines for machines without boardcaches 62 42 */ 63 static void no_sc_noop(void) {}43 static void cache_noop(void) {} 64 44 65 45 static struct bcache_ops no_sc_ops = { 66 .bc_enable = (void *) no_sc_noop,67 .bc_disable = (void *) no_sc_noop,68 .bc_wback_inv = (void *) no_sc_noop,69 .bc_inv = (void *) no_sc_noop46 .bc_enable = (void *)cache_noop, 47 .bc_disable = (void *)cache_noop, 48 .bc_wback_inv = (void *)cache_noop, 49 .bc_inv = (void *)cache_noop 70 50 }; 71 51 72 52 struct bcache_ops *bcops = &no_sc_ops; … … 94 74 { 95 75 unsigned long dc_lsize = cpu_dcache_line_size(); 96 76 97 if (dc_lsize == 16) 77 if (dc_lsize == 0) 78 r4k_blast_dcache_page = (void *)cache_noop; 79 else if (dc_lsize == 16) 98 80 r4k_blast_dcache_page = blast_dcache16_page; 99 81 else if (dc_lsize == 32) 100 82 r4k_blast_dcache_page = r4k_blast_dcache_page_dc32; … … 106 88 { 107 89 unsigned long dc_lsize = cpu_dcache_line_size(); 108 90 109 if (dc_lsize == 16) 91 if (dc_lsize == 0) 92 r4k_blast_dcache_page_indexed = (void *)cache_noop; 93 else if (dc_lsize == 16) 110 94 r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed; 111 95 else if (dc_lsize == 32) 112 96 r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed; … … 118 102 { 119 103 unsigned long dc_lsize = cpu_dcache_line_size(); 120 104 121 if (dc_lsize == 16) 105 if (dc_lsize == 0) 106 r4k_blast_dcache = (void *)cache_noop; 107 else if (dc_lsize == 16) 122 108 r4k_blast_dcache = blast_dcache16; 123 109 else if (dc_lsize == 32) 124 110 r4k_blast_dcache = blast_dcache32; … … 201 187 { 202 188 unsigned long ic_lsize = cpu_icache_line_size(); 203 189 204 if (ic_lsize == 16) 190 if (ic_lsize == 0) 191 r4k_blast_icache_page = (void *)cache_noop; 192 else if (ic_lsize == 16) 205 193 r4k_blast_icache_page = blast_icache16_page; 206 194 else if (ic_lsize == 32) 207 195 r4k_blast_icache_page = blast_icache32_page; … … 216 204 { 217 205 unsigned long ic_lsize = cpu_icache_line_size(); 218 206 219 if (ic_lsize == 16) 207 if (ic_lsize == 0) 208 r4k_blast_icache_page_indexed = (void *)cache_noop; 209 else if (ic_lsize == 16) 220 210 r4k_blast_icache_page_indexed = blast_icache16_page_indexed; 221 211 else if (ic_lsize == 32) { 222 212 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x()) … … 238 228 { 239 229 unsigned long ic_lsize = cpu_icache_line_size(); 240 230 241 if (ic_lsize == 16) 231 if (ic_lsize == 0) 232 r4k_blast_icache = (void *)cache_noop; 233 else if (ic_lsize == 16) 242 234 r4k_blast_icache = blast_icache16; 243 235 else if (ic_lsize == 32) { 244 236 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x()) … … 258 250 unsigned long sc_lsize = cpu_scache_line_size(); 259 251 260 252 if (scache_size == 0) 261 r4k_blast_scache_page = (void *) no_sc_noop;253 r4k_blast_scache_page = (void *)cache_noop; 262 254 else if (sc_lsize == 16) 263 255 r4k_blast_scache_page = blast_scache16_page; 264 256 else if (sc_lsize == 32) … … 276 268 unsigned long sc_lsize = cpu_scache_line_size(); 277 269 278 270 if (scache_size == 0) 279 r4k_blast_scache_page_indexed = (void *) no_sc_noop;271 r4k_blast_scache_page_indexed = (void *)cache_noop; 280 272 else if (sc_lsize == 16) 281 273 r4k_blast_scache_page_indexed = blast_scache16_page_indexed; 282 274 else if (sc_lsize == 32) … … 294 286 unsigned long sc_lsize = cpu_scache_line_size(); 295 287 296 288 if (scache_size == 0) 297 r4k_blast_scache = (void *) no_sc_noop;289 r4k_blast_scache = (void *)cache_noop; 298 290 else if (sc_lsize == 16) 299 291 r4k_blast_scache = blast_scache16; 300 292 else if (sc_lsize == 32) … … 320 312 if (!cpu_has_dc_aliases) 321 313 return; 322 314 323 r4k_on_each_cpu(local_r4k_flush_cache_all, NULL, 1, 1);315 __on_each_core(local_r4k_flush_cache_all, NULL); 324 316 } 325 317 326 318 static inline void local_r4k___flush_cache_all(void * args) … … 342 334 343 335 static void r4k___flush_cache_all(void) 344 336 { 345 r4k_on_each_cpu(local_r4k___flush_cache_all, NULL, 1, 1);337 __on_each_core(local_r4k___flush_cache_all, NULL); 346 338 } 347 339 348 340 static inline void local_r4k_flush_cache_range(void * args) … … 363 355 static void r4k_flush_cache_range(struct vm_area_struct *vma, 364 356 unsigned long start, unsigned long end) 365 357 { 366 r4k_on_each_cpu(local_r4k_flush_cache_range, vma, 1, 1);358 __on_each_core(local_r4k_flush_cache_range, vma); 367 359 } 368 360 369 361 static inline void local_r4k_flush_cache_mm(void * args) … … 392 384 if (!cpu_has_dc_aliases) 393 385 return; 394 386 395 r4k_on_each_cpu(local_r4k_flush_cache_mm, mm, 1, 1);387 __on_each_core(local_r4k_flush_cache_mm, mm); 396 388 } 397 389 398 390 struct flush_cache_page_args { … … 483 475 args.addr = addr; 484 476 args.pfn = pfn; 485 477 486 r4k_on_each_cpu(local_r4k_flush_cache_page, &args, 1, 1);478 __on_each_core(local_r4k_flush_cache_page, &args); 487 479 } 488 480 489 481 static inline void local_r4k_flush_data_cache_page(void * addr) … … 493 485 494 486 static void r4k_flush_data_cache_page(unsigned long addr) 495 487 { 496 r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr, 1, 1);488 __on_each_core(local_r4k_flush_data_cache_page, (void *) addr); 497 489 } 498 490 499 491 struct flush_icache_range_args { … … 508 500 unsigned long end = fir_args->end; 509 501 510 502 if (!cpu_has_ic_fills_f_dc) { 511 if (end - start > dcache_size) {503 if (end - start >= dcache_size) { 512 504 r4k_blast_dcache(); 513 505 } else { 514 506 R4600_HIT_CACHEOP_WAR_IMPL; … … 536 528 args.start = start; 537 529 args.end = end; 538 530 539 r4k_on_each_cpu(local_r4k_flush_icache_range, &args, 1, 1);531 __on_each_core(local_r4k_flush_icache_range, &args); 540 532 instruction_hazard(); 541 533 } 542 534 … … 612 604 args.vma = vma; 613 605 args.page = page; 614 606 615 r4k_on_each_cpu(local_r4k_flush_icache_page, &args, 1, 1);607 __on_each_core(local_r4k_flush_icache_page, &args); 616 608 } 617 609 618 610 … … 683 675 unsigned long addr = (unsigned long) arg; 684 676 685 677 R4600_HIT_CACHEOP_WAR_IMPL; 686 protected_writeback_dcache_line(addr & ~(dc_lsize - 1)); 678 if (dc_lsize) 679 protected_writeback_dcache_line(addr & ~(dc_lsize - 1)); 687 680 if (!cpu_icache_snoops_remote_store && scache_size) 688 681 protected_writeback_scache_line(addr & ~(sc_lsize - 1)); 689 protected_flush_icache_line(addr & ~(ic_lsize - 1)); 682 if (ic_lsize) 683 protected_flush_icache_line(addr & ~(ic_lsize - 1)); 690 684 if (MIPS4K_ICACHE_REFILL_WAR) { 691 685 __asm__ __volatile__ ( 692 686 ".set push\n\t" … … 711 705 712 706 static void r4k_flush_cache_sigtramp(unsigned long addr) 713 707 { 714 r4k_on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr, 1, 1);708 __on_each_core(local_r4k_flush_cache_sigtramp, (void *) addr); 715 709 } 716 710 717 711 static void r4k_flush_icache_all(void) … … 973 967 c->icache.waysize = icache_size / c->icache.ways; 974 968 c->dcache.waysize = dcache_size / c->dcache.ways; 975 969 976 c->icache.sets = icache_size / (c->icache.linesz * c->icache.ways); 977 c->dcache.sets = dcache_size / (c->dcache.linesz * c->dcache.ways); 970 c->icache.sets = c->icache.linesz ? 971 icache_size / (c->icache.linesz * c->icache.ways) : 0; 972 c->dcache.sets = c->dcache.linesz ? 973 dcache_size / (c->dcache.linesz * c->dcache.ways) : 0; 978 974 979 975 /* 980 976 * R10000 and R12000 P-caches are odd in a positive way. They're 32kB … … 993 989 break; 994 990 case CPU_24K: 995 991 case CPU_34K: 996 if (!(read_c0_config7() & (1 << 16))) 992 if ((read_c0_config7() & (1 << 16))) { 993 /* effectively physically indexed dcache, 994 thus no virtual aliases. */ 995 c->dcache.flags |= MIPS_CACHE_PINDEX; 996 break; 997 } 997 998 default: 998 999 999 if (c->dcache.waysize > PAGE_SIZE) 1000 c->dcache.flags |= MIPS_CACHE_ALIASES; 1000 1001 } 1001 1002 1002 1003 switch (c->cputype) { … … 1092 1093 1093 1094 extern int r5k_sc_init(void); 1094 1095 extern int rm7k_sc_init(void); 1096 extern int mips_sc_init(void); 1095 1097 1096 1098 static void __init setup_scache(void) 1097 1099 { … … 1139 1141 return; 1140 1142 1141 1143 default: 1144 if (c->isa_level == MIPS_CPU_ISA_M32R1 || 1145 c->isa_level == MIPS_CPU_ISA_M32R2 || 1146 c->isa_level == MIPS_CPU_ISA_M64R1 || 1147 c->isa_level == MIPS_CPU_ISA_M64R2) { 1148 #ifdef CONFIG_MIPS_CPU_SCACHE 1149 if (mips_sc_init ()) { 1150 scache_size = c->scache.ways * c->scache.sets * c->scache.linesz; 1151 printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n", 1152 scache_size >> 10, 1153 way_string[c->scache.ways], c->scache.linesz); 1154 } 1155 #else 1156 if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT)) 1157 panic("Dunno how to handle MIPS32 / MIPS64 second level cache"); 1158 #endif 1159 return; 1160 } 1142 1161 sc_present = 0; 1143 1162 } 1144 1163 1145 1164 if (!sc_present) 1146 1165 return; 1147 1166 1148 if ((c->isa_level == MIPS_CPU_ISA_M32R1 ||1149 c->isa_level == MIPS_CPU_ISA_M64R1) &&1150 !(c->scache.flags & MIPS_CACHE_NOT_PRESENT))1151 panic("Dunno how to handle MIPS32 / MIPS64 second level cache");1152 1153 1167 /* compute a couple of other cache variables */ 1154 1168 c->scache.waysize = scache_size / c->scache.ways; 1155 1169 … … 1246 1260 * This code supports virtually indexed processors and will be 1247 1261 * unnecessarily inefficient on physically indexed processors. 1248 1262 */ 1249 shm_align_mask = max_t( unsigned long, 1250 c->dcache.sets * c->dcache.linesz - 1, 1251 PAGE_SIZE - 1); 1252 1263 if (c->dcache.linesz) 1264 shm_align_mask = max_t( unsigned long, 1265 c->dcache.sets * c->dcache.linesz - 1, 1266 PAGE_SIZE - 1); 1267 else 1268 shm_align_mask = PAGE_SIZE-1; 1253 1269 flush_cache_all = r4k_flush_cache_all; 1254 1270 __flush_cache_all = r4k___flush_cache_all; 1255 1271 flush_cache_mm = r4k_flush_cache_mm; -
arch/mips/mm/Makefile
diff -Naur linux-2.6.17.4-kernel/arch/mips/mm/Makefile linux-2.6.17.4-mips/arch/mips/mm/Makefile
old new 30 30 obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o 31 31 obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o 32 32 obj-$(CONFIG_RM7000_CPU_SCACHE) += sc-rm7k.o 33 obj-$(CONFIG_MIPS_CPU_SCACHE) += sc-mips.o 33 34 34 35 # 35 36 # Choose one DMA coherency model -
arch/mips/pci/fixup-tb0219.c
diff -Naur linux-2.6.17.4-kernel/arch/mips/pci/fixup-tb0219.c linux-2.6.17.4-mips/arch/mips/pci/fixup-tb0219.c
old new 2 2 * fixup-tb0219.c, The TANBAC TB0219 specific PCI fixups. 3 3 * 4 4 * Copyright (C) 2003 Megasolution Inc. <matsu@megasolution.jp> 5 * Copyright (C) 2004 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>5 * Copyright (C) 2004-2005 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> 6 6 * 7 7 * This program is free software; you can redistribute it and/or modify 8 8 * it under the terms of the GNU General Public License as published by -
arch/mips/qemu/Makefile
diff -Naur linux-2.6.17.4-kernel/arch/mips/qemu/Makefile linux-2.6.17.4-mips/arch/mips/qemu/Makefile
old new 4 4 5 5 obj-y = q-firmware.o q-irq.o q-mem.o q-setup.o 6 6 7 obj-$(CONFIG_VT) += q-vga.o 7 8 obj-$(CONFIG_SMP) += q-smp.o -
arch/mips/qemu/q-setup.c
diff -Naur linux-2.6.17.4-kernel/arch/mips/qemu/q-setup.c linux-2.6.17.4-mips/arch/mips/qemu/q-setup.c
old new 2 2 #include <asm/io.h> 3 3 #include <asm/time.h> 4 4 5 extern void qvga_init(void); 6 5 7 #define QEMU_PORT_BASE 0xb4000000 6 8 7 9 const char *get_system_type(void) … … 21 23 void __init plat_setup(void) 22 24 { 23 25 set_io_port_base(QEMU_PORT_BASE); 26 #ifdef CONFIG_VT 27 qvga_init(); 28 #endif 24 29 board_timer_setup = qemu_timer_setup; 25 30 } -
arch/mips/sgi-ip27/ip27-irq.c
diff -Naur linux-2.6.17.4-kernel/arch/mips/sgi-ip27/ip27-irq.c linux-2.6.17.4-mips/arch/mips/sgi-ip27/ip27-irq.c
old new 360 360 361 361 static unsigned long irq_map[NR_IRQS / BITS_PER_LONG]; 362 362 363 staticint allocate_irqno(void)363 int allocate_irqno(void) 364 364 { 365 365 int irq; 366 366 -
arch/mips/sgi-ip27/ip27-timer.c
diff -Naur linux-2.6.17.4-kernel/arch/mips/sgi-ip27/ip27-timer.c linux-2.6.17.4-mips/arch/mips/sgi-ip27/ip27-timer.c
old new 89 89 } 90 90 #endif 91 91 92 static unsigned int rt_timer_irq; 93 92 94 void ip27_rt_timer_interrupt(struct pt_regs *regs) 93 95 { 94 96 int cpu = smp_processor_id(); 95 97 int cpuA = cputoslice(cpu) == 0; 96 int irq = 9; /* XXX Assign number */98 unsigned int irq = rt_timer_irq; 97 99 98 100 irq_enter(); 99 101 write_seqlock(&xtime_lock); … … 179 181 return mktime(year, month, date, hour, min, sec); 180 182 } 181 183 184 static void startup_rt_irq(unsigned int irq) 185 { 186 } 187 188 static void shutdown_rt_irq(unsigned int irq) 189 { 190 } 191 192 static void enable_rt_irq(unsigned int irq) 193 { 194 } 195 196 static void disable_rt_irq(unsigned int irq) 197 { 198 } 199 200 static void mask_and_ack_rt(unsigned int irq) 201 { 202 } 203 204 static void end_rt_irq(unsigned int irq) 205 { 206 } 207 208 static struct hw_interrupt_type rt_irq_type = { 209 .typename = "SN HUB RT timer", 210 .startup = startup_rt_irq, 211 .shutdown = shutdown_rt_irq, 212 .enable = enable_rt_irq, 213 .disable = disable_rt_irq, 214 .ack = mask_and_ack_rt, 215 .end = end_rt_irq, 216 }; 217 218 static struct irqaction rt_irqaction = { 219 .handler = ip27_rt_timer_interrupt, 220 .flags = SA_INTERRUPT, 221 .mask = CPU_MASK_NONE, 222 .name = "timer" 223 }; 224 225 extern int allocate_irqno(void); 226 182 227 static void ip27_timer_setup(struct irqaction *irq) 183 228 { 229 int irqno = allocate_irqno(); 230 231 if (irqno < 0) 232 panic("Can't allocate interrupt number for timer interrupt"); 233 234 irq_desc[irqno].status = IRQ_DISABLED; 235 irq_desc[irqno].action = NULL; 236 irq_desc[irqno].depth = 1; 237 irq_desc[irqno].handler = &rt_irq_type; 238 184 239 /* over-write the handler, we use our own way */ 185 240 irq->handler = no_action; 186 241 187 242 /* setup irqaction */ 188 // setup_irq(IP27_TIMER_IRQ, irq); /* XXX Can't do this yet. */ 243 irq_desc[irqno].status |= IRQ_PER_CPU; 244 245 rt_timer_irq = irqno; 189 246 } 190 247 191 248 void __init ip27_time_init(void) -
arch/mips/sgi-ip27/Kconfig
diff -Naur linux-2.6.17.4-kernel/arch/mips/sgi-ip27/Kconfig linux-2.6.17.4-mips/arch/mips/sgi-ip27/Kconfig
old new 35 35 depends on SGI_IP27 36 36 help 37 37 Change the way a Linux kernel is loaded into memory on a MIPS64 38 machine. This is required in order to support text replication and38 machine. This is required in order to support text replication on 39 39 NUMA. If you need to understand it, read the source code. 40 40 41 41 config REPLICATE_KTEXT 42 42 bool "Kernel text replication support" 43 43 depends on SGI_IP27 44 select MAPPED_KERNEL 44 45 help 45 46 Say Y here to enable replicating the kernel text across multiple 46 47 nodes in a NUMA cluster. This trades memory for speed. -
arch/mips/sibyte/bcm1480/irq.c
diff -Naur linux-2.6.17.4-kernel/arch/mips/sibyte/bcm1480/irq.c linux-2.6.17.4-mips/arch/mips/sibyte/bcm1480/irq.c
old new 503 503 #ifdef CONFIG_SIBYTE_BCM1480_PROF 504 504 if (pending & CAUSEF_IP7) /* Cpu performance counter interrupt */ 505 505 sbprof_cpu_intr(exception_epc(regs)); 506 else 506 507 #endif 507 508 508 509 if (pending & CAUSEF_IP4) 509 510 bcm1480_timer_interrupt(regs); 510 511 511 512 #ifdef CONFIG_SMP 512 if (pending & CAUSEF_IP3)513 else if (pending & CAUSEF_IP3) 513 514 bcm1480_mailbox_interrupt(regs); 514 515 #endif 515 516 516 517 #ifdef CONFIG_KGDB 517 if (pending & CAUSEF_IP6)518 else if (pending & CAUSEF_IP6) 518 519 bcm1480_kgdb_interrupt(regs); /* KGDB (uart 1) */ 519 520 #endif 520 521 521 if (pending & CAUSEF_IP2) {522 else if (pending & CAUSEF_IP2) { 522 523 unsigned long long mask_h, mask_l; 523 524 unsigned long base; 524 525 … … 534 535 mask_l = __raw_readq( 535 536 IOADDR(base + R_BCM1480_IMR_INTERRUPT_STATUS_BASE_L)); 536 537 537 if ( !mask_h) {538 if (mask_h) { 538 539 if (mask_h ^ 1) 539 540 do_IRQ(63 - dclz(mask_h), regs); 540 541 else -
arch/mips/sibyte/bcm1480/time.c
diff -Naur linux-2.6.17.4-kernel/arch/mips/sibyte/bcm1480/time.c linux-2.6.17.4-mips/arch/mips/sibyte/bcm1480/time.c
old new 110 110 __raw_writeq(M_SCD_TIMER_ENABLE|M_SCD_TIMER_MODE_CONTINUOUS, 111 111 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); 112 112 113 /*114 * CPU 0 handles the global timer interrupt job115 */116 113 if (cpu == 0) { 114 /* 115 * CPU 0 handles the global timer interrupt job 116 */ 117 117 ll_timer_interrupt(irq, regs); 118 118 } 119 120 /* 121 * every CPU should do profiling and process accouting 122 */ 123 ll_local_timer_interrupt(irq, regs); 119 else { 120 /* 121 * other CPUs should just do profiling and process accounting 122 */ 123 ll_local_timer_interrupt(irq, regs); 124 } 124 125 } 125 126 126 127 /* -
arch/mips/sibyte/Kconfig
diff -Naur linux-2.6.17.4-kernel/arch/mips/sibyte/Kconfig linux-2.6.17.4-mips/arch/mips/sibyte/Kconfig
old new 3 3 select HW_HAS_PCI 4 4 select SIBYTE_HAS_LDT 5 5 select SIBYTE_SB1xxx_SOC 6 select SYS_SUPPORTS_SMP 6 7 7 8 config SIBYTE_BCM1120 8 9 bool … … 30 31 bool 31 32 select HW_HAS_PCI 32 33 select SIBYTE_SB1xxx_SOC 34 select SYS_SUPPORTS_SMP 33 35 34 36 config SIBYTE_BCM1x55 35 37 bool 36 38 select HW_HAS_PCI 37 39 select SIBYTE_SB1xxx_SOC 40 select SYS_SUPPORTS_SMP 38 41 39 42 config SIBYTE_SB1xxx_SOC 40 43 bool -
arch/mips/sibyte/sb1250/irq.c
diff -Naur linux-2.6.17.4-kernel/arch/mips/sibyte/sb1250/irq.c linux-2.6.17.4-mips/arch/mips/sibyte/sb1250/irq.c
old new 435 435 return lz; 436 436 } 437 437 438 extern void sb1250_timer_interrupt(struct pt_regs *regs); 439 extern void sb1250_mailbox_interrupt(struct pt_regs *regs); 440 extern void sb1250_kgdb_interrupt(struct pt_regs *regs); 441 438 442 asmlinkage void plat_irq_dispatch(struct pt_regs *regs) 439 443 { 440 444 unsigned int pending; 441 445 442 446 #ifdef CONFIG_SIBYTE_SB1250_PROF 443 447 /* Set compare to count to silence count/compare timer interrupts */ 444 write_c0_co unt(read_c0_count());448 write_c0_compare(read_c0_count()); 445 449 #endif 446 450 447 451 /* … … 457 461 pending = read_c0_cause(); 458 462 459 463 #ifdef CONFIG_SIBYTE_SB1250_PROF 460 if (pending & CAUSEF_IP7) {/* Cpu performance counter interrupt */464 if (pending & CAUSEF_IP7) /* Cpu performance counter interrupt */ 461 465 sbprof_cpu_intr(exception_epc(regs)); 462 }466 else 463 467 #endif 464 468 465 469 if (pending & CAUSEF_IP4) 466 470 sb1250_timer_interrupt(regs); 467 471 468 472 #ifdef CONFIG_SMP 469 if (pending & CAUSEF_IP3)473 else if (pending & CAUSEF_IP3) 470 474 sb1250_mailbox_interrupt(regs); 471 475 #endif 472 476 473 477 #ifdef CONFIG_KGDB 474 if (pending & CAUSEF_IP6) /* KGDB (uart 1) */478 else if (pending & CAUSEF_IP6) /* KGDB (uart 1) */ 475 479 sb1250_kgdb_interrupt(regs); 476 480 #endif 477 481 478 if (pending & CAUSEF_IP2) {482 else if (pending & CAUSEF_IP2) { 479 483 unsigned long long mask; 480 484 481 485 /* 482 486 * Default...we've hit an IP[2] interrupt, which means we've 483 487 * got to check the 1250 interrupt registers to figure out what 484 488 * to do. Need to detect which CPU we're on, now that 485 ~smp_affinity is supported.489 * smp_affinity is supported. 486 490 */ 487 491 mask = __raw_readq(IOADDR(A_IMR_REGISTER(smp_processor_id(), 488 492 R_IMR_INTERRUPT_STATUS_BASE))); -
arch/mips/sibyte/swarm/setup.c
diff -Naur linux-2.6.17.4-kernel/arch/mips/sibyte/swarm/setup.c linux-2.6.17.4-mips/arch/mips/sibyte/swarm/setup.c
old new 72 72 73 73 void __init swarm_time_init(void) 74 74 { 75 #if defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X) 75 76 /* Setup HPT */ 76 77 sb1250_hpt_setup(); 78 #endif 77 79 } 78 80 79 81 void __init swarm_timer_setup(struct irqaction *irq) -
Documentation/feature-removal-schedule.txt
diff -Naur linux-2.6.17.4-kernel/Documentation/feature-removal-schedule.txt linux-2.6.17.4-mips/Documentation/feature-removal-schedule.txt
old new 147 147 148 148 --------------------------- 149 149 150 What: au1x00_uart driver151 When: January 2006152 Why: The 8250 serial driver now has the ability to deal with the differences153 between the standard 8250 family of UARTs and their slightly strange154 brother on Alchemy SOCs. The loss of features is not considered an155 issue.156 Who: Ralf Baechle <ralf@linux-mips.org>157 158 ---------------------------159 160 150 What: eepro100 network driver 161 151 When: January 2007 162 152 Why: replaced by the e100 driver -
drivers/char/decserial.c
diff -Naur linux-2.6.17.4-kernel/drivers/char/decserial.c linux-2.6.17.4-mips/drivers/char/decserial.c
old new 14 14 * device. Added support for PROM console in drivers/char/tty_io.c 15 15 * instead. Although it may work to enable more than one 16 16 * console device I strongly recommend to use only one. 17 * 18 * Copyright (C) 2004 Maciej W. Rozycki 17 19 */ 18 20 19 21 #include <linux/config.h> 22 #include <linux/errno.h> 20 23 #include <linux/init.h> 21 #include <asm/dec/machtype.h>22 23 #ifdef CONFIG_ZS24 extern int zs_init(void);25 #endif26 24 27 #ifdef CONFIG_DZ 28 extern int dz_init(void); 29 #endif 25 #include <asm/dec/machtype.h> 26 #include <asm/dec/serial.h> 30 27 31 #ifdef CONFIG_SERIAL_CONSOLE 28 extern int register_zs_hook(unsigned int channel, 29 struct dec_serial_hook *hook); 30 extern int unregister_zs_hook(unsigned int channel); 32 31 32 int register_dec_serial_hook(unsigned int channel, 33 struct dec_serial_hook *hook) 34 { 33 35 #ifdef CONFIG_ZS 34 extern void zs_serial_console_init(void); 35 #endif 36 37 #ifdef CONFIG_DZ 38 extern void dz_serial_console_init(void); 36 if (IOASIC) 37 return register_zs_hook(channel, hook); 39 38 #endif 39 return 0; 40 } 40 41 42 int unregister_dec_serial_hook(unsigned int channel) 43 { 44 #ifdef CONFIG_ZS 45 if (IOASIC) 46 return unregister_zs_hook(channel); 41 47 #endif 48 return 0; 49 } 42 50 43 /* rs_init - starts up the serial interface -44 handle normal case of starting up the serial interface */45 51 46 #ifdef CONFIG_SERIAL 52 extern int zs_init(void); 53 extern int dz_init(void); 47 54 55 /* 56 * rs_init - starts up the serial interface - 57 * handle normal case of starting up the serial interface 58 */ 48 59 int __init rs_init(void) 49 60 { 50 51 #if defined(CONFIG_ZS) && defined(CONFIG_DZ)52 if (IOASIC)53 return zs_init();54 else55 return dz_init();56 #else57 58 61 #ifdef CONFIG_ZS 59 return zs_init(); 62 if (IOASIC) 63 return zs_init(); 60 64 #endif 61 62 65 #ifdef CONFIG_DZ 63 return dz_init(); 64 #endif 65 66 if (!IOASIC) 67 return dz_init(); 66 68 #endif 69 return -ENXIO; 67 70 } 68 71 69 72 __initcall(rs_init); 70 73 71 #endif72 74 73 #ifdef CONFIG_SERIAL_CONSOLE 75 #ifdef CONFIG_SERIAL_DEC_CONSOLE 76 77 extern void zs_serial_console_init(void); 78 extern void dz_serial_console_init(void); 74 79 75 /* serial_console_init handles the special case of starting 76 * up the console on the serial port 80 /* 81 * dec_serial_console_init handles the special case of starting 82 * up the console on the serial port 77 83 */ 78 static int __init dec serial_console_init(void)84 static int __init dec_serial_console_init(void) 79 85 { 80 #if defined(CONFIG_ZS) && defined(CONFIG_DZ)81 if (IOASIC)82 zs_serial_console_init();83 else84 dz_serial_console_init();85 #else86 87 86 #ifdef CONFIG_ZS 88 zs_serial_console_init(); 87 if (IOASIC) 88 zs_serial_console_init(); 89 89 #endif 90 91 90 #ifdef CONFIG_DZ 92 dz_serial_console_init(); 93 #endif 94 91 if (!IOASIC) 92 dz_serial_console_init(); 95 93 #endif 96 94 return 0; 97 95 } 98 console_initcall(dec serial_console_init);96 console_initcall(dec_serial_console_init); 99 97 100 98 #endif -
drivers/char/Kconfig
diff -Naur linux-2.6.17.4-kernel/drivers/char/Kconfig linux-2.6.17.4-mips/drivers/char/Kconfig
old new 340 340 To compile this driver as a module, choose M here: the 341 341 module will be called istallion. 342 342 343 config AU1000_UART 344 bool "Enable Au1000 UART Support" 345 depends on SERIAL_NONSTANDARD && MIPS 346 help 347 If you have an Alchemy AU1000 processor (MIPS based) and you want 348 to use serial ports, say Y. Otherwise, say N. 349 350 config AU1000_SERIAL_CONSOLE 351 bool "Enable Au1000 serial console" 352 depends on AU1000_UART 343 config AU1X00_GPIO 344 tristate "Alchemy Au1000 GPIO device support" 345 depends on MIPS && SOC_AU1X00 346 347 config TS_AU1X00_ADS7846 348 tristate "Au1000/ADS7846 touchscreen support" 349 depends on MIPS && SOC_AU1X00 350 351 config AU1X00_USB_TTY 352 tristate "Au1000 USB TTY Device support" 353 depends on MIPS && MIPS_AU1000 && AU1000_USB_DEVICE=y && AU1000_USB_DEVICE 354 355 config AU1X00_USB_RAW 356 tristate "Au1000 USB Raw Device support" 357 depends on MIPS && MIPS_AU1000 && AU1000_USB_DEVICE=y && AU1000_USB_TTY!=y && AU1X00_USB_DEVICE 358 359 config SIBYTE_SB1250_DUART 360 bool "Support for BCM1xxx onchip DUART" 361 depends on MIPS && SIBYTE_SB1xxx_SOC=y 362 363 config SIBYTE_SB1250_DUART_CONSOLE 364 bool "Console on BCM1xxx DUART" 365 depends on SIBYTE_SB1250_DUART 366 367 config SERIAL_DEC 368 bool "DECstation serial support" 369 depends on MACH_DECSTATION 370 default y 353 371 help 354 If you have an Alchemy AU1000 processor (MIPS based) and you want 355 to use a console on a serial port, say Y. Otherwise, say N. 372 This selects whether you want to be asked about drivers for 373 DECstation serial ports. 374 375 Note that the answer to this question won't directly affect the 376 kernel: saying N will just cause the configurator to skip all 377 the questions about DECstation serial ports. 378 379 If unsure, say Y. 380 381 config SERIAL_DEC_CONSOLE 382 bool "Support for console on a DECstation serial port" 383 depends on SERIAL_DEC 384 default y 385 help 386 If you say Y here, it will be possible to use a serial port as the 387 system console (the system console is the device which receives all 388 kernel messages and warnings and which allows logins in single user 389 mode). Note that the firmware uses ttyS0 as the serial console on 390 the Maxine and ttyS2 on the others. 391 392 If unsure, say Y. 393 394 config ZS 395 bool "Z85C30 Serial Support" 396 depends on SERIAL_DEC 397 default y 398 help 399 Documentation on the Zilog 85C350 serial communications controller 400 is downloadable at <http://www.zilog.com/pdfs/serial/z85c30.pdf>. 356 401 357 402 config QTRONIX_KEYBOARD 358 403 bool "Enable Qtronix 990P Keyboard Support" 359 depends on IT8712404 depends on MIPS && (MIPS_ITE8172 || MIPS_IVR) 360 405 help 361 406 Images of Qtronix keyboards are at 362 407 <http://www.qtronix.com/keyboard.html>. … … 368 413 369 414 config IT8172_SCR0 370 415 bool "Enable Smart Card Reader 0 Support " 371 depends on IT8712416 depends on MIPS && (MIPS_ITE8172 || MIPS_IVR) 372 417 help 373 418 Say Y here to support smart-card reader 0 (SCR0) on the Integrated 374 419 Technology Express, Inc. ITE8172 SBC. Vendor page at … … 377 422 378 423 config IT8172_SCR1 379 424 bool "Enable Smart Card Reader 1 Support " 380 depends on IT8712425 depends on MIPS && (MIPS_ITE8172 || MIPS_IVR) 381 426 help 382 427 Say Y here to support smart-card reader 1 (SCR1) on the Integrated 383 428 Technology Express, Inc. ITE8172 SBC. Vendor page at 384 429 <http://www.ite.com.tw/ia/brief_it8172bsp.htm>; picture of the 385 430 board at <http://www.mvista.com/partners/semiconductor/ite.html>. 386 431 432 config ITE_GPIO 433 tristate "ITE GPIO" 434 depends on MIPS && MIPS_ITE8172 435 387 436 config A2232 388 437 tristate "Commodore A2232 serial support (EXPERIMENTAL)" 389 438 depends on EXPERIMENTAL && ZORRO && BROKEN_ON_SMP -
drivers/char/Makefile
diff -Naur linux-2.6.17.4-kernel/drivers/char/Makefile linux-2.6.17.4-mips/drivers/char/Makefile
old new 31 31 obj-$(CONFIG_A2232) += ser_a2232.o generic_serial.o 32 32 obj-$(CONFIG_ATARI_DSP56K) += dsp56k.o 33 33 obj-$(CONFIG_MOXA_SMARTIO) += mxser.o 34 obj-$(CONFIG_SIBYTE_SB1250_DUART) += sb1250_duart.o 34 35 obj-$(CONFIG_COMPUTONE) += ip2/ 35 36 obj-$(CONFIG_RISCOM8) += riscom8.o 36 37 obj-$(CONFIG_ISI) += isicom.o … … 51 52 obj-$(CONFIG_VIOTAPE) += viotape.o 52 53 obj-$(CONFIG_HVCS) += hvcs.o 53 54 obj-$(CONFIG_SGI_MBCS) += mbcs.o 55 obj-$(CONFIG_SERIAL_DEC) += decserial.o 54 56 55 57 obj-$(CONFIG_PRINTER) += lp.o 56 58 obj-$(CONFIG_TIPAR) += tipar.o … … 78 80 obj-$(CONFIG_HW_RANDOM) += hw_random.o 79 81 obj-$(CONFIG_FTAPE) += ftape/ 80 82 obj-$(CONFIG_COBALT_LCD) += lcd.o 83 obj-$(CONFIG_ITE_GPIO) += ite_gpio.o 84 obj-$(CONFIG_AU1000_GPIO) += au1000_gpio.o 85 obj-$(CONFIG_AU1000_USB_TTY) += au1000_usbtty.o 86 obj-$(CONFIG_AU1000_USB_RAW) += au1000_usbraw.o 81 87 obj-$(CONFIG_PPDEV) += ppdev.o 82 88 obj-$(CONFIG_NWBUTTON) += nwbutton.o 83 89 obj-$(CONFIG_NWFLASH) += nwflash.o -
drivers/char/qtronix.c
diff -Naur linux-2.6.17.4-kernel/drivers/char/qtronix.c linux-2.6.17.4-mips/drivers/char/qtronix.c
old new 535 535 i--; 536 536 } 537 537 if (count-i) { 538 struct inode *inode = file->f_dentry->d_inode; 539 inode->i_atime = current_fs_time(inode->i_sb); 538 file->f_dentry->d_inode->i_atime = get_seconds(); 540 539 return count-i; 541 540 } 542 541 if (signal_pending(current)) -
drivers/char/rtc.c
diff -Naur linux-2.6.17.4-kernel/drivers/char/rtc.c linux-2.6.17.4-mips/drivers/char/rtc.c
old new 35 35 * 1.09a Pete Zaitcev: Sun SPARC 36 36 * 1.09b Jeff Garzik: Modularize, init cleanup 37 37 * 1.09c Jeff Garzik: SMP cleanup 38 * 1.10 38 * 1.10 Paul Barton-Davis: add support for async I/O 39 39 * 1.10a Andrea Arcangeli: Alpha updates 40 40 * 1.10b Andrew Morton: SMP lock fix 41 41 * 1.10c Cesar Barros: SMP locking fixes and cleanup 42 42 * 1.10d Paul Gortmaker: delete paranoia check in rtc_exit 43 43 * 1.10e Maciej W. Rozycki: Handle DECstation's year weirdness. 44 * 1.11Takashi Iwai: Kernel access functions44 * 1.11 Takashi Iwai: Kernel access functions 45 45 * rtc_register/rtc_unregister/rtc_control 46 46 * 1.11a Daniele Bellucci: Audit create_proc_read_entry in rtc_init 47 * 1.12 47 * 1.12 Venkatesh Pallipadi: Hooks for emulating rtc on HPET base-timer 48 48 * CONFIG_HPET_EMULATE_RTC 49 * 1.12a Maciej W. Rozycki: Handle memory-mapped chips properly. 49 50 * 1.12ac Alan Cox: Allow read access to the day of week register 50 51 */ 51 52 52 #define RTC_VERSION "1.12ac" 53 54 #define RTC_IO_EXTENT 0x8 53 #define RTC_VERSION "1.12a" 55 54 56 55 /* 57 56 * Note that *all* calls to CMOS_READ and CMOS_WRITE are done with … … 338 337 if (rtc_has_irq == 0) 339 338 return -EIO; 340 339 341 if (count < sizeof(unsigned)) 340 /* 341 * Historically this function used to assume that sizeof(unsigned long) 342 * is the same in userspace and kernelspace. This lead to problems 343 * for configurations with multiple ABIs such a the MIPS o32 and 64 344 * ABIs supported on the same kernel. So now we support read of both 345 * 4 and 8 bytes and assume that's the sizeof(unsigned long) in the 346 * userspace ABI. 347 */ 348 if (count != sizeof(unsigned int) && count != sizeof(unsigned long)) 342 349 return -EINVAL; 343 350 344 351 add_wait_queue(&rtc_wait, &wait); … … 369 376 schedule(); 370 377 } while (1); 371 378 372 if (count < sizeof(unsigned long))373 retval = put_user(data, (unsigned int __user *)buf) ?: sizeof(int); 379 if (count == sizeof(unsigned int)) 380 retval = put_user(data, (unsigned int __user *)buf) ?: sizeof(int); 374 381 else 375 382 retval = put_user(data, (unsigned long __user *)buf) ?: sizeof(long); 383 if (!retval) 384 retval = count; 376 385 out: 377 386 current->state = TASK_RUNNING; 378 387 remove_wait_queue(&rtc_wait, &wait); … … 924 933 struct sparc_isa_device *isa_dev; 925 934 #endif 926 935 #endif 936 #ifndef __sparc__ 937 void *r; 938 #endif 927 939 928 940 #ifdef __sparc__ 929 941 for_each_ebus(ebus) { … … 969 981 } 970 982 no_irq: 971 983 #else 972 if (!request_region(RTC_PORT(0), RTC_IO_EXTENT, "rtc")) { 973 printk(KERN_ERR "rtc: I/O port %d is not free.\n", RTC_PORT (0)); 984 if (RTC_IOMAPPED) 985 r = request_region(RTC_PORT(0), RTC_IO_EXTENT, "rtc"); 986 else 987 r = request_mem_region(RTC_PORT(0), RTC_IO_EXTENT, "rtc"); 988 if (!r) { 989 printk(KERN_ERR "rtc: I/O resource %lx is not free.\n", 990 (long)(RTC_PORT(0))); 974 991 return -EIO; 975 992 } 976 993 … … 984 1001 if(request_irq(RTC_IRQ, rtc_int_handler_ptr, SA_INTERRUPT, "rtc", NULL)) { 985 1002 /* Yeah right, seeing as irq 8 doesn't even hit the bus. */ 986 1003 printk(KERN_ERR "rtc: IRQ %d is not free.\n", RTC_IRQ); 987 release_region(RTC_PORT(0), RTC_IO_EXTENT); 1004 if (RTC_IOMAPPED) 1005 release_region(RTC_PORT(0), RTC_IO_EXTENT); 1006 else 1007 release_mem_region(RTC_PORT(0), RTC_IO_EXTENT); 988 1008 return -EIO; 989 1009 } 990 1010 hpet_rtc_timer_init(); … … 1084 1104 if (rtc_has_irq) 1085 1105 free_irq (rtc_irq, &rtc_port); 1086 1106 #else 1087 release_region (RTC_PORT (0), RTC_IO_EXTENT); 1107 if (RTC_IOMAPPED) 1108 release_region(RTC_PORT(0), RTC_IO_EXTENT); 1109 else 1110 release_mem_region(RTC_PORT(0), RTC_IO_EXTENT); 1088 1111 #ifdef RTC_IRQ 1089 1112 if (rtc_has_irq) 1090 1113 free_irq (RTC_IRQ, NULL); -
drivers/ide/mips/Makefile
diff -Naur linux-2.6.17.4-kernel/drivers/ide/mips/Makefile linux-2.6.17.4-mips/drivers/ide/mips/Makefile
old new 1 1 obj-$(CONFIG_BLK_DEV_IDE_SWARM) += swarm.o 2 2 obj-$(CONFIG_BLK_DEV_IDE_AU1XXX) += au1xxx-ide.o 3 3 4 EXTRA_CFLAGS:= -Idrivers/ide4 CFLAGS_au1xxx-ide.o := -Idrivers/ide -
drivers/mtd/devices/docprobe.c
diff -Naur linux-2.6.17.4-kernel/drivers/mtd/devices/docprobe.c linux-2.6.17.4-mips/drivers/mtd/devices/docprobe.c
old new 84 84 0xe4000000, 85 85 #elif defined(CONFIG_MOMENCO_OCELOT) 86 86 0x2f000000, 87 87 0xff000000, 88 88 #elif defined(CONFIG_MOMENCO_OCELOT_G) || defined (CONFIG_MOMENCO_OCELOT_C) 89 90 # #else89 0xff000000, 90 #else 91 91 #warning Unknown architecture for DiskOnChip. No default probe locations defined 92 92 #endif 93 93 0xffffffff }; -
drivers/mtd/devices/Kconfig
diff -Naur linux-2.6.17.4-kernel/drivers/mtd/devices/Kconfig linux-2.6.17.4-mips/drivers/mtd/devices/Kconfig
old new 47 47 accelerator. Say Y here if you have a DECstation 5000/2x0 or a 48 48 DECsystem 5900 equipped with such a module. 49 49 50 If you want to compile this driver as a module ( = code which can be 51 inserted in and removed from the running kernel whenever you want), 52 say M here and read <file:Documentation/modules.txt>. The module will 53 be called ms02-nv.o. 54 50 55 config MTD_DATAFLASH 51 56 tristate "Support for AT45xxx DataFlash" 52 57 depends on MTD && SPI_MASTER && EXPERIMENTAL -
drivers/mtd/maps/Kconfig
diff -Naur linux-2.6.17.4-kernel/drivers/mtd/maps/Kconfig linux-2.6.17.4-mips/drivers/mtd/maps/Kconfig
old new 200 200 Support for the flash chip on Tsunami TIG bus. 201 201 202 202 config MTD_LASAT 203 tristate " Flash chips on LASAT board"204 depends on LASAT 203 tristate "LASAT flash device" 204 depends on LASAT && MTD_CFI 205 205 help 206 206 Support for the flash chips on the Lasat 100 and 200 boards. 207 207 … … 299 299 Mapping for the Flaga digital module. If you don't have one, ignore 300 300 this setting. 301 301 302 config MTD_XXS1500 303 tristate "MyCable XXS1500 Flash device" 304 depends on MIPS && MIPS_XXS1500 305 help 306 Flash memory access on MyCable XXS1500 Board 307 308 config MTD_MTX1 309 tristate "4-G Systems MTX-1 Flash device" 310 depends on MIPS && MIPS_MTX1 311 help 312 Flash memory access on 4-G Systems MTX-1 Board 313 302 314 config MTD_BEECH 303 315 tristate "CFI Flash device mapped on IBM 405LP Beech" 304 316 depends on MTD_CFI && BEECH -
drivers/mtd/maps/lasat.c
diff -Naur linux-2.6.17.4-kernel/drivers/mtd/maps/lasat.c linux-2.6.17.4-mips/drivers/mtd/maps/lasat.c
old new 7 7 * modify it under the terms of the GNU General Public License version 8 8 * 2 as published by the Free Software Foundation. 9 9 * 10 * $Id: lasat.c,v 1. 9 2004/11/04 13:24:15 gleixnerExp $10 * $Id: lasat.c,v 1.7 2004/07/12 21:59:44 dwmw2 Exp $ 11 11 * 12 12 */ 13 13 … … 50 50 ENABLE_VPP((&lasat_map)); 51 51 52 52 lasat_map.phys = lasat_flash_partition_start(LASAT_MTD_BOOTLOADER); 53 lasat_map.virt = ioremap_nocache(53 lasat_map.virt = (unsigned long)ioremap_nocache( 54 54 lasat_map.phys, lasat_board_info.li_flash_size); 55 55 lasat_map.size = lasat_board_info.li_flash_size; 56 56 -
drivers/net/declance.c
diff -Naur linux-2.6.17.4-kernel/drivers/net/declance.c linux-2.6.17.4-mips/drivers/net/declance.c
old new 704 704 return IRQ_HANDLED; 705 705 } 706 706 707 static irqreturn_t 708 lance_interrupt(const int irq, void *dev_id,struct pt_regs *regs)707 static irqreturn_t lance_interrupt(const int irq, void *dev_id, 708 struct pt_regs *regs) 709 709 { 710 710 struct net_device *dev = (struct net_device *) dev_id; 711 711 struct lance_private *lp = netdev_priv(dev); … … 1255 1255 return 0; 1256 1256 1257 1257 err_out_free_dev: 1258 kfree(dev);1258 free_netdev(dev); 1259 1259 1260 1260 err_out: 1261 1261 return ret; … … 1301 1301 while (root_lance_dev) { 1302 1302 struct net_device *dev = root_lance_dev; 1303 1303 struct lance_private *lp = netdev_priv(dev); 1304 1304 1305 unregister_netdev(dev); 1305 1306 #ifdef CONFIG_TC 1306 1307 if (lp->slot >= 0) -
drivers/net/gt64240eth.h
diff -Naur linux-2.6.17.4-kernel/drivers/net/gt64240eth.h linux-2.6.17.4-mips/drivers/net/gt64240eth.h
old new 9 9 * Copyright 2000 MontaVista Software Inc. 10 10 * Author: MontaVista Software, Inc. 11 11 * stevel@mvista.com or support@mvista.com 12 * Copyright 2004, 05 Ralf Baechle (ralf@linux-mips.org) 12 13 * 13 14 * This program is free software; you can distribute it and/or modify it 14 15 * under the terms of the GNU General Public License (Version 2) as … … 31 32 #ifndef _GT64240ETH_H 32 33 #define _GT64240ETH_H 33 34 35 #include <linux/config.h> 34 36 #include <asm/gt64240.h> 35 37 36 38 #define ETHERNET_PORTS_DIFFERENCE_OFFSETS 0x400 … … 108 110 #define REV_GT64240A 0x10 109 111 110 112 #define GT64240ETH_READ(gp, offset) \ 111 GT_READ((gp)->port_offset + (offset))113 MV_READ((gp)->port_offset + (offset)) 112 114 113 115 #define GT64240ETH_WRITE(gp, offset, data) \ 114 GT_WRITE((gp)->port_offset + (offset), (data))116 MV_WRITE((gp)->port_offset + (offset), (data)) 115 117 116 118 #define GT64240ETH_SETBIT(gp, offset, bits) \ 117 119 GT64240ETH_WRITE((gp), (offset), \ … … 121 123 GT64240ETH_WRITE((gp), (offset), \ 122 124 GT64240ETH_READ((gp), (offset)) & ~(bits)) 123 125 124 #define GT64240_READ(ofs) GT_READ(ofs)125 #define GT64240_WRITE(ofs, data) GT_WRITE((ofs), (data))126 #define GT64240_READ(ofs) MV_READ(ofs) 127 #define GT64240_WRITE(ofs, data) MV_WRITE((ofs), (data)) 126 128 127 129 /* Bit definitions of the SMI Reg */ 128 130 enum { -
drivers/net/Kconfig
diff -Naur linux-2.6.17.4-kernel/drivers/net/Kconfig linux-2.6.17.4-mips/drivers/net/Kconfig
old new 438 438 This is the driver for the onboard card of MIPS Magnum 4000, 439 439 Acer PICA, Olivetti M700-10 and a few other identical OEM systems. 440 440 441 config GALILEO_64240_ETH 442 tristate "Galileo GT64240 Ethernet support" 443 depends on NET_ETHERNET && MOMENCO_OCELOT_G 444 select MII 445 help 446 This is the driver for the ethernet interfaces integrated into 447 the Galileo (now Marvell) GT64240 chipset. 448 441 449 config MIPS_GT96100ETH 442 450 bool "MIPS GT96100 Ethernet support" 443 451 depends on NET_ETHERNET && MIPS_GT96100 … … 452 460 If you have an Alchemy Semi AU1X00 based system 453 461 say Y. Otherwise, say N. 454 462 455 config NET_SB1250_MAC456 tristate "SB1250 Ethernet support"457 depends on NET_ETHERNET && SIBYTE_SB1xxx_SOC458 459 463 config SGI_IOC3_ETH 460 464 bool "SGI IOC3 Ethernet" 461 465 depends on NET_ETHERNET && PCI && SGI_IP27 … … 494 498 emulated by the MIPS Simulator. 495 499 If you are not using a MIPSsim or are unsure, say N. 496 500 501 config MIPS_SIM_NET 502 tristate "MIPS simulator Network device (EXPERIMENTAL)" 503 depends on NETDEVICES && MIPS_SIM && EXPERIMENTAL 504 help 505 The MIPSNET device is a simple Ethernet network device which is 506 emulated by the MIPS Simulator. 507 If you are not using a MIPSsim or are unsure, say N. 508 497 509 config SGI_O2MACE_ETH 498 510 tristate "SGI O2 MACE Fast Ethernet support" 499 511 depends on NET_ETHERNET && SGI_IP32=y … … 1993 2005 1994 2006 If in doubt, say N. 1995 2007 2008 config NET_SB1250_MAC 2009 tristate "SB1250 Ethernet support" 2010 depends on SIBYTE_SB1xxx_SOC 2011 1996 2012 config R8169_VLAN 1997 2013 bool "VLAN support" 1998 2014 depends on R8169 && VLAN_8021Q … … 2195 2211 select MII 2196 2212 help 2197 2213 This driver supports the gigabit Ethernet on the Marvell MV643XX 2198 chipset which is used in the Momenco Ocelot C and Jaguar ATX and2199 Pegasos II, amongst other PPC and MIPS boards.2214 chipset which is used in the Momenco Ocelot C Ocelot, Jaguar ATX 2215 and Pegasos II, amongst other PPC and MIPS boards. 2200 2216 2201 2217 config MV643XX_ETH_0 2202 2218 bool "MV-643XX Port 0" … … 2219 2235 This enables support for Port 2 of the Marvell MV643XX Gigabit 2220 2236 Ethernet. 2221 2237 2238 config BIG_SUR_FE 2239 bool "PMC-Sierra TITAN Fast Ethernet Support" 2240 depends on NET_ETHERNET && PMC_BIG_SUR 2241 help 2242 This enables support for the the integrated ethernet of 2243 PMC-Sierra's Big Sur SoC. 2244 2245 config TITAN_GE 2246 bool "PMC-Sierra TITAN Gigabit Ethernet Support" 2247 depends on PMC_YOSEMITE 2248 help 2249 This enables support for the the integrated ethernet of 2250 PMC-Sierra's Titan SoC. 2251 2222 2252 endmenu 2223 2253 2224 2254 # -
drivers/net/Makefile
diff -Naur linux-2.6.17.4-kernel/drivers/net/Makefile linux-2.6.17.4-mips/drivers/net/Makefile
old new 111 111 112 112 obj-$(CONFIG_MV643XX_ETH) += mv643xx_eth.o 113 113 114 obj-$(CONFIG_GALILEO_64240_ETH) += gt64240eth.o 115 obj-$(CONFIG_MV64340_ETH) += mv64340_eth.o 116 obj-$(CONFIG_BIG_SUR_FE) += big_sur_ge.o 117 obj-$(CONFIG_TITAN_GE) += titan_mdio.o titan_ge.o 118 114 119 obj-$(CONFIG_PPP) += ppp_generic.o slhc.o 115 120 obj-$(CONFIG_PPP_ASYNC) += ppp_async.o 116 121 obj-$(CONFIG_PPP_SYNC_TTY) += ppp_synctty.o -
drivers/net/sb1250-mac.c
diff -Naur linux-2.6.17.4-kernel/drivers/net/sb1250-mac.c linux-2.6.17.4-mips/drivers/net/sb1250-mac.c
old new 156 156 157 157 #define NUMCACHEBLKS(x) (((x)+SMP_CACHE_BYTES-1)/SMP_CACHE_BYTES) 158 158 159 #define SBMAC_READCSR(t) __raw_readq((unsigned long)t) 160 #define SBMAC_WRITECSR(t,v) __raw_writeq(v, (unsigned long)t) 161 162 159 163 #define SBMAC_MAX_TXDESCR 32 160 164 #define SBMAC_MAX_RXDESCR 32 161 165 … … 2416 2420 sc->sbm_dev->name); 2417 2421 } 2418 2422 2423 if (periph_rev >= 2) { 2424 printk(KERN_INFO "%s: enabling TCP rcv checksum\n", 2425 sc->sbm_dev->name); 2426 } 2427 2419 2428 /* 2420 2429 * Display Ethernet address (this is called during the config 2421 2430 * process so we need to finish off the config message that -
drivers/scsi/dec_esp.c
diff -Naur linux-2.6.17.4-kernel/drivers/scsi/dec_esp.c linux-2.6.17.4-mips/drivers/scsi/dec_esp.c
old new 55 55 56 56 static int dma_bytes_sent(struct NCR_ESP *esp, int fifo_count); 57 57 static void dma_drain(struct NCR_ESP *esp); 58 static int dma_can_transfer(struct NCR_ESP *esp, struct scsi_cmnd * sp);58 static int dma_can_transfer(struct NCR_ESP *esp, struct scsi_cmnd * sp); 59 59 static void dma_dump_state(struct NCR_ESP *esp); 60 60 static void dma_init_read(struct NCR_ESP *esp, u32 vaddress, int length); 61 61 static void dma_init_write(struct NCR_ESP *esp, u32 vaddress, int length); … … 230 230 mem_start = get_tc_base_addr(slot); 231 231 232 232 /* Store base addr into esp struct */ 233 esp->slot = CPHYSADDR(mem_start);233 esp->slot = mem_start; 234 234 235 235 esp->dregs = 0; 236 236 esp->eregs = (void *)CKSEG1ADDR(mem_start + -
drivers/scsi/NCR53C9x.h
diff -Naur linux-2.6.17.4-kernel/drivers/scsi/NCR53C9x.h linux-2.6.17.4-mips/drivers/scsi/NCR53C9x.h
old new 145 145 146 146 #ifndef MULTIPLE_PAD_SIZES 147 147 148 #ifdef CONFIG_CPU_HAS_WB 149 #include <asm/wbflush.h> 150 #define esp_write(__reg, __val) do{(__reg) = (__val); wbflush();} while(0) 151 #else 152 #define esp_write(__reg, __val) ((__reg) = (__val)) 153 #endif 148 #define esp_write(__reg, __val) do{(__reg) = (__val); iob();} while(0) 154 149 #define esp_read(__reg) (__reg) 155 150 156 151 struct ESP_regs { -
drivers/scsi/sgiwd93.c
diff -Naur linux-2.6.17.4-kernel/drivers/scsi/sgiwd93.c linux-2.6.17.4-mips/drivers/scsi/sgiwd93.c
old new 14 14 #include <linux/interrupt.h> 15 15 #include <linux/types.h> 16 16 #include <linux/mm.h> 17 #include <linux/module.h> 17 18 #include <linux/blkdev.h> 18 19 #include <linux/delay.h> 19 20 #include <linux/dma-mapping.h> … … 197 198 udelay(50); 198 199 hregs->ctrl = 0; 199 200 } 201 EXPORT_SYMBOL_GPL(sgiwd93_reset); 200 202 201 203 static inline void init_hpc_chain(struct hpc_data *hd) 202 204 { -
drivers/serial/ip22zilog.c
diff -Naur linux-2.6.17.4-kernel/drivers/serial/ip22zilog.c linux-2.6.17.4-mips/drivers/serial/ip22zilog.c
old new 866 866 up->cflag = termios->c_cflag; 867 867 868 868 ip22zilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port)); 869 uart_update_timeout(port, termios->c_cflag, baud); 869 870 870 871 spin_unlock_irqrestore(&up->port.lock, flags); 871 872 } … … 1027 1028 } 1028 1029 1029 1030 con->cflag = cflag | CS8; /* 8N1 */ 1031 1032 uart_update_timeout(&ip22zilog_port_table[con->index].port, cflag, baud); 1030 1033 } 1031 1034 1032 1035 static int __init ip22zilog_console_setup(struct console *con, char *options) -
drivers/serial/Kconfig
diff -Naur linux-2.6.17.4-kernel/drivers/serial/Kconfig linux-2.6.17.4-mips/drivers/serial/Kconfig
old new 647 647 depends on SERIAL_SH_SCI=y 648 648 select SERIAL_CORE_CONSOLE 649 649 650 config SERIAL_IP3106 651 bool "Enable IP3106 UART Support (Philips PNX 8xx0 SoCs)" 652 depends on MIPS && (SOC_PNX8550 || SOC_PNX8330) 653 select SERIAL_CORE 654 help 655 If you have a Philips SoC with an IP 3106 UART in it, such as 656 the PNX8550 or PNX8330 (MIPS based) and you want to use 657 serial ports, say Y. Otherwise, say N. 658 659 config SERIAL_IP3106_CONSOLE 660 bool "Enable PNX8XX0 serial console" 661 depends on SERIAL_IP3106 662 select SERIAL_CORE_CONSOLE 663 help 664 If you have a Philips SoC with an IP 3106 UART in it, such as 665 the PNX8550 or PNX8330 (MIPS based) and you want to use 666 a serial console, say Y. 667 Otherwise, say N. 668 650 669 config SERIAL_CORE 651 670 tristate 652 671 -
drivers/serial/Makefile
diff -Naur linux-2.6.17.4-kernel/drivers/serial/Makefile linux-2.6.17.4-mips/drivers/serial/Makefile
old new 39 39 obj-$(CONFIG_V850E_UART) += v850e_uart.o 40 40 obj-$(CONFIG_SERIAL_PMACZILOG) += pmac_zilog.o 41 41 obj-$(CONFIG_SERIAL_LH7A40X) += serial_lh7a40x.o 42 obj-$(CONFIG_SERIAL_IP3106) += ip3106_uart.o 42 43 obj-$(CONFIG_SERIAL_DZ) += dz.o 43 44 obj-$(CONFIG_SERIAL_SH_SCI) += sh-sci.o 44 45 obj-$(CONFIG_SERIAL_SGI_L1_CONSOLE) += sn_console.o -
drivers/usb/gadget/net2280.c
diff -Naur linux-2.6.17.4-kernel/drivers/usb/gadget/net2280.c linux-2.6.17.4-mips/drivers/usb/gadget/net2280.c
old new 468 468 #elif defined(CONFIG_PPC) && !defined(CONFIG_NOT_COHERENT_CACHE) 469 469 #define USE_KMALLOC 470 470 471 #elif defined(CONFIG_MIPS) && !defined(CONFIG_DMA_NONCOHERENT) 471 #elif defined(CONFIG_MIPS) && \ 472 (defined(CONFIG_DMA_COHERENT) || defined(CONFIG_DMA_IP27)) 472 473 #define USE_KMALLOC 473 474 474 475 /* FIXME there are other cases, including an x86-64 one ... */ -
drivers/usb/host/ohci-hcd.c
diff -Naur linux-2.6.17.4-kernel/drivers/usb/host/ohci-hcd.c linux-2.6.17.4-mips/drivers/usb/host/ohci-hcd.c
old new 906 906 #include "ohci-au1xxx.c" 907 907 #endif 908 908 909 #ifdef CONFIG_PNX8550 910 #include "ohci-pnx8550.c" 911 #endif 912 909 913 #ifdef CONFIG_USB_OHCI_HCD_PPC_SOC 910 914 #include "ohci-ppc-soc.c" 911 915 #endif -
drivers/video/au1100fb.c
diff -Naur linux-2.6.17.4-kernel/drivers/video/au1100fb.c linux-2.6.17.4-mips/drivers/video/au1100fb.c
old new 38 38 * with this program; if not, write to the Free Software Foundation, Inc., 39 39 * 675 Mass Ave, Cambridge, MA 02139, USA. 40 40 */ 41 41 42 #include <linux/config.h> 42 43 #include <linux/module.h> 43 44 #include <linux/kernel.h> -
drivers/video/Kconfig
diff -Naur linux-2.6.17.4-kernel/drivers/video/Kconfig linux-2.6.17.4-mips/drivers/video/Kconfig
old new 1142 1142 Please read the <file:Documentation/fb/README-sstfb.txt> for supported 1143 1143 options and other important info support. 1144 1144 1145 config FB_SMIVGX 1146 tristate "Silicon Motion VoyagerGX support" 1147 depends on FB && PCI && (MIPS || EXPERIMENTAL) 1148 select FB_CFB_FILLRECT 1149 select FB_CFB_COPYAREA 1150 select FB_CFB_IMAGEBLIT 1151 ---help--- 1152 This drivers supports SMI VoyagerGX 501 based PCI boards 1153 The default settings drive both a CRT and LCD. The CRT 1154 can be turned off by passing in the no_crt option 1155 1145 1156 config FB_CYBLA 1146 1157 tristate "Cyberblade/i1 support" 1147 1158 depends on FB && PCI && X86_32 && !64BIT … … 1206 1217 1207 1218 config FB_AU1100 1208 1219 bool "Au1100 LCD Driver" 1209 depends on (FB = y) && EXPERIMENTAL && PCI && MIPS && MIPS_PB1100=y 1220 depends on FB && MIPS && SOC_AU1100 1221 select FB_CFB_FILLRECT 1222 select FB_CFB_COPYAREA 1223 select FB_CFB_IMAGEBLIT 1224 help 1225 This is the framebuffer driver for the AMD Au1100 SOC. It can drive 1226 various panels and CRTs by passing in kernel cmd line option 1227 au1100fb:panel=<name>. 1228 1229 config FB_AU1200 1230 bool "Au1200 LCD Driver" 1231 depends on FB && MIPS && SOC_AU1200 1232 select FB_CFB_FILLRECT 1233 select FB_CFB_COPYAREA 1234 select FB_CFB_IMAGEBLIT 1235 help 1236 This is the framebuffer driver for the AMD Au1200 SOC. It can drive 1237 various panels and CRTs by passing in kernel cmd line option 1238 au1200fb:panel=<name>. 1210 1239 1211 1240 config FB_AU1200 1212 1241 bool "Au1200 LCD Driver" … … 1322 1351 select FB_CFB_IMAGEBLIT 1323 1352 help 1324 1353 Support for the PMAGB-B TURBOchannel framebuffer card used mainly 1325 in the MIPS-based DECstation series. The card is currently only 1326 supported in 1280x1024x8 mode. 1354 in the MIPS-based DECstation series. The card is currently only 1355 supported in 1280x1024x8 mode. 1327 1356 1328 1357 config FB_MAXINE 1329 1358 bool "Maxine (Personal DECstation) onboard framebuffer support" -
drivers/video/Makefile
diff -Naur linux-2.6.17.4-kernel/drivers/video/Makefile linux-2.6.17.4-mips/drivers/video/Makefile
old new 93 93 obj-$(CONFIG_FB_TX3912) += tx3912fb.o 94 94 obj-$(CONFIG_FB_S1D13XXX) += s1d13xxxfb.o 95 95 obj-$(CONFIG_FB_IMX) += imxfb.o 96 obj-$(CONFIG_FB_SMIVGX) += smivgxfb.o 96 97 obj-$(CONFIG_FB_S3C2410) += s3c2410fb.o 97 98 98 99 # Platform or fallback drivers go here -
include/asm-mips/asmmacro-32.h
diff -Naur linux-2.6.17.4-kernel/include/asm-mips/asmmacro-32.h linux-2.6.17.4-mips/include/asm-mips/asmmacro-32.h
old new 12 12 #include <asm/fpregdef.h> 13 13 #include <asm/mipsregs.h> 14 14 15 .macro fpu_save_double thread status tmp1=t0 tmp215 .macro fpu_save_double thread status tmp1=t0 16 16 cfc1 \tmp1, fcr31 17 17 sdc1 $f0, THREAD_FPR0(\thread) 18 18 sdc1 $f2, THREAD_FPR2(\thread) … … 70 70 sw \tmp, THREAD_FCR31(\thread) 71 71 .endm 72 72 73 .macro fpu_restore_double thread tmp=t073 .macro fpu_restore_double thread status tmp=t0 74 74 lw \tmp, THREAD_FCR31(\thread) 75 75 ldc1 $f0, THREAD_FPR0(\thread) 76 76 ldc1 $f2, THREAD_FPR2(\thread) -
include/asm-mips/asmmacro-64.h
diff -Naur linux-2.6.17.4-kernel/include/asm-mips/asmmacro-64.h linux-2.6.17.4-mips/include/asm-mips/asmmacro-64.h
old new 53 53 sdc1 $f31, THREAD_FPR31(\thread) 54 54 .endm 55 55 56 .macro fpu_save_double thread status tmp 1 tmp257 sll \tmp 2, \tmp1, 558 bgez \tmp 2, 2f56 .macro fpu_save_double thread status tmp 57 sll \tmp, \status, 5 58 bgez \tmp, 2f 59 59 fpu_save_16odd \thread 60 60 2: 61 fpu_save_16even \thread \tmp 1 # clobbers t161 fpu_save_16even \thread \tmp 62 62 .endm 63 63 64 64 .macro fpu_restore_16even thread tmp=t0 … … 101 101 ldc1 $f31, THREAD_FPR31(\thread) 102 102 .endm 103 103 104 .macro fpu_restore_double thread tmp 105 mfc0 t0, CP0_STATUS 106 sll t1, t0, 5 107 bgez t1, 1f # 16 register mode? 104 .macro fpu_restore_double thread status tmp 105 sll \tmp, \status, 5 106 bgez \tmp, 1f # 16 register mode? 108 107 109 fpu_restore_16odd a0110 1: fpu_restore_16even a0, t0 # clobbers t0108 fpu_restore_16odd \thread 109 1: fpu_restore_16even \thread \tmp 111 110 .endm 112 111 113 112 .macro cpu_save_nonscratch thread -
include/asm-mips/asmmacro.h
diff -Naur linux-2.6.17.4-kernel/include/asm-mips/asmmacro.h linux-2.6.17.4-mips/include/asm-mips/asmmacro.h
old new 27 27 ori \reg, \reg, TCSTATUS_IXMT 28 28 xori \reg, \reg, TCSTATUS_IXMT 29 29 mtc0 \reg, CP0_TCSTATUS 30 ehb30 _ehb 31 31 .endm 32 32 33 33 .macro local_irq_disable reg=t0 34 34 mfc0 \reg, CP0_TCSTATUS 35 35 ori \reg, \reg, TCSTATUS_IXMT 36 36 mtc0 \reg, CP0_TCSTATUS 37 ehb37 _ehb 38 38 .endm 39 39 #else 40 40 .macro local_irq_enable reg=t0 -
include/asm-mips/cpu-features.h
diff -Naur linux-2.6.17.4-kernel/include/asm-mips/cpu-features.h linux-2.6.17.4-mips/include/asm-mips/cpu-features.h
old new 144 144 #define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) 145 145 #endif 146 146 147 #ifdef CONFIG_MIPS_MT148 147 #ifndef cpu_has_mipsmt 149 # define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT) 150 #endif 151 #else 152 # define cpu_has_mipsmt 0 148 #define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT) 153 149 #endif 154 150 155 151 #ifdef CONFIG_32BIT … … 188 184 # endif 189 185 #endif 190 186 191 #ifdef CONFIG_CPU_MIPSR2 192 # if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint) 193 # define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT) 194 # else 195 # define cpu_has_vint 0 196 # endif 197 # if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic) 198 # define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC) 199 # else 200 # define cpu_has_veic 0 201 # endif 202 #else 187 #if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint) 188 # define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT) 189 #elif !defined(cpu_has_vint) 203 190 # define cpu_has_vint 0 191 #endif 192 193 #if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic) 194 # define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC) 195 #elif !defined(cpu_has_veic) 204 196 # define cpu_has_veic 0 205 197 #endif 206 198 -
include/asm-mips/futex.h
diff -Naur linux-2.6.17.4-kernel/include/asm-mips/futex.h linux-2.6.17.4-mips/include/asm-mips/futex.h
old new 22 22 " .set push \n" \ 23 23 " .set noat \n" \ 24 24 " .set mips3 \n" \ 25 "1: ll %1, (%3) # __futex_atomic_op \n"\25 "1: ll %1, %4 # __futex_atomic_op \n" \ 26 26 " .set mips0 \n" \ 27 27 " " insn " \n" \ 28 28 " .set mips3 \n" \ 29 "2: sc $1, (%3)\n" \29 "2: sc $1, %2 \n" \ 30 30 " beqzl $1, 1b \n" \ 31 31 __FUTEX_SMP_SYNC \ 32 32 "3: \n" \ 33 33 " .set pop \n" \ 34 34 " .set mips0 \n" \ 35 35 " .section .fixup,\"ax\" \n" \ 36 "4: li %0, % 5\n" \36 "4: li %0, %6 \n" \ 37 37 " j 2b \n" \ 38 38 " .previous \n" \ 39 39 " .section __ex_table,\"a\" \n" \ 40 40 " "__UA_ADDR "\t1b, 4b \n" \ 41 41 " "__UA_ADDR "\t2b, 4b \n" \ 42 42 " .previous \n" \ 43 : "=r" (ret), "=r" (oldval) \ 44 : "0" (0), "r" (uaddr), "Jr" (oparg), "i" (-EFAULT)); \ 43 : "=r" (ret), "=&r" (oldval), "=R" (*uaddr) \ 44 : "0" (0), "R" (*uaddr), "Jr" (oparg), "i" (-EFAULT) \ 45 : "memory"); \ 45 46 } else if (cpu_has_llsc) { \ 46 47 __asm__ __volatile__( \ 47 48 " .set push \n" \ 48 49 " .set noat \n" \ 49 50 " .set mips3 \n" \ 50 "1: ll %1, (%3) # __futex_atomic_op \n"\51 "1: ll %1, %4 # __futex_atomic_op \n" \ 51 52 " .set mips0 \n" \ 52 53 " " insn " \n" \ 53 54 " .set mips3 \n" \ 54 "2: sc $1, (%3)\n" \55 "2: sc $1, %2 \n" \ 55 56 " beqz $1, 1b \n" \ 56 57 __FUTEX_SMP_SYNC \ 57 58 "3: \n" \ 58 59 " .set pop \n" \ 59 60 " .set mips0 \n" \ 60 61 " .section .fixup,\"ax\" \n" \ 61 "4: li %0, % 5\n" \62 "4: li %0, %6 \n" \ 62 63 " j 2b \n" \ 63 64 " .previous \n" \ 64 65 " .section __ex_table,\"a\" \n" \ 65 66 " "__UA_ADDR "\t1b, 4b \n" \ 66 67 " "__UA_ADDR "\t2b, 4b \n" \ 67 68 " .previous \n" \ 68 : "=r" (ret), "=r" (oldval) \ 69 : "0" (0), "r" (uaddr), "Jr" (oparg), "i" (-EFAULT)); \ 69 : "=r" (ret), "=&r" (oldval), "=R" (*uaddr) \ 70 : "0" (0), "R" (*uaddr), "Jr" (oparg), "i" (-EFAULT) \ 71 : "memory"); \ 70 72 } else \ 71 73 ret = -ENOSYS; \ 72 74 } … … 89 91 90 92 switch (op) { 91 93 case FUTEX_OP_SET: 92 __futex_atomic_op("move $1, %z 4", ret, oldval, uaddr, oparg);94 __futex_atomic_op("move $1, %z5", ret, oldval, uaddr, oparg); 93 95 break; 94 96 95 97 case FUTEX_OP_ADD: 96 __futex_atomic_op("addu $1, %1, %z 4",98 __futex_atomic_op("addu $1, %1, %z5", 97 99 ret, oldval, uaddr, oparg); 98 100 break; 99 101 case FUTEX_OP_OR: 100 __futex_atomic_op("or $1, %1, %z 4",102 __futex_atomic_op("or $1, %1, %z5", 101 103 ret, oldval, uaddr, oparg); 102 104 break; 103 105 case FUTEX_OP_ANDN: 104 __futex_atomic_op("and $1, %1, %z 4",106 __futex_atomic_op("and $1, %1, %z5", 105 107 ret, oldval, uaddr, ~oparg); 106 108 break; 107 109 case FUTEX_OP_XOR: 108 __futex_atomic_op("xor $1, %1, %z 4",110 __futex_atomic_op("xor $1, %1, %z5", 109 111 ret, oldval, uaddr, oparg); 110 112 break; 111 113 default: -
include/asm-mips/hazards.h
diff -Naur linux-2.6.17.4-kernel/include/asm-mips/hazards.h linux-2.6.17.4-mips/include/asm-mips/hazards.h
old new 70 70 * Use a macro for ehb unless explicit support for MIPSR2 is enabled 71 71 */ 72 72 73 #define irq_enable_hazard 73 #define irq_enable_hazard \ 74 74 _ehb 75 75 76 #define irq_disable_hazard 76 #define irq_disable_hazard \ 77 77 _ehb 78 78 79 79 #elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) -
include/asm-mips/io.h
diff -Naur linux-2.6.17.4-kernel/include/asm-mips/io.h linux-2.6.17.4-mips/include/asm-mips/io.h
old new 519 519 } 520 520 521 521 /* 522 * Memory Mapped I/O523 */524 #define ioread8(addr) readb(addr)525 #define ioread16(addr) readw(addr)526 #define ioread32(addr) readl(addr)527 528 #define iowrite8(b,addr) writeb(b,addr)529 #define iowrite16(w,addr) writew(w,addr)530 #define iowrite32(l,addr) writel(l,addr)531 532 #define ioread8_rep(a,b,c) readsb(a,b,c)533 #define ioread16_rep(a,b,c) readsw(a,b,c)534 #define ioread32_rep(a,b,c) readsl(a,b,c)535 536 #define iowrite8_rep(a,b,c) writesb(a,b,c)537 #define iowrite16_rep(a,b,c) writesw(a,b,c)538 #define iowrite32_rep(a,b,c) writesl(a,b,c)539 540 /* Create a virtual mapping cookie for an IO port range */541 extern void __iomem *ioport_map(unsigned long port, unsigned int nr);542 extern void ioport_unmap(void __iomem *);543 544 /* Create a virtual mapping cookie for a PCI BAR (memory or IO) */545 struct pci_dev;546 extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);547 extern void pci_iounmap(struct pci_dev *dev, void __iomem *);548 549 /*550 522 * ISA space is 'always mapped' on currently supported MIPS systems, no need 551 523 * to explicitly ioremap() it. The fact that the ISA IO space is mapped 552 524 * to PAGE_OFFSET is pure coincidence - it does not mean ISA values -
include/asm-mips/irq.h
diff -Naur linux-2.6.17.4-kernel/include/asm-mips/irq.h linux-2.6.17.4-mips/include/asm-mips/irq.h
old new 77 77 unsigned long hwmask); 78 78 #endif /* CONFIG_MIPS_MT_SMTC */ 79 79 80 #ifdef CONFIG_SMP 81 #define ARCH_HAS_IRQ_PER_CPU 82 #endif 83 80 84 #endif /* _ASM_IRQ_H */ -
include/asm-mips/mach-au1x00/au1xxx_ide.h
diff -Naur linux-2.6.17.4-kernel/include/asm-mips/mach-au1x00/au1xxx_ide.h linux-2.6.17.4-mips/include/asm-mips/mach-au1x00/au1xxx_ide.h
old new 84 84 } _auide_hwif; 85 85 86 86 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA 87 87 88 /* HD white list */ 88 89 static const struct drive_list_entry dma_white_list [] = { 89 90 /* -
include/asm-mips/mach-mips/irq.h
diff -Naur linux-2.6.17.4-kernel/include/asm-mips/mach-mips/irq.h linux-2.6.17.4-mips/include/asm-mips/mach-mips/irq.h
old new 5 5 6 6 #define NR_IRQS 256 7 7 8 #ifdef CONFIG_SMP9 10 #define ARCH_HAS_IRQ_PER_CPU11 12 #endif13 14 8 #endif /* __ASM_MACH_MIPS_IRQ_H */ -
include/asm-mips/mipsregs.h
diff -Naur linux-2.6.17.4-kernel/include/asm-mips/mipsregs.h linux-2.6.17.4-mips/include/asm-mips/mipsregs.h
old new 1462 1462 static inline void __ehb(void) 1463 1463 { 1464 1464 __asm__ __volatile__( 1465 " ehb \n"); 1465 " .set mips32r2 \n" 1466 " ehb \n" " .set mips0 \n"); 1466 1467 } 1467 1468 1468 1469 /* -
include/asm-mips/smp.h
diff -Naur linux-2.6.17.4-kernel/include/asm-mips/smp.h linux-2.6.17.4-mips/include/asm-mips/smp.h
old new 114 114 115 115 #endif /* CONFIG_SMP */ 116 116 117 int smp_call_function(void(*func)(void *info), void *info, int retry, int wait); 118 119 /* 120 * Special Variant of smp_call_function for use by cache functions: 121 * 122 * o No return value 123 * o collapses to normal function call on UP kernels 124 * o collapses to normal function call on systems with a single shared 125 * primary cache. 126 * o Both CONFIG_MIPS_MT_SMP and CONFIG_MIPS_MT_SMTC currently imply there 127 * is only one physical core. 128 */ 129 static inline void __on_other_cores(void (*func) (void *info), void *info) 130 { 131 #if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC) 132 smp_call_function(func, info, 1, 1); 133 #endif 134 } 135 136 static inline void __on_each_core(void (*func) (void *info), void *info) 137 { 138 preempt_disable(); 139 140 __on_other_cores(func, info); 141 func(info); 142 143 preempt_enable(); 144 } 145 117 146 #endif /* __ASM_SMP_H */ -
include/asm-mips/stackframe.h
diff -Naur linux-2.6.17.4-kernel/include/asm-mips/stackframe.h linux-2.6.17.4-mips/include/asm-mips/stackframe.h
old new 305 305 mfc0 v0, CP0_TCSTATUS 306 306 ori v0, TCSTATUS_IXMT 307 307 mtc0 v0, CP0_TCSTATUS 308 ehb308 _ehb 309 309 DMT 5 # dmt a1 310 310 jal mips_ihb 311 311 #endif /* CONFIG_MIPS_MT_SMTC */ … … 326 326 * restore TCStatus.IXMT. 327 327 */ 328 328 LONG_L v1, PT_TCSTATUS(sp) 329 ehb329 _ehb 330 330 mfc0 v0, CP0_TCSTATUS 331 331 andi v1, TCSTATUS_IXMT 332 332 /* We know that TCStatua.IXMT should be set from above */ 333 333 xori v0, v0, TCSTATUS_IXMT 334 334 or v0, v0, v1 335 335 mtc0 v0, CP0_TCSTATUS 336 ehb336 _ehb 337 337 andi a1, a1, VPECONTROL_TE 338 338 beqz a1, 1f 339 339 emt … … 412 412 /* Clear TKSU, leave IXMT */ 413 413 xori t0, 0x00001800 414 414 mtc0 t0, CP0_TCSTATUS 415 ehb415 _ehb 416 416 /* We need to leave the global IE bit set, but clear EXL...*/ 417 417 mfc0 t0, CP0_STATUS 418 418 ori t0, ST0_EXL | ST0_ERL … … 439 439 * and enable interrupts only for the 440 440 * current TC, using the TCStatus register. 441 441 */ 442 ehb442 _ehb 443 443 mfc0 t0,CP0_TCSTATUS 444 444 /* Fortunately CU 0 is in the same place in both registers */ 445 445 /* Set TCU0, TKSU (for later inversion) and IXMT */ … … 448 448 /* Clear TKSU *and* IXMT */ 449 449 xori t0, 0x00001c00 450 450 mtc0 t0, CP0_TCSTATUS 451 ehb451 _ehb 452 452 /* We need to leave the global IE bit set, but clear EXL...*/ 453 453 mfc0 t0, CP0_STATUS 454 454 ori t0, ST0_EXL … … 480 480 andi v1, v0, TCSTATUS_IXMT 481 481 ori v0, TCSTATUS_IXMT 482 482 mtc0 v0, CP0_TCSTATUS 483 ehb483 _ehb 484 484 DMT 2 # dmt v0 485 485 /* 486 486 * We don't know a priori if ra is "live" … … 496 496 xori t0, 0x1e 497 497 mtc0 t0, CP0_STATUS 498 498 #ifdef CONFIG_MIPS_MT_SMTC 499 ehb499 _ehb 500 500 andi v0, v0, VPECONTROL_TE 501 501 beqz v0, 2f 502 502 nop /* delay slot */ -
include/asm-mips/unistd.h
diff -Naur linux-2.6.17.4-kernel/include/asm-mips/unistd.h linux-2.6.17.4-mips/include/asm-mips/unistd.h
old new 326 326 #define __NR_unshare (__NR_Linux + 303) 327 327 #define __NR_splice (__NR_Linux + 304) 328 328 #define __NR_sync_file_range (__NR_Linux + 305) 329 #define __NR_tee (__NR_Linux + 306) 329 330 330 331 /* 331 332 * Offset of the last Linux o32 flavoured syscall 332 333 */ 333 #define __NR_Linux_syscalls 30 5334 #define __NR_Linux_syscalls 306 334 335 335 336 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ 336 337 337 338 #define __NR_O32_Linux 4000 338 #define __NR_O32_Linux_syscalls 30 5339 #define __NR_O32_Linux_syscalls 306 339 340 340 341 #if _MIPS_SIM == _MIPS_SIM_ABI64 341 342 … … 608 609 #define __NR_unshare (__NR_Linux + 262) 609 610 #define __NR_splice (__NR_Linux + 263) 610 611 #define __NR_sync_file_range (__NR_Linux + 264) 612 #define __NR_tee (__NR_Linux + 265) 611 613 612 614 /* 613 615 * Offset of the last Linux 64-bit flavoured syscall 614 616 */ 615 #define __NR_Linux_syscalls 26 4617 #define __NR_Linux_syscalls 265 616 618 617 619 #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */ 618 620 619 621 #define __NR_64_Linux 5000 620 #define __NR_64_Linux_syscalls 26 4622 #define __NR_64_Linux_syscalls 265 621 623 622 624 #if _MIPS_SIM == _MIPS_SIM_NABI32 623 625 … … 894 896 #define __NR_unshare (__NR_Linux + 266) 895 897 #define __NR_splice (__NR_Linux + 267) 896 898 #define __NR_sync_file_range (__NR_Linux + 268) 899 #define __NR_tee (__NR_Linux + 269) 897 900 898 901 /* 899 902 * Offset of the last N32 flavoured syscall 900 903 */ 901 #define __NR_Linux_syscalls 26 8904 #define __NR_Linux_syscalls 269 902 905 903 906 #endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */ 904 907 905 908 #define __NR_N32_Linux 6000 906 #define __NR_N32_Linux_syscalls 26 8909 #define __NR_N32_Linux_syscalls 269 907 910 908 911 #ifndef __ASSEMBLY__ 909 912 -
include/linux/elf.h
diff -Naur linux-2.6.17.4-kernel/include/linux/elf.h linux-2.6.17.4-mips/include/linux/elf.h
old new 67 67 68 68 #define EM_MIPS 8 /* MIPS R3000 (officially, big-endian only) */ 69 69 70 #define EM_MIPS_RS 4_BE 10 /* MIPS R4000 big-endian */70 #define EM_MIPS_RS3_LE 10 /* MIPS R3000 little-endian */ 71 71 72 72 #define EM_PARISC 15 /* HPPA */ 73 73 -
include/linux/mc146818rtc.h
diff -Naur linux-2.6.17.4-kernel/include/linux/mc146818rtc.h linux-2.6.17.4-mips/include/linux/mc146818rtc.h
old new 89 89 # define RTC_VRT 0x80 /* valid RAM and time */ 90 90 /**********************************************************************/ 91 91 92 #ifndef RTC_IO_EXTENT 93 #define RTC_IO_EXTENT 0x8 94 #endif 95 96 #ifndef RTC_IOMAPPED 97 #define RTC_IOMAPPED 1 /* Default to I/O mapping. */ 98 #endif 99 92 100 #endif /* _MC146818RTC_H */ -
include/linux/pci_ids.h
diff -Naur linux-2.6.17.4-kernel/include/linux/pci_ids.h linux-2.6.17.4-mips/include/linux/pci_ids.h
old new 1569 1569 #define PCI_VENDOR_ID_SATSAGEM 0x1267 1570 1570 #define PCI_DEVICE_ID_SATSAGEM_NICCY 0x1016 1571 1571 1572 #define PCI_VENDOR_ID_SILICON_MOTION 0x126f 1573 #define PCI_DEVICE_ID_SM501_VOYAGER_GX_REV_AA 0x0501 1574 #define PCI_DEVICE_ID_SM501_VOYAGER_GX_REV_B 0x0510 1572 1575 1573 1576 #define PCI_VENDOR_ID_ENSONIQ 0x1274 1574 1577 #define PCI_DEVICE_ID_ENSONIQ_CT5880 0x5880 -
include/linux/serial.h
diff -Naur linux-2.6.17.4-kernel/include/linux/serial.h linux-2.6.17.4-mips/include/linux/serial.h
old new 76 76 #define PORT_16654 11 77 77 #define PORT_16850 12 78 78 #define PORT_RSA 13 /* RSA-DV II/S card */ 79 #define PORT_MAX 13 79 #define PORT_SB1250 14 80 #define PORT_MAX 14 80 81 81 82 #define SERIAL_IO_PORT 0 82 83 #define SERIAL_IO_HUB6 1 -
include/linux/serial_ip3106.h
diff -Naur linux-2.6.17.4-kernel/include/linux/serial_ip3106.h linux-2.6.17.4-mips/include/linux/serial_ip3106.h
old new 78 78 #define IP3106_UART_FIFO_RXFIFO 0x00001F00 79 79 #define IP3106_UART_FIFO_RBRTHR 0x000000FF 80 80 81 #define ip3106_lcr(base,port) *(volatile u32 *)(base+(port*0x1000) + 0x000) 82 #define ip3106_mcr(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x004) 83 #define ip3106_baud(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x008) 84 #define ip3106_cfg(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x00C) 85 #define ip3106_fifo(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x028) 86 #define ip3106_istat(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFE0) 87 #define ip3106_ien(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFE4) 88 #define ip3106_iclr(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFE8) 89 #define ip3106_iset(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFEC) 90 #define ip3106_pd(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFF4) 91 #define ip3106_mid(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFFC) 92 81 93 #endif -
sound/oss/au1550_ac97.c
diff -Naur linux-2.6.17.4-kernel/sound/oss/au1550_ac97.c linux-2.6.17.4-mips/sound/oss/au1550_ac97.c
old new 60 60 #include <asm/mach-au1x00/au1000.h> 61 61 #include <asm/mach-au1x00/au1xxx_psc.h> 62 62 #include <asm/mach-au1x00/au1xxx_dbdma.h> 63 #include <asm/mach-pb1x00/pb1550.h> 63 64 64 65 #undef OSS_DOCUMENTED_MIXER_SEMANTICS 65 66 -
sound/oss/Kconfig
diff -Naur linux-2.6.17.4-kernel/sound/oss/Kconfig linux-2.6.17.4-mips/sound/oss/Kconfig
old new 117 117 tristate "Au1550 AC97 Sound" 118 118 depends on SOUND_PRIME && SOC_AU1550 119 119 120 config SOUND_AU1550_I2S 121 tristate "Au1550 I2S Sound" 122 depends on SOUND_PRIME && SOC_AU1550 123 120 124 config SOUND_TRIDENT 121 125 tristate "Trident 4DWave DX/NX, SiS 7018 or ALi 5451 PCI Audio Core" 122 126 depends on SOUND_PRIME && PCI -
sound/oss/Makefile
diff -Naur linux-2.6.17.4-kernel/sound/oss/Makefile linux-2.6.17.4-mips/sound/oss/Makefile
old new 66 66 obj-$(CONFIG_SOUND_VRC5477) += nec_vrc5477.o ac97_codec.o 67 67 obj-$(CONFIG_SOUND_AU1000) += au1000.o ac97_codec.o 68 68 obj-$(CONFIG_SOUND_AU1550_AC97) += au1550_ac97.o ac97_codec.o 69 obj-$(CONFIG_SOUND_AU1550_I2S) += au1550_i2s.o 69 70 obj-$(CONFIG_SOUND_ESSSOLO1) += esssolo1.o 70 71 obj-$(CONFIG_SOUND_FUSION) += cs46xx.o ac97_codec.o 71 72 obj-$(CONFIG_SOUND_MAESTRO) += maestro.o
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