Submitted By: Jim Gifford (patches at jg555 dot com) Date: 2006-09-16 Initial Package Version: 2.6.17.13 Origin: Linux-MIPS Upstream Status: http://www.linux-mips.org/pub/linux/mips/kernel/v2.6/ diff -Naur linux-2.6.17.13.orig/arch/mips/cobalt/console.c linux-2.6.17.13/arch/mips/cobalt/console.c --- linux-2.6.17.13.orig/arch/mips/cobalt/console.c 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/cobalt/console.c 2006-09-09 10:17:04.000000000 -0700 @@ -41,3 +41,8 @@ printk("Cobalt: early console registered\n"); } + +void __init disable_early_printk(void) +{ + unregister_console(&cons_info); +} diff -Naur linux-2.6.17.13.orig/arch/mips/configs/atlas_defconfig linux-2.6.17.13/arch/mips/configs/atlas_defconfig --- linux-2.6.17.13.orig/arch/mips/configs/atlas_defconfig 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/configs/atlas_defconfig 2006-09-09 10:17:04.000000000 -0700 @@ -67,6 +67,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_MIPS_BONITO64=y diff -Naur linux-2.6.17.13.orig/arch/mips/configs/bigsur_defconfig linux-2.6.17.13/arch/mips/configs/bigsur_defconfig --- linux-2.6.17.13.orig/arch/mips/configs/bigsur_defconfig 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/configs/bigsur_defconfig 2006-09-09 10:17:04.000000000 -0700 @@ -83,6 +83,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_DMA_COHERENT=y CONFIG_CPU_BIG_ENDIAN=y # CONFIG_CPU_LITTLE_ENDIAN is not set diff -Naur linux-2.6.17.13.orig/arch/mips/configs/capcella_defconfig linux-2.6.17.13/arch/mips/configs/capcella_defconfig --- linux-2.6.17.13.orig/arch/mips/configs/capcella_defconfig 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/configs/capcella_defconfig 2006-09-09 10:17:04.000000000 -0700 @@ -75,6 +75,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y # CONFIG_CPU_BIG_ENDIAN is not set diff -Naur linux-2.6.17.13.orig/arch/mips/configs/cobalt_defconfig linux-2.6.17.13/arch/mips/configs/cobalt_defconfig --- linux-2.6.17.13.orig/arch/mips/configs/cobalt_defconfig 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/configs/cobalt_defconfig 2006-09-09 10:17:04.000000000 -0700 @@ -68,6 +68,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_I8259=y diff -Naur linux-2.6.17.13.orig/arch/mips/configs/db1000_defconfig linux-2.6.17.13/arch/mips/configs/db1000_defconfig --- linux-2.6.17.13.orig/arch/mips/configs/db1000_defconfig 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/configs/db1000_defconfig 2006-09-09 10:17:04.000000000 -0700 @@ -67,6 +67,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y # CONFIG_CPU_BIG_ENDIAN is not set diff -Naur linux-2.6.17.13.orig/arch/mips/configs/db1100_defconfig linux-2.6.17.13/arch/mips/configs/db1100_defconfig --- linux-2.6.17.13.orig/arch/mips/configs/db1100_defconfig 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/configs/db1100_defconfig 2006-09-09 10:17:04.000000000 -0700 @@ -67,6 +67,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y # CONFIG_CPU_BIG_ENDIAN is not set diff -Naur linux-2.6.17.13.orig/arch/mips/configs/db1200_defconfig linux-2.6.17.13/arch/mips/configs/db1200_defconfig --- linux-2.6.17.13.orig/arch/mips/configs/db1200_defconfig 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/configs/db1200_defconfig 2006-09-09 10:17:04.000000000 -0700 @@ -67,6 +67,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_DMA_COHERENT=y CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y # CONFIG_CPU_BIG_ENDIAN is not set diff -Naur linux-2.6.17.13.orig/arch/mips/configs/db1500_defconfig linux-2.6.17.13/arch/mips/configs/db1500_defconfig --- linux-2.6.17.13.orig/arch/mips/configs/db1500_defconfig 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/configs/db1500_defconfig 2006-09-09 10:17:04.000000000 -0700 @@ -67,6 +67,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y diff -Naur linux-2.6.17.13.orig/arch/mips/configs/db1550_defconfig linux-2.6.17.13/arch/mips/configs/db1550_defconfig --- linux-2.6.17.13.orig/arch/mips/configs/db1550_defconfig 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/configs/db1550_defconfig 2006-09-09 10:17:04.000000000 -0700 @@ -67,6 +67,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y diff -Naur linux-2.6.17.13.orig/arch/mips/configs/ddb5476_defconfig linux-2.6.17.13/arch/mips/configs/ddb5476_defconfig --- linux-2.6.17.13.orig/arch/mips/configs/ddb5476_defconfig 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/configs/ddb5476_defconfig 2006-09-09 10:17:04.000000000 -0700 @@ -67,6 +67,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_I8259=y diff -Naur linux-2.6.17.13.orig/arch/mips/configs/ddb5477_defconfig linux-2.6.17.13/arch/mips/configs/ddb5477_defconfig --- linux-2.6.17.13.orig/arch/mips/configs/ddb5477_defconfig 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/configs/ddb5477_defconfig 2006-09-09 10:17:04.000000000 -0700 @@ -68,6 +68,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_I8259=y diff -Naur linux-2.6.17.13.orig/arch/mips/configs/decstation_defconfig linux-2.6.17.13/arch/mips/configs/decstation_defconfig --- linux-2.6.17.13.orig/arch/mips/configs/decstation_defconfig 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/configs/decstation_defconfig 2006-09-09 10:17:04.000000000 -0700 @@ -68,6 +68,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y # CONFIG_CPU_BIG_ENDIAN is not set diff -Naur linux-2.6.17.13.orig/arch/mips/configs/e55_defconfig linux-2.6.17.13/arch/mips/configs/e55_defconfig --- linux-2.6.17.13.orig/arch/mips/configs/e55_defconfig 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/configs/e55_defconfig 2006-09-09 10:17:04.000000000 -0700 @@ -73,6 +73,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y # CONFIG_CPU_BIG_ENDIAN is not set diff -Naur linux-2.6.17.13.orig/arch/mips/configs/ev64120_defconfig linux-2.6.17.13/arch/mips/configs/ev64120_defconfig --- linux-2.6.17.13.orig/arch/mips/configs/ev64120_defconfig 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/configs/ev64120_defconfig 2006-09-09 10:17:04.000000000 -0700 @@ -68,6 +68,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_CPU_BIG_ENDIAN=y diff -Naur linux-2.6.17.13.orig/arch/mips/configs/ev96100_defconfig linux-2.6.17.13/arch/mips/configs/ev96100_defconfig --- linux-2.6.17.13.orig/arch/mips/configs/ev96100_defconfig 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/configs/ev96100_defconfig 2006-09-09 10:17:04.000000000 -0700 @@ -67,6 +67,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_CPU_BIG_ENDIAN=y diff -Naur linux-2.6.17.13.orig/arch/mips/configs/ip22_defconfig linux-2.6.17.13/arch/mips/configs/ip22_defconfig --- linux-2.6.17.13.orig/arch/mips/configs/ip22_defconfig 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/configs/ip22_defconfig 2006-09-09 10:17:04.000000000 -0700 @@ -67,6 +67,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_ARC=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y diff -Naur linux-2.6.17.13.orig/arch/mips/configs/ip27_defconfig linux-2.6.17.13/arch/mips/configs/ip27_defconfig --- linux-2.6.17.13.orig/arch/mips/configs/ip27_defconfig 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/configs/ip27_defconfig 2006-09-09 10:17:04.000000000 -0700 @@ -73,6 +73,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_ARC=y CONFIG_DMA_IP27=y CONFIG_CPU_BIG_ENDIAN=y diff -Naur linux-2.6.17.13.orig/arch/mips/configs/ip32_defconfig linux-2.6.17.13/arch/mips/configs/ip32_defconfig --- linux-2.6.17.13.orig/arch/mips/configs/ip32_defconfig 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/configs/ip32_defconfig 2006-09-09 10:17:04.000000000 -0700 @@ -67,6 +67,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_ARC=y CONFIG_DMA_IP32=y CONFIG_DMA_NONCOHERENT=y diff -Naur linux-2.6.17.13.orig/arch/mips/configs/it8172_defconfig linux-2.6.17.13/arch/mips/configs/it8172_defconfig --- linux-2.6.17.13.orig/arch/mips/configs/it8172_defconfig 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/configs/it8172_defconfig 2006-09-09 10:17:04.000000000 -0700 @@ -68,6 +68,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y # CONFIG_CPU_BIG_ENDIAN is not set diff -Naur linux-2.6.17.13.orig/arch/mips/configs/ivr_defconfig linux-2.6.17.13/arch/mips/configs/ivr_defconfig --- linux-2.6.17.13.orig/arch/mips/configs/ivr_defconfig 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/configs/ivr_defconfig 2006-09-09 10:17:04.000000000 -0700 @@ -67,6 +67,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y # CONFIG_CPU_BIG_ENDIAN is not set diff -Naur linux-2.6.17.13.orig/arch/mips/configs/jaguar-atx_defconfig linux-2.6.17.13/arch/mips/configs/jaguar-atx_defconfig --- linux-2.6.17.13.orig/arch/mips/configs/jaguar-atx_defconfig 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/configs/jaguar-atx_defconfig 2006-09-09 10:17:04.000000000 -0700 @@ -68,6 +68,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_LIMITED_DMA=y diff -Naur linux-2.6.17.13.orig/arch/mips/configs/jmr3927_defconfig linux-2.6.17.13/arch/mips/configs/jmr3927_defconfig --- linux-2.6.17.13.orig/arch/mips/configs/jmr3927_defconfig 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/configs/jmr3927_defconfig 2006-09-09 10:17:04.000000000 -0700 @@ -67,6 +67,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_CPU_BIG_ENDIAN=y diff -Naur linux-2.6.17.13.orig/arch/mips/configs/lasat200_defconfig linux-2.6.17.13/arch/mips/configs/lasat200_defconfig --- linux-2.6.17.13.orig/arch/mips/configs/lasat200_defconfig 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/configs/lasat200_defconfig 2006-09-09 10:17:04.000000000 -0700 @@ -71,6 +71,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_MIPS_NILE4=y diff -Naur linux-2.6.17.13.orig/arch/mips/configs/malta_defconfig linux-2.6.17.13/arch/mips/configs/malta_defconfig --- linux-2.6.17.13.orig/arch/mips/configs/malta_defconfig 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/configs/malta_defconfig 2006-09-09 10:17:04.000000000 -0700 @@ -67,6 +67,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_ARCH_MAY_HAVE_PC_FDC=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y diff -Naur linux-2.6.17.13.orig/arch/mips/configs/mipssim_defconfig linux-2.6.17.13/arch/mips/configs/mipssim_defconfig --- linux-2.6.17.13.orig/arch/mips/configs/mipssim_defconfig 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/configs/mipssim_defconfig 2006-09-09 10:17:04.000000000 -0700 @@ -67,6 +67,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y # CONFIG_CPU_BIG_ENDIAN is not set diff -Naur linux-2.6.17.13.orig/arch/mips/configs/mpc30x_defconfig linux-2.6.17.13/arch/mips/configs/mpc30x_defconfig --- linux-2.6.17.13.orig/arch/mips/configs/mpc30x_defconfig 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/configs/mpc30x_defconfig 2006-09-09 10:17:04.000000000 -0700 @@ -75,6 +75,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y # CONFIG_CPU_BIG_ENDIAN is not set diff -Naur linux-2.6.17.13.orig/arch/mips/configs/ocelot_3_defconfig linux-2.6.17.13/arch/mips/configs/ocelot_3_defconfig --- linux-2.6.17.13.orig/arch/mips/configs/ocelot_3_defconfig 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/configs/ocelot_3_defconfig 2006-09-09 10:17:04.000000000 -0700 @@ -67,6 +67,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_CPU_BIG_ENDIAN=y diff -Naur linux-2.6.17.13.orig/arch/mips/configs/ocelot_c_defconfig linux-2.6.17.13/arch/mips/configs/ocelot_c_defconfig --- linux-2.6.17.13.orig/arch/mips/configs/ocelot_c_defconfig 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/configs/ocelot_c_defconfig 2006-09-09 10:17:04.000000000 -0700 @@ -67,6 +67,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_CPU_BIG_ENDIAN=y diff -Naur linux-2.6.17.13.orig/arch/mips/configs/ocelot_defconfig linux-2.6.17.13/arch/mips/configs/ocelot_defconfig --- linux-2.6.17.13.orig/arch/mips/configs/ocelot_defconfig 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/configs/ocelot_defconfig 2006-09-09 10:17:04.000000000 -0700 @@ -67,6 +67,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_CPU_BIG_ENDIAN=y diff -Naur linux-2.6.17.13.orig/arch/mips/configs/ocelot_g_defconfig linux-2.6.17.13/arch/mips/configs/ocelot_g_defconfig --- linux-2.6.17.13.orig/arch/mips/configs/ocelot_g_defconfig 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/configs/ocelot_g_defconfig 2006-09-09 10:17:04.000000000 -0700 @@ -67,6 +67,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_CPU_BIG_ENDIAN=y diff -Naur linux-2.6.17.13.orig/arch/mips/configs/pb1100_defconfig linux-2.6.17.13/arch/mips/configs/pb1100_defconfig --- linux-2.6.17.13.orig/arch/mips/configs/pb1100_defconfig 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/configs/pb1100_defconfig 2006-09-09 10:17:04.000000000 -0700 @@ -67,6 +67,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y # CONFIG_CPU_BIG_ENDIAN is not set diff -Naur linux-2.6.17.13.orig/arch/mips/configs/pb1500_defconfig linux-2.6.17.13/arch/mips/configs/pb1500_defconfig --- linux-2.6.17.13.orig/arch/mips/configs/pb1500_defconfig 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/configs/pb1500_defconfig 2006-09-09 10:17:04.000000000 -0700 @@ -67,6 +67,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y # CONFIG_CPU_BIG_ENDIAN is not set diff -Naur linux-2.6.17.13.orig/arch/mips/configs/pb1550_defconfig linux-2.6.17.13/arch/mips/configs/pb1550_defconfig --- linux-2.6.17.13.orig/arch/mips/configs/pb1550_defconfig 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/configs/pb1550_defconfig 2006-09-09 10:17:04.000000000 -0700 @@ -67,6 +67,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y diff -Naur linux-2.6.17.13.orig/arch/mips/configs/pnx8550-jbs_defconfig linux-2.6.17.13/arch/mips/configs/pnx8550-jbs_defconfig --- linux-2.6.17.13.orig/arch/mips/configs/pnx8550-jbs_defconfig 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/configs/pnx8550-jbs_defconfig 2006-09-09 10:17:04.000000000 -0700 @@ -67,6 +67,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y # CONFIG_CPU_BIG_ENDIAN is not set diff -Naur linux-2.6.17.13.orig/arch/mips/configs/pnx8550-v2pci_defconfig linux-2.6.17.13/arch/mips/configs/pnx8550-v2pci_defconfig --- linux-2.6.17.13.orig/arch/mips/configs/pnx8550-v2pci_defconfig 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/configs/pnx8550-v2pci_defconfig 2006-09-09 10:17:04.000000000 -0700 @@ -67,6 +67,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y # CONFIG_CPU_BIG_ENDIAN is not set diff -Naur linux-2.6.17.13.orig/arch/mips/configs/qemu_defconfig linux-2.6.17.13/arch/mips/configs/qemu_defconfig --- linux-2.6.17.13.orig/arch/mips/configs/qemu_defconfig 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/configs/qemu_defconfig 2006-09-09 10:17:04.000000000 -0700 @@ -67,6 +67,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_DMA_COHERENT=y CONFIG_GENERIC_ISA_DMA=y CONFIG_I8259=y diff -Naur linux-2.6.17.13.orig/arch/mips/configs/rbhma4500_defconfig linux-2.6.17.13/arch/mips/configs/rbhma4500_defconfig --- linux-2.6.17.13.orig/arch/mips/configs/rbhma4500_defconfig 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/configs/rbhma4500_defconfig 2006-09-09 10:17:04.000000000 -0700 @@ -74,6 +74,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_GENERIC_ISA_DMA=y diff -Naur linux-2.6.17.13.orig/arch/mips/configs/rm200_defconfig linux-2.6.17.13/arch/mips/configs/rm200_defconfig --- linux-2.6.17.13.orig/arch/mips/configs/rm200_defconfig 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/configs/rm200_defconfig 2006-09-09 10:17:04.000000000 -0700 @@ -67,6 +67,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_ARC=y CONFIG_ARCH_MAY_HAVE_PC_FDC=y CONFIG_DMA_NONCOHERENT=y diff -Naur linux-2.6.17.13.orig/arch/mips/configs/sb1250-swarm_defconfig linux-2.6.17.13/arch/mips/configs/sb1250-swarm_defconfig --- linux-2.6.17.13.orig/arch/mips/configs/sb1250-swarm_defconfig 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/configs/sb1250-swarm_defconfig 2006-09-09 10:17:04.000000000 -0700 @@ -84,6 +84,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_DMA_COHERENT=y CONFIG_CPU_BIG_ENDIAN=y # CONFIG_CPU_LITTLE_ENDIAN is not set diff -Naur linux-2.6.17.13.orig/arch/mips/configs/sead_defconfig linux-2.6.17.13/arch/mips/configs/sead_defconfig --- linux-2.6.17.13.orig/arch/mips/configs/sead_defconfig 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/configs/sead_defconfig 2006-09-09 10:17:04.000000000 -0700 @@ -67,6 +67,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y # CONFIG_CPU_BIG_ENDIAN is not set diff -Naur linux-2.6.17.13.orig/arch/mips/configs/tb0226_defconfig linux-2.6.17.13/arch/mips/configs/tb0226_defconfig --- linux-2.6.17.13.orig/arch/mips/configs/tb0226_defconfig 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/configs/tb0226_defconfig 2006-09-09 10:17:04.000000000 -0700 @@ -77,6 +77,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y # CONFIG_CPU_BIG_ENDIAN is not set diff -Naur linux-2.6.17.13.orig/arch/mips/configs/tb0229_defconfig linux-2.6.17.13/arch/mips/configs/tb0229_defconfig --- linux-2.6.17.13.orig/arch/mips/configs/tb0229_defconfig 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/configs/tb0229_defconfig 2006-09-09 10:17:04.000000000 -0700 @@ -77,6 +77,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y # CONFIG_CPU_BIG_ENDIAN is not set diff -Naur linux-2.6.17.13.orig/arch/mips/configs/workpad_defconfig linux-2.6.17.13/arch/mips/configs/workpad_defconfig --- linux-2.6.17.13.orig/arch/mips/configs/workpad_defconfig 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/configs/workpad_defconfig 2006-09-09 10:17:04.000000000 -0700 @@ -73,6 +73,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y # CONFIG_CPU_BIG_ENDIAN is not set diff -Naur linux-2.6.17.13.orig/arch/mips/configs/yosemite_defconfig linux-2.6.17.13/arch/mips/configs/yosemite_defconfig --- linux-2.6.17.13.orig/arch/mips/configs/yosemite_defconfig 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/configs/yosemite_defconfig 2006-09-09 10:17:04.000000000 -0700 @@ -68,6 +68,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_DMA_COHERENT=y CONFIG_CPU_BIG_ENDIAN=y # CONFIG_CPU_LITTLE_ENDIAN is not set diff -Naur linux-2.6.17.13.orig/arch/mips/defconfig linux-2.6.17.13/arch/mips/defconfig --- linux-2.6.17.13.orig/arch/mips/defconfig 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/defconfig 2006-09-09 10:17:04.000000000 -0700 @@ -67,6 +67,7 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y CONFIG_ARC=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y diff -Naur linux-2.6.17.13.orig/arch/mips/Kconfig linux-2.6.17.13/arch/mips/Kconfig --- linux-2.6.17.13.orig/arch/mips/Kconfig 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/Kconfig 2006-09-09 10:17:04.000000000 -0700 @@ -278,6 +278,7 @@ select SYS_SUPPORTS_64BIT_KERNEL select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_SUPPORTS_MULTITHREADING if EXPERIMENTAL help This enables support for the MIPS Technologies Atlas evaluation board. @@ -294,6 +295,7 @@ select I8259 select MIPS_BOARDS_GEN select MIPS_BONITO64 + select MIPS_CPU_SCACHE select MIPS_GT64120 select MIPS_MSC select SWAP_IO_SPACE @@ -306,6 +308,7 @@ select SYS_SUPPORTS_64BIT_KERNEL select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_SUPPORTS_MULTITHREADING help This enables support for the MIPS Technologies Malta evaluation board. @@ -438,11 +441,13 @@ config PNX8550_V2PCI bool "Philips PNX8550 based Viper2-PCI board" + depends on BROKEN select PNX8550 select SYS_SUPPORTS_LITTLE_ENDIAN config PNX8550_JBS bool "Philips PNX8550 based JBS board" + depends on BROKEN select PNX8550 select SYS_SUPPORTS_LITTLE_ENDIAN @@ -506,8 +511,6 @@ config MACH_VR41XX bool "NEC VR41XX-based machines" select SYS_HAS_CPU_VR41XX - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL config PMC_YOSEMITE bool "PMC-Sierra Yosemite eval board" @@ -522,6 +525,7 @@ select SYS_SUPPORTS_64BIT_KERNEL select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_HIGHMEM + select SYS_SUPPORTS_SMP help Yosemite is an evaluation board for the RM9000x2 processor manufactured by PMC-Sierra. @@ -555,6 +559,7 @@ select HW_HAS_EISA select IP22_CPU_SCACHE select IRQ_CPU + select NO_ISA if ISA select SWAP_IO_SPACE select SYS_HAS_CPU_R4X00 select SYS_HAS_CPU_R5000 @@ -577,6 +582,7 @@ select SYS_HAS_CPU_R10000 select SYS_SUPPORTS_64BIT_KERNEL select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_SMP help This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics workstations. To compile a Linux kernel that runs on these, say Y @@ -1035,6 +1041,9 @@ config HAVE_STD_PC_SERIAL_PORT bool +config VR4181 + bool + config ARC_CONSOLE bool "ARC console support" depends on SGI_IP22 || SNI_RM200_PCI @@ -1155,7 +1164,7 @@ select CPU_SUPPORTS_32BIT_KERNEL select CPU_SUPPORTS_64BIT_KERNEL help - The options selects support for the NEC VR4100 series of processors. + The options selects support for the NEC VR41xx series of processors. Only choose this option if you have one of these processors as a kernel built with this option will not run on any other type of processor or vice versa. @@ -1211,7 +1220,7 @@ select CPU_SUPPORTS_32BIT_KERNEL help MIPS Technologies R6000 and R6000A series processors. Note these - processors are extremly rare and the support for them is incomplete. + processors are extremely rare and the support for them is incomplete. config CPU_NEVADA bool "RM52xx" @@ -1332,7 +1341,7 @@ endmenu # -# These two indicate any levelof the MIPS32 and MIPS64 architecture +# These two indicate any level of the MIPS32 and MIPS64 architecture # config CPU_MIPS32 bool @@ -1343,7 +1352,7 @@ default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 # -# These two indicate the revision of the architecture, either 32 bot 64 bit. +# These two indicate the revision of the architecture, either Release 1 or Release 2 # config CPU_MIPSR1 bool @@ -1436,6 +1445,13 @@ bool select BOARD_SCACHE +# +# Support for a MIPS32 / MIPS64 style S-caches +# +config MIPS_CPU_SCACHE + bool + select BOARD_SCACHE + config R5000_CPU_SCACHE bool select BOARD_SCACHE @@ -1455,32 +1471,57 @@ config CPU_HAS_PREFETCH bool -config MIPS_MT - bool "Enable MIPS MT" - choice prompt "MIPS MT options" - depends on MIPS_MT + +config MIPS_MT_DISABLED + bool "Disable multithreading support." + help + Use this option if your workload can't take advantage of + MIPS hardware multithreading support. On systems that don't have + the option of an MT-enabled processor this option will be the only + option in this menu. config MIPS_MT_SMTC bool "SMTC: Use all TCs on all VPEs for SMP" + depends on CPU_MIPS32_R2 + #depends on CPU_MIPS64_R2 # once there is hardware ... + depends on SYS_SUPPORTS_MULTITHREADING select CPU_MIPSR2_IRQ_VI select CPU_MIPSR2_SRS + select MIPS_MT select SMP + help + This is a kernel model which is known a SMTC or lately has been + marketesed into SMVP. config MIPS_MT_SMP bool "Use 1 TC on each available VPE for SMP" + depends on SYS_SUPPORTS_MULTITHREADING + select CPU_MIPSR2_IRQ_VI + select CPU_MIPSR2_SRS + select MIPS_MT select SMP + help + This is a kernel model which is also known a VSMP or lately + has been marketesed into SMVP. config MIPS_VPE_LOADER bool "VPE loader support." - depends on MIPS_MT + depends on SYS_SUPPORTS_MULTITHREADING + select MIPS_MT help Includes a loader for loading an elf relocatable object onto another VPE and running it. endchoice +config MIPS_MT + bool + +config SYS_SUPPORTS_MULTITHREADING + bool + config MIPS_MT_FPAFF bool "Dynamic FPU affinity for FP-intensive threads" depends on MIPS_MT @@ -1537,32 +1578,23 @@ config CPU_HAS_WB bool +# +# Vectored interrupt mode is an R2 feature +# config CPU_MIPSR2_IRQ_VI - bool "Vectored interrupt mode" - depends on CPU_MIPSR2 - help - Vectored interrupt mode allowing faster dispatching of interrupts. - The board support code needs to be written to take advantage of this - mode. Compatibility code is included to allow the kernel to run on - a CPU that does not support vectored interrupts. It's safe to - say Y here. + bool +# +# Extended interrupt mode is an R2 feature +# config CPU_MIPSR2_IRQ_EI - bool "External interrupt controller mode" - depends on CPU_MIPSR2 - help - Extended interrupt mode takes advantage of an external interrupt - controller to allow fast dispatching from many possible interrupt - sources. Say N unless you know that external interrupt support is - required. + bool +# +# Shadow registers are an R2 feature +# config CPU_MIPSR2_SRS - bool "Make shadow set registers available for interrupt handlers" - depends on CPU_MIPSR2_IRQ_VI || CPU_MIPSR2_IRQ_EI - help - Allow the kernel to use shadow register sets for fast interrupts. - Interrupt handlers must be specially written to use shadow sets. - Say N unless you know that shadow register set upport is needed. + bool config CPU_HAS_SYNC bool @@ -1616,8 +1648,8 @@ config SMP bool "Multi-Processing support" - depends on CPU_RM9000 || ((SIBYTE_BCM1x80 || SIBYTE_BCM1x55 || SIBYTE_SB1250 || QEMU) && !SIBYTE_STANDALONE) || SGI_IP27 || MIPS_MT_SMP || MIPS_MT_SMTC - ---help--- + depends on SYS_SUPPORTS_SMP + help This enables support for systems with more than one CPU. If you have a system with only one CPU, like most personal computers, say N. If you have a system with more than one CPU, say Y. @@ -1636,6 +1668,9 @@ If you don't know what to do here, say N. +config SYS_SUPPORTS_SMP + bool + config NR_CPUS int "Maximum number of CPUs (2-64)" range 2 64 @@ -1710,6 +1745,9 @@ config ISA bool +config NO_ISA + bool + config EISA bool "EISA support" depends on HW_HAS_EISA diff -Naur linux-2.6.17.13.orig/arch/mips/kernel/cpu-probe.c linux-2.6.17.13/arch/mips/kernel/cpu-probe.c --- linux-2.6.17.13.orig/arch/mips/kernel/cpu-probe.c 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/kernel/cpu-probe.c 2006-09-09 10:17:04.000000000 -0700 @@ -111,7 +111,6 @@ case CPU_R5000: case CPU_NEVADA: case CPU_RM7000: - case CPU_RM9000: case CPU_TX49XX: case CPU_4KC: case CPU_4KEC: @@ -137,6 +136,14 @@ } else printk(" unavailable.\n"); break; + case CPU_RM9000: + if ((c->processor_id & 0x00ff) >= 0x40) { + cpu_wait = r4k_wait; + printk(" available.\n"); + } else { + printk(" unavailable.\n"); + } + break; default: printk(" unavailable.\n"); break; @@ -243,9 +250,15 @@ break; case PRID_IMP_VR41XX: switch (c->processor_id & 0xf0) { +#ifndef CONFIG_VR4181 case PRID_REV_VR4111: c->cputype = CPU_VR4111; break; +#else + case PRID_REV_VR4181: + c->cputype = CPU_VR4181; + break; +#endif case PRID_REV_VR4121: c->cputype = CPU_VR4121; break; @@ -597,8 +610,6 @@ break; case PRID_IMP_25KF: c->cputype = CPU_25KF; - /* Probe for L2 cache */ - c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; break; case PRID_IMP_34K: c->cputype = CPU_34K; diff -Naur linux-2.6.17.13.orig/arch/mips/kernel/entry.S linux-2.6.17.13/arch/mips/kernel/entry.S --- linux-2.6.17.13.orig/arch/mips/kernel/entry.S 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/kernel/entry.S 2006-09-09 10:17:04.000000000 -0700 @@ -87,7 +87,7 @@ ori v1, v0, TCSTATUS_IXMT mtc0 v1, CP0_TCSTATUS andi v0, TCSTATUS_IXMT - ehb + _ehb mfc0 t0, CP0_TCCONTEXT DMT 9 # dmt t1 jal mips_ihb @@ -95,7 +95,7 @@ andi t3, t0, 0xff00 or t2, t2, t3 mtc0 t2, CP0_STATUS - ehb + _ehb andi t1, t1, VPECONTROL_TE beqz t1, 1f EMT @@ -105,7 +105,7 @@ xori v1, v1, TCSTATUS_IXMT or v1, v0, v1 mtc0 v1, CP0_TCSTATUS - ehb + _ehb xor t0, t0, t3 mtc0 t0, CP0_TCCONTEXT #endif /* CONFIG_MIPS_MT_SMTC */ diff -Naur linux-2.6.17.13.orig/arch/mips/kernel/gdb-low.S linux-2.6.17.13/arch/mips/kernel/gdb-low.S --- linux-2.6.17.13.orig/arch/mips/kernel/gdb-low.S 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/kernel/gdb-low.S 2006-09-09 10:17:04.000000000 -0700 @@ -291,7 +291,7 @@ ori t1, t2, TCSTATUS_IXMT mtc0 t1, CP0_TCSTATUS andi t2, t2, TCSTATUS_IXMT - ehb + _ehb DMT 9 # dmt t1 jal mips_ihb nop @@ -310,7 +310,7 @@ xori t1, t1, TCSTATUS_IXMT or t1, t1, t2 mtc0 t1, CP0_TCSTATUS - ehb + _ehb #endif /* CONFIG_MIPS_MT_SMTC */ LONG_L v0, GDB_FR_STATUS(sp) LONG_L v1, GDB_FR_EPC(sp) diff -Naur linux-2.6.17.13.orig/arch/mips/kernel/genex.S linux-2.6.17.13/arch/mips/kernel/genex.S --- linux-2.6.17.13.orig/arch/mips/kernel/genex.S 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/kernel/genex.S 2006-09-09 10:17:04.000000000 -0700 @@ -214,7 +214,7 @@ mtc0 t0, CP0_TCCONTEXT xor t1, t1, t0 mtc0 t1, CP0_STATUS - ehb + _ehb #endif /* CONFIG_MIPS_MT_SMTC */ CLI move a0, sp diff -Naur linux-2.6.17.13.orig/arch/mips/kernel/head.S linux-2.6.17.13/arch/mips/kernel/head.S --- linux-2.6.17.13.orig/arch/mips/kernel/head.S 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/kernel/head.S 2006-09-09 10:17:04.000000000 -0700 @@ -96,7 +96,7 @@ /* Clear TKSU, leave IXMT */ xori t0, 0x00001800 mtc0 t0, CP0_TCSTATUS - ehb + _ehb /* We need to leave the global IE bit set, but clear EXL...*/ mfc0 t0, CP0_STATUS or t0, ST0_CU0 | ST0_EXL | ST0_ERL | \set | \clr diff -Naur linux-2.6.17.13.orig/arch/mips/kernel/irixsig.c linux-2.6.17.13/arch/mips/kernel/irixsig.c --- linux-2.6.17.13.orig/arch/mips/kernel/irixsig.c 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/kernel/irixsig.c 2006-09-09 10:17:04.000000000 -0700 @@ -185,9 +185,6 @@ if (!user_mode(regs)) return 1; - if (try_to_freeze()) - goto no_signal; - if (!oldset) oldset = ¤t->blocked; @@ -195,7 +192,6 @@ if (signr > 0) return handle_signal(signr, &info, &ka, oldset, regs); -no_signal: /* * Who's code doesn't conform to the restartable syscall convention * dies here!!! The li instruction, a single machine instruction, @@ -207,6 +203,7 @@ regs->regs[2] == ERESTARTNOINTR) { regs->cp0_epc -= 8; } + regs->regs[0] = 0; /* Don't deal with this again. */ } return 0; } diff -Naur linux-2.6.17.13.orig/arch/mips/kernel/ptrace.c linux-2.6.17.13/arch/mips/kernel/ptrace.c --- linux-2.6.17.13.orig/arch/mips/kernel/ptrace.c 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/kernel/ptrace.c 2006-09-09 10:17:04.000000000 -0700 @@ -21,12 +21,12 @@ #include #include #include -#include #include #include #include #include -#include +#include +#include #include #include @@ -482,12 +482,16 @@ */ asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit) { + /* do the secure computing check first */ + secure_computing(regs->orig_eax); + if (unlikely(current->audit_context) && entryexit) audit_syscall_exit(AUDITSC_RESULT(regs->regs[2]), regs->regs[2]); if (!(current->ptrace & PT_PTRACED)) goto out; + if (!test_thread_flag(TIF_SYSCALL_TRACE)) goto out; @@ -505,9 +509,14 @@ send_sig(current->exit_code, current, 1); current->exit_code = 0; } - out: + +out: + /* There is no ->orig_eax and that's quite intensional for now making + this work will require some work in various other place before it's + more than a placebo. */ + if (unlikely(current->audit_context) && !entryexit) - audit_syscall_entry(audit_arch(), regs->regs[2], - regs->regs[4], regs->regs[5], - regs->regs[6], regs->regs[7]); + audit_syscall_entry(audit_arch(), regs->orig_eax, + regs->regs[4], regs->regs[5], + regs->regs[6], regs->regs[7]); } diff -Naur linux-2.6.17.13.orig/arch/mips/kernel/r4k_switch.S linux-2.6.17.13/arch/mips/kernel/r4k_switch.S --- linux-2.6.17.13.orig/arch/mips/kernel/r4k_switch.S 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/kernel/r4k_switch.S 2006-09-09 10:17:04.000000000 -0700 @@ -75,8 +75,8 @@ and t0, t0, t1 LONG_S t0, ST_OFF(t3) - fpu_save_double a0 t1 t0 t2 # c0_status passed in t1 - # clobbers t0 and t2 + fpu_save_double a0 t0 t1 # c0_status passed in t0 + # clobbers t1 1: /* @@ -94,7 +94,7 @@ ori t1, t2, TCSTATUS_IXMT mtc0 t1, CP0_TCSTATUS andi t2, t2, TCSTATUS_IXMT - ehb + _ehb DMT 8 # dmt t0 move t1,ra jal mips_ihb @@ -109,7 +109,7 @@ or a2, t1 mtc0 a2, CP0_STATUS #ifdef CONFIG_MIPS_MT_SMTC - ehb + _ehb andi t0, t0, VPECONTROL_TE beqz t0, 1f emt @@ -118,7 +118,7 @@ xori t1, t1, TCSTATUS_IXMT or t1, t1, t2 mtc0 t1, CP0_TCSTATUS - ehb + _ehb #endif /* CONFIG_MIPS_MT_SMTC */ move v0, a0 jr ra @@ -129,9 +129,9 @@ */ LEAF(_save_fp) #ifdef CONFIG_64BIT - mfc0 t1, CP0_STATUS + mfc0 t0, CP0_STATUS #endif - fpu_save_double a0 t1 t0 t2 # clobbers t1 + fpu_save_double a0 t0 t1 # clobbers t1 jr ra END(_save_fp) @@ -139,7 +139,10 @@ * Restore a thread's fp context. */ LEAF(_restore_fp) - fpu_restore_double a0, t1 # clobbers t1 +#ifdef CONFIG_64BIT + mfc0 t0, CP0_STATUS +#endif + fpu_restore_double a0 t0 t1 # clobbers t1 jr ra END(_restore_fp) diff -Naur linux-2.6.17.13.orig/arch/mips/kernel/scall32-o32.S linux-2.6.17.13/arch/mips/kernel/scall32-o32.S --- linux-2.6.17.13.orig/arch/mips/kernel/scall32-o32.S 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/kernel/scall32-o32.S 2006-09-09 10:17:04.000000000 -0700 @@ -497,7 +497,7 @@ sys sys_sched_get_priority_min 1 sys sys_sched_rr_get_interval 2 /* 4165 */ sys sys_nanosleep, 2 - sys sys_mremap, 4 + sys sys_mremap, 5 sys sys_accept 3 sys sys_bind 3 sys sys_connect 3 /* 4170 */ @@ -647,6 +647,11 @@ sys sys_unshare 1 sys sys_splice 4 sys sys_sync_file_range 7 /* 4305 */ + sys sys_tee 4 + sys sys_vmsplice 4 + sys sys_ni_syscall 0 + sys sys_set_robust_list 2 + sys sys_get_robust_list 3 .endm /* We pre-compute the number of _instruction_ bytes needed to diff -Naur linux-2.6.17.13.orig/arch/mips/kernel/scall64-64.S linux-2.6.17.13/arch/mips/kernel/scall64-64.S --- linux-2.6.17.13.orig/arch/mips/kernel/scall64-64.S 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/kernel/scall64-64.S 2006-09-09 10:17:04.000000000 -0700 @@ -462,3 +462,8 @@ PTR sys_unshare PTR sys_splice PTR sys_sync_file_range + PTR sys_tee /* 5265 */ + PTR sys_vmsplice + PTR sys_ni_syscall + PTR sys_set_robust_list + PTR sys_get_robust_list diff -Naur linux-2.6.17.13.orig/arch/mips/kernel/scall64-n32.S linux-2.6.17.13/arch/mips/kernel/scall64-n32.S --- linux-2.6.17.13.orig/arch/mips/kernel/scall64-n32.S 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/kernel/scall64-n32.S 2006-09-09 10:17:04.000000000 -0700 @@ -388,3 +388,8 @@ PTR sys_unshare PTR sys_splice PTR sys_sync_file_range + PTR sys_tee + PTR sys_vmsplice /* 6270 */ + PTR sys_ni_syscall + PTR compat_sys_set_robust_list + PTR compat_sys_get_robust_list diff -Naur linux-2.6.17.13.orig/arch/mips/kernel/scall64-o32.S linux-2.6.17.13/arch/mips/kernel/scall64-o32.S --- linux-2.6.17.13.orig/arch/mips/kernel/scall64-o32.S 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/kernel/scall64-o32.S 2006-09-09 10:17:04.000000000 -0700 @@ -510,4 +510,9 @@ PTR sys_unshare PTR sys_splice PTR sys32_sync_file_range /* 4305 */ + PTR sys_tee + PTR sys_vmsplice + PTR sys_ni_syscall + PTR compat_sys_set_robust_list + PTR compat_sys_get_robust_list /* 4310 */ .size sys_call_table,.-sys_call_table diff -Naur linux-2.6.17.13.orig/arch/mips/kernel/signal32.c linux-2.6.17.13/arch/mips/kernel/signal32.c --- linux-2.6.17.13.orig/arch/mips/kernel/signal32.c 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/kernel/signal32.c 2006-09-09 10:17:04.000000000 -0700 @@ -815,9 +815,6 @@ if (!user_mode(regs)) return; - if (try_to_freeze()) - goto no_signal; - if (test_thread_flag(TIF_RESTORE_SIGMASK)) oldset = ¤t->saved_sigmask; else @@ -836,9 +833,10 @@ if (test_thread_flag(TIF_RESTORE_SIGMASK)) clear_thread_flag(TIF_RESTORE_SIGMASK); } + + return; } -no_signal: /* * Who's code doesn't conform to the restartable syscall convention * dies here!!! The li instruction, a single machine instruction, @@ -856,6 +854,7 @@ regs->regs[7] = regs->regs[26]; regs->cp0_epc -= 4; } + regs->regs[0] = 0; /* Don't deal with this again. */ } /* diff -Naur linux-2.6.17.13.orig/arch/mips/kernel/signal.c linux-2.6.17.13/arch/mips/kernel/signal.c --- linux-2.6.17.13.orig/arch/mips/kernel/signal.c 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/kernel/signal.c 2006-09-09 10:17:04.000000000 -0700 @@ -425,15 +425,11 @@ if (!user_mode(regs)) return; - if (try_to_freeze()) - goto no_signal; - if (test_thread_flag(TIF_RESTORE_SIGMASK)) oldset = ¤t->saved_sigmask; else oldset = ¤t->blocked; - signr = get_signal_to_deliver(&info, &ka, regs, NULL); if (signr > 0) { /* Whee! Actually deliver the signal. */ @@ -447,9 +443,10 @@ if (test_thread_flag(TIF_RESTORE_SIGMASK)) clear_thread_flag(TIF_RESTORE_SIGMASK); } + + return; } -no_signal: /* * Who's code doesn't conform to the restartable syscall convention * dies here!!! The li instruction, a single machine instruction, @@ -467,6 +464,7 @@ regs->regs[7] = regs->regs[26]; regs->cp0_epc -= 4; } + regs->regs[0] = 0; /* Don't deal with this again. */ } /* diff -Naur linux-2.6.17.13.orig/arch/mips/kernel/smp.c linux-2.6.17.13/arch/mips/kernel/smp.c --- linux-2.6.17.13.orig/arch/mips/kernel/smp.c 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/kernel/smp.c 2006-09-09 10:17:04.000000000 -0700 @@ -336,7 +336,7 @@ preempt_disable(); if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) { - smp_call_function(flush_tlb_mm_ipi, (void *)mm, 1, 1); + __on_other_cores(flush_tlb_mm_ipi, (void *)mm); } else { int i; for (i = 0; i < num_online_cpus(); i++) @@ -372,7 +372,7 @@ fd.vma = vma; fd.addr1 = start; fd.addr2 = end; - smp_call_function(flush_tlb_range_ipi, (void *)&fd, 1, 1); + __on_other_cores(flush_tlb_range_ipi, (void *)&fd); } else { int i; for (i = 0; i < num_online_cpus(); i++) @@ -414,7 +414,7 @@ fd.vma = vma; fd.addr1 = page; - smp_call_function(flush_tlb_page_ipi, (void *)&fd, 1, 1); + __on_other_cores(flush_tlb_page_ipi, (void *)&fd); } else { int i; for (i = 0; i < num_online_cpus(); i++) @@ -434,8 +434,7 @@ void flush_tlb_one(unsigned long vaddr) { - smp_call_function(flush_tlb_one_ipi, (void *) vaddr, 1, 1); - local_flush_tlb_one(vaddr); + __on_each_core(flush_tlb_one_ipi, (void *) vaddr); } static DEFINE_PER_CPU(struct cpu, cpu_devices); diff -Naur linux-2.6.17.13.orig/arch/mips/kernel/smp-mt.c linux-2.6.17.13/arch/mips/kernel/smp-mt.c --- linux-2.6.17.13.orig/arch/mips/kernel/smp-mt.c 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/kernel/smp-mt.c 2006-09-09 10:17:04.000000000 -0700 @@ -203,7 +203,7 @@ write_vpe_c0_config( read_c0_config()); /* make sure there are no software interrupts pending */ - write_vpe_c0_cause(read_vpe_c0_cause() & ~(C_SW1|C_SW0)); + write_vpe_c0_cause(0); /* Propagate Config7 */ write_vpe_c0_config7(read_c0_config7()); diff -Naur linux-2.6.17.13.orig/arch/mips/kernel/smtc-asm.S linux-2.6.17.13/arch/mips/kernel/smtc-asm.S --- linux-2.6.17.13.orig/arch/mips/kernel/smtc-asm.S 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/kernel/smtc-asm.S 2006-09-09 10:17:04.000000000 -0700 @@ -52,12 +52,12 @@ .set noat /* Disable thread scheduling to make Status update atomic */ DMT 27 # dmt k1 - ehb + _ehb /* Set EXL */ mfc0 k0,CP0_STATUS ori k0,k0,ST0_EXL mtc0 k0,CP0_STATUS - ehb + _ehb /* Thread scheduling now inhibited by EXL. Restore TE state. */ andi k1,k1,VPECONTROL_TE beqz k1,1f @@ -82,7 +82,7 @@ li k1,ST0_CU0 or k1,k1,k0 mtc0 k1,CP0_STATUS - ehb + _ehb get_saved_sp /* Interrupting TC will have pre-set values in slots in the new frame */ 2: subu k1,k1,PT_SIZE @@ -90,7 +90,7 @@ lw k0,PT_TCSTATUS(k1) /* Write it to TCStatus to restore CU/KSU/IXMT state */ mtc0 k0,$2,1 - ehb + _ehb lw k0,PT_EPC(k1) mtc0 k0,CP0_EPC /* Save all will redundantly recompute the SP, but use it for now */ @@ -116,7 +116,7 @@ mfc0 t0,CP0_TCSTATUS ori t1,t0,TCSTATUS_IXMT mtc0 t1,CP0_TCSTATUS - ehb + _ehb /* We know we're in kernel mode, so prepare stack frame */ subu t1,sp,PT_SIZE sw ra,PT_EPC(t1) diff -Naur linux-2.6.17.13.orig/arch/mips/kernel/syscall.c linux-2.6.17.13/arch/mips/kernel/syscall.c --- linux-2.6.17.13.orig/arch/mips/kernel/syscall.c 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/kernel/syscall.c 2006-09-09 10:17:04.000000000 -0700 @@ -117,6 +117,22 @@ } } +int mips_mmap_check(unsigned long addr, unsigned long len, + unsigned long flags) +{ +#ifdef CONFIG_MIPS32_COMPAT + if (current->thread.mflags & MF_32BIT_ADDR) { + if (len > TASK_SIZE32) + return -EINVAL; + if (flags & MAP_FIXED && + (addr >= TASK_SIZE32 || addr + len >= TASK_SIZE32)) + return -EINVAL; + } +#endif + + return 0; +} + /* common code for old and new mmaps */ static inline unsigned long do_mmap2(unsigned long addr, unsigned long len, unsigned long prot, diff -Naur linux-2.6.17.13.orig/arch/mips/kernel/traps.c linux-2.6.17.13/arch/mips/kernel/traps.c --- linux-2.6.17.13.orig/arch/mips/kernel/traps.c 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/kernel/traps.c 2006-09-09 10:17:04.000000000 -0700 @@ -1051,7 +1051,7 @@ return (void *)old_handler; } -#ifdef CONFIG_CPU_MIPSR2 +#ifdef CONFIG_CPU_MIPSR2_SRS /* * MIPSR2 shadow register set allocation * FIXME: SMP... @@ -1070,11 +1070,9 @@ static void mips_srs_init(void) { -#ifdef CONFIG_CPU_MIPSR2_SRS shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1; printk(KERN_INFO "%d MIPSR2 register sets available\n", shadow_registers.sr_supported); -#endif shadow_registers.sr_allocated = 1; /* Set 0 used by kernel */ } @@ -1199,7 +1197,14 @@ { return set_vi_srs_handler(n, addr, 0); } -#endif + +#else + +static inline void mips_srs_init(void) +{ +} + +#endif /* CONFIG_CPU_MIPSR2_SRS */ /* * This is used by native signal handling @@ -1389,9 +1394,7 @@ else ebase = CAC_BASE; -#ifdef CONFIG_CPU_MIPSR2 mips_srs_init(); -#endif per_cpu_trap_init(); diff -Naur linux-2.6.17.13.orig/arch/mips/kernel/vpe.c linux-2.6.17.13/arch/mips/kernel/vpe.c --- linux-2.6.17.13.orig/arch/mips/kernel/vpe.c 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/kernel/vpe.c 2006-09-09 10:17:04.000000000 -0700 @@ -769,10 +769,16 @@ */ write_tc_c0_tcbind((read_tc_c0_tcbind() & ~TCBIND_CURVPE) | v->minor); + write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() & ~(VPECONF0_VPA)); + + back_to_back_c0_hazard(); + /* Set up the XTC bit in vpeconf0 to point at our tc */ write_vpe_c0_vpeconf0( (read_vpe_c0_vpeconf0() & ~(VPECONF0_XTC)) | (t->index << VPECONF0_XTC_SHIFT)); + back_to_back_c0_hazard(); + /* enable this VPE */ write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA); diff -Naur linux-2.6.17.13.orig/arch/mips/lib/ashldi3.c linux-2.6.17.13/arch/mips/lib/ashldi3.c --- linux-2.6.17.13.orig/arch/mips/lib/ashldi3.c 1969-12-31 16:00:00.000000000 -0800 +++ linux-2.6.17.13/arch/mips/lib/ashldi3.c 2006-09-09 10:17:04.000000000 -0700 @@ -0,0 +1,29 @@ +#include + +#include "libgcc.h" + +long long __ashldi3(long long u, word_type b) +{ + DWunion uu, w; + word_type bm; + + if (b == 0) + return u; + + uu.ll = u; + bm = 32 - b; + + if (bm <= 0) { + w.s.low = 0; + w.s.high = (unsigned int) uu.s.low << -bm; + } else { + const unsigned int carries = (unsigned int) uu.s.low >> bm; + + w.s.low = (unsigned int) uu.s.low << b; + w.s.high = ((unsigned int) uu.s.high << b) | carries; + } + + return w.ll; +} + +EXPORT_SYMBOL(__ashldi3); diff -Naur linux-2.6.17.13.orig/arch/mips/lib/ashrdi3.c linux-2.6.17.13/arch/mips/lib/ashrdi3.c --- linux-2.6.17.13.orig/arch/mips/lib/ashrdi3.c 1969-12-31 16:00:00.000000000 -0800 +++ linux-2.6.17.13/arch/mips/lib/ashrdi3.c 2006-09-09 10:17:04.000000000 -0700 @@ -0,0 +1,31 @@ +#include + +#include "libgcc.h" + +long long __ashrdi3(long long u, word_type b) +{ + DWunion uu, w; + word_type bm; + + if (b == 0) + return u; + + uu.ll = u; + bm = 32 - b; + + if (bm <= 0) { + /* w.s.high = 1..1 or 0..0 */ + w.s.high = + uu.s.high >> 31; + w.s.low = uu.s.high >> -bm; + } else { + const unsigned int carries = (unsigned int) uu.s.high << bm; + + w.s.high = uu.s.high >> b; + w.s.low = ((unsigned int) uu.s.low >> b) | carries; + } + + return w.ll; +} + +EXPORT_SYMBOL(__ashrdi3); diff -Naur linux-2.6.17.13.orig/arch/mips/lib/iomap.c linux-2.6.17.13/arch/mips/lib/iomap.c --- linux-2.6.17.13.orig/arch/mips/lib/iomap.c 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/lib/iomap.c 1969-12-31 16:00:00.000000000 -0800 @@ -1,78 +0,0 @@ -/* - * iomap.c, Memory Mapped I/O routines for MIPS architecture. - * - * This code is based on lib/iomap.c, by Linus Torvalds. - * - * Copyright (C) 2004-2005 Yoichi Yuasa - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#include -#include -#include - -#include - -void __iomem *ioport_map(unsigned long port, unsigned int nr) -{ - unsigned long end; - - end = port + nr - 1UL; - if (ioport_resource.start > port || - ioport_resource.end < end || port > end) - return NULL; - - return (void __iomem *)(mips_io_port_base + port); -} - -void ioport_unmap(void __iomem *addr) -{ -} -EXPORT_SYMBOL(ioport_map); -EXPORT_SYMBOL(ioport_unmap); - -void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen) -{ - unsigned long start, len, flags; - - if (dev == NULL) - return NULL; - - start = pci_resource_start(dev, bar); - len = pci_resource_len(dev, bar); - if (!start || !len) - return NULL; - - if (maxlen != 0 && len > maxlen) - len = maxlen; - - flags = pci_resource_flags(dev, bar); - if (flags & IORESOURCE_IO) - return ioport_map(start, len); - if (flags & IORESOURCE_MEM) { - if (flags & IORESOURCE_CACHEABLE) - return ioremap_cachable(start, len); - return ioremap_nocache(start, len); - } - - return NULL; -} - -void pci_iounmap(struct pci_dev *dev, void __iomem *addr) -{ - iounmap(addr); -} -EXPORT_SYMBOL(pci_iomap); -EXPORT_SYMBOL(pci_iounmap); diff -Naur linux-2.6.17.13.orig/arch/mips/lib/libgcc.h linux-2.6.17.13/arch/mips/lib/libgcc.h --- linux-2.6.17.13.orig/arch/mips/lib/libgcc.h 1969-12-31 16:00:00.000000000 -0800 +++ linux-2.6.17.13/arch/mips/lib/libgcc.h 2006-09-09 10:17:04.000000000 -0700 @@ -0,0 +1,26 @@ +#ifndef __ASM_LIBGCC_H +#define __ASM_LIBGCC_H + +#include + +typedef int word_type __attribute__ ((mode (__word__))); + +#ifdef __BIG_ENDIAN +struct DWstruct { + int high, low; +}; +#elif defined(__LITTLE_ENDIAN) +struct DWstruct { + int low, high; +}; +#else +#error I feel sick. +#endif + +typedef union +{ + struct DWstruct s; + long long ll; +} DWunion; + +#endif /* __ASM_LIBGCC_H */ diff -Naur linux-2.6.17.13.orig/arch/mips/lib/lshrdi3.c linux-2.6.17.13/arch/mips/lib/lshrdi3.c --- linux-2.6.17.13.orig/arch/mips/lib/lshrdi3.c 1969-12-31 16:00:00.000000000 -0800 +++ linux-2.6.17.13/arch/mips/lib/lshrdi3.c 2006-09-09 10:17:04.000000000 -0700 @@ -0,0 +1,29 @@ +#include + +#include "libgcc.h" + +long long __lshrdi3(long long u, word_type b) +{ + DWunion uu, w; + word_type bm; + + if (b == 0) + return u; + + uu.ll = u; + bm = 32 - b; + + if (bm <= 0) { + w.s.high = 0; + w.s.low = (unsigned int) uu.s.high >> -bm; + } else { + const unsigned int carries = (unsigned int) uu.s.high << bm; + + w.s.high = (unsigned int) uu.s.high >> b; + w.s.low = ((unsigned int) uu.s.low >> b) | carries; + } + + return w.ll; +} + +EXPORT_SYMBOL(__lshrdi3); diff -Naur linux-2.6.17.13.orig/arch/mips/lib/Makefile linux-2.6.17.13/arch/mips/lib/Makefile --- linux-2.6.17.13.orig/arch/mips/lib/Makefile 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/lib/Makefile 2006-09-09 10:17:04.000000000 -0700 @@ -5,6 +5,7 @@ lib-y += csum_partial_copy.o memcpy.o promlib.o strlen_user.o strncpy_user.o \ strnlen_user.o uncached.o -obj-y += iomap.o +# libgcc-style stuff needed in the kernel +lib-y += ashldi3.o ashrdi3.o lshrdi3.o EXTRA_AFLAGS := $(CFLAGS) diff -Naur linux-2.6.17.13.orig/arch/mips/lib-32/dump_tlb.c linux-2.6.17.13/arch/mips/lib-32/dump_tlb.c --- linux-2.6.17.13.orig/arch/mips/lib-32/dump_tlb.c 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/lib-32/dump_tlb.c 2006-09-09 10:17:04.000000000 -0700 @@ -41,8 +41,6 @@ return "256Mb"; #endif } - - return "unknown"; } #define BARRIER() \ diff -Naur linux-2.6.17.13.orig/arch/mips/lib-64/dump_tlb.c linux-2.6.17.13/arch/mips/lib-64/dump_tlb.c --- linux-2.6.17.13.orig/arch/mips/lib-64/dump_tlb.c 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/lib-64/dump_tlb.c 2006-09-09 10:17:04.000000000 -0700 @@ -32,8 +32,6 @@ case PM_256M: return "256Mb"; #endif } - - return "unknown"; } #define BARRIER() \ diff -Naur linux-2.6.17.13.orig/arch/mips/Makefile linux-2.6.17.13/arch/mips/Makefile --- linux-2.6.17.13.orig/arch/mips/Makefile 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/Makefile 2006-09-09 10:17:04.000000000 -0700 @@ -83,6 +83,8 @@ LDFLAGS_vmlinux += -G 0 -static -n -nostdlib MODFLAGS += -mlong-calls +cflags-y += -ffreestanding + # # We explicitly add the endianness specifier if needed, this allows # to compile kernels with a toolchain for the other endianness. We @@ -365,6 +367,7 @@ cflags-$(CONFIG_PMC_YOSEMITE) += -Iinclude/asm-mips/mach-yosemite load-$(CONFIG_PMC_YOSEMITE) += 0xffffffff80100000 +# # Qemu simulating MIPS32 4Kc # core-$(CONFIG_QEMU) += arch/mips/qemu/ diff -Naur linux-2.6.17.13.orig/arch/mips/mips-boards/generic/memory.c linux-2.6.17.13/arch/mips/mips-boards/generic/memory.c --- linux-2.6.17.13.orig/arch/mips/mips-boards/generic/memory.c 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/mips-boards/generic/memory.c 2006-09-09 10:17:04.000000000 -0700 @@ -48,34 +48,45 @@ }; #endif +/* determined physical memory size, not overridden by command line args */ +unsigned long physical_memsize = 0L; + struct prom_pmemblock * __init prom_getmdesc(void) { char *memsize_str; unsigned int memsize; char cmdline[CL_SIZE], *ptr; - /* Check the command line first for a memsize directive */ + /* otherwise look in the environment */ + memsize_str = prom_getenv("memsize"); + if (!memsize_str) { + prom_printf("memsize not set in boot prom, set to default (32Mb)\n"); + physical_memsize = 0x02000000; + } else { +#ifdef DEBUG + prom_printf("prom_memsize = %s\n", memsize_str); +#endif + physical_memsize = simple_strtol(memsize_str, NULL, 0); + } + +#ifdef CONFIG_CPU_BIG_ENDIAN + /* SOC-it swaps, or perhaps doesn't swap, when DMA'ing the last + word of physical memory */ + physical_memsize -= PAGE_SIZE; +#endif + + /* Check the command line for a memsize directive that overrides + the physical/default amount */ strcpy(cmdline, arcs_cmdline); ptr = strstr(cmdline, "memsize="); if (ptr && (ptr != cmdline) && (*(ptr - 1) != ' ')) ptr = strstr(ptr, " memsize="); - if (ptr) { + if (ptr) memsize = memparse(ptr + 8, &ptr); - } - else { - /* otherwise look in the environment */ - memsize_str = prom_getenv("memsize"); - if (!memsize_str) { - prom_printf("memsize not set in boot prom, set to default (32Mb)\n"); - memsize = 0x02000000; - } else { -#ifdef DEBUG - prom_printf("prom_memsize = %s\n", memsize_str); -#endif - memsize = simple_strtol(memsize_str, NULL, 0); - } - } + else + memsize = physical_memsize; + memset(mdesc, 0, sizeof(mdesc)); mdesc[0].type = yamon_dontuse; diff -Naur linux-2.6.17.13.orig/arch/mips/mips-boards/malta/malta_int.c linux-2.6.17.13/arch/mips/mips-boards/malta/malta_int.c --- linux-2.6.17.13.orig/arch/mips/mips-boards/malta/malta_int.c 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/mips-boards/malta/malta_int.c 2006-09-09 10:17:04.000000000 -0700 @@ -208,23 +208,23 @@ unsigned int a0 = 7; unsigned int t0; - t0 = s0 & 0xf000; + t0 = pending & 0xf000; t0 = t0 < 1; t0 = t0 << 2; a0 = a0 - t0; - s0 = s0 << t0; + pending = pending << t0; - t0 = s0 & 0xc000; + t0 = pending & 0xc000; t0 = t0 < 1; t0 = t0 << 1; a0 = a0 - t0; - s0 = s0 << t0; + pending = pending << t0; - t0 = s0 & 0x8000; + t0 = pending & 0x8000; t0 = t0 < 1; //t0 = t0 << 2; a0 = a0 - t0; - //s0 = s0 << t0; + //pending = pending << t0; return a0; #endif diff -Naur linux-2.6.17.13.orig/arch/mips/mm/cache.c linux-2.6.17.13/arch/mips/mm/cache.c --- linux-2.6.17.13.orig/arch/mips/mm/cache.c 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/mm/cache.c 2006-09-09 10:17:04.000000000 -0700 @@ -26,7 +26,7 @@ void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn); void (*flush_icache_range)(unsigned long start, unsigned long end); -void (*flush_icache_page)(struct vm_area_struct *vma, struct page *page); +void (*__flush_icache_page)(struct vm_area_struct *vma, struct page *page); /* MIPS specific cache operations */ void (*flush_cache_sigtramp)(unsigned long addr); @@ -71,6 +71,8 @@ struct address_space *mapping = page_mapping(page); unsigned long addr; + if (PageHighMem(page)) + return; if (mapping && !mapping_mapped(mapping)) { SetPageDcacheDirty(page); return; @@ -92,16 +94,16 @@ { struct page *page; unsigned long pfn, addr; + int exec = (vma->vm_flags & VM_EXEC) && !cpu_has_ic_fills_f_dc; pfn = pte_pfn(pte); - if (pfn_valid(pfn) && (page = pfn_to_page(pfn), page_mapping(page)) && - Page_dcache_dirty(page)) { - if (pages_do_alias((unsigned long)page_address(page), - address & PAGE_MASK)) { - addr = (unsigned long) page_address(page); + if (unlikely(!pfn_valid(pfn))) + return; + page = pfn_to_page(pfn); + if (page_mapping(page) && Page_dcache_dirty(page)) { + addr = (unsigned long) page_address(page); + if (exec || pages_do_alias(addr, address & PAGE_MASK)) flush_data_cache_page(addr); - } - ClearPageDcacheDirty(page); } } diff -Naur linux-2.6.17.13.orig/arch/mips/mm/c-r3k.c linux-2.6.17.13/arch/mips/mm/c-r3k.c --- linux-2.6.17.13.orig/arch/mips/mm/c-r3k.c 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/mm/c-r3k.c 2006-09-09 10:17:04.000000000 -0700 @@ -335,7 +335,7 @@ flush_cache_mm = r3k_flush_cache_mm; flush_cache_range = r3k_flush_cache_range; flush_cache_page = r3k_flush_cache_page; - flush_icache_page = r3k_flush_icache_page; + __flush_icache_page = r3k_flush_icache_page; flush_icache_range = r3k_flush_icache_range; flush_cache_sigtramp = r3k_flush_cache_sigtramp; diff -Naur linux-2.6.17.13.orig/arch/mips/mm/c-r4k.c linux-2.6.17.13/arch/mips/mm/c-r4k.c --- linux-2.6.17.13.orig/arch/mips/mm/c-r4k.c 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/mm/c-r4k.c 2006-09-09 10:17:04.000000000 -0700 @@ -24,32 +24,12 @@ #include #include #include +#include #include #include #include #include /* for run_uncached() */ - -/* - * Special Variant of smp_call_function for use by cache functions: - * - * o No return value - * o collapses to normal function call on UP kernels - * o collapses to normal function call on systems with a single shared - * primary cache. - */ -static inline void r4k_on_each_cpu(void (*func) (void *info), void *info, - int retry, int wait) -{ - preempt_disable(); - -#if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC) - smp_call_function(func, info, retry, wait); -#endif - func(info); - preempt_enable(); -} - /* * Must die. */ @@ -60,13 +40,13 @@ /* * Dummy cache handling routines for machines without boardcaches */ -static void no_sc_noop(void) {} +static void cache_noop(void) {} static struct bcache_ops no_sc_ops = { - .bc_enable = (void *)no_sc_noop, - .bc_disable = (void *)no_sc_noop, - .bc_wback_inv = (void *)no_sc_noop, - .bc_inv = (void *)no_sc_noop + .bc_enable = (void *)cache_noop, + .bc_disable = (void *)cache_noop, + .bc_wback_inv = (void *)cache_noop, + .bc_inv = (void *)cache_noop }; struct bcache_ops *bcops = &no_sc_ops; @@ -94,7 +74,9 @@ { unsigned long dc_lsize = cpu_dcache_line_size(); - if (dc_lsize == 16) + if (dc_lsize == 0) + r4k_blast_dcache_page = (void *)cache_noop; + else if (dc_lsize == 16) r4k_blast_dcache_page = blast_dcache16_page; else if (dc_lsize == 32) r4k_blast_dcache_page = r4k_blast_dcache_page_dc32; @@ -106,7 +88,9 @@ { unsigned long dc_lsize = cpu_dcache_line_size(); - if (dc_lsize == 16) + if (dc_lsize == 0) + r4k_blast_dcache_page_indexed = (void *)cache_noop; + else if (dc_lsize == 16) r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed; else if (dc_lsize == 32) r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed; @@ -118,7 +102,9 @@ { unsigned long dc_lsize = cpu_dcache_line_size(); - if (dc_lsize == 16) + if (dc_lsize == 0) + r4k_blast_dcache = (void *)cache_noop; + else if (dc_lsize == 16) r4k_blast_dcache = blast_dcache16; else if (dc_lsize == 32) r4k_blast_dcache = blast_dcache32; @@ -201,7 +187,9 @@ { unsigned long ic_lsize = cpu_icache_line_size(); - if (ic_lsize == 16) + if (ic_lsize == 0) + r4k_blast_icache_page = (void *)cache_noop; + else if (ic_lsize == 16) r4k_blast_icache_page = blast_icache16_page; else if (ic_lsize == 32) r4k_blast_icache_page = blast_icache32_page; @@ -216,7 +204,9 @@ { unsigned long ic_lsize = cpu_icache_line_size(); - if (ic_lsize == 16) + if (ic_lsize == 0) + r4k_blast_icache_page_indexed = (void *)cache_noop; + else if (ic_lsize == 16) r4k_blast_icache_page_indexed = blast_icache16_page_indexed; else if (ic_lsize == 32) { if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x()) @@ -238,7 +228,9 @@ { unsigned long ic_lsize = cpu_icache_line_size(); - if (ic_lsize == 16) + if (ic_lsize == 0) + r4k_blast_icache = (void *)cache_noop; + else if (ic_lsize == 16) r4k_blast_icache = blast_icache16; else if (ic_lsize == 32) { if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x()) @@ -258,7 +250,7 @@ unsigned long sc_lsize = cpu_scache_line_size(); if (scache_size == 0) - r4k_blast_scache_page = (void *)no_sc_noop; + r4k_blast_scache_page = (void *)cache_noop; else if (sc_lsize == 16) r4k_blast_scache_page = blast_scache16_page; else if (sc_lsize == 32) @@ -276,7 +268,7 @@ unsigned long sc_lsize = cpu_scache_line_size(); if (scache_size == 0) - r4k_blast_scache_page_indexed = (void *)no_sc_noop; + r4k_blast_scache_page_indexed = (void *)cache_noop; else if (sc_lsize == 16) r4k_blast_scache_page_indexed = blast_scache16_page_indexed; else if (sc_lsize == 32) @@ -294,7 +286,7 @@ unsigned long sc_lsize = cpu_scache_line_size(); if (scache_size == 0) - r4k_blast_scache = (void *)no_sc_noop; + r4k_blast_scache = (void *)cache_noop; else if (sc_lsize == 16) r4k_blast_scache = blast_scache16; else if (sc_lsize == 32) @@ -320,7 +312,7 @@ if (!cpu_has_dc_aliases) return; - r4k_on_each_cpu(local_r4k_flush_cache_all, NULL, 1, 1); + __on_each_core(local_r4k_flush_cache_all, NULL); } static inline void local_r4k___flush_cache_all(void * args) @@ -342,7 +334,7 @@ static void r4k___flush_cache_all(void) { - r4k_on_each_cpu(local_r4k___flush_cache_all, NULL, 1, 1); + __on_each_core(local_r4k___flush_cache_all, NULL); } static inline void local_r4k_flush_cache_range(void * args) @@ -363,7 +355,7 @@ static void r4k_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) { - r4k_on_each_cpu(local_r4k_flush_cache_range, vma, 1, 1); + __on_each_core(local_r4k_flush_cache_range, vma); } static inline void local_r4k_flush_cache_mm(void * args) @@ -392,7 +384,7 @@ if (!cpu_has_dc_aliases) return; - r4k_on_each_cpu(local_r4k_flush_cache_mm, mm, 1, 1); + __on_each_core(local_r4k_flush_cache_mm, mm); } struct flush_cache_page_args { @@ -464,7 +456,7 @@ } } if (exec) { - if (cpu_has_vtag_icache) { + if (cpu_has_vtag_icache && mm == current->active_mm) { int cpu = smp_processor_id(); if (cpu_context(cpu, mm) != 0) @@ -483,7 +475,7 @@ args.addr = addr; args.pfn = pfn; - r4k_on_each_cpu(local_r4k_flush_cache_page, &args, 1, 1); + __on_each_core(local_r4k_flush_cache_page, &args); } static inline void local_r4k_flush_data_cache_page(void * addr) @@ -493,7 +485,7 @@ static void r4k_flush_data_cache_page(unsigned long addr) { - r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr, 1, 1); + __on_each_core(local_r4k_flush_data_cache_page, (void *) addr); } struct flush_icache_range_args { @@ -508,7 +500,7 @@ unsigned long end = fir_args->end; if (!cpu_has_ic_fills_f_dc) { - if (end - start > dcache_size) { + if (end - start >= dcache_size) { r4k_blast_dcache(); } else { R4600_HIT_CACHEOP_WAR_IMPL; @@ -536,7 +528,7 @@ args.start = start; args.end = end; - r4k_on_each_cpu(local_r4k_flush_icache_range, &args, 1, 1); + __on_each_core(local_r4k_flush_icache_range, &args); instruction_hazard(); } @@ -588,7 +580,7 @@ * We're not sure of the virtual address(es) involved here, so * we have to flush the entire I-cache. */ - if (cpu_has_vtag_icache) { + if (cpu_has_vtag_icache && vma->vm_mm == current->active_mm) { int cpu = smp_processor_id(); if (cpu_context(cpu, vma->vm_mm) != 0) @@ -612,7 +604,7 @@ args.vma = vma; args.page = page; - r4k_on_each_cpu(local_r4k_flush_icache_page, &args, 1, 1); + __on_each_core(local_r4k_flush_icache_page, &args); } @@ -683,10 +675,12 @@ unsigned long addr = (unsigned long) arg; R4600_HIT_CACHEOP_WAR_IMPL; - protected_writeback_dcache_line(addr & ~(dc_lsize - 1)); + if (dc_lsize) + protected_writeback_dcache_line(addr & ~(dc_lsize - 1)); if (!cpu_icache_snoops_remote_store && scache_size) protected_writeback_scache_line(addr & ~(sc_lsize - 1)); - protected_flush_icache_line(addr & ~(ic_lsize - 1)); + if (ic_lsize) + protected_flush_icache_line(addr & ~(ic_lsize - 1)); if (MIPS4K_ICACHE_REFILL_WAR) { __asm__ __volatile__ ( ".set push\n\t" @@ -711,7 +705,7 @@ static void r4k_flush_cache_sigtramp(unsigned long addr) { - r4k_on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr, 1, 1); + __on_each_core(local_r4k_flush_cache_sigtramp, (void *) addr); } static void r4k_flush_icache_all(void) @@ -973,8 +967,10 @@ c->icache.waysize = icache_size / c->icache.ways; c->dcache.waysize = dcache_size / c->dcache.ways; - c->icache.sets = icache_size / (c->icache.linesz * c->icache.ways); - c->dcache.sets = dcache_size / (c->dcache.linesz * c->dcache.ways); + c->icache.sets = c->icache.linesz ? + icache_size / (c->icache.linesz * c->icache.ways) : 0; + c->dcache.sets = c->dcache.linesz ? + dcache_size / (c->dcache.linesz * c->dcache.ways) : 0; /* * R10000 and R12000 P-caches are odd in a positive way. They're 32kB @@ -993,10 +989,15 @@ break; case CPU_24K: case CPU_34K: - if (!(read_c0_config7() & (1 << 16))) + if ((read_c0_config7() & (1 << 16))) { + /* effectively physically indexed dcache, + thus no virtual aliases. */ + c->dcache.flags |= MIPS_CACHE_PINDEX; + break; + } default: - if (c->dcache.waysize > PAGE_SIZE) - c->dcache.flags |= MIPS_CACHE_ALIASES; + if (c->dcache.waysize > PAGE_SIZE) + c->dcache.flags |= MIPS_CACHE_ALIASES; } switch (c->cputype) { @@ -1092,6 +1093,7 @@ extern int r5k_sc_init(void); extern int rm7k_sc_init(void); +extern int mips_sc_init(void); static void __init setup_scache(void) { @@ -1139,17 +1141,29 @@ return; default: + if (c->isa_level == MIPS_CPU_ISA_M32R1 || + c->isa_level == MIPS_CPU_ISA_M32R2 || + c->isa_level == MIPS_CPU_ISA_M64R1 || + c->isa_level == MIPS_CPU_ISA_M64R2) { +#ifdef CONFIG_MIPS_CPU_SCACHE + if (mips_sc_init ()) { + scache_size = c->scache.ways * c->scache.sets * c->scache.linesz; + printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n", + scache_size >> 10, + way_string[c->scache.ways], c->scache.linesz); + } +#else + if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT)) + panic("Dunno how to handle MIPS32 / MIPS64 second level cache"); +#endif + return; + } sc_present = 0; } if (!sc_present) return; - if ((c->isa_level == MIPS_CPU_ISA_M32R1 || - c->isa_level == MIPS_CPU_ISA_M64R1) && - !(c->scache.flags & MIPS_CACHE_NOT_PRESENT)) - panic("Dunno how to handle MIPS32 / MIPS64 second level cache"); - /* compute a couple of other cache variables */ c->scache.waysize = scache_size / c->scache.ways; @@ -1246,15 +1260,17 @@ * This code supports virtually indexed processors and will be * unnecessarily inefficient on physically indexed processors. */ - shm_align_mask = max_t( unsigned long, - c->dcache.sets * c->dcache.linesz - 1, - PAGE_SIZE - 1); - + if (c->dcache.linesz) + shm_align_mask = max_t( unsigned long, + c->dcache.sets * c->dcache.linesz - 1, + PAGE_SIZE - 1); + else + shm_align_mask = PAGE_SIZE-1; flush_cache_all = r4k_flush_cache_all; __flush_cache_all = r4k___flush_cache_all; flush_cache_mm = r4k_flush_cache_mm; flush_cache_page = r4k_flush_cache_page; - flush_icache_page = r4k_flush_icache_page; + __flush_icache_page = r4k_flush_icache_page; flush_cache_range = r4k_flush_cache_range; flush_cache_sigtramp = r4k_flush_cache_sigtramp; diff -Naur linux-2.6.17.13.orig/arch/mips/mm/c-sb1.c linux-2.6.17.13/arch/mips/mm/c-sb1.c --- linux-2.6.17.13.orig/arch/mips/mm/c-sb1.c 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/mm/c-sb1.c 2006-09-09 10:17:04.000000000 -0700 @@ -156,6 +156,26 @@ } /* + * Invalidate a range of the icache. The addresses are virtual, and + * the cache is virtually indexed and tagged. However, we don't + * necessarily have the right ASID context, so use index ops instead + * of hit ops. + */ +static inline void __sb1_flush_icache_range(unsigned long start, + unsigned long end) +{ + start &= ~(icache_line_size - 1); + end = (end + icache_line_size - 1) & ~(icache_line_size - 1); + + while (start != end) { + cache_set_op(Index_Invalidate_I, start & icache_index_mask); + start += icache_line_size; + } + mispredict(); + sync(); +} + +/* * Flush the icache for a given physical page. Need to writeback the * dcache first, then invalidate the icache. If the page isn't * executable, nothing is required. @@ -174,8 +194,11 @@ /* * Bumping the ASID is probably cheaper than the flush ... */ - if (cpu_context(cpu, vma->vm_mm) != 0) - drop_mmu_context(vma->vm_mm, cpu); + if (vma->vm_mm == current->active_mm) { + if (cpu_context(cpu, vma->vm_mm) != 0) + drop_mmu_context(vma->vm_mm, cpu); + } else + __sb1_flush_icache_range(addr, addr + PAGE_SIZE); } #ifdef CONFIG_SMP @@ -211,26 +234,6 @@ __attribute__((alias("local_sb1_flush_cache_page"))); #endif -/* - * Invalidate a range of the icache. The addresses are virtual, and - * the cache is virtually indexed and tagged. However, we don't - * necessarily have the right ASID context, so use index ops instead - * of hit ops. - */ -static inline void __sb1_flush_icache_range(unsigned long start, - unsigned long end) -{ - start &= ~(icache_line_size - 1); - end = (end + icache_line_size - 1) & ~(icache_line_size - 1); - - while (start != end) { - cache_set_op(Index_Invalidate_I, start & icache_index_mask); - start += icache_line_size; - } - mispredict(); - sync(); -} - /* * Invalidate all caches on this CPU @@ -327,9 +330,12 @@ * If there's a context, bump the ASID (cheaper than a flush, * since we don't know VAs!) */ - if (cpu_context(cpu, vma->vm_mm) != 0) { - drop_mmu_context(vma->vm_mm, cpu); - } + if (vma->vm_mm == current->active_mm) { + if (cpu_context(cpu, vma->vm_mm) != 0) + drop_mmu_context(vma->vm_mm, cpu); + } else + __sb1_flush_icache_range(start, start + PAGE_SIZE); + } #ifdef CONFIG_SMP @@ -521,7 +527,7 @@ /* These routines are for Icache coherence with the Dcache */ flush_icache_range = sb1_flush_icache_range; - flush_icache_page = sb1_flush_icache_page; + __flush_icache_page = sb1_flush_icache_page; flush_icache_all = __sb1_flush_icache_all; /* local only */ /* This implies an Icache flush too, so can't be nop'ed */ diff -Naur linux-2.6.17.13.orig/arch/mips/mm/c-tx39.c linux-2.6.17.13/arch/mips/mm/c-tx39.c --- linux-2.6.17.13.orig/arch/mips/mm/c-tx39.c 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/mm/c-tx39.c 2006-09-09 10:17:04.000000000 -0700 @@ -382,7 +382,7 @@ flush_cache_mm = (void *) tx39h_flush_icache_all; flush_cache_range = (void *) tx39h_flush_icache_all; flush_cache_page = (void *) tx39h_flush_icache_all; - flush_icache_page = (void *) tx39h_flush_icache_all; + __flush_icache_page = (void *) tx39h_flush_icache_all; flush_icache_range = (void *) tx39h_flush_icache_all; flush_cache_sigtramp = (void *) tx39h_flush_icache_all; @@ -408,7 +408,7 @@ flush_cache_mm = tx39_flush_cache_mm; flush_cache_range = tx39_flush_cache_range; flush_cache_page = tx39_flush_cache_page; - flush_icache_page = tx39_flush_icache_page; + __flush_icache_page = tx39_flush_icache_page; flush_icache_range = tx39_flush_icache_range; flush_cache_sigtramp = tx39_flush_cache_sigtramp; diff -Naur linux-2.6.17.13.orig/arch/mips/mm/init.c linux-2.6.17.13/arch/mips/mm/init.c --- linux-2.6.17.13.orig/arch/mips/mm/init.c 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/mm/init.c 2006-09-09 10:17:04.000000000 -0700 @@ -31,11 +31,39 @@ #include #include #include +#include #include #include #include #include #include +#include + +/* CP0 hazard avoidance. */ +#define BARRIER __asm__ __volatile__(".set noreorder\n\t" \ + "nop; nop; nop; nop; nop; nop;\n\t" \ + ".set reorder\n\t") + +/* Atomicity and interruptability */ +#ifdef CONFIG_MIPS_MT_SMTC + +#include + +#define ENTER_CRITICAL(flags) \ + { \ + unsigned int mvpflags; \ + local_irq_save(flags);\ + mvpflags = dvpe() +#define EXIT_CRITICAL(flags) \ + evpe(mvpflags); \ + local_irq_restore(flags); \ + } +#else + +#define ENTER_CRITICAL(flags) local_irq_save(flags) +#define EXIT_CRITICAL(flags) local_irq_restore(flags) + +#endif /* CONFIG_MIPS_MT_SMTC */ DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); @@ -81,13 +109,183 @@ return 1UL << order; } -#ifdef CONFIG_HIGHMEM -pte_t *kmap_pte; -pgprot_t kmap_prot; +/* + * These are almost like kmap_atomic / kunmap_atmic except they take an + * additional address argument as the hint. + */ #define kmap_get_fixmap_pte(vaddr) \ pte_offset_kernel(pmd_offset(pud_offset(pgd_offset_k(vaddr), (vaddr)), (vaddr)), (vaddr)) +#ifdef CONFIG_MIPS_MT_SMTC +static pte_t *kmap_coherent_pte; +static void __init kmap_coherent_init(void) +{ + unsigned long vaddr; + + /* cache the first coherent kmap pte */ + vaddr = __fix_to_virt(FIX_CMAP_BEGIN); + kmap_coherent_pte = kmap_get_fixmap_pte(vaddr); +} +#else +static inline void kmap_coherent_init(void) {} +#endif + +static inline void *kmap_coherent(struct page *page, unsigned long addr) +{ + enum fixed_addresses idx; + unsigned long vaddr, flags, entrylo; + unsigned long old_ctx; + pte_t pte; + unsigned int tlbidx; + + inc_preempt_count(); + idx = (addr >> PAGE_SHIFT) & (FIX_N_COLOURS - 1); +#ifdef CONFIG_MIPS_MT_SMTC + idx += FIX_N_COLOURS * smp_processor_id(); +#endif + vaddr = __fix_to_virt(FIX_CMAP_END - idx); + pte = mk_pte(page, PAGE_KERNEL); +#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) + entrylo = pte.pte_high; +#else + entrylo = pte_val(pte) >> 6; +#endif + + ENTER_CRITICAL(flags); + old_ctx = read_c0_entryhi(); + write_c0_entryhi(vaddr & (PAGE_MASK << 1)); + write_c0_entrylo0(entrylo); + write_c0_entrylo1(entrylo); +#ifdef CONFIG_MIPS_MT_SMTC + set_pte(kmap_coherent_pte - (FIX_CMAP_END - idx), pte); + /* preload TLB instead of local_flush_tlb_one() */ + mtc0_tlbw_hazard(); + tlb_probe(); + BARRIER; + tlbidx = read_c0_index(); + mtc0_tlbw_hazard(); + if (tlbidx < 0) + tlb_write_random(); + else + tlb_write_indexed(); +#else + tlbidx = read_c0_wired(); + write_c0_wired(tlbidx + 1); + write_c0_index(tlbidx); + mtc0_tlbw_hazard(); + tlb_write_indexed(); +#endif + tlbw_use_hazard(); + write_c0_entryhi(old_ctx); + EXIT_CRITICAL(flags); + + return (void*) vaddr; +} + +#define UNIQUE_ENTRYHI(idx) (CKSEG0 + ((idx) << (PAGE_SHIFT + 1))) + +static inline void kunmap_coherent(struct page *page) +{ +#ifndef CONFIG_MIPS_MT_SMTC + unsigned int wired; + unsigned long flags, old_ctx; + + ENTER_CRITICAL(flags); + old_ctx = read_c0_entryhi(); + wired = read_c0_wired() - 1; + write_c0_wired(wired); + write_c0_index(wired); + write_c0_entryhi(UNIQUE_ENTRYHI(wired)); + write_c0_entrylo0(0); + write_c0_entrylo1(0); + mtc0_tlbw_hazard(); + tlb_write_indexed(); + write_c0_entryhi(old_ctx); + EXIT_CRITICAL(flags); +#endif + dec_preempt_count(); + preempt_check_resched(); +} + +void copy_user_highpage(struct page *to, struct page *from, + unsigned long vaddr, struct vm_area_struct *vma) +{ + void *vfrom, *vto; + + vto = kmap_atomic(to, KM_USER1); + if (cpu_has_dc_aliases) { + vfrom = kmap_coherent(from, vaddr); + copy_page(vto, vfrom); + kunmap_coherent(from); + } else { + vfrom = kmap_atomic(from, KM_USER0); + copy_page(vto, vfrom); + kunmap_atomic(vfrom, KM_USER0); + } + if (((vma->vm_flags & VM_EXEC) && !cpu_has_ic_fills_f_dc) || + pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK)) + flush_data_cache_page((unsigned long)vto); + kunmap_atomic(vto, KM_USER1); + /* Make sure this page is cleared on other CPU's too before using it */ + smp_wmb(); +} + +EXPORT_SYMBOL(copy_user_highpage); + +void copy_user_page(void *vto, void *vfrom, unsigned long vaddr, + struct page *to) +{ + if (cpu_has_dc_aliases) { + struct page *from = virt_to_page(vfrom); + vfrom = kmap_coherent(from, vaddr); + copy_page(vto, vfrom); + kunmap_coherent(from); + } else + copy_page(vto, vfrom); + if (!cpu_has_ic_fills_f_dc || + pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK)) + flush_data_cache_page((unsigned long)vto); +} + +EXPORT_SYMBOL(copy_user_page); + +void copy_to_user_page(struct vm_area_struct *vma, + struct page *page, unsigned long vaddr, void *dst, const void *src, + unsigned long len) +{ + if (cpu_has_dc_aliases) { + void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK); + memcpy(vto, src, len); + kunmap_coherent(page); + } else + memcpy(dst, src, len); + if ((vma->vm_flags & VM_EXEC) && !cpu_has_ic_fills_f_dc) + flush_cache_page(vma, vaddr, page_to_pfn(page)); +} + +EXPORT_SYMBOL(copy_to_user_page); + +void copy_from_user_page(struct vm_area_struct *vma, + struct page *page, unsigned long vaddr, void *dst, const void *src, + unsigned long len) +{ + if (cpu_has_dc_aliases) { + void *vfrom = + kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK); + memcpy(dst, vfrom, len); + kunmap_coherent(page); + } else + memcpy(dst, src, len); +} + +EXPORT_SYMBOL(copy_from_user_page); + + +#ifdef CONFIG_HIGHMEM +pte_t *kmap_pte; +pgprot_t kmap_prot; + static void __init kmap_init(void) { unsigned long kmap_vstart; @@ -98,11 +296,12 @@ kmap_prot = PAGE_KERNEL; } +#endif /* CONFIG_HIGHMEM */ -#ifdef CONFIG_32BIT void __init fixrange_init(unsigned long start, unsigned long end, pgd_t *pgd_base) { +#if defined(CONFIG_HIGHMEM) || defined(CONFIG_MIPS_MT_SMTC) pgd_t *pgd; pud_t *pud; pmd_t *pmd; @@ -123,7 +322,7 @@ for (; (k < PTRS_PER_PMD) && (vaddr != end); pmd++, k++) { if (pmd_none(*pmd)) { pte = (pte_t *) alloc_bootmem_low_pages(PAGE_SIZE); - set_pmd(pmd, __pmd(pte)); + set_pmd(pmd, __pmd((unsigned long)pte)); if (pte != pte_offset_kernel(pmd, 0)) BUG(); } @@ -133,9 +332,8 @@ } j = 0; } +#endif } -#endif /* CONFIG_32BIT */ -#endif /* CONFIG_HIGHMEM */ #ifndef CONFIG_NEED_MULTIPLE_NODES extern void pagetable_init(void); @@ -150,6 +348,7 @@ #ifdef CONFIG_HIGHMEM kmap_init(); #endif + kmap_coherent_init(); max_dma = virt_to_phys((char *)MAX_DMA_ADDRESS) >> PAGE_SHIFT; low = max_low_pfn; diff -Naur linux-2.6.17.13.orig/arch/mips/mm/Makefile linux-2.6.17.13/arch/mips/mm/Makefile --- linux-2.6.17.13.orig/arch/mips/mm/Makefile 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/mm/Makefile 2006-09-09 10:17:04.000000000 -0700 @@ -30,6 +30,7 @@ obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o obj-$(CONFIG_RM7000_CPU_SCACHE) += sc-rm7k.o +obj-$(CONFIG_MIPS_CPU_SCACHE) += sc-mips.o # # Choose one DMA coherency model diff -Naur linux-2.6.17.13.orig/arch/mips/mm/pgtable-32.c linux-2.6.17.13/arch/mips/mm/pgtable-32.c --- linux-2.6.17.13.orig/arch/mips/mm/pgtable-32.c 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/mm/pgtable-32.c 2006-09-09 10:17:04.000000000 -0700 @@ -32,9 +32,10 @@ void __init pagetable_init(void) { -#ifdef CONFIG_HIGHMEM unsigned long vaddr; - pgd_t *pgd, *pgd_base; + pgd_t *pgd_base; +#ifdef CONFIG_HIGHMEM + pgd_t *pgd; pud_t *pud; pmd_t *pmd; pte_t *pte; @@ -45,7 +46,6 @@ pgd_init((unsigned long)swapper_pg_dir + sizeof(pgd_t) * USER_PTRS_PER_PGD); -#ifdef CONFIG_HIGHMEM pgd_base = swapper_pg_dir; /* @@ -54,6 +54,7 @@ vaddr = __fix_to_virt(__end_of_fixed_addresses - 1) & PMD_MASK; fixrange_init(vaddr, 0, pgd_base); +#ifdef CONFIG_HIGHMEM /* * Permanent kmaps: */ diff -Naur linux-2.6.17.13.orig/arch/mips/mm/pgtable-64.c linux-2.6.17.13/arch/mips/mm/pgtable-64.c --- linux-2.6.17.13.orig/arch/mips/mm/pgtable-64.c 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/mm/pgtable-64.c 2006-09-09 10:17:04.000000000 -0700 @@ -8,6 +8,7 @@ */ #include #include +#include #include void pgd_init(unsigned long page) @@ -52,7 +53,17 @@ void __init pagetable_init(void) { + unsigned long vaddr; + pgd_t *pgd_base; + /* Initialize the entire pgd. */ pgd_init((unsigned long)swapper_pg_dir); pmd_init((unsigned long)invalid_pmd_table, (unsigned long)invalid_pte_table); + + pgd_base = swapper_pg_dir; + /* + * Fixed mappings: + */ + vaddr = __fix_to_virt(__end_of_fixed_addresses - 1) & PMD_MASK; + fixrange_init(vaddr, 0, pgd_base); } diff -Naur linux-2.6.17.13.orig/arch/mips/mm/sc-mips.c linux-2.6.17.13/arch/mips/mm/sc-mips.c --- linux-2.6.17.13.orig/arch/mips/mm/sc-mips.c 1969-12-31 16:00:00.000000000 -0800 +++ linux-2.6.17.13/arch/mips/mm/sc-mips.c 2006-09-09 10:17:04.000000000 -0700 @@ -0,0 +1,112 @@ +/* + * Copyright (C) 2006 Chris Dearman (chris@mips.com), + */ +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * MIPS32/MIPS64 L2 cache handling + */ + +/* + * Writeback and invalidate the secondary cache before DMA. + */ +static void mips_sc_wback_inv(unsigned long addr, unsigned long size) +{ + blast_scache_range(addr, addr + size); +} + +/* + * Invalidate the secondary cache before DMA. + */ +static void mips_sc_inv(unsigned long addr, unsigned long size) +{ + blast_inv_scache_range(addr, addr + size); +} + +static void mips_sc_enable(void) +{ + /* L2 cache is permanently enabled */ +} + +static void mips_sc_disable(void) +{ + /* L2 cache is permanently enabled */ +} + +static struct bcache_ops mips_sc_ops = { + .bc_enable = mips_sc_enable, + .bc_disable = mips_sc_disable, + .bc_wback_inv = mips_sc_wback_inv, + .bc_inv = mips_sc_inv +}; + +static inline int __init mips_sc_probe(void) +{ + struct cpuinfo_mips *c = ¤t_cpu_data; + unsigned int config1, config2; + unsigned int tmp; + + /* Mark as not present until probe completed */ + c->scache.flags |= MIPS_CACHE_NOT_PRESENT; + + /* Ignore anything but MIPSxx processors */ + if (c->isa_level != MIPS_CPU_ISA_M32R1 && + c->isa_level != MIPS_CPU_ISA_M32R2 && + c->isa_level != MIPS_CPU_ISA_M64R1 && + c->isa_level != MIPS_CPU_ISA_M64R2) + return 0; + + /* Does this MIPS32/MIPS64 CPU have a config2 register? */ + config1 = read_c0_config1(); + if (!(config1 & MIPS_CONF_M)) + return 0; + + config2 = read_c0_config2(); + tmp = (config2 >> 4) & 0x0f; + if (0 < tmp && tmp <= 7) + c->scache.linesz = 2 << tmp; + else + return 0; + + tmp = (config2 >> 8) & 0x0f; + if (0 <= tmp && tmp <= 7) + c->scache.sets = 64 << tmp; + else + return 0; + + tmp = (config2 >> 0) & 0x0f; + if (0 <= tmp && tmp <= 7) + c->scache.ways = tmp + 1; + else + return 0; + + c->scache.waysize = c->scache.sets * c->scache.linesz; + c->scache.waybit = __ffs(c->scache.waysize); + + c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; + + return 1; +} + +int __init mips_sc_init(void) +{ + int found = mips_sc_probe (); + if (found) { + mips_sc_enable(); + bcops = &mips_sc_ops; + } + return found; +} + diff -Naur linux-2.6.17.13.orig/arch/mips/pci/fixup-tb0219.c linux-2.6.17.13/arch/mips/pci/fixup-tb0219.c --- linux-2.6.17.13.orig/arch/mips/pci/fixup-tb0219.c 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/pci/fixup-tb0219.c 2006-09-09 10:17:04.000000000 -0700 @@ -2,7 +2,7 @@ * fixup-tb0219.c, The TANBAC TB0219 specific PCI fixups. * * Copyright (C) 2003 Megasolution Inc. - * Copyright (C) 2004 Yoichi Yuasa + * Copyright (C) 2004-2005 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff -Naur linux-2.6.17.13.orig/arch/mips/pci/ops-au1000.c linux-2.6.17.13/arch/mips/pci/ops-au1000.c --- linux-2.6.17.13.orig/arch/mips/pci/ops-au1000.c 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/pci/ops-au1000.c 2006-09-09 10:17:04.000000000 -0700 @@ -111,7 +111,7 @@ if (first_cfg) { /* reserve a wired entry for pci config accesses */ first_cfg = 0; - pci_cfg_vm = get_vm_area(0x2000, 0); + pci_cfg_vm = get_vm_area(0x2000, VM_IOREMAP); if (!pci_cfg_vm) panic (KERN_ERR "PCI unable to get vm area\n"); pci_cfg_wired_entry = read_c0_wired(); diff -Naur linux-2.6.17.13.orig/arch/mips/qemu/Makefile linux-2.6.17.13/arch/mips/qemu/Makefile --- linux-2.6.17.13.orig/arch/mips/qemu/Makefile 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/qemu/Makefile 2006-09-09 10:17:04.000000000 -0700 @@ -4,4 +4,5 @@ obj-y = q-firmware.o q-irq.o q-mem.o q-setup.o +obj-$(CONFIG_VT) += q-vga.o obj-$(CONFIG_SMP) += q-smp.o diff -Naur linux-2.6.17.13.orig/arch/mips/qemu/q-setup.c linux-2.6.17.13/arch/mips/qemu/q-setup.c --- linux-2.6.17.13.orig/arch/mips/qemu/q-setup.c 2006-09-08 20:23:25.000000000 -0700 +++ linux-2.6.17.13/arch/mips/qemu/q-setup.c 2006-09-09 10:17:04.000000000 -0700 @@ -2,6 +2,8 @@ #include #include +extern void qvga_init(void); + #define QEMU_PORT_BASE 0xb4000000 const char *get_system_type(void) @@ -21,5 +23,8 @@ void __init plat_setup(void) { set_io_port_base(QEMU_PORT_BASE); +#ifdef CONFIG_VT + qvga_init(); +#endif board_timer_setup = qemu_timer_setup; } diff -Naur linux-2.6.17.13.orig/arch/mips/qemu/q-vga.c linux-2.6.17.13/arch/mips/qemu/q-vga.c --- linux-2.6.17.13.orig/arch/mips/qemu/q-vga.c 1969-12-31 16:00:00.000000000 -0800 +++ linux-2.6.17.13/arch/mips/qemu/q-vga.c 2006-09-09 10:17:04.000000000 -0700 @@ -0,0 +1,188 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2005 by Ralf Baechle (ralf@linux-mips.org) + * + * This will eventually go into the qemu firmware. + */ +#include +#include +#include +#include