source: patches/linux-2.6.17.11-mips_fixes-1.patch@ bf76de5

arch/mips/kernel/Makefile

@@ -54 +54 @@
 obj-$(CONFIG_64BIT)             += scall64-64.o
 obj-$(CONFIG_BINFMT_IRIX)       += binfmt_irix.o
 obj-$(CONFIG_MIPS32_COMPAT)     += linux32.o signal32.o
-obj-$(CONFIG_MIPS32_N32)        += binfmt_elfn32.o scall64-n32.o signal_n32.o
+obj-$(CONFIG_MIPS32_N32)        += binfmt_elfn32.o scall64-n32.o signal_n32.o ptrace32.o
 obj-$(CONFIG_MIPS32_O32)        += binfmt_elfo32.o scall64-o32.o ptrace32.o
 
 obj-$(CONFIG_KGDB)              += gdb-low.o gdb-stub.o

arch/mips/lib/Makefile

@@ -5 +5 @@
 lib-y   += csum_partial_copy.o memcpy.o promlib.o strlen_user.o strncpy_user.o \
            strnlen_user.o uncached.o
 
+obj-y   += iomap.o
+
 # libgcc-style stuff needed in the kernel
 lib-y += ashldi3.o ashrdi3.o lshrdi3.o
 

arch/mips/lib/ashldi3.c

@@ +1 @@
+#include <linux/module.h>
+
+#include "libgcc.h"
+
+long long __ashldi3(long long u, word_type b)
+{
+        DWunion uu, w;
+        word_type bm;
+
+        if (b == 0)
+                return u;
+
+        uu.ll = u;
+        bm = 32 - b;
+
+        if (bm <= 0) {
+                w.s.low = 0;
+                w.s.high = (unsigned int) uu.s.low << -bm;
+        } else {
+                const unsigned int carries = (unsigned int) uu.s.low >> bm;
+
+                w.s.low = (unsigned int) uu.s.low << b;
+                w.s.high = ((unsigned int) uu.s.high << b) | carries;
+        }
+
+        return w.ll;
+}
+
+EXPORT_SYMBOL(__ashldi3);

arch/mips/lib/ashrdi3.c

@@ +1 @@
+#include <linux/module.h>
+
+#include "libgcc.h"
+
+long long __ashrdi3(long long u, word_type b)
+{
+        DWunion uu, w;
+        word_type bm;
+
+        if (b == 0)
+                return u;
+
+        uu.ll = u;
+        bm = 32 - b;
+
+        if (bm <= 0) {
+                /* w.s.high = 1..1 or 0..0 */
+                w.s.high =
+                    uu.s.high >> 31;
+                w.s.low = uu.s.high >> -bm;
+        } else {
+                const unsigned int carries = (unsigned int) uu.s.high << bm;
+
+                w.s.high = uu.s.high >> b;
+                w.s.low = ((unsigned int) uu.s.low >> b) | carries;
+        }
+
+        return w.ll;
+}
+
+EXPORT_SYMBOL(__ashrdi3);

arch/mips/lib/iomap.c

@@ +1 @@
+/*
+ *  iomap.c, Memory Mapped I/O routines for MIPS architecture.
+ *
+ *  This code is based on lib/iomap.c, by Linus Torvalds.
+ *
+ *  Copyright (C) 2004-2005  Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/ioport.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+
+#include <asm/io.h>
+
+void __iomem *ioport_map(unsigned long port, unsigned int nr)
+{
+        unsigned long end;
+
+        end = port + nr - 1UL;
+        if (ioport_resource.start > port ||
+            ioport_resource.end < end || port > end)
+                return NULL;
+
+        return (void __iomem *)(mips_io_port_base + port);
+}
+
+void ioport_unmap(void __iomem *addr)
+{
+}
+EXPORT_SYMBOL(ioport_map);
+EXPORT_SYMBOL(ioport_unmap);
+
+void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
+{
+        unsigned long start, len, flags;
+
+        if (dev == NULL)
+                return NULL;
+
+        start = pci_resource_start(dev, bar);
+        len = pci_resource_len(dev, bar);
+        if (!start || !len)
+                return NULL;
+
+        if (maxlen != 0 && len > maxlen)
+                len = maxlen;
+
+        flags = pci_resource_flags(dev, bar);
+        if (flags & IORESOURCE_IO)
+                return ioport_map(start, len);
+        if (flags & IORESOURCE_MEM) {
+                if (flags & IORESOURCE_CACHEABLE)
+                        return ioremap_cachable(start, len);
+                return ioremap_nocache(start, len);
+        }
+
+        return NULL;
+}
+
+void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
+{
+        iounmap(addr);
+}
+EXPORT_SYMBOL(pci_iomap);
+EXPORT_SYMBOL(pci_iounmap);

arch/mips/lib/libgcc.h

@@ +1 @@
+#ifndef __ASM_LIBGCC_H
+#define __ASM_LIBGCC_H
+
+#include <asm/byteorder.h>
+
+typedef int word_type __attribute__ ((mode (__word__)));
+
+#ifdef __BIG_ENDIAN
+struct DWstruct {
+        int high, low;
+};
+#elif defined(__LITTLE_ENDIAN)
+struct DWstruct {
+        int low, high;
+};
+#else
+#error I feel sick.
+#endif
+
+typedef union
+{
+        struct DWstruct s;
+        long long ll;
+} DWunion;
+
+#endif /* __ASM_LIBGCC_H */

arch/mips/lib/lshrdi3.c

@@ +1 @@
+#include <linux/module.h>
+
+#include "libgcc.h"
+
+long long __lshrdi3(long long u, word_type b)
+{
+        DWunion uu, w;
+        word_type bm;
+
+        if (b == 0)
+                return u;
+
+        uu.ll = u;
+        bm = 32 - b;
+
+        if (bm <= 0) {
+                w.s.high = 0;
+                w.s.low = (unsigned int) uu.s.high >> -bm;
+        } else {
+                const unsigned int carries = (unsigned int) uu.s.high << bm;
+
+                w.s.high = (unsigned int) uu.s.high >> b;
+                w.s.low = ((unsigned int) uu.s.low >> b) | carries;
+        }
+
+        return w.ll;
+}
+
+EXPORT_SYMBOL(__lshrdi3);

include/asm-mips/io.h

@@ -519 +519 @@
 }
 
 /*
+ * Memory Mapped I/O
+ */
+#define ioread8(addr)           readb(addr)
+#define ioread16(addr)          readw(addr)
+#define ioread32(addr)          readl(addr)
+
+#define iowrite8(b,addr)        writeb(b,addr)
+#define iowrite16(w,addr)       writew(w,addr)
+#define iowrite32(l,addr)       writel(l,addr)
+
+#define ioread8_rep(a,b,c)      readsb(a,b,c)
+#define ioread16_rep(a,b,c)     readsw(a,b,c)
+#define ioread32_rep(a,b,c)     readsl(a,b,c)
+
+#define iowrite8_rep(a,b,c)     writesb(a,b,c)
+#define iowrite16_rep(a,b,c)    writesw(a,b,c)
+#define iowrite32_rep(a,b,c)    writesl(a,b,c)
+
+/* Create a virtual mapping cookie for an IO port range */
+extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
+extern void ioport_unmap(void __iomem *);
+
+/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
+struct pci_dev;
+extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
+extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
+
+/*
  * ISA space is 'always mapped' on currently supported MIPS systems, no need
  * to explicitly ioremap() it. The fact that the ISA IO space is mapped
  * to PAGE_OFFSET is pure coincidence - it does not mean ISA values

include/asm-mips/mach-cobalt/ide.h

@@ +1 @@
+
+/*
+ * PIO "in" transfers can cause D-cache lines to be allocated
+ * to the data being read. If the target is the page cache then
+ * the kernel can create a user space mapping of the same page
+ * without flushing it from the D-cache. This has large potential
+ * to create cache aliases. The Cobalts seem to trigger this
+ * problem easily.
+ *
+ * MIPs doesn't have a flush_dcache_range() so we roll
+ * our own.
+ *
+ * -- pdh
+ */
+
+#define MAX_HWIFS                       2
+
+#include <asm/r4kcache.h>
+
+static inline void __flush_dcache(void)
+{
+        unsigned long dc_size, dc_line, addr, end;
+
+        dc_size = current_cpu_data.dcache.ways << current_cpu_data.dcache.waybit;
+        dc_line = current_cpu_data.dcache.linesz;
+
+        addr = CKSEG0;
+        end = addr + dc_size;
+
+        for (; addr < end; addr += dc_line)
+                flush_dcache_line_indexed(addr);
+}
+
+static inline void __flush_dcache_range(unsigned long start, unsigned long end)
+{
+        unsigned long dc_size, dc_line, addr;
+
+        dc_size = current_cpu_data.dcache.ways << current_cpu_data.dcache.waybit;
+        dc_line = current_cpu_data.dcache.linesz;
+
+        addr = start & ~(dc_line - 1);
+        end += dc_line - 1;
+
+        if (end - addr < dc_size)
+                for (; addr < end; addr += dc_line)
+                        flush_dcache_line(addr);
+        else
+                __flush_dcache();
+}
+
+static inline void __ide_insw(unsigned long port, void *addr, unsigned int count)
+{
+        insw(port, addr, count);
+
+        __flush_dcache_range((unsigned long) addr, (unsigned long) addr + count * 2);
+}
+
+static inline void __ide_insl(unsigned long port, void *addr, unsigned int count)
+{
+        insl(port, addr, count);
+
+        __flush_dcache_range((unsigned long) addr, (unsigned long) addr + count * 4);
+}
+
+static inline void __ide_mm_insw(volatile void __iomem *port, void *addr, unsigned int count)
+{
+        readsw(port, addr, count);
+
+        __flush_dcache_range((unsigned long) addr, (unsigned long) addr + count * 2);
+}
+
+static inline void __ide_mm_insl(volatile void __iomem *port, void *addr, unsigned int count)
+{
+        readsl(port, addr, count);
+
+        __flush_dcache_range((unsigned long) addr, (unsigned long) addr + count * 4);
+}
+
+#define insw                    __ide_insw
+#define insl                    __ide_insl
+
+#define __ide_mm_outsw          writesw
+#define __ide_mm_outsl          writesl