source: patches/gcc-4.6.3-mips_fix-1.patch@ ec40e5f

clfs-2.1 clfs-3.0.0-systemd clfs-3.0.0-sysvinit systemd sysvinit
Last change on this file since ec40e5f was 736bb57, checked in by Jonathan Norman <jon@…>, 13 years ago

Renamed GCC 4.6.2 patches to 4.6.3
  • Property mode set to 100644
File size: 5.1 KB

  • gcc/expmed.c 

    Submitted By: Jonathan Norman (jonathan at bluesquarelinux.co.uk)
Date: 2011-07-12
Initial Package Version: 4.6.0
Origin: Upstream
Upstream Status: Applied
Description: Fixes a issue with Mips that causes GCC to setfault
             when using optimation greater than -O0. Taken from
             GCC Revision 174541 and applied to GCC 4.6.0

diff -Naur gcc-4.6.0.orig/gcc/expmed.c gcc-4.6.0/gcc/expmed.c
    old new  
    14311431      unsigned int nwords = (bitsize + (BITS_PER_WORD - 1)) / BITS_PER_WORD;
    14321432      unsigned int i;
    14331433
    1434       if (target == 0 || !REG_P (target))
     1434      if (target == 0 || !REG_P (target) || !valid_multiword_target_p (target))
    14351435        target = gen_reg_rtx (mode);
    14361436
    14371437      /* Indicate for flow that the entire target reg is being set.  */

  • gcc/optabs.c 

    diff -Naur gcc-4.6.0.orig/gcc/optabs.c gcc-4.6.0/gcc/optabs.c
    old new  
    16941694
    16951695      /* If TARGET is the same as one of the operands, the REG_EQUAL note
    16961696         won't be accurate, so use a new target.  */
    1697       if (target == 0 || target == op0 || target == op1)
     1697      if (target == 0
     1698          || target == op0
     1699          || target == op1
     1700          || !valid_multiword_target_p (target))
    16981701        target = gen_reg_rtx (mode);
    16991702
    17001703      start_sequence ();
    … …  
    17621765
    17631766          /* If TARGET is the same as one of the operands, the REG_EQUAL note
    17641767             won't be accurate, so use a new target.  */
    1765           if (target == 0 || target == op0 || target == op1)
     1768          if (target == 0
     1769              || target == op0
     1770              || target == op1
     1771              || !valid_multiword_target_p (target))
    17661772            target = gen_reg_rtx (mode);
    17671773
    17681774          start_sequence ();
    … …  
    18161822         opportunities, and second because if target and op0 happen to be MEMs
    18171823         designating the same location, we would risk clobbering it too early
    18181824         in the code sequence we generate below.  */
    1819       if (target == 0 || target == op0 || target == op1 || ! REG_P (target))
     1825      if (target == 0
     1826          || target == op0
     1827          || target == op1
     1828          || !REG_P (target)
     1829          || !valid_multiword_target_p (target))
    18201830        target = gen_reg_rtx (mode);
    18211831
    18221832      start_sequence ();
    … …  
    19361946
    19371947      xtarget = gen_reg_rtx (mode);
    19381948
    1939       if (target == 0 || !REG_P (target))
     1949      if (target == 0 || !REG_P (target) || !valid_multiword_target_p (target))
    19401950        target = xtarget;
    19411951
    19421952      /* Indicate for flow that the entire target reg is being set.  */
    … …  
    26892699  t0 = expand_unop (word_mode, bswap_optab,
    26902700                    operand_subword_force (op, 1, mode), NULL_RTX, true);
    26912701
    2692   if (target == 0)
     2702  if (target == 0 || !valid_multiword_target_p (target))
    26932703    target = gen_reg_rtx (mode);
    26942704  if (REG_P (target))
    26952705    emit_clobber (target);
    … …  
    29322942  if (code == ABS)
    29332943    mask = double_int_not (mask);
    29342944
    2935   if (target == 0 || target == op0)
     2945  if (target == 0
     2946      || target == op0
     2947      || (nwords > 1 && !valid_multiword_target_p (target)))
    29362948    target = gen_reg_rtx (mode);
    29372949
    29382950  if (nwords > 1)
    … …  
    31403152      int i;
    31413153      rtx insns;
    31423154
    3143       if (target == 0 || target == op0)
     3155      if (target == 0 || target == op0 || !valid_multiword_target_p (target))
    31443156        target = gen_reg_rtx (mode);
    31453157
    31463158      start_sequence ();
    … …  
    36113623
    36123624  mask = double_int_setbit (double_int_zero, bitpos);
    36133625
    3614   if (target == 0 || target == op0 || target == op1)
     3626  if (target == 0
     3627      || target == op0
     3628      || target == op1
     3629      || (nwords > 1 && !valid_multiword_target_p (target)))
    36153630    target = gen_reg_rtx (mode);
    36163631
    36173632  if (nwords > 1)
    … …  
    73307345  return NULL_RTX;
    73317346}
    73327347
     7348/* TARGET is a target of a multiword operation that we are going to
     7349   implement as a series of word-mode operations.  Return true if
     7350   TARGET is suitable for this purpose.  */
     7351
     7352bool
     7353valid_multiword_target_p (rtx target)
     7354{
     7355  enum machine_mode mode;
     7356  int i;
     7357
     7358  mode = GET_MODE (target);
     7359  for (i = 0; i < GET_MODE_SIZE (mode); i += UNITS_PER_WORD)
     7360    if (!validate_subreg (word_mode, mode, target, i))
     7361      return false;
     7362  return true;
     7363}
     7364
    73337365#include "gt-optabs.h"

  • gcc/optabs.h 

    diff -Naur gcc-4.6.0.orig/gcc/optabs.h gcc-4.6.0/gcc/optabs.h
    old new  
    923923extern rtx optab_libfunc (optab optab, enum machine_mode mode);
    924924extern rtx convert_optab_libfunc (convert_optab optab, enum machine_mode mode1,
    925925                                  enum machine_mode mode2);
     926
     927extern bool valid_multiword_target_p (rtx);
    926928#endif /* GCC_OPTABS_H */

  • gcc/testsuite/gcc.target/mips/pr45074.c 

    diff -Naur gcc-4.6.0.orig/gcc/testsuite/gcc.target/mips/pr45074.c gcc-4.6.0/gcc/testsuite/gcc.target/mips/pr45074.c
    old new  
     1/* { dg-options "-mhard-float -mgp32 -O" } */
     2register double g __asm__("$f20");
     3
     4NOMIPS16 void
     5test (double a)
     6{
     7  g = -a;
     8}
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