source: patches/coreutils-5.96-uname-1.patch @ f71c005

clfs-1.2clfs-2.1clfs-3.0.0-systemdclfs-3.0.0-sysvinitsystemdsysvinit
Last change on this file since f71c005 was f71c005, checked in by Jim Gifford <clfs@…>, 18 years ago

Updated Coreutils Patches

  • Property mode set to 100644
File size: 4.5 KB
RevLine 
[69cde8d]1Submitted By: Matthew Burgess <matthew at linuxfromscratch dot org>
2Date: 2005-10-23
3Initial Package Version: 5.92
4Upstream Status: pending
5Origin: Scot McPherson
6Description: Fix the output of uname once and for all.
7
8        $ uname -m      # This always worked.
9        i686
10        $ uname -i      # Used to report 'unknown'.
11        i386
12        $ uname -p      # Likewise.
13        athlon-4
14
15diff -Naur coreutils-5.92.orig/src/uname.c coreutils-5.92/src/uname.c
16--- coreutils-5.92.orig/src/uname.c     2005-09-15 20:34:42.000000000 +0000
17+++ coreutils-5.92/src/uname.c  2005-10-23 10:14:06.000000000 +0000
18@@ -29,6 +29,12 @@
19 # include <sys/systeminfo.h>
20 #endif
21 
22+#ifdef linux
23+#define cpuid(in,a,b,c,d)\
24+  asm("cpuid": "=a" (a), "=b" (b), "=c" (c), "=d" (d) : "a" (in));
25+int has_sse( void );
26+#endif
27+
28 #if HAVE_SYS_SYSCTL_H
29 # if HAVE_SYS_PARAM_H
30 #  include <sys/param.h> /* needed for OpenBSD 3.0 */
31@@ -256,6 +262,96 @@
32        if (0 <= sysinfo (SI_ARCHITECTURE, processor, sizeof processor))
33          element = processor;
34       }
35+#else
36+      {
37+       struct utsname u;
38+       uname (&u);
39+       element = u.machine;
40+#ifdef linux
41+/******************************************************************************
42+ *
43+ * Hello, major hack.  I shouldn't have to do this.  struct utsname should
44+ * have another element with this info in it.  There's probably a struct
45+ * somewhere that has this info, I just don't know where it is.
46+ *
47+ *****************************************************************************/
48+
49+       if( !strcmp( element, "i586" ) || !strcmp( element, "i686" ) ) {
50+         int eax, ebx, ecx, edx, unused;
51+         int model, family, sse;
52+     
53+         cpuid(0,unused,ebx,ecx,edx);
54+         cpuid(1,eax,unused,unused,unused);
55+         model = (eax >> 4) & 0xf;
56+         family = (eax >> 8) & 0xf;
57+
58+         switch(ebx) {
59+         case 0x756e6547: // Intel
60+           switch( family ) {
61+           case 5: // Pentium
62+             if( model <= 3 )
63+               element="pentium";
64+             if( model > 3 )
65+               element="pentium-mmx";
66+             break;
67+           case 6: // PentiumPro - Pentium III
68+             if( model == 1 ) // Pentium Pro
69+               element="pentiumpro";
70+             if( ( model == 3 ) || ( model == 5 ) ||
71+                 ( model == 6 ) ) // Pentium II
72+               element="pentium2";
73+             if( ( model == 7 ) || ( model == 8 ) ||
74+                 ( model == 10 ) || ( model == 11 ) ) // These are all Pentium III
75+               element="pentium3";
76+             break;
77+           case 15: // Pentium4
78+             element="pentium4";
79+             break;
80+           default:
81+             break;
82+           } // end switch( family )
83+           break;
84+         case 0x68747541: // AMD
85+           switch(family) {
86+           case 5:
87+             if( ( model == 0 ) || ( model == 1 ) ||
88+                 ( model == 2 ) || ( model == 3 ) ) // K5
89+               element="i586";
90+             if( ( model == 6 ) || ( model == 7 ) ) // K6
91+               element="k6";
92+             if( model == 8 ) // K6-2
93+               element="k6-2";
94+             if( model == 9 ) // K6-3
95+               element="k6-3";
96+             break;
97+           case 6:
98+             if( model <= 4 )
99+               element="athlon";
100+             if( model > 4 ) {
101+               sse = has_sse();
102+               if( sse == 0 )
103+                 element="athlon";
104+               if( sse == 1 )
105+                 element="athlon-4";
106+             }
107+             break;
108+           case 15:
109+             element="athlon-4";
110+             break;
111+           default:
112+             break;
113+           } // end switch( family )
114+           break;
115+         case 0x69727943: // Cyrix
116+           element="i386"; // who knows what cyrix supports, lets be safe
117+           break;
118+         default:
119+           break;
120+         } // end switch(ebx)
121+       }
122+
123+#endif
124+      }
125 #endif
126 #ifdef UNAME_PROCESSOR
127       if (element == unknown)
128@@ -293,7 +389,7 @@
129 
130   if (toprint & PRINT_HARDWARE_PLATFORM)
131     {
132-      char const *element = unknown;
133+      char *element = unknown;
134 #if HAVE_SYSINFO && defined SI_PLATFORM
135       {
136        static char hardware_platform[257];
137@@ -301,6 +397,15 @@
138                          hardware_platform, sizeof hardware_platform))
139          element = hardware_platform;
140       }
141+#else
142+      {
143+       struct utsname u;
144+       uname (&u);
145+       element = u.machine;
146+       if (strlen (element) == 4 && element[0] == 'i' && element[2] == '8'
147+           && element[3] == '6')
148+         element[1] = '3';
149+      }
150 #endif
151 #ifdef UNAME_HARDWARE_PLATFORM
152       if (element == unknown)
153@@ -323,3 +428,29 @@
154 
155   exit (EXIT_SUCCESS);
156 }
157+
158+#ifdef linux
159+
160+/******************************************************************************
161+ *
162+ * int has_sse( void )
163+ * Checks Athlon CPU's to see if they support SSE.
164+ *
165+ *****************************************************************************/
166+
167+int has_sse( void )
168+{
169+  unsigned long edx, unused;
170+  int sse;
171+  cpuid(1,unused,unused,unused,edx);
172+  // I think, I need this tested on a Duron with SSE
173+  // and one without it.
174+  sse = edx & 0x2000000;
175+  if( sse == 0 ) {
176+    return 0;
177+  } else {
178+    return 1;
179+  }
180+
181+}
182+#endif
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