source: clfs-embedded/patches/linux-2.6.19-bcm947xx-1.patch@ b80b6a7

arch/mips/Kconfig

@@ -4 +4 @@
         # Horrible source of confusion.  Die, die, die ...
         select EMBEDDED
 
+config CFE
+        bool
+        # Common Firmware Environment
+
 mainmenu "Linux/MIPS Kernel Configuration"
 
 menu "Machine selection"
@@ -222 +226 @@
          Members include the Acer PICA, MIPS Magnum 4000, MIPS Millenium and
          Olivetti M700-10 workstations.
 
+config BCM947XX
+        bool "Support for BCM947xx based boards"
+        select DMA_NONCOHERENT
+        select HW_HAS_PCI
+        select IRQ_CPU
+        select SYS_HAS_CPU_MIPS32_R1
+        select SYS_SUPPORTS_32BIT_KERNEL
+        select SYS_SUPPORTS_LITTLE_ENDIAN
+        select MIPS_CPU_SCACHE
+        select SSB
+        select SSB_DRIVER_MIPS
+        select SSB_DRIVER_EXTIF
+        select CFE
+        help
+         Support for BCM947xx based boards
+
 config LASAT
         bool "LASAT Networks platforms"
         select DMA_NONCOHERENT

arch/mips/Makefile

@@ -571 +571 @@
 load-$(CONFIG_SIBYTE_BIGSUR)    := 0xffffffff80100000
 
 #
+# Broadcom BCM47XX boards
+#
+core-$(CONFIG_BCM947XX)         += arch/mips/bcm947xx/
+cflags-$(CONFIG_BCM947XX)       += -Iarch/mips/bcm947xx/include -Iinclude/asm-mips/mach-bcm947xx
+load-$(CONFIG_BCM947XX)         := 0xffffffff80001000
+
+#
+# Common Firmware Environment
+#
+core-$(CONFIG_CFE)              += arch/mips/cfe/
+
+#
 # SNI RM200 PCI
 #
 core-$(CONFIG_SNI_RM200_PCI)    += arch/mips/sni/

arch/mips/bcm947xx/Makefile

@@ +1 @@
+#
+# Makefile for the BCM47xx specific kernel interface routines
+# under Linux.
+#
+
+obj-y := irq.o prom.o setup.o time.o
+obj-y += nvram.o cfe_env.o
+#obj-y += pci.o

arch/mips/bcm947xx/cfe_env.c

@@ +1 @@
+/*
+ * CFE environment varialble access
+ *
+ * Copyright 2006, Felix Fietkau <nbd@openwrt.org>
+ * 
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ * Copyright 2001-2003, Broadcom Corporation
+ * 
+ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
+ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
+ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <asm/io.h>
+#include <asm/uaccess.h>
+
+#define NVRAM_SIZE       (0x1ff0)
+static char _nvdata[NVRAM_SIZE] __initdata;
+static char _valuestr[256] __initdata;
+
+/*
+ * TLV types.  These codes are used in the "type-length-value"
+ * encoding of the items stored in the NVRAM device (flash or EEPROM)
+ *
+ * The layout of the flash/nvram is as follows:
+ *
+ * <type> <length> <data ...> <type> <length> <data ...> <type_end>
+ *
+ * The type code of "ENV_TLV_TYPE_END" marks the end of the list.
+ * The "length" field marks the length of the data section, not
+ * including the type and length fields.
+ *
+ * Environment variables are stored as follows:
+ *
+ * <type_env> <length> <flags> <name> = <value>
+ *
+ * If bit 0 (low bit) is set, the length is an 8-bit value.
+ * If bit 0 (low bit) is clear, the length is a 16-bit value
+ * 
+ * Bit 7 set indicates "user" TLVs.  In this case, bit 0 still
+ * indicates the size of the length field.  
+ *
+ * Flags are from the constants below:
+ *
+ */
+#define ENV_LENGTH_16BITS       0x00    /* for low bit */
+#define ENV_LENGTH_8BITS        0x01
+
+#define ENV_TYPE_USER           0x80
+
+#define ENV_CODE_SYS(n,l) (((n)<<1)|(l))
+#define ENV_CODE_USER(n,l) ((((n)<<1)|(l)) | ENV_TYPE_USER)
+
+/*
+ * The actual TLV types we support
+ */
+
+#define ENV_TLV_TYPE_END        0x00    
+#define ENV_TLV_TYPE_ENV        ENV_CODE_SYS(0,ENV_LENGTH_8BITS)
+
+/*
+ * Environment variable flags 
+ */
+
+#define ENV_FLG_NORMAL          0x00    /* normal read/write */
+#define ENV_FLG_BUILTIN         0x01    /* builtin - not stored in flash */
+#define ENV_FLG_READONLY        0x02    /* read-only - cannot be changed */
+
+#define ENV_FLG_MASK            0xFF    /* mask of attributes we keep */
+#define ENV_FLG_ADMIN           0x100   /* lets us internally override permissions */
+
+
+/*  *********************************************************************
+    *  _nvram_read(buffer,offset,length)
+    *  
+    *  Read data from the NVRAM device
+    *  
+    *  Input parameters: 
+    *      buffer - destination buffer
+    *      offset - offset of data to read
+    *      length - number of bytes to read
+    *      
+    *  Return value:
+    *      number of bytes read, or <0 if error occured
+    ********************************************************************* */
+static int
+_nvram_read(unsigned char *nv_buf, unsigned char *buffer, int offset, int length)
+{
+    int i;
+    if (offset > NVRAM_SIZE)
+        return -1; 
+
+    for ( i = 0; i < length; i++) {
+        buffer[i] = ((volatile unsigned char*)nv_buf)[offset + i];
+    }
+    return length;
+}
+
+
+static char*
+_strnchr(const char *dest,int c,size_t cnt)
+{
+        while (*dest && (cnt > 0)) {
+        if (*dest == c) return (char *) dest;
+        dest++;
+        cnt--;
+        }
+        return NULL;
+}
+
+
+
+/*
+ * Core support API: Externally visible.
+ */
+
+/*
+ * Get the value of an NVRAM variable
+ * @param       name    name of variable to get
+ * @return      value of variable or NULL if undefined
+ */
+
+char* 
+cfe_env_get(unsigned char *nv_buf, char* name)
+{
+    int size;
+    unsigned char *buffer;
+    unsigned char *ptr;
+    unsigned char *envval;
+    unsigned int reclen;
+    unsigned int rectype;
+    int offset;
+    int flg;
+    
+    size = NVRAM_SIZE;
+    buffer = &_nvdata[0];
+
+    ptr = buffer;
+    offset = 0;
+
+    /* Read the record type and length */
+    if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
+        goto error;
+    }
+    
+    while ((*ptr != ENV_TLV_TYPE_END)  && (size > 1)) {
+
+        /* Adjust pointer for TLV type */
+        rectype = *(ptr);
+        offset++;
+        size--;
+
+        /* 
+         * Read the length.  It can be either 1 or 2 bytes
+         * depending on the code 
+         */
+        if (rectype & ENV_LENGTH_8BITS) {
+            /* Read the record type and length - 8 bits */
+            if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
+                goto error;
+            }
+            reclen = *(ptr);
+            size--;
+            offset++;
+        }
+        else {
+            /* Read the record type and length - 16 bits, MSB first */
+            if (_nvram_read(nv_buf, ptr,offset,2) != 2) {
+                goto error;
+            }
+            reclen = (((unsigned int) *(ptr)) << 8) + (unsigned int) *(ptr+1);
+            size -= 2;
+            offset += 2;
+        }
+
+        if (reclen > size)
+            break;      /* should not happen, bad NVRAM */
+
+        switch (rectype) {
+            case ENV_TLV_TYPE_ENV:
+                /* Read the TLV data */
+                if (_nvram_read(nv_buf, ptr,offset,reclen) != reclen)
+                    goto error;
+                flg = *ptr++;
+                envval = (unsigned char *) _strnchr(ptr,'=',(reclen-1));
+                if (envval) {
+                    *envval++ = '\0';
+                    memcpy(_valuestr,envval,(reclen-1)-(envval-ptr));
+                    _valuestr[(reclen-1)-(envval-ptr)] = '\0';
+#if 0                   
+                    printk(KERN_INFO "NVRAM:%s=%s\n", ptr, _valuestr);
+#endif
+                    if(!strcmp(ptr, name)){
+                        return _valuestr;
+                    }
+                    if((strlen(ptr) > 1) && !strcmp(&ptr[1], name))
+                        return _valuestr;
+                }
+                break;
+                
+            default: 
+                /* Unknown TLV type, skip it. */
+                break;
+            }
+
+        /*
+         * Advance to next TLV 
+         */
+                
+        size -= (int)reclen;
+        offset += reclen;
+
+        /* Read the next record type */
+        ptr = buffer;
+        if (_nvram_read(nv_buf, ptr,offset,1) != 1)
+            goto error;
+        }
+
+error:
+    return NULL;
+
+}
+

arch/mips/bcm947xx/include/nvram.h

@@ +1 @@
+/*
+ *  Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+
+#ifndef __NVRAM_H
+#define __NVRAM_H
+
+struct nvram_header {
+        u32 magic;
+        u32 len;
+        u32 crc_ver_init;       /* 0:7 crc, 8:15 ver, 16:31 sdram_init */
+        u32 config_refresh;     /* 0:15 sdram_config, 16:31 sdram_refresh */
+        u32 config_ncdl;        /* ncdl values for memc */
+};
+
+struct nvram_tuple {
+        char *name;
+        char *value;
+        struct nvram_tuple *next;
+};
+
+#define NVRAM_HEADER            0x48534C46      /* 'FLSH' */
+#define NVRAM_VERSION           1
+#define NVRAM_HEADER_SIZE       20
+#define NVRAM_SPACE             0x8000
+
+#define NVRAM_MAX_VALUE_LEN 255
+#define NVRAM_MAX_PARAM_LEN 64
+
+char *nvram_get(const char *name);
+
+#endif

arch/mips/bcm947xx/irq.c

@@ +1 @@
+/*
+ *  Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/module.h>
+#include <linux/smp.h>
+#include <linux/types.h>
+
+#include <asm/cpu.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/irq_cpu.h>
+
+void plat_irq_dispatch(void)
+{
+        u32 cause;
+
+        cause = read_c0_cause() & read_c0_status() & CAUSEF_IP;
+
+        clear_c0_status(cause);
+
+        if (cause & CAUSEF_IP7)
+                do_IRQ(7);
+        if (cause & CAUSEF_IP2)
+                do_IRQ(2);
+        if (cause & CAUSEF_IP3)
+                do_IRQ(3);
+        if (cause & CAUSEF_IP4)
+                do_IRQ(4);
+        if (cause & CAUSEF_IP5)
+                do_IRQ(5);
+        if (cause & CAUSEF_IP6)
+                do_IRQ(6);
+}
+
+void __init arch_init_irq(void)
+{
+        mips_cpu_irq_init(0);
+}

arch/mips/bcm947xx/nvram.c

@@ +1 @@
+/*
+ * BCM947xx nvram variable access
+ *
+ * Copyright 2006, Felix Fietkau <nbd@openwrt.org>
+ * 
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ *
+ * Copyright 2005, Broadcom Corporation
+ * 
+ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
+ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
+ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/ssb.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+#include <linux/slab.h>
+#include <asm/byteorder.h>
+#include <asm/bootinfo.h>
+#include <asm/addrspace.h>
+#include <asm/io.h>
+#include <asm/uaccess.h>
+
+#include <nvram.h>
+
+#define MB * 1048576
+extern struct ssb_bus ssb;
+
+static char nvram_buf[NVRAM_SPACE];
+static int cfe_env;
+extern char *cfe_env_get(char *nv_buf, const char *name);
+                
+/* Probe for NVRAM header */
+static void __init early_nvram_init(void)
+{
+        struct ssb_mipscore *mcore = &ssb.mipscore;
+        struct nvram_header *header;
+        int i;
+        u32 base, lim, off;
+        u32 *src, *dst;
+        
+        base = mcore->flash_window;
+        lim = mcore->flash_window_size;
+        cfe_env = 0;
+
+        
+        /* XXX: hack for supporting the CFE environment stuff on WGT634U */
+        if (lim >= 8 MB) {
+                src = (u32 *) KSEG1ADDR(base + 8 MB - 0x2000);
+                dst = (u32 *) nvram_buf;
+
+                if ((*src & 0xff00ff) == 0x000001) {
+                        printk("early_nvram_init: WGT634U NVRAM found.\n");
+
+                        for (i = 0; i < 0x1ff0; i++) {
+                                if (*src == 0xFFFFFFFF)
+                                        break;
+                                *dst++ = *src++;
+                        }
+                        cfe_env = 1;
+                        return;
+                }
+        }
+
+        off = 0x20000;
+        while (off <= lim) {
+                /* Windowed flash access */
+                header = (struct nvram_header *) KSEG1ADDR(base + off - NVRAM_SPACE);
+                if (header->magic == NVRAM_HEADER)
+                        goto found;
+                off <<= 1;
+        }
+
+        /* Try embedded NVRAM at 4 KB and 1 KB as last resorts */
+        header = (struct nvram_header *) KSEG1ADDR(base + 4096);
+        if (header->magic == NVRAM_HEADER)
+                goto found;
+        
+        header = (struct nvram_header *) KSEG1ADDR(base + 1024);
+        if (header->magic == NVRAM_HEADER)
+                goto found;
+        
+        return;
+
+found:
+        src = (u32 *) header;
+        dst = (u32 *) nvram_buf;
+        for (i = 0; i < sizeof(struct nvram_header); i += 4)
+                *dst++ = *src++;
+        for (; i < header->len && i < NVRAM_SPACE; i += 4)
+                *dst++ = le32_to_cpu(*src++);
+}
+
+char *nvram_get(const char *name)
+{
+        char *var, *value, *end, *eq;
+
+        if (!name)
+                return NULL;
+
+        if (!nvram_buf[0])
+                early_nvram_init();
+
+        if (cfe_env)
+                return cfe_env_get(nvram_buf, name);
+
+        /* Look for name=value and return value */
+        var = &nvram_buf[sizeof(struct nvram_header)];
+        end = nvram_buf + sizeof(nvram_buf) - 2;
+        end[0] = end[1] = '\0';
+        for (; *var; var = value + strlen(value) + 1) {
+                if (!(eq = strchr(var, '=')))
+                        break;
+                value = eq + 1;
+                if ((eq - var) == strlen(name) && strncmp(var, name, (eq - var)) == 0)
+                        return value;
+        }
+
+        return NULL;
+}

arch/mips/bcm947xx/pci.c

@@ +1 @@
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/types.h>
+
+#include <asm/cpu.h>
+#include <asm/io.h>
+
+#include <typedefs.h>
+#include <osl.h>
+#include <sbutils.h>
+#include <sbmips.h>
+#include <sbconfig.h>
+#include <sbpci.h>
+#include <bcmdevs.h>
+#include <pcicfg.h>
+
+extern sb_t *sbh;
+extern spinlock_t sbh_lock;
+
+
+static int
+sb_pci_read_config(struct pci_bus *bus, unsigned int devfn,
+                                int reg, int size, u32 *val)
+{
+        int ret;
+        unsigned long flags;
+        
+        spin_lock_irqsave(&sbh_lock, flags);
+        ret = sbpci_read_config(sbh, bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), reg, val, size);
+        spin_unlock_irqrestore(&sbh_lock, flags);
+
+        return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
+}
+
+static int
+sb_pci_write_config(struct pci_bus *bus, unsigned int devfn,
+                                int reg, int size, u32 val)
+{
+        int ret;
+        unsigned long flags;
+        
+        spin_lock_irqsave(&sbh_lock, flags);
+        ret = sbpci_write_config(sbh, bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), reg, &val, size);
+        spin_unlock_irqrestore(&sbh_lock, flags);
+
+        return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
+}
+
+
+static struct pci_ops sb_pci_ops = {
+        .read   = sb_pci_read_config,
+        .write  = sb_pci_write_config,
+};
+
+static struct resource sb_pci_mem_resource = {
+        .name   = "SB PCI Memory resources",
+        .start  = SB_ENUM_BASE,
+        .end    = SB_ENUM_LIM - 1,
+        .flags  = IORESOURCE_MEM,
+};
+
+static struct resource sb_pci_io_resource = {
+        .name   = "SB PCI I/O resources",
+        .start  = 0x000,
+        .end    = 0x0FF,
+        .flags  = IORESOURCE_IO,
+};
+
+static struct pci_controller bcm47xx_sb_pci_controller = {
+        .pci_ops        = &sb_pci_ops,
+        .mem_resource   = &sb_pci_mem_resource,
+        .io_resource    = &sb_pci_io_resource,
+};
+
+static struct resource ext_pci_mem_resource = {
+        .name   = "Ext PCI Memory resources",
+        .start  = 0x40000000,
+        .end    = 0x7fffffff,
+        .flags  = IORESOURCE_MEM,
+};
+
+static struct resource ext_pci_io_resource = {
+        .name   = "Ext PCI I/O resources",
+        .start  = 0x100,
+        .end    = 0x7FF,
+        .flags  = IORESOURCE_IO,
+};
+
+static struct pci_controller bcm47xx_ext_pci_controller = {
+        .pci_ops        = &sb_pci_ops,
+        .io_resource    = &ext_pci_io_resource,
+        .mem_resource   = &ext_pci_mem_resource,
+        .mem_offset             = 0x24000000,
+};
+
+void bcm47xx_pci_init(void)
+{
+        unsigned long flags;
+        
+        spin_lock_irqsave(&sbh_lock, flags);
+        sbpci_init(sbh);
+        spin_unlock_irqrestore(&sbh_lock, flags);
+
+        set_io_port_base((unsigned long) ioremap_nocache(SB_PCI_MEM, 0x04000000));
+
+        register_pci_controller(&bcm47xx_sb_pci_controller);
+        register_pci_controller(&bcm47xx_ext_pci_controller);
+}
+
+int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+        unsigned long flags;
+        u8 irq;
+        uint idx;
+        
+        /* external: use the irq of the pci core */
+        if (dev->bus->number >= 1) {
+                spin_lock_irqsave(&sbh_lock, flags);
+                idx = sb_coreidx(sbh);
+                sb_setcore(sbh, SB_PCI, 0);
+                irq = sb_irq(sbh);
+                sb_setcoreidx(sbh, idx);
+                spin_unlock_irqrestore(&sbh_lock, flags);
+                
+                return irq + 2;
+        }
+        
+        /* internal */
+        pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
+        return irq + 2;
+}
+
+u32 pci_iobase = 0x100;
+u32 pci_membase = SB_PCI_DMA;
+
+static void bcm47xx_fixup_device(struct pci_dev *d)
+{
+        struct resource *res;
+        int pos, size;
+        u32 *base;
+
+        if (d->bus->number == 0)
+                return;
+        
+        printk("PCI: Fixing up device %s\n", pci_name(d));
+
+        /* Fix up resource bases */
+        for (pos = 0; pos < 6; pos++) {
+                res = &d->resource[pos];
+                base = ((res->flags & IORESOURCE_IO) ? &pci_iobase : &pci_membase);
+                if (res->end) {
+                        size = res->end - res->start + 1;
+                        if (*base & (size - 1))
+                                *base = (*base + size) & ~(size - 1);
+                        res->start = *base;
+                        res->end = res->start + size - 1;
+                        *base += size;
+                        pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
+                }
+                /* Fix up PCI bridge BAR0 only */
+                if (d->bus->number == 1 && PCI_SLOT(d->devfn) == 0)
+                        break;
+        }
+        /* Fix up interrupt lines */
+        if (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))
+                d->irq = (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))->irq;
+        pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
+}
+
+
+static void bcm47xx_fixup_bridge(struct pci_dev *dev)
+{
+        if (dev->bus->number != 1 || PCI_SLOT(dev->devfn) != 0)
+                return;
+        
+        printk("PCI: fixing up bridge\n");
+
+        /* Enable PCI bridge bus mastering and memory space */
+        pci_set_master(dev);
+        pcibios_enable_device(dev, ~0);
+        
+        /* Enable PCI bridge BAR1 prefetch and burst */
+        pci_write_config_dword(dev, PCI_BAR1_CONTROL, 3);
+}
+
+/* Do platform specific device initialization at pci_enable_device() time */
+int pcibios_plat_dev_init(struct pci_dev *dev)
+{
+        uint coreidx;
+        unsigned long flags;
+        
+        bcm47xx_fixup_device(dev);
+
+        /* These cores come out of reset enabled */
+        if ((dev->bus->number != 0) ||
+                (dev->device == SB_MIPS) ||
+                (dev->device == SB_MIPS33) ||
+                (dev->device == SB_EXTIF) ||
+                (dev->device == SB_CC))
+                return 0;
+
+        /* Do a core reset */
+        spin_lock_irqsave(&sbh_lock, flags);
+        coreidx = sb_coreidx(sbh);
+        if (sb_setcoreidx(sbh, PCI_SLOT(dev->devfn)) && (sb_coreid(sbh) == SB_USB)) {
+                /* 
+                 * The USB core requires a special bit to be set during core
+                 * reset to enable host (OHCI) mode. Resetting the SB core in
+                 * pcibios_enable_device() is a hack for compatibility with
+                 * vanilla usb-ohci so that it does not have to know about
+                 * SB. A driver that wants to use the USB core in device mode
+                 * should know about SB and should reset the bit back to 0
+                 * after calling pcibios_enable_device().
+                 */
+                sb_core_disable(sbh, sb_coreflags(sbh, 0, 0));
+                sb_core_reset(sbh, 1 << 29);
+        } else {
+                sb_core_reset(sbh, 0);
+        }
+        sb_setcoreidx(sbh, coreidx);
+        spin_unlock_irqrestore(&sbh_lock, flags);
+        
+        return 0;
+}
+
+DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, bcm47xx_fixup_bridge);

arch/mips/bcm947xx/prom.c

@@ +1 @@
+/*
+ *  Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/bootmem.h>
+
+#include <asm/addrspace.h>
+#include <asm/bootinfo.h>
+#include <asm/pmon.h>
+
+const char *get_system_type(void)
+{
+        return "Broadcom BCM47xx";
+}
+
+void __init prom_init(void)
+{
+        unsigned long mem;
+
+        mips_machgroup = MACH_GROUP_BRCM;
+        mips_machtype = MACH_BCM47XX;
+
+        /* Figure out memory size by finding aliases */
+        for (mem = (1 << 20); mem < (128 << 20); mem += (1 << 20)) {
+                if (*(unsigned long *)((unsigned long)(prom_init) + mem) == 
+                    *(unsigned long *)(prom_init))
+                        break;
+        }
+
+        add_memory_region(0, mem, BOOT_MEM_RAM);
+}
+
+unsigned long __init prom_free_prom_memory(void)
+{
+        return 0;
+}

arch/mips/bcm947xx/setup.c

@@ +1 @@
+/*
+ *  Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
+ *  Copyright (C) 2005 Waldemar Brodkorb <wbx@openwrt.org>
+ *  Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
+ *  Copyright (C) 2006 Michael Buesch
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/tty.h>
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+#include <linux/serial_reg.h>
+#include <asm/bootinfo.h>
+#include <asm/time.h>
+#include <asm/reboot.h>
+#include <asm/cfe.h>
+#include <linux/pm.h>
+#include <linux/ssb.h>
+
+#include <nvram.h>
+
+extern void bcm47xx_pci_init(void);
+extern void bcm47xx_time_init(void);
+
+struct ssb_bus ssb;
+
+static void bcm47xx_machine_restart(char *command)
+{
+        printk(KERN_ALERT "Please stand by while rebooting the system...\n");
+        local_irq_disable();
+        /* CFE has a reboot callback, but that does not work.
+         * Oopses with: Reserved instruction in kernel code.
+         */
+
+        /* Set the watchdog timer to reset immediately */
+//TODO  sb_watchdog(sbh, 1);
+        while (1)
+                cpu_relax();
+}
+
+static void bcm47xx_machine_halt(void)
+{
+        /* Disable interrupts and watchdog and spin forever */
+        local_irq_disable();
+//TODO  sb_watchdog(sbh, 0);
+        while (1)
+                cpu_relax();
+}
+
+static void e_aton(char *str, char *dest)
+{
+        int i = 0;
+
+        if (str == NULL) {
+                memset(dest, 0, 6);
+                return;
+        }
+        
+        for (;;) {
+                dest[i++] = (char) simple_strtoul(str, NULL, 16);
+                str += 2;
+                if (!*str++ || i == 6)
+                        break;
+        }
+}
+
+static void bcm47xx_fill_sprom(struct ssb_sprom *sprom)
+{
+        // TODO
+}
+
+static void bcm47xx_fill_sprom_nvram(struct ssb_sprom *sprom)
+{
+        char *s;
+
+        memset(sprom, 0, sizeof(struct ssb_sprom));
+        
+        sprom->revision = 3;
+        if ((s = nvram_get("et0macaddr")))
+                e_aton(s, sprom->r1.et0mac);
+        if ((s = nvram_get("et1macaddr")))
+                e_aton(s, sprom->r1.et1mac);
+        if ((s = nvram_get("et0phyaddr")))
+                sprom->r1.et0phyaddr = simple_strtoul(s, NULL, 10);
+        if ((s = nvram_get("et1phyaddr")))
+                sprom->r1.et1phyaddr = simple_strtoul(s, NULL, 10);
+}
+
+void __init plat_mem_setup(void)
+{
+        int i, err;
+        char *s;
+        struct ssb_mipscore *mcore;
+
+        err = ssb_bus_ssbbus_register(&ssb, SSB_ENUM_BASE, bcm47xx_fill_sprom);
+        if (err) {
+                const char *msg = "Failed to initialize SSB bus (err %d)\n";
+                cfe_printk(msg, err); /* Make sure the message gets out of the box. */
+                panic(msg, err);
+        }
+        mcore = &ssb.mipscore;
+
+        /* FIXME: the nvram init depends on the ssb being fully initializes,
+         * can't use the fill_sprom callback yet! */
+        bcm47xx_fill_sprom_nvram(&ssb.sprom);
+        
+        s = nvram_get("kernel_args");
+        if (s && !strncmp(s, "console=ttyS1", 13) && (mcore->nr_serial_ports >= 2)) {
+                struct ssb_serial_port port;
+
+                /* swap serial ports */
+                memcpy(&port, &mcore->serial_ports[0], sizeof(port));
+                memcpy(&mcore->serial_ports[0], &mcore->serial_ports[1], sizeof(port));
+                memcpy(&mcore->serial_ports[1], &port, sizeof(port));
+        }
+
+        for (i = 0; i < mcore->nr_serial_ports; i++) {
+                struct ssb_serial_port *port = &(mcore->serial_ports[i]);
+                struct uart_port s;
+        
+                memset(&s, 0, sizeof(s));
+                s.line = i;
+                s.membase = port->regs;
+                s.irq = port->irq + 2;//FIXME?
+                s.uartclk = port->baud_base;
+                s.flags = ASYNC_BOOT_AUTOCONF;
+                s.iotype = SERIAL_IO_MEM;
+                s.regshift = port->reg_shift;
+
+                early_serial_setup(&s);
+        }
+        cfe_printk("Serial init done.\n");
+
+        _machine_restart = bcm47xx_machine_restart;
+        _machine_halt = bcm47xx_machine_halt;
+        pm_power_off = bcm47xx_machine_halt;
+
+        board_time_init = bcm47xx_time_init;//FIXME move into ssb
+}
+

arch/mips/bcm947xx/time.c

@@ +1 @@
+/*
+ *  Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/serial_reg.h>
+#include <linux/interrupt.h>
+#include <linux/ssb.h>
+#include <asm/addrspace.h>
+#include <asm/io.h>
+#include <asm/time.h>
+
+extern struct ssb_bus ssb;
+
+void __init
+bcm47xx_time_init(void)
+{
+        unsigned long hz;
+
+        /*
+         * Use deterministic values for initial counter interrupt
+         * so that calibrate delay avoids encountering a counter wrap.
+         */
+        write_c0_count(0);
+        write_c0_compare(0xffff);
+
+        hz = ssb_clockspeed(&ssb);
+        if (!hz)
+                hz = 100000000;
+
+        /* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
+        mips_hpt_frequency = hz;
+}
+
+void __init
+plat_timer_setup(struct irqaction *irq)
+{
+        /* Enable the timer interrupt */
+        setup_irq(7, irq);
+}

arch/mips/cfe/Makefile

@@ +1 @@
+#
+# Makefile for the Broadcom Common Firmware Environment support
+#
+
+obj-y += cfe.o

arch/mips/cfe/cfe.c

@@ +1 @@
+/*
+ * Broadcom Common Firmware Environment (CFE) support
+ *
+ * Copyright 2000, 2001, 2002
+ * Broadcom Corporation. All rights reserved.
+ *
+ * Copyright (C) 2006 Michael Buesch
+ *
+ * Original Authors:  Mitch Lichtenberg, Chris Demetriou
+ *
+ * This software is furnished under license and may be used and copied only
+ * in accordance with the following terms and conditions.  Subject to these
+ * conditions, you may download, copy, install, use, modify and distribute
+ * modified or unmodified copies of this software in source and/or binary
+ * form. No title or ownership is transferred hereby.
+ *
+ * 1) Any source code used, modified or distributed must reproduce and
+ *    retain this copyright notice and list of conditions as they appear in
+ *    the source file.
+ *
+ * 2) No right is granted to use any trade name, trademark, or logo of
+ *    Broadcom Corporation.  The "Broadcom Corporation" name may not be
+ *    used to endorse or promote products derived from this software
+ *    without the prior written permission of Broadcom Corporation.
+ *
+ * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED
+ *    WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF
+ *    MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR
+ *    NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE
+ *    FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE
+ *    LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ *    BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ *    WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ *    OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <linux/init.h>
+#include <linux/string.h>
+#include <linux/errno.h>
+#include <linux/spinlock.h>
+#include <asm/cfe.h>
+
+#include "cfe_private.h"
+
+
+static cfe_uint_t cfe_handle;
+static int (*cfe_trampoline)(long handle, long iocb);
+
+
+#include <linux/kernel.h>
+
+void __init cfe_setup(unsigned long fwarg0, unsigned long fwarg1,
+                      unsigned long fwarg2, unsigned long fwarg3)
+{
+        if (fwarg3 == 0x80300000) {
+                /* WRT54G workaround */
+                fwarg3 = CFE_EPTSEAL;
+                fwarg2 = 0xBFC00500;
+        }
+        if (fwarg3 != CFE_EPTSEAL) {
+                /* We are not booted from CFE */
+                return;
+        }
+        if (fwarg1 == 0) {
+                /* We are on the boot CPU */
+                cfe_handle = (cfe_uint_t)fwarg0;
+                cfe_trampoline = CFE_TO_PTR(fwarg2);
+        }
+}
+
+int cfe_vprintk(const char *fmt, va_list args)
+{
+        static char buffer[1024];
+        static DEFINE_SPINLOCK(lock);
+        static const char pfx[] = "CFE-console: ";
+        static const size_t pfx_len = sizeof(pfx) - 1;
+        unsigned long flags;
+        int len, cnt, pos;
+        int handle;
+        int res;
+
+        if (!cfe_present())
+                return -ENODEV;
+
+        spin_lock_irqsave(&lock, flags);
+        handle = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE);
+        if (CFE_ISERR(handle)) {
+                len = -EIO;
+                goto out;
+        }
+        strcpy(buffer, pfx);
+        len = vscnprintf(buffer + pfx_len,
+                         sizeof(buffer) - pfx_len - 2,
+                         fmt, args);
+        len += pfx_len;
+        /* The CFE console requires CR-LF line-ends.
+         * Add a CR, if we only terminate lines with a LF.
+         * This does only fix CR-LF at the end of the string.
+         * So for multiple lines, use multiple cfe_vprintk calls.
+         */
+        if (len > 1 &&
+            buffer[len - 1] == '\n' && buffer[len - 2] != '\r') {
+                buffer[len - 1] = '\r';
+                buffer[len] = '\n';
+                len += 1;
+        }
+        cnt = len;
+        pos = 0;
+        while (cnt > 0) {
+                res = cfe_write(handle, buffer + pos, len - pos);
+                if (CFE_ISERR(res)) {
+                        len = -EIO;
+                        goto out;
+                }
+                cnt -= res;
+                pos += res;
+        }
+out:
+        spin_unlock_irqrestore(&lock, flags);
+
+        return len;
+}
+
+int cfe_printk(const char *fmt, ...)
+{
+        va_list args;
+        int res;
+
+        va_start(args, fmt);
+        res = cfe_vprintk(fmt, args);
+        va_end(args);
+
+        return res;
+}
+
+static int cfe_iocb_dispatch(struct cfe_iocb *iocb)
+{
+        if (!cfe_present())
+                return CFE_ERR_UNSUPPORTED;
+        return cfe_trampoline((long)cfe_handle, (long)iocb);
+}
+
+int cfe_present(void)
+{
+        return (cfe_trampoline != NULL);
+}
+
+int cfe_close(int handle)
+{
+        struct cfe_iocb iocb;
+        int err;
+
+        memset(&iocb, 0, sizeof(iocb));
+        iocb.fcode = CFE_CMD_DEV_CLOSE;
+        iocb.handle = handle;
+
+        err = cfe_iocb_dispatch(&iocb);
+
+        return (CFE_ISERR(err)) ? err : iocb.status;
+}
+
+int cfe_cpu_start(int cpu, void (*fn)(void), long sp, long gp, long a1)
+{
+        struct cfe_iocb iocb;
+        int err;
+
+        memset(&iocb, 0, sizeof(iocb));
+        iocb.fcode = CFE_CMD_FW_CPUCTL;
+        iocb.psize = sizeof(struct cfe_iocb_cpuctl);
+        iocb.cpuctl.number = cpu;
+        iocb.cpuctl.command = CFE_CPU_CMD_START;
+        iocb.cpuctl.gp = gp;
+        iocb.cpuctl.sp = sp;
+        iocb.cpuctl.a1 = a1;
+        iocb.cpuctl.start_addr = (long)fn;
+
+        err = cfe_iocb_dispatch(&iocb);
+
+        return (CFE_ISERR(err)) ? err : iocb.status;
+}
+
+int cfe_cpu_stop(int cpu)
+{
+        struct cfe_iocb iocb;
+        int err;
+
+        memset(&iocb, 0, sizeof(iocb));
+        iocb.fcode = CFE_CMD_FW_CPUCTL;
+        iocb.psize = sizeof(struct cfe_iocb_cpuctl);
+        iocb.cpuctl.number = cpu;
+        iocb.cpuctl.command = CFE_CPU_CMD_STOP;
+
+        err = cfe_iocb_dispatch(&iocb);
+
+        return (CFE_ISERR(err)) ? err : iocb.status;
+}
+
+int cfe_enumenv(int idx, char *name, int namelen, char *val, int vallen)
+{
+        struct cfe_iocb iocb;
+        int err;
+
+        memset(&iocb, 0, sizeof(iocb));
+        iocb.fcode = CFE_CMD_ENV_ENUM;
+        iocb.psize = sizeof(struct cfe_iocb_envbuf);
+        iocb.envbuf.index = idx;
+        iocb.envbuf.name = PTR_TO_CFE(name);
+        iocb.envbuf.name_len = namelen;
+        iocb.envbuf.val = PTR_TO_CFE(val);
+        iocb.envbuf.val_len = vallen;
+
+        err = cfe_iocb_dispatch(&iocb);
+
+        return (CFE_ISERR(err)) ? err : iocb.status;
+}
+
+int cfe_enumdev(int idx, char *name, int namelen)
+{
+        struct cfe_iocb iocb;
+        int err;
+
+        memset(&iocb, 0, sizeof(iocb));
+
+        iocb.fcode = CFE_CMD_DEV_ENUM;
+        iocb.psize = sizeof(struct cfe_iocb_envbuf);
+        iocb.envbuf.index = idx;
+        iocb.envbuf.name = PTR_TO_CFE(name);
+        iocb.envbuf.name_len = namelen;
+
+        err = cfe_iocb_dispatch(&iocb);
+
+        return (CFE_ISERR(err)) ? err : iocb.status;
+}
+
+int cfe_enummem(int idx, int flags, u64 *start, u64 *length,
+                u64 *type)
+{
+        struct cfe_iocb iocb;
+        int err;
+
+        memset(&iocb, 0, sizeof(iocb));
+
+        iocb.fcode = CFE_CMD_FW_MEMENUM;
+        iocb.flags = flags;
+        iocb.psize = sizeof(struct cfe_iocb_meminfo);
+        iocb.meminfo.index = idx;
+
+        err = cfe_iocb_dispatch(&iocb);
+        if (CFE_ISERR(err))
+                return err;
+        if (!CFE_ISERR(iocb.status)) {
+                *start = iocb.meminfo.addr;
+                *length = iocb.meminfo.size;
+                *type = iocb.meminfo.type;
+        }
+
+        return iocb.status;
+}
+
+int cfe_exit(int warm, int status)
+{
+        struct cfe_iocb iocb;
+        int err;
+
+printk("CFE REBOOT\n");
+        memset(&iocb, 0, sizeof(iocb));
+        iocb.fcode = CFE_CMD_FW_RESTART;
+        if (warm)
+                iocb.flags = CFE_FLG_WARMSTART;
+        iocb.psize = sizeof(struct cfe_iocb_exitstat);
+        iocb.exitstat.status = status;
+
+printk("CALL\n");
+        err = cfe_iocb_dispatch(&iocb);
+printk("DONE\n");
+
+        return (CFE_ISERR(err)) ? err : iocb.status;
+}
+
+int cfe_flushcache(int flags)
+{
+        struct cfe_iocb iocb;
+        int err;
+
+        memset(&iocb, 0, sizeof(iocb));
+        iocb.fcode = CFE_CMD_FW_FLUSHCACHE;
+        iocb.flags = flags;
+
+        err = cfe_iocb_dispatch(&iocb);
+
+        return (CFE_ISERR(err)) ? err : iocb.status;
+}
+
+int cfe_getdevinfo(char *name)
+{
+        struct cfe_iocb iocb;
+        int err;
+
+        memset(&iocb, 0, sizeof(iocb));
+        iocb.fcode = CFE_CMD_DEV_GETINFO;
+        iocb.psize = sizeof(struct cfe_iocb_buf);
+        iocb.buffer.ptr = PTR_TO_CFE(name);
+        iocb.buffer.length = strlen(name);
+
+        err = cfe_iocb_dispatch(&iocb);
+        if (CFE_ISERR(err))
+                return err;
+        if (CFE_ISERR(iocb.status))
+                return iocb.status;
+
+        return iocb.buffer.devflags;
+}
+
+int cfe_getenv(char *name, char *dest, int destlen)
+{
+        struct cfe_iocb iocb;
+        int err;
+
+        dest[0] = '\0';
+        memset(&iocb, 0, sizeof(iocb));
+        iocb.fcode = CFE_CMD_ENV_GET;
+        iocb.psize = sizeof(struct cfe_iocb_envbuf);
+        iocb.envbuf.name = PTR_TO_CFE(name);
+        iocb.envbuf.name_len = strlen(name);
+        iocb.envbuf.val = PTR_TO_CFE(dest);
+        iocb.envbuf.val_len = destlen;
+
+        err = cfe_iocb_dispatch(&iocb);
+
+        return (CFE_ISERR(err)) ? err : iocb.status;
+}
+
+int cfe_getfwinfo(struct cfe_fwinfo *info)
+{
+        struct cfe_iocb iocb;
+        int err;
+
+        memset(&iocb, 0, sizeof(iocb));
+        iocb.fcode = CFE_CMD_FW_GETINFO;
+        iocb.psize = sizeof(struct cfe_iocb_fwinfo);
+
+        err = cfe_iocb_dispatch(&iocb);
+        if (CFE_ISERR(err))
+                return err;
+        if (CFE_ISERR(iocb.status))
+                return err;
+
+        info->version = iocb.fwinfo.version;
+        info->totalmem = iocb.fwinfo.totalmem;
+        info->flags = iocb.fwinfo.flags;
+        info->boardid = iocb.fwinfo.boardid;
+        info->bootarea_va = iocb.fwinfo.bootarea_va;
+        info->bootarea_pa = iocb.fwinfo.bootarea_pa;
+        info->bootarea_size = iocb.fwinfo.bootarea_size;
+
+        return iocb.status;
+}
+
+int cfe_getstdhandle(int handletype)
+{
+        struct cfe_iocb iocb;
+        int err;
+
+        memset(&iocb, 0, sizeof(iocb));
+        iocb.fcode = CFE_CMD_DEV_GETHANDLE;
+        iocb.flags = handletype;
+
+        err = cfe_iocb_dispatch(&iocb);
+        if (CFE_ISERR(err))
+                return err;
+        if (CFE_ISERR(iocb.status))
+                return iocb.status;
+
+        return iocb.handle;
+}
+
+int cfe_getticks(s64 *ticks)
+{
+        struct cfe_iocb iocb;
+        int err;
+
+        memset(&iocb, 0, sizeof(iocb));
+        iocb.fcode = CFE_CMD_FW_GETTIME;
+        iocb.psize = sizeof(struct cfe_iocb_time);
+
+        err = cfe_iocb_dispatch(&iocb);
+        if (CFE_ISERR(err))
+                return err;
+        if (!CFE_ISERR(iocb.status))
+                *ticks = iocb.time.ticks;
+
+        return iocb.status;
+}
+
+int cfe_inpstat(int handle)
+{
+        struct cfe_iocb iocb;
+        int err;
+
+        memset(&iocb, 0, sizeof(iocb));
+        iocb.fcode = CFE_CMD_DEV_INPSTAT;
+        iocb.handle = handle;
+        iocb.psize = sizeof(struct cfe_iocb_inpstat);
+
+        err = cfe_iocb_dispatch(&iocb);
+        if (CFE_ISERR(err))
+                return err;
+        if (CFE_ISERR(iocb.status))
+                return iocb.status;
+
+        return iocb.inpstat.status;
+}
+
+int cfe_ioctl(int handle, unsigned int ioctlnum,
+              unsigned char *buffer, int length,
+              int *retlen, u64 offset)
+{
+        struct cfe_iocb iocb;
+        int err;
+
+        memset(&iocb, 0, sizeof(iocb));
+        iocb.fcode = CFE_CMD_DEV_IOCTL;
+        iocb.handle = handle;
+        iocb.psize = sizeof(struct cfe_iocb_buf);
+        iocb.buffer.offset = offset;
+        iocb.buffer.ioctlcmd = ioctlnum;
+        iocb.buffer.ptr = PTR_TO_CFE(buffer);
+        iocb.buffer.length = length;
+
+        err = cfe_iocb_dispatch(&iocb);
+        if (CFE_ISERR(err))
+                return err;
+        if (CFE_ISERR(iocb.status))
+                return iocb.status;
+        if (retlen)
+                *retlen = iocb.buffer.retlen;
+
+        return iocb.status;
+}
+
+int cfe_open(char *name)
+{
+        struct cfe_iocb iocb;
+        int err;
+
+        memset(&iocb, 0, sizeof(iocb));
+        iocb.fcode = CFE_CMD_DEV_OPEN;
+        iocb.psize = sizeof(struct cfe_iocb_buf);
+        iocb.buffer.ptr = PTR_TO_CFE(name);
+        iocb.buffer.length = strlen(name);
+
+        err = cfe_iocb_dispatch(&iocb);
+        if (CFE_ISERR(err))
+                return err;
+        if (CFE_ISERR(iocb.status))
+                return iocb.status;
+
+        return iocb.handle;
+}
+
+int cfe_read(int handle, unsigned char *buffer, int length)
+{
+        return cfe_readblk(handle, 0, buffer, length);
+}
+
+int cfe_readblk(int handle, s64 offset, unsigned char *buffer, int length)
+{
+        struct cfe_iocb iocb;
+        int err;
+
+        memset(&iocb, 0, sizeof(iocb));
+        iocb.fcode = CFE_CMD_DEV_READ;
+        iocb.handle = handle;
+        iocb.psize = sizeof(struct cfe_iocb_buf);
+        iocb.buffer.offset = offset;
+        iocb.buffer.ptr = PTR_TO_CFE(buffer);
+        iocb.buffer.length = length;
+
+        err = cfe_iocb_dispatch(&iocb);
+        if (CFE_ISERR(err))
+                return err;
+        if (CFE_ISERR(iocb.status))
+                return iocb.status;
+
+        return iocb.buffer.retlen;
+}
+
+int cfe_setenv(char *name, char *val)
+{
+        struct cfe_iocb iocb;
+        int err;
+
+        memset(&iocb, 0, sizeof(iocb));
+        iocb.fcode = CFE_CMD_ENV_SET;
+        iocb.psize = sizeof(struct cfe_iocb_envbuf);
+        iocb.envbuf.name = PTR_TO_CFE(name);
+        iocb.envbuf.name_len = strlen(name);
+        iocb.envbuf.val = PTR_TO_CFE(val);
+        iocb.envbuf.val_len = strlen(val);
+
+        err = cfe_iocb_dispatch(&iocb);
+
+        return (CFE_ISERR(err)) ? err : iocb.status;
+}
+
+int cfe_write(int handle, unsigned char *buffer, int length)
+{
+        return cfe_writeblk(handle, 0, buffer, length);
+}
+
+int cfe_writeblk(int handle, s64 offset, unsigned char *buffer, int length)
+{
+        struct cfe_iocb iocb;
+        int err;
+
+        memset(&iocb, 0, sizeof(iocb));
+        iocb.fcode = CFE_CMD_DEV_WRITE;
+        iocb.handle = handle;
+        iocb.psize = sizeof(struct cfe_iocb_buf);
+        iocb.buffer.offset = offset;
+        iocb.buffer.ptr = PTR_TO_CFE(buffer);
+        iocb.buffer.length = length;
+
+        err = cfe_iocb_dispatch(&iocb);
+        if (CFE_ISERR(err))
+                return err;
+        if (CFE_ISERR(iocb.status))
+                return iocb.status;
+
+        return iocb.buffer.retlen;
+}

arch/mips/cfe/cfe_private.h

@@ +1 @@
+/*
+ * Broadcom Common Firmware Environment (CFE) support
+ *
+ * Copyright 2000, 2001, 2002
+ * Broadcom Corporation. All rights reserved.
+ *
+ * Copyright (C) 2006 Michael Buesch
+ *
+ * Original Authors:  Mitch Lichtenberg, Chris Demetriou
+ *
+ * This software is furnished under license and may be used and copied only
+ * in accordance with the following terms and conditions.  Subject to these
+ * conditions, you may download, copy, install, use, modify and distribute
+ * modified or unmodified copies of this software in source and/or binary
+ * form. No title or ownership is transferred hereby.
+ *
+ * 1) Any source code used, modified or distributed must reproduce and
+ *    retain this copyright notice and list of conditions as they appear in
+ *    the source file.
+ *
+ * 2) No right is granted to use any trade name, trademark, or logo of
+ *    Broadcom Corporation.  The "Broadcom Corporation" name may not be
+ *    used to endorse or promote products derived from this software
+ *    without the prior written permission of Broadcom Corporation.
+ *
+ * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED
+ *    WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF
+ *    MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR
+ *    NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE
+ *    FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE
+ *    LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ *    BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ *    WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ *    OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LINUX_CFE_PRIVATE_H_
+#define LINUX_CFE_PRIVATE_H_
+
+#ifndef __ASSEMBLY__
+
+/* Seal indicating CFE's presence, passed to the kernel. */
+#define CFE_EPTSEAL             0x43464531
+
+#define CFE_CMD_FW_GETINFO      0
+#define CFE_CMD_FW_RESTART      1
+#define CFE_CMD_FW_BOOT         2
+#define CFE_CMD_FW_CPUCTL       3
+#define CFE_CMD_FW_GETTIME      4
+#define CFE_CMD_FW_MEMENUM      5
+#define CFE_CMD_FW_FLUSHCACHE   6
+
+#define CFE_CMD_DEV_GETHANDLE   9
+#define CFE_CMD_DEV_ENUM        10
+#define CFE_CMD_DEV_OPEN        11
+#define CFE_CMD_DEV_INPSTAT     12
+#define CFE_CMD_DEV_READ        13
+#define CFE_CMD_DEV_WRITE       14
+#define CFE_CMD_DEV_IOCTL       15
+#define CFE_CMD_DEV_CLOSE       16
+#define CFE_CMD_DEV_GETINFO     17
+
+#define CFE_CMD_ENV_ENUM        20
+#define CFE_CMD_ENV_GET         22
+#define CFE_CMD_ENV_SET         23
+#define CFE_CMD_ENV_DEL         24
+
+#define CFE_CMD_MAX             32
+
+#define CFE_CMD_VENDOR_USE      0x8000  /* codes above this are for customer use */
+
+typedef u64 cfe_uint_t;
+typedef s64 cfe_int_t;
+typedef s64 cfe_ptr_t;
+
+/* Cast a pointer from native to CFE-API pointer and back */
+#define CFE_TO_PTR(p)           ((void *)(unsigned long)(p))
+#define PTR_TO_CFE(p)           ((cfe_ptr_t)(unsigned long)(p))
+
+struct cfe_iocb_buf {
+        cfe_uint_t      offset;         /* offset on device (bytes) */
+        cfe_ptr_t       ptr;            /* pointer to a buffer */
+        cfe_uint_t      length;         /* length of this buffer */
+        cfe_uint_t      retlen;         /* returned length (for read ops) */
+        union {
+                cfe_uint_t      ioctlcmd;       /* IOCTL command (used only for IOCTLs) */
+                cfe_uint_t      devflags;       /* Returned device info flags */
+        };
+};
+
+struct cfe_iocb_inpstat {
+        cfe_uint_t      status;         /* 1 means input available */
+};
+
+struct cfe_iocb_envbuf {
+        cfe_int_t       index;          /* 0-based enumeration index */
+        cfe_ptr_t       name;           /* name string buffer */
+        cfe_int_t       name_len;       /* size of name buffer */
+        cfe_ptr_t       val;            /* value string buffer */
+        cfe_int_t       val_len;        /* size of value string buffer */
+};
+
+struct cfe_iocb_cpuctl {
+        cfe_uint_t      number;         /* cpu number to control */
+        cfe_uint_t      command;        /* command to issue to CPU */
+        cfe_uint_t      start_addr;     /* CPU start address */
+        cfe_uint_t      gp;             /* starting GP value */
+        cfe_uint_t      sp;             /* starting SP value */
+        cfe_uint_t      a1;             /* starting A1 value */
+};
+
+struct cfe_iocb_time {
+        cfe_int_t       ticks;          /* current time in ticks */
+};
+
+struct cfe_iocb_exitstat {
+        cfe_int_t       status;
+};
+
+struct cfe_iocb_meminfo {
+        cfe_int_t       index;          /* 0-based enumeration index */
+        cfe_int_t       type;           /* type of memory block */
+        cfe_uint_t      addr;           /* physical start address */
+        cfe_uint_t      size;           /* block size */
+};
+
+struct cfe_iocb_fwinfo {
+        cfe_int_t       version;        /* major, minor, eco version */
+        cfe_int_t       totalmem;       /* total installed mem */
+        cfe_int_t       flags;          /* various flags */
+        cfe_int_t       boardid;        /* board ID */
+        cfe_int_t       bootarea_va;    /* VA of boot area */
+        cfe_int_t       bootarea_pa;    /* PA of boot area */
+        cfe_int_t       bootarea_size;  /* size of boot area */
+        cfe_int_t       reserved1;
+        cfe_int_t       reserved2;
+        cfe_int_t       reserved3;
+};
+
+/* CFE I/O Control Block */
+struct cfe_iocb {
+        cfe_uint_t      fcode;          /* IOCB function code */
+        cfe_int_t       status;         /* return status */
+        cfe_int_t       handle;         /* file/device handle */
+        cfe_uint_t      flags;          /* flags for this IOCB */
+        cfe_uint_t      psize;          /* size of parameter list */
+        union {
+                struct cfe_iocb_buf             buffer;         /* buffer parameters */
+                struct cfe_iocb_inpstat         inpstat;        /* input status parameters */
+                struct cfe_iocb_envbuf          envbuf;         /* environment function parameters */
+                struct cfe_iocb_cpuctl          cpuctl;         /* CPU control parameters */
+                struct cfe_iocb_time            time;           /* timer parameters */
+                struct cfe_iocb_meminfo         meminfo;        /* memory arena info parameters */
+                struct cfe_iocb_fwinfo          fwinfo;         /* firmware information */
+                struct cfe_iocb_exitstat        exitstat;       /* Exit Status */
+        };
+};
+
+
+#include <linux/init.h>
+
+void __init cfe_setup(unsigned long fwarg0, unsigned long fwarg1,
+                      unsigned long fwarg2, unsigned long fwarg3);
+
+#else /* __ASSEMBLY__ */
+
+        .macro  cfe_early_init
+#ifdef CONFIG_CFE
+                jal     cfe_setup
+#endif
+        .endm
+
+#endif /* __ASSEMBLY__ */
+#endif /* LINUX_CFE_PRIVATE_H_ */

arch/mips/kernel/cpu-probe.c

@@ -723 +723 @@
 }
 
 
+static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
+{
+        decode_config1(c);
+        switch (c->processor_id & 0xff00) {
+                case PRID_IMP_BCM3302:
+                        c->cputype = CPU_BCM3302;
+                        c->isa_level = MIPS_CPU_ISA_M32R1;
+                        c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
+                                        MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER;
+                break;
+                case PRID_IMP_BCM4710:
+                        c->cputype = CPU_BCM4710;
+                        c->isa_level = MIPS_CPU_ISA_M32R1;
+                        c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
+                                        MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER;
+                break;
+        default:
+                c->cputype = CPU_UNKNOWN;
+                break;
+        }
+}
+
 __init void cpu_probe(void)
 {
         struct cpuinfo_mips *c = &current_cpu_data;
@@ -745 +767 @@
         case PRID_COMP_SIBYTE:
                 cpu_probe_sibyte(c);
                 break;
+        case PRID_COMP_BROADCOM:
+                cpu_probe_broadcom(c);
+                break;
         case PRID_COMP_SANDCRAFT:
                 cpu_probe_sandcraft(c);
                 break;

arch/mips/kernel/head.S

@@ -129 +129 @@
 #endif
         .endm
 
+        j kernel_entry
+        nop
+
         /*
          * Reserved space for exception handlers.
          * Necessary for machines which link their kernels at KSEG0.

arch/mips/kernel/proc.c

@@ -83 +83 @@
         [CPU_VR4181]    = "NEC VR4181",
         [CPU_VR4181A]   = "NEC VR4181A",
         [CPU_SR71000]   = "Sandcraft SR71000",
+        [CPU_BCM3302]   = "Broadcom BCM3302",
+        [CPU_BCM4710]   = "Broadcom BCM4710",
         [CPU_PR4450]    = "Philips PR4450",
 };
 

arch/mips/mm/tlbex.c

@@ -880 +880 @@
         case CPU_4KSC:
         case CPU_20KC:
         case CPU_25KF:
+        case CPU_BCM3302:
+        case CPU_BCM4710:
                 tlbw(p);
                 break;
 

drivers/Kconfig

@@ -56 +56 @@
 
 source "drivers/hwmon/Kconfig"
 
+source "drivers/ssb/Kconfig"
+
 source "drivers/mfd/Kconfig"
 
 source "drivers/media/Kconfig"

drivers/Makefile

@@ -77 +77 @@
 obj-$(CONFIG_SUPERH)            += sh/
 obj-$(CONFIG_GENERIC_TIME)      += clocksource/
 obj-$(CONFIG_DMA_ENGINE)        += dma/
+obj-$(CONFIG_SSB)               += ssb/

drivers/mtd/chips/cfi_cmdset_0002.c

@@ -296 +296 @@
                         printk(KERN_ERR "  Unknown Amd/Fujitsu Extended Query "
                                "version %c.%c.\n",  extp->MajorVersion,
                                extp->MinorVersion);
-                        kfree(extp);
-                        kfree(mtd);
-                        return NULL;
                 }
 
                 /* Install our own private info structure */

drivers/mtd/maps/Kconfig

@@ -299 +299 @@
           Mapping for the Flaga digital module. If you don't have one, ignore
           this setting.
 
+config MTD_BCM47XX
+        tristate "BCM47xx flash device"
+        depends on MIPS && MTD_CFI && BCM947XX
+        help
+          Support for the flash chips on the BCM947xx board.
+          
 config MTD_BEECH
         tristate "CFI Flash device mapped on IBM 405LP Beech"
         depends on MTD_CFI && BEECH

drivers/mtd/maps/Makefile

@@ -29 +29 @@
 obj-$(CONFIG_MTD_PCMCIA)        += pcmciamtd.o
 obj-$(CONFIG_MTD_RPXLITE)       += rpxlite.o
 obj-$(CONFIG_MTD_TQM8XXL)       += tqm8xxl.o
+obj-$(CONFIG_MTD_BCM47XX)       += bcm47xx-flash.o
 obj-$(CONFIG_MTD_SA1100)        += sa1100-flash.o
 obj-$(CONFIG_MTD_IPAQ)          += ipaq-flash.o
 obj-$(CONFIG_MTD_SBC_GXX)       += sbc_gxx.o

drivers/mtd/maps/bcm47xx-flash.c

@@ +1 @@
+/*
+ *  Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
+ *  Copyright (C) 2005 Waldemar Brodkorb <wbx@openwrt.org>
+ *  Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
+ *
+ *  original functions for finding root filesystem from Mike Baker 
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ * 
+ *  Copyright 2001-2003, Broadcom Corporation
+ *  All Rights Reserved.
+ * 
+ *  THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
+ *  KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
+ *  SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
+ *  FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
+ *
+ *  Flash mapping for BCM947XX boards
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/wait.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/map.h>
+#ifdef CONFIG_MTD_PARTITIONS
+#include <linux/mtd/partitions.h>
+#endif
+#include <linux/squashfs_fs.h>
+#include <linux/jffs2.h>
+#include <linux/crc32.h>
+#include <linux/ssb.h>
+#include <asm/io.h>
+
+
+#define TRX_MAGIC       0x30524448      /* "HDR0" */
+#define TRX_VERSION     1
+#define TRX_MAX_LEN     0x3A0000
+#define TRX_NO_HEADER   1               /* Do not write TRX header */   
+#define TRX_GZ_FILES    0x2     /* Contains up to TRX_MAX_OFFSET individual gzip files */
+#define TRX_MAX_OFFSET  3
+
+struct trx_header {
+        u32 magic;              /* "HDR0" */
+        u32 len;                /* Length of file including header */
+        u32 crc32;              /* 32-bit CRC from flag_version to end of file */
+        u32 flag_version;       /* 0:15 flags, 16:31 version */
+        u32 offsets[TRX_MAX_OFFSET];    /* Offsets of partitions from start of header */
+};
+
+#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y))
+#define NVRAM_SPACE 0x8000
+#define WINDOW_ADDR 0x1fc00000
+#define WINDOW_SIZE 0x400000
+#define BUSWIDTH 2
+
+extern struct ssb_bus ssb;
+static struct mtd_info *bcm947xx_mtd;
+
+static void bcm947xx_map_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len)
+{
+#define MIPS_MEMCPY_ALIGN 4
+        map_word ret;
+        ssize_t transfer;
+        ssize_t done = 0;
+        if ((len >= MIPS_MEMCPY_ALIGN) && (!(from & (MIPS_MEMCPY_ALIGN - 1))) && (!(((unsigned int)to & (MIPS_MEMCPY_ALIGN - 1))))) {
+                done = len & ~(MIPS_MEMCPY_ALIGN - 1);
+                memcpy_fromio(to, map->virt + from, done);
+        }
+        while (done < len) {
+                ret = map->read(map, from + done);
+                transfer = len - done;
+                if (transfer > map->bankwidth)
+                        transfer = map->bankwidth;
+                memcpy((void *)((unsigned long)to + done), &ret.x[0], transfer);
+                done += transfer;
+        }
+}
+
+static struct map_info bcm947xx_map = {
+        name: "Physically mapped flash",
+        size: WINDOW_SIZE,
+        bankwidth: BUSWIDTH,
+        phys: WINDOW_ADDR,
+};
+
+#ifdef CONFIG_MTD_PARTITIONS
+
+static struct mtd_partition bcm947xx_parts[] = {
+        { name: "cfe",  offset: 0, size: 0, mask_flags: MTD_WRITEABLE, },
+        { name: "linux", offset: 0, size: 0, },
+        { name: "rootfs", offset: 0, size: 0, },
+        { name: "nvram", offset: 0, size: 0, },
+        { name: "OpenWrt", offset: 0, size: 0, },
+        { name: NULL, },
+};
+
+static int __init
+find_cfe_size(struct mtd_info *mtd, size_t size)
+{
+        struct trx_header *trx;
+        unsigned char buf[512];
+        int off;
+        size_t len;
+        int blocksize;
+
+        trx = (struct trx_header *) buf;
+
+        blocksize = mtd->erasesize;
+        if (blocksize < 0x10000)
+                blocksize = 0x10000;
+
+        for (off = (128*1024); off < size; off += blocksize) {
+                memset(buf, 0xe5, sizeof(buf));
+
+                /*
+                 * Read into buffer 
+                 */
+                if (mtd->read(mtd, off, sizeof(buf), &len, buf) ||
+                    len != sizeof(buf))
+                        continue;
+
+                /* found a TRX header */
+                if (le32_to_cpu(trx->magic) == TRX_MAGIC) {
+                        goto found;
+                }
+        }
+
+        printk(KERN_NOTICE
+               "%s: Couldn't find bootloader size\n",
+               mtd->name);
+        return -1;
+
+ found:
+        printk(KERN_NOTICE "bootloader size: %d\n", off);
+        return off;
+
+}
+
+/*
+ * Copied from mtdblock.c
+ *
+ * Cache stuff...
+ * 
+ * Since typical flash erasable sectors are much larger than what Linux's
+ * buffer cache can handle, we must implement read-modify-write on flash
+ * sectors for each block write requests.  To avoid over-erasing flash sectors
+ * and to speed things up, we locally cache a whole flash sector while it is
+ * being written to until a different sector is required.
+ */
+
+static void erase_callback(struct erase_info *done)
+{
+        wait_queue_head_t *wait_q = (wait_queue_head_t *)done->priv;
+        wake_up(wait_q);
+}
+
+static int erase_write (struct mtd_info *mtd, unsigned long pos, 
+                        int len, const char *buf)
+{
+        struct erase_info erase;
+        DECLARE_WAITQUEUE(wait, current);
+        wait_queue_head_t wait_q;
+        size_t retlen;
+        int ret;
+
+        /*
+         * First, let's erase the flash block.
+         */
+
+        init_waitqueue_head(&wait_q);
+        erase.mtd = mtd;
+        erase.callback = erase_callback;
+        erase.addr = pos;
+        erase.len = len;
+        erase.priv = (u_long)&wait_q;
+
+        set_current_state(TASK_INTERRUPTIBLE);
+        add_wait_queue(&wait_q, &wait);
+
+        ret = mtd->erase(mtd, &erase);
+        if (ret) {
+                set_current_state(TASK_RUNNING);
+                remove_wait_queue(&wait_q, &wait);
+                printk (KERN_WARNING "erase of region [0x%lx, 0x%x] "
+                                     "on \"%s\" failed\n",
+                        pos, len, mtd->name);
+                return ret;
+        }
+
+        schedule();  /* Wait for erase to finish. */
+        remove_wait_queue(&wait_q, &wait);
+
+        /*
+         * Next, writhe data to flash.
+         */
+
+        ret = mtd->write (mtd, pos, len, &retlen, buf);
+        if (ret)
+                return ret;
+        if (retlen != len)
+                return -EIO;
+        return 0;
+}
+
+
+
+
+static int __init
+find_root(struct mtd_info *mtd, size_t size, struct mtd_partition *part)
+{
+        struct trx_header trx, *trx2;
+        unsigned char buf[512], *block;
+        int off, blocksize;
+        u32 i, crc = ~0;
+        size_t len;
+        struct squashfs_super_block *sb = (struct squashfs_super_block *) buf;
+
+        blocksize = mtd->erasesize;
+        if (blocksize < 0x10000)
+                blocksize = 0x10000;
+
+        for (off = (128*1024); off < size; off += blocksize) {
+                memset(&trx, 0xe5, sizeof(trx));
+
+                /*
+                 * Read into buffer 
+                 */
+                if (mtd->read(mtd, off, sizeof(trx), &len, (char *) &trx) ||
+                    len != sizeof(trx))
+                        continue;
+
+                /* found a TRX header */
+                if (le32_to_cpu(trx.magic) == TRX_MAGIC) {
+                        part->offset = le32_to_cpu(trx.offsets[2]) ? : 
+                                le32_to_cpu(trx.offsets[1]);
+                        part->size = le32_to_cpu(trx.len); 
+
+                        part->size -= part->offset;
+                        part->offset += off;
+
+                        goto found;
+                }
+        }
+
+        printk(KERN_NOTICE
+               "%s: Couldn't find root filesystem\n",
+               mtd->name);
+        return -1;
+
+ found:
+        if (part->size == 0)
+                return 0;
+        
+        if (mtd->read(mtd, part->offset, sizeof(buf), &len, buf) || len != sizeof(buf))
+                return 0;
+
+        if (*((__u32 *) buf) == SQUASHFS_MAGIC) {
+                printk(KERN_INFO "%s: Filesystem type: squashfs, size=0x%x\n", mtd->name, (u32) sb->bytes_used);
+
+                /* Update the squashfs partition size based on the superblock info */
+                part->size = sb->bytes_used;
+                len = part->offset + part->size;
+                len +=  (mtd->erasesize - 1);
+                len &= ~(mtd->erasesize - 1);
+                part->size = len - part->offset;
+        } else if (*((__u16 *) buf) == JFFS2_MAGIC_BITMASK) {
+                printk(KERN_INFO "%s: Filesystem type: jffs2\n", mtd->name);
+
+                /* Move the squashfs outside of the trx */
+                part->size = 0;
+        } else {
+                printk(KERN_INFO "%s: Filesystem type: unknown\n", mtd->name);
+                return 0;
+        }
+
+        if (trx.len != part->offset + part->size - off) {
+                /* Update the trx offsets and length */
+                trx.len = part->offset + part->size - off;
+        
+                /* Update the trx crc32 */
+                for (i = (u32) &(((struct trx_header *)NULL)->flag_version); i <= trx.len; i += sizeof(buf)) {
+                        if (mtd->read(mtd, off + i, sizeof(buf), &len, buf) || len != sizeof(buf))
+                                return 0;
+                        crc = crc32_le(crc, buf, min(sizeof(buf), trx.len - i));
+                }
+                trx.crc32 = crc;
+
+                /* read first eraseblock from the trx */
+                block = kmalloc(mtd->erasesize, GFP_KERNEL);
+                trx2 = (struct trx_header *) block;
+                if (mtd->read(mtd, off, mtd->erasesize, &len, block) || len != mtd->erasesize) {
+                        printk("Error accessing the first trx eraseblock\n");
+                        return 0;
+                }
+                
+                printk("Updating TRX offsets and length:\n");
+                printk("old trx = [0x%08x, 0x%08x, 0x%08x], len=0x%08x crc32=0x%08x\n", trx2->offsets[0], trx2->offsets[1], trx2->offsets[2], trx2->len, trx2->crc32);
+                printk("new trx = [0x%08x, 0x%08x, 0x%08x], len=0x%08x crc32=0x%08x\n",   trx.offsets[0],   trx.offsets[1],   trx.offsets[2],   trx.len, trx.crc32);
+
+                /* Write updated trx header to the flash */
+                memcpy(block, &trx, sizeof(trx));
+                if (mtd->unlock)
+                        mtd->unlock(mtd, off, mtd->erasesize);
+                erase_write(mtd, off, mtd->erasesize, block);
+                if (mtd->sync)
+                        mtd->sync(mtd);
+                kfree(block);
+                printk("Done\n");
+        }
+        
+        return part->size;
+}
+
+struct mtd_partition * __init
+init_mtd_partitions(struct mtd_info *mtd, size_t size)
+{
+        int cfe_size;
+
+        if ((cfe_size = find_cfe_size(mtd,size)) < 0)
+                return NULL;
+
+        /* boot loader */
+        bcm947xx_parts[0].offset = 0;
+        bcm947xx_parts[0].size   = cfe_size;
+
+        /* nvram */
+        if (cfe_size != 384 * 1024) {
+                bcm947xx_parts[3].offset = size - ROUNDUP(NVRAM_SPACE, mtd->erasesize);
+                bcm947xx_parts[3].size   = ROUNDUP(NVRAM_SPACE, mtd->erasesize);
+        } else {
+                /* nvram (old 128kb config partition on netgear wgt634u) */
+                bcm947xx_parts[3].offset = bcm947xx_parts[0].size;
+                bcm947xx_parts[3].size   = ROUNDUP(NVRAM_SPACE, mtd->erasesize);
+        }
+
+        /* linux (kernel and rootfs) */
+        if (cfe_size != 384 * 1024) {
+                bcm947xx_parts[1].offset = bcm947xx_parts[0].size;
+                bcm947xx_parts[1].size   = bcm947xx_parts[3].offset - 
+                        bcm947xx_parts[1].offset;
+        } else {
+                /* do not count the elf loader, which is on one block */
+                bcm947xx_parts[1].offset = bcm947xx_parts[0].size + 
+                        bcm947xx_parts[3].size + mtd->erasesize;
+                bcm947xx_parts[1].size   = size - 
+                        bcm947xx_parts[0].size - 
+                        (2*bcm947xx_parts[3].size) - 
+                        mtd->erasesize;
+        }
+
+        /* find and size rootfs */
+        if (find_root(mtd,size,&bcm947xx_parts[2])==0) {
+                /* entirely jffs2 */
+                bcm947xx_parts[4].name = NULL;
+                bcm947xx_parts[2].size = size - bcm947xx_parts[2].offset - 
+                                bcm947xx_parts[3].size;
+        } else {
+                /* legacy setup */
+                /* calculate leftover flash, and assign it to the jffs2 partition */
+                if (cfe_size != 384 * 1024) {
+                        bcm947xx_parts[4].offset = bcm947xx_parts[2].offset + 
+                                bcm947xx_parts[2].size;
+                        if ((bcm947xx_parts[4].offset % mtd->erasesize) > 0) {
+                                bcm947xx_parts[4].offset += mtd->erasesize - 
+                                        (bcm947xx_parts[4].offset % mtd->erasesize);
+                        }
+                        bcm947xx_parts[4].size = bcm947xx_parts[3].offset - 
+                                bcm947xx_parts[4].offset;
+                } else {
+                        bcm947xx_parts[4].offset = bcm947xx_parts[2].offset + 
+                                bcm947xx_parts[2].size;
+                        if ((bcm947xx_parts[4].offset % mtd->erasesize) > 0) {
+                                bcm947xx_parts[4].offset += mtd->erasesize - 
+                                        (bcm947xx_parts[4].offset % mtd->erasesize);
+                        }
+                        bcm947xx_parts[4].size = size - bcm947xx_parts[3].size - 
+                                bcm947xx_parts[4].offset;
+                }
+        }
+
+        return bcm947xx_parts;
+}
+#endif
+
+int __init init_bcm947xx_map(void)
+{
+        struct ssb_mipscore *mcore = &ssb.mipscore;
+        size_t size;
+        int ret = 0;
+#ifdef CONFIG_MTD_PARTITIONS
+        struct mtd_partition *parts;
+        int i;
+#endif
+        u32 window = mcore->flash_window;
+        u32 window_size = mcore->flash_window_size;
+
+        printk("flash init: 0x%08x 0x%08x\n", window, window_size);
+        bcm947xx_map.virt = ioremap(window, window_size);
+
+        if (!bcm947xx_map.virt) {
+                printk("Failed to ioremap\n");
+                return -EIO;
+        }
+        simple_map_init(&bcm947xx_map);
+        
+        bcm947xx_map.copy_from = bcm947xx_map_copy_from;
+        
+        if (!(bcm947xx_mtd = do_map_probe("cfi_probe", &bcm947xx_map))) {
+                printk("Failed to do_map_probe\n");
+                iounmap((void *)bcm947xx_map.virt);
+                return -ENXIO;
+        }
+
+        bcm947xx_mtd->owner = THIS_MODULE;
+
+        size = bcm947xx_mtd->size;
+
+        printk(KERN_NOTICE "Flash device: 0x%x at 0x%x\n", size, WINDOW_ADDR);
+
+#ifdef CONFIG_MTD_PARTITIONS
+        parts = init_mtd_partitions(bcm947xx_mtd, size);
+        for (i = 0; parts[i].name; i++);
+        ret = add_mtd_partitions(bcm947xx_mtd, parts, i);
+        if (ret) {
+                printk(KERN_ERR "Flash: add_mtd_partitions failed\n");
+                goto fail;
+        }
+#endif
+        return 0;
+
+ fail:
+        if (bcm947xx_mtd)
+                map_destroy(bcm947xx_mtd);
+        if (bcm947xx_map.virt)
+                iounmap((void *)bcm947xx_map.virt);
+        bcm947xx_map.virt = 0;
+        return ret;
+}
+
+void __exit cleanup_bcm947xx_map(void)
+{
+#ifdef CONFIG_MTD_PARTITIONS
+        del_mtd_partitions(bcm947xx_mtd);
+#endif
+        map_destroy(bcm947xx_mtd);
+        iounmap((void *)bcm947xx_map.virt);
+}
+
+module_init(init_bcm947xx_map);
+module_exit(cleanup_bcm947xx_map);

drivers/net/Kconfig

@@ -1394 +1394 @@
 
 config B44
         tristate "Broadcom 4400 ethernet support"
-        depends on NET_PCI && PCI
+        depends on SSB && EXPERIMENTAL
         select MII
         help
           If you have a network (Ethernet) controller of this type, say Y and

drivers/net/b44.c

@@ -1 @@
-/* b44.c: Broadcom 4400 device driver.
+/* b44.c: Broadcom 4400/47xx device driver.
  *
  * Copyright (C) 2002 David S. Miller (davem@redhat.com)
- * Fixed by Pekka Pietikainen (pp@ee.oulu.fi)
+ * Copyright (C) 2004 Pekka Pietikainen (pp@ee.oulu.fi)
+ * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
+ * Copyright (C) 2006 Felix Fietkau (nbd@openwrt.org)
  * Copyright (C) 2006 Broadcom Corporation.
  *
  * Distribute under GPL.
@@ -20 +22 @@
 #include <linux/delay.h>
 #include <linux/init.h>
 #include <linux/dma-mapping.h>
+#include <linux/ssb.h>
 
 #include <asm/uaccess.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 
+
 #include "b44.h"
 
 #define DRV_MODULE_NAME         "b44"
@@ -87 +91 @@
 static char version[] __devinitdata =
         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 
-MODULE_AUTHOR("Florian Schirmer, Pekka Pietikainen, David S. Miller");
-MODULE_DESCRIPTION("Broadcom 4400 10/100 PCI ethernet driver");
+MODULE_AUTHOR("Felix Fietkau, Florian Schirmer, Pekka Pietikainen, David S. Miller");
+MODULE_DESCRIPTION("Broadcom 4400/47xx 10/100 PCI ethernet driver");
 MODULE_LICENSE("GPL");
 MODULE_VERSION(DRV_MODULE_VERSION);
 
@@ -96 +100 @@
 module_param(b44_debug, int, 0);
 MODULE_PARM_DESC(b44_debug, "B44 bitmapped debugging message enable value");
 
-static struct pci_device_id b44_pci_tbl[] = {
-        { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401,
-          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
-        { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B0,
-          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
-        { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1,
-          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
-        { }     /* terminate list with empty entry */
+static struct ssb_device_id b44_ssb_tbl[] = {
+        SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_ETHERNET, SSB_ANY_REV),
+        SSB_DEVTABLE_END
 };
 
-MODULE_DEVICE_TABLE(pci, b44_pci_tbl);
-
 static void b44_halt(struct b44 *);
 static void b44_init_rings(struct b44 *);
 static void b44_init_hw(struct b44 *, int);
 
 static int dma_desc_align_mask;
 static int dma_desc_sync_size;
+static int instance;
 
 static const char b44_gstrings[][ETH_GSTRING_LEN] = {
 #define _B44(x...)      # x,
@@ -121 +119 @@
 #undef _B44
 };
 
-static inline void b44_sync_dma_desc_for_device(struct pci_dev *pdev,
-                                                dma_addr_t dma_base,
-                                                unsigned long offset,
-                                                enum dma_data_direction dir)
-{
-        dma_sync_single_range_for_device(&pdev->dev, dma_base,
-                                         offset & dma_desc_align_mask,
-                                         dma_desc_sync_size, dir);
-}
-
-static inline void b44_sync_dma_desc_for_cpu(struct pci_dev *pdev,
-                                             dma_addr_t dma_base,
-                                             unsigned long offset,
-                                             enum dma_data_direction dir)
-{
-        dma_sync_single_range_for_cpu(&pdev->dev, dma_base,
-                                      offset & dma_desc_align_mask,
-                                      dma_desc_sync_size, dir);
-}
-
-static inline unsigned long br32(const struct b44 *bp, unsigned long reg)
-{
-        return readl(bp->regs + reg);
-}
-
-static inline void bw32(const struct b44 *bp,
-                        unsigned long reg, unsigned long val)
-{
-        writel(val, bp->regs + reg);
+static inline void b44_sync_dma_desc_for_device(struct ssb_device *sdev,
+                                               dma_addr_t dma_base,
+                                               unsigned long offset,
+                                               enum dma_data_direction dir)
+{
+        dma_sync_single_range_for_device(&sdev->dev, dma_base,
+                                        offset & dma_desc_align_mask,
+                                        dma_desc_sync_size, dir);
+}
+
+static inline void b44_sync_dma_desc_for_cpu(struct ssb_device *sdev,
+                                            dma_addr_t dma_base,
+                                            unsigned long offset,
+                                            enum dma_data_direction dir)
+{
+        dma_sync_single_range_for_cpu(&sdev->dev, dma_base,
+                                     offset & dma_desc_align_mask,
+                                     dma_desc_sync_size, dir);
 }
 
 static int b44_wait_bit(struct b44 *bp, unsigned long reg,
@@ -177 +164 @@
         return 0;
 }
 
-/* Sonics SiliconBackplane support routines.  ROFL, you should see all the
- * buzz words used on this company's website :-)
- *
- * All of these routines must be invoked with bp->lock held and
- * interrupts disabled.
- */
-
-#define SB_PCI_DMA             0x40000000      /* Client Mode PCI memory access space (1 GB) */
-#define BCM4400_PCI_CORE_ADDR  0x18002000      /* Address of PCI core on BCM4400 cards */
-
-static u32 ssb_get_core_rev(struct b44 *bp)
-{
-        return (br32(bp, B44_SBIDHIGH) & SBIDHIGH_RC_MASK);
-}
-
-static u32 ssb_pci_setup(struct b44 *bp, u32 cores)
-{
-        u32 bar_orig, pci_rev, val;
-
-        pci_read_config_dword(bp->pdev, SSB_BAR0_WIN, &bar_orig);
-        pci_write_config_dword(bp->pdev, SSB_BAR0_WIN, BCM4400_PCI_CORE_ADDR);
-        pci_rev = ssb_get_core_rev(bp);
-
-        val = br32(bp, B44_SBINTVEC);
-        val |= cores;
-        bw32(bp, B44_SBINTVEC, val);
-
-        val = br32(bp, SSB_PCI_TRANS_2);
-        val |= SSB_PCI_PREF | SSB_PCI_BURST;
-        bw32(bp, SSB_PCI_TRANS_2, val);
-
-        pci_write_config_dword(bp->pdev, SSB_BAR0_WIN, bar_orig);
-
-        return pci_rev;
-}
-
-static void ssb_core_disable(struct b44 *bp)
-{
-        if (br32(bp, B44_SBTMSLOW) & SBTMSLOW_RESET)
-                return;
-
-        bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_CLOCK));
-        b44_wait_bit(bp, B44_SBTMSLOW, SBTMSLOW_REJECT, 100000, 0);
-        b44_wait_bit(bp, B44_SBTMSHIGH, SBTMSHIGH_BUSY, 100000, 1);
-        bw32(bp, B44_SBTMSLOW, (SBTMSLOW_FGC | SBTMSLOW_CLOCK |
-                            SBTMSLOW_REJECT | SBTMSLOW_RESET));
-        br32(bp, B44_SBTMSLOW);
-        udelay(1);
-        bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_RESET));
-        br32(bp, B44_SBTMSLOW);
-        udelay(1);
-}
-
-static void ssb_core_reset(struct b44 *bp)
+static inline void __b44_cam_read(struct b44 *bp, unsigned char *data, int index)
 {
         u32 val;
 
-        ssb_core_disable(bp);
-        bw32(bp, B44_SBTMSLOW, (SBTMSLOW_RESET | SBTMSLOW_CLOCK | SBTMSLOW_FGC));
-        br32(bp, B44_SBTMSLOW);
-        udelay(1);
-
-        /* Clear SERR if set, this is a hw bug workaround.  */
-        if (br32(bp, B44_SBTMSHIGH) & SBTMSHIGH_SERR)
-                bw32(bp, B44_SBTMSHIGH, 0);
-
-        val = br32(bp, B44_SBIMSTATE);
-        if (val & (SBIMSTATE_IBE | SBIMSTATE_TO))
-                bw32(bp, B44_SBIMSTATE, val & ~(SBIMSTATE_IBE | SBIMSTATE_TO));
-
-        bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK | SBTMSLOW_FGC));
-        br32(bp, B44_SBTMSLOW);
-        udelay(1);
-
-        bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK));
-        br32(bp, B44_SBTMSLOW);
-        udelay(1);
-}
+        bw32(bp, B44_CAM_CTRL, (CAM_CTRL_READ |
+                            (index << CAM_CTRL_INDEX_SHIFT)));
 
-static int ssb_core_unit(struct b44 *bp)
-{
-#if 0
-        u32 val = br32(bp, B44_SBADMATCH0);
-        u32 base;
+        b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
 
-        type = val & SBADMATCH0_TYPE_MASK;
-        switch (type) {
-        case 0:
-                base = val & SBADMATCH0_BS0_MASK;
-                break;
+        val = br32(bp, B44_CAM_DATA_LO);
 
-        case 1:
-                base = val & SBADMATCH0_BS1_MASK;
-                break;
+        data[2] = (val >> 24) & 0xFF;
+        data[3] = (val >> 16) & 0xFF;
+        data[4] = (val >> 8) & 0xFF;
+        data[5] = (val >> 0) & 0xFF;
 
-        case 2:
-        default:
-                base = val & SBADMATCH0_BS2_MASK;
-                break;
-        };
-#endif
-        return 0;
-}
+        val = br32(bp, B44_CAM_DATA_HI);
 
-static int ssb_is_core_up(struct b44 *bp)
-{
-        return ((br32(bp, B44_SBTMSLOW) & (SBTMSLOW_RESET | SBTMSLOW_REJECT | SBTMSLOW_CLOCK))
-                == SBTMSLOW_CLOCK);
+        data[0] = (val >> 8) & 0xFF;
+        data[1] = (val >> 0) & 0xFF;
 }
 
-static void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
+static inline void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
 {
         u32 val;
 
@@ -323 +222 @@
         bw32(bp, B44_IMASK, bp->imask);
 }
 
-static int b44_readphy(struct b44 *bp, int reg, u32 *val)
+static int __b44_readphy(struct b44 *bp, int phy_addr, int reg, u32 *val)
 {
         int err;
 
         bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
         bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
                              (MDIO_OP_READ << MDIO_DATA_OP_SHIFT) |
-                             (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
+                             (phy_addr << MDIO_DATA_PMD_SHIFT) |
                              (reg << MDIO_DATA_RA_SHIFT) |
                              (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT)));
         err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
@@ -339 +238 @@
         return err;
 }
 
-static int b44_writephy(struct b44 *bp, int reg, u32 val)
+static int __b44_writephy(struct b44 *bp, int phy_addr, int reg, u32 val)
 {
         bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
         bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
                              (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) |
-                             (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
+                             (phy_addr << MDIO_DATA_PMD_SHIFT) |
                              (reg << MDIO_DATA_RA_SHIFT) |
                              (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT) |
                              (val & MDIO_DATA_DATA)));
         return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
 }
 
+static inline int b44_readphy(struct b44 *bp, int reg, u32 *val)
+{
+        if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
+                return 0;
+
+        return __b44_readphy(bp, bp->phy_addr, reg, val);
+}
+
+static inline int b44_writephy(struct b44 *bp, int reg, u32 val)
+{
+        if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
+                return 0;
+                
+        return __b44_writephy(bp, bp->phy_addr, reg, val);
+}
+
 /* miilib interface */
 /* FIXME FIXME: phy_id is ignored, bp->phy_addr use is unconditional
  * due to code existing before miilib use was added to this driver.
@@ -379 +294 @@
         u32 val;
         int err;
 
+        if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
+                return 0;
         err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
         if (err)
                 return err;
@@ -437 +354 @@
         __b44_set_flow_ctrl(bp, pause_enab);
 }
 
+
+extern char *nvram_get(char *name); //FIXME: move elsewhere
 static int b44_setup_phy(struct b44 *bp)
 {
         u32 val;
         int err;
 
+        /*
+         * workaround for bad hardware design in Linksys WAP54G v1.0
+         * see https://dev.openwrt.org/ticket/146
+         * check and reset bit "isolate"
+         */
+        if ((atoi(nvram_get("boardnum")) == 2) &&
+                        (__b44_readphy(bp, 0, MII_BMCR, &val) == 0) && 
+                        (val & BMCR_ISOLATE) &&
+                        (__b44_writephy(bp, 0, MII_BMCR, val & ~BMCR_ISOLATE) != 0)) {
+                printk(KERN_WARNING PFX "PHY: cannot reset MII transceiver isolate bit.\n");
+        }
+
+        if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
+                return 0;
         if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
                 goto out;
         if ((err = b44_writephy(bp, B44_MII_ALEDCTRL,
@@ -537 +470 @@
 {
         u32 bmsr, aux;
 
+        if (bp->phy_addr == B44_PHY_ADDR_NO_PHY) {
+                bp->flags |= B44_FLAG_100_BASE_T;
+                bp->flags |= B44_FLAG_FULL_DUPLEX;
+                if (!netif_carrier_ok(bp->dev)) {
+                        u32 val = br32(bp, B44_TX_CTRL);
+                        val |= TX_CTRL_DUPLEX;
+                        bw32(bp, B44_TX_CTRL, val);
+                        netif_carrier_on(bp->dev);
+                        b44_link_report(bp);
+                }
+                return;
+        }
+
         if (!b44_readphy(bp, MII_BMSR, &bmsr) &&
             !b44_readphy(bp, B44_MII_AUXCTRL, &aux) &&
             (bmsr != 0xffff)) {
@@ -613 +559 @@
 
                 BUG_ON(skb == NULL);
 
-                pci_unmap_single(bp->pdev,
+                dma_unmap_single(&bp->sdev->dev,
                                  pci_unmap_addr(rp, mapping),
                                  skb->len,
-                                 PCI_DMA_TODEVICE);
+                                 DMA_TO_DEVICE);
                 rp->skb = NULL;
                 dev_kfree_skb_irq(skb);
         }
@@ -652 +598 @@
         skb = dev_alloc_skb(RX_PKT_BUF_SZ);
         if (skb == NULL)
                 return -ENOMEM;
-
-        mapping = pci_map_single(bp->pdev, skb->data,
+        
+        mapping = dma_map_single(&bp->sdev->dev, skb->data,
                                  RX_PKT_BUF_SZ,
-                                 PCI_DMA_FROMDEVICE);
+                                 DMA_FROM_DEVICE);
 
         /* Hardware bug work-around, the chip is unable to do PCI DMA
            to/from anything above 1GB :-( */
@@ -663 +609 @@
                 mapping + RX_PKT_BUF_SZ > B44_DMA_MASK) {
                 /* Sigh... */
                 if (!dma_mapping_error(mapping))
-                        pci_unmap_single(bp->pdev, mapping, RX_PKT_BUF_SZ,PCI_DMA_FROMDEVICE);
+                        dma_unmap_single(&bp->sdev->dev, mapping, RX_PKT_BUF_SZ,DMA_FROM_DEVICE);
                 dev_kfree_skb_any(skb);
                 skb = __dev_alloc_skb(RX_PKT_BUF_SZ,GFP_DMA);
                 if (skb == NULL)
                         return -ENOMEM;
-                mapping = pci_map_single(bp->pdev, skb->data,
+                mapping = dma_map_single(&bp->sdev->dev, skb->data,
                                          RX_PKT_BUF_SZ,
-                                         PCI_DMA_FROMDEVICE);
+                                         DMA_FROM_DEVICE);
                 if (dma_mapping_error(mapping) ||
                         mapping + RX_PKT_BUF_SZ > B44_DMA_MASK) {
                         if (!dma_mapping_error(mapping))
-                                pci_unmap_single(bp->pdev, mapping, RX_PKT_BUF_SZ,PCI_DMA_FROMDEVICE);
+                                dma_unmap_single(&bp->sdev->dev, mapping, RX_PKT_BUF_SZ,DMA_FROM_DEVICE);
                         dev_kfree_skb_any(skb);
                         return -ENOMEM;
                 }
@@ -703 +649 @@
         dp->addr = cpu_to_le32((u32) mapping + bp->rx_offset + bp->dma_offset);
 
         if (bp->flags & B44_FLAG_RX_RING_HACK)
-                b44_sync_dma_desc_for_device(bp->pdev, bp->rx_ring_dma,
-                                             dest_idx * sizeof(dp),
-                                             DMA_BIDIRECTIONAL);
+                b44_sync_dma_desc_for_device(bp->sdev, bp->rx_ring_dma,
+                                            dest_idx * sizeof(dp),
+                                            DMA_BIDIRECTIONAL);
 
         return RX_PKT_BUF_SZ;
 }
@@ -732 +678 @@
                            pci_unmap_addr(src_map, mapping));
 
         if (bp->flags & B44_FLAG_RX_RING_HACK)
-                b44_sync_dma_desc_for_cpu(bp->pdev, bp->rx_ring_dma,
-                                          src_idx * sizeof(src_desc),
-                                          DMA_BIDIRECTIONAL);
+                b44_sync_dma_desc_for_cpu(bp->sdev, bp->rx_ring_dma,
+                                         src_idx * sizeof(src_desc),
+                                         DMA_BIDIRECTIONAL);
 
         ctrl = src_desc->ctrl;
         if (dest_idx == (B44_RX_RING_SIZE - 1))
@@ -748 +694 @@
         src_map->skb = NULL;
 
         if (bp->flags & B44_FLAG_RX_RING_HACK)
-                b44_sync_dma_desc_for_device(bp->pdev, bp->rx_ring_dma,
-                                             dest_idx * sizeof(dest_desc),
-                                             DMA_BIDIRECTIONAL);
+                b44_sync_dma_desc_for_device(bp->sdev, bp->rx_ring_dma,
+                                            dest_idx * sizeof(dest_desc),
+                                            DMA_BIDIRECTIONAL);
 
-        pci_dma_sync_single_for_device(bp->pdev, src_desc->addr,
+        dma_sync_single_for_device(&bp->sdev->dev, src_desc->addr,
                                        RX_PKT_BUF_SZ,
-                                       PCI_DMA_FROMDEVICE);
+                                       DMA_FROM_DEVICE);
 }
 
 static int b44_rx(struct b44 *bp, int budget)
@@ -774 +720 @@
                 struct rx_header *rh;
                 u16 len;
 
-                pci_dma_sync_single_for_cpu(bp->pdev, map,
+                dma_sync_single_for_cpu(&bp->sdev->dev, map,
                                             RX_PKT_BUF_SZ,
-                                            PCI_DMA_FROMDEVICE);
+                                            DMA_FROM_DEVICE);
                 rh = (struct rx_header *) skb->data;
                 len = cpu_to_le16(rh->len);
                 if ((len > (RX_PKT_BUF_SZ - bp->rx_offset)) ||
@@ -808 +754 @@
                         skb_size = b44_alloc_rx_skb(bp, cons, bp->rx_prod);
                         if (skb_size < 0)
                                 goto drop_it;
-                        pci_unmap_single(bp->pdev, map,
-                                         skb_size, PCI_DMA_FROMDEVICE);
+                        dma_unmap_single(&bp->sdev->dev, map,
+                                         skb_size, DMA_FROM_DEVICE);
                         /* Leave out rx_header */
-                        skb_put(skb, len+bp->rx_offset);
-                        skb_pull(skb,bp->rx_offset);
+                skb_put(skb, len+bp->rx_offset);
+                        skb_pull(skb,bp->rx_offset);
                 } else {
                         struct sk_buff *copy_skb;
 
@@ -980 +926 @@
                 goto err_out;
         }
 
-        mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
+        mapping = dma_map_single(&bp->sdev->dev, skb->data, len, DMA_TO_DEVICE);
         if (dma_mapping_error(mapping) || mapping + len > B44_DMA_MASK) {
                 /* Chip can't handle DMA to/from >1GB, use bounce buffer */
                 if (!dma_mapping_error(mapping))
-                        pci_unmap_single(bp->pdev, mapping, len, PCI_DMA_TODEVICE);
+                        dma_unmap_single(&bp->sdev->dev, mapping, len, DMA_TO_DEVICE);
 
                 bounce_skb = __dev_alloc_skb(TX_PKT_BUF_SZ,
                                              GFP_ATOMIC|GFP_DMA);
                 if (!bounce_skb)
                         goto err_out;
 
-                mapping = pci_map_single(bp->pdev, bounce_skb->data,
-                                         len, PCI_DMA_TODEVICE);
+                mapping = dma_map_single(&bp->sdev->dev, bounce_skb->data,
+                                         len, DMA_TO_DEVICE);
                 if (dma_mapping_error(mapping) || mapping + len > B44_DMA_MASK) {
                         if (!dma_mapping_error(mapping))
-                                pci_unmap_single(bp->pdev, mapping,
-                                         len, PCI_DMA_TODEVICE);
+                                dma_unmap_single(&bp->sdev->dev, mapping,
+                                         len, DMA_TO_DEVICE);
                         dev_kfree_skb_any(bounce_skb);
                         goto err_out;
                 }
@@ -1019 +965 @@
         bp->tx_ring[entry].addr = cpu_to_le32((u32) mapping+bp->dma_offset);
 
         if (bp->flags & B44_FLAG_TX_RING_HACK)
-                b44_sync_dma_desc_for_device(bp->pdev, bp->tx_ring_dma,
-                                             entry * sizeof(bp->tx_ring[0]),
-                                             DMA_TO_DEVICE);
+                b44_sync_dma_desc_for_device(bp->sdev, bp->tx_ring_dma,
+                                            entry * sizeof(bp->tx_ring[0]),
+                                            DMA_TO_DEVICE);
 
         entry = NEXT_TX(entry);
 
@@ -1094 +1040 @@
 
                 if (rp->skb == NULL)
                         continue;
-                pci_unmap_single(bp->pdev,
+                dma_unmap_single(&bp->sdev->dev,
                                  pci_unmap_addr(rp, mapping),
                                  RX_PKT_BUF_SZ,
-                                 PCI_DMA_FROMDEVICE);
+                                 DMA_FROM_DEVICE);
                 dev_kfree_skb_any(rp->skb);
                 rp->skb = NULL;
         }
@@ -1108 +1054 @@
 
                 if (rp->skb == NULL)
                         continue;
-                pci_unmap_single(bp->pdev,
+                dma_unmap_single(&bp->sdev->dev,
                                  pci_unmap_addr(rp, mapping),
                                  rp->skb->len,
-                                 PCI_DMA_TODEVICE);
+                                 DMA_TO_DEVICE);
                 dev_kfree_skb_any(rp->skb);
                 rp->skb = NULL;
         }
@@ -1133 +1079 @@
         memset(bp->tx_ring, 0, B44_TX_RING_BYTES);
 
         if (bp->flags & B44_FLAG_RX_RING_HACK)
-                dma_sync_single_for_device(&bp->pdev->dev, bp->rx_ring_dma,
-                                           DMA_TABLE_BYTES,
-                                           PCI_DMA_BIDIRECTIONAL);
+                dma_sync_single_for_device(&bp->sdev->dev, bp->rx_ring_dma,
+                                          DMA_TABLE_BYTES,
+                                          DMA_BIDIRECTIONAL);
 
         if (bp->flags & B44_FLAG_TX_RING_HACK)
-                dma_sync_single_for_device(&bp->pdev->dev, bp->tx_ring_dma,
-                                           DMA_TABLE_BYTES,
-                                           PCI_DMA_TODEVICE);
+                dma_sync_single_for_device(&bp->sdev->dev, bp->tx_ring_dma,
+                                          DMA_TABLE_BYTES,
+                                          DMA_TO_DEVICE);
 
         for (i = 0; i < bp->rx_pending; i++) {
                 if (b44_alloc_rx_skb(bp, -1, i) < 0)
@@ -1160 +1106 @@
         bp->tx_buffers = NULL;
         if (bp->rx_ring) {
                 if (bp->flags & B44_FLAG_RX_RING_HACK) {
-                        dma_unmap_single(&bp->pdev->dev, bp->rx_ring_dma,
-                                         DMA_TABLE_BYTES,
-                                         DMA_BIDIRECTIONAL);
+                        dma_unmap_single(&bp->sdev->dev, bp->rx_ring_dma,
+                                        DMA_TABLE_BYTES,
+                                        DMA_BIDIRECTIONAL);
                         kfree(bp->rx_ring);
                 } else
-                        pci_free_consistent(bp->pdev, DMA_TABLE_BYTES,
+                        dma_free_coherent(&bp->sdev->dev, DMA_TABLE_BYTES,
                                             bp->rx_ring, bp->rx_ring_dma);
                 bp->rx_ring = NULL;
                 bp->flags &= ~B44_FLAG_RX_RING_HACK;
         }
         if (bp->tx_ring) {
                 if (bp->flags & B44_FLAG_TX_RING_HACK) {
-                        dma_unmap_single(&bp->pdev->dev, bp->tx_ring_dma,
-                                         DMA_TABLE_BYTES,
-                                         DMA_TO_DEVICE);
+                        dma_unmap_single(&bp->sdev->dev, bp->tx_ring_dma,
+                                        DMA_TABLE_BYTES,
+                                        DMA_TO_DEVICE);
                         kfree(bp->tx_ring);
                 } else
-                        pci_free_consistent(bp->pdev, DMA_TABLE_BYTES,
+                        dma_free_coherent(&bp->sdev->dev, DMA_TABLE_BYTES,
                                             bp->tx_ring, bp->tx_ring_dma);
                 bp->tx_ring = NULL;
                 bp->flags &= ~B44_FLAG_TX_RING_HACK;
@@ -1203 +1149 @@
                 goto out_err;
 
         size = DMA_TABLE_BYTES;
-        bp->rx_ring = pci_alloc_consistent(bp->pdev, size, &bp->rx_ring_dma);
+        bp->rx_ring = dma_alloc_coherent(&bp->sdev->dev, size, &bp->rx_ring_dma, GFP_ATOMIC);
         if (!bp->rx_ring) {
                 /* Allocation may have failed due to pci_alloc_consistent
                    insisting on use of GFP_DMA, which is more restrictive
@@ -1215 +1161 @@
                 if (!rx_ring)
                         goto out_err;
 
-                rx_ring_dma = dma_map_single(&bp->pdev->dev, rx_ring,
-                                             DMA_TABLE_BYTES,
-                                             DMA_BIDIRECTIONAL);
+                rx_ring_dma = dma_map_single(&bp->sdev->dev, rx_ring,
+                                            DMA_TABLE_BYTES,
+                                            DMA_BIDIRECTIONAL);
 
                 if (dma_mapping_error(rx_ring_dma) ||
                         rx_ring_dma + size > B44_DMA_MASK) {
@@ -1230 +1176 @@
                 bp->flags |= B44_FLAG_RX_RING_HACK;
         }
 
-        bp->tx_ring = pci_alloc_consistent(bp->pdev, size, &bp->tx_ring_dma);
+        bp->tx_ring = dma_alloc_coherent(&bp->sdev->dev, size, &bp->tx_ring_dma, GFP_ATOMIC);
         if (!bp->tx_ring) {
-                /* Allocation may have failed due to pci_alloc_consistent
+                /* Allocation may have failed due to dma_alloc_coherent
                    insisting on use of GFP_DMA, which is more restrictive
                    than necessary...  */
                 struct dma_desc *tx_ring;
@@ -1242 +1188 @@
                 if (!tx_ring)
                         goto out_err;
 
-                tx_ring_dma = dma_map_single(&bp->pdev->dev, tx_ring,
-                                             DMA_TABLE_BYTES,
-                                             DMA_TO_DEVICE);
+                tx_ring_dma = dma_map_single(&bp->sdev->dev, tx_ring,
+                                            DMA_TABLE_BYTES,
+                                            DMA_TO_DEVICE);
 
                 if (dma_mapping_error(tx_ring_dma) ||
                         tx_ring_dma + size > B44_DMA_MASK) {
@@ -1279 +1225 @@
 /* bp->lock is held. */
 static void b44_chip_reset(struct b44 *bp)
 {
-        if (ssb_is_core_up(bp)) {
+        struct ssb_device *sdev = bp->sdev;
+
+        if (ssb_core_is_enabled(bp->sdev)) {
                 bw32(bp, B44_RCV_LAZY, 0);
                 bw32(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE);
                 b44_wait_bit(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE, 100, 1);
@@ -1291 +1239 @@
                 }
                 bw32(bp, B44_DMARX_CTRL, 0);
                 bp->rx_prod = bp->rx_cons = 0;
-        } else {
-                ssb_pci_setup(bp, (bp->core_unit == 0 ?
-                                   SBINTVEC_ENET0 :
-                                   SBINTVEC_ENET1));
         }
 
-        ssb_core_reset(bp);
-
+        ssb_core_enable(bp->sdev, 0);
         b44_clear_stats(bp);
 
-        /* Make PHY accessible. */
-        bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
+        switch (sdev->bus->bustype) {
+        case SSB_BUSTYPE_SSB: 
+                        bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
+                             (((ssb_clockspeed(sdev->bus) + (B44_MDC_RATIO / 2)) / B44_MDC_RATIO)
+                             & MDIO_CTRL_MAXF_MASK)));
+                break;
+        case SSB_BUSTYPE_PCI:
+                bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
                              (0x0d & MDIO_CTRL_MAXF_MASK)));
+                break;
+        }
+
         br32(bp, B44_MDIO_CTRL);
 
         if (!(br32(bp, B44_DEVCTRL) & DEVCTRL_IPP)) {
@@ -1346 +1298 @@
 {
         struct b44 *bp = netdev_priv(dev);
         struct sockaddr *addr = p;
+        u32 val;
 
         if (netif_running(dev))
                 return -EBUSY;
@@ -1356 +1309 @@
         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
 
         spin_lock_irq(&bp->lock);
-        __b44_set_mac_addr(bp);
+   
+        val = br32(bp, B44_RXCONFIG);
+        if (!(val & RXCONFIG_CAM_ABSENT))
+                __b44_set_mac_addr(bp);
+   
         spin_unlock_irq(&bp->lock);
 
         return 0;
@@ -1442 +1399 @@
         return err;
 }
 
-#if 0
-/*static*/ void b44_dump_state(struct b44 *bp)
-{
-        u32 val32, val32_2, val32_3, val32_4, val32_5;
-        u16 val16;
-
-        pci_read_config_word(bp->pdev, PCI_STATUS, &val16);
-        printk("DEBUG: PCI status [%04x] \n", val16);
-
-}
-#endif
-
 #ifdef CONFIG_NET_POLL_CONTROLLER
 /*
  * Polling receive - used by netconsole and other diagnostic tools
@@ -1568 +1513 @@
 static void b44_setup_wol(struct b44 *bp)
 {
         u32 val;
-        u16 pmval;
 
         bw32(bp, B44_RXCONFIG, RXCONFIG_ALLMULTI);
 
@@ -1592 +1536 @@
         } else {
                 b44_setup_pseudo_magicp(bp);
         }
-
-        val = br32(bp, B44_SBTMSLOW);
-        bw32(bp, B44_SBTMSLOW, val | SBTMSLOW_PE);
-
-        pci_read_config_word(bp->pdev, SSB_PMCSR, &pmval);
-        pci_write_config_word(bp->pdev, SSB_PMCSR, pmval | SSB_PE);
-
 }
 
 static int b44_close(struct net_device *dev)
@@ -1698 +1635 @@
 
         val = br32(bp, B44_RXCONFIG);
         val &= ~(RXCONFIG_PROMISC | RXCONFIG_ALLMULTI);
-        if (dev->flags & IFF_PROMISC) {
+        if ((dev->flags & IFF_PROMISC) || (val & RXCONFIG_CAM_ABSENT)) {
                 val |= RXCONFIG_PROMISC;
                 bw32(bp, B44_RXCONFIG, val);
         } else {
@@ -1745 +1682 @@
 
 static void b44_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
 {
-        struct b44 *bp = netdev_priv(dev);
-        struct pci_dev *pci_dev = bp->pdev;
-
         strcpy (info->driver, DRV_MODULE_NAME);
         strcpy (info->version, DRV_MODULE_VERSION);
-        strcpy (info->bus_info, pci_name(pci_dev));
 }
 
 static int b44_nway_reset(struct net_device *dev)
@@ -2034 +1967 @@
         .get_perm_addr          = ethtool_op_get_perm_addr,
 };
 
+static int b44_ethtool_ioctl (struct net_device *dev, void __user *useraddr)
+{
+        struct b44 *bp = dev->priv;
+        u32 ethcmd;
+
+        if (copy_from_user (&ethcmd, useraddr, sizeof (ethcmd)))
+                return -EFAULT;
+
+        switch (ethcmd) {
+        case ETHTOOL_GDRVINFO: {
+                struct ethtool_drvinfo info = { ETHTOOL_GDRVINFO };
+                strcpy (info.driver, DRV_MODULE_NAME);
+                strcpy (info.version, DRV_MODULE_VERSION);
+                memset(&info.fw_version, 0, sizeof(info.fw_version));
+                info.eedump_len = 0;
+                info.regdump_len = 0;
+                if (copy_to_user (useraddr, &info, sizeof (info)))
+                        return -EFAULT;
+                return 0;
+        }
+
+        case ETHTOOL_GSET: {
+                struct ethtool_cmd cmd = { ETHTOOL_GSET };
+
+                if (!(bp->flags & B44_FLAG_INIT_COMPLETE))
+                        return -EAGAIN;
+                cmd.supported = (SUPPORTED_Autoneg);
+                cmd.supported |= (SUPPORTED_100baseT_Half |
+                                  SUPPORTED_100baseT_Full |
+                                  SUPPORTED_10baseT_Half |
+                                  SUPPORTED_10baseT_Full |
+                                  SUPPORTED_MII);
+
+                cmd.advertising = 0;
+                if (bp->flags & B44_FLAG_ADV_10HALF)
+                        cmd.advertising |= ADVERTISE_10HALF;
+                if (bp->flags & B44_FLAG_ADV_10FULL)
+                        cmd.advertising |= ADVERTISE_10FULL;
+                if (bp->flags & B44_FLAG_ADV_100HALF)
+                        cmd.advertising |= ADVERTISE_100HALF;
+                if (bp->flags & B44_FLAG_ADV_100FULL)
+                        cmd.advertising |= ADVERTISE_100FULL;
+                cmd.advertising |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
+                cmd.speed = (bp->flags & B44_FLAG_100_BASE_T) ?
+                        SPEED_100 : SPEED_10;
+                cmd.duplex = (bp->flags & B44_FLAG_FULL_DUPLEX) ?
+                        DUPLEX_FULL : DUPLEX_HALF;
+                cmd.port = 0;
+                cmd.phy_address = bp->phy_addr;
+                cmd.transceiver = (bp->flags & B44_FLAG_INTERNAL_PHY) ?
+                        XCVR_INTERNAL : XCVR_EXTERNAL;
+                cmd.autoneg = (bp->flags & B44_FLAG_FORCE_LINK) ?
+                        AUTONEG_DISABLE : AUTONEG_ENABLE;
+                cmd.maxtxpkt = 0;
+                cmd.maxrxpkt = 0;
+                if (copy_to_user(useraddr, &cmd, sizeof(cmd)))
+                        return -EFAULT;
+                return 0;
+        }
+        case ETHTOOL_SSET: {
+                struct ethtool_cmd cmd;
+
+                if (!(bp->flags & B44_FLAG_INIT_COMPLETE))
+                        return -EAGAIN;
+
+                if (copy_from_user(&cmd, useraddr, sizeof(cmd)))
+                        return -EFAULT;
+
+                /* We do not support gigabit. */
+                if (cmd.autoneg == AUTONEG_ENABLE) {
+                        if (cmd.advertising &
+                            (ADVERTISED_1000baseT_Half |
+                             ADVERTISED_1000baseT_Full))
+                                return -EINVAL;
+                } else if ((cmd.speed != SPEED_100 &&
+                            cmd.speed != SPEED_10) ||
+                           (cmd.duplex != DUPLEX_HALF &&
+                            cmd.duplex != DUPLEX_FULL)) {
+                                return -EINVAL;
+                }
+
+                spin_lock_irq(&bp->lock);
+
+                if (cmd.autoneg == AUTONEG_ENABLE) {
+                        bp->flags &= ~B44_FLAG_FORCE_LINK;
+                        bp->flags &= ~(B44_FLAG_ADV_10HALF |
+                                       B44_FLAG_ADV_10FULL |
+                                       B44_FLAG_ADV_100HALF |
+                                       B44_FLAG_ADV_100FULL);
+                        if (cmd.advertising & ADVERTISE_10HALF)
+                                bp->flags |= B44_FLAG_ADV_10HALF;
+                        if (cmd.advertising & ADVERTISE_10FULL)
+                                bp->flags |= B44_FLAG_ADV_10FULL;
+                        if (cmd.advertising & ADVERTISE_100HALF)
+                                bp->flags |= B44_FLAG_ADV_100HALF;
+                        if (cmd.advertising & ADVERTISE_100FULL)
+                                bp->flags |= B44_FLAG_ADV_100FULL;
+                } else {
+                        bp->flags |= B44_FLAG_FORCE_LINK;
+                        if (cmd.speed == SPEED_100)
+                                bp->flags |= B44_FLAG_100_BASE_T;
+                        if (cmd.duplex == DUPLEX_FULL)
+                                bp->flags |= B44_FLAG_FULL_DUPLEX;
+                }
+
+                b44_setup_phy(bp);
+
+                spin_unlock_irq(&bp->lock);
+
+                return 0;
+        }
+
+        case ETHTOOL_GMSGLVL: {
+                struct ethtool_value edata = { ETHTOOL_GMSGLVL };
+                edata.data = bp->msg_enable;
+                if (copy_to_user(useraddr, &edata, sizeof(edata)))
+                        return -EFAULT;
+                return 0;
+        }
+        case ETHTOOL_SMSGLVL: {
+                struct ethtool_value edata;
+                if (copy_from_user(&edata, useraddr, sizeof(edata)))
+                        return -EFAULT;
+                bp->msg_enable = edata.data;
+                return 0;
+        }
+        case ETHTOOL_NWAY_RST: {
+                u32 bmcr;
+                int r;
+
+                spin_lock_irq(&bp->lock);
+                b44_readphy(bp, MII_BMCR, &bmcr);
+                b44_readphy(bp, MII_BMCR, &bmcr);
+                r = -EINVAL;
+                if (bmcr & BMCR_ANENABLE) {
+                        b44_writephy(bp, MII_BMCR,
+                                     bmcr | BMCR_ANRESTART);
+                        r = 0;
+                }
+                spin_unlock_irq(&bp->lock);
+
+                return r;
+        }
+        case ETHTOOL_GLINK: {
+                struct ethtool_value edata = { ETHTOOL_GLINK };
+                edata.data = netif_carrier_ok(bp->dev) ? 1 : 0;
+                if (copy_to_user(useraddr, &edata, sizeof(edata)))
+                        return -EFAULT;
+                return 0;
+        }
+        case ETHTOOL_GRINGPARAM: {
+                struct ethtool_ringparam ering = { ETHTOOL_GRINGPARAM };
+
+                ering.rx_max_pending = B44_RX_RING_SIZE - 1;
+                ering.rx_pending = bp->rx_pending;
+
+                /* XXX ethtool lacks a tx_max_pending, oops... */
+
+                if (copy_to_user(useraddr, &ering, sizeof(ering)))
+                        return -EFAULT;
+                return 0;
+        }
+        case ETHTOOL_SRINGPARAM: {
+                struct ethtool_ringparam ering;
+
+                if (copy_from_user(&ering, useraddr, sizeof(ering)))
+                        return -EFAULT;
+
+                if ((ering.rx_pending > B44_RX_RING_SIZE - 1) ||
+                    (ering.rx_mini_pending != 0) ||
+                    (ering.rx_jumbo_pending != 0) ||
+                    (ering.tx_pending > B44_TX_RING_SIZE - 1))
+                        return -EINVAL;
+
+                spin_lock_irq(&bp->lock);
+
+                bp->rx_pending = ering.rx_pending;
+                bp->tx_pending = ering.tx_pending;
+
+                b44_halt(bp);
+                b44_init_rings(bp);
+                b44_init_hw(bp, 1);
+                netif_wake_queue(bp->dev);
+                spin_unlock_irq(&bp->lock);
+
+                b44_enable_ints(bp);
+                
+                return 0;
+        }
+        case ETHTOOL_GPAUSEPARAM: {
+                struct ethtool_pauseparam epause = { ETHTOOL_GPAUSEPARAM };
+
+                epause.autoneg =
+                        (bp->flags & B44_FLAG_PAUSE_AUTO) != 0;
+                epause.rx_pause =
+                        (bp->flags & B44_FLAG_RX_PAUSE) != 0;
+                epause.tx_pause =
+                        (bp->flags & B44_FLAG_TX_PAUSE) != 0;
+                if (copy_to_user(useraddr, &epause, sizeof(epause)))
+                        return -EFAULT;
+                return 0;
+        }
+        case ETHTOOL_SPAUSEPARAM: {
+                struct ethtool_pauseparam epause;
+
+                if (copy_from_user(&epause, useraddr, sizeof(epause)))
+                        return -EFAULT;
+
+                spin_lock_irq(&bp->lock);
+                if (epause.autoneg)
+                        bp->flags |= B44_FLAG_PAUSE_AUTO;
+                else
+                        bp->flags &= ~B44_FLAG_PAUSE_AUTO;
+                if (epause.rx_pause)
+                        bp->flags |= B44_FLAG_RX_PAUSE;
+                else
+                        bp->flags &= ~B44_FLAG_RX_PAUSE;
+                if (epause.tx_pause)
+                        bp->flags |= B44_FLAG_TX_PAUSE;
+                else
+                        bp->flags &= ~B44_FLAG_TX_PAUSE;
+                if (bp->flags & B44_FLAG_PAUSE_AUTO) {
+                        b44_halt(bp);
+                        b44_init_rings(bp);
+                        b44_init_hw(bp, 1);
+                } else {
+                        __b44_set_flow_ctrl(bp, bp->flags);
+                }
+                spin_unlock_irq(&bp->lock);
+
+                b44_enable_ints(bp);
+                
+                return 0;
+        }
+        };
+
+        return -EOPNOTSUPP;
+}
+
 static int b44_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 {
         struct mii_ioctl_data *data = if_mii(ifr);
@@ -2043 +2215 @@
         if (!netif_running(dev))
                 goto out;
 
-        spin_lock_irq(&bp->lock);
-        err = generic_mii_ioctl(&bp->mii_if, data, cmd, NULL);
-        spin_unlock_irq(&bp->lock);
-out:
-        return err;
-}
+        switch (cmd) {
+        case SIOCETHTOOL:
+               return b44_ethtool_ioctl(dev, (void __user*) ifr->ifr_data);
 
-/* Read 128-bytes of EEPROM. */
-static int b44_read_eeprom(struct b44 *bp, u8 *data)
-{
-        long i;
-        u16 *ptr = (u16 *) data;
+        case SIOCGMIIPHY:
+               data->phy_id = bp->phy_addr;
 
-        for (i = 0; i < 128; i += 2)
-                ptr[i / 2] = cpu_to_le16(readw(bp->regs + 4096 + i));
+               /* fallthru */
+        case SIOCGMIIREG: {
+               u32 mii_regval;
+               spin_lock_irq(&bp->lock);
+               err = __b44_readphy(bp, data->phy_id & 0x1f, data->reg_num & 0x1f, &mii_regval);
+               spin_unlock_irq(&bp->lock);
 
-        return 0;
+               data->val_out = mii_regval;
+
+               return err;
+        }
+
+        case SIOCSMIIREG:
+               if (!capable(CAP_NET_ADMIN))
+                      return -EPERM;
+
+               spin_lock_irq(&bp->lock);
+               err = __b44_writephy(bp, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
+               spin_unlock_irq(&bp->lock);
+
+               return err;
+
+        default:
+               break;
+        };
+        return -EOPNOTSUPP;
+
+out:
+        return err;
 }
 
 static int __devinit b44_get_invariants(struct b44 *bp)
 {
-        u8 eeprom[128];
-        int err;
+        struct ssb_device *sdev = bp->sdev;
+        int err = 0;
+        u8 *addr;
 
-        err = b44_read_eeprom(bp, &eeprom[0]);
-        if (err)
-                goto out;
+        bp->dma_offset = ssb_dma_offset(sdev);
 
-        bp->dev->dev_addr[0] = eeprom[79];
-        bp->dev->dev_addr[1] = eeprom[78];
-        bp->dev->dev_addr[2] = eeprom[81];
-        bp->dev->dev_addr[3] = eeprom[80];
-        bp->dev->dev_addr[4] = eeprom[83];
-        bp->dev->dev_addr[5] = eeprom[82];
+        switch (instance) {
+        case 1:
+               addr = sdev->bus->sprom.r1.et0mac;
+               bp->phy_addr = sdev->bus->sprom.r1.et0phyaddr;
+               break;
+        default:
+               addr = sdev->bus->sprom.r1.et1mac;
+               bp->phy_addr = sdev->bus->sprom.r1.et1phyaddr;
+               break;
+        }
+
+        memcpy(bp->dev->dev_addr, addr, 6);
 
         if (!is_valid_ether_addr(&bp->dev->dev_addr[0])){
                 printk(KERN_ERR PFX "Invalid MAC address found in EEPROM\n");
@@ -2085 +2281 @@
 
         memcpy(bp->dev->perm_addr, bp->dev->dev_addr, bp->dev->addr_len);
 
-        bp->phy_addr = eeprom[90] & 0x1f;
-
         /* With this, plus the rx_header prepended to the data by the
          * hardware, we'll land the ethernet header on a 2-byte boundary.
          */
         bp->rx_offset = 30;
-
         bp->imask = IMASK_DEF;
-
-        bp->core_unit = ssb_core_unit(bp);
-        bp->dma_offset = SB_PCI_DMA;
-
         /* XXX - really required?
            bp->flags |= B44_FLAG_BUGGY_TXPTR;
-         */
+        */
 
-        if (ssb_get_core_rev(bp) >= 7)
-                bp->flags |= B44_FLAG_B0_ANDLATER;
-
-out:
         return err;
 }
 
-static int __devinit b44_init_one(struct pci_dev *pdev,
-                                  const struct pci_device_id *ent)
+static int __devinit b44_init_one(struct ssb_device *sdev,
+                                  const struct ssb_device_id *ent)
 {
         static int b44_version_printed = 0;
-        unsigned long b44reg_base, b44reg_len;
         struct net_device *dev;
         struct b44 *bp;
         int err, i;
 
+        instance++;
+
         if (b44_version_printed++ == 0)
                 printk(KERN_INFO "%s", version);
 
-        err = pci_enable_device(pdev);
-        if (err) {
-                dev_err(&pdev->dev, "Cannot enable PCI device, "
-                       "aborting.\n");
-                return err;
-        }
-
-        if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
-                dev_err(&pdev->dev,
-                        "Cannot find proper PCI device "
-                       "base address, aborting.\n");
-                err = -ENODEV;
-                goto err_out_disable_pdev;
-        }
-
-        err = pci_request_regions(pdev, DRV_MODULE_NAME);
-        if (err) {
-                dev_err(&pdev->dev,
-                        "Cannot obtain PCI resources, aborting.\n");
-                goto err_out_disable_pdev;
-        }
-
-        pci_set_master(pdev);
-
-        err = pci_set_dma_mask(pdev, (u64) B44_DMA_MASK);
-        if (err) {
-                dev_err(&pdev->dev, "No usable DMA configuration, aborting.\n");
-                goto err_out_free_res;
-        }
-
-        err = pci_set_consistent_dma_mask(pdev, (u64) B44_DMA_MASK);
-        if (err) {
-                dev_err(&pdev->dev, "No usable DMA configuration, aborting.\n");
-                goto err_out_free_res;
-        }
-
-        b44reg_base = pci_resource_start(pdev, 0);
-        b44reg_len = pci_resource_len(pdev, 0);
-
         dev = alloc_etherdev(sizeof(*bp));
         if (!dev) {
-                dev_err(&pdev->dev, "Etherdev alloc failed, aborting.\n");
+                dev_err(&sdev->dev, "Etherdev alloc failed, aborting.\n");
                 err = -ENOMEM;
-                goto err_out_free_res;
+                goto out;
         }
 
         SET_MODULE_OWNER(dev);
-        SET_NETDEV_DEV(dev,&pdev->dev);
+        SET_NETDEV_DEV(dev,&sdev->dev);
 
         /* No interesting netdevice features in this card... */
         dev->features |= 0;
 
         bp = netdev_priv(dev);
-        bp->pdev = pdev;
+        bp->sdev = sdev;
         bp->dev = dev;
 
         bp->msg_enable = netif_msg_init(b44_debug, B44_DEF_MSG_ENABLE);
 
         spin_lock_init(&bp->lock);
 
-        bp->regs = ioremap(b44reg_base, b44reg_len);
-        if (bp->regs == 0UL) {
-                dev_err(&pdev->dev, "Cannot map device registers, aborting.\n");
-                err = -ENOMEM;
-                goto err_out_free_dev;
-        }
-
         bp->rx_pending = B44_DEF_RX_RING_PENDING;
         bp->tx_pending = B44_DEF_TX_RING_PENDING;
 
@@ -2205 +2345 @@
         dev->poll_controller = b44_poll_controller;
 #endif
         dev->change_mtu = b44_change_mtu;
-        dev->irq = pdev->irq;
+        dev->irq = sdev->irq;
         SET_ETHTOOL_OPS(dev, &b44_ethtool_ops);
 
         netif_carrier_off(dev);
 
         err = b44_get_invariants(bp);
         if (err) {
-                dev_err(&pdev->dev,
+                dev_err(&sdev->dev,
                         "Problem fetching invariants of chip, aborting.\n");
-                goto err_out_iounmap;
+                goto err_out_free_dev;
         }
 
         bp->mii_if.dev = dev;
@@ -2233 +2373 @@
 
         err = register_netdev(dev);
         if (err) {
-                dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
-                goto err_out_iounmap;
+                dev_err(&sdev->dev, "Cannot register net device, aborting.\n");
+                goto out;
         }
 
-        pci_set_drvdata(pdev, dev);
-
-        pci_save_state(bp->pdev);
+        ssb_set_drvdata(sdev, dev);
 
         /* Chip reset provides power to the b44 MAC & PCI cores, which
          * is necessary for MAC register access.
          */
         b44_chip_reset(bp);
 
-        printk(KERN_INFO "%s: Broadcom 4400 10/100BaseT Ethernet ", dev->name);
+        printk(KERN_INFO "%s: Broadcom 10/100BaseT Ethernet ", dev->name);
         for (i = 0; i < 6; i++)
                 printk("%2.2x%c", dev->dev_addr[i],
                        i == 5 ? '\n' : ':');
 
-        return 0;
+        /* Initialize phy */
+        spin_lock_irq(&bp->lock);
+        b44_chip_reset(bp);
+        spin_unlock_irq(&bp->lock);
 
-err_out_iounmap:
-        iounmap(bp->regs);
+        return 0;
 
 err_out_free_dev:
         free_netdev(dev);
 
-err_out_free_res:
-        pci_release_regions(pdev);
-
-err_out_disable_pdev:
-        pci_disable_device(pdev);
-        pci_set_drvdata(pdev, NULL);
+out:
         return err;
 }
 
-static void __devexit b44_remove_one(struct pci_dev *pdev)
+static void __devexit b44_remove_one(struct ssb_device *pdev)
 {
-        struct net_device *dev = pci_get_drvdata(pdev);
-        struct b44 *bp = netdev_priv(dev);
+        struct net_device *dev = ssb_get_drvdata(pdev);
 
         unregister_netdev(dev);
-        iounmap(bp->regs);
         free_netdev(dev);
-        pci_release_regions(pdev);
-        pci_disable_device(pdev);
-        pci_set_drvdata(pdev, NULL);
+        ssb_set_drvdata(pdev, NULL);
 }
 
-static int b44_suspend(struct pci_dev *pdev, pm_message_t state)
+static int b44_suspend(struct ssb_device *pdev, pm_message_t state)
 {
-        struct net_device *dev = pci_get_drvdata(pdev);
+        struct net_device *dev = ssb_get_drvdata(pdev);
         struct b44 *bp = netdev_priv(dev);
 
         if (!netif_running(dev))
-                 return 0;
+                return 0;
 
         del_timer_sync(&bp->timer);
 
@@ -2305 +2436 @@
                 b44_init_hw(bp, 0);
                 b44_setup_wol(bp);
         }
-        pci_disable_device(pdev);
+
         return 0;
 }
 
-static int b44_resume(struct pci_dev *pdev)
+static int b44_resume(struct ssb_device *pdev)
 {
-        struct net_device *dev = pci_get_drvdata(pdev);
+        struct net_device *dev = ssb_get_drvdata(pdev);
         struct b44 *bp = netdev_priv(dev);
 
-        pci_restore_state(pdev);
-        pci_enable_device(pdev);
-        pci_set_master(pdev);
-
         if (!netif_running(dev))
                 return 0;
 
@@ -2339 +2466 @@
         return 0;
 }
 
-static struct pci_driver b44_driver = {
+static struct ssb_driver b44_driver = {
         .name           = DRV_MODULE_NAME,
-        .id_table       = b44_pci_tbl,
+        .id_table       = b44_ssb_tbl,
         .probe          = b44_init_one,
         .remove         = __devexit_p(b44_remove_one),
-        .suspend        = b44_suspend,
-        .resume         = b44_resume,
+        .suspend        = b44_suspend,
+        .resume         = b44_resume,
 };
 
 static int __init b44_init(void)
 {
         unsigned int dma_desc_align_size = dma_get_cache_alignment();
 
+        instance = 0;
+
         /* Setup paramaters for syncing RX/TX DMA descriptors */
         dma_desc_align_mask = ~(dma_desc_align_size - 1);
         dma_desc_sync_size = max_t(unsigned int, dma_desc_align_size, sizeof(struct dma_desc));
 
-        return pci_register_driver(&b44_driver);
+        return ssb_driver_register(&b44_driver);
 }
 
 static void __exit b44_cleanup(void)
 {
-        pci_unregister_driver(&b44_driver);
+        ssb_driver_unregister(&b44_driver);
 }
 
 module_init(b44_init);

drivers/net/b44.h

@@ -129 +129 @@
 #define  RXCONFIG_FLOW          0x00000020 /* Flow Control Enable */
 #define  RXCONFIG_FLOW_ACCEPT   0x00000040 /* Accept Unicast Flow Control Frame */
 #define  RXCONFIG_RFILT         0x00000080 /* Reject Filter */
+#define  RXCONFIG_CAM_ABSENT    0x00000100 /* CAM Absent */
 #define B44_RXMAXLEN    0x0404UL /* EMAC RX Max Packet Length */
 #define B44_TXMAXLEN    0x0408UL /* EMAC TX Max Packet Length */
 #define B44_MDIO_CTRL   0x0410UL /* EMAC MDIO Control */
@@ -227 +228 @@
 #define B44_RX_PAUSE    0x05D4UL /* MIB RX Pause Packets */
 #define B44_RX_NPAUSE   0x05D8UL /* MIB RX Non-Pause Packets */
 
-/* Silicon backplane register definitions */
-#define B44_SBIMSTATE   0x0F90UL /* SB Initiator Agent State */
-#define  SBIMSTATE_PC           0x0000000f /* Pipe Count */
-#define  SBIMSTATE_AP_MASK      0x00000030 /* Arbitration Priority */
-#define  SBIMSTATE_AP_BOTH      0x00000000 /* Use both timeslices and token */
-#define  SBIMSTATE_AP_TS        0x00000010 /* Use timeslices only */
-#define  SBIMSTATE_AP_TK        0x00000020 /* Use token only */
-#define  SBIMSTATE_AP_RSV       0x00000030 /* Reserved */
-#define  SBIMSTATE_IBE          0x00020000 /* In Band Error */
-#define  SBIMSTATE_TO           0x00040000 /* Timeout */
-#define B44_SBINTVEC    0x0F94UL /* SB Interrupt Mask */
-#define  SBINTVEC_PCI           0x00000001 /* Enable interrupts for PCI */
-#define  SBINTVEC_ENET0         0x00000002 /* Enable interrupts for enet 0 */
-#define  SBINTVEC_ILINE20       0x00000004 /* Enable interrupts for iline20 */
-#define  SBINTVEC_CODEC         0x00000008 /* Enable interrupts for v90 codec */
-#define  SBINTVEC_USB           0x00000010 /* Enable interrupts for usb */
-#define  SBINTVEC_EXTIF         0x00000020 /* Enable interrupts for external i/f */
-#define  SBINTVEC_ENET1         0x00000040 /* Enable interrupts for enet 1 */
-#define B44_SBTMSLOW    0x0F98UL /* SB Target State Low */
-#define  SBTMSLOW_RESET         0x00000001 /* Reset */
-#define  SBTMSLOW_REJECT        0x00000002 /* Reject */
-#define  SBTMSLOW_CLOCK         0x00010000 /* Clock Enable */
-#define  SBTMSLOW_FGC           0x00020000 /* Force Gated Clocks On */
-#define  SBTMSLOW_PE            0x40000000 /* Power Management Enable */
-#define  SBTMSLOW_BE            0x80000000 /* BIST Enable */
-#define B44_SBTMSHIGH   0x0F9CUL /* SB Target State High */
-#define  SBTMSHIGH_SERR         0x00000001 /* S-error */
-#define  SBTMSHIGH_INT          0x00000002 /* Interrupt */
-#define  SBTMSHIGH_BUSY         0x00000004 /* Busy */
-#define  SBTMSHIGH_GCR          0x20000000 /* Gated Clock Request */
-#define  SBTMSHIGH_BISTF        0x40000000 /* BIST Failed */
-#define  SBTMSHIGH_BISTD        0x80000000 /* BIST Done */
-#define B44_SBIDHIGH    0x0FFCUL /* SB Identification High */
-#define  SBIDHIGH_RC_MASK       0x0000000f /* Revision Code */
-#define  SBIDHIGH_CC_MASK       0x0000fff0 /* Core Code */
-#define  SBIDHIGH_CC_SHIFT      4
-#define  SBIDHIGH_VC_MASK       0xffff0000 /* Vendor Code */
-#define  SBIDHIGH_VC_SHIFT      16
-
-/* SSB PCI config space registers.  */
-#define SSB_PMCSR               0x44
-#define  SSB_PE                 0x100
-#define SSB_BAR0_WIN            0x80
-#define SSB_BAR1_WIN            0x84
-#define SSB_SPROM_CONTROL       0x88
-#define SSB_BAR1_CONTROL        0x8c
-
-/* SSB core and host control registers.  */
-#define SSB_CONTROL             0x0000UL
-#define SSB_ARBCONTROL          0x0010UL
-#define SSB_ISTAT               0x0020UL
-#define SSB_IMASK               0x0024UL
-#define SSB_MBOX                0x0028UL
-#define SSB_BCAST_ADDR          0x0050UL
-#define SSB_BCAST_DATA          0x0054UL
-#define SSB_PCI_TRANS_0         0x0100UL
-#define SSB_PCI_TRANS_1         0x0104UL
-#define SSB_PCI_TRANS_2         0x0108UL
-#define SSB_SPROM               0x0800UL
-
-#define SSB_PCI_MEM             0x00000000
-#define SSB_PCI_IO              0x00000001
-#define SSB_PCI_CFG0            0x00000002
-#define SSB_PCI_CFG1            0x00000003
-#define SSB_PCI_PREF            0x00000004
-#define SSB_PCI_BURST           0x00000008
-#define SSB_PCI_MASK0           0xfc000000
-#define SSB_PCI_MASK1           0xfc000000
-#define SSB_PCI_MASK2           0xc0000000
+#define br32(bp, REG)   ssb_read32((bp)->sdev, (REG))
+#define bw32(bp, REG, VAL)      ssb_write32((bp)->sdev, (REG), (VAL))
+#define atoi(str) simple_strtoul(((str != NULL) ? str : ""), NULL, 0)
 
 /* 4400 PHY registers */
 #define B44_MII_AUXCTRL         24      /* Auxiliary Control */
@@ -346 +281 @@
 
 struct ring_info {
         struct sk_buff          *skb;
-        DECLARE_PCI_UNMAP_ADDR(mapping);
+        dma_addr_t      mapping;
 };
 
 #define B44_MCAST_TABLE_SIZE    32
+#define B44_PHY_ADDR_NO_PHY     30
+#define B44_MDC_RATIO           5000000
 
 #define B44_STAT_REG_DECLARE            \
         _B44(tx_good_octets)            \
@@ -425 +362 @@
 
         u32                     dma_offset;
         u32                     flags;
-#define B44_FLAG_B0_ANDLATER    0x00000001
+#define B44_FLAG_INIT_COMPLETE  0x00000001
 #define B44_FLAG_BUGGY_TXPTR    0x00000002
 #define B44_FLAG_REORDER_BUG    0x00000004
+#define B44_FLAG_B0_ANDLATER    0x00000008
 #define B44_FLAG_PAUSE_AUTO     0x00008000
 #define B44_FLAG_FULL_DUPLEX    0x00010000
 #define B44_FLAG_100_BASE_T     0x00020000
@@ -452 +390 @@
         struct net_device_stats stats;
         struct b44_hw_stats     hw_stats;
 
-        void __iomem            *regs;
-        struct pci_dev          *pdev;
+        struct ssb_device       *sdev;
         struct net_device       *dev;
 
         dma_addr_t              rx_ring_dma, tx_ring_dma;

drivers/ssb/Kconfig

@@ +1 @@
+menu "Sonics Silicon Backplane"
+
+config SSB
+        tristate "Sonics Silicon Backplane support"
+        depends on PCI
+        help
+          Support for the Sonics Silicon Backplane bus
+
+          The module will be called ssb
+
+          If unsure, say m
+
+config SSB_SILENT
+        bool "No SSB kernel messages"
+        depends on SSB
+        help
+          This option turns off all Sonics Silicon Backplane printks.
+          Note that you won't be able to identify problems, once
+          messages are turned off.
+          This might only be desired for production kernels on
+          embedded devices.
+
+          Say n
+
+config SSB_DEBUG
+        bool "SSB debugging"
+        depends on SSB && !SSB_SILENT
+        # TODO: Default y for now, but change to n later
+        default y
+        help
+          This turns on additional runtime checks and debugging
+          messages. Turn this on for SSB troubleshooting.
+
+          If unsure, say n
+
+config SSB_SERIAL
+        bool
+        depends on SSB
+        # ChipCommon and ExtIf serial support routines.
+
+config SSB_DRIVER_EXTIF
+        bool "SSB Broadcom EXTIF core driver"
+        help
+          Driver for the Sonics Silicon Backplane attached
+          Broadcom EXTIF core
+
+          If unsure, say n
+
+config SSB_DRIVER_MIPS
+        bool "SSB Broadcom MIPS core driver"
+        depends on SSB
+        select SSB_SERIAL
+        help
+          Driver for the Sonics Silicon Backplane attached
+          Broadcom MIPS core
+
+          If unsure, say n
+
+endmenu

drivers/ssb/Makefile

@@ +1 @@
+ssb-drivers-y                           += driver_chipcommon/
+ssb-drivers-$(CONFIG_SSB_DRIVER_MIPS)   += driver_mips/
+
+obj-y += ssb.o $(ssb-drivers-y)
+
+ssb-objs := core.o pci.o scan.o

drivers/ssb/core.c

@@ +1 @@
+#include "ssb_private.h"
+
+#include <linux/delay.h>
+#include <linux/pci.h>
+#include <linux/ssb.h>
+#include <linux/ssb_regs.h>
+
+
+static LIST_HEAD(attach_queue);
+static LIST_HEAD(buses);
+static int nr_buses;
+static DEFINE_SPINLOCK(buses_lock);
+
+
+static struct ssb_device * ssb_device_get(struct ssb_device *dev)
+{
+        if (dev)
+                get_device(&dev->dev);
+        return dev;
+}
+
+static void ssb_device_put(struct ssb_device *dev)
+{
+        if (dev)
+                put_device(&dev->dev);
+}
+
+static int ssb_device_resume(struct device *dev)
+{//TODO
+        return 0;
+}
+
+static int ssb_device_suspend(struct device *dev, pm_message_t state)
+{//TODO
+        return 0;
+}
+
+static void ssb_device_shutdown(struct device *dev)
+{//TODO
+}
+
+static int ssb_device_remove(struct device *dev)
+{
+        struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
+        struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
+
+        if (ssb_drv && ssb_drv->remove)
+                ssb_drv->remove(ssb_dev);
+        ssb_device_put(ssb_dev);
+
+        return 0;
+}
+
+static int ssb_device_probe(struct device *dev)
+{
+        struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
+        struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
+        int err = 0;
+
+        ssb_device_get(ssb_dev);
+        if (ssb_drv && ssb_drv->probe)
+                err = ssb_drv->probe(ssb_dev, &ssb_dev->id);
+        if (!err)
+                ssb_device_put(ssb_dev);
+
+        return err;
+}
+
+static int ssb_match_devid(const struct ssb_device_id *tabid,
+                           const struct ssb_device_id *devid)
+{
+        if ((tabid->vendor != devid->vendor) &&
+            tabid->vendor != SSB_ANY_VENDOR)
+                return 0;
+        if ((tabid->coreid != devid->coreid) &&
+            tabid->coreid != SSB_ANY_ID)
+                return 0;
+        if ((tabid->revision != devid->revision) &&
+            tabid->revision != SSB_ANY_REV)
+                return 0;
+        return 1;
+}
+
+static int ssb_bus_match(struct device *dev, struct device_driver *drv)
+{
+        struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
+        struct ssb_driver *ssb_drv = drv_to_ssb_drv(drv);
+        const struct ssb_device_id *id;
+
+        for (id = ssb_drv->id_table;
+             id->vendor || id->coreid || id->revision;
+             id++) {
+                if (ssb_match_devid(id, &ssb_dev->id))
+                        return 1; /* found */
+        }
+
+        return 0;
+}
+
+struct bus_type ssb_bustype = {
+        .name           = NULL, /* Intentionally NULL to indicate early boot */
+        .match          = ssb_bus_match,
+        .probe          = ssb_device_probe,
+        .remove         = ssb_device_remove,
+        .shutdown       = ssb_device_shutdown,
+        .suspend        = ssb_device_suspend,
+        .resume         = ssb_device_resume,
+};
+
+#define is_early_boot()         (ssb_bustype.name == NULL)
+
+void ssb_bus_unregister(struct ssb_bus *bus)
+{//FIXME?
+        spin_lock(&buses_lock);
+        list_del(&bus->list);
+        spin_unlock(&buses_lock);
+
+//TODO chipcommon exit
+        /* Free MMIO */
+        bus->mapped_device = NULL;
+        if (bus->bustype == SSB_BUSTYPE_SSB)
+                iounmap(bus->mmio);
+        else
+                pci_iounmap(bus->host_pci, bus->mmio);
+        bus->mmio = NULL;
+}
+EXPORT_SYMBOL_GPL(ssb_bus_unregister);
+
+/* Needs buses_lock locked */
+static int ssb_attach_queued_buses(void)
+{
+        struct ssb_bus *bus, *n;
+        struct ssb_device *dev;
+        int i, err;
+
+ssb_printk("BUSINIT\n");
+        list_for_each_entry_safe(bus, n, &attach_queue, list) {
+                for (i = 0; i < bus->nr_devices; i++) {
+                        dev = &(bus->devices[i]);
+
+                        err = device_register(&dev->dev);
+                        if (err) {
+                                ssb_printk("Could not register %s\n",
+                                           dev->dev.bus_id);
+                        }
+                }
+                list_move_tail(&bus->list, &buses);
+        }
+ssb_printk("BUS init second stage completed\n");
+//FIXME dynamic clock somewhere?
+        return 0;
+}
+
+static int ssb_bus_register(struct ssb_bus *bus,
+                            unsigned long baseaddr)
+{
+        int err;
+
+        ssb_printk("Sonics Silicon Backplane bus found at:\n");
+        if (bus->bustype == SSB_BUSTYPE_PCI)
+                ssb_printk("PCI device %s\n", bus->host_pci->dev.bus_id);
+        else
+                ssb_printk("Address 0x%08lX\n", baseaddr);
+
+        spin_lock(&buses_lock);
+
+        spin_lock_init(&bus->bar_lock);
+        INIT_LIST_HEAD(&bus->list);
+        bus->busnumber = nr_buses;
+
+        /* Powerup the bus */
+        err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
+        if (err)
+                goto out;
+        /* Scan for devices (cores) */
+        err = ssb_bus_scan(bus, baseaddr);
+        if (err)
+                goto err_disable_xtal;
+
+        /* Initialize basic system devices (if available) */
+        ssb_chipcommon_init(&bus->chipco);
+        ssb_mipscore_init(&bus->mipscore);
+        //TODO also register drivers for the basic system stuff later?
+        //     I think the only purpose would be to show them in sysfs.
+
+        /* Queue it for attach */
+        list_add_tail(&bus->list, &attach_queue);
+        if (!is_early_boot()) {
+                /* This is not early boot, so we must attach the bus now */
+                err = ssb_attach_queued_buses();
+                if (err)
+                        goto err_dequeue;
+        }
+
+        nr_buses++;
+out:
+        spin_unlock(&buses_lock);
+
+ssb_printk("busregister %d\n", err);
+        return err;
+err_dequeue:
+        list_del(&bus->list);
+err_disable_xtal:
+        ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
+        goto out;
+}
+
+int ssb_bus_pcibus_register(struct ssb_bus *bus,
+                            struct pci_dev *host_pci)
+{
+        int err;
+
+        bus->bustype = SSB_BUSTYPE_PCI;
+        bus->host_pci = host_pci;
+
+        err = ssb_pci_sprom_get(bus);
+        if (!err)
+                err = ssb_bus_register(bus, 0);
+
+        return err;
+}
+EXPORT_SYMBOL_GPL(ssb_bus_pcibus_register);
+
+int ssb_bus_ssbbus_register(struct ssb_bus *bus,
+                            unsigned long baseaddr,
+                            void (*fill_sprom)(struct ssb_sprom *sprom))
+{
+        int err;
+
+        bus->bustype = SSB_BUSTYPE_SSB;
+        fill_sprom(&bus->sprom);
+        err = ssb_bus_register(bus, baseaddr);
+
+        return err;
+}
+
+static inline
+int do_select_core(struct ssb_bus *bus,
+                   struct ssb_device *dev,
+                   u16 *offset)
+{
+        int err = 0;
+
+        switch (bus->bustype) {
+        case SSB_BUSTYPE_PCI:
+                if (unlikely(dev != bus->mapped_device))
+                        err = ssb_pci_switch_core(bus, dev);
+                break;
+        case SSB_BUSTYPE_SSB:
+                *offset += dev->core_index * SSB_CORE_SIZE;
+                break;
+        }
+
+        return err;
+}
+
+u16 ssb_read16(struct ssb_device *dev, u16 offset)
+{
+        struct ssb_bus *bus = dev->bus;
+
+        if (unlikely(do_select_core(bus, dev, &offset)))
+                return 0xFFFF;
+        return ssb_raw_read16(bus, offset);
+}
+EXPORT_SYMBOL_GPL(ssb_read16);
+
+u32 ssb_read32(struct ssb_device *dev, u16 offset)
+{
+        struct ssb_bus *bus = dev->bus;
+
+        if (unlikely(do_select_core(bus, dev, &offset)))
+                return 0xFFFFFFFF;
+        return ssb_raw_read32(bus, offset);
+}
+EXPORT_SYMBOL_GPL(ssb_read32);
+
+void ssb_write16(struct ssb_device *dev, u16 offset, u16 value)
+{
+        struct ssb_bus *bus = dev->bus;
+
+        if (unlikely(do_select_core(bus, dev, &offset)))
+                return;
+        ssb_raw_write16(bus, offset, value);
+}
+EXPORT_SYMBOL_GPL(ssb_write16);
+
+void ssb_write32(struct ssb_device *dev, u16 offset, u32 value)
+{
+        struct ssb_bus *bus = dev->bus;
+
+        if (unlikely(do_select_core(bus, dev, &offset)))
+                return;
+        ssb_raw_write32(bus, offset, value);
+}
+EXPORT_SYMBOL_GPL(ssb_write32);
+
+int __ssb_driver_register(struct ssb_driver *drv, struct module *owner)
+{
+        drv->drv.name = drv->name;
+        drv->drv.bus = &ssb_bustype;
+        drv->drv.owner = owner;
+
+        return driver_register(&drv->drv);
+}
+EXPORT_SYMBOL_GPL(__ssb_driver_register);
+
+void ssb_driver_unregister(struct ssb_driver *drv)
+{
+        driver_unregister(&drv->drv);
+}
+EXPORT_SYMBOL_GPL(ssb_driver_unregister);
+
+static u32 clkfactor_f6_resolve(u32 v)
+{
+        /* map the magic values */
+        switch (v) {
+        case SSB_CHIPCO_CLK_F6_2:
+                return 2;
+        case SSB_CHIPCO_CLK_F6_3:
+                return 3;
+        case SSB_CHIPCO_CLK_F6_4:
+                return 4;
+        case SSB_CHIPCO_CLK_F6_5:
+                return 5;
+        case SSB_CHIPCO_CLK_F6_6:
+                return 6;
+        case SSB_CHIPCO_CLK_F6_7:
+                return 7;
+        }
+        return 0;
+}
+
+/* Calculate the speed the backplane would run at a given set of clockcontrol values */
+u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m)
+{
+        u32 n1, n2, clock, m1, m2, m3, mc;
+
+        n1 = (n & SSB_CHIPCO_CLK_N1);
+        n2 = ((n & SSB_CHIPCO_CLK_N2) >> SSB_CHIPCO_CLK_N2_SHIFT);
+
+        switch (plltype) {
+        case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
+                if (m & SSB_CHIPCO_CLK_T6_MMASK)
+                        return SSB_CHIPCO_CLK_T6_M0;
+                return SSB_CHIPCO_CLK_T6_M1;
+        case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
+        case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
+        case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
+        case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
+                n1 = clkfactor_f6_resolve(n1);
+                n2 += SSB_CHIPCO_CLK_F5_BIAS;
+                break;
+        case SSB_PLLTYPE_2: /* 48Mhz, 4 dividers */
+                n1 += SSB_CHIPCO_CLK_T2_BIAS;
+                n2 += SSB_CHIPCO_CLK_T2_BIAS;
+                assert((n1 >= 2) && (n1 <= 7));
+                assert((n2 >= 5) && (n2 <= 23));
+                break;
+        case SSB_PLLTYPE_5: /* 25Mhz, 4 dividers */
+                return 100000000;
+        default:
+                assert(0);
+        }
+
+        switch (plltype) {
+        case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
+        case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
+                clock = SSB_CHIPCO_CLK_BASE2 * n1 * n2;
+                break;
+        default:
+                clock = SSB_CHIPCO_CLK_BASE1 * n1 * n2;
+        }
+        if (!clock)
+                return 0;
+
+        m1 = (m & SSB_CHIPCO_CLK_M1);
+        m2 = ((m & SSB_CHIPCO_CLK_M2) >> SSB_CHIPCO_CLK_M2_SHIFT);
+        m3 = ((m & SSB_CHIPCO_CLK_M3) >> SSB_CHIPCO_CLK_M3_SHIFT);
+        mc = ((m & SSB_CHIPCO_CLK_MC) >> SSB_CHIPCO_CLK_MC_SHIFT);
+
+        switch (plltype) {
+        case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
+        case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
+        case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
+        case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
+                m1 = clkfactor_f6_resolve(m1);
+                if ((plltype == SSB_PLLTYPE_1) ||
+                    (plltype == SSB_PLLTYPE_3))
+                        m2 += SSB_CHIPCO_CLK_F5_BIAS;
+                else
+                        m2 = clkfactor_f6_resolve(m2);
+                m3 = clkfactor_f6_resolve(m3);
+
+                switch (mc) {
+                case SSB_CHIPCO_CLK_MC_BYPASS:
+                        return clock;
+                case SSB_CHIPCO_CLK_MC_M1:
+                        return (clock / m1);
+                case SSB_CHIPCO_CLK_MC_M1M2:
+                        return (clock / (m1 * m2));
+                case SSB_CHIPCO_CLK_MC_M1M2M3:
+                        return (clock / (m1 * m2 * m3));
+                case SSB_CHIPCO_CLK_MC_M1M3:
+                        return (clock / (m1 * m3));
+                }
+                return 0;
+        case SSB_PLLTYPE_2:
+                m1 += SSB_CHIPCO_CLK_T2_BIAS;
+                m2 += SSB_CHIPCO_CLK_T2M2_BIAS;
+                m3 += SSB_CHIPCO_CLK_T2_BIAS;
+                assert((m1 >= 2) && (m1 <= 7));
+                assert((m2 >= 3) && (m2 <= 10));
+                assert((m3 >= 2) && (m3 <= 7));
+
+                if (!(mc & SSB_CHIPCO_CLK_T2MC_M1BYP))
+                        clock /= m1;
+                if (!(mc & SSB_CHIPCO_CLK_T2MC_M2BYP))
+                        clock /= m2;
+                if (!(mc & SSB_CHIPCO_CLK_T2MC_M3BYP))
+                        clock /= m3;
+                return clock;
+        default:
+                assert(0);
+        }
+        return 0;
+}
+
+/* Get the current speed the backplane is running at */
+u32 ssb_clockspeed(struct ssb_bus *bus)
+{
+        u32 rate;
+        u32 plltype;
+        u32 clkctl_n, clkctl_m;
+
+        //TODO if EXTIF: PLLTYPE == 1, read n from clockcontrol_n, m from clockcontrol_sb
+
+        if (bus->chipco.dev) {
+                ssb_chipco_get_clockcontrol(&bus->chipco, &plltype,
+                                            &clkctl_n, &clkctl_m);
+        } else
+                return 0;
+
+        if (bus->chip_id == 0x5365) {
+                rate = 100000000;
+        } else {
+                rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m);
+                if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */
+                        rate /= 2;
+        }
+
+        return rate;
+}
+
+int ssb_core_is_enabled(struct ssb_device *dev)
+{
+        u32 val;
+
+        val = ssb_read32(dev, SSB_TMSLOW);
+        val &= SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET | SSB_TMSLOW_REJECT;
+
+        return (val == SSB_TMSLOW_CLOCK);
+}
+EXPORT_SYMBOL(ssb_core_is_enabled);
+
+void ssb_core_enable(struct ssb_device *dev, u32 core_specific_flags)
+{
+        u32 val;
+
+        ssb_core_disable(dev, core_specific_flags);
+        ssb_write32(dev, SSB_TMSLOW,
+                    SSB_TMSLOW_RESET | SSB_TMSLOW_CLOCK |
+                    SSB_TMSLOW_FGC | core_specific_flags);
+        /* flush */
+        ssb_read32(dev, SSB_TMSLOW);
+        udelay(1);
+
+        /* Clear SERR if set. This is a hw bug workaround. */
+        if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_SERR)
+                ssb_write32(dev, SSB_TMSHIGH, 0);
+
+        val = ssb_read32(dev, SSB_IMSTATE);
+        if (val & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) {
+                val &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO);
+                ssb_write32(dev, SSB_IMSTATE, val);
+        }
+
+        ssb_write32(dev, SSB_TMSLOW,
+                    SSB_TMSLOW_CLOCK | SSB_TMSLOW_FGC |
+                    core_specific_flags);
+        /* flush */
+        ssb_read32(dev, SSB_TMSLOW);
+        udelay(1);
+
+        ssb_write32(dev, SSB_TMSLOW, SSB_TMSLOW_CLOCK |
+                    core_specific_flags);
+        /* flush */
+        ssb_read32(dev, SSB_TMSLOW);
+        udelay(1);
+}
+EXPORT_SYMBOL(ssb_core_enable);
+
+static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask,
+                        int timeout, int set)
+{
+        int i;
+        u32 val;
+
+        for (i = 0; i < timeout; i++) {
+                val = ssb_read32(dev, reg);
+                if (set) {
+                        if (val & bitmask)
+                                return 0;
+                } else {
+                        if (!(val & bitmask))
+                                return 0;
+                }
+                udelay(10);
+        }
+        printk(KERN_ERR PFX "Timeout waiting for bitmask %08X on "
+                            "register %04X to %s.\n",
+               bitmask, reg, (set ? "set" : "clear"));
+
+        return -ETIMEDOUT;
+}
+
+void ssb_core_disable(struct ssb_device *dev, u32 core_specific_flags)
+{
+        if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
+                return;
+
+        ssb_write32(dev, SSB_TMSLOW, SSB_TMSLOW_REJECT | SSB_TMSLOW_CLOCK);
+        ssb_wait_bit(dev, SSB_TMSLOW, SSB_TMSLOW_REJECT, 1000, 1);
+        ssb_wait_bit(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
+        ssb_write32(dev, SSB_TMSLOW,
+                    SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
+                    SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET |
+                    core_specific_flags);
+        /* flush */
+        ssb_read32(dev, SSB_TMSLOW);
+        udelay(1);
+
+        ssb_write32(dev, SSB_TMSLOW,
+                    SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET |
+                    core_specific_flags);
+        /* flush */
+        ssb_read32(dev, SSB_TMSLOW);
+        udelay(1);
+}
+EXPORT_SYMBOL(ssb_core_disable);
+
+int __ssb_printk(const char *fmt, ...)
+{
+        va_list args;
+        int res;
+
+        va_start(args, fmt);
+#ifdef CONFIG_CFE
+        if (is_early_boot() && cfe_present()) {
+                res = cfe_vprintk(fmt, args);
+        } else
+#endif
+        {
+                printk(KERN_INFO);
+                res = vprintk(fmt, args);
+        }
+        va_end(args);
+
+        return res;
+}
+
+
+static int ssb_modinit(void)
+{
+        int err;
+
+        ssb_bustype.name = "ssb";
+        err = bus_register(&ssb_bustype);
+        if (err)
+                return err;
+
+        /* Maybe we already registered some buses at early boot.
+         * Check for this and attach them
+         */
+        spin_lock(&buses_lock);
+        err = ssb_attach_queued_buses();
+        spin_unlock(&buses_lock);
+
+        return err;
+}
+subsys_initcall(ssb_modinit);
+
+static void __exit ssb_modexit(void)
+{
+        bus_unregister(&ssb_bustype);
+}
+module_exit(ssb_modexit)

drivers/ssb/driver_chipcommon/Makefile

@@ +1 @@
+obj-y += chipcommon.o

drivers/ssb/driver_chipcommon/chipcommon.c

@@ +1 @@
+#include <linux/ssb.h>
+#include <linux/ssb_regs.h>
+
+#include "../ssb_private.h"
+
+
+static inline u32 chipco_read32(struct ssb_chipcommon *cc,
+                                u16 offset)
+{
+        return ssb_read32(cc->dev, offset);
+}
+
+static inline void chipco_write32(struct ssb_chipcommon *cc,
+                                  u16 offset,
+                                  u32 value)
+{
+        ssb_write32(cc->dev, offset, value);
+}
+
+static void ssb_clock(struct ssb_chipcommon *cc, enum ssb_clkmode mode)
+{
+        struct ssb_device *ccdev = cc->dev;
+        struct ssb_bus *bus;
+        u32 tmp;
+
+        if (!ccdev)
+                return;
+        bus = ccdev->bus;
+        /* chipcommon cores prior to rev6 don't support dynamic clock control */
+        if (ccdev->id.revision < 6)
+                return;
+        /* chipcommon cores rev10 are a whole new ball game */
+        if (ccdev->id.revision >= 10)
+                return;
+        if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
+                return;
+
+        switch (mode) {
+        case SSB_CLKMODE_SLOW:
+                tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
+                tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW;
+                chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
+                break;
+        case SSB_CLKMODE_FAST:
+                ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
+                tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
+                tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
+                tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
+                chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
+                break;
+        case SSB_CLKMODE_DYNAMIC:
+                tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
+                tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
+                tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
+                tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
+                if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) != SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
+                        tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
+                chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
+
+                /* for dynamic control, we have to release our xtal_pu "force on" */
+                if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
+                        ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
+                break;
+        default:
+                assert(0);
+        }
+}
+
+void ssb_chipcommon_init(struct ssb_chipcommon *cc)
+{
+        if (!cc->dev)
+                return; /* We don't have a ChipCommon */
+        ssb_dprintk("Initializing Chipcommon...\n");
+        ssb_clock(cc, SSB_CLKMODE_FAST);
+}
+
+void ssb_chipcommon_exit(struct ssb_chipcommon *cc)
+{
+        //TODO
+}
+
+void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
+                                 u32 *plltype, u32 *n, u32 *m)
+{
+        *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
+        *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
+        switch (*plltype) {
+        case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
+                *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS);
+                break;
+        case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
+                if (cc->dev->bus->chip_id != 0x5365) {
+                        *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2);
+                        break;
+                }
+                /* Fallthough */
+        default:
+                *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB);
+        }
+}
+
+void ssb_chipco_timing_init(struct ssb_chipcommon *cc,
+                            unsigned long ns)
+{
+        struct ssb_device *dev = cc->dev;
+        struct ssb_bus *bus = dev->bus;
+        u32 tmp;
+
+        /* set register for external IO to control LED. */
+        chipco_write32(cc, SSB_CHIPCO_PROG_CFG, 0x11);
+        tmp = ceildiv(10, ns) << SSB_PROG_WCNT_3_SHIFT;         /* Waitcount-3 = 10ns */
+        tmp |= ceildiv(40, ns) << SSB_PROG_WCNT_1_SHIFT;        /* Waitcount-1 = 40ns */
+        tmp |= ceildiv(240, ns);                                /* Waitcount-0 = 240ns */
+        chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp);       /* 0x01020a0c for a 100Mhz clock */
+
+        /* Set timing for the flash */
+        tmp = ceildiv(10, ns) << SSB_FLASH_WCNT_3_SHIFT;        /* Waitcount-3 = 10nS */
+        tmp |= ceildiv(10, ns) << SSB_FLASH_WCNT_1_SHIFT;       /* Waitcount-1 = 10nS */
+        tmp |= ceildiv(120, ns);                                /* Waitcount-0 = 120nS */
+        if ((bus->chip_id == 0x5365) ||
+            (dev->id.revision < 9))
+                chipco_write32(cc, SSB_CHIPCO_FLASH_WAITCNT, tmp);
+        if ((bus->chip_id == 0x5365) ||
+            (dev->id.revision < 9) ||
+            ((bus->chip_id == 0x5350) && (bus->chip_rev == 0)))
+                chipco_write32(cc, SSB_CHIPCO_PCMCIA_MEMWAIT, tmp);
+
+        if (bus->chip_id == 0x5350) {
+                /* Enable EXTIF */
+                tmp = ceildiv(10, ns) << SSB_PROG_WCNT_3_SHIFT;   /* Waitcount-3 = 10ns */
+                tmp |= ceildiv(20, ns) << SSB_PROG_WCNT_2_SHIFT;  /* Waitcount-2 = 20ns */
+                tmp |= ceildiv(100, ns) << SSB_PROG_WCNT_1_SHIFT; /* Waitcount-1 = 100ns */
+                tmp |= ceildiv(120, ns);                          /* Waitcount-0 = 120ns */
+                chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp); /* 0x01020a0c for a 100Mhz clock */
+        }
+}
+
+
+#ifdef CONFIG_SSB_SERIAL
+int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
+                           struct ssb_serial_port *ports)
+{
+        struct ssb_bus *bus = cc->dev->bus;
+        int nr_ports = 0;
+        u32 plltype;
+        unsigned int irq;
+        u32 baud_base, div;
+        u32 i, n;
+
+        plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
+        irq = ssb_mips_irq(cc->dev);
+
+        if (plltype == SSB_PLLTYPE_1) {
+                /* PLL clock */
+                baud_base = ssb_calc_clock_rate(plltype,
+                                                chipco_read32(cc, SSB_CHIPCO_CLOCK_N),
+                                                chipco_read32(cc, SSB_CHIPCO_CLOCK_M2));
+                div = 1;
+        } else {
+                if (cc->dev->id.revision >= 11) {
+                        /* Fixed ALP clock */
+                        baud_base = 20000000;
+                        div = 1;
+                        /* Set the override bit so we don't divide it */
+                        chipco_write32(cc, SSB_CHIPCO_CORECTL,
+                                       SSB_CHIPCO_CORECTL_UARTCLK0);
+                } else if (cc->dev->id.revision >= 3) {
+                        /* Internal backplane clock */
+                        baud_base = ssb_clockspeed(bus);
+                        div = 2; /* Minimum divisor */
+                        chipco_write32(cc, SSB_CHIPCO_CLKDIV,
+                                       (chipco_read32(cc, SSB_CHIPCO_CLKDIV)
+                                        & ~SSB_CHIPCO_CLKDIV_UART) | div);
+                } else {
+                        /* Fixed internal backplane clock */
+                        baud_base = 88000000;
+                        div = 48;
+                }
+
+                /* Clock source depends on strapping if UartClkOverride is unset */
+                if ((cc->dev->id.revision > 0) &&
+                    !(chipco_read32(cc, SSB_CHIPCO_CORECTL) & SSB_CHIPCO_CORECTL_UARTCLK0)) {
+                        if ((cc->capabilities & SSB_CHIPCO_CAP_UARTCLK) ==
+                            SSB_CHIPCO_CAP_UARTCLK_INT) {
+                                /* Internal divided backplane clock */
+                                baud_base /= div;
+                        } else {
+                                /* Assume external clock of 1.8432 MHz */
+                                baud_base = 1843200;
+                        }
+                }
+        }
+
+        /* Determine the registers of the UARTs */
+        n = (cc->capabilities & SSB_CHIPCO_CAP_NRUART);
+        for (i = 0; i < n; i++) {
+                void __iomem *cc_mmio;
+                void __iomem *uart_regs;
+                
+                cc_mmio = cc->dev->bus->mmio + (cc->dev->core_index * SSB_CORE_SIZE);
+                uart_regs = cc_mmio + SSB_CHIPCO_UART0_DATA;
+                /* Offset changed at after rev 0 */
+                if (cc->dev->id.revision == 0)
+                        uart_regs += (i * 8);
+                else
+                        uart_regs += (i * 256);
+
+                nr_ports++;
+                ports[i].regs = uart_regs;
+                ports[i].irq = irq;
+                ports[i].baud_base = baud_base;
+                ports[i].reg_shift = 0;
+        }
+
+        return nr_ports;
+}
+#endif /* CONFIG_SSB_SERIAL */

drivers/ssb/driver_mips/Makefile

@@ +1 @@
+obj-y += mips.o

drivers/ssb/driver_mips/mips.c

@@ +1 @@
+#include <linux/ssb.h>
+
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+#include <linux/serial_reg.h>
+#include <asm/time.h>
+
+#include "../ssb_private.h"
+
+
+static inline u32 mips_read32(struct ssb_mipscore *mcore,
+                              u16 offset)
+{
+        return ssb_read32(mcore->dev, offset);
+}
+
+static inline void mips_write32(struct ssb_mipscore *mcore,
+                                u16 offset,
+                                u32 value)
+{
+        ssb_write32(mcore->dev, offset, value);
+}
+
+static const u32 ipsflag_irq_mask[] = {
+        0,
+        SSB_IPSFLAG_IRQ1,
+        SSB_IPSFLAG_IRQ2,
+        SSB_IPSFLAG_IRQ3,
+        SSB_IPSFLAG_IRQ4,
+};
+
+static const u32 ipsflag_irq_shift[] = {
+        0,
+        SSB_IPSFLAG_IRQ1_SHIFT,
+        SSB_IPSFLAG_IRQ2_SHIFT,
+        SSB_IPSFLAG_IRQ3_SHIFT,
+        SSB_IPSFLAG_IRQ4_SHIFT,
+};
+
+static inline u32 ssb_irqflag(struct ssb_device *dev)
+{
+        return ssb_read32(dev, SSB_TPSFLAG) & SSB_TPSFLAG_BPFLAG;
+}
+
+/* Get the MIPS IRQ assignment for a specified device.
+ * If unassigned, 0 is returned.
+ */
+unsigned int ssb_mips_irq(struct ssb_device *dev)
+{
+        struct ssb_bus *bus = dev->bus;
+        u32 irqflag;
+        u32 ipsflag;
+        u32 tmp;
+        unsigned int irq;
+
+        irqflag = ssb_irqflag(dev);
+        ipsflag = ssb_read32(bus->mipscore.dev, SSB_IPSFLAG);
+        for (irq = 1; irq <= 4; irq++) {
+                tmp = ((ipsflag & ipsflag_irq_mask[irq]) >> ipsflag_irq_shift[irq]);
+                if (tmp == irqflag)
+                        break;
+        }
+        if (irq == 5)
+                irq = 0;
+
+        return irq;
+}
+
+static void clear_irq(struct ssb_bus *bus, unsigned int irq)
+{
+        struct ssb_device *dev = bus->mipscore.dev;
+
+        /* Clear the IRQ in the MIPScore backplane registers */
+        if (irq == 0) {
+                ssb_write32(dev, SSB_INTVEC, 0);
+        } else {
+                ssb_write32(dev, SSB_IPSFLAG,
+                            ssb_read32(dev, SSB_IPSFLAG) |
+                            ipsflag_irq_mask[irq]);
+        }
+}
+
+static void set_irq(struct ssb_device *dev, unsigned int irq)
+{
+        unsigned int oldirq = ssb_mips_irq(dev);
+        struct ssb_bus *bus = dev->bus;
+        struct ssb_device *mdev = bus->mipscore.dev;
+        u32 irqflag = ssb_irqflag(dev);
+
+        dev->irq = irq + 2;
+        
+        ssb_dprintk("set_irq: core 0x%04x, irq %d => %d\n", dev->id.coreid, oldirq, irq);
+        /* clear the old irq */
+        if (oldirq == 0)
+                ssb_write32(mdev, SSB_INTVEC, (~(1 << irqflag) & ssb_read32(mdev, SSB_INTVEC)));
+        else
+                clear_irq(bus, oldirq);
+
+        /* assign the new one */
+        if (irq == 0)
+                ssb_write32(mdev, SSB_INTVEC, ((1 << irqflag) & ssb_read32(mdev, SSB_INTVEC)));
+        
+        irqflag <<= ipsflag_irq_shift[irq];
+        irqflag |= (ssb_read32(mdev, SSB_IPSFLAG) & ~ipsflag_irq_mask[irq]);
+        ssb_write32(mdev, SSB_IPSFLAG, irqflag);
+}
+
+
+static void ssb_mips_serial_init(struct ssb_mipscore *mcore)
+{
+        struct ssb_bus *bus = mcore->dev->bus;
+
+        //TODO if (EXTIF available
+#if 0
+                extifregs_t *eir = (extifregs_t *) regs;
+                sbconfig_t *sb;
+
+                /* Determine external UART register base */
+                sb = (sbconfig_t *)((ulong) eir + SBCONFIGOFF);
+                base = EXTIF_CFGIF_BASE(sb_base(R_REG(&sb->sbadmatch1)));
+
+                /* Determine IRQ */
+                irq = sb_irq(sbh);
+
+                /* Disable GPIO interrupt initially */
+                W_REG(&eir->gpiointpolarity, 0);
+                W_REG(&eir->gpiointmask, 0);
+
+                /* Search for external UARTs */
+                n = 2;
+                for (i = 0; i < 2; i++) {
+                        regs = (void *) REG_MAP(base + (i * 8), 8);
+                        if (BCMINIT(serial_exists)(regs)) {
+                                /* Set GPIO 1 to be the external UART IRQ */
+                                W_REG(&eir->gpiointmask, 2);
+                                if (add)
+                                        add(regs, irq, 13500000, 0);
+                        }
+                }
+
+                /* Add internal UART if enabled */
+                if (R_REG(&eir->corecontrol) & CC_UE)
+                        if (add)
+                                add((void *) &eir->uartdata, irq, sb_clock(sbh), 2);
+
+#endif
+        if (bus->chipco.dev)
+                mcore->nr_serial_ports = ssb_chipco_serial_init(&bus->chipco, mcore->serial_ports);
+        else
+                mcore->nr_serial_ports = 0;
+}
+
+static void ssb_mips_flash_detect(struct ssb_mipscore *mcore)
+{
+        struct ssb_bus *bus = mcore->dev->bus;
+
+        if (bus->chipco.dev) {
+                mcore->flash_window = 0x1c000000;
+                mcore->flash_window_size = 0x800000;
+        } else {
+                mcore->flash_window = 0x1fc00000;
+                mcore->flash_window_size = 0x400000;
+        }
+}
+
+void ssb_mipscore_init(struct ssb_mipscore *mcore)
+{
+        struct ssb_bus *bus = mcore->dev->bus;
+        struct ssb_device *dev;
+        unsigned long hz, ns;
+        unsigned int irq, i;
+
+        if (!mcore->dev)
+                return; /* We don't have a MIPS core */
+
+        ssb_dprintk("Initializing MIPS core...\n");
+
+        hz = ssb_clockspeed(bus);
+        if (!hz)
+                hz = 100000000;
+        ns = 1000000000 / hz;
+
+//TODO
+#if 0
+        if (have EXTIF) {
+                /* Initialize extif so we can get to the LEDs and external UART */
+                W_REG(&eir->prog_config, CF_EN);
+
+                /* Set timing for the flash */
+                tmp = CEIL(10, ns) << FW_W3_SHIFT;      /* W3 = 10nS */
+                tmp = tmp | (CEIL(40, ns) << FW_W1_SHIFT); /* W1 = 40nS */
+                tmp = tmp | CEIL(120, ns);              /* W0 = 120nS */
+                W_REG(&eir->prog_waitcount, tmp);       /* 0x01020a0c for a 100Mhz clock */
+
+                /* Set programmable interface timing for external uart */
+                tmp = CEIL(10, ns) << FW_W3_SHIFT;      /* W3 = 10nS */
+                tmp = tmp | (CEIL(20, ns) << FW_W2_SHIFT); /* W2 = 20nS */
+                tmp = tmp | (CEIL(100, ns) << FW_W1_SHIFT); /* W1 = 100nS */
+                tmp = tmp | CEIL(120, ns);              /* W0 = 120nS */
+                W_REG(&eir->prog_waitcount, tmp);
+        }
+        else... chipcommon
+#endif
+        if (bus->chipco.dev)
+                ssb_chipco_timing_init(&bus->chipco, ns);
+
+        /* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
+        for (irq = 2, i = 0; i < bus->nr_devices; i++) {
+                dev = &(bus->devices[i]);
+                dev->irq = ssb_mips_irq(dev) + 2;
+                switch(dev->id.coreid) {
+                        case SSB_DEV_USB11_HOST:
+                                /* shouldn't need a separate irq line for non-4710, most of them have a proper
+                                 * external usb controller on the pci */
+                                if ((bus->chip_id == 0x4710) && (irq <= 4)) {
+                                        set_irq(dev, irq++);
+                                        break;
+                                }
+                        case SSB_DEV_PCI:
+                        case SSB_DEV_ETHERNET:
+                        case SSB_DEV_80211:
+                        case SSB_DEV_USB20_HOST:
+                                /* These devices get their own IRQ line if available, the rest goes on IRQ0 */
+                                if (irq <= 4) {
+                                        set_irq(dev, irq++);
+                                        break;
+                                }
+                }
+        }
+
+        ssb_mips_serial_init(mcore);
+        ssb_mips_flash_detect(mcore);
+}

drivers/ssb/pci.c

@@ +1 @@
+/*
+ * Sonics Silicon Backplane PCI-Hostbus related functions.
+ *
+ * Copyright (C) 2005-2006 Michael Buesch <mb@bu3sch.de>
+ * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
+ * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
+ * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
+ * Copyright (C) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
+ *
+ * Derived from the Broadcom 4400 device driver.
+ * Copyright (C) 2002 David S. Miller (davem@redhat.com)
+ * Fixed by Pekka Pietikainen (pp@ee.oulu.fi)
+ * Copyright (C) 2006 Broadcom Corporation.
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+
+#include <linux/ssb.h>
+#include <linux/ssb_regs.h>
+#include <linux/pci.h>
+#include <linux/delay.h>
+
+#include "ssb_private.h"
+
+
+int ssb_pci_switch_coreidx(struct ssb_bus *bus, u8 coreidx)
+{
+        int err;
+        int attempts = 0;
+        u32 cur_core;
+
+        while (1) {
+                err = pci_write_config_dword(bus->host_pci, SSB_BAR0_WIN,
+                                             (coreidx * SSB_CORE_SIZE)
+                                             + SSB_ENUM_BASE);
+                if (err)
+                        goto error;
+                err = pci_read_config_dword(bus->host_pci, SSB_BAR0_WIN,
+                                            &cur_core);
+                if (err)
+                        goto error;
+                cur_core = (cur_core - SSB_ENUM_BASE)
+                           / SSB_CORE_SIZE;
+                if (cur_core == coreidx)
+                        break;
+
+                if (attempts++ > SSB_BAR0_MAX_RETRIES)
+                        goto error;
+                udelay(10);
+        }
+        return 0;
+error:
+        printk(KERN_ERR PFX "Failed to switch to core %u\n", coreidx);
+        return -ENODEV;
+}
+
+int ssb_pci_switch_core(struct ssb_bus *bus,
+                        struct ssb_device *dev)
+{
+        int err;
+        unsigned long flags;
+
+        ssb_dprintk("Switching to core %d\n",
+                    dev->core_index);
+
+        spin_lock_irqsave(&bus->bar_lock, flags);
+        err = ssb_pci_switch_coreidx(bus, dev->core_index);
+        if (!err)
+                bus->mapped_device = dev;
+        spin_unlock_irqrestore(&bus->bar_lock, flags);
+
+        return err;
+}
+
+int ssb_pci_xtal(struct ssb_bus *bus, u32 what, int turn_on)
+{
+        int err;
+        u32 in, out, outenable;
+
+        if (bus->bustype != SSB_BUSTYPE_PCI)
+                return 0;
+
+        err = pci_read_config_dword(bus->host_pci, SSB_GPIO_IN, &in);
+        if (err)
+                goto err_pci;
+        err = pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT, &out);
+        if (err)
+                goto err_pci;
+        err = pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT_ENABLE, &outenable);
+        if (err)
+                goto err_pci;
+
+        outenable |= what;
+
+        if (turn_on) {
+                /* Avoid glitching the clock if GPRS is already using it.
+                 * We can't actually read the state of the PLLPD so we infer it
+                 * by the value of XTAL_PU which *is* readable via gpioin.
+                 */
+                if (in & SSB_GPIO_XTAL)
+                        return 0;
+
+                if (what & SSB_GPIO_XTAL) {
+                        /* Turn the crystal on */
+                        out |= SSB_GPIO_XTAL;
+                        if (what & SSB_GPIO_PLL)
+                                out |= SSB_GPIO_PLL;
+                        err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT, out);
+                        if (err)
+                                goto err_pci;
+                        err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT_ENABLE,
+                                                     outenable);
+                        if (err)
+                                goto err_pci;
+                        msleep(1);
+                }
+                if (what & SSB_GPIO_PLL) {
+                        /* Turn the PLL on */
+                        out &= ~SSB_GPIO_PLL;
+                        err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT, out);
+                        if (err)
+                                goto err_pci;
+                        msleep(2);
+                }
+        } else {
+                if (what & SSB_GPIO_XTAL) {
+                        /* Turn the crystal off */
+                        out &= ~SSB_GPIO_XTAL;
+                }
+                if (what & SSB_GPIO_PLL) {
+                        /* Turn the PLL off */
+                        out |= SSB_GPIO_PLL;
+                }
+                err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT, out);
+                if (err)
+                        goto err_pci;
+                err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT_ENABLE, outenable);
+                if (err)
+                        goto err_pci;
+        }
+
+out:
+        return err;
+
+err_pci:
+        printk(KERN_ERR PFX "Error: pctl_set_clock() could not access PCI config space!\n");
+        err = -EBUSY;
+        goto out;
+}
+
+#define SPOFF(offset)   (((offset) - SSB_SPROM_BASE) / sizeof(u16))
+#define SPEX(_outvar, _offset, _mask, _shift)   \
+        out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
+
+static inline u8 ssb_crc8(u8 crc, u8 data)
+{
+        /* Polynomial:   x^8 + x^7 + x^6 + x^4 + x^2 + 1   */
+        static const u8 t[] = {
+                0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
+                0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
+                0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
+                0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
+                0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
+                0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
+                0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
+                0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
+                0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
+                0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
+                0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
+                0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
+                0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
+                0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
+                0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
+                0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
+                0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
+                0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
+                0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
+                0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
+                0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
+                0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
+                0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
+                0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
+                0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
+                0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
+                0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
+                0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
+                0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
+                0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
+                0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
+                0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F,
+        };
+        return t[crc ^ data];
+}
+
+static u8 ssb_sprom_crc(const u16 *sprom)
+{
+        int word;
+        u8 crc = 0xFF;
+
+        for (word = 0; word < SSB_SPROMSIZE_WORDS - 1; word++) {
+                crc = ssb_crc8(crc, sprom[word] & 0x00FF);
+                crc = ssb_crc8(crc, (sprom[word] & 0xFF00) >> 8);
+        }
+        crc = ssb_crc8(crc, sprom[SPOFF(SSB_SPROM_REVISION)] & 0x00FF);
+        crc ^= 0xFF;
+
+        return crc;
+}
+
+static int sprom_check_crc(const u16 *sprom)
+{
+        u8 crc;
+        u8 expected_crc;
+        u16 tmp;
+
+        crc = ssb_sprom_crc(sprom);
+        tmp = sprom[SPOFF(SSB_SPROM_REVISION)] & SSB_SPROM_REVISION_CRC;
+        expected_crc = tmp >> SSB_SPROM_REVISION_CRC_SHIFT;
+        if (crc != expected_crc)
+                return -EPROTO;
+
+        return 0;
+}
+
+static void sprom_do_read(struct ssb_bus *bus, u16 *sprom)
+{
+        int i;
+
+        for (i = 0; i < SSB_SPROMSIZE_WORDS; i++)
+                sprom[i] = ssb_raw_read16(bus, SSB_SPROM_BASE + (i * 2));
+}
+
+static void sprom_extract_r1(struct ssb_sprom_r1 *out, const u16 *in)
+{
+        int i;
+        u16 v;
+
+        SPEX(pci_spid, SSB_SPROM1_SPID, 0xFFFF, 0);
+        SPEX(pci_svid, SSB_SPROM1_SVID, 0xFFFF, 0);
+        SPEX(pci_pid, SSB_SPROM1_PID, 0xFFFF, 0);
+        for (i = 0; i < 3; i++) {
+                v = in[SPOFF(SSB_SPROM1_IL0MAC) + i];
+                *(((u16 *)out->il0mac) + i) = cpu_to_be16(v);
+        }
+        for (i = 0; i < 3; i++) {
+                v = in[SPOFF(SSB_SPROM1_ET0MAC) + i];
+                *(((u16 *)out->et0mac) + i) = cpu_to_be16(v);
+        }
+        for (i = 0; i < 3; i++) {
+                v = in[SPOFF(SSB_SPROM1_ET1MAC) + i];
+                *(((u16 *)out->et1mac) + i) = cpu_to_be16(v);
+        }
+        SPEX(et0phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0A, 0);
+        SPEX(et1phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1A,
+             SSB_SPROM1_ETHPHY_ET1A_SHIFT);
+        SPEX(et0mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0M, 14);
+        SPEX(et1mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1M, 15);
+        SPEX(board_rev, SSB_SPROM1_BINF, SSB_SPROM1_BINF_BREV, 0);
+        SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE,
+             SSB_SPROM1_BINF_CCODE_SHIFT);
+        SPEX(antenna_a, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTA,
+             SSB_SPROM1_BINF_ANTA_SHIFT);
+        SPEX(antenna_bg, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTBG,
+             SSB_SPROM1_BINF_ANTBG_SHIFT);
+        SPEX(pa0b0, SSB_SPROM1_PA0B0, 0xFFFF, 0);
+        SPEX(pa0b1, SSB_SPROM1_PA0B1, 0xFFFF, 0);
+        SPEX(pa0b2, SSB_SPROM1_PA0B2, 0xFFFF, 0);
+        SPEX(pa1b0, SSB_SPROM1_PA1B0, 0xFFFF, 0);
+        SPEX(pa1b1, SSB_SPROM1_PA1B1, 0xFFFF, 0);
+        SPEX(pa1b2, SSB_SPROM1_PA1B2, 0xFFFF, 0);
+        SPEX(gpio0, SSB_SPROM1_GPIOA, SSB_SPROM1_GPIOA_P0, 0);
+        SPEX(gpio1, SSB_SPROM1_GPIOA, SSB_SPROM1_GPIOA_P1,
+             SSB_SPROM1_GPIOA_P1_SHIFT);
+        SPEX(gpio2, SSB_SPROM1_GPIOB, SSB_SPROM1_GPIOB_P2, 0);
+        SPEX(gpio3, SSB_SPROM1_GPIOB, SSB_SPROM1_GPIOB_P3,
+             SSB_SPROM1_GPIOB_P3_SHIFT);
+        SPEX(maxpwr_a, SSB_SPROM1_MAXPWR, SSB_SPROM1_MAXPWR_A, 0);
+        SPEX(maxpwr_bg, SSB_SPROM1_MAXPWR, SSB_SPROM1_MAXPWR_BG,
+             SSB_SPROM1_MAXPWR_BG_SHIFT);
+        SPEX(itssi_a, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_A, 0);
+        SPEX(itssi_bg, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_BG,
+             SSB_SPROM1_ITSSI_BG_SHIFT);
+        SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0);
+        SPEX(antenna_gain_a, SSB_SPROM1_AGAIN, SSB_SPROM1_AGAIN_A, 0);
+        SPEX(antenna_gain_bg, SSB_SPROM1_AGAIN, SSB_SPROM1_AGAIN_BG,
+             SSB_SPROM1_AGAIN_BG_SHIFT);
+        for (i = 0; i < 4; i++) {
+                v = in[SPOFF(SSB_SPROM1_OEM) + i];
+                *(((u16 *)out->oem) + i) = cpu_to_le16(v);
+        }
+}
+
+static void sprom_extract_r2(struct ssb_sprom_r2 *out, const u16 *in)
+{
+        int i;
+        u16 v;
+
+        SPEX(boardflags_hi, SSB_SPROM2_BFLHI,  0xFFFF, 0);
+        SPEX(maxpwr_a_hi, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_HI, 0);
+        SPEX(maxpwr_a_lo, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_LO,
+             SSB_SPROM2_MAXP_A_LO_SHIFT);
+        SPEX(pa1lob0, SSB_SPROM2_PA1LOB0, 0xFFFF, 0);
+        SPEX(pa1lob1, SSB_SPROM2_PA1LOB1, 0xFFFF, 0);
+        SPEX(pa1lob2, SSB_SPROM2_PA1LOB2, 0xFFFF, 0);
+        SPEX(pa1hib0, SSB_SPROM2_PA1HIB0, 0xFFFF, 0);
+        SPEX(pa1hib1, SSB_SPROM2_PA1HIB1, 0xFFFF, 0);
+        SPEX(pa1hib2, SSB_SPROM2_PA1HIB2, 0xFFFF, 0);
+        SPEX(ofdm_pwr_off, SSB_SPROM2_OPO, SSB_SPROM2_OPO_VALUE, 0);
+        for (i = 0; i < 4; i++) {
+                v = in[SPOFF(SSB_SPROM2_CCODE) + i];
+                *(((u16 *)out->country_str) + i) = cpu_to_le16(v);
+        }
+}
+
+static void sprom_extract_r3(struct ssb_sprom_r3 *out, const u16 *in)
+{
+        out->ofdmapo  = (in[SPOFF(SSB_SPROM3_OFDMAPO) + 0] & 0xFF00) >> 8;
+        out->ofdmapo |= (in[SPOFF(SSB_SPROM3_OFDMAPO) + 0] & 0x00FF) << 8;
+        out->ofdmapo <<= 16;
+        out->ofdmapo |= (in[SPOFF(SSB_SPROM3_OFDMAPO) + 1] & 0xFF00) >> 8;
+        out->ofdmapo |= (in[SPOFF(SSB_SPROM3_OFDMAPO) + 1] & 0x00FF) << 8;
+
+        out->ofdmalpo  = (in[SPOFF(SSB_SPROM3_OFDMALPO) + 0] & 0xFF00) >> 8;
+        out->ofdmalpo |= (in[SPOFF(SSB_SPROM3_OFDMALPO) + 0] & 0x00FF) << 8;
+        out->ofdmalpo <<= 16;
+        out->ofdmalpo |= (in[SPOFF(SSB_SPROM3_OFDMALPO) + 1] & 0xFF00) >> 8;
+        out->ofdmalpo |= (in[SPOFF(SSB_SPROM3_OFDMALPO) + 1] & 0x00FF) << 8;
+
+        out->ofdmahpo  = (in[SPOFF(SSB_SPROM3_OFDMAHPO) + 0] & 0xFF00) >> 8;
+        out->ofdmahpo |= (in[SPOFF(SSB_SPROM3_OFDMAHPO) + 0] & 0x00FF) << 8;
+        out->ofdmahpo <<= 16;
+        out->ofdmahpo |= (in[SPOFF(SSB_SPROM3_OFDMAHPO) + 1] & 0xFF00) >> 8;
+        out->ofdmahpo |= (in[SPOFF(SSB_SPROM3_OFDMAHPO) + 1] & 0x00FF) << 8;
+
+        SPEX(gpioldc_on_cnt, SSB_SPROM3_GPIOLDC, SSB_SPROM3_GPIOLDC_ON,
+             SSB_SPROM3_GPIOLDC_ON_SHIFT);
+        SPEX(gpioldc_off_cnt, SSB_SPROM3_GPIOLDC, SSB_SPROM3_GPIOLDC_OFF,
+             SSB_SPROM3_GPIOLDC_OFF_SHIFT);
+        SPEX(cckpo_1M, SSB_SPROM3_CCKPO, SSB_SPROM3_CCKPO_1M, 0);
+        SPEX(cckpo_2M, SSB_SPROM3_CCKPO, SSB_SPROM3_CCKPO_2M,
+             SSB_SPROM3_CCKPO_2M_SHIFT);
+        SPEX(cckpo_55M, SSB_SPROM3_CCKPO, SSB_SPROM3_CCKPO_55M,
+             SSB_SPROM3_CCKPO_55M_SHIFT);
+        SPEX(cckpo_11M, SSB_SPROM3_CCKPO, SSB_SPROM3_CCKPO_11M,
+             SSB_SPROM3_CCKPO_11M_SHIFT);
+
+        out->ofdmgpo  = (in[SPOFF(SSB_SPROM3_OFDMGPO) + 0] & 0xFF00) >> 8;
+        out->ofdmgpo |= (in[SPOFF(SSB_SPROM3_OFDMGPO) + 0] & 0x00FF) << 8;
+        out->ofdmgpo <<= 16;
+        out->ofdmgpo |= (in[SPOFF(SSB_SPROM3_OFDMGPO) + 1] & 0xFF00) >> 8;
+        out->ofdmgpo |= (in[SPOFF(SSB_SPROM3_OFDMGPO) + 1] & 0x00FF) << 8;
+}
+
+static int sprom_extract(struct ssb_sprom *out, const u16 *in)
+{
+        memset(out, 0, sizeof(*out));
+
+        SPEX(revision, SSB_SPROM_REVISION, SSB_SPROM_REVISION_REV, 0);
+        SPEX(crc, SSB_SPROM_REVISION, SSB_SPROM_REVISION_CRC,
+             SSB_SPROM_REVISION_CRC_SHIFT);
+
+        if (out->revision == 0)
+                goto err_unsup;
+        if (out->revision >= 1 && out->revision <= 3)
+                sprom_extract_r1(&out->r1, in);
+        if (out->revision >= 2 && out->revision <= 3)
+                sprom_extract_r2(&out->r2, in);
+        if (out->revision == 3)
+                sprom_extract_r3(&out->r3, in);
+        if (out->revision >= 4)
+                goto err_unsup;
+        
+        return 0;
+err_unsup:
+        ssb_printk("ERROR: Unsupported SPROM revision %d\n",
+                   out->revision);
+        return -EOPNOTSUPP;
+}
+
+int ssb_pci_sprom_get(struct ssb_bus *bus)
+{
+        int err = -ENOMEM;
+        u16 *buf;
+
+        assert(bus->bustype == SSB_BUSTYPE_PCI);
+
+        buf = kcalloc(SSB_SPROMSIZE_WORDS, sizeof(u16), GFP_KERNEL);
+        if (!buf)
+                goto out;
+        sprom_do_read(bus, buf);
+        err = sprom_check_crc(buf);
+        if (err)
+                ssb_printk("WARNING: Invalid SPROM CRC (corrupt SPROM)\n");
+        err = sprom_extract(&bus->sprom, buf);
+
+        kfree(buf);
+out:
+        return err;
+}

drivers/ssb/scan.c

@@ +1 @@
+#include <linux/ssb.h>
+#include <linux/ssb_regs.h>
+#include <linux/pci.h>
+#include <asm/io.h>
+
+#include "ssb_private.h"
+
+
+static const char * ssb_core_name(u16 coreid)
+{
+        switch (coreid) {
+        case SSB_DEV_CHIPCOMMON:
+                return "ChipCommon";
+        case SSB_DEV_ILINE20:
+                return "ILine 20";
+        case SSB_DEV_SDRAM:
+                return "SDRAM";
+        case SSB_DEV_PCI:
+                return "PCI";
+        case SSB_DEV_MIPS:
+                return "MIPS";
+        case SSB_DEV_ETHERNET:
+                return "Fast Ethernet";
+        case SSB_DEV_V90:
+                return "V90";
+        case SSB_DEV_USB11_HOSTDEV:
+                return "USB 1.1 Hostdev";
+        case SSB_DEV_ADSL:
+                return "ADSL";
+        case SSB_DEV_ILINE100:
+                return "ILine 100";
+        case SSB_DEV_IPSEC:
+                return "IPSEC";
+        case SSB_DEV_PCMCIA:
+                return "PCMCIA";
+        case SSB_DEV_INTERNAL_MEM:
+                return "Internal Memory";
+        case SSB_DEV_MEMC_SDRAM:
+                return "MEMC SDRAM";
+        case SSB_DEV_EXTIF:
+                return "EXTIF";
+        case SSB_DEV_80211:
+                return "IEEE 802.11";
+        case SSB_DEV_MIPS_3302:
+                return "MIPS 3302";
+        case SSB_DEV_USB11_HOST:
+                return "USB 1.1 Host";
+        case SSB_DEV_USB11_DEV:
+                return "USB 1.1 Device";
+        case SSB_DEV_USB20_HOST:
+                return "USB 2.0 Host";
+        case SSB_DEV_USB20_DEV:
+                return "USB 2.0 Device";
+        case SSB_DEV_SDIO_HOST:
+                return "SDIO Host";
+        case SSB_DEV_ROBOSWITCH:
+                return "Roboswitch";
+        case SSB_DEV_PARA_ATA:
+                return "PATA";
+        case SSB_DEV_SATA_XORDMA:
+                return "SATA XOR-DMA";
+        case SSB_DEV_ETHERNET_GBIT:
+                return "GBit Ethernet";
+        case SSB_DEV_PCIE:
+                return "PCI-E";
+        case SSB_DEV_MIMO_PHY:
+                return "MIMO PHY";
+        case SSB_DEV_SRAM_CTRLR:
+                return "SRAM Controller";
+        case SSB_DEV_MINI_MACPHY:
+                return "Mini MACPHY";
+        case SSB_DEV_ARM_1176:
+                return "ARM 1176";
+        case SSB_DEV_ARM_7TDMI:
+                return "ARM 7TDMI";
+        }
+        return "Unknown CoreID";
+}
+
+static u16 pcidev_to_chipid(struct pci_dev *pci_dev)
+{
+        u16 chipid_fallback = 0;
+
+        switch (pci_dev->device) {
+        case 0x4301:
+                chipid_fallback = 0x4301;
+                break;
+        case 0x4305 ... 0x4307:
+                chipid_fallback = 0x4307;
+                break;
+        case 0x4402 ... 0x4403:
+                chipid_fallback = 0x4402;
+                break;
+        case 0x4610 ... 0x4615:
+                chipid_fallback = 0x4610;
+                break;
+        case 0x4710 ... 0x4715:
+                chipid_fallback = 0x4710;
+                break;
+        case 0x4320 ... 0x4325:
+                chipid_fallback = 0x4309;
+                break;
+        default:
+                ssb_printk("PCI-ID not in fallback list\n");
+        }
+
+        return chipid_fallback;
+}
+
+static u8 chipid_to_nrcores(u16 chipid)
+{
+        switch (chipid) {
+        case 0x5365:
+                return 7;
+        case 0x4306:
+                return 6;
+        case 0x4310:
+                return 8;
+        case 0x4307:
+        case 0x4301:
+                return 5;
+        case 0x4402:
+                return 3;
+        case 0x4710:
+        case 0x4610:
+        case 0x4704:
+                return 9;
+        default:
+                ssb_printk("CHIPID not found in nrcores fallback list\n");
+        }
+        return 1;
+}
+
+static u32 scan_read32(struct ssb_bus *bus, u8 current_coreidx,
+                       u16 offset)
+{
+        if (bus->bustype == SSB_BUSTYPE_SSB)
+                offset += current_coreidx * SSB_CORE_SIZE;
+        return ssb_raw_read32(bus, offset);
+}
+
+static int scan_switchcore(struct ssb_bus *bus, u8 coreidx)
+{
+        switch (bus->bustype) {
+        case SSB_BUSTYPE_SSB:
+                break;
+        case SSB_BUSTYPE_PCI:
+                return ssb_pci_switch_coreidx(bus, coreidx);
+        default:
+                assert(0);
+        }
+        return 0;
+}
+
+int ssb_bus_scan(struct ssb_bus *bus,
+                 unsigned long baseaddr)
+{
+        int err = -ENOMEM;
+        void __iomem *mmio;
+        u32 idhi, cc, rev, tmp;
+        int i;
+        struct ssb_device *dev;
+
+        if (bus->bustype == SSB_BUSTYPE_SSB) {
+                /* Only map the first core for now. */
+                mmio = ioremap(baseaddr, SSB_CORE_SIZE);
+        } else {
+                assert(bus->host_pci);
+                mmio = pci_iomap(bus->host_pci, 0, ~0UL);
+        }
+        if (!mmio)
+                goto out;
+        bus->mmio = mmio;
+
+        err = scan_switchcore(bus, 0); /* Switch to first core */
+        if (err)
+                goto err_unmap;
+
+        idhi = scan_read32(bus, 0, SSB_IDHIGH);
+        cc = (idhi & SSB_IDHIGH_CC) >> SSB_IDHIGH_CC_SHIFT;
+        rev = (idhi & SSB_IDHIGH_RCLO);
+        rev |= (idhi & SSB_IDHIGH_RCHI) >> SSB_IDHIGH_RCHI_SHIFT;
+
+        bus->nr_devices = 0;
+        if (cc == SSB_DEV_CHIPCOMMON) {
+                tmp = scan_read32(bus, 0, SSB_CHIPCO_CHIPID);
+
+                bus->chip_id = (tmp & SSB_CHIPCO_IDMASK);
+                bus->chip_rev = (tmp & SSB_CHIPCO_REVMASK) >>
+                                SSB_CHIPCO_REVSHIFT;
+                bus->chip_package = (tmp & SSB_CHIPCO_PACKMASK) >>
+                                    SSB_CHIPCO_PACKSHIFT;
+                if (rev >= 4) {
+                        bus->nr_devices = (tmp & SSB_CHIPCO_NRCORESMASK) >>
+                                          SSB_CHIPCO_NRCORESSHIFT;
+                }
+                tmp = scan_read32(bus, 0, SSB_CHIPCO_CAP);
+                bus->chipco.capabilities = tmp;
+        } else {
+                if (bus->bustype == SSB_BUSTYPE_SSB) {
+                        bus->chip_id = 0x4710;
+                        bus->chip_rev = 0;
+                        bus->chip_package = 0;
+                } else {
+                        bus->chip_id = pcidev_to_chipid(bus->host_pci);
+                        pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
+                                             &bus->chip_rev);
+                        bus->chip_package = 0;
+                }
+        }
+        if (!bus->nr_devices)
+                bus->nr_devices = chipid_to_nrcores(bus->chip_id);
+        if (bus->nr_devices > ARRAY_SIZE(bus->devices)) {
+                ssb_printk("ERR: More than %d ssb cores found (%d)\n",
+                           SSB_MAX_NR_CORES, bus->nr_devices);
+                goto err_unmap;
+        }
+        if (bus->bustype == SSB_BUSTYPE_SSB) {
+                /* Now that we know the number of cores,
+                 * remap the whole IO space for all cores.
+                 */
+                err = -ENOMEM;
+                iounmap(mmio);
+                mmio = ioremap(baseaddr, SSB_CORE_SIZE * bus->nr_devices);
+                if (!mmio)
+                        goto out;
+                bus->mmio = mmio;
+        }
+
+        /* Fetch basic information about each core/device */
+        for (i = 0; i < bus->nr_devices; i++) {
+                err = scan_switchcore(bus, i);
+                if (err)
+                        goto err_unmap;
+                dev = &(bus->devices[i]);
+
+                idhi = scan_read32(bus, i, SSB_IDHIGH);
+                dev->id.coreid = (idhi & SSB_IDHIGH_CC) >> SSB_IDHIGH_CC_SHIFT;
+                dev->id.revision = (idhi & SSB_IDHIGH_RCLO);
+                dev->id.revision |= (idhi & SSB_IDHIGH_RCHI) >> SSB_IDHIGH_RCHI_SHIFT;
+                dev->id.vendor = (idhi & SSB_IDHIGH_VC) >> SSB_IDHIGH_VC_SHIFT;
+                dev->core_index = i;
+                dev->bus = bus;
+                if ((dev->bus->bustype == SSB_BUSTYPE_PCI) && (bus->host_pci))
+                        dev->irq = bus->host_pci->irq;
+
+                ssb_printk("Core %d found: %s "
+                           "(cc 0x%03X, rev 0x%02X, vendor 0x%04X)\n",
+                           i, ssb_core_name(dev->id.coreid),
+                           dev->id.coreid, dev->id.revision, dev->id.vendor);
+
+                dev->dev.bus = &ssb_bustype;
+                snprintf(dev->dev.bus_id, sizeof(dev->dev.bus_id),
+                         "ssb%02x:%02x", bus->busnumber, i);
+
+                switch (dev->id.coreid) {
+                case SSB_DEV_CHIPCOMMON:
+                        if (bus->chipco.dev) {
+                                ssb_printk("WARNING: Multiple Chipcommon found\n");
+                                break;
+                        }
+                        bus->chipco.dev = dev;
+                        break;
+                case SSB_DEV_MIPS:
+                case SSB_DEV_MIPS_3302:
+                        if (bus->mipscore.dev) {
+                                ssb_printk("WARNING: Multiple MIPS cores found\n");
+                                break;
+                        }
+                        bus->mipscore.dev = dev;
+                default:
+                        break;
+                }
+        }
+        err = 0;
+out:
+        return err;
+err_unmap:
+        if (bus->bustype == SSB_BUSTYPE_SSB)
+                iounmap(mmio);
+        else
+                pci_iounmap(bus->host_pci, mmio);
+        goto out;
+}

drivers/ssb/sprom.c

@@ +1 @@
+ 

drivers/ssb/ssb_private.h

@@ +1 @@
+#ifndef LINUX_SSB_PRIVATE_H_
+#define LINUX_SSB_PRIVATE_H_
+
+#include <linux/ssb.h>
+#include <linux/types.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_CFE
+# include <asm/cfe.h>
+#endif
+
+
+#define PFX     "ssb: "
+
+#ifdef CONFIG_SSB_SILENT
+# define ssb_printk(fmt, x...)  do { /* nothing */ } while (0)
+#else
+/* SSB specific printk. If CFE is available, this can be used in early boot.
+ * But it does not harm otherwise. It just does not print anything.
+ */
+int __ssb_printk(const char *fmt, ...) __attribute__((format(printf, 1, 2)));
+# define ssb_printk(fmt, x...)  __ssb_printk(PFX fmt ,##x)
+#endif /* CONFIG_SSB_SILENT */
+
+/* dprintk: Debugging printk; vanishes for non-debug compilation */
+#ifdef CONFIG_SSB_DEBUG
+# define ssb_dprintk(fmt, x...) ssb_printk(fmt ,##x)
+#else
+# define ssb_dprintk(fmt, x...) do { /* nothing */ } while (0)
+#endif
+
+/* printkl: Rate limited printk */
+#define ssb_printkl(fmt, x...)  do {            \
+        if (printk_ratelimit())                 \
+                ssb_printk(fmt ,##x);           \
+                                } while (0)
+
+/* dprintkl: Rate limited debugging printk */
+#ifdef CONFIG_SSB_DEBUG
+# define ssb_dprintkl                   ssb_printkl
+#else
+# define ssb_dprintkl(fmt, x...)        do { /* nothing */ } while (0)
+#endif
+
+#define assert(cond)    do {                                            \
+        if (unlikely(!(cond))) {                                        \
+                ssb_dprintk(KERN_ERR PFX "BUG: Assertion failed (%s) "  \
+                            "at: %s:%d:%s()\n",                         \
+                            #cond, __FILE__, __LINE__, __func__);       \
+        }                                                               \
+                       } while (0)
+
+
+extern struct bus_type ssb_bustype;
+
+/* pci.c */
+extern int ssb_pci_switch_core(struct ssb_bus *bus,
+                               struct ssb_device *dev);
+extern int ssb_pci_switch_coreidx(struct ssb_bus *bus,
+                                  u8 coreidx);
+extern int ssb_pci_xtal(struct ssb_bus *bus, u32 what,
+                        int turn_on);
+extern int ssb_pci_sprom_get(struct ssb_bus *bus);
+
+
+/* scan.c */
+extern int ssb_bus_scan(struct ssb_bus *bus,
+                        unsigned long baseaddr);
+
+
+/* core.c */
+extern u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m);
+
+static inline
+u16 ssb_raw_read16(struct ssb_bus *bus, u16 offset)
+{
+        return readw(bus->mmio + offset);
+}
+
+static inline
+u32 ssb_raw_read32(struct ssb_bus *bus, u16 offset)
+{
+        return readl(bus->mmio + offset);
+}
+
+static inline
+void ssb_raw_write16(struct ssb_bus *bus, u16 offset, u16 value)
+{
+        writew(value, bus->mmio + offset);
+}
+
+static inline
+void ssb_raw_write32(struct ssb_bus *bus, u16 offset, u32 value)
+{
+        writel(value, bus->mmio + offset);
+}
+
+
+static inline
+unsigned long ceildiv(unsigned long x, unsigned long y)
+{
+        return ((x + (y - 1)) / y);
+}
+
+
+#endif /* LINUX_SSB_PRIVATE_H_ */

include/asm-mips/asm-offsets.h

@@ +1 @@
+#ifndef __ASM_OFFSETS_H__
+#define __ASM_OFFSETS_H__
+/*
+ * DO NOT MODIFY.
+ *
+ * This file was generated by Kbuild
+ *
+ */
+
+/* MIPS pt_regs offsets. */
+#define PT_R0     24    
+#define PT_R1     28    
+#define PT_R2     32    
+#define PT_R3     36    
+#define PT_R4     40    
+#define PT_R5     44    
+#define PT_R6     48    
+#define PT_R7     52    
+#define PT_R8     56    
+#define PT_R9     60    
+#define PT_R10    64    
+#define PT_R11    68    
+#define PT_R12    72    
+#define PT_R13    76    
+#define PT_R14    80    
+#define PT_R15    84    
+#define PT_R16    88    
+#define PT_R17    92    
+#define PT_R18    96    
+#define PT_R19    100   
+#define PT_R20    104   
+#define PT_R21    108   
+#define PT_R22    112   
+#define PT_R23    116   
+#define PT_R24    120   
+#define PT_R25    124   
+#define PT_R26    128   
+#define PT_R27    132   
+#define PT_R28    136   
+#define PT_R29    140   
+#define PT_R30    144   
+#define PT_R31    148   
+#define PT_LO     160   
+#define PT_HI     156   
+#define PT_EPC    172   
+#define PT_BVADDR 164   
+#define PT_STATUS 152   
+#define PT_CAUSE  168   
+#define PT_SIZE   176   
+
+/* MIPS task_struct offsets. */
+#define TASK_STATE         0    
+#define TASK_THREAD_INFO   4    
+#define TASK_FLAGS         12   
+#define TASK_MM            132  
+#define TASK_PID           168  
+#define TASK_STRUCT_SIZE   1048 
+
+/* MIPS thread_info offsets. */
+#define TI_TASK            0    
+#define TI_EXEC_DOMAIN     4    
+#define TI_FLAGS           8    
+#define TI_TP_VALUE        12   
+#define TI_CPU             16   
+#define TI_PRE_COUNT       20   
+#define TI_ADDR_LIMIT      24   
+#define TI_RESTART_BLOCK   28   
+#define TI_REGS            48   
+#define _THREAD_SIZE_ORDER 0x1  
+#define _THREAD_SIZE       0x2000       
+#define _THREAD_MASK       0x1fff       
+
+/* MIPS specific thread_struct offsets. */
+#define THREAD_REG16   432      
+#define THREAD_REG17   436      
+#define THREAD_REG18   440      
+#define THREAD_REG19   444      
+#define THREAD_REG20   448      
+#define THREAD_REG21   452      
+#define THREAD_REG22   456      
+#define THREAD_REG23   460      
+#define THREAD_REG29   464      
+#define THREAD_REG30   468      
+#define THREAD_REG31   472      
+#define THREAD_STATUS  476      
+#define THREAD_FPU     480      
+#define THREAD_BVADDR  772      
+#define THREAD_BUADDR  776      
+#define THREAD_ECODE   780      
+#define THREAD_TRAPNO  784      
+#define THREAD_MFLAGS  788      
+#define THREAD_TRAMP   792      
+#define THREAD_OLDCTX  796      
+
+#define THREAD_FPR0    480      
+#define THREAD_FPR1    488      
+#define THREAD_FPR2    496      
+#define THREAD_FPR3    504      
+#define THREAD_FPR4    512      
+#define THREAD_FPR5    520      
+#define THREAD_FPR6    528      
+#define THREAD_FPR7    536      
+#define THREAD_FPR8    544      
+#define THREAD_FPR9    552      
+#define THREAD_FPR10   560      
+#define THREAD_FPR11   568      
+#define THREAD_FPR12   576      
+#define THREAD_FPR13   584      
+#define THREAD_FPR14   592      
+#define THREAD_FPR15   600      
+#define THREAD_FPR16   608      
+#define THREAD_FPR17   616      
+#define THREAD_FPR18   624      
+#define THREAD_FPR19   632      
+#define THREAD_FPR20   640      
+#define THREAD_FPR21   648      
+#define THREAD_FPR22   656      
+#define THREAD_FPR23   664      
+#define THREAD_FPR24   672      
+#define THREAD_FPR25   680      
+#define THREAD_FPR26   688      
+#define THREAD_FPR27   696      
+#define THREAD_FPR28   704      
+#define THREAD_FPR29   712      
+#define THREAD_FPR30   720      
+#define THREAD_FPR31   728      
+#define THREAD_FCR31   736      
+
+/* Linux sigcontext offsets. */
+#define SC_REGS       16        
+#define SC_FPREGS     272       
+#define SC_MDHI       552       
+#define SC_MDLO       560       
+#define SC_PC         8 
+#define SC_STATUS     4 
+#define SC_FPC_CSR    532       
+#define SC_FPC_EIR    536       
+#define SC_HI1        568       
+#define SC_LO1        572       
+#define SC_HI2        576       
+#define SC_LO2        580       
+#define SC_HI3        584       
+#define SC_LO3        588       
+
+/* Linux signal numbers. */
+#define _SIGHUP     0x1 
+#define _SIGINT     0x2 
+#define _SIGQUIT    0x3 
+#define _SIGILL     0x4 
+#define _SIGTRAP    0x5 
+#define _SIGIOT     0x6 
+#define _SIGABRT    0x6 
+#define _SIGEMT     0x7 
+#define _SIGFPE     0x8 
+#define _SIGKILL    0x9 
+#define _SIGBUS     0xa 
+#define _SIGSEGV    0xb 
+#define _SIGSYS     0xc 
+#define _SIGPIPE    0xd 
+#define _SIGALRM    0xe 
+#define _SIGTERM    0xf 
+#define _SIGUSR1    0x10        
+#define _SIGUSR2    0x11        
+#define _SIGCHLD    0x12        
+#define _SIGPWR     0x13        
+#define _SIGWINCH   0x14        
+#define _SIGURG     0x15        
+#define _SIGIO      0x16        
+#define _SIGSTOP    0x17        
+#define _SIGTSTP    0x18        
+#define _SIGCONT    0x19        
+#define _SIGTTIN    0x1a        
+#define _SIGTTOU    0x1b        
+#define _SIGVTALRM  0x1c        
+#define _SIGPROF    0x1d        
+#define _SIGXCPU    0x1e        
+#define _SIGXFSZ    0x1f        
+
+/* Linux irq_cpustat_t offsets. */
+#define IC_SOFTIRQ_PENDING 0    
+#define IC_IRQ_CPUSTAT_T   32   
+
+/* Size of struct page  */
+#define STRUCT_PAGE_SIZE   32   
+
+/* Linux mm_struct offsets. */
+#define MM_USERS      40        
+#define MM_PGD        36        
+#define MM_CONTEXT    348       
+
+#define _PAGE_SIZE     0x1000   
+#define _PAGE_SHIFT    0xc      
+
+#define _PGD_T_SIZE    0x4      
+#define _PMD_T_SIZE    0x4      
+#define _PTE_T_SIZE    0x4      
+
+#define _PGD_T_LOG2    $2       
+#define _PMD_T_LOG2    $2       
+#define _PTE_T_LOG2    $2       
+
+#define _PMD_SHIFT     0x16     
+#define _PGDIR_SHIFT   0x16     
+
+#define _PGD_ORDER     0x0      
+#define _PMD_ORDER     0x1      
+#define _PTE_ORDER     0x0      
+
+#define _PTRS_PER_PGD  0x400    
+#define _PTRS_PER_PMD  0x1      
+#define _PTRS_PER_PTE  0x400    
+
+
+#endif

include/asm-mips/bootinfo.h

@@ -212 +212 @@
 #define MACH_GROUP_NEC_EMMA2RH 25       /* NEC EMMA2RH (was 23)         */
 #define  MACH_NEC_MARKEINS      0       /* NEC EMMA2RH Mark-eins        */
 
+/*
+ * Valid machtype for group Broadcom
+ */
+#define MACH_GROUP_BRCM         23      /* Broadcom                     */
+#define MACH_BCM47XX            1       /* Broadcom BCM47xx             */
+
 #define CL_SIZE                 COMMAND_LINE_SIZE
 
 const char *get_system_type(void);

include/asm-mips/cfe.h

@@ +1 @@
+/*
+ * Broadcom Common Firmware Environment (CFE) support
+ *
+ * Copyright 2000, 2001, 2002
+ * Broadcom Corporation. All rights reserved.
+ *
+ * Copyright (C) 2006 Michael Buesch
+ *
+ * Original Authors:  Mitch Lichtenberg, Chris Demetriou
+ *
+ * This software is furnished under license and may be used and copied only
+ * in accordance with the following terms and conditions.  Subject to these
+ * conditions, you may download, copy, install, use, modify and distribute
+ * modified or unmodified copies of this software in source and/or binary
+ * form. No title or ownership is transferred hereby.
+ *
+ * 1) Any source code used, modified or distributed must reproduce and
+ *    retain this copyright notice and list of conditions as they appear in
+ *    the source file.
+ *
+ * 2) No right is granted to use any trade name, trademark, or logo of
+ *    Broadcom Corporation.  The "Broadcom Corporation" name may not be
+ *    used to endorse or promote products derived from this software
+ *    without the prior written permission of Broadcom Corporation.
+ *
+ * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED
+ *    WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF
+ *    MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR
+ *    NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE
+ *    FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE
+ *    LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ *    BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ *    WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ *    OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LINUX_CFE_API_H_
+#define LINUX_CFE_API_H_
+
+#include <linux/types.h>
+
+
+#define CFE_MI_RESERVED         0               /* memory is reserved, do not use */
+#define CFE_MI_AVAILABLE        1               /* memory is available */
+
+#define CFE_FLG_WARMSTART       0x00000001
+#define CFE_FLG_FULL_ARENA      0x00000001
+#define CFE_FLG_ENV_PERMANENT   0x00000001
+
+#define CFE_CPU_CMD_START       1
+#define CFE_CPU_CMD_STOP        0
+
+#define CFE_STDHANDLE_CONSOLE   0
+
+#define CFE_DEV_NETWORK         1
+#define CFE_DEV_DISK            2
+#define CFE_DEV_FLASH           3
+#define CFE_DEV_SERIAL          4
+#define CFE_DEV_CPU             5
+#define CFE_DEV_NVRAM           6
+#define CFE_DEV_CLOCK           7
+#define CFE_DEV_OTHER           8
+#define CFE_DEV_MASK            0x0F
+
+#define CFE_CACHE_FLUSH_D       1
+#define CFE_CACHE_INVAL_I       2
+#define CFE_CACHE_INVAL_D       4
+#define CFE_CACHE_INVAL_L2      8
+
+#define CFE_FWI_64BIT           0x00000001
+#define CFE_FWI_32BIT           0x00000002
+#define CFE_FWI_RELOC           0x00000004
+#define CFE_FWI_UNCACHED        0x00000008
+#define CFE_FWI_MULTICPU        0x00000010
+#define CFE_FWI_FUNCSIM         0x00000020
+#define CFE_FWI_RTLSIM          0x00000040
+
+struct cfe_fwinfo {
+        s64 version;            /* major, minor, eco version */
+        s64 totalmem;           /* total installed mem */
+        s64 flags;              /* various flags */
+        s64 boardid;            /* board ID */
+        s64 bootarea_va;        /* VA of boot area */
+        s64 bootarea_pa;        /* PA of boot area */
+        s64 bootarea_size;      /* size of boot area */
+};
+
+
+/* The public CFE API */
+
+int cfe_present(void);  /* Check if we booted from CFE. Returns bool */
+
+int cfe_getticks(s64 *ticks);
+int cfe_close(int handle);
+int cfe_cpu_start(int cpu, void (*fn)(void), long sp, long gp, long a1);
+int cfe_cpu_stop(int cpu);
+int cfe_enumenv(int idx, char *name, int namelen, char *val, int vallen);
+int cfe_enumdev(int idx, char *name, int namelen);
+int cfe_enummem(int idx, int flags, u64 *start, u64 *length,
+                u64 *type);
+int cfe_exit(int warm, int status);
+int cfe_flushcache(int flags);
+int cfe_getdevinfo(char *name);
+int cfe_getenv(char *name, char *dest, int destlen);
+int cfe_getfwinfo(struct cfe_fwinfo *info);
+int cfe_getstdhandle(int handletype);
+int cfe_inpstat(int handle);
+int cfe_ioctl(int handle, unsigned int ioctlnum, unsigned char *buffer,
+              int length, int *retlen, u64 offset);
+int cfe_open(char *name);
+int cfe_read(int handle, unsigned char *buffer, int length);
+int cfe_readblk(int handle, s64 offset, unsigned char *buffer, int length);
+int cfe_setenv(char *name, char *val);
+int cfe_write(int handle, unsigned char *buffer, int length);
+int cfe_writeblk(int handle, s64 offset, unsigned char *buffer,
+                 int length);
+
+
+/* High level API */
+
+/* Print some information to CFE's console (most likely serial line) */
+int cfe_printk(const char *fmt, ...) __attribute__((format(printf, 1, 2)));
+int cfe_vprintk(const char *fmt, va_list args);
+
+
+
+/* Error codes returned by the low API functions */
+
+#define CFE_ISERR(errcode)      (errcode < 0)
+
+#define CFE_OK                   0
+#define CFE_ERR                 -1      /* generic error */
+#define CFE_ERR_INV_COMMAND     -2
+#define CFE_ERR_EOF             -3
+#define CFE_ERR_IOERR           -4
+#define CFE_ERR_NOMEM           -5
+#define CFE_ERR_DEVNOTFOUND     -6
+#define CFE_ERR_DEVOPEN         -7
+#define CFE_ERR_INV_PARAM       -8
+#define CFE_ERR_ENVNOTFOUND     -9
+#define CFE_ERR_ENVREADONLY     -10
+
+#define CFE_ERR_NOTELF          -11
+#define CFE_ERR_NOT32BIT        -12
+#define CFE_ERR_WRONGENDIAN     -13
+#define CFE_ERR_BADELFVERS      -14
+#define CFE_ERR_NOTMIPS         -15
+#define CFE_ERR_BADELFFMT       -16
+#define CFE_ERR_BADADDR         -17
+
+#define CFE_ERR_FILENOTFOUND    -18
+#define CFE_ERR_UNSUPPORTED     -19
+
+#define CFE_ERR_HOSTUNKNOWN     -20
+
+#define CFE_ERR_TIMEOUT         -21
+
+#define CFE_ERR_PROTOCOLERR     -22
+
+#define CFE_ERR_NETDOWN         -23
+#define CFE_ERR_NONAMESERVER    -24
+
+#define CFE_ERR_NOHANDLES       -25
+#define CFE_ERR_ALREADYBOUND    -26
+
+#define CFE_ERR_CANNOTSET       -27
+#define CFE_ERR_NOMORE          -28
+#define CFE_ERR_BADFILESYS      -29
+#define CFE_ERR_FSNOTAVAIL      -30
+
+#define CFE_ERR_INVBOOTBLOCK    -31
+#define CFE_ERR_WRONGDEVTYPE    -32
+#define CFE_ERR_BBCHECKSUM      -33
+#define CFE_ERR_BOOTPROGCHKSUM  -34
+
+#define CFE_ERR_LDRNOTAVAIL     -35
+
+#define CFE_ERR_NOTREADY        -36
+
+#define CFE_ERR_GETMEM          -37
+#define CFE_ERR_SETMEM          -38
+
+#define CFE_ERR_NOTCONN         -39
+#define CFE_ERR_ADDRINUSE       -40
+
+
+#endif /* LINUX_CFE_API_H_ */

include/asm-mips/cpu.h

@@ -104 +104 @@
 #define PRID_IMP_SR71000        0x0400
 
 /*
+ * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM
+ */
+
+#define PRID_IMP_BCM4710        0x4000
+#define PRID_IMP_BCM3302        0x9000
+
+/*
  * Definitions for 7:0 on legacy processors
  */
 
@@ -200 +207 @@
 #define CPU_SB1A                62
 #define CPU_74K                 63
 #define CPU_R14000              64
-#define CPU_LAST                64
+#define CPU_BCM3302             65
+#define CPU_BCM4710             66
+#define CPU_LAST                66
 
 /*
  * ISA Level encodings

include/asm-mips/mach-bcm947xx/kernel-entry-init.h

@@ +1 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2005 Embedded Alley Solutions, Inc
+ * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
+ * Copyright (C) 2006 Michael Buesch
+ */
+#ifndef __ASM_MACH_GENERIC_KERNEL_ENTRY_H
+#define __ASM_MACH_GENERIC_KERNEL_ENTRY_H
+
+/* Intentionally empty macro, used in head.S. Override in
+ * arch/mips/mach-xxx/kernel-entry-init.h when necessary.
+ */
+        .macro  kernel_entry_setup
+        .endm
+
+/*
+ * Do SMP slave processor setup necessary before we can savely execute C code.
+ */
+        .macro  smp_slave_setup
+        .endm
+
+
+#endif /* __ASM_MACH_GENERIC_KERNEL_ENTRY_H */

include/linux/pci_ids.h

@@ -1953 +1953 @@
 #define PCI_DEVICE_ID_TIGON3_5906M      0x1713
 #define PCI_DEVICE_ID_BCM4401           0x4401
 #define PCI_DEVICE_ID_BCM4401B0         0x4402
+#define PCI_DEVICE_ID_BCM4713           0x4713
 
 #define PCI_VENDOR_ID_TOPIC             0x151f
 #define PCI_DEVICE_ID_TOPIC_TP560       0x0000

include/linux/ssb.h

@@ +1 @@
+#ifndef LINUX_SSB_H_
+#define LINUX_SSB_H_
+#ifdef __KERNEL__
+
+#include <linux/device.h>
+#include <linux/list.h>
+#include <linux/types.h>
+#include <linux/spinlock.h>
+
+#include <linux/ssb_regs.h>
+
+
+struct ssb_bus;
+struct ssb_driver;
+
+
+struct ssb_sprom_r1 {
+        u16 pci_spid;           /* Subsystem Product ID for PCI */
+        u16 pci_svid;           /* Subsystem Vendor ID for PCI */
+        u16 pci_pid;            /* Product ID for PCI */
+        u8 il0mac[6];           /* MAC address for 802.11b/g */
+        u8 et0mac[6];           /* MAC address for Ethernet */
+        u8 et1mac[6];           /* MAC address for 802.11a */
+        u8 et0phyaddr:5;        /* MII address for enet0 */
+        u8 et1phyaddr:5;        /* MII address for enet1 */
+        u8 et0mdcport:1;        /* MDIO for enet0 */
+        u8 et1mdcport:1;        /* MDIO for enet1 */
+        u8 board_rev;           /* Board revision */
+        u8 country_code:4;      /* Country Code */
+        u8 antenna_a:2;         /* Antenna 0/1 available for A-PHY */
+        u8 antenna_bg:2;        /* Antenna 0/1 available for B-PHY and G-PHY */
+        u16 pa0b0;
+        u16 pa0b1;
+        u16 pa0b2;
+        u16 pa1b0;
+        u16 pa1b1;
+        u16 pa1b2;
+        u8 gpio0;               /* GPIO pin 0 */
+        u8 gpio1;               /* GPIO pin 1 */
+        u8 gpio2;               /* GPIO pin 2 */
+        u8 gpio3;               /* GPIO pin 3 */
+        u16 maxpwr_a;           /* A-PHY Power Amplifier Max Power (in dBm Q5.2) */
+        u16 maxpwr_bg;          /* B/G-PHY Power Amplifier Max Power (in dBm Q5.2) */
+        u8 itssi_a;             /* Idle TSSI Target for A-PHY */
+        u8 itssi_bg;            /* Idle TSSI Target for B/G-PHY */
+        u16 boardflags_lo;      /* Boardflags (low 16 bits) */
+        u8 antenna_gain_a;      /* A-PHY Antenna gain (in dBm Q5.2) */
+        u8 antenna_gain_bg;     /* B/G-PHY Antenna gain (in dBm Q5.2) */
+        u8 oem[8];              /* OEM string (rev 1 only) */
+};
+
+struct ssb_sprom_r2 {
+        u16 boardflags_hi;      /* Boardflags (high 16 bits) */
+        u8 maxpwr_a_lo;         /* A-PHY Max Power Low */
+        u8 maxpwr_a_hi;         /* A-PHY Max Power High */
+        u16 pa1lob0;            /* A-PHY PA Low Settings */
+        u16 pa1lob1;            /* A-PHY PA Low Settings */
+        u16 pa1lob2;            /* A-PHY PA Low Settings */
+        u16 pa1hib0;            /* A-PHY PA High Settings */
+        u16 pa1hib1;            /* A-PHY PA High Settings */
+        u16 pa1hib2;            /* A-PHY PA High Settings */
+        u8 ofdm_pwr_off;        /* OFDM Power Offset from CCK Level */
+        u8 country_str[2];      /* Two char Country Code */
+};
+
+struct ssb_sprom_r3 {
+        u32 ofdmapo;            /* A-PHY OFDM Mid Power Offset */
+        u32 ofdmalpo;           /* A-PHY OFDM Low Power Offset */
+        u32 ofdmahpo;           /* A-PHY OFDM High Power Offset */
+        u8 gpioldc_on_cnt;      /* GPIO LED Powersave Duty Cycle ON count */
+        u8 gpioldc_off_cnt;     /* GPIO LED Powersave Duty Cycle OFF count */
+        u8 cckpo_1M:4;          /* CCK Power Offset for Rate 1M */
+        u8 cckpo_2M:4;          /* CCK Power Offset for Rate 2M */
+        u8 cckpo_55M:4;         /* CCK Power Offset for Rate 5.5M */
+        u8 cckpo_11M:4;         /* CCK Power Offset for Rate 11M */
+        u32 ofdmgpo;            /* G-PHY OFDM Power Offset */
+};
+
+struct ssb_sprom_r4 {
+        /* TODO */
+};
+
+struct ssb_sprom {
+        u8 revision;
+        u8 crc;
+        /* The valid r# fields are selected by the "revision".
+         * Revision 3 and lower inherit from lower revisions.
+         */
+        union {
+                struct {
+                        struct ssb_sprom_r1 r1;
+                        struct ssb_sprom_r2 r2;
+                        struct ssb_sprom_r3 r3;
+                };
+                struct ssb_sprom_r4 r4;
+        };
+};
+
+
+/* Core-ID values. */
+#define SSB_DEV_CHIPCOMMON      0x800
+#define SSB_DEV_ILINE20         0x801
+#define SSB_DEV_SDRAM           0x803
+#define SSB_DEV_PCI             0x804
+#define SSB_DEV_MIPS            0x805
+#define SSB_DEV_ETHERNET        0x806
+#define SSB_DEV_V90             0x807
+#define SSB_DEV_USB11_HOSTDEV   0x808
+#define SSB_DEV_ADSL            0x809
+#define SSB_DEV_ILINE100        0x80A
+#define SSB_DEV_IPSEC           0x80B
+#define SSB_DEV_PCMCIA          0x80D
+#define SSB_DEV_INTERNAL_MEM    0x80E
+#define SSB_DEV_MEMC_SDRAM      0x80F
+#define SSB_DEV_EXTIF           0x811
+#define SSB_DEV_80211           0x812
+#define SSB_DEV_MIPS_3302       0x816
+#define SSB_DEV_USB11_HOST      0x817
+#define SSB_DEV_USB11_DEV       0x818
+#define SSB_DEV_USB20_HOST      0x819
+#define SSB_DEV_USB20_DEV       0x81A
+#define SSB_DEV_SDIO_HOST       0x81B
+#define SSB_DEV_ROBOSWITCH      0x81C
+#define SSB_DEV_PARA_ATA        0x81D
+#define SSB_DEV_SATA_XORDMA     0x81E
+#define SSB_DEV_ETHERNET_GBIT   0x81F
+#define SSB_DEV_PCIE            0x820
+#define SSB_DEV_MIMO_PHY        0x821
+#define SSB_DEV_SRAM_CTRLR      0x822
+#define SSB_DEV_MINI_MACPHY     0x823
+#define SSB_DEV_ARM_1176        0x824
+#define SSB_DEV_ARM_7TDMI       0x825
+
+/* Vendor-ID values */
+#define SSB_VENDOR_BROADCOM     0x4243
+
+struct ssb_device_id {
+        u16 vendor;
+        u16 coreid;
+        u8 revision;
+};
+#define SSB_DEVICE(_vendor, _coreid, _revision)  \
+        { .vendor = _vendor, .coreid = _coreid, .revision = _revision, }
+#define SSB_DEVTABLE_END  \
+        { 0, },
+
+#define SSB_ANY_VENDOR          0xFFFF
+#define SSB_ANY_ID              0xFFFF
+#define SSB_ANY_REV             0xFF
+
+
+struct ssb_device {
+        struct device dev;
+        struct ssb_bus *bus;
+        struct ssb_device_id id;
+
+        u8 core_index;
+        u32 dma_routing;        //FIXME assign this! move to bus? Use helper function?
+        unsigned int irq; 
+        void *drvdata;
+};
+#define dev_to_ssb_dev(_dev) container_of(_dev, struct ssb_device, dev)
+
+static inline
+void ssb_set_drvdata(struct ssb_device *dev, void *data)
+{
+        dev->drvdata = data;
+}
+static inline
+void * ssb_get_drvdata(struct ssb_device *dev)
+{
+        return dev->drvdata;
+}
+
+u16 ssb_read16(struct ssb_device *dev, u16 offset);
+u32 ssb_read32(struct ssb_device *dev, u16 offset);
+void ssb_write16(struct ssb_device *dev, u16 offset, u16 value);
+void ssb_write32(struct ssb_device *dev, u16 offset, u32 value);
+
+
+struct ssb_driver {
+        const char *name;
+        const struct ssb_device_id *id_table;
+
+        int (*probe)(struct ssb_device *dev, const struct ssb_device_id *id);
+        void (*remove)(struct ssb_device *dev);
+        int (*suspend)(struct ssb_device *dev, pm_message_t state);
+        int (*resume)(struct ssb_device *dev);
+        void (*shutdown)(struct ssb_device *dev);
+
+        struct device_driver drv;
+};
+#define drv_to_ssb_drv(_drv) container_of(_drv, struct ssb_driver, drv)
+
+extern int __ssb_driver_register(struct ssb_driver *drv, struct module *owner);
+static inline int ssb_driver_register(struct ssb_driver *drv)
+{
+        return __ssb_driver_register(drv, THIS_MODULE);
+}
+extern void ssb_driver_unregister(struct ssb_driver *drv);
+
+
+
+
+enum ssb_bustype {
+        SSB_BUSTYPE_SSB,        /* This SSB bus is the system bus */
+        SSB_BUSTYPE_PCI,        /* SSB is connected to PCI bus */
+        //FIXME JTAG?
+};
+
+#include <linux/ssb_driver_chipcommon.h>
+#include <linux/ssb_driver_mips.h>
+#include <linux/ssb_driver_extif.h>
+
+struct ssb_bus {
+        enum ssb_bustype bustype;
+        struct pci_dev *host_pci;
+        void __iomem *mmio;
+
+        u16 chip_id;
+        u16 chip_rev;
+        u8 chip_package;
+        struct ssb_sprom sprom;
+
+        spinlock_t bar_lock;
+        struct ssb_device *mapped_device;
+        int nr_devices;
+        struct ssb_device devices[SSB_MAX_NR_CORES]; /* cores */
+
+        struct ssb_chipcommon chipco;
+        struct ssb_mipscore mipscore;
+
+        int busnumber;
+        struct list_head list;
+};
+
+extern int ssb_bus_ssbbus_register(struct ssb_bus *bus,
+                                   unsigned long baseaddr,
+                                   void (*fill_sprom)(struct ssb_sprom *sprom));
+extern int ssb_bus_pcibus_register(struct ssb_bus *bus,
+                                   struct pci_dev *host_pci);
+extern void ssb_bus_unregister(struct ssb_bus *bus);
+extern u32 ssb_clockspeed(struct ssb_bus *bus);
+
+int ssb_core_is_enabled(struct ssb_device *dev);
+void ssb_core_enable(struct ssb_device *dev, u32 core_specific_flags);
+void ssb_core_disable(struct ssb_device *dev, u32 core_specific_flags);
+
+static inline dma_addr_t ssb_dma_offset(struct ssb_device *dev)
+{
+        switch(dev->bus->bustype) {
+        case SSB_BUSTYPE_SSB:
+                return 0;
+        case SSB_BUSTYPE_PCI:
+                return SSB_PCI_DMA;
+        }
+        return 0;
+}
+
+
+
+#endif /* __KERNEL__ */
+#endif /* LINUX_SSB_H_ */

include/linux/ssb_driver_chipcommon.h

@@ +1 @@
+#ifndef LINUX_SSB_CHIPCO_H_
+#define LINUX_SSB_CHIPCO_H_
+
+/* SonicsSiliconBackplane CHIPCOMMON core hardware definitions
+ *
+ * The chipcommon core provides chip identification, SB control,
+ * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
+ * gpio interface, extbus, and support for serial and parallel flashes.
+ *
+ * Copyright 2005, Broadcom Corporation
+ * Copyright 2006, Michael Buesch <mb@bu3sch.de>
+ *
+ * Licensed under the GPL version 2. See COPYING for details.
+ */
+#ifdef __KERNEL__
+
+/** ChipCommon core registers. **/
+
+#define SSB_CHIPCO_CHIPID               0x0000
+#define  SSB_CHIPCO_IDMASK              0x0000FFFF
+#define  SSB_CHIPCO_REVMASK             0x000F0000
+#define  SSB_CHIPCO_REVSHIFT            16
+#define  SSB_CHIPCO_PACKMASK            0x00F00000
+#define  SSB_CHIPCO_PACKSHIFT           20
+#define  SSB_CHIPCO_NRCORESMASK         0x0F000000
+#define  SSB_CHIPCO_NRCORESSHIFT        24
+#define SSB_CHIPCO_CAP                  0x0004          /* Capabilities */
+#define  SSB_CHIPCO_CAP_NRUART          0x00000003      /* # of UARTs */
+#define  SSB_CHIPCO_CAP_MIPSEB          0x00000004      /* MIPS in BigEndian Mode */
+#define  SSB_CHIPCO_CAP_UARTCLK         0x00000018      /* UART clock select */
+#define   SSB_CHIPCO_CAP_UARTCLK_INT    0x00000008      /* UARTs are driven by internal divided clock */
+#define  SSB_CHIPCO_CAP_UARTGPIO        0x00000020      /* UARTs on GPIO 15-12 */
+#define  SSB_CHIPCO_CAP_EXTBUS          0x000000C0      /* External buses present */
+#define  SSB_CHIPCO_CAP_FLASHT          0x00000700      /* Flash Type */
+#define   SSB_CHIPCO_FLASHT_NONE        0x00000000      /* No flash */
+#define   SSB_CHIPCO_FLASHT_STSER       0x00000100      /* ST serial flash */
+#define   SSB_CHIPCO_FLASHT_ATSER       0x00000200      /* Atmel serial flash */
+#define   SSB_CHIPCO_FLASHT_PARA        0x00000700      /* Parallel flash */
+#define  SSB_CHIPCO_CAP_PLLT            0x00038000      /* PLL Type */
+#define   SSB_PLLTYPE_NONE              0x00000000
+#define   SSB_PLLTYPE_1                 0x00010000      /* 48Mhz base, 3 dividers */
+#define   SSB_PLLTYPE_2                 0x00020000      /* 48Mhz, 4 dividers */
+#define   SSB_PLLTYPE_3                 0x00030000      /* 25Mhz, 2 dividers */
+#define   SSB_PLLTYPE_4                 0x00008000      /* 48Mhz, 4 dividers */
+#define   SSB_PLLTYPE_5                 0x00018000      /* 25Mhz, 4 dividers */
+#define   SSB_PLLTYPE_6                 0x00028000      /* 100/200 or 120/240 only */
+#define   SSB_PLLTYPE_7                 0x00038000      /* 25Mhz, 4 dividers */
+#define  SSB_CHIPCO_CAP_PCTL            0x00040000      /* Power Control */
+#define  SSB_CHIPCO_CAP_OTPS            0x00380000      /* OTP size */
+#define  SSB_CHIPCO_CAP_OTPS_SHIFT      19
+#define  SSB_CHIPCO_CAP_OTPS_BASE       5
+#define  SSB_CHIPCO_CAP_JTAGM           0x00400000      /* JTAG master present */
+#define  SSB_CHIPCO_CAP_BROM            0x00800000      /* Internal boot ROM active */
+#define  SSB_CHIPCO_CAP_64BIT           0x08000000      /* 64-bit Backplane */
+#define SSB_CHIPCO_CORECTL              0x0008
+#define  SSB_CHIPCO_CORECTL_UARTCLK0    0x00000001      /* Drive UART with internal clock */
+#define  SSB_CHIPCO_CORECTL_SE          0x00000002      /* sync clk out enable (corerev >= 3) */
+#define SSB_CHIPCO_BIST                 0x000C
+#define SSB_CHIPCO_OTPS                 0x0010          /* OTP status */
+#define  SSB_CHIPCO_OTPS_PROGFAIL       0x80000000
+#define  SSB_CHIPCO_OTPS_PROTECT        0x00000007
+#define  SSB_CHIPCO_OTPS_HW_PROTECT     0x00000001
+#define  SSB_CHIPCO_OTPS_SW_PROTECT     0x00000002
+#define  SSB_CHIPCO_OTPS_CID_PROTECT    0x00000004
+#define SSB_CHIPCO_OTPC                 0x0014          /* OTP control */
+#define  SSB_CHIPCO_OTPC_RECWAIT        0xFF000000
+#define  SSB_CHIPCO_OTPC_PROGWAIT       0x00FFFF00
+#define  SSB_CHIPCO_OTPC_PRW_SHIFT      8
+#define  SSB_CHIPCO_OTPC_MAXFAIL        0x00000038
+#define  SSB_CHIPCO_OTPC_VSEL           0x00000006
+#define  SSB_CHIPCO_OTPC_SELVL          0x00000001
+#define SSB_CHIPCO_OTPP                 0x0018          /* OTP prog */
+#define  SSB_CHIPCO_OTPP_COL            0x000000FF
+#define  SSB_CHIPCO_OTPP_ROW            0x0000FF00
+#define  SSB_CHIPCO_OTPP_ROW_SHIFT      8
+#define  SSB_CHIPCO_OTPP_READERR        0x10000000
+#define  SSB_CHIPCO_OTPP_VALUE          0x20000000
+#define  SSB_CHIPCO_OTPP_READ           0x40000000
+#define  SSB_CHIPCO_OTPP_START          0x80000000
+#define  SSB_CHIPCO_OTPP_BUSY           0x80000000
+#define SSB_CHIPCO_IRQSTAT              0x0020
+#define SSB_CHIPCO_IRQMASK              0x0024
+#define  SSB_CHIPCO_IRQ_GPIO            0x00000001      /* gpio intr */
+#define  SSB_CHIPCO_IRQ_EXT             0x00000002      /* ro: ext intr pin (corerev >= 3) */
+#define  SSB_CHIPCO_IRQ_WDRESET         0x80000000      /* watchdog reset occurred */
+#define SSB_CHIPCO_CHIPCTL              0x0028          /* Rev >= 11 only */
+#define SSB_CHIPCO_CHIPSTAT             0x002C          /* Rev >= 11 only */
+#define SSB_CHIPCO_JCMD                 0x0030          /* Rev >= 10 only */
+#define  SSB_CHIPCO_JCMD_START          0x80000000
+#define  SSB_CHIPCO_JCMD_BUSY           0x80000000
+#define  SSB_CHIPCO_JCMD_PAUSE          0x40000000
+#define  SSB_CHIPCO_JCMD0_ACC_MASK      0x0000F000
+#define  SSB_CHIPCO_JCMD0_ACC_IRDR      0x00000000
+#define  SSB_CHIPCO_JCMD0_ACC_DR        0x00001000
+#define  SSB_CHIPCO_JCMD0_ACC_IR        0x00002000
+#define  SSB_CHIPCO_JCMD0_ACC_RESET     0x00003000
+#define  SSB_CHIPCO_JCMD0_ACC_IRPDR     0x00004000
+#define  SSB_CHIPCO_JCMD0_ACC_PDR       0x00005000
+#define  SSB_CHIPCO_JCMD0_IRW_MASK      0x00000F00
+#define  SSB_CHIPCO_JCMD_ACC_MASK       0x000F0000      /* Changes for corerev 11 */
+#define  SSB_CHIPCO_JCMD_ACC_IRDR       0x00000000
+#define  SSB_CHIPCO_JCMD_ACC_DR         0x00010000
+#define  SSB_CHIPCO_JCMD_ACC_IR         0x00020000
+#define  SSB_CHIPCO_JCMD_ACC_RESET      0x00030000
+#define  SSB_CHIPCO_JCMD_ACC_IRPDR      0x00040000
+#define  SSB_CHIPCO_JCMD_ACC_PDR        0x00050000
+#define  SSB_CHIPCO_JCMD_IRW_MASK       0x00001F00
+#define  SSB_CHIPCO_JCMD_IRW_SHIFT      8
+#define  SSB_CHIPCO_JCMD_DRW_MASK       0x0000003F
+#define SSB_CHIPCO_JIR                  0x0034          /* Rev >= 10 only */
+#define SSB_CHIPCO_JDR                  0x0038          /* Rev >= 10 only */
+#define SSB_CHIPCO_JCTL                 0x003C          /* Rev >= 10 only */
+#define  SSB_CHIPCO_JCTL_FORCE_CLK      4               /* Force clock */
+#define  SSB_CHIPCO_JCTL_EXT_EN         2               /* Enable external targets */
+#define  SSB_CHIPCO_JCTL_EN             1               /* Enable Jtag master */
+#define SSB_CHIPCO_FLASHCTL             0x0040
+#define  SSB_CHIPCO_FLASHCTL_START      0x80000000
+#define  SSB_CHIPCO_FLASHCTL_BUSY       SSB_CHIPCO_FLASHCTL_START
+#define SSB_CHIPCO_FLASHADDR            0x0044
+#define SSB_CHIPCO_FLASHDATA            0x0048
+#define SSB_CHIPCO_BCAST_ADDR           0x0050
+#define SSB_CHIPCO_BCAST_DATA           0x0054
+#define SSB_CHIPCO_GPIOIN               0x0060
+#define SSB_CHIPCO_GPIOOUT              0x0064
+#define SSB_CHIPCO_GPIOOUTEN            0x0068
+#define SSB_CHIPCO_GPIOCTL              0x006C
+#define SSB_CHIPCO_GPIOPOL              0x0070
+#define SSB_CHIPCO_GPIOIRQ              0x0074
+#define SSB_CHIPCO_WATCHDOG             0x0080
+#define SSB_CHIPCO_GPIOTIMER            0x0088          /* LED powersave (corerev >= 16) */
+#define  SSB_CHIPCO_GPIOTIMER_ONTIME_SHIFT      16
+#define SSB_CHIPCO_GPIOTOUTM            0x008C          /* LED powersave (corerev >= 16) */
+#define SSB_CHIPCO_CLOCK_N              0x0090
+#define SSB_CHIPCO_CLOCK_SB             0x0094
+#define SSB_CHIPCO_CLOCK_PCI            0x0098
+#define SSB_CHIPCO_CLOCK_M2             0x009C
+#define SSB_CHIPCO_CLOCK_MIPS           0x00A0
+#define SSB_CHIPCO_CLKDIV               0x00A4          /* Rev >= 3 only */
+#define  SSB_CHIPCO_CLKDIV_SFLASH       0x0F000000
+#define  SSB_CHIPCO_CLKDIV_SFLASH_SHIFT 24
+#define  SSB_CHIPCO_CLKDIV_OTP          0x000F0000
+#define  SSB_CHIPCO_CLKDIV_OTP_SHIFT    16
+#define  SSB_CHIPCO_CLKDIV_JTAG         0x00000F00
+#define  SSB_CHIPCO_CLKDIV_JTAG_SHIFT   8
+#define  SSB_CHIPCO_CLKDIV_UART         0x000000FF
+#define SSB_CHIPCO_PLLONDELAY           0x00B0          /* Rev >= 4 only */
+#define SSB_CHIPCO_FREFSELDELAY         0x00B4          /* Rev >= 4 only */
+#define SSB_CHIPCO_SLOWCLKCTL           0x00B8          /* 6 <= Rev <= 9 only */
+#define  SSB_CHIPCO_SLOWCLKCTL_SRC      0x00000007      /* slow clock source mask */
+#define   SSB_CHIPCO_SLOWCLKCTL_SRC_LPO         0x00000000      /* source of slow clock is LPO */
+#define   SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL        0x00000001      /* source of slow clock is crystal */
+#define   SSB_CHIPCO_SLOECLKCTL_SRC_PCI         0x00000002      /* source of slow clock is PCI */
+#define  SSB_CHIPCO_SLOWCLKCTL_LPOFREQ  0x00000200      /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
+#define  SSB_CHIPCO_SLOWCLKCTL_LPOPD    0x00000400      /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
+#define  SSB_CHIPCO_SLOWCLKCTL_FSLOW    0x00000800      /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
+#define  SSB_CHIPCO_SLOWCLKCTL_IPLL     0x00001000      /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */
+#define  SSB_CHIPCO_SLOWCLKCTL_ENXTAL   0x00002000      /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */
+#define  SSB_CHIPCO_SLOWCLKCTL_XTALPU   0x00004000      /* XtalPU (RO), 1/0: crystal running/disabled */
+#define  SSB_CHIPCO_SLOWCLKCTL_CLKDIV   0xFFFF0000      /* ClockDivider (SlowClk = 1/(4+divisor)) */
+#define  SSB_CHIPCO_SLOWCLKCTL_CLKDIV_SHIFT     16
+#define SSB_CHIPCO_SYSCLKCTL            0x00C0          /* Rev >= 3 only */
+#define  SSB_CHIPCO_SYSCLKCTL_IDLPEN    0x00000001      /* ILPen: Enable Idle Low Power */
+#define  SSB_CHIPCO_SYSCLKCTL_ALPEN     0x00000002      /* ALPen: Enable Active Low Power */
+#define  SSB_CHIPCO_SYSCLKCTL_PLLEN     0x00000004      /* ForcePLLOn */
+#define  SSB_CHIPCO_SYSCLKCTL_FORCEALP  0x00000008      /* Force ALP (or HT if ALPen is not set */
+#define  SSB_CHIPCO_SYSCLKCTL_FORCEHT   0x00000010      /* Force HT */
+#define  SSB_CHIPCO_SYSCLKCTL_CLKDIV    0xFFFF0000      /* ClkDiv  (ILP = 1/(4+divisor)) */
+#define  SSB_CHIPCO_SYSCLKCTL_CLKDIV_SHIFT      16
+#define SSB_CHIPCO_CLKSTSTR             0x00C4          /* Rev >= 3 only */
+#define SSB_CHIPCO_PCMCIA_CFG           0x0100
+#define SSB_CHIPCO_PCMCIA_MEMWAIT       0x0104
+#define SSB_CHIPCO_PCMCIA_ATTRWAIT      0x0108
+#define SSB_CHIPCO_PCMCIA_IOWAIT        0x010C
+#define SSB_CHIPCO_IDE_CFG              0x0110
+#define SSB_CHIPCO_IDE_MEMWAIT          0x0114
+#define SSB_CHIPCO_IDE_ATTRWAIT         0x0118
+#define SSB_CHIPCO_IDE_IOWAIT           0x011C
+#define SSB_CHIPCO_PROG_CFG             0x0120
+#define SSB_CHIPCO_PROG_WAITCNT         0x0124
+#define SSB_CHIPCO_FLASH_CFG            0x0128
+#define SSB_CHIPCO_FLASH_WAITCNT        0x012C
+#define SSB_CHIPCO_UART0_DATA           0x0300
+#define SSB_CHIPCO_UART0_IMR            0x0304
+#define SSB_CHIPCO_UART0_FCR            0x0308
+#define SSB_CHIPCO_UART0_LCR            0x030C
+#define SSB_CHIPCO_UART0_MCR            0x0310
+#define SSB_CHIPCO_UART0_LSR            0x0314
+#define SSB_CHIPCO_UART0_MSR            0x0318
+#define SSB_CHIPCO_UART0_SCRATCH        0x031C
+#define SSB_CHIPCO_UART1_DATA           0x0400
+#define SSB_CHIPCO_UART1_IMR            0x0404
+#define SSB_CHIPCO_UART1_FCR            0x0408
+#define SSB_CHIPCO_UART1_LCR            0x040C
+#define SSB_CHIPCO_UART1_MCR            0x0410
+#define SSB_CHIPCO_UART1_LSR            0x0414
+#define SSB_CHIPCO_UART1_MSR            0x0418
+#define SSB_CHIPCO_UART1_SCRATCH        0x041C
+
+
+
+/** Clockcontrol masks and values **/
+
+/* SSB_CHIPCO_CLOCK_N */
+#define SSB_CHIPCO_CLK_N1               0x0000003F      /* n1 control */
+#define SSB_CHIPCO_CLK_N2               0x00003F00      /* n2 control */
+#define SSB_CHIPCO_CLK_N2_SHIFT         8
+#define SSB_CHIPCO_CLK_PLLC             0x000F0000      /* pll control */
+#define SSB_CHIPCO_CLK_PLLC_SHIFT       16
+
+/* SSB_CHIPCO_CLOCK_SB/PCI/UART */
+#define SSB_CHIPCO_CLK_M1               0x0000003F      /* m1 control */
+#define SSB_CHIPCO_CLK_M2               0x00003F00      /* m2 control */
+#define SSB_CHIPCO_CLK_M2_SHIFT         8
+#define SSB_CHIPCO_CLK_M3               0x003F0000      /* m3 control */
+#define SSB_CHIPCO_CLK_M3_SHIFT         16
+#define SSB_CHIPCO_CLK_MC               0x1F000000      /* mux control */
+#define SSB_CHIPCO_CLK_MC_SHIFT         24
+
+/* N3M Clock control magic field values */
+#define SSB_CHIPCO_CLK_F6_2             0x02            /* A factor of 2 in */
+#define SSB_CHIPCO_CLK_F6_3             0x03            /* 6-bit fields like */
+#define SSB_CHIPCO_CLK_F6_4             0x05            /* N1, M1 or M3 */
+#define SSB_CHIPCO_CLK_F6_5             0x09
+#define SSB_CHIPCO_CLK_F6_6             0x11
+#define SSB_CHIPCO_CLK_F6_7             0x21
+
+#define SSB_CHIPCO_CLK_F5_BIAS          5               /* 5-bit fields get this added */
+
+#define SSB_CHIPCO_CLK_MC_BYPASS        0x08
+#define SSB_CHIPCO_CLK_MC_M1            0x04
+#define SSB_CHIPCO_CLK_MC_M1M2          0x02
+#define SSB_CHIPCO_CLK_MC_M1M2M3        0x01
+#define SSB_CHIPCO_CLK_MC_M1M3          0x11
+
+/* Type 2 Clock control magic field values */
+#define SSB_CHIPCO_CLK_T2_BIAS          2               /* n1, n2, m1 & m3 bias */
+#define SSB_CHIPCO_CLK_T2M2_BIAS        3               /* m2 bias */
+
+#define SSB_CHIPCO_CLK_T2MC_M1BYP       1
+#define SSB_CHIPCO_CLK_T2MC_M2BYP       2
+#define SSB_CHIPCO_CLK_T2MC_M3BYP       4
+
+/* Type 6 Clock control magic field values */
+#define SSB_CHIPCO_CLK_T6_MMASK         1               /* bits of interest in m */
+#define SSB_CHIPCO_CLK_T6_M0            120000000       /* sb clock for m = 0 */
+#define SSB_CHIPCO_CLK_T6_M1            100000000       /* sb clock for m = 1 */
+#define SSB_CHIPCO_CLK_SB2MIPS_T6(sb)   (2 * (sb))
+
+/* Common clock base */
+#define SSB_CHIPCO_CLK_BASE1            24000000        /* Half the clock freq */
+#define SSB_CHIPCO_CLK_BASE2            12500000        /* Alternate crystal on some PLL's */
+
+/* Clock control values for 200Mhz in 5350 */
+#define SSB_CHIPCO_CLK_5350_N           0x0311
+#define SSB_CHIPCO_CLK_5350_M           0x04020009
+
+
+/** Bits in the config registers **/
+
+#define SSB_CHIPCO_CFG_EN               0x0001          /* Enable */
+#define SSB_CHIPCO_CFG_EXTM             0x000E          /* Extif Mode */
+#define  SSB_CHIPCO_CFG_EXTM_ASYNC      0x0002          /* Async/Parallel flash */
+#define  SSB_CHIPCO_CFG_EXTM_SYNC       0x0004          /* Synchronous */
+#define  SSB_CHIPCO_CFG_EXTM_PCMCIA     0x0008          /* PCMCIA */
+#define  SSB_CHIPCO_CFG_EXTM_IDE        0x000A          /* IDE */
+#define SSB_CHIPCO_CFG_DS16             0x0010          /* Data size, 0=8bit, 1=16bit */
+#define SSB_CHIPCO_CFG_CLKDIV           0x0060          /* Sync: Clock divisor */
+#define SSB_CHIPCO_CFG_CLKEN            0x0080          /* Sync: Clock enable */
+#define SSB_CHIPCO_CFG_BSTRO            0x0100          /* Sync: Size/Bytestrobe */
+
+
+/** Flash-specific control/status values */
+
+/* flashcontrol opcodes for ST flashes */
+#define SSB_CHIPCO_FLASHCTL_ST_WREN     0x0006          /* Write Enable */
+#define SSB_CHIPCO_FLASHCTL_ST_WRDIS    0x0004          /* Write Disable */
+#define SSB_CHIPCO_FLASHCTL_ST_RDSR     0x0105          /* Read Status Register */
+#define SSB_CHIPCO_FLASHCTL_ST_WRSR     0x0101          /* Write Status Register */
+#define SSB_CHIPCO_FLASHCTL_ST_READ     0x0303          /* Read Data Bytes */
+#define SSB_CHIPCO_FLASHCTL_ST_PP       0x0302          /* Page Program */
+#define SSB_CHIPCO_FLASHCTL_ST_SE       0x02D8          /* Sector Erase */
+#define SSB_CHIPCO_FLASHCTL_ST_BE       0x00C7          /* Bulk Erase */
+#define SSB_CHIPCO_FLASHCTL_ST_DP       0x00B9          /* Deep Power-down */
+#define SSB_CHIPCO_FLASHCTL_ST_RSIG     0x03AB          /* Read Electronic Signature */
+
+/* Status register bits for ST flashes */
+#define SSB_CHIPCO_FLASHSTA_ST_WIP      0x01            /* Write In Progress */
+#define SSB_CHIPCO_FLASHSTA_ST_WEL      0x02            /* Write Enable Latch */
+#define SSB_CHIPCO_FLASHSTA_ST_BP       0x1C            /* Block Protect */
+#define SSB_CHIPCO_FLASHSTA_ST_BP_SHIFT 2
+#define SSB_CHIPCO_FLASHSTA_ST_SRWD     0x80            /* Status Register Write Disable */
+
+/* flashcontrol opcodes for Atmel flashes */
+#define SSB_CHIPCO_FLASHCTL_AT_READ             0x07E8
+#define SSB_CHIPCO_FLASHCTL_AT_PAGE_READ        0x07D2
+#define SSB_CHIPCO_FLASHCTL_AT_BUF1_READ        /* FIXME */
+#define SSB_CHIPCO_FLASHCTL_AT_BUF2_READ        /* FIXME */
+#define SSB_CHIPCO_FLASHCTL_AT_STATUS           0x01D7
+#define SSB_CHIPCO_FLASHCTL_AT_BUF1_WRITE       0x0384
+#define SSB_CHIPCO_FLASHCTL_AT_BUF2_WRITE       0x0387
+#define SSB_CHIPCO_FLASHCTL_AT_BUF1_ERASE_PRGM  0x0283  /* Erase program */
+#define SSB_CHIPCO_FLASHCTL_AT_BUF2_ERASE_PRGM  0x0286  /* Erase program */
+#define SSB_CHIPCO_FLASHCTL_AT_BUF1_PROGRAM     0x0288
+#define SSB_CHIPCO_FLASHCTL_AT_BUF2_PROGRAM     0x0289
+#define SSB_CHIPCO_FLASHCTL_AT_PAGE_ERASE       0x0281
+#define SSB_CHIPCO_FLASHCTL_AT_BLOCK_ERASE      0x0250
+#define SSB_CHIPCO_FLASHCTL_AT_BUF1_WRER_PRGM   0x0382  /* Write erase program */
+#define SSB_CHIPCO_FLASHCTL_AT_BUF2_WRER_PRGM   0x0385  /* Write erase program */
+#define SSB_CHIPCO_FLASHCTL_AT_BUF1_LOAD        0x0253
+#define SSB_CHIPCO_FLASHCTL_AT_BUF2_LOAD        0x0255
+#define SSB_CHIPCO_FLASHCTL_AT_BUF1_COMPARE     0x0260
+#define SSB_CHIPCO_FLASHCTL_AT_BUF2_COMPARE     0x0261
+#define SSB_CHIPCO_FLASHCTL_AT_BUF1_REPROGRAM   0x0258
+#define SSB_CHIPCO_FLASHCTL_AT_BUF2_REPROGRAM   0x0259
+
+/* Status register bits for Atmel flashes */
+#define SSB_CHIPCO_FLASHSTA_AT_READY    0x80
+#define SSB_CHIPCO_FLASHSTA_AT_MISMATCH 0x40
+#define SSB_CHIPCO_FLASHSTA_AT_ID       0x38
+#define SSB_CHIPCO_FLASHSTA_AT_ID_SHIFT 3
+
+
+/** OTP **/
+
+/* OTP regions */
+#define SSB_CHIPCO_OTP_HW_REGION        SSB_CHIPCO_OTPS_HW_PROTECT
+#define SSB_CHIPCO_OTP_SW_REGION        SSB_CHIPCO_OTPS_SW_PROTECT
+#define SSB_CHIPCO_OTP_CID_REGION       SSB_CHIPCO_OTPS_CID_PROTECT
+
+/* OTP regions (Byte offsets from otp size) */
+#define SSB_CHIPCO_OTP_SWLIM_OFF        (-8)
+#define SSB_CHIPCO_OTP_CIDBASE_OFF      0
+#define SSB_CHIPCO_OTP_CIDLIM_OFF       8
+
+/* Predefined OTP words (Word offset from otp size) */
+#define SSB_CHIPCO_OTP_BOUNDARY_OFF     (-4)
+#define SSB_CHIPCO_OTP_HWSIGN_OFF       (-3)
+#define SSB_CHIPCO_OTP_SWSIGN_OFF       (-2)
+#define SSB_CHIPCO_OTP_CIDSIGN_OFF      (-1)
+
+#define SSB_CHIPCO_OTP_CID_OFF          0
+#define SSB_CHIPCO_OTP_PKG_OFF          1
+#define SSB_CHIPCO_OTP_FID_OFF          2
+#define SSB_CHIPCO_OTP_RSV_OFF          3
+#define SSB_CHIPCO_OTP_LIM_OFF          4
+
+#define SSB_CHIPCO_OTP_SIGNATURE        0x578A
+#define SSB_CHIPCO_OTP_MAGIC            0x4E56
+
+
+struct ssb_device;
+struct ssb_serial_port;
+
+struct ssb_chipcommon {
+        struct ssb_device *dev;
+        u32 capabilities;
+};
+
+enum ssb_clkmode {
+        SSB_CLKMODE_SLOW,
+        SSB_CLKMODE_FAST,
+        SSB_CLKMODE_DYNAMIC,
+};
+
+extern void ssb_chipcommon_init(struct ssb_chipcommon *cc);
+extern void ssb_chipcommon_exit(struct ssb_chipcommon *cc);
+
+extern void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
+                                        u32 *plltype, u32 *n, u32 *m);
+extern void ssb_chipco_timing_init(struct ssb_chipcommon *cc,
+                                   unsigned long ns_per_cycle);
+
+#ifdef CONFIG_SSB_SERIAL
+extern int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
+                                  struct ssb_serial_port *ports);
+#endif /* CONFIG_SSB_SERIAL */
+
+#endif /* __KERNEL__ */
+#endif /* LINUX_SSB_CHIPCO_H_ */

include/linux/ssb_driver_extif.h

@@ +1 @@
+/*
+ * Hardware-specific External Interface I/O core definitions
+ * for the BCM47xx family of SiliconBackplane-based chips.
+ *
+ * The External Interface core supports a total of three external chip selects
+ * supporting external interfaces. One of the external chip selects is
+ * used for Flash, one is used for PCMCIA, and the other may be
+ * programmed to support either a synchronous interface or an
+ * asynchronous interface. The asynchronous interface can be used to
+ * support external devices such as UARTs and the BCM2019 Bluetooth
+ * baseband processor.
+ * The external interface core also contains 2 on-chip 16550 UARTs, clock
+ * frequency control, a watchdog interrupt timer, and a GPIO interface.
+ *
+ * Copyright 2005, Broadcom Corporation      
+ * Copyright 2006, Michael Buesch
+ *
+ * Licensed under the GPL version 2. See COPYING for details.
+ */
+#ifndef LINUX_SSB_EXTIFCORE_H_
+#define LINUX_SSB_EXTIFCORE_H_
+
+#ifdef __KERNEL__
+
+/* external interface address space */
+#define SSB_EXTIF_PCMCIA_MEMBASE(x)     (x)
+#define SSB_EXTIF_PCMCIA_IOBASE(x)      ((x) + 0x100000)
+#define SSB_EXTIF_PCMCIA_CFGBASE(x)     ((x) + 0x200000)
+#define SSB_EXTIF_CFGIF_BASE(x)         ((x) + 0x800000)
+#define SSB_EXTIF_FLASH_BASE(x)         ((x) + 0xc00000)
+
+#define SSB_EXTIF_NR_GPIOOUT            5
+/* GPIO NOTE:
+ * The multiple instances of output and output enable registers
+ * are present to allow driver software for multiple cores to control
+ * gpio outputs without needing to share a single register pair.
+ * Use the following helper macro to get a register offset value.
+ */
+#define SSB_EXTIF_GPIO_OUT(index)       ({              \
+        BUILD_BUG_ON(index >= SSB_EXTIF_NR_GPIOOUT);    \
+        SSB_EXTIF_GPIO_OUT_BASE + ((index) * 8);        \
+                                        })
+#define SSB_EXTIF_GPIO_OUTEN(index)     ({              \
+        BUILD_BUG_ON(index >= SSB_EXTIF_NR_GPIOOUT);    \
+        SSB_EXTIF_GPIO_OUTEN_BASE + ((index) * 8);      \
+                                        })
+
+/** EXTIF core registers **/
+
+#define SSB_EXTIF_CTL                   0x0000
+#define  SSB_EXTIF_CTL_UARTEN           (1 << 0) /* UART enable */
+#define SSB_EXTIF_EXTSTAT               0x0004
+#define  SSB_EXTIF_EXTSTAT_EMODE        (1 << 0) /* Endian mode (ro) */
+#define  SSB_EXTIF_EXTSTAT_EIRQPIN      (1 << 1) /* External interrupt pin (ro) */
+#define  SSB_EXTIF_EXTSTAT_GPIOIRQPIN   (1 << 2) /* GPIO interrupt pin (ro) */
+#define SSB_EXTIF_PCMCIA_CFG            0x0010
+#define SSB_EXTIF_PCMCIA_MEMWAIT        0x0014
+#define SSB_EXTIF_PCMCIA_ATTRWAIT       0x0018
+#define SSB_EXTIF_PCMCIA_IOWAIT         0x001C
+#define SSB_EXTIF_PROG_CFG              0x0020
+#define SSB_EXTIF_PROG_WAITCNT          0x0024
+#define SSB_EXTIF_FLASH_CFG             0x0028
+#define SSB_EXTIF_FLASH_WAITCNT         0x002C
+#define SSB_EXTIF_WATCHDOG              0x0040
+#define SSB_EXTIF_CLOCK_N               0x0044
+#define SSB_EXTIF_CLOCK_SB              0x0048
+#define SSB_EXTIF_CLOCK_PCI             0x004C
+#define SSB_EXTIF_CLOCK_MII             0x0050
+#define SSB_EXTIF_GPIO_IN               0x0060
+#define SSB_EXTIF_GPIO_OUT_BASE         0x0064
+#define SSB_EXTIF_GPIO_OUTEN_BASE       0x0068
+#define SSB_EXTIF_EJTAG_OUTEN           0x0090
+#define SSB_EXTIF_GPIO_INTPOL           0x0094
+#define SSB_EXTIF_GPIO_INTMASK          0x0098
+#define SSB_EXTIF_UART_DATA             0x0300
+#define SSB_EXTIF_UART_TIMER            0x0310
+#define SSB_EXTIF_UART_FCR              0x0320
+#define SSB_EXTIF_UART_LCR              0x0330
+#define SSB_EXTIF_UART_MCR              0x0340
+#define SSB_EXTIF_UART_LSR              0x0350
+#define SSB_EXTIF_UART_MSR              0x0360
+#define SSB_EXTIF_UART_SCRATCH          0x0370
+
+
+
+
+/* pcmcia/prog/flash_config */
+#define SSB_EXTCFG_EN                   (1 << 0)        /* enable */
+#define SSB_EXTCFG_MODE                 0xE             /* mode */
+#define SSB_EXTCFG_MODE_SHIFT           1
+#define  SSB_EXTCFG_MODE_FLASH          0x0             /* flash/asynchronous mode */
+#define  SSB_EXTCFG_MODE_SYNC           0x2             /* synchronous mode */
+#define  SSB_EXTCFG_MODE_PCMCIA         0x4             /* pcmcia mode */
+#define SSB_EXTCFG_DS16                 (1 << 4)        /* destsize:  0=8bit, 1=16bit */
+#define SSB_EXTCFG_BSWAP                (1 << 5)        /* byteswap */
+#define SSB_EXTCFG_CLKDIV               0xC0            /* clock divider */
+#define SSB_EXTCFG_CLKDIV_SHIFT         6
+#define  SSB_EXTCFG_CLKDIV_2            0x0             /* backplane/2 */
+#define  SSB_EXTCFG_CLKDIV_3            0x40            /* backplane/3 */
+#define  SSB_EXTCFG_CLKDIV_4            0x80            /* backplane/4 */
+#define SSB_EXTCFG_CLKEN                (1 << 8)        /* clock enable */
+#define SSB_EXTCFG_STROBE               (1 << 9)        /* size/bytestrobe (synch only) */
+
+/* pcmcia_memwait */
+#define SSB_PCMCIA_MEMW_0               0x0000003F      /* waitcount0 */
+#define SSB_PCMCIA_MEMW_1               0x00001F00      /* waitcount1 */
+#define SSB_PCMCIA_MEMW_1_SHIFT         8
+#define SSB_PCMCIA_MEMW_2               0x001F0000      /* waitcount2 */
+#define SSB_PCMCIA_MEMW_2_SHIFT         16
+#define SSB_PCMCIA_MEMW_3               0x1F000000      /* waitcount3 */
+#define SSB_PCMCIA_MEMW_3_SHIFT         24
+
+/* pcmcia_attrwait */
+#define SSB_PCMCIA_ATTW_0               0x0000003F      /* waitcount0 */
+#define SSB_PCMCIA_ATTW_1               0x00001F00      /* waitcount1 */
+#define SSB_PCMCIA_ATTW_1_SHIFT         8
+#define SSB_PCMCIA_ATTW_2               0x001F0000      /* waitcount2 */
+#define SSB_PCMCIA_ATTW_2_SHIFT         16
+#define SSB_PCMCIA_ATTW_3               0x1F000000      /* waitcount3 */
+#define SSB_PCMCIA_ATTW_3_SHIFT         24
+
+/* pcmcia_iowait */
+#define SSB_PCMCIA_IOW_0                0x0000003F      /* waitcount0 */
+#define SSB_PCMCIA_IOW_1                0x00001F00      /* waitcount1 */
+#define SSB_PCMCIA_IOW_1_SHIFT          8
+#define SSB_PCMCIA_IOW_2                0x001F0000      /* waitcount2 */
+#define SSB_PCMCIA_IOW_2_SHIFT          16
+#define SSB_PCMCIA_IOW_3                0x1F000000      /* waitcount3 */
+#define SSB_PCMCIA_IOW_3_SHIFT          24
+
+/* prog_waitcount */
+#define SSB_PROG_WCNT_0                 0x0000001F      /* waitcount0 */
+#define SSB_PROG_WCNT_1                 0x00001F00      /* waitcount1 */
+#define SSB_PROG_WCNT_1_SHIFT           8
+#define SSB_PROG_WCNT_2                 0x001F0000      /* waitcount2 */
+#define SSB_PROG_WCNT_2_SHIFT           16
+#define SSB_PROG_WCNT_3                 0x1F000000      /* waitcount3 */
+#define SSB_PROG_WCNT_3_SHIFT           24
+
+#define SSB_PROG_W0                     0x0000000C
+#define SSB_PROG_W1                     0x00000A00
+#define SSB_PROG_W2                     0x00020000
+#define SSB_PROG_W3                     0x01000000
+
+/* flash_waitcount */
+#define SSB_FLASH_WCNT_0                0x0000001F      /* waitcount0 */
+#define SSB_FLASH_WCNT_1                0x00001F00      /* waitcount1 */
+#define SSB_FLASH_WCNT_1_SHIFT          8
+#define SSB_FLASH_WCNT_2                0x001F0000      /* waitcount2 */
+#define SSB_FLASH_WCNT_2_SHIFT          16
+#define SSB_FLASH_WCNT_3                0x1F000000      /* waitcount3 */
+#define SSB_FLASH_WCNT_3_SHIFT          24
+
+/* watchdog */
+#define SSB_EXTIF_WATCHDOG_CLK          48000000        /* Hz */
+
+
+#endif /* __KERNEL__ */
+#endif /* LINUX_SSB_EXTIFCORE_H_ */

include/linux/ssb_driver_mips.h

@@ +1 @@
+#ifndef LINUX_SSB_MIPSCORE_H_
+#define LINUX_SSB_MIPSCORE_H_
+
+#ifdef __KERNEL__
+
+#ifdef CONFIG_SSB_DRIVER_MIPS
+
+struct ssb_device;
+
+struct ssb_serial_port {
+        void *regs;
+        unsigned int irq;
+        unsigned int baud_base;
+        unsigned int reg_shift;
+};
+
+
+struct ssb_mipscore {
+        struct ssb_device *dev;
+        
+        int nr_serial_ports;
+        struct ssb_serial_port serial_ports[4];
+
+        u32 flash_window;
+        u32 flash_window_size;
+};
+
+extern void ssb_mipscore_init(struct ssb_mipscore *mcore);
+
+extern unsigned int ssb_mips_irq(struct ssb_device *dev);
+
+
+#else /* CONFIG_SSB_DRIVER_MIPS */
+
+struct ssb_mipscore {
+};
+
+static inline
+void ssb_mipscore_init(struct ssb_mipscore *mcore)
+{
+}
+
+#endif /* CONFIG_SSB_DRIVER_MIPS */
+
+#endif /* __KERNEL__ */
+#endif /* LINUX_SSB_MIPSCORE_H_ */

include/linux/ssb_driver_pci.h

@@ +1 @@
+#ifndef LINUX_SSB_PCICORE_H_
+#define LINUX_SSB_PCICORE_H_
+#ifndef __KERNEL__
+
+
+/* PCI core registers. */
+#define SSB_PCICORE_CTL         0x0000  /* PCI Control */
+#define SSB_PCICORE_ARBCTL      0x0010  /* PCI Arbiter Control */
+#define SSB_PCICORE_ISTAT       0x0020  /* Interrupt status */
+#define SSB_PCICORE_IMASK       0x0024  /* Interrupt mask */
+#define SSB_PCICORE_MBOX        0x0028  /* Backplane to PCI Mailbox */
+#define SSB_PCICORE_BCAST_ADDR  0x0050  /* Backplane Broadcast Address */
+#define SSB_PCICORE_BCAST_DATA  0x0054  /* Backplane Broadcast Data */
+#define SSB_PCICORE_GPIO_IN     0x0060  /* rev >= 2 only */
+#define SSB_PCICORE_GPIO_OUT    0x0064  /* rev >= 2 only */
+#define SSB_PCICORE_GPIO_ENABLE 0x0068  /* rev >= 2 only */
+#define SSB_PCICORE_GPIO_CTL    0x006C  /* rev >= 2 only */
+#define SSB_PCICORE_TRANS0      0x0100  /* Backplane to PCI translation 0 (sbtopci0) */
+#define SSB_PCICORE_TRANS1      0x0104  /* Backplane to PCI translation 1 (sbtopci1) */
+#define SSB_PCICORE_TRANS2      0x0108  /* Backplane to PCI translation 2 (dbtopci2) */
+#define  SSB_PCICORE_TRANS2_MEM         0x00000000
+#define  SSB_PCICORE_TRANS2_IO          0x00000001
+#define  SSB_PCICORE_TRANS2_CFG0        0x00000002
+#define  SSB_PCICORE_TRANS2_CFG1        0x00000003
+#define  SSB_PCICORE_TRANS2_PREF        0x00000004      /* Prefetch enable */
+#define  SSB_PCICORE_TRANS2_BURST       0x00000008      /* Burst enable */
+#define  SSB_PCICORE_TRANS2_MRM         0x00000020      /* Memory Read Multiple */
+#define  SSB_PCICORE_TRANS2_MASK0       0xfc000000
+#define  SSB_PCICORE_TRANS2_MASK1       0xfc000000
+#define  SSB_PCICORE_TRANS2_MASK2       0xc0000000
+
+
+
+#endif /* __KERNEL__ */
+#endif /* LINUX_SSB_PCICORE_H_ */

include/linux/ssb_regs.h

@@ +1 @@
+#ifndef LINUX_SSB_REGS_H_
+#define LINUX_SSB_REGS_H_
+#ifdef __KERNEL__
+
+
+/* SiliconBackplane Address Map.
+ * All regions may not exist on all chips.
+ */
+#define SSB_SDRAM_BASE          0x00000000      /* Physical SDRAM */
+#define SSB_PCI_MEM             0x08000000      /* Host Mode sb2pcitranslation0 (64 MB) */
+#define SSB_PCI_CFG             0x0c000000      /* Host Mode sb2pcitranslation1 (64 MB) */
+#define SSB_SDRAM_SWAPPED       0x10000000      /* Byteswapped Physical SDRAM */
+#define SSB_ENUM_BASE           0x18000000      /* Enumeration space base */
+#define SSB_ENUM_LIMIT          0x18010000      /* Enumeration space limit */
+
+#define SSB_FLASH2              0x1c000000      /* Flash Region 2 (region 1 shadowed here) */
+#define SSB_FLASH2_SZ           0x02000000      /* Size of Flash Region 2 */
+
+#define SSB_EXTIF_BASE          0x1f000000      /* External Interface region base address */
+#define SSB_FLASH1              0x1fc00000      /* Flash Region 1 */
+#define SSB_FLASH1_SZ           0x00400000      /* Size of Flash Region 1 */
+
+#define SSB_PCI_DMA             0x40000000      /* Client Mode sb2pcitranslation2 (1 GB) */
+#define SSB_PCI_DMA_SZ          0x40000000      /* Client Mode sb2pcitranslation2 size in bytes */
+#define SSB_PCIE_DMA_L32                0x00000000      /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), low 32 bits */
+#define SSB_PCIE_DMA_H32                0x80000000      /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), high 32 bits */
+#define SSB_EUART               (SB_EXTIF_BASE + 0x00800000)
+#define SSB_LED                 (SB_EXTIF_BASE + 0x00900000)
+
+
+/* Enumeration space constants */
+#define SSB_CORE_SIZE           0x1000  /* Size of a core MMIO area */
+#define SSB_MAX_NR_CORES        ((SSB_ENUM_LIMIT - SSB_ENUM_BASE) / SSB_CORE_SIZE)
+
+
+/* mips address */
+#define SSB_EJTAG               0xff200000      /* MIPS EJTAG space (2M) */
+
+
+/* SSB PCI config space registers. */
+#define SSB_BAR0_WIN            0x80    /* Backplane address space 0 */
+#define SSB_BAR1_WIN            0x84    /* Backplane address space 1 */
+#define SSB_SPROMCTL            0x88    /* SPROM control */
+#define  SSB_SPROMCTL_WE        0x10    /* SPROM write enable */
+#define SSB_BAR1_CONTROL        0x8c    /* Address space 1 burst control */
+#define SSB_PCI_IRQS            0x90    /* PCI interrupts */
+#define SSB_PCI_IRQMASK         0x94    /* PCI IRQ control and mask (pcirev >= 6 only) */
+#define SSB_BACKPLANE_IRQS      0x98    /* Backplane Interrupts */
+#define SSB_GPIO_IN             0xB0    /* GPIO Input (pcirev >= 3 only) */
+#define SSB_GPIO_OUT            0xB4    /* GPIO Output (pcirev >= 3 only) */
+#define SSB_GPIO_OUT_ENABLE     0xB8    /* GPIO Output Enable/Disable (pcirev >= 3 only) */
+#define  SSB_GPIO_SCS           0x10    /* PCI config space bit 4 for 4306c0 slow clock source */
+#define  SSB_GPIO_HWRAD         0x20    /* PCI config space GPIO 13 for hw radio disable */
+#define  SSB_GPIO_XTAL          0x40    /* PCI config space GPIO 14 for Xtal powerup */
+#define  SSB_GPIO_PLL           0x80    /* PCI config space GPIO 15 for PLL powerdown */
+
+
+#define SSB_BAR0_MAX_RETRIES    50
+
+/* Silicon backplane configuration register definitions */
+#define SSB_IPSFLAG             0x0F08
+#define  SSB_IPSFLAG_IRQ1       0x0000003F /* which sbflags get routed to mips interrupt 1 */
+#define  SSB_IPSFLAG_IRQ1_SHIFT 0
+#define  SSB_IPSFLAG_IRQ2       0x00003F00 /* which sbflags get routed to mips interrupt 2 */
+#define  SSB_IPSFLAG_IRQ2_SHIFT 8
+#define  SSB_IPSFLAG_IRQ3       0x003F0000 /* which sbflags get routed to mips interrupt 3 */
+#define  SSB_IPSFLAG_IRQ3_SHIFT 16
+#define  SSB_IPSFLAG_IRQ4       0x3F000000 /* which sbflags get routed to mips interrupt 4 */
+#define  SSB_IPSFLAG_IRQ4_SHIFT 24
+#define SSB_TPSFLAG             0x0F18
+#define  SSB_TPSFLAG_BPFLAG     0x0000003F /* Backplane flag # */
+#define  SSB_TPSFLAG_ALWAYSIRQ  0x00000040 /* IRQ is always sent on the Backplane */
+#define SSB_TMERRLOGA           0x0F48
+#define SSB_TMERRLOG            0x0F50
+#define SSB_ADMATCH3            0x0F60
+#define SSB_ADMATCH2            0x0F68
+#define SSB_ADMATCH1            0x0F70
+#define SSB_IMSTATE             0x0F90     /* SB Initiator Agent State */
+#define  SSB_IMSTATE_PC         0x0000000f /* Pipe Count */
+#define  SSB_IMSTATE_AP_MASK    0x00000030 /* Arbitration Priority */
+#define  SSB_IMSTATE_AP_BOTH    0x00000000 /* Use both timeslices and token */
+#define  SSB_IMSTATE_AP_TS      0x00000010 /* Use timeslices only */
+#define  SSB_IMSTATE_AP_TK      0x00000020 /* Use token only */
+#define  SSB_IMSTATE_AP_RSV     0x00000030 /* Reserved */
+#define  SSB_IMSTATE_IBE        0x00020000 /* In Band Error */
+#define  SSB_IMSTATE_TO         0x00040000 /* Timeout */
+#define SSB_INTVEC              0x0F94     /* SB Interrupt Mask */
+#define  SSB_INTVEC_PCI         0x00000001 /* Enable interrupts for PCI */
+#define  SSB_INTVEC_ENET0       0x00000002 /* Enable interrupts for enet 0 */
+#define  SSB_INTVEC_ILINE20     0x00000004 /* Enable interrupts for iline20 */
+#define  SSB_INTVEC_CODEC       0x00000008 /* Enable interrupts for v90 codec */
+#define  SSB_INTVEC_USB         0x00000010 /* Enable interrupts for usb */
+#define  SSB_INTVEC_EXTIF       0x00000020 /* Enable interrupts for external i/f */
+#define  SSB_INTVEC_ENET1       0x00000040 /* Enable interrupts for enet 1 */
+#define SSB_TMSLOW              0x0F98     /* SB Target State Low */
+#define  SSB_TMSLOW_RESET       0x00000001 /* Reset */
+#define  SSB_TMSLOW_REJECT      0x00000002 /* Reject */
+#define  SSB_TMSLOW_CLOCK       0x00010000 /* Clock Enable */
+#define  SSB_TMSLOW_FGC         0x00020000 /* Force Gated Clocks On */
+#define  SSB_TMSLOW_PE          0x40000000 /* Power Management Enable */
+#define  SSB_TMSLOW_BE          0x80000000 /* BIST Enable */
+#define SSB_TMSHIGH             0x0F9C     /* SB Target State High */
+#define  SSB_TMSHIGH_SERR       0x00000001 /* S-error */
+#define  SSB_TMSHIGH_INT        0x00000002 /* Interrupt */
+#define  SSB_TMSHIGH_BUSY       0x00000004 /* Busy */
+#define  SSB_TMSHIGH_TO         0x00000020 /* Timeout. Backplane rev >= 2.3 only */
+#define  SSB_TMSHIGH_COREFL     0x1FFF0000 /* Core specific flags */
+#define  SSB_TMSHIGH_COREFL_SHIFT       16
+#define  SSB_TMSHIGH_DMA64      0x10000000 /* 64bit DMA supported */
+#define  SSB_TMSHIGH_GCR        0x20000000 /* Gated Clock Request */
+#define  SSB_TMSHIGH_BISTF      0x40000000 /* BIST Failed */
+#define  SSB_TMSHIGH_BISTD      0x80000000 /* BIST Done */
+#define SSB_BWA0                0x0FA0
+#define SSB_IMCFGLO             0x0FA8
+#define  SSB_IMCFGLO_SERTO      0x00000007 /* Service timeout */
+#define  SSB_IMCFGLO_REQTO      0x00000070 /* Request timeout */
+#define  SSB_IMCFGLO_REQTO_SHIFT        4
+#define  SSB_IMCFGLO_CONNID     0x00FF0000 /* Connection ID */
+#define  SSB_IMCFGLO_CONNID_SHIFT       16
+#define SSB_IMCFGHI             0x0FAC
+#define SSB_BCONFIG             0x0FC0
+#define SSB_BSTATE              0x0FC8
+#define SSB_ACTCFG              0x0FD8
+#define SSB_FLAGST              0x0FE8
+#define SSB_IDLOW               0x0FF8
+#define  SSB_IDLOW_CFGSP        0x00000003 /* Config Space */
+#define  SSB_IDLOW_ADDRNGE      0x00000038 /* Address Ranges supported */
+#define  SSB_IDLOW_ADDRNGE_SHIFT        3
+#define  SSB_IDLOW_SYNC         0x00000040
+#define  SSB_IDLOW_INITIATOR    0x00000080
+#define  SSB_IDLOW_MIBL         0x00000F00 /* Minimum Backplane latency */
+#define  SSB_IDLOW_MIBL_SHIFT   8
+#define  SSB_IDLOW_MABL         0x0000F000 /* Maximum Backplane latency */
+#define  SSB_IDLOW_MABL_SHIFT   12
+#define  SSB_IDLOW_TIF          0x00010000 /* This Initiator is first */
+#define  SSB_IDLOW_CCW          0x000C0000 /* Cycle counter width */
+#define  SSB_IDLOW_CCW_SHIFT    18
+#define  SSB_IDLOW_TPT          0x00F00000 /* Target ports */
+#define  SSB_IDLOW_TPT_SHIFT    20
+#define  SSB_IDLOW_INITP        0x0F000000 /* Initiator ports */
+#define  SSB_IDLOW_INITP_SHIFT  24
+#define  SSB_IDLOW_SSBREV       0xF0000000 /* Sonics Backplane Revision code */
+#define  SSB_IDLOW_SSBREV_22    0x00000000 /* <= 2.2 */
+#define  SSB_IDLOW_SSBREV_23    0x10000000 /* 2.3 */
+#define SSB_IDHIGH              0x0FFC     /* SB Identification High */
+#define  SSB_IDHIGH_RCLO        0x0000000F /* Revision Code (low part) */
+#define  SSB_IDHIGH_CC          0x00008FF0 /* Core Code */
+#define  SSB_IDHIGH_CC_SHIFT    4
+#define  SSB_IDHIGH_RCHI        0x00007000 /* Revision Code (high part) */
+#define  SSB_IDHIGH_RCHI_SHIFT  8          /* yes, shift 8 is right */
+#define  SSB_IDHIGH_VC          0xFFFF0000 /* Vendor Code */
+#define  SSB_IDHIGH_VC_SHIFT    16
+
+/* SPROM shadow area. If not otherwise noted, fields are
+ * two bytes wide. Note that the SPROM can _only_ be read
+ * in two-byte quantinies.
+ */
+#define SSB_SPROMSIZE_WORDS             64
+#define SSB_SPROMSIZE_BYTES             (SSB_SPROMSIZE_WORDS * sizeof(u16))
+#define SSB_SPROM_BASE                  0x1000
+#define SSB_SPROM_REVISION              0x107E
+#define  SSB_SPROM_REVISION_REV         0x00FF  /* SPROM Revision number */
+#define  SSB_SPROM_REVISION_CRC         0xFF00  /* SPROM CRC8 value */
+#define  SSB_SPROM_REVISION_CRC_SHIFT   8
+/* SPROM Revision 1 */
+#define SSB_SPROM1_SPID                 0x1004  /* Subsystem Product ID for PCI */
+#define SSB_SPROM1_SVID                 0x1006  /* Subsystem Vendor ID for PCI */
+#define SSB_SPROM1_PID                  0x1008  /* Product ID for PCI */
+#define SSB_SPROM1_IL0MAC               0x1048  /* 6 bytes MAC address for 802.11b/g */
+#define SSB_SPROM1_ET0MAC               0x104E  /* 6 bytes MAC address for Ethernet */
+#define SSB_SPROM1_ET1MAC               0x1054  /* 6 bytes MAC address for 802.11a */
+#define SSB_SPROM1_ETHPHY               0x105A  /* Ethernet PHY settings */
+#define  SSB_SPROM1_ETHPHY_ET0A         0x001F  /* MII Address for enet0 */
+#define  SSB_SPROM1_ETHPHY_ET1A         0x03E0  /* MII Address for enet1 */
+#define  SSB_SPROM1_ETHPHY_ET1A_SHIFT   5
+#define  SSB_SPROM1_ETHPHY_ET0M         (1<<14) /* MDIO for enet0 */
+#define  SSB_SPROM1_ETHPHY_ET1M         (1<<15) /* MDIO for enet1 */
+#define SSB_SPROM1_BINF                 0x105C  /* Board info */
+#define  SSB_SPROM1_BINF_BREV           0x00FF  /* Board Revision */
+#define  SSB_SPROM1_BINF_CCODE          0x0F00  /* Country Code */
+#define  SSB_SPROM1_BINF_CCODE_SHIFT    8
+#define  SSB_SPROM1_BINF_ANTA           0x3000  /* Available A-PHY antennas */
+#define  SSB_SPROM1_BINF_ANTA_SHIFT     12
+#define  SSB_SPROM1_BINF_ANTBG          0xC000  /* Available B-PHY antennas */
+#define  SSB_SPROM1_BINF_ANTBG_SHIFT    14
+#define SSB_SPROM1_PA0B0                0x105E
+#define SSB_SPROM1_PA0B1                0x1060
+#define SSB_SPROM1_PA0B2                0x1062
+#define SSB_SPROM1_GPIOA                0x1064  /* General Purpose IO pins 0 and 1 */
+#define  SSB_SPROM1_GPIOA_P0            0x00FF  /* Pin 0 */
+#define  SSB_SPROM1_GPIOA_P1            0xFF00  /* Pin 1 */
+#define  SSB_SPROM1_GPIOA_P1_SHIFT      8
+#define SSB_SPROM1_GPIOB                0x1066  /* General Purpuse IO pins 2 and 3 */
+#define  SSB_SPROM1_GPIOB_P2            0x00FF  /* Pin 2 */
+#define  SSB_SPROM1_GPIOB_P3            0xFF00  /* Pin 3 */
+#define  SSB_SPROM1_GPIOB_P3_SHIFT      8
+#define SSB_SPROM1_MAXPWR               0x1068  /* Power Amplifier Max Power */
+#define  SSB_SPROM1_MAXPWR_A            0x00FF  /* A-PHY (in dBm Q5.2) */
+#define  SSB_SPROM1_MAXPWR_BG           0xFF00  /* B-PHY and G-PHY (in dBm Q5.2) */
+#define  SSB_SPROM1_MAXPWR_BG_SHIFT     8
+#define SSB_SPROM1_PA1B0                0x106A
+#define SSB_SPROM1_PA1B1                0x106C
+#define SSB_SPROM1_PA1B2                0x106E
+#define SSB_SPROM1_ITSSI                0x1070  /* Idle TSSI Target */
+#define  SSB_SPROM1_ITSSI_A             0x00FF  /* A-PHY */
+#define  SSB_SPROM1_ITSSI_BG            0xFF00  /* B-PHY and G-PHY */
+#define  SSB_SPROM1_ITSSI_BG_SHIFT      8
+#define SSB_SPROM1_BFLLO                0x1072  /* Boardflags (low 16 bits) */
+#define SSB_SPROM1_AGAIN                0x1074  /* Antenna Gain (in dBm Q5.2) */
+#define  SSB_SPROM1_AGAIN_A             0x00FF  /* A-PHY */
+#define  SSB_SPROM1_AGAIN_BG            0xFF00  /* B-PHY and G-PHY */
+#define  SSB_SPROM1_AGAIN_BG_SHIFT      8
+#define SSB_SPROM1_OEM                  0x1076  /* 8 bytes OEM string (rev 1 only) */
+/* SPROM Revision 2 (inherits from rev 1) */
+#define SSB_SPROM2_BFLHI                0x1038  /* Boardflags (high 16 bits) */
+#define SSB_SPROM2_MAXP_A               0x103A  /* A-PHY Max Power */
+#define  SSB_SPROM2_MAXP_A_HI           0x00FF  /* Max Power High */
+#define  SSB_SPROM2_MAXP_A_LO           0xFF00  /* Max Power Low */
+#define  SSB_SPROM2_MAXP_A_LO_SHIFT     8
+#define SSB_SPROM2_PA1LOB0              0x103C  /* A-PHY PowerAmplifier Low Settings */
+#define SSB_SPROM2_PA1LOB1              0x103E  /* A-PHY PowerAmplifier Low Settings */
+#define SSB_SPROM2_PA1LOB2              0x1040  /* A-PHY PowerAmplifier Low Settings */
+#define SSB_SPROM2_PA1HIB0              0x1042  /* A-PHY PowerAmplifier High Settings */
+#define SSB_SPROM2_PA1HIB1              0x1044  /* A-PHY PowerAmplifier High Settings */
+#define SSB_SPROM2_PA1HIB2              0x1046  /* A-PHY PowerAmplifier High Settings */
+#define SSB_SPROM2_OPO                  0x1078  /* OFDM Power Offset from CCK Level */
+#define  SSB_SPROM2_OPO_VALUE           0x00FF
+#define  SSB_SPROM2_OPO_UNUSED          0xFF00
+#define SSB_SPROM2_CCODE                0x107C  /* Two char Country Code */
+/* SPROM Revision 3 (inherits from rev 2) */
+#define SSB_SPROM3_OFDMAPO              0x102C  /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
+#define SSB_SPROM3_OFDMALPO             0x1030  /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
+#define SSB_SPROM3_OFDMAHPO             0x1034  /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
+#define SSB_SPROM3_GPIOLDC              0x1042  /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
+#define  SSB_SPROM3_GPIOLDC_OFF         0x0000FF00      /* Off Count */
+#define  SSB_SPROM3_GPIOLDC_OFF_SHIFT   8
+#define  SSB_SPROM3_GPIOLDC_ON          0x00FF0000      /* On Count */
+#define  SSB_SPROM3_GPIOLDC_ON_SHIFT    16
+#define SSB_SPROM3_CCKPO                0x1078  /* CCK Power Offset */
+#define  SSB_SPROM3_CCKPO_1M            0x000F  /* 1M Rate PO */
+#define  SSB_SPROM3_CCKPO_2M            0x00F0  /* 2M Rate PO */
+#define  SSB_SPROM3_CCKPO_2M_SHIFT      4
+#define  SSB_SPROM3_CCKPO_55M           0x0F00  /* 5.5M Rate PO */
+#define  SSB_SPROM3_CCKPO_55M_SHIFT     8
+#define  SSB_SPROM3_CCKPO_11M           0xF000  /* 11M Rate PO */
+#define  SSB_SPROM3_CCKPO_11M_SHIFT     12
+#define  SSB_SPROM3_OFDMGPO             0x107A  /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
+
+/* Values for SSB_SPROM1_BINF_CCODE */
+enum {
+        SSB_SPROM1CCODE_WORLD = 0,
+        SSB_SPROM1CCODE_THAILAND,
+        SSB_SPROM1CCODE_ISRAEL,
+        SSB_SPROM1CCODE_JORDAN,
+        SSB_SPROM1CCODE_CHINA,
+        SSB_SPROM1CCODE_JAPAN,
+        SSB_SPROM1CCODE_USA_CANADA_ANZ,
+        SSB_SPROM1CCODE_EUROPE,
+        SSB_SPROM1CCODE_USA_LOW,
+        SSB_SPROM1CCODE_JAPAN_HIGH,
+        SSB_SPROM1CCODE_ALL,
+        SSB_SPROM1CCODE_NONE,
+};
+
+
+#endif /* __KERNEL__ */
+#endif /* LINUX_SSB_REGS_H_ */